/** ****************************************************************************** * @file fm33a0xxev_spi.h * @author FM33A0XXEV Application Team * @version V1.0.0 * @date 16-April-2020 * @brief This file contains all the functions prototypes for the SPI firmware library. ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __FM33A0XXEV_SPI_H #define __FM33A0XXEV_SPI_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "FM33A0XXEV.h" //------------------------------------------------------------------------------ #define SPIx_CR1_IOSWAP_Pos 11 /* MOSIºÍMISOÒý½Å½»»» (IO swapping) 0£ºÄ¬ÈÏÒý½Å˳Ðò 1£º½»»»Òý½Å˳Ðò */ #define SPIx_CR1_IOSWAP_Msk (0x1U << SPIx_CR1_IOSWAP_Pos) #define SPIx_CR1_IOSWAP_DEFAULT (0x0U << SPIx_CR1_IOSWAP_Pos) /* ĬÈÏÒý½Å˳Ðò */ #define SPIx_CR1_IOSWAP_EXCHANGE (0x1U << SPIx_CR1_IOSWAP_Pos) /* ½»»»Òý½Å˳Ðò */ #define SPIx_CR1_MSPA_Pos 10 /* Master Sampling Position Adjustment£¬Master¶ÔMISOÐźŵIJÉÑùλÖõ÷Õû£¬ÓÃÓÚ¸ßËÙͨÐÅʱ²¹³¥PCB×ßÏßÑÓ³Ù 1£º²ÉÑùµãÑÓ³Ù°ë¸öSCKÖÜÆÚ 0£º²»µ÷Õû */ #define SPIx_CR1_MSPA_Msk (0x1U << SPIx_CR1_MSPA_Pos) #define SPIx_CR1_MSPA_DELAY (0x1U << SPIx_CR1_MSPA_Pos) /* ²ÉÑùµãÑÓ³Ù°ë¸öSCKÖÜÆÚ */ #define SPIx_CR1_MSPA_NORMAL (0x0U << SPIx_CR1_MSPA_Pos) /* ²»µ÷Õû */ #define SPIx_CR1_SSPA_Pos 9 /* Slave Sending Position Adjustment£¬Slave MISO·¢ËÍλÖõ÷Õû 1£ºÌáÇ°°ë¸öSCKÖÜÆÚ·¢ËÍ 0£º²»µ÷Õû */ #define SPIx_CR1_SSPA_Msk (0x1U << SPIx_CR1_SSPA_Pos) #define SPIx_CR1_SSPA_EARLY (0x1U << SPIx_CR1_SSPA_Pos) /* ÌáÇ°°ë¸öSCKÖÜÆÚ·¢ËÍ */ #define SPIx_CR1_SSPA_NORMAL (0x0U << SPIx_CR1_SSPA_Pos) /* ²»µ÷Õû */ #define SPIx_CR1_MM_Pos 8 /* Master/SlaveģʽѡÔñ¡£(Master Mode) 1£ºMasterģʽ 0£ºSlaveģʽ */ #define SPIx_CR1_MM_Msk (0x1U << SPIx_CR1_MM_Pos) #define SPIx_CR1_MM_MASTER (0x1U << SPIx_CR1_MM_Pos) #define SPIx_CR1_MM_SLAVE (0x0U << SPIx_CR1_MM_Pos) #define SPIx_CR1_WAIT_Pos 6 /* MasterģʽÏ£¬Ã¿·¢ËÍÍêÒ»Ö¡ºó¼ÓÈëÖÁÉÙ(1+WAIT)¸öSCK cycleµÈ´ýʱ¼ä£¬ÔÙ´«ÊäÏÂÒ»Ö¡µÄÊý¾Ý¡£Èç¹ûSSNÓÉÓ²¼þ¿ØÖÆ£¬²¢ÇÒSSNM=1£¬ÔòÓ²¼þ»á×Ô¶¯À­¸ßSSN¡£ */ #define SPIx_CR1_WAIT_Msk (0x3U << SPIx_CR1_WAIT_Pos) #define SPIx_CR1_WAIT_1WAIT (0x0U << SPIx_CR1_WAIT_Pos) #define SPIx_CR1_WAIT_2WAIT (0x1U << SPIx_CR1_WAIT_Pos) #define SPIx_CR1_WAIT_3WAIT (0x2U << SPIx_CR1_WAIT_Pos) #define SPIx_CR1_WAIT_4WAIT (0x3U << SPIx_CR1_WAIT_Pos) #define SPIx_CR1_BAUD_Pos 3 /* Masterģʽ²¨ÌØÂÊÅäÖÃλ: (Baud rate) 000£º fAPBCLK/2 001£º fAPBCLK/4 010£º fAPBCLK/8 011£º fAPBCLK/16 100£º fAPBCLK/32 101£º fAPBCLK/64 110£º fAPBCLK/128 111£º fAPBCLK/256 µ±Í¨ÐÅÕýÔÚ½øÐеÄʱºò£¬²»ÄÜÐÞ¸ÄÕâЩλ¡£ */ #define SPIx_CR1_BAUD_Msk (0x7U << SPIx_CR1_BAUD_Pos) #define SPIx_CR1_BAUD_DIV2 (0x0U << SPIx_CR1_BAUD_Pos) #define SPIx_CR1_BAUD_DIV4 (0x1U << SPIx_CR1_BAUD_Pos) #define SPIx_CR1_BAUD_DIV8 (0x2U << SPIx_CR1_BAUD_Pos) #define SPIx_CR1_BAUD_DIV16 (0x3U << SPIx_CR1_BAUD_Pos) #define SPIx_CR1_BAUD_DIV32 (0x4U << SPIx_CR1_BAUD_Pos) #define SPIx_CR1_BAUD_DIV64 (0x5U << SPIx_CR1_BAUD_Pos) #define SPIx_CR1_BAUD_DIV128 (0x6U << SPIx_CR1_BAUD_Pos) #define SPIx_CR1_BAUD_DIV256 (0x7U << SPIx_CR1_BAUD_Pos) #define SPIx_CR1_LSBF_Pos 2 /* Ö¡¸ñʽ (LSB First) 0£ºÏÈ·¢ËÍMSB 1£ºÏÈ·¢ËÍLSB ×¢£ºµ±Í¨ÐÅÔÚ½øÐÐʱ²»Äܸıä¸ÃλµÄÖµ¡£ */ #define SPIx_CR1_LSBF_Msk (0x1U << SPIx_CR1_LSBF_Pos) #define SPIx_CR1_LSBF_MSB (0x0U << SPIx_CR1_LSBF_Pos) #define SPIx_CR1_LSBF_LSB (0x1U << SPIx_CR1_LSBF_Pos) #define SPIx_CR1_CPHOL_Pos 1 #define SPIx_CR1_CPHOL_Msk (0x1U << SPIx_CR1_CPHOL_Pos) #define SPIx_CR1_CPHOL_LOW (0x0U << SPIx_CR1_CPHOL_Pos) #define SPIx_CR1_CPHOL_HIGH (0x1U << SPIx_CR1_CPHOL_Pos) #define SPIx_CR1_CPHA_Pos 0 /* ʱÖÓÏàλѡÔñ (Clock Phase) 1£ºµÚ¶þ¸öʱÖÓ±ßÑØÊǵÚÒ»¸ö²¶×½±ßÑØ 0£ºµÚÒ»¸öʱÖÓ±ßÑØÊǵÚÒ»¸ö²¶×½±ßÑØ ×¢£ºµ±Í¨ÐÅÔÚ½øÐÐʱ²»Äܸıä¸ÃλµÄÖµ¡£ */ #define SPIx_CR1_CPHA_Msk (0x1U << SPIx_CR1_CPHA_Pos) #define SPIx_CR1_CPHA_1CLOCK (0x0U << SPIx_CR1_CPHA_Pos) #define SPIx_CR1_CPHA_2CLOCK (0x1U << SPIx_CR1_CPHA_Pos) #define SPIx_CR2_DUMMY_EN_Pos 15 /* 4Ïß°ëË«¹¤Ð­ÒéÏÂÊÇ·ñÔÚ¶Á²Ù×÷ÖвåÈëdummy cycle (Dummy cycle Enable) 0£º²»²åÈëdummy cycle 1£ºÔÚ¶ÁÃüÁîÖ®ºó²åÈëÒ»¸ödummy cycle */ #define SPIx_CR2_DUMMY_EN_Msk (0x1U << SPIx_CR2_DUMMY_EN_Pos) /* ²»²åÈëdummy cycle */ /* ÔÚ¶ÁÃüÁîÖ®ºó²åÈëÒ»¸ödummy cycle */ #define SPIx_CR2_RXO_Pos 11 /* RXONLY¿ØÖÆ룬´Ë¼Ä´æÆ÷ÖÃλʱ£¬SPI¿ÉÒÔÁ¬Ðø½ÓÊÕ£¬ÎÞÐèÈí¼þдTXBUF (Receive Only mode) 1£ºÆô¶¯MasterµÄµ¥½ÓÊÕģʽ 0£º¹Ø±Õµ¥½ÓÊÕģʽ£¨ÊÕ·¢È«Ë«¹¤£© */ #define SPIx_CR2_RXO_Msk (0x1U << SPIx_CR2_RXO_Pos) /* Æô¶¯MasterµÄµ¥½ÓÊÕģʽ */ /* ¹Ø±Õµ¥½ÓÊÕģʽ£¨ÊÕ·¢È«Ë«¹¤£© */ #define SPIx_CR2_DLEN_Pos 9 /* ͨÐÅÊý¾Ý×Ö³¤ÅäÖà (Data Length) 00£º8bit 01£º16bit 10£º24bit 11£º32bit */ #define SPIx_CR2_DLEN_Msk (0x3U << SPIx_CR2_DLEN_Pos) #define SPIx_CR2_DLEN_8BIT (0x0U << SPIx_CR2_DLEN_Pos) /* 8bit */ #define SPIx_CR2_DLEN_16BIT (0x1U << SPIx_CR2_DLEN_Pos) /* 16bit */ #define SPIx_CR2_DLEN_24BIT (0x2U << SPIx_CR2_DLEN_Pos) /* 24bit */ #define SPIx_CR2_DLEN_32BIT (0x3U << SPIx_CR2_DLEN_Pos) /* 32bit */ #define SPIx_CR2_HALFDUPLEX_Pos 8 /* ͨÐÅģʽѡÔñ (Half-Duplex mode) 0£º±ê×¼SPIģʽ£¬4ÏßÈ«Ë«¹¤ 1£ºDCNģʽ£¬4Ïß°ëË«¹¤ */ #define SPIx_CR2_HALFDUPLEX_Msk (0x1U << SPIx_CR2_HALFDUPLEX_Pos) #define SPIx_CR2_HALFDUPLEX_SPI (0x0U << SPIx_CR2_HALFDUPLEX_Pos) /* ±ê×¼SPIģʽ£¬4ÏßÈ«Ë«¹¤ */ #define SPIx_CR2_HALFDUPLEX_DCN (0x1U << SPIx_CR2_HALFDUPLEX_Pos) /* DCNģʽ£¬4Ïß°ëË«¹¤ */ #define SPIx_CR2_HD_RW_Pos 7 /* °ëË«¹¤Ä£Ê½ÏÂÖ÷»ú¶Áд²Ù×÷ÅäÖà (Read/Write config for Half-Duplex mode) 0£º4Ïß°ëË«¹¤Ð­ÒéÏÂÖ÷»úдÈë´Ó»ú 1£º4Ïß°ëË«¹¤Ð­ÒéÏÂÖ÷»ú¶ÁÈ¡´Ó»ú */ #define SPIx_CR2_HD_RW_Msk (0x1U << SPIx_CR2_HD_RW_Pos) #define SPIx_CR2_HD_RW_WRITE (0x0U << SPIx_CR2_HD_RW_Pos) /* 4Ïß°ëË«¹¤Ð­ÒéÏÂÖ÷»úдÈë´Ó»ú */ #define SPIx_CR2_HD_RW_READ (0x1U << SPIx_CR2_HD_RW_Pos) /* 4Ïß°ëË«¹¤Ð­ÒéÏÂÖ÷»ú¶ÁÈ¡´Ó»ú */ #define SPIx_CR2_CMD8b_Pos 6 /* °ëË«¹¤Ä£Ê½Ï¶¨ÒåcommandÖ¡³¤¶È (Command 8 bits) 1£ºcommandÖ¡¹Ì¶¨Îª8bit 0£ºcommandÖ¡³¤¶ÈÓÉDLEN¶¨Òå */ #define SPIx_CR2_CMD8b_Msk (0x1U << SPIx_CR2_CMD8b_Pos) #define SPIx_CR2_CMD8b_8BIT (0x1U << SPIx_CR2_CMD8b_Pos) /* commandÖ¡¹Ì¶¨Îª8bit */ #define SPIx_CR2_CMD8b_DLEN (0x0U << SPIx_CR2_CMD8b_Pos) /* commandÖ¡³¤¶ÈÓÉDLEN¶¨Òå */ #define SPIx_CR2_SSNM_Pos 5 /* MasterģʽÏÂSSN¿ØÖÆģʽѡÔñ (SSN mode) 1£ºÃ¿·¢ËÍÍêÒ»Ö¡ºóMasterÀ­¸ßSSN£¬Î¬³Ö¸ßµçƽʱ¼äÓÉWAIT¼Ä´æÆ÷¿ØÖÆ 0£ºÃ¿·¢ËÍÍêÒ»Ö¡ºóMaster±£³ÖSSNΪµÍ */ #define SPIx_CR2_SSNM_Msk (0x1U << SPIx_CR2_SSNM_Pos) #define SPIx_CR2_SSNM_HIGH (0x1U << SPIx_CR2_SSNM_Pos) /* ÿ·¢ËÍÍêÒ»Ö¡ºóMasterÀ­¸ßSSN£¬Î¬³Ö¸ßµçƽʱ¼äÓÉWAIT¼Ä´æÆ÷¿ØÖÆ */ #define SPIx_CR2_SSNM_LOW (0x0U << SPIx_CR2_SSNM_Pos) /* ÿ·¢ËÍÍêÒ»Ö¡ºóMaster±£³ÖSSNΪµÍ */ #define SPIx_CR2_TXO_AC_Pos 4 /* TXONLYÓ²¼þ×Ô¶¯Çå¿ÕµÄʹÄÜ (TXONLY auto-clear enable) 1£ºTXONLYÓ²¼þ×Ô¶¯ÇåÁãÓÐЧ£¬Èí¼þʹÄÜTXOºó£¬µÈ´ý·¢ËÍÍê±Ïºó£¬Ó²¼þÇåÁã 0£º¹Ø±ÕTXONLYÓ²¼þ×Ô¶¯ÇåÁã */ #define SPIx_CR2_TXO_AC_Msk (0x1U << SPIx_CR2_TXO_AC_Pos) #define SPIx_CR2_TXO_Pos 3 /* TXONLY¿ØÖÆλ (Transmit Only mode enable) 1£ºÆô¶¯MasterµÄµ¥·¢ËÍģʽ 0£º¹Ø±Õµ¥·¢ËÍģʽ£¨ÊÕ·¢È«Ë«¹¤£© */ #define SPIx_CR2_TXO_Msk (0x1U << SPIx_CR2_TXO_Pos) /* Æô¶¯MasterµÄµ¥·¢ËÍģʽ */ /* ¹Ø±Õµ¥·¢ËÍģʽ£¨ÊÕ·¢È«Ë«¹¤£© */ #define SPIx_CR2_SSN_Pos 2 /* MasterģʽÏ£¬Èç¹ûSSNSENΪ1£¬Èí¼þ¿ÉÒÔͨ¹ý´Ëλ¿ØÖÆSSNÊä³öµçƽ 1£ºSSNÊä³ö¸ßµçƽ 0£ºSSNÊä³öµÍµçƽ */ #define SPIx_CR2_SSN_Msk (0x1U << SPIx_CR2_SSN_Pos) #define SPIx_CR2_SSN_LOW (0x0U << SPIx_CR2_SSN_Pos) /* SSNÊä³ö¸ßµçƽ */ #define SPIx_CR2_SSN_HIGH (0x1U << SPIx_CR2_SSN_Pos) /* SSNÊä³öµÍµçƽ */ #define SPIx_CR2_SSNSEN_Pos 1 /* MasterģʽÏ£¬Èí¼þ¿ØÖÆSSNʹÄÜ (SSN Software Enable) 1£ºMasterģʽÏÂSSNÊä³öÓÉÈí¼þ¿ØÖÆ 0£ºMasterģʽÏÂSSNÊä³öÓÉÓ²¼þ×Ô¶¯¿ØÖÆ */ #define SPIx_CR2_SSNSEN_Msk (0x1U << SPIx_CR2_SSNSEN_Pos) /* MasterģʽÏÂSSNÊä³öÓÉÈí¼þ¿ØÖÆ */ /* MasterģʽÏÂSSNÊä³öÓÉÓ²¼þ×Ô¶¯¿ØÖÆ */ #define SPIx_CR2_SPIEN_Pos 0 /* SPIʹÄÜ (SPI enable) 1£ºÊ¹ÄÜSPI 0£º¹Ø±ÕSPI£¬Çå¿Õ·¢ËͽÓÊÕ»º´æ */ #define SPIx_CR2_SPIEN_Msk (0x1U << SPIx_CR2_SPIEN_Pos) #define SPIx_CR3_TXBFC_Pos 3 /* Transmit Buffer Clear£¬Èí¼þд1Çå³ý·¢ËÍ»º´æ£¬Ð´0ÎÞЧ */ #define SPIx_CR3_TXBFC_Msk (0x1U << SPIx_CR3_TXBFC_Pos) #define SPIx_CR3_RXBFC_Pos 2 /* Receive Buffer Clear£¬Èí¼þд1Çå³ý·¢ËÍ»º´æ£¬Ð´0ÎÞЧ */ #define SPIx_CR3_RXBFC_Msk (0x1U << SPIx_CR3_RXBFC_Pos) #define SPIx_CR3_MERRC_Pos 1 /* Master Error Clear£¬Èí¼þд1Çå³ýHSPISTA.MERR¼Ä´æÆ÷ */ #define SPIx_CR3_MERRC_Msk (0x1U << SPIx_CR3_MERRC_Pos) #define SPIx_CR3_SERRC_Pos 0 /* Slave Error Clear£¬Èí¼þд1Çå³ýHSPISTA.SERR¼Ä´æÆ÷ */ #define SPIx_CR3_SERRC_Msk (0x1U << SPIx_CR3_SERRC_Pos) #define SPIx_IER_ERRIE_Pos 2 /* SPI´íÎóÖжÏʹÄÜ (Error Interrupt Enable) */ #define SPIx_IER_ERRIE_Msk (0x1U << SPIx_IER_ERRIE_Pos) #define SPIx_IER_TXIE_Pos 1 /* ·¢ËÍÍê³ÉÖжÏʹÄÜ (Transmit Interrupt Enable) */ #define SPIx_IER_TXIE_Msk (0x1U << SPIx_IER_TXIE_Pos) #define SPIx_IER_RXIE_Pos 0 /* ½ÓÊÕÍê³ÉÖжÏʹÄÜ (Receive Interrupt Enable) */ #define SPIx_IER_RXIE_Msk (0x1U << SPIx_IER_RXIE_Pos) #define SPIx_ISR_DCN_TX_Pos 12 /* °ëË«¹¤Ä£Ê½Ï£¨HALFDUPLEX=1£©£¬ÅäÖÃÔÚÿ¸öÊý¾ÝÖ¡µÄ×îºóbit·¢Ë͵ÄDCNÐźŵçƽ (Data/Command transmit config) 0£ºDCN=0£¬±íʾÃüÁîÖ¡ 1£ºDCN=1£¬±íʾÊý¾ÝÖ¡ Èí¼þÓ¦ÔÚ·¢ËÍÇ°ÉèÖÃDCN_TX¼Ä´æÆ÷£¬Èç¹ûDCN_TX=0£¬Ó²¼þÔÚÍê³ÉÒ»Ö¡·¢Ëͺó£¬×Ô¶¯½«DCN_TXÖÃ1£¬¼´Ä¬ÈÏÖ»»á·¢ËÍÒ»¸öÃüÁîÖ¡£¬ºóÐø¶¼ÊÇÊý¾ÝÖ¡¡£ */ #define SPIx_ISR_DCN_TX_Msk (0x1U << SPIx_ISR_DCN_TX_Pos) #define SPIx_ISR_DCN_TX_COMMAND (0x0U << SPIx_ISR_DCN_TX_Pos) /* DCN=0£¬±íʾÃüÁîÖ¡ */ #define SPIx_ISR_DCN_TX_DATA (0x1U << SPIx_ISR_DCN_TX_Pos) /* DCN=1£¬±íʾÊý¾ÝÖ¡ */ #define SPIx_ISR_RXCOL_Pos 10 /* ½ÓÊÕ»º´æÒç³ö£¬Èí¼þд1ÇåÁã (Receive Collision flag,write 1 to flag) */ #define SPIx_ISR_RXCOL_Msk (0x1U << SPIx_ISR_RXCOL_Pos) #define SPIx_ISR_TXCOL_Pos 9 /* ·¢ËÍ»º´æÒç³ö£¬Èí¼þд1ÇåÁã (Transmit Collision flag,write 1 to clear) */ #define SPIx_ISR_TXCOL_Msk (0x1U << SPIx_ISR_TXCOL_Pos) #define SPIx_ISR_BUSY_Pos 8 /* SPI¿ÕÏбêÖ¾£¬Ö»¶Á (busy flag) 1£ºSPI´«Êä½øÐÐÖÐ 0£ºSPI´«Êä¿ÕÏÐ */ #define SPIx_ISR_BUSY_Msk (0x1U << SPIx_ISR_BUSY_Pos) #define SPIx_ISR_MERR_Pos 6 /* Master Error±êÖ¾(Master Error flag) µ±MasterÏ´«ÊäδÂú8λSSN¾Í±»À­¸ßʱ£¬MERRÖÃλ */ #define SPIx_ISR_MERR_Msk (0x1U << SPIx_ISR_MERR_Pos) #define SPIx_ISR_SERR_Pos 5 /* Slave Error±êÖ¾(Slave Error flag) µ±SlaveÏ´«ÊäδÂú8λSSN¾Í±»À­¸ßʱ£¬SERRÖÃλ */ #define SPIx_ISR_SERR_Msk (0x1U << SPIx_ISR_SERR_Pos) #define SPIx_ISR_TXBE_Pos 1 /* TX Buffer Empty±ê־λ(TX Buffer Empty flag) 1£º·¢ËÍ»º´æ¿Õ£¬Èí¼þдTXBUFÇåÁã 0£º·¢ËÍ»º´æÂú */ #define SPIx_ISR_TXBE_Msk (0x1U << SPIx_ISR_TXBE_Pos) #define SPIx_ISR_RXBF_Pos 0 /* RX Buffer Full±ê־λ(RX Buffer Full flag) 1£º½ÓÊÕ»º´æÂú£¬Èí¼þ¶ÁRXBUFÇåÁã 0£º½ÓÊÕ»º´æ¿Õ */ #define SPIx_ISR_RXBF_Msk (0x1U << SPIx_ISR_RXBF_Pos) #define SPIx_TXBUF_TXBUF_Pos 0 /* SPI·¢ËÍ»º´æ (Transmit Buffer) */ #define SPIx_TXBUF_TXBUF_Msk (0xffffffffU << SPIx_TXBUF_TXBUF_Pos) #define SPIx_RXBUF_RXBUF_Pos 0 /* SPI½ÓÊÕ»º´æ (Receive Buffer) */ #define SPIx_RXBUF_RXBUF_Msk (0xffffffffU << SPIx_RXBUF_RXBUF_Pos) //Macro_End /* Exported functions --------------------------------------------------------*/ extern void SPIx_Deinit(SPI_Type* SPIx); /* MOSIºÍMISOÒý½Å½»»» (IO swapping) 0£ºÄ¬ÈÏÒý½Å˳Ðò 1£º½»»»Òý½Å˳Ðò Ïà¹Øº¯Êý */ extern void SPIx_CR1_IOSWAP_Set(SPI_Type* SPIx, uint32_t SetValue); extern uint32_t SPIx_CR1_IOSWAP_Get(SPI_Type* SPIx); /* Master Sampling Position Adjustment£¬Master¶ÔMISOÐźŵIJÉÑùλÖõ÷Õû£¬ÓÃÓÚ¸ßËÙͨÐÅʱ²¹³¥PCB×ßÏßÑÓ³Ù 1£º²ÉÑùµãÑÓ³Ù°ë¸öSCKÖÜÆÚ 0£º²»µ÷Õû Ïà¹Øº¯Êý */ extern void SPIx_CR1_MSPA_Set(SPI_Type* SPIx, uint32_t SetValue); extern uint32_t SPIx_CR1_MSPA_Get(SPI_Type* SPIx); /* Slave Sending Position Adjustment£¬Slave MISO·¢ËÍλÖõ÷Õû 1£ºÌáÇ°°ë¸öSCKÖÜÆÚ·¢ËÍ 0£º²»µ÷Õû Ïà¹Øº¯Êý */ extern void SPIx_CR1_SSPA_Set(SPI_Type* SPIx, uint32_t SetValue); extern uint32_t SPIx_CR1_SSPA_Get(SPI_Type* SPIx); /* Master/SlaveģʽѡÔñ¡£(Master Mode) 1£ºMasterģʽ 0£ºSlaveģʽ Ïà¹Øº¯Êý */ extern void SPIx_CR1_MM_Set(SPI_Type* SPIx, uint32_t SetValue); extern uint32_t SPIx_CR1_MM_Get(SPI_Type* SPIx); /* MasterģʽÏ£¬Ã¿·¢ËÍÍêÒ»Ö¡ºó¼ÓÈëÖÁÉÙ(1+WAIT)¸öSCK cycleµÈ´ýʱ¼ä£¬ÔÙ´«ÊäÏÂÒ»Ö¡µÄÊý¾Ý¡£Èç¹ûSSNÓÉÓ²¼þ¿ØÖÆ£¬²¢ÇÒSSNM=1£¬ÔòÓ²¼þ»á×Ô¶¯À­¸ßSSN¡£ Ïà¹Øº¯Êý */ extern void SPIx_CR1_WAIT_Set(SPI_Type* SPIx, uint32_t SetValue); extern uint32_t SPIx_CR1_WAIT_Get(SPI_Type* SPIx); /* Masterģʽ²¨ÌØÂÊÅäÖÃλ: (Baud rate) 000£º fAPBCLK/2 001£º fAPBCLK/4 010£º fAPBCLK/8 011£º fAPBCLK/16 100£º fAPBCLK/32 101£º fAPBCLK/64 110£º fAPBCLK/128 111£º fAPBCLK/256 µ±Í¨ÐÅÕýÔÚ½øÐеÄʱºò£¬²»ÄÜÐÞ¸ÄÕâЩλ¡£ Ïà¹Øº¯Êý */ extern void SPIx_CR1_BAUD_Set(SPI_Type* SPIx, uint32_t SetValue); extern uint32_t SPIx_CR1_BAUD_Get(SPI_Type* SPIx); /* Ö¡¸ñʽ (LSB First) 0£ºÏÈ·¢ËÍMSB 1£ºÏÈ·¢ËÍLSB ×¢£ºµ±Í¨ÐÅÔÚ½øÐÐʱ²»Äܸıä¸ÃλµÄÖµ¡£ Ïà¹Øº¯Êý */ extern void SPIx_CR1_LSBF_Set(SPI_Type* SPIx, uint32_t SetValue); extern uint32_t SPIx_CR1_LSBF_Get(SPI_Type* SPIx); extern void SPIx_CR1_CPHOL_Set(SPI_Type* SPIx, uint32_t SetValue); extern uint32_t SPIx_CR1_CPHOL_Get(SPI_Type* SPIx); /* ʱÖÓÏàλѡÔñ (Clock Phase) 1£ºµÚ¶þ¸öʱÖÓ±ßÑØÊǵÚÒ»¸ö²¶×½±ßÑØ 0£ºµÚÒ»¸öʱÖÓ±ßÑØÊǵÚÒ»¸ö²¶×½±ßÑØ ×¢£ºµ±Í¨ÐÅÔÚ½øÐÐʱ²»Äܸıä¸ÃλµÄÖµ¡£ Ïà¹Øº¯Êý */ extern void SPIx_CR1_CPHA_Set(SPI_Type* SPIx, uint32_t SetValue); extern uint32_t SPIx_CR1_CPHA_Get(SPI_Type* SPIx); /* 4Ïß°ëË«¹¤Ð­ÒéÏÂÊÇ·ñÔÚ¶Á²Ù×÷ÖвåÈëdummy cycle (Dummy cycle Enable) 0£º²»²åÈëdummy cycle 1£ºÔÚ¶ÁÃüÁîÖ®ºó²åÈëÒ»¸ödummy cycle Ïà¹Øº¯Êý */ extern void SPIx_CR2_DUMMY_EN_Setable(SPI_Type* SPIx, FunState NewState); extern FunState SPIx_CR2_DUMMY_EN_Getable(SPI_Type* SPIx); /* RXONLY¿ØÖÆ룬´Ë¼Ä´æÆ÷ÖÃλʱ£¬SPI¿ÉÒÔÁ¬Ðø½ÓÊÕ£¬ÎÞÐèÈí¼þдTXBUF (Receive Only mode) 1£ºÆô¶¯MasterµÄµ¥½ÓÊÕģʽ 0£º¹Ø±Õµ¥½ÓÊÕģʽ£¨ÊÕ·¢È«Ë«¹¤£© Ïà¹Øº¯Êý */ extern void SPIx_CR2_RXO_Setable(SPI_Type* SPIx, FunState NewState); extern FunState SPIx_CR2_RXO_Getable(SPI_Type* SPIx); /* ͨÐÅÊý¾Ý×Ö³¤ÅäÖà (Data Length) 00£º8bit 01£º16bit 10£º24bit 11£º32bit Ïà¹Øº¯Êý */ extern void SPIx_CR2_DLEN_Set(SPI_Type* SPIx, uint32_t SetValue); extern uint32_t SPIx_CR2_DLEN_Get(SPI_Type* SPIx); /* ͨÐÅģʽѡÔñ (Half-Duplex mode) 0£º±ê×¼SPIģʽ£¬4ÏßÈ«Ë«¹¤ 1£ºDCNģʽ£¬4Ïß°ëË«¹¤ Ïà¹Øº¯Êý */ extern void SPIx_CR2_HALFDUPLEX_Set(SPI_Type* SPIx, uint32_t SetValue); extern uint32_t SPIx_CR2_HALFDUPLEX_Get(SPI_Type* SPIx); /* °ëË«¹¤Ä£Ê½ÏÂÖ÷»ú¶Áд²Ù×÷ÅäÖà (Read/Write config for Half-Duplex mode) 0£º4Ïß°ëË«¹¤Ð­ÒéÏÂÖ÷»úдÈë´Ó»ú 1£º4Ïß°ëË«¹¤Ð­ÒéÏÂÖ÷»ú¶ÁÈ¡´Ó»ú Ïà¹Øº¯Êý */ extern void SPIx_CR2_HD_RW_Set(SPI_Type* SPIx, uint32_t SetValue); extern uint32_t SPIx_CR2_HD_RW_Get(SPI_Type* SPIx); /* °ëË«¹¤Ä£Ê½Ï¶¨ÒåcommandÖ¡³¤¶È (Command 8 bits) 1£ºcommandÖ¡¹Ì¶¨Îª8bit 0£ºcommandÖ¡³¤¶ÈÓÉDLEN¶¨Òå Ïà¹Øº¯Êý */ extern void SPIx_CR2_CMD8b_Set(SPI_Type* SPIx, uint32_t SetValue); extern uint32_t SPIx_CR2_CMD8b_Get(SPI_Type* SPIx); /* MasterģʽÏÂSSN¿ØÖÆģʽѡÔñ (SSN mode) 1£ºÃ¿·¢ËÍÍêÒ»Ö¡ºóMasterÀ­¸ßSSN£¬Î¬³Ö¸ßµçƽʱ¼äÓÉWAIT¼Ä´æÆ÷¿ØÖÆ 0£ºÃ¿·¢ËÍÍêÒ»Ö¡ºóMaster±£³ÖSSNΪµÍ Ïà¹Øº¯Êý */ extern void SPIx_CR2_SSNM_Set(SPI_Type* SPIx, uint32_t SetValue); extern uint32_t SPIx_CR2_SSNM_Get(SPI_Type* SPIx); /* TXONLYÓ²¼þ×Ô¶¯Çå¿ÕµÄʹÄÜ (TXONLY auto-clear enable) 1£ºTXONLYÓ²¼þ×Ô¶¯ÇåÁãÓÐЧ£¬Èí¼þʹÄÜTXOºó£¬µÈ´ý·¢ËÍÍê±Ïºó£¬Ó²¼þÇåÁã 0£º¹Ø±ÕTXONLYÓ²¼þ×Ô¶¯ÇåÁã Ïà¹Øº¯Êý */ extern void SPIx_CR2_TXO_AC_Setable(SPI_Type* SPIx, FunState NewState); extern FunState SPIx_CR2_TXO_AC_Getable(SPI_Type* SPIx); /* TXONLY¿ØÖÆλ (Transmit Only mode enable) 1£ºÆô¶¯MasterµÄµ¥·¢ËÍģʽ 0£º¹Ø±Õµ¥·¢ËÍģʽ£¨ÊÕ·¢È«Ë«¹¤£© Ïà¹Øº¯Êý */ extern void SPIx_CR2_TXO_Setable(SPI_Type* SPIx, FunState NewState); extern FunState SPIx_CR2_TXO_Getable(SPI_Type* SPIx); /* MasterģʽÏ£¬Èç¹ûSSNSENΪ1£¬Èí¼þ¿ÉÒÔͨ¹ý´Ëλ¿ØÖÆSSNÊä³öµçƽ 1£ºSSNÊä³ö¸ßµçƽ 0£ºSSNÊä³öµÍµçƽ Ïà¹Øº¯Êý */ extern void SPIx_CR2_SSN_Set(SPI_Type* SPIx, uint32_t SetValue); extern uint32_t SPIx_CR2_SSN_Get(SPI_Type* SPIx); /* MasterģʽÏ£¬Èí¼þ¿ØÖÆSSNʹÄÜ (SSN Software Enable) 1£ºMasterģʽÏÂSSNÊä³öÓÉÈí¼þ¿ØÖÆ 0£ºMasterģʽÏÂSSNÊä³öÓÉÓ²¼þ×Ô¶¯¿ØÖÆ Ïà¹Øº¯Êý */ extern void SPIx_CR2_SSNSEN_Setable(SPI_Type* SPIx, FunState NewState); extern FunState SPIx_CR2_SSNSEN_Getable(SPI_Type* SPIx); /* SPIʹÄÜ (SPI enable) 1£ºÊ¹ÄÜSPI 0£º¹Ø±ÕSPI£¬Çå¿Õ·¢ËͽÓÊÕ»º´æ Ïà¹Øº¯Êý */ extern void SPIx_CR2_SPIEN_Setable(SPI_Type* SPIx, FunState NewState); extern FunState SPIx_CR2_SPIEN_Getable(SPI_Type* SPIx); /* Transmit Buffer Clear£¬Èí¼þд1Çå³ý·¢ËÍ»º´æ£¬Ð´0ÎÞЧ Ïà¹Øº¯Êý */ extern void SPIx_CR3_TXBFC_Clr(SPI_Type* SPIx); /* Receive Buffer Clear£¬Èí¼þд1Çå³ý·¢ËÍ»º´æ£¬Ð´0ÎÞЧ Ïà¹Øº¯Êý */ extern void SPIx_CR3_RXBFC_Clr(SPI_Type* SPIx); /* Master Error Clear£¬Èí¼þд1Çå³ýHSPISTA.MERR¼Ä´æÆ÷ Ïà¹Øº¯Êý */ extern void SPIx_CR3_MERRC_Clr(SPI_Type* SPIx); /* Slave Error Clear£¬Èí¼þд1Çå³ýHSPISTA.SERR¼Ä´æÆ÷ Ïà¹Øº¯Êý */ extern void SPIx_CR3_SERRC_Clr(SPI_Type* SPIx); /* SPI´íÎóÖжÏʹÄÜ (Error Interrupt Enable) Ïà¹Øº¯Êý */ extern void SPIx_IER_ERRIE_Setable(SPI_Type* SPIx, FunState NewState); extern FunState SPIx_IER_ERRIE_Getable(SPI_Type* SPIx); /* ·¢ËÍÍê³ÉÖжÏʹÄÜ (Transmit Interrupt Enable) Ïà¹Øº¯Êý */ extern void SPIx_IER_TXIE_Setable(SPI_Type* SPIx, FunState NewState); extern FunState SPIx_IER_TXIE_Getable(SPI_Type* SPIx); /* ½ÓÊÕÍê³ÉÖжÏʹÄÜ (Receive Interrupt Enable) Ïà¹Øº¯Êý */ extern void SPIx_IER_RXIE_Setable(SPI_Type* SPIx, FunState NewState); extern FunState SPIx_IER_RXIE_Getable(SPI_Type* SPIx); /* °ëË«¹¤Ä£Ê½Ï£¨HALFDUPLEX=1£©£¬ÅäÖÃÔÚÿ¸öÊý¾ÝÖ¡µÄ×îºóbit·¢Ë͵ÄDCNÐźŵçƽ (Data/Command transmit config) 0£ºDCN=0£¬±íʾÃüÁîÖ¡ 1£ºDCN=1£¬±íʾÊý¾ÝÖ¡ Èí¼þÓ¦ÔÚ·¢ËÍÇ°ÉèÖÃDCN_TX¼Ä´æÆ÷£¬Èç¹ûDCN_TX=0£¬Ó²¼þÔÚÍê³ÉÒ»Ö¡·¢Ëͺó£¬×Ô¶¯½«DCN_TXÖÃ1£¬¼´Ä¬ÈÏÖ»»á·¢ËÍÒ»¸öÃüÁîÖ¡£¬ºóÐø¶¼ÊÇÊý¾ÝÖ¡¡£ Ïà¹Øº¯Êý */ extern void SPIx_ISR_DCN_TX_Set(SPI_Type* SPIx, uint32_t SetValue); extern uint32_t SPIx_ISR_DCN_TX_Get(SPI_Type* SPIx); /* ½ÓÊÕ»º´æÒç³ö£¬Èí¼þд1ÇåÁã (Receive Collision flag,write 1 to flag) Ïà¹Øº¯Êý */ extern void SPIx_ISR_RXCOL_Clr(SPI_Type* SPIx); extern FlagStatus SPIx_ISR_RXCOL_Chk(SPI_Type* SPIx); /* ·¢ËÍ»º´æÒç³ö£¬Èí¼þд1ÇåÁã (Transmit Collision flag,write 1 to clear) Ïà¹Øº¯Êý */ extern void SPIx_ISR_TXCOL_Clr(SPI_Type* SPIx); extern FlagStatus SPIx_ISR_TXCOL_Chk(SPI_Type* SPIx); /* SPI¿ÕÏбêÖ¾£¬Ö»¶Á (busy flag) 1£ºSPI´«Êä½øÐÐÖÐ 0£ºSPI´«Êä¿ÕÏÐ Ïà¹Øº¯Êý */ extern FlagStatus SPIx_ISR_BUSY_Chk(SPI_Type* SPIx); /* Master Error±êÖ¾(Master Error flag) µ±MasterÏ´«ÊäδÂú8λSSN¾Í±»À­¸ßʱ£¬MERRÖÃλ Ïà¹Øº¯Êý */ extern FlagStatus SPIx_ISR_MERR_Chk(SPI_Type* SPIx); /* Slave Error±êÖ¾(Slave Error flag) µ±SlaveÏ´«ÊäδÂú8λSSN¾Í±»À­¸ßʱ£¬SERRÖÃλ Ïà¹Øº¯Êý */ extern FlagStatus SPIx_ISR_SERR_Chk(SPI_Type* SPIx); /* TX Buffer Empty±ê־λ(TX Buffer Empty flag) 1£º·¢ËÍ»º´æ¿Õ£¬Èí¼þдTXBUFÇåÁã 0£º·¢ËÍ»º´æÂú Ïà¹Øº¯Êý */ extern FlagStatus SPIx_ISR_TXBE_Chk(SPI_Type* SPIx); /* RX Buffer Full±ê־λ(RX Buffer Full flag) 1£º½ÓÊÕ»º´æÂú£¬Èí¼þ¶ÁRXBUFÇåÁã 0£º½ÓÊÕ»º´æ¿Õ Ïà¹Øº¯Êý */ extern FlagStatus SPIx_ISR_RXBF_Chk(SPI_Type* SPIx); /* SPI·¢ËÍ»º´æ (Transmit Buffer) Ïà¹Øº¯Êý */ extern void SPIx_TXBUF_Write(SPI_Type* SPIx, uint32_t SetValue); /* SPI½ÓÊÕ»º´æ (Receive Buffer) Ïà¹Øº¯Êý */ extern uint32_t SPIx_RXBUF_Read(SPI_Type* SPIx); //Announce_End void SPIx_Deinit(SPI_Type* SPIx); void SPI_SSN_Set_Low(SPI_Type* SPIx); void SPI_SSN_Set_High(SPI_Type* SPIx); uint8_t SPI_RW_Byte(SPI_Type* SPIx, uint8_t data); #ifdef __cplusplus } #endif #endif /*__FM33A0XXEV_SPI_H */