/**
  ******************************************************************************
  * @file    fm33a0xxev_lpuart.h
  * @author  FM33A0XXEV Application Team
  * @version V1.0.0
  * @date    16-April-2020
  * @brief   This file contains all the functions prototypes for the LPUART firmware library.  
  ******************************************************************************
  */
  
/* Define to prevent recursive inclusion -------------------------------------*/

#ifndef __FM33A0XXEV_LPUART_H
#define __FM33A0XXEV_LPUART_H


#ifdef __cplusplus
 extern "C" {
#endif

/* Includes ------------------------------------------------------------------*/

#include "FM33A0XXEV.h" 
	 
#define LPUARTx_MCTL_FOR9600 (0x00000552<<16)
#define LPUARTx_MCTL_FOR4800 (0x00001EFB<<16)
#define LPUARTx_MCTL_FOR2400 (0x000016DB<<16)
#define LPUARTx_MCTL_FOR1200 (0x00000492<<16)
#define LPUARTx_MCTL_FOR600  (0x000016D6<<16)
#define LPUARTx_MCTL_FOR300  (0x00000842<<16)	 
	 
#define	LPUARTx_CSR_BUSY_Pos	24	/* LPUARTͨÐűêÖ¾£¬Ö»¶Á (Busy)
1£ºLPUARTÕýÔÚͨÐÅÖÐ
0£ºLPUART¿ÕÏÐ */
#define	LPUARTx_CSR_BUSY_Msk	(0x1U << LPUARTx_CSR_BUSY_Pos)

#define	LPUARTx_CSR_WKBYTECFG_Pos	19	/* Êý¾Ý½ÓÊÕ»½ÐÑÌõ¼þÅäÖà (Wakeup Byte Config)
1£º½ÓÊÕÍê1×Ö½Ú£¬²¢ÇÒÆæżУÑéºÍSTOPλ¶¼ÕýÈ·£¬²Å´¥·¢»½ÐÑÖжÏ
0£º½ÓÊÕÍê1×Ö½Ú£¬²»¼ì²éУÑéλºÍSTOPλ£¬Ö±½Ó´¥·¢»½ÐÑÖÐ¶Ï */
#define	LPUARTx_CSR_WKBYTECFG_Msk	(0x1U << LPUARTx_CSR_WKBYTECFG_Pos)

#define	LPUARTx_CSR_RXEV_Pos	16	/* »½ÐÑÖжÏʼþÅäÖã¬ÓÃÓÚ¿ØÖƺÎÖÖʼþÏÂÏòCPUÌṩ»½ÐÑÖжÏ
(Receive Wakeup Event)
00£ºSTARTλ¼ì²â»½ÐÑ
01£º1byteÊý¾Ý½ÓÊÕÍê³É
10£º½ÓÊÕÊý¾ÝÆ¥Åä³É¹¦
11£ºRXDϽµÑؼì²â */
#define	LPUARTx_CSR_RXEV_Msk	(0x3U << LPUARTx_CSR_RXEV_Pos)
#define	LPUARTx_CSR_RXEV_START	(0x0U << LPUARTx_CSR_RXEV_Pos)	/* STARTλ¼ì²â»½ÐÑ */
#define	LPUARTx_CSR_RXEV_1BYTE	(0x1U << LPUARTx_CSR_RXEV_Pos)	/* 1byteÊý¾Ý½ÓÊÕÍê³É */
#define	LPUARTx_CSR_RXEV_MATCH	(0x2U << LPUARTx_CSR_RXEV_Pos)	/* ½ÓÊÕÊý¾ÝÆ¥Åä³É¹¦ */
#define	LPUARTx_CSR_RXEV_FALLING	(0x3U << LPUARTx_CSR_RXEV_Pos)	/* RXDϽµÑؼì²â */

#define	LPUARTx_CSR_IOSWAP_Pos	11	/* RXÓëTXÒý½Å½»»»
0£ºÄ¬ÈÏ
1£º½»»» */
#define	LPUARTx_CSR_IOSWAP_Msk	(0x1U << LPUARTx_CSR_IOSWAP_Pos)
#define	LPUARTx_CSR_IOSWAP_DEFUALT	(0x0U << LPUARTx_CSR_IOSWAP_Pos)	/* ĬÈÏ */
#define	LPUARTx_CSR_IOSWAP_SWAP		(0x1U << LPUARTx_CSR_IOSWAP_Pos)	/* ½»»» */


#define	LPUARTx_CSR_DMATXIFCFG_Pos	10	/* DMA·¢ËÍÍê³ÉÖжÏʹÄÜ£¬½öÔÚLPUARTͨ¹ýDMA½øÐз¢ËÍʱÓÐЧ (DMA Transmit Interrupt Config)
1£ºIE=1µÄÇé¿öÏ£¬DMAģʽÏ·¢ËÍÍê×îºóÒ»Ö¡ºó£¬ÔÊÐíÖжÏÐźÅÊä³ö£»×îºóһ֮֡ǰµÄÊý¾ÝÖ¡·¢ËÍÍê³Éºó²»ÔÊÐíÖжÏÐźÅÊä³ö
0£ºÊÇ·ñÔÊÐíÖжÏÐźÅÊä³ö½öÓÉIE¾ö¶¨ */
#define	LPUARTx_CSR_DMATXIFCFG_Msk	(0x1U << LPUARTx_CSR_DMATXIFCFG_Pos)
	/* IE=1µÄÇé¿öÏ£¬DMAģʽÏ·¢ËÍÍê×îºóÒ»Ö¡ºó£¬ÔÊÐíÖжÏÐźÅÊä³ö£»×îºóһ֮֡ǰµÄÊý¾ÝÖ¡·¢ËÍÍê³Éºó²»ÔÊÐíÖжÏÐźÅÊä³ö */
	/* ÊÇ·ñÔÊÐíÖжÏÐźÅÊä³ö½öÓÉIE¾ö¶¨ */

#define	LPUARTx_CSR_BITORD_Pos	9	/* Êý¾Ý·¢ËÍ/½ÓÊÕʱµÄλ˳Ðò (Bit Order)
0£ºLSB first
1£ºMSB first */
#define	LPUARTx_CSR_BITORD_Msk	(0x1U << LPUARTx_CSR_BITORD_Pos)
#define	LPUARTx_CSR_BITORD_LSB	(0x0U << LPUARTx_CSR_BITORD_Pos)	/* LSB first */
#define	LPUARTx_CSR_BITORD_MSB	(0x1U << LPUARTx_CSR_BITORD_Pos)	/* MSB first */

#define	LPUARTx_CSR_STOPCFG_Pos	8	/* ֹͣλ¿í¶ÈÅäÖ㬽ö¶Ô·¢ËÍÖ¡¸ñʽÓÐЧ£¬½ÓÊÕʱ²»ÅжÏֹͣλ¸öÊý (Stop bit Config)
0£º1λֹͣλ
1£º2λֹͣλ */
#define	LPUARTx_CSR_STOPCFG_Msk	(0x1U << LPUARTx_CSR_STOPCFG_Pos)
#define	LPUARTx_CSR_STOPCFG_1STOP	(0x0U << LPUARTx_CSR_STOPCFG_Pos)	/* 1λֹͣλ */
#define	LPUARTx_CSR_STOPCFG_2STOP	(0x1U << LPUARTx_CSR_STOPCFG_Pos)	/* 2λֹͣλ */

#define	LPUARTx_CSR_PDSEL_Pos	6	/* ÿ֡Êý¾Ý³¤¶ÈÑ¡Ôñ£»´Ë¼Ä´æÆ÷¶ÔÊý¾Ý·¢ËͺͽÓÊÕͬʱÓÐЧ
(Payload Data length Select)
00£º7λÊý¾Ý
01£º8λÊý¾Ý
10£º9λÊý¾Ý
11£º6λÊý¾Ý */
#define	LPUARTx_CSR_PDSEL_Msk	(0x3U << LPUARTx_CSR_PDSEL_Pos)
#define	LPUARTx_CSR_PDSEL_7BITS	(0x0U << LPUARTx_CSR_PDSEL_Pos)	/* 7λÊý¾Ý */
#define	LPUARTx_CSR_PDSEL_8BITS	(0x1U << LPUARTx_CSR_PDSEL_Pos)	/* 8λÊý¾Ý */
#define	LPUARTx_CSR_PDSEL_9BITS	(0x2U << LPUARTx_CSR_PDSEL_Pos)	/* 9λÊý¾Ý */
#define	LPUARTx_CSR_PDSEL_6BITS	(0x3U << LPUARTx_CSR_PDSEL_Pos)	/* 6λÊý¾Ý */

#define	LPUARTx_CSR_PARITY_Pos	4	/* УÑéλÅäÖ㻴˼ĴæÆ÷¶ÔÊý¾Ý·¢ËͺͽÓÊÕͬʱÓÐЧ (Parity)
00£ºÎÞУÑéλ
01£ºÅ¼Ð£Ñé
10£ºÆæУÑé
11£ºRFU */
#define	LPUARTx_CSR_PARITY_Msk	(0x3U << LPUARTx_CSR_PARITY_Pos)
#define	LPUARTx_CSR_PARITY_NON	(0x0U << LPUARTx_CSR_PARITY_Pos)	/* ÎÞУÑéλ */
#define	LPUARTx_CSR_PARITY_EVEN	(0x1U << LPUARTx_CSR_PARITY_Pos)	/* żУÑé */
#define	LPUARTx_CSR_PARITY_ODD	(0x2U << LPUARTx_CSR_PARITY_Pos)	/* ÆæУÑé */

#define	LPUARTx_CSR_RXPOL_Pos	3	/* ½ÓÊÕÊý¾Ý¼«ÐÔÅäÖà (Receive Polarity)
0£ºÕýÏò
1£ºÈ¡·´ */
#define	LPUARTx_CSR_RXPOL_Msk	(0x1U << LPUARTx_CSR_RXPOL_Pos)
#define	LPUARTx_CSR_RXPOL_POS	(0x0U << LPUARTx_CSR_RXPOL_Pos)	/* ÕýÏò */
#define	LPUARTx_CSR_RXPOL_NEG	(0x1U << LPUARTx_CSR_RXPOL_Pos)	/* È¡·´ */

#define	LPUARTx_CSR_TXPOL_Pos	2	/* ·¢ËÍÊý¾Ý¼«ÐÔÅäÖà (Transmit Polarity)
0£ºÕýÏò
1£ºÈ¡·´ */
#define	LPUARTx_CSR_TXPOL_Msk	(0x1U << LPUARTx_CSR_TXPOL_Pos)
#define	LPUARTx_CSR_TXPOL_POS	(0x0U << LPUARTx_CSR_TXPOL_Pos)	/* ÕýÏò */
#define	LPUARTx_CSR_TXPOL_NEG	(0x1U << LPUARTx_CSR_TXPOL_Pos)	/* È¡·´ */

#define	LPUARTx_CSR_RXEN_Pos	1	/* ½ÓÊÕʹÄÜ£¬1ÓÐЧ (Receive Enable) */
#define	LPUARTx_CSR_RXEN_Msk	(0x1U << LPUARTx_CSR_RXEN_Pos)

#define	LPUARTx_CSR_TXEN_Pos	0	/* ·¢ËÍʹÄÜ£¬1ÓÐЧ (Transmit Enable) */
#define	LPUARTx_CSR_TXEN_Msk	(0x1U << LPUARTx_CSR_TXEN_Pos)

#define	LPUARTx_IER_RXEV_IE_Pos	12	/* ½ÓÊÕ»½ÐÑʼþÖжÏʹÄÜ£¬1ÓÐЧ (Receive Event Interrupt Enable) */
#define	LPUARTx_IER_RXEV_IE_Msk	(0x1U << LPUARTx_IER_RXEV_IE_Pos)

#define	LPUARTx_IER_RXERR_IE_Pos	10	/* ½ÓÊÕ´íÎóÖжÏʹÄÜ£¬1ÓÐЧ (Receive Error Interrupt Enable) */
#define	LPUARTx_IER_RXERR_IE_Msk	(0x1U << LPUARTx_IER_RXERR_IE_Pos)

#define	LPUARTx_IER_RXBF_IE_Pos	8	/* ½ÓÊÕ»º´æÂúÖжÏʹÄÜ£¬1ÓÐЧ (Receive Buffer Full Interrupt Enable) */
#define	LPUARTx_IER_RXBF_IE_Msk	(0x1U << LPUARTx_IER_RXBF_IE_Pos)

#define	LPUARTx_IER_TXBE_IE_Pos	1	/* ·¢ËÍ»º´æ¿ÕÖжÏʹÄÜ£¬1ÓÐЧ (Transmit Buffer Empty Interrupt Enable) */
#define	LPUARTx_IER_TXBE_IE_Msk	(0x1U << LPUARTx_IER_TXBE_IE_Pos)

#define	LPUARTx_IER_TXSE_IE_Pos	0	/* ·¢ËÍ»º´æ¿ÕÇÒ·¢ËÍÒÆλ¼Ä´æÆ÷¿ÕÖжÏʹÄÜ£¬1ÓÐЧ (Transmit Shift register Interrupt Enable) */
#define	LPUARTx_IER_TXSE_IE_Msk	(0x1U << LPUARTx_IER_TXSE_IE_Pos)

#define	LPUARTx_ISR_RXEVF_Pos	24	/* ½ÓÊÕ»½ÐÑʼþÖжϱêÖ¾£¬Ó²¼þÖÃ룬Èí¼þд1ÇåÁã (Receive Event Interrupt Flag)
ÖжϱêÖ¾´¥·¢Ô´ÓÉLPUxCR.RXEV¼Ä´æÆ÷ÅäÖᣠ*/
#define	LPUARTx_ISR_RXEVF_Msk	(0x1U << LPUARTx_ISR_RXEVF_Pos)

#define	LPUARTx_ISR_TXOV_Pos	19	/* ·¢ËÍ»º´æÒç³ö´íÎó£¬Ó²¼þÖÃ룬Èí¼þд1ÇåÁã (Transmit Overflow Error)
µ±·¢ËÍ»º´æÖеÄÊý¾Ý»¹Î´½øÈëÒÆλ¼Ä´æÆ÷·¢ËÍʱ£¬Èí¼þÏò·¢ËÍ»º´æдÈëÐÂÊý¾Ý£¬½«´¥·¢TXOV±êÖ¾ÖÃλ¡£ */
#define	LPUARTx_ISR_TXOV_Msk	(0x1U << LPUARTx_ISR_TXOV_Pos)

#define	LPUARTx_ISR_PERR_Pos	18	/* ÆæżУÑé´íÎóÖжϱêÖ¾£¬Ó²¼þÖÃ룬Èí¼þд1ÇåÁã (Parity Error) */
#define	LPUARTx_ISR_PERR_Msk	(0x1U << LPUARTx_ISR_PERR_Pos)

#define	LPUARTx_ISR_FERR_Pos	17	/* Ö¡¸ñʽ´íÎóÖжϱêÖ¾£¬Ó²¼þÖÃ룬Èí¼þд1ÇåÁã (Frame Error) */
#define	LPUARTx_ISR_FERR_Msk	(0x1U << LPUARTx_ISR_FERR_Pos)

#define	LPUARTx_ISR_OERR_Pos	16	/* ½ÓÊÕ»º´æÒç³ö´íÎóÖжϱêÖ¾£¬µ±½ÓÊÕ»º´æÂúµÄÇé¿öÏ£¬ÊÕµ½ÐµÄÊý¾ÝʱÖÃλ£»Ó²¼þÖÃ룬Èí¼þд1ÇåÁã (Receive Buffer Overflow Error) */
#define	LPUARTx_ISR_OERR_Msk	(0x1U << LPUARTx_ISR_OERR_Pos)

#define	LPUARTx_ISR_RXBF_Pos	8	/* ½ÓÊÕ»º´æÂúÖжϱêÖ¾£¬Ó²¼þÖÃ룬Èí¼þд1»òÕ߶ÁÈ¡RXBUFʱÇåÁã (Receive Buffer Full) */
#define	LPUARTx_ISR_RXBF_Msk	(0x1U << LPUARTx_ISR_RXBF_Pos)

#define	LPUARTx_ISR_TXBE_Pos	1	/* ·¢ËÍ»º´æ¿ÕÖжϱêÖ¾£¬Ó²¼þÖÃλ£¬Ð´ÈëTXBUFʱÇåÁã (Transmit Buffer Empty) */
#define	LPUARTx_ISR_TXBE_Msk	(0x1U << LPUARTx_ISR_TXBE_Pos)

#define	LPUARTx_ISR_TXSE_Pos	0	/* ·¢ËÍ»º´æ¿ÕÇÒ·¢ËÍÒÆλ¼Ä´æÆ÷¿ÕÖжϱêÖ¾£¬Ó²¼þÖÃ룬Èí¼þд1»òÕß·¢ËÍÊý¾Ý±»ÔØÈëÒÆλ¼Ä´æÆ÷ʱÇåÁã (Transmit Shift register Empty) */
#define	LPUARTx_ISR_TXSE_Msk	(0x1U << LPUARTx_ISR_TXSE_Pos)

#define	LPUARTx_BMR_MCTL_Pos	16	/* LPUARTÿ¸öbitµÄλ¿íµ÷ÖÆ¿ØÖÆÐźţ¬²Î¼û´íÎó!δÕÒµ½ÒýÓÃÔ´¡£´íÎó!δÕÒµ½ÒýÓÃÔ´¡£ (Bit Modulation Control) */
#define	LPUARTx_BMR_MCTL_Msk	(0x1fffU << LPUARTx_BMR_MCTL_Pos)

#define	LPUARTx_BMR_BAUD_Pos	0	/* ²¨ÌØÂÊ¿ØÖÆ£¨bps£©
000£º9600
001£º4800
010£º2400
011£º1200
100£º600
101/110/111£º300 */
#define	LPUARTx_BMR_BAUD_Msk	(0x7U << LPUARTx_BMR_BAUD_Pos)
#define	LPUARTx_BMR_BAUD_9600	(0x0U << LPUARTx_BMR_BAUD_Pos)	/* 9600 */
#define	LPUARTx_BMR_BAUD_4800	(0x1U << LPUARTx_BMR_BAUD_Pos)	/* 4800 */
#define	LPUARTx_BMR_BAUD_2400	(0x2U << LPUARTx_BMR_BAUD_Pos)	/* 2400 */
#define	LPUARTx_BMR_BAUD_1200	(0x3U << LPUARTx_BMR_BAUD_Pos)	/* 1200 */
#define	LPUARTx_BMR_BAUD_600	(0x4U << LPUARTx_BMR_BAUD_Pos)	/* 600 */
#define	LPUARTx_BMR_BAUD_300	(0x5U << LPUARTx_BMR_BAUD_Pos)	/* 300 */

#define	LPUARTx_RXBUF_RXBUF_Pos	0	/* ½ÓÊÕÊý¾Ý»º´æ¼Ä´æÆ÷ (Receive Buffer) */
#define	LPUARTx_RXBUF_RXBUF_Msk	(0x1ffU << LPUARTx_RXBUF_RXBUF_Pos)

#define	LPUARTx_TXBUF_TXBUF_Pos	0	/* ·¢ËÍÊý¾Ý»º´æ¼Ä´æÆ÷ (Transmit Buffer) */
#define	LPUARTx_TXBUF_TXBUF_Msk	(0x1ffU << LPUARTx_TXBUF_TXBUF_Pos)

#define	LPUARTx_DMR_MATD_Pos	0	/* µÚÒ»Ö¡½ÓÊձȽÏÊý¾Ý£¬Èç¹ûRXEV=10£¬µ±½ÓÊÕµ½µÄµÚÒ»Ö¡Êý¾ÝÓëMATDÏàͬʱ£¬´¥·¢RXEVFÖжϣ¬¿ÉÒÔÓÃÓÚÐÝÃßģʽϵÄÊý¾Ý½ÓÊÕ»½ÐÑ¡£
(Matched Data) */
#define	LPUARTx_DMR_MATD_Msk	(0x1ffU << LPUARTx_DMR_MATD_Pos)
//Macro_End

/* Exported functions --------------------------------------------------------*/ 
extern void LPUARTx_Deinit(LPUART_Type* LPUARTx);

/* LPUARTͨÐűêÖ¾£¬Ö»¶Á (Busy)
1£ºLPUARTÕýÔÚͨÐÅÖÐ
0£ºLPUART¿ÕÏÐ Ïà¹Øº¯Êý */
extern FlagStatus LPUARTx_CSR_BUSY_Chk(LPUART_Type* LPUARTx);

/* Êý¾Ý½ÓÊÕ»½ÐÑÌõ¼þÅäÖà Ïà¹Øº¯Êý */
extern void LPUARTx_CSR_WKBYTECFG_Setable(LPUART_Type* LPUARTx, FunState NewState);
	
/* Êý¾Ý½ÓÊÕ»½ÐÑÌõ¼þÅäÖà (Wakeup Byte Config)
1£º½ÓÊÕÍê1×Ö½Ú£¬²¢ÇÒÆæżУÑéºÍSTOPλ¶¼ÕýÈ·£¬²Å´¥·¢»½ÐÑÖжÏ
0£º½ÓÊÕÍê1×Ö½Ú£¬²»¼ì²éУÑéλºÍSTOPλ£¬Ö±½Ó´¥·¢»½ÐÑÖÐ¶Ï Ïà¹Øº¯Êý */
extern FlagStatus LPUARTx_CSR_WKBYTECFG_Chk(LPUART_Type* LPUARTx);

/* »½ÐÑÖжÏʼþÅäÖã¬ÓÃÓÚ¿ØÖƺÎÖÖʼþÏÂÏòCPUÌṩ»½ÐÑÖжÏ
(Receive Wakeup Event)
00£ºSTARTλ¼ì²â»½ÐÑ
01£º1byteÊý¾Ý½ÓÊÕÍê³É
10£º½ÓÊÕÊý¾ÝÆ¥Åä³É¹¦
11£ºRXDϽµÑؼì²â Ïà¹Øº¯Êý */
extern void LPUARTx_CSR_RXEV_Set(LPUART_Type* LPUARTx,uint32_t SetValue);
extern uint32_t LPUARTx_CSR_RXEV_Get(LPUART_Type* LPUARTx);

/* RXÓëTXÒý½Å½»»»
0£ºÄ¬ÈÏ
1£º½»»» */
extern void LPUARTx_CSR_IOSWAP_Set(LPUART_Type* LPUARTx,uint32_t SetValue);
extern uint32_t LPUARTx_CSR_IOSWAP_Get(LPUART_Type* LPUARTx);


/* DMA·¢ËÍÍê³ÉÖжÏʹÄÜ£¬½öÔÚLPUARTͨ¹ýDMA½øÐз¢ËÍʱÓÐЧ (DMA Transmit Interrupt Config)
1£ºIE=1µÄÇé¿öÏ£¬DMAģʽÏ·¢ËÍÍê×îºóÒ»Ö¡ºó£¬ÔÊÐíÖжÏÐźÅÊä³ö£»×îºóһ֮֡ǰµÄÊý¾ÝÖ¡·¢ËÍÍê³Éºó²»ÔÊÐíÖжÏÐźÅÊä³ö
0£ºÊÇ·ñÔÊÐíÖжÏÐźÅÊä³ö½öÓÉIE¾ö¶¨ Ïà¹Øº¯Êý */
extern void LPUARTx_CSR_DMATXIFCFG_Setable(LPUART_Type* LPUARTx,FunState NewState);
extern FunState LPUARTx_CSR_DMATXIFCFG_Getable(LPUART_Type* LPUARTx);

/* Êý¾Ý·¢ËÍ/½ÓÊÕʱµÄλ˳Ðò (Bit Order)
0£ºLSB first
1£ºMSB first Ïà¹Øº¯Êý */
extern void LPUARTx_CSR_BITORD_Set(LPUART_Type* LPUARTx,uint32_t SetValue);
extern uint32_t LPUARTx_CSR_BITORD_Get(LPUART_Type* LPUARTx);

/* ֹͣλ¿í¶ÈÅäÖ㬽ö¶Ô·¢ËÍÖ¡¸ñʽÓÐЧ£¬½ÓÊÕʱ²»ÅжÏֹͣλ¸öÊý (Stop bit Config)
0£º1λֹͣλ
1£º2λֹͣλ Ïà¹Øº¯Êý */
extern void LPUARTx_CSR_STOPCFG_Set(LPUART_Type* LPUARTx,uint32_t SetValue);
extern uint32_t LPUARTx_CSR_STOPCFG_Get(LPUART_Type* LPUARTx);

/* ÿ֡Êý¾Ý³¤¶ÈÑ¡Ôñ£»´Ë¼Ä´æÆ÷¶ÔÊý¾Ý·¢ËͺͽÓÊÕͬʱÓÐЧ
(Payload Data length Select)
00£º7λÊý¾Ý
01£º8λÊý¾Ý
10£º9λÊý¾Ý
11£º6λÊý¾Ý Ïà¹Øº¯Êý */
extern void LPUARTx_CSR_PDSEL_Set(LPUART_Type* LPUARTx,uint32_t SetValue);
extern uint32_t LPUARTx_CSR_PDSEL_Get(LPUART_Type* LPUARTx);

/* УÑéλÅäÖ㻴˼ĴæÆ÷¶ÔÊý¾Ý·¢ËͺͽÓÊÕͬʱÓÐЧ (Parity)
00£ºÎÞУÑéλ
01£ºÅ¼Ð£Ñé
10£ºÆæУÑé
11£ºRFU Ïà¹Øº¯Êý */
extern void LPUARTx_CSR_PARITY_Set(LPUART_Type* LPUARTx,uint32_t SetValue);
extern uint32_t LPUARTx_CSR_PARITY_Get(LPUART_Type* LPUARTx);

/* ½ÓÊÕÊý¾Ý¼«ÐÔÅäÖà (Receive Polarity)
0£ºÕýÏò
1£ºÈ¡·´ Ïà¹Øº¯Êý */
extern void LPUARTx_CSR_RXPOL_Set(LPUART_Type* LPUARTx,uint32_t SetValue);
extern uint32_t LPUARTx_CSR_RXPOL_Get(LPUART_Type* LPUARTx);

/* ·¢ËÍÊý¾Ý¼«ÐÔÅäÖà (Transmit Polarity)
0£ºÕýÏò
1£ºÈ¡·´ Ïà¹Øº¯Êý */
extern void LPUARTx_CSR_TXPOL_Set(LPUART_Type* LPUARTx,uint32_t SetValue);
extern uint32_t LPUARTx_CSR_TXPOL_Get(LPUART_Type* LPUARTx);

/* ½ÓÊÕʹÄÜ£¬1ÓÐЧ (Receive Enable) Ïà¹Øº¯Êý */
extern void LPUARTx_CSR_RXEN_Setable(LPUART_Type* LPUARTx,FunState NewState);
extern FunState LPUARTx_CSR_RXEN_Getable(LPUART_Type* LPUARTx);

/* ·¢ËÍʹÄÜ£¬1ÓÐЧ (Transmit Enable) Ïà¹Øº¯Êý */
extern void LPUARTx_CSR_TXEN_Setable(LPUART_Type* LPUARTx,FunState NewState);
extern FunState LPUARTx_CSR_TXEN_Getable(LPUART_Type* LPUARTx);

/* ½ÓÊÕ»½ÐÑʼþÖжÏʹÄÜ£¬1ÓÐЧ (Receive Event Interrupt Enable) Ïà¹Øº¯Êý */
extern void LPUARTx_IER_RXEV_IE_Setable(LPUART_Type* LPUARTx,FunState NewState);
extern FunState LPUARTx_IER_RXEV_IE_Getable(LPUART_Type* LPUARTx);

/* ½ÓÊÕ´íÎóÖжÏʹÄÜ£¬1ÓÐЧ (Receive Error Interrupt Enable) Ïà¹Øº¯Êý */
extern void LPUARTx_IER_RXERR_IE_Setable(LPUART_Type* LPUARTx,FunState NewState);
extern FunState LPUARTx_IER_RXERR_IE_Getable(LPUART_Type* LPUARTx);

/* ½ÓÊÕ»º´æÂúÖжÏʹÄÜ£¬1ÓÐЧ (Receive Buffer Full Interrupt Enable) Ïà¹Øº¯Êý */
extern void LPUARTx_IER_RXBF_IE_Setable(LPUART_Type* LPUARTx,FunState NewState);
extern FunState LPUARTx_IER_RXBF_IE_Getable(LPUART_Type* LPUARTx);

/* ·¢ËÍ»º´æ¿ÕÖжÏʹÄÜ£¬1ÓÐЧ (Transmit Buffer Empty Interrupt Enable) Ïà¹Øº¯Êý */
extern void LPUARTx_IER_TXBE_IE_Setable(LPUART_Type* LPUARTx,FunState NewState);
extern FunState LPUARTx_IER_TXBE_IE_Getable(LPUART_Type* LPUARTx);

/* ·¢ËÍ»º´æ¿ÕÇÒ·¢ËÍÒÆλ¼Ä´æÆ÷¿ÕÖжÏʹÄÜ£¬1ÓÐЧ (Transmit Shift register Interrupt Enable) Ïà¹Øº¯Êý */
extern void LPUARTx_IER_TXSE_IE_Setable(LPUART_Type* LPUARTx,FunState NewState);
extern FunState LPUARTx_IER_TXSE_IE_Getable(LPUART_Type* LPUARTx);

/* ½ÓÊÕ»½ÐÑʼþÖжϱêÖ¾£¬Ó²¼þÖÃ룬Èí¼þд1ÇåÁã (Receive Event Interrupt Flag)
ÖжϱêÖ¾´¥·¢Ô´ÓÉLPUxCR.RXEV¼Ä´æÆ÷ÅäÖᣠÏà¹Øº¯Êý */
extern void LPUARTx_ISR_RXEVF_Clr(LPUART_Type* LPUARTx);
extern FlagStatus LPUARTx_ISR_RXEVF_Chk(LPUART_Type* LPUARTx);

/* ·¢ËÍ»º´æÒç³ö´íÎó£¬Ó²¼þÖÃ룬Èí¼þд1ÇåÁã (Transmit Overflow Error)
µ±·¢ËÍ»º´æÖеÄÊý¾Ý»¹Î´½øÈëÒÆλ¼Ä´æÆ÷·¢ËÍʱ£¬Èí¼þÏò·¢ËÍ»º´æдÈëÐÂÊý¾Ý£¬½«´¥·¢TXOV±êÖ¾ÖÃλ¡£ Ïà¹Øº¯Êý */
extern void LPUARTx_ISR_TXOV_Clr(LPUART_Type* LPUARTx);
extern FlagStatus LPUARTx_ISR_TXOV_Chk(LPUART_Type* LPUARTx);

/* ÆæżУÑé´íÎóÖжϱêÖ¾£¬Ó²¼þÖÃ룬Èí¼þд1ÇåÁã (Parity Error) Ïà¹Øº¯Êý */
extern void LPUARTx_ISR_PERR_Clr(LPUART_Type* LPUARTx);
extern FlagStatus LPUARTx_ISR_PERR_Chk(LPUART_Type* LPUARTx);

/* Ö¡¸ñʽ´íÎóÖжϱêÖ¾£¬Ó²¼þÖÃ룬Èí¼þд1ÇåÁã (Frame Error) Ïà¹Øº¯Êý */
extern void LPUARTx_ISR_FERR_Clr(LPUART_Type* LPUARTx);
extern FlagStatus LPUARTx_ISR_FERR_Chk(LPUART_Type* LPUARTx);

/* ½ÓÊÕ»º´æÒç³ö´íÎóÖжϱêÖ¾£¬µ±½ÓÊÕ»º´æÂúµÄÇé¿öÏ£¬ÊÕµ½ÐµÄÊý¾ÝʱÖÃλ£»Ó²¼þÖÃ룬Èí¼þд1ÇåÁã (Receive Buffer Overflow Error) Ïà¹Øº¯Êý */
extern void LPUARTx_ISR_OERR_Clr(LPUART_Type* LPUARTx);
extern FlagStatus LPUARTx_ISR_OERR_Chk(LPUART_Type* LPUARTx);

/* ½ÓÊÕ»º´æÂúÖжϱêÖ¾£¬Ó²¼þÖÃ룬Èí¼þд1»òÕ߶ÁÈ¡RXBUFʱÇåÁã (Receive Buffer Full) Ïà¹Øº¯Êý */
extern void LPUARTx_ISR_RXBF_Clr(LPUART_Type* LPUARTx);
extern FlagStatus LPUARTx_ISR_RXBF_Chk(LPUART_Type* LPUARTx);

/* ·¢ËÍ»º´æ¿ÕÖжϱêÖ¾£¬Ó²¼þÖÃλ£¬Ð´ÈëTXBUFʱÇåÁã (Transmit Buffer Empty) Ïà¹Øº¯Êý */
extern FlagStatus LPUARTx_ISR_TXBE_Chk(LPUART_Type* LPUARTx);

/* ·¢ËÍ»º´æ¿ÕÇÒ·¢ËÍÒÆλ¼Ä´æÆ÷¿ÕÖжϱêÖ¾£¬Ó²¼þÖÃ룬Èí¼þд1»òÕß·¢ËÍÊý¾Ý±»ÔØÈëÒÆλ¼Ä´æÆ÷ʱÇåÁã (Transmit Shift register Empty) Ïà¹Øº¯Êý */
extern void LPUARTx_ISR_TXSE_Clr(LPUART_Type* LPUARTx);
extern FlagStatus LPUARTx_ISR_TXSE_Chk(LPUART_Type* LPUARTx);

/* LPUARTÿ¸öbitµÄλ¿íµ÷ÖÆ¿ØÖÆÐźţ¬²Î¼û´íÎó!δÕÒµ½ÒýÓÃÔ´¡£´íÎó!δÕÒµ½ÒýÓÃÔ´¡£ (Bit Modulation Control) Ïà¹Øº¯Êý */
extern void LPUARTx_BMR_MCTL_Set(LPUART_Type* LPUARTx,uint32_t SetValue);
extern uint32_t LPUARTx_BMR_MCTL_Get(LPUART_Type* LPUARTx);

/* ²¨ÌØÂÊ¿ØÖÆ£¨bps£©
000£º9600
001£º4800
010£º2400
011£º1200
100£º600
101/110/111£º300 Ïà¹Øº¯Êý */
extern void LPUARTx_BMR_BAUD_Set(LPUART_Type* LPUARTx,uint32_t SetValue);
extern uint32_t LPUARTx_BMR_BAUD_Get(LPUART_Type* LPUARTx);

/* ½ÓÊÕÊý¾Ý»º´æ¼Ä´æÆ÷ (Receive Buffer) Ïà¹Øº¯Êý */
extern uint32_t LPUARTx_RXBUF_Read(LPUART_Type* LPUARTx);

/* ·¢ËÍÊý¾Ý»º´æ¼Ä´æÆ÷ (Transmit Buffer) Ïà¹Øº¯Êý */
extern void LPUARTx_TXBUF_Write(LPUART_Type* LPUARTx,uint32_t SetValue);

/* µÚÒ»Ö¡½ÓÊձȽÏÊý¾Ý£¬Èç¹ûRXEV=10£¬µ±½ÓÊÕµ½µÄµÚÒ»Ö¡Êý¾ÝÓëMATDÏàͬʱ£¬´¥·¢RXEVFÖжϣ¬¿ÉÒÔÓÃÓÚÐÝÃßģʽϵÄÊý¾Ý½ÓÊÕ»½ÐÑ¡£
(Matched Data) Ïà¹Øº¯Êý */
extern void LPUARTx_DMR_Write(LPUART_Type* LPUARTx,uint32_t SetValue);
extern uint32_t LPUARTx_DMR_Read(LPUART_Type* LPUARTx);
//Announce_End
#ifdef __cplusplus
}
#endif

#endif /*__FM33A0XXEV_LPUART_H */