/** ****************************************************************************** * @file fm33a0xxev_qspi.h * @author FM33A0XXEV Application Team * @version V1.0.0 * @date 16-April-2020 * @brief This file contains all the functions prototypes for the QSPI firmware library. ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __FM33A0XXEV_QSPI_H #define __FM33A0XXEV_QSPI_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "FM33A0XXEV.h" typedef struct { uint32_t Instruction; uint32_t Address; uint32_t AlternateByte; uint32_t AddressSize; uint32_t AlternateByteSize; uint32_t DummyCycles; uint32_t InstructionMode; uint32_t AddressMode; uint32_t AlternateByteMode; uint32_t DataMode; }QSPI_CmdTypeDef; #define QSPI_CR_PRESCALER_Pos 24 #define QSPI_CR_PRESCALER_Msk (0xffU << QSPI_CR_PRESCALER_Pos) #define QSPI_CR_PMM_Pos 23 /* ÂÖѯƥÅäģʽ 0£ºANDģʽ£¬ËùÓÐbit¶¼Æ¥Åä²ÅÖÃλSMF 1£ºORģʽ£¬ÖÁÉÙ1bitÆ¥Åä¾Í»áÖÃλSMF */ #define QSPI_CR_PMM_Msk (0x1U << QSPI_CR_PMM_Pos) #define QSPI_CR_PMM_AND (0x0U << QSPI_CR_PMM_Pos) /* ANDģʽ£¬ËùÓÐbit¶¼Æ¥Åä²ÅÖÃλSMF */ #define QSPI_CR_PMM_OR (0x1U << QSPI_CR_PMM_Pos) /* ORģʽ£¬ÖÁÉÙ1bitÆ¥Åä¾Í»áÖÃλSMF */ #define QSPI_CR_TOIE_Pos 20 /* ³¬Ê±ÖжÏʹÄÜ 0£º½ûÖ¹³¬Ê±ÖÐ¶Ï 1£ºÔÊÐí³¬Ê±ÖÐ¶Ï */ #define QSPI_CR_TOIE_Msk (0x1U << QSPI_CR_TOIE_Pos) /* ½ûÖ¹³¬Ê±ÖÐ¶Ï */ /* ÔÊÐí³¬Ê±ÖÐ¶Ï */ #define QSPI_CR_SMIE_Pos 19 /* ״̬ƥÅäÖжÏʹÄÜ 0£º½ûֹ״̬ƥÅäÖÐ¶Ï 1£ºÔÊÐí״̬ƥÅäÖÐ¶Ï */ #define QSPI_CR_SMIE_Msk (0x1U << QSPI_CR_SMIE_Pos) /* ½ûֹ״̬ƥÅäÖÐ¶Ï */ /* ÔÊÐí״̬ƥÅäÖÐ¶Ï */ #define QSPI_CR_FTIE_Pos 18 /* FIFOˮλÖжÏʹÄÜ 0£º½ûÖ¹FIFOˮλÖÐ¶Ï 1£ºÔÊÐíFIFOˮλÖÐ¶Ï */ #define QSPI_CR_FTIE_Msk (0x1U << QSPI_CR_FTIE_Pos) /* ½ûÖ¹FIFOˮλÖÐ¶Ï */ /* ÔÊÐíFIFOˮλÖÐ¶Ï */ #define QSPI_CR_TCIE_Pos 17 /* ´«ÊäÍê³ÉÖжÏʹÄÜ 0£º½ûÖ¹´«ÊäÍê³ÉÖÐ¶Ï 1£ºÔÊÐí´«ÊäÍê³ÉÖÐ¶Ï */ #define QSPI_CR_TCIE_Msk (0x1U << QSPI_CR_TCIE_Pos) /* ½ûÖ¹´«ÊäÍê³ÉÖÐ¶Ï */ /* ÔÊÐí´«ÊäÍê³ÉÖÐ¶Ï */ #define QSPI_CR_TEIE_Pos 16 /* ´«Êä´íÎóÖжÏʹÄÜ 0£º½ûÖ¹´«Êä´íÎóÖÐ¶Ï 1£ºÔÊÐí´«Êä´íÎóÖÐ¶Ï */ #define QSPI_CR_TEIE_Msk (0x1U << QSPI_CR_TEIE_Pos) /* ½ûÖ¹´«Êä´íÎóÖÐ¶Ï */ /* ÔÊÐí´«Êä´íÎóÖÐ¶Ï */ #define QSPI_CR_FIFOTHR_Pos 8 /* FIFOˮλ¼Ä´æÆ÷£¬½öÍâÉèģʽÏÂÆðЧ ÍâÉèдģʽ£º 0£ºFTFÔÚFIFO¿Õ×Ö½Ú´óÓÚµÈÓÚ1ʱÖÃλ 1£ºFTFÔÚFIFO¿Õ×Ö½Ú´óÓÚµÈÓÚ2ʱÖÃλ ¡­¡­ 15£ºFTFÔÚFIFO¿Õ×Ö½ÚµÈÓÚ16ʱÖÃλ ÍâÉè¶Áģʽ£º 0£ºFTFÔÚFIFOÖÐ×Ö½ÚÊý´óÓÚµÈÓÚ1ʱÖÃλ 1£ºFTFÔÚFIFOÖÐ×Ö½ÚÊý´óÓÚµÈÓÚ2ʱÖÃλ ¡­¡­ 15£ºFTFÔÚFIFOÖÐ×Ö½ÚÊýµÈÓÚ16ʱÖÃλ */ #define QSPI_CR_FIFOTHR_Msk (0xfU << QSPI_CR_FIFOTHR_Pos) #define QSPI_CR_FIFOTHR_1 (0x0U << QSPI_CR_FIFOTHR_Pos) /* FTFÔÚFIFO¿Õ×Ö½Ú´óÓÚµÈÓÚ1ʱÖÃλ */ #define QSPI_CR_FIFOTHR_2 (0x1U << QSPI_CR_FIFOTHR_Pos) /* FTFÔÚFIFO¿Õ×Ö½Ú´óÓÚµÈÓÚ2ʱÖÃλ */ #define QSPI_CR_FIFOTHR_3 (0x2U << QSPI_CR_FIFOTHR_Pos) /* FTFÔÚFIFO¿Õ×Ö½Ú´óÓÚµÈÓÚ3ʱÖÃλ */ #define QSPI_CR_FIFOTHR_4 (0x3U << QSPI_CR_FIFOTHR_Pos) /* FTFÔÚFIFO¿Õ×Ö½Ú´óÓÚµÈÓÚ4ʱÖÃλ */ #define QSPI_CR_FIFOTHR_5 (0x4U << QSPI_CR_FIFOTHR_Pos) /* FTFÔÚFIFO¿Õ×Ö½Ú´óÓÚµÈÓÚ5ʱÖÃλ */ #define QSPI_CR_FIFOTHR_6 (0x5U << QSPI_CR_FIFOTHR_Pos) /* FTFÔÚFIFO¿Õ×Ö½Ú´óÓÚµÈÓÚ6ʱÖÃλ */ #define QSPI_CR_FIFOTHR_7 (0x6U << QSPI_CR_FIFOTHR_Pos) /* FTFÔÚFIFO¿Õ×Ö½Ú´óÓÚµÈÓÚ7ʱÖÃλ */ #define QSPI_CR_FIFOTHR_8 (0x7U << QSPI_CR_FIFOTHR_Pos) /* FTFÔÚFIFO¿Õ×Ö½Ú´óÓÚµÈÓÚ8ʱÖÃλ */ #define QSPI_CR_FIFOTHR_9 (0x8U << QSPI_CR_FIFOTHR_Pos) /* FTFÔÚFIFO¿Õ×Ö½Ú´óÓÚµÈÓÚ9ʱÖÃλ */ #define QSPI_CR_FIFOTHR_10 (0x9U << QSPI_CR_FIFOTHR_Pos) /* FTFÔÚFIFO¿Õ×Ö½Ú´óÓÚµÈÓÚ10ʱÖÃλ */ #define QSPI_CR_FIFOTHR_11 (0x10U << QSPI_CR_FIFOTHR_Pos) /* FTFÔÚFIFO¿Õ×Ö½Ú´óÓÚµÈÓÚ11ʱÖÃλ */ #define QSPI_CR_FIFOTHR_12 (0x11U << QSPI_CR_FIFOTHR_Pos) /* FTFÔÚFIFO¿Õ×Ö½Ú´óÓÚµÈÓÚ12ʱÖÃλ */ #define QSPI_CR_FIFOTHR_13 (0x12U << QSPI_CR_FIFOTHR_Pos) /* FTFÔÚFIFO¿Õ×Ö½Ú´óÓÚµÈÓÚ13ʱÖÃλ */ #define QSPI_CR_FIFOTHR_14 (0x13U << QSPI_CR_FIFOTHR_Pos) /* FTFÔÚFIFO¿Õ×Ö½Ú´óÓÚµÈÓÚ14ʱÖÃλ */ #define QSPI_CR_FIFOTHR_15 (0x14U << QSPI_CR_FIFOTHR_Pos) /* FTFÔÚFIFO¿Õ×Ö½Ú´óÓÚµÈÓÚ15ʱÖÃλ */ #define QSPI_CR_FIFOTHR_16 (0x15U << QSPI_CR_FIFOTHR_Pos) /* FTFÔÚFIFO¿Õ×Ö½ÚµÈÓÚ16ʱÖÃλ */ #define QSPI_CR_SSHFT_Pos 4 /* ÑÓ³Ù²ÉÑùʹÄÜ 0£º¹Ø±ÕÑÓ³Ù²ÉÑù¹¦ÄÜ 1£ºÊ¹ÄÜÑÓ³Ù²ÉÑù¹¦ÄÜ */ #define QSPI_CR_SSHFT_Msk (0x1U << QSPI_CR_SSHFT_Pos) /* ¹Ø±ÕÑÓ³Ù²ÉÑù¹¦ÄÜ */ /* ʹÄÜÑÓ³Ù²ÉÑù¹¦ÄÜ */ #define QSPI_CR_TCEN_Pos 3 /* ×ÜÏß³¬Ê±Ê¹ÄÜ£¬´Ë¼Ä´æÆ÷½öÔÚ´æ´¢Æ÷Ó³ÉäģʽÏÂÓÐЧ µ±BUSYÖÃλºó£¬Èç¹ûQuadSPI²»·¢Æð¶ÔQSPI´æ´¢Æ÷µÄ·ÃÎÊ£¬³¬Ê±¼Ä´æÆ÷¿ªÊ¼¼ÆÊý£¬¼ÆÊýÒç³ö³¤¶ÈÓÉTIMEOUT¼Ä´æÆ÷¶¨Òå¡£µ±QSPI×ÜÏß³¤Ê±¼äÎÞ¶¯×÷£¬¼ÆÊýÆ÷Òç³ö£¬nCS±»×Ô¶¯À­¸ß£¬Ç¿ÖƽáÊøµ±Ç°´«Êä¹ý³Ì¡£ 0£º¹Ø±Õ³¬Ê±¹¦ÄÜ 1£ºÊ¹Äܳ¬Ê±¹¦ÄÜ */ #define QSPI_CR_TCEN_Msk (0x1U << QSPI_CR_TCEN_Pos) /* ¹Ø±Õ³¬Ê±¹¦ÄÜ */ /* ʹÄܳ¬Ê±¹¦ÄÜ */ #define QSPI_CR_DMAEN_Pos 2 /* DMAʹÄÜ 0£ºDMA¹¦Äܹرգ¬QuadSPI²»»á·¢ËÍDMAÇëÇó 1£ºDMA¹¦ÄÜ¿ªÆô£¬QuadSPIÔÚÂú×ãÌõ¼þʱ·¢ËÍDMAÇëÇó */ #define QSPI_CR_DMAEN_Msk (0x1U << QSPI_CR_DMAEN_Pos) /* DMA¹¦Äܹرգ¬QuadSPI²»»á·¢ËÍDMAÇëÇó */ /* DMA¹¦ÄÜ¿ªÆô£¬QuadSPIÔÚÂú×ãÌõ¼þʱ·¢ËÍDMAÇëÇó */ #define QSPI_CR_ABORT_Pos 1 /* µ±Ç°´«ÊäÖÕÖ¹¼Ä´æÆ÷£¬Èí¼þд1ÖÕÖ¹´«Ê䣬Ӳ¼þÀ­¸ßnCSºó×Ô¶¯ÇåÁã */ #define QSPI_CR_ABORT_Msk (0x1U << QSPI_CR_ABORT_Pos) #define QSPI_CR_EN_Pos 0 /* QuadSPIÄ£¿éʹÄÜ 0£º¹Ø±ÕQuadSPI 1£ºÊ¹ÄÜQuadSPI */ #define QSPI_CR_EN_Msk (0x1U << QSPI_CR_EN_Pos) /* ¹Ø±ÕQuadSPI */ /* ʹÄÜQuadSPI */ #define QSPI_CFG_CSHT_Pos 8 /* nCS×îС¸ßµçƽʱ¼ä£¬¶¨ÒåÁËÁ¬ÐøÁ½¸öÖ¡Ö®¼änCSËùÐè±£³Ö¸ßµçƽµÄ×î¶Ìʱ¼ä£¬ÒÔQSPI_CLKÖÜÆÚ¼ÆÊý 0£ºÖÁÉÙ1 cycle 1£ºÖÁÉÙ2 cycles ¡­¡­ 7£ºÖÁÉÙ8 cycles */ #define QSPI_CFG_CSHT_Msk (0x7U << QSPI_CFG_CSHT_Pos) #define QSPI_CFG_CSHT_1CYCLE (0x0U << QSPI_CFG_CSHT_Pos) /* ÖÁÉÙ1 cycle */ #define QSPI_CFG_CSHT_2CYCLES (0x1U << QSPI_CFG_CSHT_Pos) /* ÖÁÉÙ2 cycles */ #define QSPI_CFG_CSHT_3CYCLES (0x2U << QSPI_CFG_CSHT_Pos) /* ÖÁÉÙ3 cycles */ #define QSPI_CFG_CSHT_4CYCLES (0x3U << QSPI_CFG_CSHT_Pos) /* ÖÁÉÙ4 cycles */ #define QSPI_CFG_CSHT_5CYCLES (0x4U << QSPI_CFG_CSHT_Pos) /* ÖÁÉÙ5 cycles */ #define QSPI_CFG_CSHT_6CYCLES (0x5U << QSPI_CFG_CSHT_Pos) /* ÖÁÉÙ6 cycles */ #define QSPI_CFG_CSHT_7CYCLES (0x6U << QSPI_CFG_CSHT_Pos) /* ÖÁÉÙ7 cycles */ #define QSPI_CFG_CSHT_8CYCLES (0x7U << QSPI_CFG_CSHT_Pos) /* ÖÁÉÙ8 cycles */ #define QSPI_CFG_CKMODE_Pos 0 /* SPI Clock Mode¼Ä´æÆ÷ 0£ºmode 0 1£ºmode 3 */ #define QSPI_CFG_CKMODE_Msk (0x1U << QSPI_CFG_CKMODE_Pos) #define QSPI_CFG_CKMODE_MODE0 (0x0U << QSPI_CFG_CKMODE_Pos) /* mode 0 */ #define QSPI_CFG_CKMODE_MODE3 (0x1U << QSPI_CFG_CKMODE_Pos) /* mode 3 */ #define QSPI_SR_FIFOLVL_Pos 8 /* FIFOˮλ±êÖ¾ ´Ë¼Ä´æÆ÷±íʾµ±Ç°FIFOÖб£´æµÄÊý¾Ý×Ö½ÚÊý£¬0±íʾFIFO¿Õ£¬16±íʾFIFOÂú ×Ô¶¯²éѯģʽÏ´˼ĴæÆ÷±£³Ö0 */ #define QSPI_SR_FIFOLVL_Msk (0x1fU << QSPI_SR_FIFOLVL_Pos) #define QSPI_SR_BUSY_Pos 5 /* 1±íʾQuadSPI´«Êä½øÐÐÖУ¬Í¨ÐŽáÊøºó×Ô¶¯ÇåÁã */ #define QSPI_SR_BUSY_Msk (0x1U << QSPI_SR_BUSY_Pos) #define QSPI_SR_TOF_Pos 4 /* ³¬Ê±±êÖ¾£¬Ó²¼þÖÃ룬Èí¼þд1ÇåÁã */ #define QSPI_SR_TOF_Msk (0x1U << QSPI_SR_TOF_Pos) #define QSPI_SR_SMF_Pos 3 /* ×Ô¶¯²éѯģʽϱíÕ÷״̬¼Ä´æÆ÷Æ¥Åä³É¹¦£¬Ó²¼þÖÃ룬Èí¼þд1ÇåÁã */ #define QSPI_SR_SMF_Msk (0x1U << QSPI_SR_SMF_Pos) #define QSPI_SR_FTF_Pos 2 /* FIFO threshold±êÖ¾£¬FIFOˮλ¸ßÓÚÉ趨ãÐֵʱ×Ô¶¯ÖÃ룬µÍÓÚãÐֵʱ×Ô¶¯ÇåÁã ×Ô¶¯²éѯģʽÏ£¬Ã¿´Î¶Á»ØÒ»×é״ֵ̬ºó¶¼»á×Ô¶¯ÖÃλFTF£¬Èç¹ûÈí¼þ¶ÁÈ¡QSPI_DATA¼Ä´æÆ÷ÔòFTFÇåÁã */ #define QSPI_SR_FTF_Msk (0x1U << QSPI_SR_FTF_Pos) #define QSPI_SR_TCF_Pos 1 /* ´«ÊäÍê³É±êÖ¾£¬Ó²¼þÖÃ룬Èí¼þд1ÇåÁã */ #define QSPI_SR_TCF_Msk (0x1U << QSPI_SR_TCF_Pos) #define QSPI_DATALEN_QSPI_DATALEN_Pos 0 /* ´«ÊäÊý¾Ý³¤¶ÈΪDATALEN+1£¨bytes£© */ #define QSPI_DATALEN_QSPI_DATALEN_Msk (0xffffffffU << QSPI_DATALEN_QSPI_DATALEN_Pos) #define QSPI_CCR_CRM_Pos 28 /* Continuous Read Mode 0£ºÃ¿´ÎͨÐÅ·¢Æðʱ¶¼Òª·¢ËÍÖ¸Áî 1£ºÖ»ÔÚµÚÒ»´ÎͨÐÅʱ·¢ËÍÖ¸Áî */ #define QSPI_CCR_CRM_Msk (0x1U << QSPI_CCR_CRM_Pos) #define QSPI_CCR_CRM_ALWAYS (0x0U << QSPI_CCR_CRM_Pos) /* ÿ´ÎͨÐÅ·¢Æðʱ¶¼Òª·¢ËÍÖ¸Áî */ #define QSPI_CCR_CRM_ONLY (0x1U << QSPI_CCR_CRM_Pos) /* Ö»ÔÚµÚÒ»´ÎͨÐÅʱ·¢ËÍÖ¸Áî */ #define QSPI_CCR_OPMODE_Pos 26 /* ²Ù×÷ģʽ 00£ºÍâÉèдģʽ 01£ºÍâÉè¶Áģʽ 10£º×Ô¶¯²éѯģʽ 11£º´æ´¢Æ÷Ó³Éäģʽ */ #define QSPI_CCR_OPMODE_Msk (0x3U << QSPI_CCR_OPMODE_Pos) #define QSPI_CCR_OPMODE_WRITE (0x0U << QSPI_CCR_OPMODE_Pos) /* ÍâÉèдģʽ */ #define QSPI_CCR_OPMODE_READ (0x1U << QSPI_CCR_OPMODE_Pos) /* ÍâÉè¶Áģʽ */ #define QSPI_CCR_OPMODE_QUERY (0x2U << QSPI_CCR_OPMODE_Pos) /* ×Ô¶¯²éѯģʽ */ #define QSPI_CCR_OPMODE_MAP (0x3U << QSPI_CCR_OPMODE_Pos) /* ´æ´¢Æ÷Ó³Éäģʽ */ #define QSPI_CCR_DMODE_Pos 24 /* Êý¾ÝͨÐÅģʽ£¨data phase£© 00£ºÎÞÊý¾Ý 01£ºµ¥Ïß 10£ºË«Ïß 11£ºËÄÏß */ #define QSPI_CCR_DMODE_Msk (0x3U << QSPI_CCR_DMODE_Pos) #define QSPI_CCR_DMODE_NONE (0x0U << QSPI_CCR_DMODE_Pos) /* ÎÞÊý¾Ý */ #define QSPI_CCR_DMODE_SINGLE (0x1U << QSPI_CCR_DMODE_Pos) /* µ¥Ïß */ #define QSPI_CCR_DMODE_DOUBLE (0x2U << QSPI_CCR_DMODE_Pos) /* Ë«Ïß */ #define QSPI_CCR_DMODE_FOUR (0x3U << QSPI_CCR_DMODE_Pos) /* ËÄÏß */ #define QSPI_CCR_DUMCYC_Pos 18 /* Dummy cycle¸öÊýÅäÖã¨ÒÔQSPI_CLKÖÜÆÚ¼ÆË㣩£¬0~31 */ #define QSPI_CCR_DUMCYC_Msk (0x1fU << QSPI_CCR_DUMCYC_Pos) #define QSPI_CCR_ABSIZE_Pos 16 /* Alternate bytes¸öÊý 00£º8bits alternate bytes 01£º16bits alternate bytes 10£º24bits alternate bytes 11£º32bits alternate bytes */ #define QSPI_CCR_ABSIZE_Msk (0x3U << QSPI_CCR_ABSIZE_Pos) #define QSPI_CCR_ABSIZE_8BITS (0x0U << QSPI_CCR_ABSIZE_Pos) /* 8bits alternate bytes */ #define QSPI_CCR_ABSIZE_16BITS (0x1U << QSPI_CCR_ABSIZE_Pos) /* 16bits alternate bytes */ #define QSPI_CCR_ABSIZE_24BITS (0x2U << QSPI_CCR_ABSIZE_Pos) /* 24bits alternate bytes */ #define QSPI_CCR_ABSIZE_32BITS (0x3U << QSPI_CCR_ABSIZE_Pos) /* 32bits alternate bytes */ #define QSPI_CCR_ABMODE_Pos 14 /* Alternate bytes·¢ËÍģʽ 00£ºÎÞalternate bytes 01£ºµ¥Ïß 10£ºË«Ïß 11£ºËÄÏß */ #define QSPI_CCR_ABMODE_Msk (0x3U << QSPI_CCR_ABMODE_Pos) #define QSPI_CCR_ABMODE_NONE (0x0U << QSPI_CCR_ABMODE_Pos) /* ÎÞalternate bytes */ #define QSPI_CCR_ABMODE_SINGLE (0x1U << QSPI_CCR_ABMODE_Pos) /* µ¥Ïß */ #define QSPI_CCR_ABMODE_DOUBLE (0x2U << QSPI_CCR_ABMODE_Pos) /* Ë«Ïß */ #define QSPI_CCR_ABMODE_FOUR (0x3U << QSPI_CCR_ABMODE_Pos) /* ËÄÏß */ #define QSPI_CCR_ADSIZE_Pos 12 /* µØÖ·×Ö½Ú³¤¶È 00£º8bitsµØÖ· 01£º16bitsµØÖ· 10£º24bitsµØÖ· 11£º32bitsµØÖ· */ #define QSPI_CCR_ADSIZE_Msk (0x3U << QSPI_CCR_ADSIZE_Pos) #define QSPI_CCR_ADSIZE_8BITS (0x0U << QSPI_CCR_ADSIZE_Pos) /* 8bitsµØÖ· */ #define QSPI_CCR_ADSIZE_16BITS (0x1U << QSPI_CCR_ADSIZE_Pos) /* 16bitsµØÖ· */ #define QSPI_CCR_ADSIZE_24BITS (0x2U << QSPI_CCR_ADSIZE_Pos) /* 24bitsµØÖ· */ #define QSPI_CCR_ADSIZE_32BITS (0x3U << QSPI_CCR_ADSIZE_Pos) /* 32bitsµØÖ· */ #define QSPI_CCR_ADMODE_Pos 10 /* µØÖ·×Ö½Ú·¢ËÍģʽ 00£ºÎÞµØÖ·×Ö½Ú 01£ºµ¥Ïß 10£ºË«Ïß 11£ºËÄÏß */ #define QSPI_CCR_ADMODE_Msk (0x3U << QSPI_CCR_ADMODE_Pos) #define QSPI_CCR_ADMODE_NONE (0x0U << QSPI_CCR_ADMODE_Pos) /* ÎÞµØÖ·×Ö½Ú */ #define QSPI_CCR_ADMODE_SINGLE (0x1U << QSPI_CCR_ADMODE_Pos) /* µ¥Ïß */ #define QSPI_CCR_ADMODE_DOUBLE (0x2U << QSPI_CCR_ADMODE_Pos) /* Ë«Ïß */ #define QSPI_CCR_ADMODE_FOUR (0x3U << QSPI_CCR_ADMODE_Pos) /* ËÄÏß */ #define QSPI_CCR_IMODE_Pos 8 /* Ö¸Áî·¢ËÍģʽ 00£ºÎÞÖ¸Áî×Ö½Ú 01£ºµ¥Ïß 10£ºË«Ïß 11£ºËÄÏß */ #define QSPI_CCR_IMODE_Msk (0x3U << QSPI_CCR_IMODE_Pos) #define QSPI_CCR_IMODE_NONE (0x0U << QSPI_CCR_IMODE_Pos) /* ÎÞÖ¸Áî×Ö½Ú */ #define QSPI_CCR_IMODE_SINGLE (0x1U << QSPI_CCR_IMODE_Pos) /* µ¥Ïß */ #define QSPI_CCR_IMODE_DOUBLE (0x2U << QSPI_CCR_IMODE_Pos) /* Ë«Ïß */ #define QSPI_CCR_IMODE_FOUR (0x3U << QSPI_CCR_IMODE_Pos) /* ËÄÏß */ #define QSPI_CCR_INSTRUCTION_Pos 0 /* QuadSPI·¢Ë͵ÄÖ¸Áî×Ö½Ú */ #define QSPI_CCR_INSTRUCTION_Msk (0xffU << QSPI_CCR_INSTRUCTION_Pos) #define QSPI_ADDR_QSPI_ADDR_Pos 0 /* ·¢Ë͸øQSPI´æ´¢Æ÷µÄµØÖ·£¬ÔÚ´æ´¢Æ÷Ó³ÉäģʽÏÂÎÞЧ */ #define QSPI_ADDR_QSPI_ADDR_Msk (0xffffffffU << QSPI_ADDR_QSPI_ADDR_Pos) #define QSPI_ABR_QSPI_ABR_Pos 0 /* ·¢Ë͸øQSPI´æ´¢Æ÷µÄalternate bytes */ #define QSPI_ABR_QSPI_ABR_Msk (0xffffffffU << QSPI_ABR_QSPI_ABR_Pos) #define QSPI_DR_QSPI_DATA_Pos 0 /* QSPIÊý¾Ý¼Ä´æÆ÷ ÍâÉèģʽд²Ù×÷ʱ£¬¶ÔQSPI_DR¼Ä´æÆ÷дÈëµÄÊý¾Ý½«±»push FIFO£¬Ö§³Ö×Ö½Ú¡¢°ë×Ö¡¢×ÖдÈ룬·Ö±ð¶ÔFIFOѹÈë1¡¢2¡¢4×Ö½Ú£»Èç¹ûдÈë×Ö½ÚÊý´óÓÚFIFOÖпÕ×Ö½ÚÊý£¬µ±Ç°Ð´²Ù×÷±»¹ÒÆð£¬Ö±µ½FIFOÖÐÓÐ×ã¹»¿Õ¼äÈÝÄɵ±Ç°Ð´ÈëÊý¾Ý¡£ ÍâÉèģʽ¶Á²Ù×÷ʱ£¬¶ÁÈ¡QSPI_DR¼Ä´æÆ÷½«pop FIFO£¬Ö§³Ö×Ö½Ú¡¢°ë×Ö¡¢×Ö¶ÁÈ¡£¬·Ö±ð´ÓFIFOµ¯³ö1¡¢2¡¢4×Ö½Ú£»Èç¹û¶ÁÈ¡×Ö½ÚÊý´óÓÚFIFOÖÐÓÐЧ×Ö½ÚÊý£¬µ±Ç°¶Á²Ù×÷±»¹ÒÆð£¬Ö±µ½FIFOÖÐÓÐ×ã¹»×Ö½Ú¿ÉÒÔ±»¶ÁÈ¡£¬»òÕß´«ÊäÍê³É£¬ºóÒ»ÖÖÇé¿öÏÂÖ»µ¯³ö×îºó¼¸¸öʵ¼ÊÓÐЧ×Ö½Ú¡£ ¶ÔQSPI_DRµÄ·ÃÎʱØÐë¶ÔÆëµÍµØÖ·£¬¼´×Ö½Ú·ÃÎʱØÐë¶ÔÆëQSPI_DR[7:0]£¬°ë×Ö·ÃÎʱØÐë¶ÔÆëQSPI_DR[15:0] */ #define QSPI_DR_QSPI_DATA_Msk (0xffffffffU << QSPI_DR_QSPI_DATA_Pos) #define QSPI_SMSK_QSPI_SMSK_Pos 0 /* ×Ô¶¯×´Ì¬²éѯģʽϵÄ״̬mask¼Ä´æÆ÷£¬¶ÔÓ¦bitд0ÆÁ±ÎÏàӦ״̬λ */ #define QSPI_SMSK_QSPI_SMSK_Msk (0xffffffffU << QSPI_SMSK_QSPI_SMSK_Pos) #define QSPI_SMAT_QSPI_SMAT_Pos 0 /* ×Ô¶¯×´Ì¬²éѯģʽϵÄ״̬ƥÅä¼Ä´æÆ÷ ±È½Ï¶ÔÏóÊÇQSPI_DATA & QSPI_SMSK */ #define QSPI_SMAT_QSPI_SMAT_Msk (0xffffffffU << QSPI_SMAT_QSPI_SMAT_Pos) #define QSPI_PITV_QSPI_PITV_Pos 0 /* ×Ô¶¯×´Ì¬²éѯģʽϵÄÂÖѯ¼ä¸ô£¨polling interval£©£¬¶¨ÒåΪQSPI_CLKÖÜÆÚÊý */ #define QSPI_PITV_QSPI_PITV_Msk (0xffffU << QSPI_PITV_QSPI_PITV_Pos) #define QSPI_TO_QSPI_TO_Pos 0 /* ³¬Ê±ÖÜÆÚÉèÖ㬶¨ÒåΪQSPI_CLKÖÜÆÚÊý£¬½öÔÚ´æ´¢Æ÷Ó³ÉäģʽÏÂÓÐЧ µ±FIFOÂúÖ®ºó£¬QSPI×ÜÏßÐÐΪֹͣ£¬³¬Ê±¼ÆÊýÆ÷¿ªÊ¼¼ÆÊý£¬¼ÆÊýÖµµ½´ïQSPI_TOÉ趨ֵ֮ºó£¬À­¸ßnCS */ #define QSPI_TO_QSPI_TO_Msk (0xffffU << QSPI_TO_QSPI_TO_Pos) //Macro_End /* Exported functions --------------------------------------------------------*/ extern void QSPI_Deinit(void); extern void QSPI_CR_PRESCALER_Set(uint32_t SetValue); extern uint32_t QSPI_CR_PRESCALER_Get(void); /* ÂÖѯƥÅäģʽ 0£ºANDģʽ£¬ËùÓÐbit¶¼Æ¥Åä²ÅÖÃλSMF 1£ºORģʽ£¬ÖÁÉÙ1bitÆ¥Åä¾Í»áÖÃλSMF Ïà¹Øº¯Êý */ extern void QSPI_CR_PMM_Set(uint32_t SetValue); extern uint32_t QSPI_CR_PMM_Get(void); /* ³¬Ê±ÖжÏʹÄÜ 0£º½ûÖ¹³¬Ê±ÖÐ¶Ï 1£ºÔÊÐí³¬Ê±ÖÐ¶Ï Ïà¹Øº¯Êý */ extern void QSPI_CR_TOIE_Setable(FunState NewState); extern FunState QSPI_CR_TOIE_Getable(void); /* ״̬ƥÅäÖжÏʹÄÜ 0£º½ûֹ״̬ƥÅäÖÐ¶Ï 1£ºÔÊÐí״̬ƥÅäÖÐ¶Ï Ïà¹Øº¯Êý */ extern void QSPI_CR_SMIE_Setable(FunState NewState); extern FunState QSPI_CR_SMIE_Getable(void); /* FIFOˮλÖжÏʹÄÜ 0£º½ûÖ¹FIFOˮλÖÐ¶Ï 1£ºÔÊÐíFIFOˮλÖÐ¶Ï Ïà¹Øº¯Êý */ extern void QSPI_CR_FTIE_Setable(FunState NewState); extern FunState QSPI_CR_FTIE_Getable(void); /* ´«ÊäÍê³ÉÖжÏʹÄÜ 0£º½ûÖ¹´«ÊäÍê³ÉÖÐ¶Ï 1£ºÔÊÐí´«ÊäÍê³ÉÖÐ¶Ï Ïà¹Øº¯Êý */ extern void QSPI_CR_TCIE_Setable(FunState NewState); extern FunState QSPI_CR_TCIE_Getable(void); /* ´«Êä´íÎóÖжÏʹÄÜ 0£º½ûÖ¹´«Êä´íÎóÖÐ¶Ï 1£ºÔÊÐí´«Êä´íÎóÖÐ¶Ï Ïà¹Øº¯Êý */ extern void QSPI_CR_TEIE_Setable(FunState NewState); extern FunState QSPI_CR_TEIE_Getable(void); /* FIFOˮλ¼Ä´æÆ÷£¬½öÍâÉèģʽÏÂÆðЧ ÍâÉèдģʽ£º 0£ºFTFÔÚFIFO¿Õ×Ö½Ú´óÓÚµÈÓÚ1ʱÖÃλ 1£ºFTFÔÚFIFO¿Õ×Ö½Ú´óÓÚµÈÓÚ2ʱÖÃλ ¡­¡­ 15£ºFTFÔÚFIFO¿Õ×Ö½ÚµÈÓÚ16ʱÖÃλ ÍâÉè¶Áģʽ£º 0£ºFTFÔÚFIFOÖÐ×Ö½ÚÊý´óÓÚµÈÓÚ1ʱÖÃλ 1£ºFTFÔÚFIFOÖÐ×Ö½ÚÊý´óÓÚµÈÓÚ2ʱÖÃλ ¡­¡­ 15£ºFTFÔÚFIFOÖÐ×Ö½ÚÊýµÈÓÚ16ʱÖÃλ Ïà¹Øº¯Êý */ extern void QSPI_CR_FIFOTHR_Set(uint32_t SetValue); extern uint32_t QSPI_CR_FIFOTHR_Get(void); /* ÑÓ³Ù²ÉÑùʹÄÜ 0£º¹Ø±ÕÑÓ³Ù²ÉÑù¹¦ÄÜ 1£ºÊ¹ÄÜÑÓ³Ù²ÉÑù¹¦ÄÜ Ïà¹Øº¯Êý */ extern void QSPI_CR_SSHFT_Setable(FunState NewState); extern FunState QSPI_CR_SSHFT_Getable(void); /* ×ÜÏß³¬Ê±Ê¹ÄÜ£¬´Ë¼Ä´æÆ÷½öÔÚ´æ´¢Æ÷Ó³ÉäģʽÏÂÓÐЧ µ±BUSYÖÃλºó£¬Èç¹ûQuadSPI²»·¢Æð¶ÔQSPI´æ´¢Æ÷µÄ·ÃÎÊ£¬³¬Ê±¼Ä´æÆ÷¿ªÊ¼¼ÆÊý£¬¼ÆÊýÒç³ö³¤¶ÈÓÉTIMEOUT¼Ä´æÆ÷¶¨Òå¡£µ±QSPI×ÜÏß³¤Ê±¼äÎÞ¶¯×÷£¬¼ÆÊýÆ÷Òç³ö£¬nCS±»×Ô¶¯À­¸ß£¬Ç¿ÖƽáÊøµ±Ç°´«Êä¹ý³Ì¡£ 0£º¹Ø±Õ³¬Ê±¹¦ÄÜ 1£ºÊ¹Äܳ¬Ê±¹¦ÄÜ Ïà¹Øº¯Êý */ extern void QSPI_CR_TCEN_Setable(FunState NewState); extern FunState QSPI_CR_TCEN_Getable(void); /* DMAʹÄÜ 0£ºDMA¹¦Äܹرգ¬QuadSPI²»»á·¢ËÍDMAÇëÇó 1£ºDMA¹¦ÄÜ¿ªÆô£¬QuadSPIÔÚÂú×ãÌõ¼þʱ·¢ËÍDMAÇëÇó Ïà¹Øº¯Êý */ extern void QSPI_CR_DMAEN_Setable(FunState NewState); extern FunState QSPI_CR_DMAEN_Getable(void); /* µ±Ç°´«ÊäÖÕÖ¹¼Ä´æÆ÷£¬Èí¼þд1ÖÕÖ¹´«Ê䣬Ӳ¼þÀ­¸ßnCSºó×Ô¶¯ÇåÁã Ïà¹Øº¯Êý */ extern void QSPI_CR_ABORT_Setable(FunState NewState); extern FunState QSPI_CR_ABORT_Getable(void); /* QuadSPIÄ£¿éʹÄÜ 0£º¹Ø±ÕQuadSPI 1£ºÊ¹ÄÜQuadSPI Ïà¹Øº¯Êý */ extern void QSPI_CR_EN_Setable(FunState NewState); extern FunState QSPI_CR_EN_Getable(void); /* nCS×îС¸ßµçƽʱ¼ä£¬¶¨ÒåÁËÁ¬ÐøÁ½¸öÖ¡Ö®¼änCSËùÐè±£³Ö¸ßµçƽµÄ×î¶Ìʱ¼ä£¬ÒÔQSPI_CLKÖÜÆÚ¼ÆÊý 0£ºÖÁÉÙ1 cycle 1£ºÖÁÉÙ2 cycles ¡­¡­ 7£ºÖÁÉÙ8 cycles Ïà¹Øº¯Êý */ extern void QSPI_CFG_CSHT_Set(uint32_t SetValue); extern uint32_t QSPI_CFG_CSHT_Get(void); /* SPI Clock Mode¼Ä´æÆ÷ 0£ºmode 0 1£ºmode 3 Ïà¹Øº¯Êý */ extern void QSPI_CFG_CKMODE_Set(uint32_t SetValue); extern uint32_t QSPI_CFG_CKMODE_Get(void); /* FIFOˮλ±êÖ¾ ´Ë¼Ä´æÆ÷±íʾµ±Ç°FIFOÖб£´æµÄÊý¾Ý×Ö½ÚÊý£¬0±íʾFIFO¿Õ£¬16±íʾFIFOÂú ×Ô¶¯²éѯģʽÏ´˼ĴæÆ÷±£³Ö0 Ïà¹Øº¯Êý */ extern uint32_t QSPI_SR_FIFOLVL_Get(void); /* 1±íʾQuadSPI´«Êä½øÐÐÖУ¬Í¨ÐŽáÊøºó×Ô¶¯ÇåÁã Ïà¹Øº¯Êý */ extern FlagStatus QSPI_SR_BUSY_Chk(void); /* ³¬Ê±±êÖ¾£¬Ó²¼þÖÃ룬Èí¼þд1ÇåÁã Ïà¹Øº¯Êý */ extern void QSPI_SR_TOF_Clr(void); extern FlagStatus QSPI_SR_TOF_Chk(void); /* ×Ô¶¯²éѯģʽϱíÕ÷״̬¼Ä´æÆ÷Æ¥Åä³É¹¦£¬Ó²¼þÖÃ룬Èí¼þд1ÇåÁã Ïà¹Øº¯Êý */ extern void QSPI_SR_SMF_Clr(void); extern FlagStatus QSPI_SR_SMF_Chk(void); /* FIFO threshold±êÖ¾£¬FIFOˮλ¸ßÓÚÉ趨ãÐֵʱ×Ô¶¯ÖÃ룬µÍÓÚãÐֵʱ×Ô¶¯ÇåÁã ×Ô¶¯²éѯģʽÏ£¬Ã¿´Î¶Á»ØÒ»×é״ֵ̬ºó¶¼»á×Ô¶¯ÖÃλFTF£¬Èç¹ûÈí¼þ¶ÁÈ¡QSPI_DATA¼Ä´æÆ÷ÔòFTFÇåÁã Ïà¹Øº¯Êý */ extern FlagStatus QSPI_SR_FTF_Chk(void); /* ´«ÊäÍê³É±êÖ¾£¬Ó²¼þÖÃ룬Èí¼þд1ÇåÁã Ïà¹Øº¯Êý */ extern void QSPI_SR_TCF_Clr(void); extern FlagStatus QSPI_SR_TCF_Chk(void); /* ´«ÊäÊý¾Ý³¤¶ÈΪDATALEN+1£¨bytes£© Ïà¹Øº¯Êý */ extern void QSPI_DATALEN_Write(uint32_t SetValue); extern uint32_t QSPI_DATALEN_Read(void); /* QuadSPI ͨÐÅ¿ØÖƼĴæÆ÷ Ïà¹Øº¯Êý */ #define QSPI_CCR_DUMCYC_SET(value) ((value << QSPI_CCR_DUMCYC_Pos) & QSPI_CCR_DUMCYC_Msk) #define QSPI_CCR_DUMCYC_GET(value) ((value >> QSPI_CCR_DUMCYC_Pos) & QSPI_CCR_DUMCYC_Msk) #define QSPI_CCR_INSTRUCTION_SET(value) ((value << QSPI_CCR_INSTRUCTION_Pos) & QSPI_CCR_INSTRUCTION_Msk) #define QSPI_CCR_INSTRUCTION_GET(value) ((value >> QSPI_CCR_INSTRUCTION_Pos) & QSPI_CCR_INSTRUCTION_Msk) extern void QSPI_CCR_Write(uint32_t SetValue); extern uint32_t QSPI_CCR_Read(void); /* ·¢Ë͸øQSPI´æ´¢Æ÷µÄµØÖ·£¬ÔÚ´æ´¢Æ÷Ó³ÉäģʽÏÂÎÞЧ Ïà¹Øº¯Êý */ extern void QSPI_ADDR_Write(uint32_t SetValue); extern uint32_t QSPI_ADDR_Read(void); /* ·¢Ë͸øQSPI´æ´¢Æ÷µÄalternate bytes Ïà¹Øº¯Êý */ extern void QSPI_ABR_Write(uint32_t SetValue); extern uint32_t QSPI_ABR_Read(void); /* QSPIÊý¾Ý¼Ä´æÆ÷ ÍâÉèģʽд²Ù×÷ʱ£¬¶ÔQSPI_DR¼Ä´æÆ÷дÈëµÄÊý¾Ý½«±»push FIFO£¬Ö§³Ö×Ö½Ú¡¢°ë×Ö¡¢×ÖдÈ룬·Ö±ð¶ÔFIFOѹÈë1¡¢2¡¢4×Ö½Ú£»Èç¹ûдÈë×Ö½ÚÊý´óÓÚFIFOÖпÕ×Ö½ÚÊý£¬µ±Ç°Ð´²Ù×÷±»¹ÒÆð£¬Ö±µ½FIFOÖÐÓÐ×ã¹»¿Õ¼äÈÝÄɵ±Ç°Ð´ÈëÊý¾Ý¡£ ÍâÉèģʽ¶Á²Ù×÷ʱ£¬¶ÁÈ¡QSPI_DR¼Ä´æÆ÷½«pop FIFO£¬Ö§³Ö×Ö½Ú¡¢°ë×Ö¡¢×Ö¶ÁÈ¡£¬·Ö±ð´ÓFIFOµ¯³ö1¡¢2¡¢4×Ö½Ú£»Èç¹û¶ÁÈ¡×Ö½ÚÊý´óÓÚFIFOÖÐÓÐЧ×Ö½ÚÊý£¬µ±Ç°¶Á²Ù×÷±»¹ÒÆð£¬Ö±µ½FIFOÖÐÓÐ×ã¹»×Ö½Ú¿ÉÒÔ±»¶ÁÈ¡£¬»òÕß´«ÊäÍê³É£¬ºóÒ»ÖÖÇé¿öÏÂÖ»µ¯³ö×îºó¼¸¸öʵ¼ÊÓÐЧ×Ö½Ú¡£ ¶ÔQSPI_DRµÄ·ÃÎʱØÐë¶ÔÆëµÍµØÖ·£¬¼´×Ö½Ú·ÃÎʱØÐë¶ÔÆëQSPI_DR[7:0]£¬°ë×Ö·ÃÎʱØÐë¶ÔÆëQSPI_DR[15:0] Ïà¹Øº¯Êý */ extern void QSPI_DR_WriteByte(uint8_t SetValue); extern uint8_t QSPI_DR_ReadByte(void); extern void QSPI_DR_WriteHalfword(uint16_t SetValue); extern uint16_t QSPI_DR_ReadHalfword(void); extern void QSPI_DR_WriteWord(uint32_t SetValue); extern uint32_t QSPI_DR_ReadWord(void); /* ×Ô¶¯×´Ì¬²éѯģʽϵÄ״̬mask¼Ä´æÆ÷£¬¶ÔÓ¦bitд0ÆÁ±ÎÏàӦ״̬λ Ïà¹Øº¯Êý */ extern void QSPI_SMSK_Write(uint32_t SetValue); extern uint32_t QSPI_SMSK_Read(void); /* ×Ô¶¯×´Ì¬²éѯģʽϵÄ״̬ƥÅä¼Ä´æÆ÷ ±È½Ï¶ÔÏóÊÇQSPI_DATA & QSPI_SMSK Ïà¹Øº¯Êý */ extern void QSPI_SMAT_Write(uint32_t SetValue); extern uint32_t QSPI_SMAT_Read(void); /* ×Ô¶¯×´Ì¬²éѯģʽϵÄÂÖѯ¼ä¸ô£¨polling interval£©£¬¶¨ÒåΪQSPI_CLKÖÜÆÚÊý Ïà¹Øº¯Êý */ extern void QSPI_PITV_Write(uint32_t SetValue); extern uint32_t QSPI_PITV_Read(void); /* ³¬Ê±ÖÜÆÚÉèÖ㬶¨ÒåΪQSPI_CLKÖÜÆÚÊý£¬½öÔÚ´æ´¢Æ÷Ó³ÉäģʽÏÂÓÐЧ µ±FIFOÂúÖ®ºó£¬QSPI×ÜÏßÐÐΪֹͣ£¬³¬Ê±¼ÆÊýÆ÷¿ªÊ¼¼ÆÊý£¬¼ÆÊýÖµµ½´ïQSPI_TOÉ趨ֵ֮ºó£¬À­¸ßnCS Ïà¹Øº¯Êý */ extern void QSPI_TO_Write(uint32_t SetValue); extern uint32_t QSPI_TO_Read(void); //Announce_End void QSPI_Deinit(void); void QSPI_Init(void); #ifdef __cplusplus } #endif #endif /* __FM33A0XXEV_QSPI_H */