#include "ir_nec.h"
#include "gpio.h"
#include "uart.h"
#include "upper_computer.h"

/*ÓÉÓÚFM33A0ûÓд®¿Ú¿ÕÏÐÖжϣ¬ËùÒÔÀûÓÃDMA¼Ä´æÆ÷Ö¸Õë²»Òƶ¯À´Åж¨ÊÇ·ñ½ÓÊÕÍê³É*/
ErrorStatus_STM32 IR_Uart5_Rx_DMA_CH5_Check(void)
{
  uint16_t timeout_cnt = 0, dma_recv_cnt;
  uint32_t dma_mar_reg_read = DMA_CHxMAR_Read(DMA_CH5);

  if (dma_mar_reg_read != (uint32)uc_recv_para_g.uc_recv_buf_union.uc_recv_buf)
  {
    delay_ms(2);
    while (dma_mar_reg_read != DMA_CHxMAR_Read(DMA_CH5))
    {
      dma_mar_reg_read = DMA_CHxMAR_Read(DMA_CH5);
      delay_ms(2);
      if (timeout_cnt++ > 100)
        break;
    }
  }
  else
    return ERROR_1;

  dma_recv_cnt = dma_mar_reg_read - (uint32)uc_recv_para_g.uc_recv_buf_union.uc_recv_buf;
  if (dma_recv_cnt)
  {
    uc_recv_para_g.uc_recv_length = dma_recv_cnt;
    // ½ÓÊÕRAMµØÖ·ÖØÔØ
    DMA_ISR_DMACHFT_Clr(DMA_CH5);
    DMA_CHxCR_ChxEN_Setable(DMA_CH5, DISABLE); // ͨµÀʧÄÜ

    DMA_CHxMAR_Write(DMA_CH5, (uint32)uc_recv_para_g.uc_recv_buf_union.uc_recv_buf);

    DMA_CHxCR_ChxEN_Setable(DMA_CH5, ENABLE); // ͨµÀʹÄÜ
    uc_recv_para_g.uc_recv_flag = SET;        // ½ÓÊÕÍê³É
    return SUCCESS_0;
    //		DMA_GCR_DMAEN_Setable(DISABLE);//DMA×ÜʹÄÜ
  }
  return ERROR_1;
}