/**
  ******************************************************************************
  * @file    fm33a0xxev_pmu.h
  * @author  FM33A0XXEV Application Team
  * @version V1.0.0
  * @date    16-April-2020
  * @brief   This file contains all the functions prototypes for the PMU firmware library.  
  ******************************************************************************
  */
  
/* Define to prevent recursive inclusion -------------------------------------*/

#ifndef __FM33A0XXEV_PMU_H
#define __FM33A0XXEV_PMU_H


#ifdef __cplusplus
 extern "C" {
#endif

/* Includes ------------------------------------------------------------------*/
#include "FM33A0XXEV.h"
typedef struct
{
	uint32_t PMOD;				/*!<µÍ¹¦ºÄģʽÅäÖà  */	
	uint32_t SLPDP;				/*!<DeepSleep¿ØÖƼĴæÆ÷  */
	FunState CVS;				/*!<Äں˵çѹ½µµÍʹÄÜ¿ØÖÆ  */
	uint32_t SCR;				/*!<M0ϵͳ¿ØÖƼĴæÆ÷£¬Ò»°ãÅäÖÃΪ0¼´¿É  */	
	uint32_t TIA;				/*!¿É±à³Ì¶îÍ⻽ÐÑÑÓ³Ù */	
}PMU_SleepCfg_InitTypeDef;
   
#define	PMU_CR_LDO15EN_Pos	17	/* LDO15ʹÄܱê־λ
1£ºLDO15´¦ÓÚ¹¤×÷״̬
0£ºLDO15±»¹Ø±Õ */
#define	PMU_CR_LDO15EN_Msk	(0x1U << PMU_CR_LDO15EN_Pos)

#define	PMU_CR_LDO15EN_B_Pos	16	/* LDO15ʹÄܱêÖ¾·´ÂëУÑéλ */
#define	PMU_CR_LDO15EN_B_Msk	(0x1U << PMU_CR_LDO15EN_B_Pos)

#define	PMU_CR_WKFSEL_Pos	10	/* Sleep/DeepSleep»½ÐѺóµÄϵͳƵÂÊ
00£ºRCHF-8MHz
01£ºRCHF-16MHz
10£ºRCHF-24MHz
11£ºRCHF-32MHz */
#define	PMU_CR_WKFSEL_Msk	(0x3U << PMU_CR_WKFSEL_Pos)
#define	PMU_CR_WKFSEL_RCHF_8M	(0x0U << PMU_CR_WKFSEL_Pos)	/* RCHF-8MHz */
#define	PMU_CR_WKFSEL_RCHF_16M	(0x1U << PMU_CR_WKFSEL_Pos)	/* RCHF-16MHz */
#define	PMU_CR_WKFSEL_RCHF_24M	(0x2U << PMU_CR_WKFSEL_Pos)	/* RCHF-24MHz */
#define	PMU_CR_WKFSEL_RCHF_32M	(0x3U << PMU_CR_WKFSEL_Pos)	/* RCHF-32MHz */

#define	PMU_CR_SLPDP_Pos	9	/* DeepSleep¿ØÖƼĴæÆ÷
1£ºDeepSleepģʽʹÄÜ£¬Ï¹رջù×¼µçѹԴ
0£º³£¹æSleepģʽ
ÔÚSleepÏ£¬Èç¹ûÖÃλÁËSLPDPλ¼´ÎªDeepSleepģʽ£»
¸Ãλ½öÔÚSleepÏÂÓÐЧ */
#define	PMU_CR_SLPDP_Msk	(0x1U << PMU_CR_SLPDP_Pos)
#define	PMU_CR_SLPDP_DEEPSLEEP	(0x1U << PMU_CR_SLPDP_Pos)	/* DeepSleepģʽʹÄÜ£¬Ï¹رջù×¼µçѹԴ */
#define	PMU_CR_SLPDP_SLEEP	(0x0U << PMU_CR_SLPDP_Pos)	/* ³£¹æSleepģʽ */

#define	PMU_CR_CVS_Pos	8	/* CoreVoltageScalingÅäÖÃ
0£ºµÍ¹¦ºÄģʽϲ»Ê¹ÄÜÄں˵çѹµ÷Õû
1£ºµÍ¹¦ºÄģʽϽµµÍÄں˵çѹ
¸Ãλ½öÔÚSleep/DeepSleep/RTCBKPģʽÏÂÆð×÷Óà */
#define	PMU_CR_CVS_Msk	(0x1U << PMU_CR_CVS_Pos)
#define	PMU_CR_CVS_DISABLE	(0x0U << PMU_CR_CVS_Pos)	/* µÍ¹¦ºÄģʽϲ»Ê¹ÄÜÄں˵çѹµ÷Õû */
#define	PMU_CR_CVS_ENABLE	(0x1U << PMU_CR_CVS_Pos)	/* µÍ¹¦ºÄģʽϽµµÍÄں˵çѹ */

#define	PMU_CR_PMOD_Pos	0	/* µÍ¹¦ºÄģʽÅäÖüĴæÆ÷
00£ºActive mode / LP Active mode
01£ºLPRUN mode
10£ºSleep mode / DeepSleep mode
11£ºRTCBKP mode */
#define	PMU_CR_PMOD_Msk	(0x3U << PMU_CR_PMOD_Pos)
#define	PMU_CR_PMOD_ACTIVE	(0x0U << PMU_CR_PMOD_Pos)	/* Active mode / LP Active mode */
#define	PMU_CR_PMOD_LPRUN 	(0x1U << PMU_CR_PMOD_Pos)	/* LPRUN mode */
#define	PMU_CR_PMOD_SLEEP	(0x2U << PMU_CR_PMOD_Pos)	/* Sleep mode / DeepSleep mode */

#define	PMU_WKTR_STPCLR_Pos	2	/* Flash Stop»½ÐÑ¿ØÖÆ
0£ºStopÐźŵȴýʱÖÓ½¨Á¢ºóͬ²½ÇåÁã
1£ºStopÐźÅÒì²½ÇåÁã */
#define	PMU_WKTR_STPCLR_Msk	(0x1U << PMU_WKTR_STPCLR_Pos)
#define	PMU_WKTR_STPCLR_SYN	(0x0U << PMU_WKTR_STPCLR_Pos)	/* StopÐźŵȴýʱÖÓ½¨Á¢ºóͬ²½ÇåÁã */
#define	PMU_WKTR_STPCLR_ASY	(0x1U << PMU_WKTR_STPCLR_Pos)	/* StopÐźÅÒì²½ÇåÁã */

#define	PMU_WKTR_T1A_Pos	0	/* ¿É±à³Ì¶îÍ⻽ÐÑÑÓ³Ù
ÔÚDeepSleepģʽÏ£¬RCHFʱÖÓµ½À´ºó£¬¸ù¾Ý´Ë¼Ä´æÆ÷ÅäÖõȴý¶îÍâÑÓ³Ùʱ¼äºó£¬ÔÙ¶ÁÈ¡FlashУÑé×Ö
00£º0us
01£º2us
10£º4us
11£º8us */
#define	PMU_WKTR_T1A_Msk	(0x3U << PMU_WKTR_T1A_Pos)
#define	PMU_WKTR_T1A_0US	(0x0U << PMU_WKTR_T1A_Pos)	/* 0us */
#define	PMU_WKTR_T1A_2US	(0x1U << PMU_WKTR_T1A_Pos)	/* 2us */
#define	PMU_WKTR_T1A_4US	(0x2U << PMU_WKTR_T1A_Pos)	/* 4us */
#define	PMU_WKTR_T1A_8US	(0x3U << PMU_WKTR_T1A_Pos)	/* 8us */

#define	PMU_WKFR_ADCWKF_Pos	31	/* ADCÖжϻ½ÐѱêÖ¾£¬Öжϳ·ÏúʱӲ¼þ×Ô¶¯ÇåÁã */
#define	PMU_WKFR_ADCWKF_Msk	(0x1U << PMU_WKFR_ADCWKF_Pos)

#define	PMU_WKFR_RTCWKF_Pos	28	/* RTCÖжϻ½ÐѱêÖ¾£¬Öжϳ·ÏúʱӲ¼þ×Ô¶¯ÇåÁã */
#define	PMU_WKFR_RTCWKF_Msk	(0x1U << PMU_WKFR_RTCWKF_Pos)

#define	PMU_WKFR_SVDWKF_Pos	27	/* SVDÖжϻ½ÐѱêÖ¾£¬Öжϳ·ÏúʱӲ¼þ×Ô¶¯ÇåÁã */
#define	PMU_WKFR_SVDWKF_Msk	(0x1U << PMU_WKFR_SVDWKF_Pos)

#define	PMU_WKFR_LFDETWKF_Pos	26	/* 32768Hz¾§ÌåÍ£ÕñÖжϻ½ÐѱêÖ¾£¬Öжϳ·ÏúʱӲ¼þ×Ô¶¯ÇåÁã */
#define	PMU_WKFR_LFDETWKF_Msk	(0x1U << PMU_WKFR_LFDETWKF_Pos)

#define	PMU_WKFR_IOWKF_Pos	24	/* IOÖжϻ½ÐѱêÖ¾£¬Öжϳ·ÏúʱӲ¼þ×Ô¶¯ÇåÁã */
#define	PMU_WKFR_IOWKF_Msk	(0x1U << PMU_WKFR_IOWKF_Pos)

#define	PMU_WKFR_LPU1WKF_Pos	21	/* LPUART1Öжϻ½ÐѱêÖ¾£¬Öжϳ·ÏúʱӲ¼þ×Ô¶¯ÇåÁã */
#define	PMU_WKFR_LPU1WKF_Msk	(0x1U << PMU_WKFR_LPU1WKF_Pos)

#define	PMU_WKFR_LPU0WKF_Pos	20	/* LPUART0Öжϻ½ÐѱêÖ¾£¬Öжϳ·ÏúʱӲ¼þ×Ô¶¯ÇåÁã */
#define	PMU_WKFR_LPU0WKF_Msk	(0x1U << PMU_WKFR_LPU0WKF_Pos)

#define	PMU_WKFR_COMP_OOWF_Pos	19	/* ±È½ÏÆ÷out-of-window»½ÐѱêÖ¾£¬Öжϳ·ÏúʱӲ¼þ×Ô¶¯ÇåÁã */
#define	PMU_WKFR_COMP_OOWF_Msk	(0x1U << PMU_WKFR_COMP_OOWF_Pos)

#define	PMU_WKFR_COMP_WINF_Pos	18	/* ±È½ÏÆ÷window»½ÐѱêÖ¾£¬Öжϳ·ÏúʱӲ¼þ×Ô¶¯ÇåÁã */
#define	PMU_WKFR_COMP_WINF_Msk	(0x1U << PMU_WKFR_COMP_WINF_Pos)

#define	PMU_WKFR_COMP2WKF_Pos	17	/* ±È½ÏÆ÷2Öжϻ½ÐѱêÖ¾£¬Öжϳ·ÏúʱӲ¼þ×Ô¶¯ÇåÁã */
#define	PMU_WKFR_COMP2WKF_Msk	(0x1U << PMU_WKFR_COMP2WKF_Pos)

#define	PMU_WKFR_COMP1WKF_Pos	16	/* ±È½ÏÆ÷1Öжϻ½ÐѱêÖ¾£¬Öжϳ·ÏúʱӲ¼þ×Ô¶¯ÇåÁã */
#define	PMU_WKFR_COMP1WKF_Msk	(0x1U << PMU_WKFR_COMP1WKF_Pos)

#define	PMU_WKFR_LPTWKF_Pos	10	/*  _32Öжϻ½ÐѱêÖ¾£¬Öжϳ·ÏúʱӲ¼þ×Ô¶¯ÇåÁã */
#define	PMU_WKFR_LPTWKF_Msk	(0x1U << PMU_WKFR_LPTWKF_Pos)

#define	PMU_WKFR_BSTWKF_Pos	9	/* BSTIM32Öжϻ½ÐѱêÖ¾£¬Öжϳ·ÏúʱӲ¼þ×Ô¶¯ÇåÁã */
#define	PMU_WKFR_BSTWKF_Msk	(0x1U << PMU_WKFR_BSTWKF_Pos)

#define	PMU_WKFR_DBGWKF_Pos	8	/* CPU Debugger»½ÐѱêÖ¾£¬Èí¼þд1ÇåÁã */
#define	PMU_WKFR_DBGWKF_Msk	(0x1U << PMU_WKFR_DBGWKF_Pos)


#define	PMU_IER_SLPEIE_Pos	1	/* SLEEP´íÎóÖжÏʹÄÜ (Sleep mode Error Interrupt Enable)
1£ºÊ¹ÄÜSLEEP´íÎóÖжÏ
0£º½ûÖ¹SLEEP´íÎóÖÐ¶Ï */
#define	PMU_IER_SLPEIE_Msk	(0x1U << PMU_IER_SLPEIE_Pos)
	/* ʹÄÜSLEEP´íÎóÖÐ¶Ï */
	/* ½ûÖ¹SLEEP´íÎóÖÐ¶Ï */

#define	PMU_IER_RTCEIE_Pos	0	/* RTCBKP´íÎóÖжÏʹÄÜ(RTCBKP mode Error Interrupt Enable)
1£ºÊ¹ÄÜRTCBKP´íÎóÖжÏ
0£º½ûÖ¹RTCBKP´íÎóÖÐ¶Ï */
#define	PMU_IER_RTCEIE_Msk	(0x1U << PMU_IER_RTCEIE_Pos)
	/* ʹÄÜRTCBKP´íÎóÖÐ¶Ï */
	/* ½ûÖ¹RTCBKP´íÎóÖÐ¶Ï */

#define	PMU_ISR_SLPEIF_Pos	1	/* SLEEP´íÎóÖжϱêÖ¾£¬Ó²¼þÖÃ룬Èí¼þд1ÇåÁã (Sleep Error Interrupt Flag, write 1 to clear)
1£ºÔÚPMOD=2¡¯h2ºó£¬CPUÖ´ÐÐWFI/WFEÖ¸ÁîÇ°ÖÃλÁËSLEEPDEEP¼Ä´æÆ÷ʱÖÃλ
0£ºÔÚPMOD=2¡¯h2ºó£¬CPUÕýÈ·½øÈëSLEEP */
#define	PMU_ISR_SLPEIF_Msk	(0x1U << PMU_ISR_SLPEIF_Pos)

#define	PMU_ISR_RTCEIF_Pos	0	/* RTCBKP´íÎóÖжϱêÖ¾£¬Ó²¼þÖÃ룬Èí¼þд1ÇåÁã(RTC Error Interrupt Flag, write 1 to clear)
1£ºÔÚPMOD=2¡¯h3ºó£¬Î´¸ÄдCPUÄÚ²¿¼Ä´æÆ÷SLEEPDEEP=1£¬È»ºóÖ´ÐÐWFI/WFEÖ¸Á»òÕßϵͳʱÖÓÀ´×ÔUSB PHY£¬ÊÔͼ½øÈëRTCBKPģʽ
0£ºÔÚPMOD=2¡¯h3ºó£¬CPU×ÔÉíÕýÈ·½øÈëDEEP SLEEP */
#define	PMU_ISR_RTCEIF_Msk	(0x1U << PMU_ISR_RTCEIF_Pos)
//Macro_End

/* Exported functions --------------------------------------------------------*/ 
extern void PMU_Deinit(void);

/* LDO15ʹÄܱê־λ
1£ºLDO15´¦ÓÚ¹¤×÷״̬
0£ºLDO15±»¹Ø±Õ Ïà¹Øº¯Êý */
extern FlagStatus PMU_CR_LDO15EN_Chk(void);

/* LDO15ʹÄܱêÖ¾·´ÂëУÑéλ Ïà¹Øº¯Êý */
extern FlagStatus PMU_CR_LDO15EN_B_Chk(void);

/* Sleep/DeepSleep»½ÐѺóµÄϵͳƵÂÊ
00£ºRCHF-8MHz
01£ºRCHF-16MHz
10£ºRCHF-24MHz
11£ºRCHF-32MHz Ïà¹Øº¯Êý */
extern void PMU_CR_WKFSEL_Set(uint32_t SetValue);
extern uint32_t PMU_CR_WKFSEL_Get(void);

/* DeepSleep¿ØÖƼĴæÆ÷
1£ºDeepSleepģʽʹÄÜ£¬Ï¹رջù×¼µçѹԴ
0£º³£¹æSleepģʽ
ÔÚSleepÏ£¬Èç¹ûÖÃλÁËSLPDPλ¼´ÎªDeepSleepģʽ£»
¸Ãλ½öÔÚSleepÏÂÓÐЧ Ïà¹Øº¯Êý */
extern void PMU_CR_SLPDP_Set(uint32_t SetValue);
extern uint32_t PMU_CR_SLPDP_Get(void);

/* CoreVoltageScalingÅäÖÃ
0£ºµÍ¹¦ºÄģʽϲ»Ê¹ÄÜÄں˵çѹµ÷Õû
1£ºµÍ¹¦ºÄģʽϽµµÍÄں˵çѹ
¸Ãλ½öÔÚSleep/DeepSleep/RTCBKPģʽÏÂÆð×÷Óà Ïà¹Øº¯Êý */
extern void PMU_CR_CVS_Set(uint32_t SetValue);
extern uint32_t PMU_CR_CVS_Get(void);

/* µÍ¹¦ºÄģʽÅäÖüĴæÆ÷
00£ºActive mode / LP Active mode
01£ºLPRUN mode
10£ºSleep mode / DeepSleep mode
11£ºRTCBKP mode Ïà¹Øº¯Êý */
extern void PMU_CR_PMOD_Set(uint32_t SetValue);
extern uint32_t PMU_CR_PMOD_Get(void);

/* Flash Stop»½ÐÑ¿ØÖÆ
0£ºStopÐźŵȴýʱÖÓ½¨Á¢ºóͬ²½ÇåÁã
1£ºStopÐźÅÒì²½ÇåÁã Ïà¹Øº¯Êý */
extern void PMU_WKTR_STPCLR_Set(uint32_t SetValue);
extern uint32_t PMU_WKTR_STPCLR_Get(void);

/* ¿É±à³Ì¶îÍ⻽ÐÑÑÓ³Ù
ÔÚDeepSleepģʽÏ£¬RCHFʱÖÓµ½À´ºó£¬¸ù¾Ý´Ë¼Ä´æÆ÷ÅäÖõȴý¶îÍâÑÓ³Ùʱ¼äºó£¬ÔÙ¶ÁÈ¡FlashУÑé×Ö
00£º0us
01£º2us
10£º4us
11£º8us Ïà¹Øº¯Êý */
extern void PMU_WKTR_T1A_Set(uint32_t SetValue);
extern uint32_t PMU_WKTR_T1A_Get(void);

/* ADCÖжϻ½ÐѱêÖ¾£¬Öжϳ·ÏúʱӲ¼þ×Ô¶¯ÇåÁã Ïà¹Øº¯Êý */
extern FlagStatus PMU_WKFR_ADCWKF_Chk(void);

/* RTCÖжϻ½ÐѱêÖ¾£¬Öжϳ·ÏúʱӲ¼þ×Ô¶¯ÇåÁã Ïà¹Øº¯Êý */
extern FlagStatus PMU_WKFR_RTCWKF_Chk(void);

/* SVDÖжϻ½ÐѱêÖ¾£¬Öжϳ·ÏúʱӲ¼þ×Ô¶¯ÇåÁã Ïà¹Øº¯Êý */
extern FlagStatus PMU_WKFR_SVDWKF_Chk(void);

/* 32768Hz¾§ÌåÍ£ÕñÖжϻ½ÐѱêÖ¾£¬Öжϳ·ÏúʱӲ¼þ×Ô¶¯ÇåÁã Ïà¹Øº¯Êý */
extern FlagStatus PMU_WKFR_LFDETWKF_Chk(void);

/* IOÖжϻ½ÐѱêÖ¾£¬Öжϳ·ÏúʱӲ¼þ×Ô¶¯ÇåÁã Ïà¹Øº¯Êý */
extern FlagStatus PMU_WKFR_IOWKF_Chk(void);

/* LPUART1Öжϻ½ÐѱêÖ¾£¬Öжϳ·ÏúʱӲ¼þ×Ô¶¯ÇåÁã Ïà¹Øº¯Êý */
extern FlagStatus PMU_WKFR_LPU1WKF_Chk(void);

/* LPUART0Öжϻ½ÐѱêÖ¾£¬Öжϳ·ÏúʱӲ¼þ×Ô¶¯ÇåÁã Ïà¹Øº¯Êý */
extern FlagStatus PMU_WKFR_LPU0WKF_Chk(void);

/* ±È½ÏÆ÷out-of-window»½ÐѱêÖ¾£¬Öжϳ·ÏúʱӲ¼þ×Ô¶¯ÇåÁã Ïà¹Øº¯Êý */
extern FlagStatus PMU_WKFR_COMP_OOWF_Chk(void);

/* ±È½ÏÆ÷window»½ÐѱêÖ¾£¬Öжϳ·ÏúʱӲ¼þ×Ô¶¯ÇåÁã Ïà¹Øº¯Êý */
extern FlagStatus PMU_WKFR_COMP_WINF_Chk(void);

/* ±È½ÏÆ÷2Öжϻ½ÐѱêÖ¾£¬Öжϳ·ÏúʱӲ¼þ×Ô¶¯ÇåÁã Ïà¹Øº¯Êý */
extern FlagStatus PMU_WKFR_COMP2WKF_Chk(void);

/* ±È½ÏÆ÷1Öжϻ½ÐѱêÖ¾£¬Öжϳ·ÏúʱӲ¼þ×Ô¶¯ÇåÁã Ïà¹Øº¯Êý */
extern FlagStatus PMU_WKFR_COMP1WKF_Chk(void);

/*  _32Öжϻ½ÐѱêÖ¾£¬Öжϳ·ÏúʱӲ¼þ×Ô¶¯ÇåÁã Ïà¹Øº¯Êý */
extern FlagStatus PMU_WKFR_LPTWKF_Chk(void);

/* BSTIM32Öжϻ½ÐѱêÖ¾£¬Öжϳ·ÏúʱӲ¼þ×Ô¶¯ÇåÁã Ïà¹Øº¯Êý */
extern FlagStatus PMU_WKFR_BSTWKF_Chk(void);

/* CPU Debugger»½ÐѱêÖ¾£¬Èí¼þд1ÇåÁã Ïà¹Øº¯Êý */
extern void PMU_WKFR_DBGWKF_Clr(void);
extern FlagStatus PMU_WKFR_DBGWKF_Chk(void);


/* SLEEP´íÎóÖжÏʹÄÜ (Sleep mode Error Interrupt Enable)
1£ºÊ¹ÄÜSLEEP´íÎóÖжÏ
0£º½ûÖ¹SLEEP´íÎóÖÐ¶Ï Ïà¹Øº¯Êý */
extern void PMU_IER_SLPEIE_Setable(FunState NewState);
extern FunState PMU_IER_SLPEIE_Getable(void);

/* RTCBKP´íÎóÖжÏʹÄÜ(RTCBKP mode Error Interrupt Enable)
1£ºÊ¹ÄÜRTCBKP´íÎóÖжÏ
0£º½ûÖ¹RTCBKP´íÎóÖÐ¶Ï Ïà¹Øº¯Êý */
extern void PMU_IER_RTCEIE_Setable(FunState NewState);
extern FunState PMU_IER_RTCEIE_Getable(void);

/* SLEEP´íÎóÖжϱêÖ¾£¬Ó²¼þÖÃ룬Èí¼þд1ÇåÁã (Sleep Error Interrupt Flag, write 1 to clear)
1£ºÔÚPMOD=2¡¯h2ºó£¬CPUÖ´ÐÐWFI/WFEÖ¸ÁîÇ°ÖÃλÁËSLEEPDEEP¼Ä´æÆ÷ʱÖÃλ
0£ºÔÚPMOD=2¡¯h2ºó£¬CPUÕýÈ·½øÈëSLEEP Ïà¹Øº¯Êý */
extern void PMU_ISR_SLPEIF_Clr(void);
extern FlagStatus PMU_ISR_SLPEIF_Chk(void);

/* RTCBKP´íÎóÖжϱêÖ¾£¬Ó²¼þÖÃ룬Èí¼þд1ÇåÁã(RTC Error Interrupt Flag, write 1 to clear)
1£ºÔÚPMOD=2¡¯h3ºó£¬Î´¸ÄдCPUÄÚ²¿¼Ä´æÆ÷SLEEPDEEP=1£¬È»ºóÖ´ÐÐWFI/WFEÖ¸Á»òÕßϵͳʱÖÓÀ´×ÔUSB PHY£¬ÊÔͼ½øÈëRTCBKPģʽ
0£ºÔÚPMOD=2¡¯h3ºó£¬CPU×ÔÉíÕýÈ·½øÈëDEEP SLEEP Ïà¹Øº¯Êý */
extern void PMU_ISR_RTCEIF_Clr(void);
extern FlagStatus PMU_ISR_RTCEIF_Chk(void);

extern void PMU_WKFR_WKPxF_Clr(uint32_t NWKPinDef);
extern FlagStatus PMU_WKFR_WKPxF_Chk(uint32_t NWKPinDef);
extern void PMU_SleepCfg_Init(PMU_SleepCfg_InitTypeDef* SleepCfg_InitStruct);

//Announce_End
#ifdef __cplusplus
}
#endif

#endif /* __FM33A0XXEV_PMU_H */