/** ****************************************************************************** * @file fm33a0xxev_i2c.h * @author FM33A0XXEV Application Team * @version V1.0.0 * @date 16-April-2020 * @brief This file contains all the functions prototypes for the I2C firmware library. ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __FM33A0XXEV_I2C_H #define __FM33A0XXEV_I2C_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "FM33A0XXEV.h" #define I2C_SEND_STARTBIT(I2Cx) I2Cx_CR_SEN_Setable(I2Cx,ENABLE) #define I2C_SEND_RESTARTBIT(I2Cx) I2Cx_CR_RSEN_Setable(I2Cx,ENABLE) #define I2C_SEND_STOPBIT(I2Cx) I2Cx_CR_PEN_Setable(I2Cx,ENABLE) #define I2C_SEND_ACK_0(I2Cx) I2Cx_SR_ACKMO_Set(I2Cx,I2Cx_SR_ACKMO_RESET) #define I2C_SEND_ACK_1(I2Cx) I2Cx_SR_ACKMO_Set(I2Cx,I2Cx_SR_ACKMO_SET) #define I2Cx_CFGR_AUTOEND_Pos 17 /* Ö÷»úDMA×Ô¶¯ÖÕÖ¹ (Automatic Ending) 1£ºDMAÖ¸¶¨³¤¶È´«ÊäÍê³Éºó£¬×Ô¶¯·¢ËÍSTOPʱÐò 0£ºDMAÖ¸¶¨³¤¶È´«ÊäÍê³Éºó£¬µÈ´ýÈí¼þ½Ó¹Ü */ #define I2Cx_CFGR_AUTOEND_Msk (0x1U << I2Cx_CFGR_AUTOEND_Pos) #define I2Cx_CFGR_AUTOEND_AUTO (0x1U << I2Cx_CFGR_AUTOEND_Pos) /* DMAÖ¸¶¨³¤¶È´«ÊäÍê³Éºó£¬×Ô¶¯·¢ËÍSTOPʱÐò */ #define I2Cx_CFGR_AUTOEND_MANUAL (0x0U << I2Cx_CFGR_AUTOEND_Pos) /* DMAÖ¸¶¨³¤¶È´«ÊäÍê³Éºó£¬µÈ´ýÈí¼þ½Ó¹Ü */ #define I2Cx_CFGR_MSP_DMAEN_Pos 16 /* Ö÷»úDMAʹÄÜ (Master DMA Enable) 0£º¹Ø±ÕDMA¹¦ÄÜ 1£ºÊ¹ÄÜDMA¹¦ÄÜ */ #define I2Cx_CFGR_MSP_DMAEN_Msk (0x1U << I2Cx_CFGR_MSP_DMAEN_Pos) /* ¹Ø±ÕDMA¹¦ÄÜ */ /* ʹÄÜDMA¹¦ÄÜ */ #define I2Cx_CFGR_TOEN_Pos 1 /* SCLÀ­µÍ³¬Ê±Ê¹ÄÜ£¨TimeOut£© 1£ºÊ¹Äܳ¬Ê±¹¦ÄÜ£¬³¬Ê±ÖÜÆÚÓÉMSPTO¼Ä´æÆ÷¶¨Òå 0£º¹Ø±Õ³¬Ê±¹¦ÄÜ */ #define I2Cx_CFGR_TOEN_Msk (0x1U << I2Cx_CFGR_TOEN_Pos) #define I2Cx_CFGR_TOEN_ENABLE (0x1U << I2Cx_CFGR_TOEN_Pos) /* ʹÄܳ¬Ê±¹¦ÄÜ£¬³¬Ê±ÖÜÆÚÓÉMSPTO¼Ä´æÆ÷¶¨Òå */ #define I2Cx_CFGR_TOEN_DISABLE (0x0U << I2Cx_CFGR_TOEN_Pos) /* ¹Ø±Õ³¬Ê±¹¦ÄÜ */ #define I2Cx_CFGR_MSPEN_Pos 0 /* I2CÖ÷»úÄ£¿éʹÄÜ¿ØÖÆλ (Master Enable) 1 = I2CÖ÷»úʹÄÜ 0 = I2CÖ÷»ú½ûÖ¹ */ #define I2Cx_CFGR_MSPEN_Msk (0x1U << I2Cx_CFGR_MSPEN_Pos) #define I2Cx_CR_RCEN_Pos 3 /* Ö÷¿Ø½ÓÊÕģʽÏ£¬½ÓÊÕʹÄÜλ (Receive Enable) 1 = Ö÷»ú½ÓÊÕʹÄÜ 0 = ½ÓÊÕ½ûÖ¹ */ #define I2Cx_CR_RCEN_Msk (0x1U << I2Cx_CR_RCEN_Pos) #define I2Cx_CR_PEN_Pos 2 /* STOPʱÐò²úÉúʹÄÜ¿ØÖÆ룬Èí¼þд1·¢ËÍSTOPʱÐò£¬·¢ËÍÍê³ÉºóÓ²¼þ×Ô¶¯ÇåÁã (Stop Enable) */ #define I2Cx_CR_PEN_Msk (0x1U << I2Cx_CR_PEN_Pos) #define I2Cx_CR_RSEN_Pos 1 /* Repeated STARTʱÐò²úÉúʹÄÜ¿ØÖÆ룬Èí¼þд1·¢ËÍSTOPʱÐò£¬·¢ËÍÍê³ÉºóÓ²¼þ×Ô¶¯ÇåÁã (ReStart Enable) */ #define I2Cx_CR_RSEN_Msk (0x1U << I2Cx_CR_RSEN_Pos) #define I2Cx_CR_SEN_Pos 0 /* STARTʱÐò²úÉúʹÄÜ¿ØÖÆ룬Èí¼þд1·¢ËÍSTOPʱÐò£¬·¢ËÍÍê³ÉºóÓ²¼þ×Ô¶¯ÇåÁã (Start Enable) */ #define I2Cx_CR_SEN_Msk (0x1U << I2Cx_CR_SEN_Pos) #define I2Cx_IER_WCOLE_Pos 6 /* WCOLÖжÏʹÄܼĴæÆ÷ (Write Collide Enable) 1£ºÔÊÐíд³åÍ»ÖÐ¶Ï 0£º½ûֹд³åÍ»ÖÐ¶Ï */ #define I2Cx_IER_WCOLE_Msk (0x1U << I2Cx_IER_WCOLE_Pos) /* ÔÊÐíд³åÍ»ÖÐ¶Ï */ /* ½ûֹд³åÍ»ÖÐ¶Ï */ #define I2Cx_IER_TOE_Pos 5 /* SCL³¬Ê±ÖжÏʹÄܼĴæÆ÷ (Time-Out Enable) 1£ºÔÊÐí³¬Ê±ÖÐ¶Ï 0£º½ûÖ¹³¬Ê±ÖÐ¶Ï */ #define I2Cx_IER_TOE_Msk (0x1U << I2Cx_IER_TOE_Pos) #define I2Cx_IER_SE_Pos 4 /* STARTʱÐòÖжÏʹÄܼĴæÆ÷ (START interrupt Enable) 1£ºÔÊÐíSTARTʱÐòÖÐ¶Ï 0£º½ûÖ¹STARTʱÐòÖÐ¶Ï */ #define I2Cx_IER_SE_Msk (0x1U << I2Cx_IER_SE_Pos) /* ÔÊÐíSTARTʱÐòÖÐ¶Ï */ /* ½ûÖ¹STARTʱÐòÖÐ¶Ï */ #define I2Cx_IER_PE_Pos 3 /* STOPʱÐòÖжÏʹÄܼĴæÆ÷ (STOP interrupt Enable) 1£ºÔÊÐíSTOPʱÐòÖÐ¶Ï 0£º½ûÖ¹STOPʱÐòÖÐ¶Ï */ #define I2Cx_IER_PE_Msk (0x1U << I2Cx_IER_PE_Pos) /* ÔÊÐíSTOPʱÐòÖÐ¶Ï */ /* ½ûÖ¹STOPʱÐòÖÐ¶Ï */ #define I2Cx_IER_NACKE_Pos 2 /* Ö÷»ú·¢ËÍģʽÏÂNACKÖжÏʹÄܼĴæÆ÷ (Non-ACK interrupt Enable) 1£ºÔÊÐíÊÕµ½NACK²úÉúÖÐ¶Ï 0£º½ûÖ¹²úÉúNACKÖÐ¶Ï */ #define I2Cx_IER_NACKE_Msk (0x1U << I2Cx_IER_NACKE_Pos) /* ÔÊÐíÊÕµ½NACK²úÉúÖÐ¶Ï */ /* ½ûÖ¹²úÉúNACKÖÐ¶Ï */ #define I2Cx_IER_TXIE_Pos 1 /* I2CÖ÷»ú·¢ËÍÍê³ÉÖжÏʹÄÜ (Transmit done interrupt enable) 1£ºÔÊÐí·¢ËÍÍê³ÉÖÐ¶Ï 0£º½ûÖ¹·¢ËÍÍê³ÉÖÐ¶Ï */ #define I2Cx_IER_TXIE_Msk (0x1U << I2Cx_IER_TXIE_Pos) /* ÔÊÐí·¢ËÍÍê³ÉÖÐ¶Ï */ /* ½ûÖ¹·¢ËÍÍê³ÉÖÐ¶Ï */ #define I2Cx_IER_RXIE_Pos 0 /* I2CÖ÷»ú½ÓÊÕÍê³ÉÖжÏʹÄÜ (Receive done interrupt enable) 1£ºÔÊÐí½ÓÊÕÍê³ÉÖÐ¶Ï 0£º½ûÖ¹½ÓÊÕÍê³ÉÖÐ¶Ï */ #define I2Cx_IER_RXIE_Msk (0x1U << I2Cx_IER_RXIE_Pos) /* ÔÊÐí½ÓÊÕÍê³ÉÖÐ¶Ï */ /* ½ûÖ¹½ÓÊÕÍê³ÉÖÐ¶Ï */ #define I2Cx_ISR_WCOL_Pos 6 /* д³åÍ»¼ì²â룬MCUÖ»ÄÜÔÚÍê³ÉSTARTʱÐò»ò·¢ËÍÍê³ÉÒ»Ö¡¶Áд֮ºó²ÅÄÜдSSPBUF£¬·ñÔò·¢Éúд³åÍ»£»Ó²¼þÖÃ룬Èí¼þд1ÇåÁã (Write Collide) 1 = ·¢ËÍд³åÍ» 0 = δ·¢Éú³åÍ» */ #define I2Cx_ISR_WCOL_Msk (0x1U << I2Cx_ISR_WCOL_Pos) #define I2Cx_ISR_TO_Pos 5 /* SCLÖжϱêÖ¾*/ #define I2Cx_ISR_TO_Msk (0x1U << I2Cx_ISR_TO_Pos) #define I2Cx_ISR_S_Pos 4 /* STARTʱÐò·¢ËÍÍê³ÉÖжϱêÖ¾£¬Ó²¼þÖÃ룬Èí¼þ¶ÁÈ¡ºóÇåÁã (START done) */ #define I2Cx_ISR_S_Msk (0x1U << I2Cx_ISR_S_Pos) #define I2Cx_ISR_P_Pos 3 /* STOPʱÐò·¢ËÍÍê³ÉÖжϱêÖ¾£¬Ó²¼þÖÃ룬Èí¼þ¶ÁÈ¡ºóÇåÁã (STOP done) */ #define I2Cx_ISR_P_Msk (0x1U << I2Cx_ISR_P_Pos) #define I2Cx_ISR_ACKSTA_Pos 2 /* Ö÷¿Ø·¢ËÍģʽÏ£¬À´×Ô´Ó»úµÄ»ØÓ¦Ðźţ»µ±Ö÷»ú·¢ËͺóÊÕµ½NACK£¬´Ë±êÖ¾¿ÉÒÔ²úÉúÖжϣ»Ó²¼þÖÃ룬Èí¼þд1ÇåÁã¡£(Acknowledge Status) 1£º´Ó»ú»ØÓ¦NACK 0£º´Ó»ú»ØÓ¦ACK */ #define I2Cx_ISR_ACKSTA_Msk (0x1U << I2Cx_ISR_ACKSTA_Pos) #define I2Cx_ISR_TXIF_Pos 1 /* I2CÖ÷»ú·¢ËÍÍê³ÉÖжϱêÖ¾£¬Ó²¼þÖÃ룬Èí¼þд1ÇåÁã (Transmit done interrupt flag) */ #define I2Cx_ISR_TXIF_Msk (0x1U << I2Cx_ISR_TXIF_Pos) #define I2Cx_ISR_RXIF_Pos 0 /* I2CÖ÷»ú½ÓÊÕÍê³ÉÖжϱêÖ¾£¬Ó²¼þÖÃ룬Èí¼þд1ÇåÁã (Receive done interrupt flag) */ #define I2Cx_ISR_RXIF_Msk (0x1U << I2Cx_ISR_RXIF_Pos) #define I2Cx_SR_BUSY_Pos 5 /* I2CͨÐÅ״̬λ (I2C is busy) 1£º½Ó¿Ú´¦ÓÚ¶Áд״̬£¬ÕýÔÚ½øÐÐÊý¾Ý´«Ê䣬 0£ºÒÑÍê³ÉÊý¾Ý´«Êä */ #define I2Cx_SR_BUSY_Msk (0x1U << I2Cx_SR_BUSY_Pos) #define I2Cx_SR_RW_Pos 4 /* I2C´«Êä·½Ïò״̬λ (Read or Write Bar) 1£ºÖ÷»ú´Ó´Ó»ú¶ÁÈ¡Êý¾Ý 0£ºÖ÷»úÏò´Ó»úдÈëÊý¾Ý */ #define I2Cx_SR_RW_Msk (0x1U << I2Cx_SR_RW_Pos) #define I2Cx_SR_BF_Pos 2 /* »º³åÆ÷Âú״̬λ (Buffer full) ½ÓÊÕ£º 1 = ½ÓÊÕÍê³É£¬SSPBUFÂú 0 = ½ÓÊÕδÍê³É£¬SSPBUF¿Õ ·¢ËÍ£º 1 = ÕýÔÚ·¢ËÍ£¬SSPBUFÂú 0 = ·¢ËÍÍê³É£¬SSPBUF¿Õ */ #define I2Cx_SR_BF_Msk (0x1U << I2Cx_SR_BF_Pos) #define I2Cx_SR_ACKMO_Pos 0 /* Ö÷¿Ø½ÓÊÕģʽÏ£¬Ö÷»ú»ØÓ¦ÐźŵÄ״̬ (Acknowledge mode) 1£ºÖ÷»ú»Ø·¢NACK 0£ºÖ÷»ú»Ø·¢ACK ×¢Ò⣺±ØÐëÔÚP±êÖ¾¼Ä´æÆ÷±»ÇåÁãµÄÇé¿öÏ£¬Èí¼þ²ÅÄÜÖÃλACKMO */ #define I2Cx_SR_ACKMO_Msk (0x1U << I2Cx_SR_ACKMO_Pos) #define I2Cx_SR_ACKMO_RESET (0x0U << I2Cx_SR_ACKMO_Pos) /* 0£ºÖ÷»ú»Ø·¢ACK */ #define I2Cx_SR_ACKMO_SET (0x1U << I2Cx_SR_ACKMO_Pos) /* 1£ºÖ÷»ú»Ø·¢NACK */ #define I2Cx_BRG_MSPBRGH_Pos 16 /* Ö÷»ú·¢Ë͵ÄSCLʱÖӸߵçƽ¿í¶È£¬ÒÔI2C¹¤×÷ʱÖÓ¼ÆÊý */ #define I2Cx_BRG_MSPBRGH_Msk (0x1ffU << I2Cx_BRG_MSPBRGH_Pos) #define I2Cx_BRG_MSPBRGL_Pos 0 /* Ö÷»ú·¢Ë͵ÄSCLʱÖӵ͵çƽ¿í¶È£¬ÒÔI2C¹¤×÷ʱÖÓ¼ÆÊý */ #define I2Cx_BRG_MSPBRGL_Msk (0x1ffU << I2Cx_BRG_MSPBRGL_Pos) #define I2Cx_BUF_WR_Pos 0 /* SSPBUF[7:0]£ºÊý¾ÝµÄ¶Áдͨ¹ý¶ÔSSPBUFµÄ²Ù×÷Íê³É¡£·¢ËÍʱ£¬¶ÔSSPBUFÖ´ÐÐд²Ù×÷£¬Í¬Ê±Ò²ÔØÈëÊý¾ÝÊÕ·¢ÒÆλ¼Ä´æÆ÷(SSPSR)£»½ÓÊÕʱ£¬SSPBUFÓëSSPSR×é³ÉË«»º³å½á¹¹£¬¶Á³öÊý¾ÝΪSSPBUFµÄÊý¾Ý¡£½ÓÊÕÍêÒ»¸ö×Ö½ÚµÄÊý¾Ý£¬SSPSR½«Êý¾ÝÔØÈëSSPBUF£¬Í¬Ê±ÖÃλI2CIF¡£SSPSR²»ÊÇÖ±½Ó¼Ä´æÆ÷£¬Ã»ÓÐÎïÀíµØÖ· */ #define I2Cx_BUF_WR_Msk (0xffU << I2Cx_BUF_WR_Pos) #define I2Cx_TIMING_SDAHD_Pos 0 /* ¶¨ÒåSDAÏà¶ÔÓÚSCLϽµÑصı£³Öʱ¼ä²ÎÊý£¬ÒÔI2C¹¤×÷ʱÖÓ¼ÆÊý (SDA hold time) */ #define I2Cx_TIMING_SDAHD_Msk (0x1ffU << I2Cx_TIMING_SDAHD_Pos) #define I2Cx_TO_TIMEOUT_Pos 0 /* ¶¨Òå´Ó»úSCLµÍµçƽÑÓÕ¹³¬Ê±ÖÜÆÚ£¬Èí¼þ¿ÉÒÔÔÚMSPEN=0µÄÇé¿öϸÄд TSCL_STRETCHING_TIMEOUT=TIMEOUT[11:0] * TSCL */ #define I2Cx_TO_TIMEOUT_Msk (0xfffU << I2Cx_TO_TIMEOUT_Pos) //Macro_End /* Exported functions --------------------------------------------------------*/ extern void I2Cx_Deinit(I2C_Type* I2Cx); /* Ö÷»úDMA×Ô¶¯ÖÕÖ¹ (Automatic Ending) 1£ºDMAÖ¸¶¨³¤¶È´«ÊäÍê³Éºó£¬×Ô¶¯·¢ËÍSTOPʱÐò 0£ºDMAÖ¸¶¨³¤¶È´«ÊäÍê³Éºó£¬µÈ´ýÈí¼þ½Ó¹Ü Ïà¹Øº¯Êý */ extern void I2Cx_CFGR_AUTOEND_Set(I2C_Type* I2Cx, uint32_t SetValue); extern uint32_t I2Cx_CFGR_AUTOEND_Get(I2C_Type* I2Cx); /* Ö÷»úDMAʹÄÜ (Master DMA Enable) 0£º¹Ø±ÕDMA¹¦ÄÜ 1£ºÊ¹ÄÜDMA¹¦ÄÜ Ïà¹Øº¯Êý */ extern void I2Cx_CFGR_MSP_DMAEN_Setable(I2C_Type* I2Cx, FunState NewState); extern FunState I2Cx_CFGR_MSP_DMAEN_Getable(I2C_Type* I2Cx); /* SCLÀ­µÍ³¬Ê±Ê¹ÄÜ£¨TimeOut£© 1£ºÊ¹Äܳ¬Ê±¹¦ÄÜ£¬³¬Ê±ÖÜÆÚÓÉMSPTO¼Ä´æÆ÷¶¨Òå 0£º¹Ø±Õ³¬Ê±¹¦ÄÜ Ïà¹Øº¯Êý */ extern void I2Cx_CFGR_TOEN_Setable(I2C_Type* I2Cx, FunState NewState); extern FunState I2Cx_CFGR_TOEN_Getable(I2C_Type* I2Cx); /* I2CÖ÷»úÄ£¿éʹÄÜ¿ØÖÆλ (Master Enable) 1 = I2CÖ÷»úʹÄÜ 0 = I2CÖ÷»ú½ûÖ¹ Ïà¹Øº¯Êý */ extern void I2Cx_CFGR_MSPEN_Setable(I2C_Type* I2Cx, FunState NewState); extern FunState I2Cx_CFGR_MSPEN_Getable(I2C_Type* I2Cx); /* Ö÷¿Ø½ÓÊÕģʽÏ£¬½ÓÊÕʹÄÜλ (Receive Enable) 1 = Ö÷»ú½ÓÊÕʹÄÜ 0 = ½ÓÊÕ½ûÖ¹ Ïà¹Øº¯Êý */ extern void I2Cx_CR_RCEN_Setable(I2C_Type* I2Cx, FunState NewState); extern FunState I2Cx_CR_RCEN_Getable(I2C_Type* I2Cx); /* STOPʱÐò²úÉúʹÄÜ¿ØÖÆ룬Èí¼þд1·¢ËÍSTOPʱÐò£¬·¢ËÍÍê³ÉºóÓ²¼þ×Ô¶¯ÇåÁã (Stop Enable) Ïà¹Øº¯Êý */ extern void I2Cx_CR_PEN_Setable(I2C_Type* I2Cx, FunState NewState); extern FunState I2Cx_CR_PEN_Getable(I2C_Type* I2Cx); /* Repeated STARTʱÐò²úÉúʹÄÜ¿ØÖÆ룬Èí¼þд1·¢ËÍSTOPʱÐò£¬·¢ËÍÍê³ÉºóÓ²¼þ×Ô¶¯ÇåÁã (ReStart Enable) Ïà¹Øº¯Êý */ extern void I2Cx_CR_RSEN_Setable(I2C_Type* I2Cx, FunState NewState); extern FunState I2Cx_CR_RSEN_Getable(I2C_Type* I2Cx); /* STARTʱÐò²úÉúʹÄÜ¿ØÖÆ룬Èí¼þд1·¢ËÍSTOPʱÐò£¬·¢ËÍÍê³ÉºóÓ²¼þ×Ô¶¯ÇåÁã (Start Enable) Ïà¹Øº¯Êý */ extern void I2Cx_CR_SEN_Setable(I2C_Type* I2Cx, FunState NewState); extern FunState I2Cx_CR_SEN_Getable(I2C_Type* I2Cx); /* WCOLÖжÏʹÄܼĴæÆ÷ (Write Collide Enable) 1£ºÔÊÐíд³åÍ»ÖÐ¶Ï 0£º½ûֹд³åÍ»ÖÐ¶Ï Ïà¹Øº¯Êý */ extern void I2Cx_IER_WCOLE_Setable(I2C_Type* I2Cx, FunState NewState); extern FunState I2Cx_IER_WCOLE_Getable(I2C_Type* I2Cx); /* SCL³¬Ê±ÖжÏʹÄܼĴæÆ÷ (Time-Out Enable) 1£ºÔÊÐí³¬Ê±ÖÐ¶Ï 0£º½ûÖ¹³¬Ê±ÖÐ¶Ï Ïà¹Øº¯Êý */ extern void I2Cx_IER_TOE_Setable(I2C_Type* I2Cx, FunState NewState); extern FunState I2Cx_IER_TOE_Getable(I2C_Type* I2Cx); /* STARTʱÐòÖжÏʹÄܼĴæÆ÷ (START interrupt Enable) 1£ºÔÊÐíSTARTʱÐòÖÐ¶Ï 0£º½ûÖ¹STARTʱÐòÖÐ¶Ï Ïà¹Øº¯Êý */ extern void I2Cx_IER_SE_Setable(I2C_Type* I2Cx, FunState NewState); extern FunState I2Cx_IER_SE_Getable(I2C_Type* I2Cx); /* STOPʱÐòÖжÏʹÄܼĴæÆ÷ (STOP interrupt Enable) 1£ºÔÊÐíSTOPʱÐòÖÐ¶Ï 0£º½ûÖ¹STOPʱÐòÖÐ¶Ï Ïà¹Øº¯Êý */ extern void I2Cx_IER_PE_Setable(I2C_Type* I2Cx, FunState NewState); extern FunState I2Cx_IER_PE_Getable(I2C_Type* I2Cx); /* Ö÷»ú·¢ËÍģʽÏÂNACKÖжÏʹÄܼĴæÆ÷ (Non-ACK interrupt Enable) 1£ºÔÊÐíÊÕµ½NACK²úÉúÖÐ¶Ï 0£º½ûÖ¹²úÉúNACKÖÐ¶Ï Ïà¹Øº¯Êý */ extern void I2Cx_IER_NACKE_Setable(I2C_Type* I2Cx, FunState NewState); extern FunState I2Cx_IER_NACKE_Getable(I2C_Type* I2Cx); /* I2CÖ÷»ú·¢ËÍÍê³ÉÖжÏʹÄÜ (Transmit done interrupt enable) 1£ºÔÊÐí·¢ËÍÍê³ÉÖÐ¶Ï 0£º½ûÖ¹·¢ËÍÍê³ÉÖÐ¶Ï Ïà¹Øº¯Êý */ extern void I2Cx_IER_TXIE_Setable(I2C_Type* I2Cx, FunState NewState); extern FunState I2Cx_IER_TXIE_Getable(I2C_Type* I2Cx); /* I2CÖ÷»ú½ÓÊÕÍê³ÉÖжÏʹÄÜ (Receive done interrupt enable) 1£ºÔÊÐí½ÓÊÕÍê³ÉÖÐ¶Ï 0£º½ûÖ¹½ÓÊÕÍê³ÉÖÐ¶Ï Ïà¹Øº¯Êý */ extern void I2Cx_IER_RXIE_Setable(I2C_Type* I2Cx, FunState NewState); extern FunState I2Cx_IER_RXIE_Getable(I2C_Type* I2Cx); /* д³åÍ»¼ì²â룬MCUÖ»ÄÜÔÚÍê³ÉSTARTʱÐò»ò·¢ËÍÍê³ÉÒ»Ö¡¶Áд֮ºó²ÅÄÜдSSPBUF£¬·ñÔò·¢Éúд³åÍ»£»Ó²¼þÖÃ룬Èí¼þд1ÇåÁã (Write Collide) 1 = ·¢ËÍд³åÍ» 0 = δ·¢Éú³åÍ» Ïà¹Øº¯Êý */ extern void I2Cx_ISR_WCOL_Clr(I2C_Type* I2Cx); extern FlagStatus I2Cx_ISR_WCOL_Chk(I2C_Type* I2Cx); extern void I2Cx_ISR_OVT_Clr(I2C_Type* I2Cx); extern FlagStatus I2Cx_ISR_OVT_Chk(I2C_Type* I2Cx); /* STARTʱÐò·¢ËÍÍê³ÉÖжϱêÖ¾£¬Ó²¼þÖÃ룬Èí¼þ¶ÁÈ¡ºóÇåÁã (START done) Ïà¹Øº¯Êý */ extern FlagStatus I2Cx_ISR_S_Chk(I2C_Type* I2Cx); /* STOPʱÐò·¢ËÍÍê³ÉÖжϱêÖ¾£¬Ó²¼þÖÃ룬Èí¼þ¶ÁÈ¡ºóÇåÁã (STOP done) Ïà¹Øº¯Êý */ extern FlagStatus I2Cx_ISR_P_Chk(I2C_Type* I2Cx); /* Ö÷¿Ø·¢ËÍģʽÏ£¬À´×Ô´Ó»úµÄ»ØÓ¦Ðźţ»µ±Ö÷»ú·¢ËͺóÊÕµ½NACK£¬´Ë±êÖ¾¿ÉÒÔ²úÉúÖжϣ»Ó²¼þÖÃ룬Èí¼þд1ÇåÁã¡£(Acknowledge Status) 1£º´Ó»ú»ØÓ¦NACK 0£º´Ó»ú»ØÓ¦ACK Ïà¹Øº¯Êý */ extern void I2Cx_ISR_ACKSTA_Clr(I2C_Type* I2Cx); extern FlagStatus I2Cx_ISR_ACKSTA_Chk(I2C_Type* I2Cx); /* I2CÖ÷»ú·¢ËÍÍê³ÉÖжϱêÖ¾£¬Ó²¼þÖÃ룬Èí¼þд1ÇåÁã (Transmit done interrupt flag) Ïà¹Øº¯Êý */ extern void I2Cx_ISR_TXIF_Clr(I2C_Type* I2Cx); extern FlagStatus I2Cx_ISR_TXIF_Chk(I2C_Type* I2Cx); /* I2CÖ÷»ú½ÓÊÕÍê³ÉÖжϱêÖ¾£¬Ó²¼þÖÃ룬Èí¼þд1ÇåÁã (Receive done interrupt flag) Ïà¹Øº¯Êý */ extern void I2Cx_ISR_RXIF_Clr(I2C_Type* I2Cx); extern FlagStatus I2Cx_ISR_RXIF_Chk(I2C_Type* I2Cx); /* I2CͨÐÅ״̬λ (I2C is busy) 1£º½Ó¿Ú´¦ÓÚ¶Áд״̬£¬ÕýÔÚ½øÐÐÊý¾Ý´«Ê䣬 0£ºÒÑÍê³ÉÊý¾Ý´«Êä Ïà¹Øº¯Êý */ extern FlagStatus I2Cx_SR_BUSY_Chk(I2C_Type* I2Cx); /* I2C´«Êä·½Ïò״̬λ (Read or Write Bar) 1£ºÖ÷»ú´Ó´Ó»ú¶ÁÈ¡Êý¾Ý 0£ºÖ÷»úÏò´Ó»úдÈëÊý¾Ý Ïà¹Øº¯Êý */ extern FlagStatus I2Cx_SR_RW_Chk(I2C_Type* I2Cx); /* »º³åÆ÷Âú״̬λ (Buffer full) ½ÓÊÕ£º 1 = ½ÓÊÕÍê³É£¬SSPBUFÂú 0 = ½ÓÊÕδÍê³É£¬SSPBUF¿Õ ·¢ËÍ£º 1 = ÕýÔÚ·¢ËÍ£¬SSPBUFÂú 0 = ·¢ËÍÍê³É£¬SSPBUF¿Õ Ïà¹Øº¯Êý */ extern FlagStatus I2Cx_SR_BF_Chk(I2C_Type* I2Cx); /* Ö÷¿Ø½ÓÊÕģʽÏ£¬Ö÷»ú»ØÓ¦ÐźŵÄ״̬ (Acknowledge mode) 1£ºÖ÷»ú»Ø·¢NACK 0£ºÖ÷»ú»Ø·¢ACK ×¢Ò⣺±ØÐëÔÚP±êÖ¾¼Ä´æÆ÷±»ÇåÁãµÄÇé¿öÏ£¬Èí¼þ²ÅÄÜÖÃλACKMO Ïà¹Øº¯Êý */ extern void I2Cx_SR_ACKMO_Set(I2C_Type* I2Cx,uint32_t SetValue); extern uint32_t I2Cx_SR_ACKMO_Get(I2C_Type* I2Cx); /* Ö÷»ú·¢Ë͵ÄSCLʱÖӸߵçƽ¿í¶È£¬ÒÔI2C¹¤×÷ʱÖÓ¼ÆÊý Ïà¹Øº¯Êý */ extern void I2Cx_BRG_MSPBRGH_Set(I2C_Type* I2Cx, uint32_t SetValue); extern uint32_t I2Cx_BRG_MSPBRGH_Get(I2C_Type* I2Cx); /* Ö÷»ú·¢Ë͵ÄSCLʱÖӵ͵çƽ¿í¶È£¬ÒÔI2C¹¤×÷ʱÖÓ¼ÆÊý Ïà¹Øº¯Êý */ extern void I2Cx_BRG_MSPBRGL_Set(I2C_Type* I2Cx, uint32_t SetValue); extern uint32_t I2Cx_BRG_MSPBRGL_Get(I2C_Type* I2Cx); /* SSPBUF[7:0]£ºÊý¾ÝµÄ¶Áдͨ¹ý¶ÔSSPBUFµÄ²Ù×÷Íê³É¡£·¢ËÍʱ£¬¶ÔSSPBUFÖ´ÐÐд²Ù×÷£¬Í¬Ê±Ò²ÔØÈëÊý¾ÝÊÕ·¢ÒÆλ¼Ä´æÆ÷(SSPSR)£»½ÓÊÕʱ£¬SSPBUFÓëSSPSR×é³ÉË«»º³å½á¹¹£¬¶Á³öÊý¾ÝΪSSPBUFµÄÊý¾Ý¡£½ÓÊÕÍêÒ»¸ö×Ö½ÚµÄÊý¾Ý£¬SSPSR½«Êý¾ÝÔØÈëSSPBUF£¬Í¬Ê±ÖÃλI2CIF¡£SSPSR²»ÊÇÖ±½Ó¼Ä´æÆ÷£¬Ã»ÓÐÎïÀíµØÖ· Ïà¹Øº¯Êý */ extern void I2Cx_BUF_Write(I2C_Type* I2Cx, uint32_t SetValue); extern uint32_t I2Cx_BUF_Read(I2C_Type* I2Cx); /* ¶¨ÒåSDAÏà¶ÔÓÚSCLϽµÑصı£³Öʱ¼ä²ÎÊý£¬ÒÔI2C¹¤×÷ʱÖÓ¼ÆÊý (SDA hold time) Ïà¹Øº¯Êý */ extern void I2Cx_TIMING_Write(I2C_Type* I2Cx, uint32_t SetValue); extern uint32_t I2Cx_TIMING_Read(I2C_Type* I2Cx); /* ¶¨Òå´Ó»úSCLµÍµçƽÑÓÕ¹³¬Ê±ÖÜÆÚ£¬Èí¼þ¿ÉÒÔÔÚMSPEN=0µÄÇé¿öϸÄд TSCL_STRETCHING_TIMEOUT=TIMEOUT[11:0] * TSCL Ïà¹Øº¯Êý */ extern void I2Cx_TO_Write(I2C_Type* I2Cx, uint32_t SetValue); extern uint32_t I2Cx_TO_Read(I2C_Type* I2Cx); extern void I2Cx_Deinit(I2C_Type* I2Cx); extern uint32_t I2C_BaudREG_Calc(uint32_t I2CClk, uint32_t APBClk); //Announce_End #ifdef __cplusplus } #endif #endif /*__FM33A0XXEV_I2C_H */