/** ****************************************************************************** * @file fm33a0xxev_et.h * @author FM33A0XXEV Application Team * @version V1.0.0 * @date 16-April-2020 * @brief This file contains all the functions prototypes for the ET firmware library. ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __FM33A0XXEV_ET_H #define __FM33A0XXEV_ET_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "FM33A0XXEV.h" #define ETx_CR_OPOL_Pos 10 /* Êä³ö¼«ÐÔÑ¡Ôñ (Output Polarity) 0£ºÊä³ö²»È¡·´ 1£ºÊä³öÈ¡·´ */ #define ETx_CR_OPOL_Msk (0x1U << ETx_CR_OPOL_Pos) #define ETx_CR_OPOL_NORMAL (0x0U << ETx_CR_OPOL_Pos) /* Êä³ö²»È¡·´ */ #define ETx_CR_OPOL_REVERSE (0x1U << ETx_CR_OPOL_Pos) /* Êä³öÈ¡·´ */ #define ETx_CR_EXFLT_Pos 9 /* ÍⲿÒý½ÅÊäÈëÊý×ÖÂ˲¨Ê¹ÄÜ 1 = ´ò¿ªÒý½ÅÊäÈëÐźÅÊý×ÖÂ˲¨ 0 = ¹Ø±ÕÒý½ÅÊäÈëÐźÅÊý×ÖÂ˲¨ */ #define ETx_CR_EXFLT_Msk (0x1U << ETx_CR_EXFLT_Pos) #define ETx_CR_EXFLT_OPEN (0x1U << ETx_CR_EXFLT_Pos) #define ETx_CR_EXFLT_CLOSE (0x0U << ETx_CR_EXFLT_Pos) #define ETx_CR_PWM_Pos 8 /* PWMÊä³ö¿ØÖÆ 1 = PWMÊä³öʹÄÜ 0 = PWMÊä³ö½ûÖ¹ */ #define ETx_CR_PWM_Msk (0x1U << ETx_CR_PWM_Pos) #define ETx_CR_CEN_Pos 7 /* Æô¶¯¿ØÖÆ 1 = Æô¶¯¶¨Ê±Æ÷£¬ÔÚ¼ÆÊýÆ÷ģʽÏÂÆô¶¯Ê±½«¼ÆÊý³õÖµ¼ÓÔØÖÁ¼ÆÊýÆ÷ºÍ¹¤×÷¼Ä´æÆ÷£»ÔÚ²¶×½Ä£Ê½Ï£¬Æô¶¯Ê±¼ÆÊýÆ÷ÓÉÁ㿪ʼ×ÔÓɼÆÊý£¬¼ÆÊýµ½0xFFFFºó²úÉúÒç³öÐźÅÈ»ºóÓÉÁ㿪ʼÖØмÆÊý 0 = Í£Ö¹¼ÆÊýÆ÷¼ÆÊý */ #define ETx_CR_CEN_Msk (0x1U << ETx_CR_CEN_Pos) #define ETx_CR_MOD_Pos 6 /* ¹¤×÷ģʽѡÔñ 1 = ²¶×½Ä£Ê½ 0 = ¶¨Ê±/¼ÆÊýģʽ */ #define ETx_CR_MOD_Msk (0x1U << ETx_CR_MOD_Pos) #define ETx_CR_MOD_CAPTURE (0x1U << ETx_CR_MOD_Pos) #define ETx_CR_MOD_COUNTER (0x0U << ETx_CR_MOD_Pos) #define ETx_CR_CASEN_Pos 5 /* Cascade Enable£¬À©Õ¹¶¨Ê±Æ÷¼¶ÁªÊ¹ÄÜ 1 = ET1£¨ET3£©ºÍET2£¨ET4£©¼¶Áª³É32bit¶¨Ê±Æ÷ 0 = 16bit¶¨Ê±Æ÷¶ÀÁ¢¹¤×÷ */ #define ETx_CR_CASEN_Msk (0x1U << ETx_CR_CASEN_Pos) #define ETx_CR_CASEN_32BITS (0x1U << ETx_CR_CASEN_Pos) #define ETx_CR_CASEN_16BITS (0x0U << ETx_CR_CASEN_Pos) #define ETx_CR_EDGESEL_Pos 4 /* ¼ÆÊýģʽ²ÉÑØ·½Ê½Ñ¡Ôñ £¨¼ÆÊýʱÖÓÑ¡Ôñmcu_clkʱ¸ÃλÎÞЧ£¬×ÜÊDzÉÓÃmcu_clkʱÖÓÉÏÉýÑؼÆÊý£© 1 = ¼ÆÊýģʽ²ÉϽµÑØ 0 = ¼ÆÊýģʽ²ÉÉÏÉýÑØ */ #define ETx_CR_EDGESEL_Msk (0x1U << ETx_CR_EDGESEL_Pos) #define ETx_CR_EDGESEL_FALLING (0x1U << ETx_CR_EDGESEL_Pos) #define ETx_CR_EDGESEL_RISING (0x0U << ETx_CR_EDGESEL_Pos) #define ETx_CR_CAPMOD_Pos 3 /* ²¶×½Ä£Ê½¿ØÖÆ 1 = Âö¿í²¶×½ 0 = Âö³åÖÜÆÚ²¶×½ */ #define ETx_CR_CAPMOD_Msk (0x1U << ETx_CR_CAPMOD_Pos) #define ETx_CR_CAPMOD_PULSE (0x1U << ETx_CR_CAPMOD_Pos) #define ETx_CR_CAPMOD_CYCLE (0x0U << ETx_CR_CAPMOD_Pos) #define ETx_CR_CAPCLR_Pos 2 /* ´øÇåÁ㲶׽ģʽ¿ØÖÆ 1 = ʼþ´¥·¢²¶×½£ºÊ¹Äܺó¼ÆÊýÆ÷±£³Ö0£¬²¶×½µ½µÚÒ»¸öÓÐЧÑØÖ®ºótimer²Å¿ªÊ¼¼ÆÊý 0 = ²¶×½²»ÇåÁ㣬¼ÆÊýÆ÷Ò»Ö±×ÔÓɼÆÊý */ #define ETx_CR_CAPCLR_Msk (0x1U << ETx_CR_CAPCLR_Pos) /* ʹÄܺó¼ÆÊýÆ÷±£³Ö0£¬²¶×½µ½µÚÒ»¸öÓÐЧÑØÖ®ºótimer²Å¿ªÊ¼¼ÆÊý */ #define ETx_CR_CAPONCE_Pos 1 /* µ¥´Î²¶×½¿ØÖÆ 1 = µ¥´Î²¶×½ÓÐЧ£¬ÔÚ²¶×½µ½Ò»´ÎÂö³åÖÜÆÚºó¼ÆÊýÆ÷Í£Ö¹£¬ÈôÐèÒªÔٴβ¶×½ÐèÖØÐÂÆô¶¯ 0 = Á¬Ðø²¶×½ */ #define ETx_CR_CAPONCE_Msk (0x1U << ETx_CR_CAPONCE_Pos) #define ETx_CR_CAPONCE_SINGLE (0x1U << ETx_CR_CAPONCE_Pos) #define ETx_CR_CAPONCE_CONTINUE (0x0U << ETx_CR_CAPONCE_Pos) #define ETx_CR_CAPEDGE_Pos 0 /* ²¶×½ÑØÑ¡Ôñ 1 = ÖÜÆÚ²¶×½Ä£Ê½Ê±ÏÂÑز¶×½ 0 = ÖÜÆÚ²¶×½Ä£Ê½Ê±ÉÏÑز¶×½ */ #define ETx_CR_CAPEDGE_Msk (0x1U << ETx_CR_CAPEDGE_Pos) #define ETx_CR_CAPEDGE_FALLING (0x1U << ETx_CR_CAPEDGE_Pos) #define ETx_CR_CAPEDGE_RISING (0x0U << ETx_CR_CAPEDGE_Pos) #define ETx_INSR_SIG2SEL_Pos 7 /* ÄÚ²¿ÐźÅ2Ô´Ñ¡Ôñ(²¶×½Ô´) 1 = À©Õ¹¶¨Ê±Æ÷3µÄÄÚ²¿ÐźÅ2Ñ¡ÔñGroup1 0 = À©Õ¹¶¨Ê±Æ÷3µÄÄÚ²¿ÐźÅ2Ñ¡ÔñGroup2 */ #define ETx_INSR_SIG2SEL_Msk (0x1U << ETx_INSR_SIG2SEL_Pos) #define ETx_INSR_SIG2SEL_GROUP1 (0x1U << ETx_INSR_SIG2SEL_Pos) #define ETx_INSR_SIG2SEL_GROUP2 (0x0U << ETx_INSR_SIG2SEL_Pos) #define ETx_INSR_SIG1SEL_Pos 6 /* ÄÚ²¿ÐźÅ1Ô´Ñ¡Ôñ£¨ÔÚ¼ÆÊýģʽϼÆÊýÔ´½öÓÉ´ËÑ¡Ôñ£¬²¶×½Ä£Ê½Ï¼ÆÊýÔ´£© 1 = À©Õ¹¶¨Ê±Æ÷3µÄÄÚ²¿ÐźÅ1Ñ¡ÔñGroup2 0 = À©Õ¹¶¨Ê±Æ÷3µÄÄÚ²¿ÐźÅ1Ñ¡ÔñGroup1 */ #define ETx_INSR_SIG1SEL_Msk (0x1U << ETx_INSR_SIG1SEL_Pos) #define ETx_INSR_SIG1SEL_GROUP2 (0x1U << ETx_INSR_SIG1SEL_Pos) #define ETx_INSR_SIG1SEL_GROUP1 (0x0U << ETx_INSR_SIG1SEL_Pos) #define ETx_INSR_GRP2SEL_Pos 2 /* GROUP2 ÐźÅÑ¡Ôñ¿ØÖÆ ET1 000 = UART0_RX 001 = UART1_RX 010 = XTLF 011 = ET1_IN1 100 = ET1_IN2 101 = CMP1O£¨±È½ÏÆ÷1Êä³ö£© 110 = CMP2O£¨±È½ÏÆ÷2Êä³ö£© 111 = RCMF ET2 000 = UART2_RX 001 = UART3_RX 010 = XTLF 011 = ET2_IN1 100 = ET2_IN2 101 = CMP1O£¨±È½ÏÆ÷1Êä³ö£© 110 = CMP2O£¨±È½ÏÆ÷2Êä³ö£© 111 = RCMF ET3 000 = ET3_IN1 001 = XTLF 010 = UART4_RX 011 = UART5_RX 100 = RTCSEC 101~111 = RFU ET4 000 = ET4_IN1 001 = XTLF 010 = UART_RX2 011 = UART_RX0 100 = CMP1O£¨±È½ÏÆ÷1Êä³ö£© 101 = CMP2O£¨±È½ÏÆ÷2Êä³ö£© 110= RTCSEC 111= RCMF? */ #define ETx_INSR_GRP2SEL_Msk (0x7U << ETx_INSR_GRP2SEL_Pos) #define ETx_INSR_GRP2SEL_ET1_UART0_RX (0x0U << ETx_INSR_GRP2SEL_Pos) #define ETx_INSR_GRP2SEL_ET1_UART1_RX (0x1U << ETx_INSR_GRP2SEL_Pos) #define ETx_INSR_GRP2SEL_ET1_XTLF (0x2U << ETx_INSR_GRP2SEL_Pos) #define ETx_INSR_GRP2SEL_ET1_IN1 (0x3U << ETx_INSR_GRP2SEL_Pos) #define ETx_INSR_GRP2SEL_ET1_IN2 (0x4U << ETx_INSR_GRP2SEL_Pos) #define ETx_INSR_GRP2SEL_ET1_CMP1O (0x5U << ETx_INSR_GRP2SEL_Pos) #define ETx_INSR_GRP2SEL_ET1_CMP2O (0x6U << ETx_INSR_GRP2SEL_Pos) #define ETx_INSR_GRP2SEL_ET1_RCMF (0x7U << ETx_INSR_GRP2SEL_Pos) #define ETx_INSR_GRP2SEL_ET2_UART2_RX (0x0U << ETx_INSR_GRP2SEL_Pos) #define ETx_INSR_GRP2SEL_ET2_UART3_RX (0x1U << ETx_INSR_GRP2SEL_Pos) #define ETx_INSR_GRP2SEL_ET2_XTLF (0x2U << ETx_INSR_GRP2SEL_Pos) #define ETx_INSR_GRP2SEL_ET2_IN1 (0x3U << ETx_INSR_GRP2SEL_Pos) #define ETx_INSR_GRP2SEL_ET2_IN2 (0x4U << ETx_INSR_GRP2SEL_Pos) #define ETx_INSR_GRP2SEL_ET2_CMP1O (0x5U << ETx_INSR_GRP2SEL_Pos) #define ETx_INSR_GRP2SEL_ET2_CMP2O (0x6U << ETx_INSR_GRP2SEL_Pos) #define ETx_INSR_GRP2SEL_ET2_RCMF (0x7U << ETx_INSR_GRP2SEL_Pos) #define ETx_INSR_GRP2SEL_ET3_IN1 (0x0U << ETx_INSR_GRP2SEL_Pos) #define ETx_INSR_GRP2SEL_ET3_XTLF (0x1U << ETx_INSR_GRP2SEL_Pos) #define ETx_INSR_GRP2SEL_ET3_UART4_RX (0x2U << ETx_INSR_GRP2SEL_Pos) #define ETx_INSR_GRP2SEL_ET3_UART5_RX (0x3U << ETx_INSR_GRP2SEL_Pos) #define ETx_INSR_GRP2SEL_ET3_RTCSEC (0x4U << ETx_INSR_GRP2SEL_Pos) #define ETx_INSR_GRP2SEL_ET4_IN (0x0U << ETx_INSR_GRP2SEL_Pos) #define ETx_INSR_GRP2SEL_ET4_XTLF (0x1U << ETx_INSR_GRP2SEL_Pos) #define ETx_INSR_GRP2SEL_ET4_UART_RX2 (0x2U << ETx_INSR_GRP2SEL_Pos) #define ETx_INSR_GRP2SEL_ET4_UART_RX0 (0x3U << ETx_INSR_GRP2SEL_Pos) #define ETx_INSR_GRP2SEL_ET4_CMP1O (0x4U << ETx_INSR_GRP2SEL_Pos) #define ETx_INSR_GRP2SEL_ET4_CMP2O (0x5U << ETx_INSR_GRP2SEL_Pos) #define ETx_INSR_GRP2SEL_ET4_RTCSEC (0x6U << ETx_INSR_GRP2SEL_Pos) #define ETx_INSR_GRP2SEL_ET4_RCMF (0x7U << ETx_INSR_GRP2SEL_Pos) #define ETx_INSR_GRP1SEL_Pos 0 /* GROUP1 ÐźÅÑ¡Ôñ¿ØÖÆ ET1 00 = APBCLK 01 = XTLF 10 = RCLP 11 = ET1_IN0 ET2 00 = APBCLK 01 = XTLF 10 = RCLP 11 = ET2_IN0 ET3 00 = APBCLK 01 = ET3_IN0 10 = RTCSEC 11 = RCLP ET4 00 = APBCLK 01 = ET4_IN0 10 = RTC64HZ 11 = RCMF */ #define ETx_INSR_GRP1SEL_Msk (0x3U << ETx_INSR_GRP1SEL_Pos) #define ETx_INSR_GRP1SEL_ET1_APBCLK (0x0U << ETx_INSR_GRP1SEL_Pos) #define ETx_INSR_GRP1SEL_ET1_XTLF (0x1U << ETx_INSR_GRP1SEL_Pos) #define ETx_INSR_GRP1SEL_ET1_RCLP (0x2U << ETx_INSR_GRP1SEL_Pos) #define ETx_INSR_GRP1SEL_ET1_IN0 (0x3U << ETx_INSR_GRP1SEL_Pos) #define ETx_INSR_GRP1SEL_ET2_APBCLK (0x0U << ETx_INSR_GRP1SEL_Pos) #define ETx_INSR_GRP1SEL_ET2_XTLF (0x1U << ETx_INSR_GRP1SEL_Pos) #define ETx_INSR_GRP1SEL_ET2_RCLP (0x2U << ETx_INSR_GRP1SEL_Pos) #define ETx_INSR_GRP1SEL_ET2_IN0 (0x3U << ETx_INSR_GRP1SEL_Pos) #define ETx_INSR_GRP1SEL_ET3_APBCLK (0x0U << ETx_INSR_GRP1SEL_Pos) #define ETx_INSR_GRP1SEL_ET3_IN0 (0x1U << ETx_INSR_GRP1SEL_Pos) #define ETx_INSR_GRP1SEL_ET3_RTCSEC (0x2U << ETx_INSR_GRP1SEL_Pos) #define ETx_INSR_GRP1SEL_ET3_RCLP (0x3U << ETx_INSR_GRP1SEL_Pos) #define ETx_INSR_GRP1SEL_ET4_APBCLK (0x0U << ETx_INSR_GRP1SEL_Pos) #define ETx_INSR_GRP1SEL_ET4_IN0 (0x1U << ETx_INSR_GRP1SEL_Pos) #define ETx_INSR_GRP1SEL_ET4_RTC64HZ (0x2U << ETx_INSR_GRP1SEL_Pos) #define ETx_INSR_GRP1SEL_ET4_RCMF (0x3U << ETx_INSR_GRP1SEL_Pos) #define ETx_PSCR1_PRESCALE1_Pos 0 /* ÊäÈëSignal1£¨¼ÆÊýÔ´£©µÄÔ¤·ÖƵ¼Ä´æÆ÷ 00±íʾ1·ÖƵ£¬FF±íʾ256·ÖƵ */ #define ETx_PSCR1_PRESCALE1_Msk (0xffU << ETx_PSCR1_PRESCALE1_Pos) #define ETx_PSCR2_PRESCALE2_Pos 0 /* ÊäÈëSignal2£¨²¶×½Ô´£©µÄÔ¤·ÖƵ¼Ä´æÆ÷ 00±íʾ1·ÖƵ£¬FF±íʾ256·ÖƵ¡£ */ #define ETx_PSCR2_PRESCALE2_Msk (0xffU << ETx_PSCR2_PRESCALE2_Pos) #define ETx_IVR_INITVALUE_Pos 0 /* À©Õ¹¶¨Ê±Æ÷³õÖµ¼Ä´æÆ÷ */ #define ETx_IVR_INITVALUE_Msk (0xffffU << ETx_IVR_INITVALUE_Pos) #define ETx_CMPR_CMP_Pos 0 /* À©Õ¹¶¨Ê±Æ÷±È½Ï¼Ä´æÆ÷ ¸Ã¼Ä´æÆ÷Óë¼ÆÊýÆ÷±È½Ï£¬Èô¼ÆÊýÖµ´óÓÚµÈÓڸüĴæÆ÷µÄÖµ£¬Ôò²úÉú¼ÆÊýÆ¥ÅäÐźÅÖÁÊä³ö¿ØÖÆÄ£¿é£¬²¢²úÉúÏàÓ¦Öжϡ£ */ #define ETx_CMPR_CMP_Msk (0xffffU << ETx_CMPR_CMP_Pos) #define ETx_IER_CMPIE_Pos 2 /* À©Õ¹¶¨Ê±Æ÷±È½ÏÖжÏʹÄÜ 1 = ʹÄÜ 0 = ½ûÖ¹ */ #define ETx_IER_CMPIE_Msk (0x1U << ETx_IER_CMPIE_Pos) #define ETx_IER_CAPIE_Pos 1 /* À©Õ¹¶¨Ê±Æ÷²¶×½ÖжÏʹÄÜ 1 = ʹÄÜ 0 = ½ûÖ¹ */ #define ETx_IER_CAPIE_Msk (0x1U << ETx_IER_CAPIE_Pos) #define ETx_IER_OVIE_Pos 0 /* À©Õ¹¶¨Ê±Æ÷3Òç³öÖжÏʹÄÜ 1 = ʹÄÜ 0 = ½ûÖ¹ */ #define ETx_IER_OVIE_Msk (0x1U << ETx_IER_OVIE_Pos) #define ETx_ISR_CMPIF_Pos 3 /* ±È½Ï״̬£¬Ð´1Çå0 1 =µ±Ç°¼ÆÊýÆ÷µÄÖµ´óÓÚµÈÓڱȽϼĴæÆ÷µÄÖµ 0 =µ±Ç°¼ÆÊýÆ÷µÄֵСÓڱȽϼĴæÆ÷µÄÖµ */ #define ETx_ISR_CMPIF_Msk (0x1U << ETx_ISR_CMPIF_Pos) #define ETx_ISR_EDGESTA_Pos 2 /* ²¶×½ÑØ״̬±êÖ¾ 1 = ²¶×½µ½ÏÂÑØ 0 = ²¶×½µ½ÉÏÑØ */ #define ETx_ISR_EDGESTA_Msk (0x1U << ETx_ISR_EDGESTA_Pos) #define ETx_ISR_CAPIF_Pos 1 /* À©Õ¹¶¨Ê±Æ÷²¶×½²úÉúÐźŠ1 = ²¶×½µ½Ö¸¶¨µÄÑØ 0 = δ²¶×½µ½Ö¸¶¨µÄÑØ */ #define ETx_ISR_CAPIF_Msk (0x1U << ETx_ISR_CAPIF_Pos) #define ETx_ISR_OVIF_Pos 0 /* À©Õ¹¶¨Ê±Æ÷3Òç³öÐźţ¬µ±¼ÆÊýÆ÷µÄÖµÓÉ0xFFFFÔÙÔö¼Óʱ½«ÖÃλ 1 = ²úÉú¼ÆÊýÒç³ö 0 = δ²úÉúÒç³ö */ #define ETx_ISR_OVIF_Msk (0x1U << ETx_ISR_OVIF_Pos) #define ETCNTx_CNT_Pos 0 #define ETCNTx_CNT_Msk (0xffffU << ETCNTx_CNT_Pos) //Macro_End /* Exported functions --------------------------------------------------------*/ extern void ETx_Deinit(ET_Type* ETx); /* Êä³ö¼«ÐÔÑ¡Ôñ (Output Polarity) 0£ºÊä³ö²»È¡·´ 1£ºÊä³öÈ¡·´ Ïà¹Øº¯Êý */ extern void ETx_CR_OPOL_Set(ET_Type* ETx, uint32_t SetValue); extern uint32_t ETx_CR_OPOL_Get(ET_Type* ETx); /* ÍⲿÒý½ÅÊäÈëÊý×ÖÂ˲¨Ê¹ÄÜ 1 = ´ò¿ªÒý½ÅÊäÈëÐźÅÊý×ÖÂ˲¨ 0 = ¹Ø±ÕÒý½ÅÊäÈëÐźÅÊý×ÖÂ˲¨ Ïà¹Øº¯Êý */ extern void ETx_CR_EXFLT_Set(ET_Type* ETx, uint32_t SetValue); extern uint32_t ETx_CR_EXFLT_Get(ET_Type* ETx); /* PWMÊä³ö¿ØÖÆ 1 = PWMÊä³öʹÄÜ 0 = PWMÊä³ö½ûÖ¹ Ïà¹Øº¯Êý */ extern void ETx_CR_PWM_Setable(ET_Type* ETx, FunState NewState); extern FunState ETx_CR_PWM_Getable(ET_Type* ETx); /* Æô¶¯¿ØÖÆ 1 = Æô¶¯¶¨Ê±Æ÷£¬ÔÚ¼ÆÊýÆ÷ģʽÏÂÆô¶¯Ê±½«¼ÆÊý³õÖµ¼ÓÔØÖÁ¼ÆÊýÆ÷ºÍ¹¤×÷¼Ä´æÆ÷£»ÔÚ²¶×½Ä£Ê½Ï£¬Æô¶¯Ê±¼ÆÊýÆ÷ÓÉÁ㿪ʼ×ÔÓɼÆÊý£¬¼ÆÊýµ½0xFFFFºó²úÉúÒç³öÐźÅÈ»ºóÓÉÁ㿪ʼÖØмÆÊý 0 = Í£Ö¹¼ÆÊýÆ÷¼ÆÊý Ïà¹Øº¯Êý */ extern void ETx_CR_CEN_Setable(ET_Type* ETx, FunState NewState); extern FunState ETx_CR_CEN_Getable(ET_Type* ETx); /* ¹¤×÷ģʽѡÔñ 1 = ²¶×½Ä£Ê½ 0 = ¶¨Ê±/¼ÆÊýģʽ Ïà¹Øº¯Êý */ extern void ETx_CR_MOD_Set(ET_Type* ETx, uint32_t SetValue); extern uint32_t ETx_CR_MOD_Get(ET_Type* ETx); /* Cascade Enable£¬À©Õ¹¶¨Ê±Æ÷¼¶ÁªÊ¹ÄÜ 1 = ET1£¨ET3£©ºÍET2£¨ET4£©¼¶Áª³É32bit¶¨Ê±Æ÷ 0 = 16bit¶¨Ê±Æ÷¶ÀÁ¢¹¤×÷ Ïà¹Øº¯Êý */ extern void ETx_CR_CASEN_Set(ET_Type* ETx, uint32_t SetValue); extern uint32_t ETx_CR_CASEN_Get(ET_Type* ETx); /* ¼ÆÊýģʽ²ÉÑØ·½Ê½Ñ¡Ôñ £¨¼ÆÊýʱÖÓÑ¡Ôñmcu_clkʱ¸ÃλÎÞЧ£¬×ÜÊDzÉÓÃmcu_clkʱÖÓÉÏÉýÑؼÆÊý£© 1 = ¼ÆÊýģʽ²ÉϽµÑØ 0 = ¼ÆÊýģʽ²ÉÉÏÉýÑØ Ïà¹Øº¯Êý */ extern void ETx_CR_EDGESEL_Set(ET_Type* ETx, uint32_t SetValue); extern uint32_t ETx_CR_EDGESEL_Get(ET_Type* ETx); /* ²¶×½Ä£Ê½¿ØÖÆ 1 = Âö¿í²¶×½ 0 = Âö³åÖÜÆÚ²¶×½ Ïà¹Øº¯Êý */ extern void ETx_CR_CAPMOD_Set(ET_Type* ETx, uint32_t SetValue); extern uint32_t ETx_CR_CAPMOD_Get(ET_Type* ETx); /* ´øÇåÁ㲶׽ģʽ¿ØÖÆ 1 = ʼþ´¥·¢²¶×½£ºÊ¹Äܺó¼ÆÊýÆ÷±£³Ö0£¬²¶×½µ½µÚÒ»¸öÓÐЧÑØÖ®ºótimer²Å¿ªÊ¼¼ÆÊý 0 = ²¶×½²»ÇåÁ㣬¼ÆÊýÆ÷Ò»Ö±×ÔÓɼÆÊý Ïà¹Øº¯Êý */ extern void ETx_CR_CAPCLR_Setable(ET_Type* ETx, FunState NewState); extern FunState ETx_CR_CAPCLR_Getable(ET_Type* ETx); /* µ¥´Î²¶×½¿ØÖÆ 1 = µ¥´Î²¶×½ÓÐЧ£¬ÔÚ²¶×½µ½Ò»´ÎÂö³åÖÜÆÚºó¼ÆÊýÆ÷Í£Ö¹£¬ÈôÐèÒªÔٴβ¶×½ÐèÖØÐÂÆô¶¯ 0 = Á¬Ðø²¶×½ Ïà¹Øº¯Êý */ extern void ETx_CR_CAPONCE_Set(ET_Type* ETx, uint32_t SetValue); extern uint32_t ETx_CR_CAPONCE_Get(ET_Type* ETx); /* ²¶×½ÑØÑ¡Ôñ 1 = ÖÜÆÚ²¶×½Ä£Ê½Ê±ÏÂÑز¶×½ 0 = ÖÜÆÚ²¶×½Ä£Ê½Ê±ÉÏÑز¶×½ Ïà¹Øº¯Êý */ extern void ETx_CR_CAPEDGE_Set(ET_Type* ETx, uint32_t SetValue); extern uint32_t ETx_CR_CAPEDGE_Get(ET_Type* ETx); /* ÄÚ²¿ÐźÅ2Ô´Ñ¡Ôñ(²¶×½Ô´) 1 = À©Õ¹¶¨Ê±Æ÷3µÄÄÚ²¿ÐźÅ2Ñ¡ÔñGroup1 0 = À©Õ¹¶¨Ê±Æ÷3µÄÄÚ²¿ÐźÅ2Ñ¡ÔñGroup2 Ïà¹Øº¯Êý */ extern void ETx_INSR_SIG2SEL_Set(ET_Type* ETx, uint32_t SetValue); extern uint32_t ETx_INSR_SIG2SEL_Get(ET_Type* ETx); /* ÄÚ²¿ÐźÅ1Ô´Ñ¡Ôñ£¨ÔÚ¼ÆÊýģʽϼÆÊýÔ´½öÓÉ´ËÑ¡Ôñ£¬²¶×½Ä£Ê½Ï¼ÆÊýÔ´£© 1 = À©Õ¹¶¨Ê±Æ÷3µÄÄÚ²¿ÐźÅ1Ñ¡ÔñGroup2 0 = À©Õ¹¶¨Ê±Æ÷3µÄÄÚ²¿ÐźÅ1Ñ¡ÔñGroup1 Ïà¹Øº¯Êý */ extern void ETx_INSR_SIG1SEL_Set(ET_Type* ETx, uint32_t SetValue); extern uint32_t ETx_INSR_SIG1SEL_Get(ET_Type* ETx); /* GROUP2 ÐźÅÑ¡Ôñ¿ØÖÆ ET1 000 = UART0_RX 001 = UART1_RX 010 = XTLF 011 = ET1_IN1 100 = ET1_IN2 101 = CMP1O£¨±È½ÏÆ÷1Êä³ö£© 110 = CMP2O£¨±È½ÏÆ÷2Êä³ö£© 111 = RCMF ET2 000 = UART2_RX 001 = UART3_RX 010 = XTLF 011 = ET2_IN1 100 = ET2_IN2 101 = CMP1O£¨±È½ÏÆ÷1Êä³ö£© 110 = CMP2O£¨±È½ÏÆ÷2Êä³ö£© 111 = RCMF ET3 000 = ET3_IN1 001 = XTLF 010 = UART4_RX 011 = UART5_RX 100 = RTCSEC 101~111 = RFU ET4 000 = ET4_IN1 001 = XTLF 010 = UART_RX2 011 = UART_RX0 100 = CMP1O£¨±È½ÏÆ÷1Êä³ö£© 101 = CMP2O£¨±È½ÏÆ÷2Êä³ö£© 110= RTCSEC 111= RCMF? Ïà¹Øº¯Êý */ extern void ETx_INSR_GRP2SEL_Set(ET_Type* ETx, uint32_t SetValue); extern uint32_t ETx_INSR_GRP2SEL_Get(ET_Type* ETx); /* GROUP1 ÐźÅÑ¡Ôñ¿ØÖÆ ET1 00 = APBCLK 01 = XTLF 10 = RCLP 11 = ET1_IN0 ET2 00 = APBCLK 01 = XTLF 10 = RCLP 11 = ET2_IN0 ET3 00 = APBCLK 01 = ET3_IN0 10 = RTCSEC 11 = RCLP ET4 00 = APBCLK 01 = ET4_IN0 10 = RTC64HZ 11 = RCMF Ïà¹Øº¯Êý */ extern void ETx_INSR_GRP1SEL_Set(ET_Type* ETx, uint32_t SetValue); extern uint32_t ETx_INSR_GRP1SEL_Get(ET_Type* ETx); /* ÊäÈëSignal1£¨¼ÆÊýÔ´£©µÄÔ¤·ÖƵ¼Ä´æÆ÷ 00±íʾ1·ÖƵ£¬FF±íʾ256·ÖƵ Ïà¹Øº¯Êý */ extern void ETx_PSCR1_Write(ET_Type* ETx, uint32_t SetValue); extern uint32_t ETx_PSCR1_Read(ET_Type* ETx); /* ÊäÈëSignal2£¨²¶×½Ô´£©µÄÔ¤·ÖƵ¼Ä´æÆ÷ 00±íʾ1·ÖƵ£¬FF±íʾ256·ÖƵ¡£ Ïà¹Øº¯Êý */ extern void ETx_PSCR2_Write(ET_Type* ETx, uint32_t SetValue); extern uint32_t ETx_PSCR2_Read(ET_Type* ETx); /* À©Õ¹¶¨Ê±Æ÷³õÖµ¼Ä´æÆ÷ Ïà¹Øº¯Êý */ extern void ETx_IVR_Write(ET_Type* ETx, uint32_t SetValue); extern uint32_t ETx_IVR_Read(ET_Type* ETx); /* À©Õ¹¶¨Ê±Æ÷±È½Ï¼Ä´æÆ÷ ¸Ã¼Ä´æÆ÷Óë¼ÆÊýÆ÷±È½Ï£¬Èô¼ÆÊýÖµ´óÓÚµÈÓڸüĴæÆ÷µÄÖµ£¬Ôò²úÉú¼ÆÊýÆ¥ÅäÐźÅÖÁÊä³ö¿ØÖÆÄ£¿é£¬²¢²úÉúÏàÓ¦Öжϡ£ Ïà¹Øº¯Êý */ extern void ETx_CMPR_Write(ET_Type* ETx, uint32_t SetValue); extern uint32_t ETx_CMPR_Read(ET_Type* ETx); /* À©Õ¹¶¨Ê±Æ÷±È½ÏÖжÏʹÄÜ 1 = ʹÄÜ 0 = ½ûÖ¹ Ïà¹Øº¯Êý */ extern void ETx_IER_CMPIE_Setable(ET_Type* ETx, FunState NewState); extern FunState ETx_IER_CMPIE_Getable(ET_Type* ETx); /* À©Õ¹¶¨Ê±Æ÷²¶×½ÖжÏʹÄÜ 1 = ʹÄÜ 0 = ½ûÖ¹ Ïà¹Øº¯Êý */ extern void ETx_IER_CAPIE_Setable(ET_Type* ETx, FunState NewState); extern FunState ETx_IER_CAPIE_Getable(ET_Type* ETx); /* À©Õ¹¶¨Ê±Æ÷3Òç³öÖжÏʹÄÜ 1 = ʹÄÜ 0 = ½ûÖ¹ Ïà¹Øº¯Êý */ extern void ETx_IER_OVIE_Setable(ET_Type* ETx, FunState NewState); extern FunState ETx_IER_OVIE_Getable(ET_Type* ETx); /* ±È½Ï״̬£¬Ð´1Çå0 1 =µ±Ç°¼ÆÊýÆ÷µÄÖµ´óÓÚµÈÓڱȽϼĴæÆ÷µÄÖµ 0 =µ±Ç°¼ÆÊýÆ÷µÄֵСÓڱȽϼĴæÆ÷µÄÖµ Ïà¹Øº¯Êý */ extern void ETx_ISR_CMPIF_Clr(ET_Type* ETx); extern FlagStatus ETx_ISR_CMPIF_Chk(ET_Type* ETx); /* ²¶×½ÑØ״̬±êÖ¾ 1 = ²¶×½µ½ÏÂÑØ 0 = ²¶×½µ½ÉÏÑØ */ extern FlagStatus ETx_ISR_EDGESTA_Chk(ET_Type* ETx); /* À©Õ¹¶¨Ê±Æ÷²¶×½²úÉúÐźŠ1 = ²¶×½µ½Ö¸¶¨µÄÑØ 0 = δ²¶×½µ½Ö¸¶¨µÄÑØ Ïà¹Øº¯Êý */ extern void ETx_ISR_CAPIF_Clr(ET_Type* ETx); extern FlagStatus ETx_ISR_CAPIF_Chk(ET_Type* ETx); /* À©Õ¹¶¨Ê±Æ÷3Òç³öÐźţ¬µ±¼ÆÊýÆ÷µÄÖµÓÉ0xFFFFÔÙÔö¼Óʱ½«ÖÃλ 1 = ²úÉú¼ÆÊýÒç³ö 0 = δ²úÉúÒç³ö Ïà¹Øº¯Êý */ extern void ETx_ISR_OVIF_Clr(ET_Type* ETx); extern FlagStatus ETx_ISR_OVIF_Chk(ET_Type* ETx); /*»ñÈ¡ET ¼ÆÊýÆ÷ÊýÖµ*/ extern uint32_t ETxCNT_CNTx_Read(ETCNT_Type* ETIMx); //Announce_End #ifdef __cplusplus } #endif #endif /*__FM33A0XXEV_ET_H */