From 6e3f1f560d618b37ee1a47fa2b0f682b70c3ef1c Mon Sep 17 00:00:00 2001
From: jinlicong <493886250@qq.com>
Date: Wed, 19 Jun 2024 17:25:45 +0800
Subject: [PATCH] 增加OTA协议
---
HARDWARE/UART/uart.c | 294 ++++++++++++++++++++++++++++++++++++++++++++++++----------
1 files changed, 244 insertions(+), 50 deletions(-)
diff --git a/HARDWARE/UART/uart.c b/HARDWARE/UART/uart.c
index e365a70..7a1c099 100644
--- a/HARDWARE/UART/uart.c
+++ b/HARDWARE/UART/uart.c
@@ -5,6 +5,14 @@
uint8_t RS485_read_data_recv_buff[RS485_READ_DATA_RECV_BUFF_LEN_MAX] = {0};
+uint8_t up_comm_recv_buff[UP_COMM_RECV_BUFF_LEN_MAX] = {0};
+uint8_t WRC_recv_buff[WRC_RECV_BUFF_LEN_MAX] = {0};
+
+UART_CTRL_PARA_T uart_ctrl_para_g = {
+ .WRC_rxto_flag = RESET,
+ .RS485_rxto_flag = RESET,
+ .UP_COMM_rxto_flag = RESET,
+};
u16 USART_RX_STA = 0; //����״̬���
//void Usmart_RecvDataProcess(UC_RECV_PARA_T *usmart_recv_para_p)
@@ -32,15 +40,15 @@
//��д�������,�ض���printf���������ڣ���˼����˵printfֱ����������ڣ���Ĭ�����������̨��
/*fputc*/
-int fputc(int c, FILE *f)
-{
- uint8_t ch;
- ch = c;
- UARTx_TXBUF_Write(UART0,ch);//���ʹ���
- while(RESET == UARTx_ISR_TXSE_Chk(UART0))
- ; //�ȴ��������
- return ch;
-}
+//int fputc(int c, FILE *f)
+//{
+// uint8_t ch;
+// ch = c;
+// UARTx_TXBUF_Write(UART0,ch);//���ʹ���
+// while(RESET == UARTx_ISR_TXSE_Chk(UART0))
+// ; //�ȴ��������
+// return ch;
+//}
//�ض���scanf���������� ��˼����˵���ܴ��ڷ����������ݣ���Ĭ���ǽ��ܿ���̨������
/*fgetc*/
@@ -62,6 +70,25 @@
}
}
+void UART1_IRQHandler(void)
+{
+ //ֻ��uart0��uart1�н��ճ�ʱ�ж�
+ if(UARTx_ISR_RXTO_Chk(UART1) == SET){
+ UARTx_ISR_RXTO_Clr(UART1);
+ uart_ctrl_para_g.RS485_rxto_flag = SET;
+ uart_ctrl_para_g.WRC_rxto_flag = SET;
+ }
+}
+
+//void UART5_IRQHandler(void)
+//{
+// //ֻ��uart0��uart1�н��ճ�ʱ�ж�
+// if(UARTx_ISR_RXTO_Chk(UART5) == SET){
+// UARTx_ISR_RXTO_Clr(UART5);
+// uart_ctrl_para_g.UP_COMM_rxto_flag = SET;
+// }
+//}
+
void RS485_read_data_uart_Init(uint32_t BaudRate,UART_ParityBitTypeDef ParityBit,UART_StopBitTypeDef StopBit)
{
@@ -74,8 +101,11 @@
AltFunIO(RS485_READ_DATA_RX_PORT, RS485_READ_DATA_RX_PIN, ALTFUN_NORMAL);
//UART����ʱ��Դѡ�� ֻ��UART0��1��Ҫѡ�� ����UART�˿��ݲ���Ҫ ֱ��ע�ͼ���
- if((RS485_READ_DATA_UARTX==UART0)||(RS485_READ_DATA_UARTX==UART1))
+ if(RS485_READ_DATA_UARTX==UART0)
UART_para.ClockSrc = CMU_OPCCR1_UART0CKS_APBCLK; //UART0����ʱ��ѡ��
+ else if(RS485_READ_DATA_UARTX==UART1)
+ UART_para.ClockSrc = CMU_OPCCR1_UART1CKS_APBCLK; //UART1����ʱ��ѡ��
+
UART_para.BaudRate = BaudRate;
UART_para.ParityBit = ParityBit; //��żУ��
@@ -88,13 +118,19 @@
CMU_GetClocksFreq(&CMU_Clocks); //��ȡϵͳ��ʱ��Ƶ��
UART_SInit(RS485_READ_DATA_UARTX, &UART_para,&CMU_Clocks); //��ʼ��uart
-// UARTx_IER_RXBF_IE_Setable(MODBUS_UART, ENABLE);//���ջ������ж�ʹ�� ��Ҫʹ�ý����жϴ˴�����
-// UARTx_IER_TXSE_IE_Setable(MODBUS_UART, ENABLE)��//���ͻ�����ҷ�����λ�Ĵ������ж�ʹ�� ��Ҫʹ�÷����жϴ˴�����
+// UARTx_IER_RXBF_IE_Setable(RS485_READ_DATA_UARTX, ENABLE);//���ջ������ж�ʹ�� ��Ҫʹ�ý����жϴ˴�����
+// UARTx_IER_TXSE_IE_Setable(RS485_READ_DATA_UARTX, ENABLE)��//���ͻ�����ҷ�����λ�Ĵ������ж�ʹ�� ��Ҫʹ�÷����жϴ˴�����
- /*NVIC�ж����ȼ��Լ��Ƿ���ж�����*/
NVIC_DisableIRQ(RS485_READ_DATA_UARTX_IRQn);
-// NVIC_SetPriority(UART0_IRQn,2);//�ж����ȼ�����
-// NVIC_EnableIRQ(UART0_IRQn); //�жϷ�������
+ UARTx_TODR_RXTO_LEN_Set(RS485_READ_DATA_UARTX, 255);//ֻ��uart0��uart1�н��ճ�ʱ�ж�
+ UARTx_ISR_RXTO_Clr(RS485_READ_DATA_UARTX);
+ UARTx_IER_RXTO_IE_Setable(RS485_READ_DATA_UARTX, ENABLE);
+// NVIC_EnableIRQ(RS485_READ_DATA_UARTX_IRQn);
+ UARTx_CSR_RXTOEN_Setable(RS485_READ_DATA_UARTX, ENABLE);
+ /*NVIC�ж����ȼ��Լ��Ƿ���ж�����*/
+// NVIC_DisableIRQ(RS485_READ_DATA_UARTX_IRQn);
+ NVIC_SetPriority(RS485_READ_DATA_UARTX_IRQn,2);//�ж����ȼ�����
+ NVIC_EnableIRQ(RS485_READ_DATA_UARTX_IRQn); //�жϷ�������
UARTx_CSR_RXEN_Setable(RS485_READ_DATA_UARTX, ENABLE); //����ʹ��
UARTx_CSR_TXEN_Setable(RS485_READ_DATA_UARTX, ENABLE); //����ʹ��
@@ -110,7 +146,7 @@
CMU_PERCLK_SetableEx(DMACLK, ENABLE);//DMAʱ��ʹ��
DMA_GCR_DMAEN_Setable(ENABLE);//DMA��ʹ��
- DMA_InitStructure.CHx = DMA_CH3;//DMAͨ��������
+ DMA_InitStructure.CHx = RS485_READ_DATA_DMA_CHX;//DMAͨ��������
DMA_InitStructure.CHxPRI = DMA_CHxCR_CHxPRI_HIGH;//ͨ�����ȼ�����
DMA_InitStructure.CHxINC = DMA_CHxCR_CHxINC_INCREASE;//ͨ����ַ��������
DMA_InitStructure.CHxSSEL = DMA_CHxCR_CH3SSEL_UART1_RX;//����ͨ��ѡ��
@@ -130,57 +166,215 @@
// DMA_CHxCR_CHxFTIE_Setable(MODBUS_DMA_RX_CHANNEL,ENABLE);//ͨ����������ж�ʹ��
- DMA_ISR_DMACHFT_Clr(DMA_CH3);
+ DMA_ISR_DMACHFT_Clr(RS485_READ_DATA_DMA_CHX);
DMA_Init(&DMA_InitStructure);//DMA���ò���д��
}
void RS485_read_data_RX_DMA_CH3_reload(void)
{
- DMA_ISR_DMACHFT_Clr(DMA_CH3);
- DMA_CHxCR_ChxEN_Setable(DMA_CH3, DISABLE); //ͨ��ʧ��
+ DMA_ISR_DMACHFT_Clr(RS485_READ_DATA_DMA_CHX);
+ DMA_CHxCR_ChxEN_Setable(RS485_READ_DATA_DMA_CHX, DISABLE); //ͨ��ʧ��
memset(RS485_read_data_recv_buff,0,sizeof(RS485_read_data_recv_buff));
- DMA_CHxMAR_Write(DMA_CH3, (uint32)RS485_read_data_recv_buff);
+ DMA_CHxMAR_Write(RS485_READ_DATA_DMA_CHX, (uint32)RS485_read_data_recv_buff);
- DMA_CHxCR_ChxEN_Setable(DMA_CH3, ENABLE); //ͨ��ʹ��
+ DMA_CHxCR_ChxEN_Setable(RS485_READ_DATA_DMA_CHX, ENABLE); //ͨ��ʹ��
}
-void Uart5_RX_DMA_CH5_Init(void)
+//��λ���ӿ�
+void up_comm_uart_Init(uint32_t BaudRate,UART_ParityBitTypeDef ParityBit,UART_StopBitTypeDef StopBit)
{
-// DMA_InitTypeDef DMA_InitStructure;//DMA��ʼ�������ṹ��
-//
-// CMU_PERCLK_SetableEx(DMACLK, ENABLE);//DMAʱ��ʹ��
-// DMA_GCR_DMAEN_Setable(ENABLE);//DMA��ʹ��
-//
-// DMA_InitStructure.CHx = DMA_CH5;//DMAͨ��������
-// DMA_InitStructure.CHxPRI = DMA_CHxCR_CHxPRI_HIGH;//ͨ�����ȼ�����
-// DMA_InitStructure.CHxINC = DMA_CHxCR_CHxINC_INCREASE;//ͨ����ַ��������
-// DMA_InitStructure.CHxSSEL = DMA_CHxCR_CH5SSEL_UART5_RX;//����ͨ��ѡ��
-// DMA_InitStructure.CHxDIR = DMA_CHxCR_DIR_TO_RAM;//���ݴ��䷽������
-// DMA_InitStructure.CHxTSIZE = GPRS_RECV_LEN_MAX - 1;//ͨ�����䳤��
-// DMA_InitStructure.CHxRAMAD = (uint32)gprs_module_para_g.gprs_recv_buf;//Ŀ���ַ
-// DMA_InitStructure.CHxBDW = DMA_CHxCR_BDW_8BITS;//ͨ���������
-//
-// DMA_InitStructure.CHxFTIE = DISABLE; //ͨ����������ж�ʹ��
-// DMA_InitStructure.CHxHTIE = DISABLE; //ͨ���������ն�ʹ��
-
-// DMA_InitStructure.CHxEN = ENABLE; //ͨ��ʹ��
-//
-// NVIC_DisableIRQ(DMA_IRQn);
-//// NVIC_SetPriority(DMA_IRQn,3);//�ж����ȼ�����
-//// NVIC_EnableIRQ(DMA_IRQn);
-//
-//// DMA_CHxCR_CHxFTIE_Setable(MODBUS_DMA_RX_CHANNEL,ENABLE);//ͨ����������ж�ʹ��
-
-// DMA_ISR_DMACHFT_Clr(DMA_CH5);
-
-// DMA_Init(&DMA_InitStructure);//DMA���ò���д��
+ UART_SInitTypeDef UART_para;//UART��ʼ���ṹ��
+ CMU_ClocksType CMU_Clocks;//ϵͳ��ʱ��Ƶ�ʽṹ�� �ڴ�����㲨�����й�
+
+ /*UART0 IO ����*/
+ CMU_PERCLK_SetableEx(PADCLK, ENABLE); //PADʱ�ӣ�GPIO��ʹ�ܺ���
+ AltFunIO(UP_COMM_TX_PORT, UP_COMM_TX_PIN, ALTFUN_NORMAL);
+ AltFunIO(UP_COMM_RX_PORT, UP_COMM_RX_PIN, ALTFUN_NORMAL);
+
+ OutputIO(UP_COMM_RE_PORT,UP_COMM_RE_PIN,OUT_PUSHPULL);
+ UP_COMM_RE_RECV_EN;
+
+ //UART����ʱ��Դѡ�� ֻ��UART0��1��Ҫѡ�� ����UART�˿��ݲ���Ҫ ֱ��ע�ͼ���
+ if(UP_COMM_UARTX==UART0)
+ UART_para.ClockSrc = CMU_OPCCR1_UART0CKS_APBCLK; //UART0����ʱ��ѡ��
+ else if(UP_COMM_UARTX==UART1)
+ UART_para.ClockSrc = CMU_OPCCR1_UART1CKS_APBCLK; //UART1����ʱ��ѡ��
+
+ UART_para.BaudRate = BaudRate;
+ UART_para.ParityBit = ParityBit; //��żУ��
+ if(ParityBit==NONE)
+ UART_para.DataBit = Eight8Bit; //�����
+ else
+ UART_para.DataBit = Nine9Bit; //�����
+ UART_para.StopBit = StopBit; //ֹͣλ
+
+ CMU_GetClocksFreq(&CMU_Clocks); //��ȡϵͳ��ʱ��Ƶ��
+ UART_SInit(UP_COMM_UARTX, &UART_para,&CMU_Clocks); //��ʼ��uart
+
+// UARTx_IER_RXBF_IE_Setable(UP_COMM_UARTX, ENABLE);//���ջ������ж�ʹ�� ��Ҫʹ�ý����жϴ˴�����
+// UARTx_IER_TXSE_IE_Setable(UP_COMM_UARTX, ENABLE)��//���ͻ�����ҷ�����λ�Ĵ������ж�ʹ�� ��Ҫʹ�÷����жϴ˴�����
+// NVIC_DisableIRQ(UP_COMM_UARTX_IRQn);
+// UARTx_TODR_RXTO_LEN_Set(UP_COMM_UARTX, 255);//ֻ��uart0��uart1�н��ճ�ʱ�ж�
+// UARTx_ISR_RXTO_Clr(UP_COMM_UARTX);
+// UARTx_IER_RXTO_IE_Setable(UP_COMM_UARTX, ENABLE);
+//// NVIC_EnableIRQ(UP_COMM_UARTX_IRQn);
+// UARTx_CSR_RXTOEN_Setable(UP_COMM_UARTX, ENABLE);
+
+
+ /*NVIC�ж����ȼ��Լ��Ƿ���ж�����*/
+ NVIC_DisableIRQ(UP_COMM_UARTX_IRQn);
+// NVIC_SetPriority(UP_COMM_UARTX_IRQn,4);//�ж����ȼ�����
+// NVIC_EnableIRQ(UP_COMM_UARTX_IRQn); //�жϷ�������
+
+ UARTx_CSR_RXEN_Setable(UP_COMM_UARTX, ENABLE); //����ʹ��
+ UARTx_CSR_TXEN_Setable(UP_COMM_UARTX, ENABLE); //����ʹ��
+
+ UARTx_ISR_RXBF_Clr(UP_COMM_UARTX);
}
+void up_comm_RX_DMA_CH2_Init(void)
+{
+ DMA_InitTypeDef DMA_InitStructure;//DMA��ʼ�������ṹ��
+
+ CMU_PERCLK_SetableEx(DMACLK, ENABLE);//DMAʱ��ʹ��
+ DMA_GCR_DMAEN_Setable(ENABLE);//DMA��ʹ��
+
+ DMA_InitStructure.CHx = UP_COMM_DMA_CHX;//DMAͨ��������
+ DMA_InitStructure.CHxPRI = DMA_CHxCR_CHxPRI_HIGH;//ͨ�����ȼ�����
+ DMA_InitStructure.CHxINC = DMA_CHxCR_CHxINC_INCREASE;//ͨ����ַ��������
+ DMA_InitStructure.CHxSSEL = DMA_CHxCR_CH2SSEL_UART5_RX;//����ͨ��ѡ��
+ DMA_InitStructure.CHxDIR = DMA_CHxCR_DIR_TO_RAM;//���ݴ��䷽������
+ DMA_InitStructure.CHxTSIZE = UP_COMM_RECV_BUFF_LEN_MAX - 1;//ͨ�����䳤��
+ DMA_InitStructure.CHxRAMAD = (uint32)up_comm_recv_buff;//Ŀ���ַ
+ DMA_InitStructure.CHxBDW = DMA_CHxCR_BDW_8BITS;//ͨ���������
+
+ DMA_InitStructure.CHxFTIE = DISABLE; //ͨ����������ж�ʹ��
+ DMA_InitStructure.CHxHTIE = DISABLE; //ͨ���������ն�ʹ��
+
+ DMA_InitStructure.CHxEN = ENABLE; //ͨ��ʹ��
+
+ NVIC_DisableIRQ(DMA_IRQn);
+// NVIC_SetPriority(DMA_IRQn,3);//�ж����ȼ�����
+// NVIC_EnableIRQ(DMA_IRQn);
+
+// DMA_CHxCR_CHxFTIE_Setable(MODBUS_DMA_RX_CHANNEL,ENABLE);//ͨ����������ж�ʹ��
+
+ DMA_ISR_DMACHFT_Clr(UP_COMM_DMA_CHX);
+
+ DMA_Init(&DMA_InitStructure);//DMA���ò���д��
+}
+
+void up_comm_RX_DMA_CH2_reload(void)
+{
+ DMA_ISR_DMACHFT_Clr(UP_COMM_DMA_CHX);
+ DMA_CHxCR_ChxEN_Setable(UP_COMM_DMA_CHX, DISABLE); //ͨ��ʧ��
+
+ memset(up_comm_recv_buff,0,sizeof(up_comm_recv_buff));
+
+ DMA_CHxMAR_Write(UP_COMM_DMA_CHX, (uint32)up_comm_recv_buff);
+
+ DMA_CHxCR_ChxEN_Setable(UP_COMM_DMA_CHX, ENABLE); //ͨ��ʹ��
+}
+
+
+void WRC_uart_Init(uint32_t BaudRate,UART_ParityBitTypeDef ParityBit,UART_StopBitTypeDef StopBit)
+{
+ UART_SInitTypeDef UART_para;//UART��ʼ���ṹ��
+ CMU_ClocksType CMU_Clocks;//ϵͳ��ʱ��Ƶ�ʽṹ�� �ڴ�����㲨�����й�
+
+ /*UART0 IO ����*/
+ CMU_PERCLK_SetableEx(PADCLK, ENABLE); //PADʱ�ӣ�GPIO��ʹ�ܺ���
+ AltFunIO(WRC_TX_PORT, WRC_TX_PIN, ALTFUN_NORMAL);
+ AltFunIO(WRC_RX_PORT, WRC_RX_PIN, ALTFUN_NORMAL);
+
+ //UART����ʱ��Դѡ�� ֻ��UART0��1��Ҫѡ�� ����UART�˿��ݲ���Ҫ ֱ��ע�ͼ���
+ if(WRC_UARTX==UART0)
+ UART_para.ClockSrc = CMU_OPCCR1_UART0CKS_APBCLK; //UART0����ʱ��ѡ��
+ else if(WRC_UARTX==UART1)
+ UART_para.ClockSrc = CMU_OPCCR1_UART1CKS_APBCLK; //UART1����ʱ��ѡ��
+
+ UART_para.BaudRate = BaudRate;
+ UART_para.ParityBit = ParityBit; //��żУ��
+ if(ParityBit==NONE)
+ UART_para.DataBit = Eight8Bit; //�����
+ else
+ UART_para.DataBit = Nine9Bit; //�����
+ UART_para.StopBit = StopBit; //ֹͣλ
+
+ CMU_GetClocksFreq(&CMU_Clocks); //��ȡϵͳ��ʱ��Ƶ��
+ UART_SInit(WRC_UARTX, &UART_para,&CMU_Clocks); //��ʼ��uart
+
+// UARTx_IER_RXBF_IE_Setable(WRC_UARTX, ENABLE);//���ջ������ж�ʹ�� ��Ҫʹ�ý����жϴ˴�����
+// UARTx_IER_TXSE_IE_Setable(WRC_UARTX, ENABLE)��//���ͻ�����ҷ�����λ�Ĵ������ж�ʹ�� ��Ҫʹ�÷����жϴ˴�����
+
+ NVIC_DisableIRQ(WRC_UARTX_IRQn);
+ UARTx_TODR_RXTO_LEN_Set(WRC_UARTX, 255);//ֻ��uart0��uart1�н��ճ�ʱ�ж�
+ UARTx_ISR_RXTO_Clr(WRC_UARTX);
+ UARTx_IER_RXTO_IE_Setable(WRC_UARTX, ENABLE);
+// NVIC_EnableIRQ(WRC_UARTX_IRQn);
+ UARTx_CSR_RXTOEN_Setable(WRC_UARTX, ENABLE);
+
+ /*NVIC�ж����ȼ��Լ��Ƿ���ж�����*/
+// NVIC_DisableIRQ(WRC_UARTX_IRQn);
+ NVIC_SetPriority(WRC_UARTX_IRQn,2);//�ж����ȼ�����
+ NVIC_EnableIRQ(WRC_UARTX_IRQn); //�жϷ�������
+
+ UARTx_CSR_RXEN_Setable(WRC_UARTX, ENABLE); //����ʹ��
+ UARTx_CSR_TXEN_Setable(WRC_UARTX, ENABLE); //����ʹ��
+
+ UARTx_ISR_RXBF_Clr(WRC_UARTX);
+}
+
+
+void WRC_RX_DMA_CH3_Init(void)
+{
+ DMA_InitTypeDef DMA_InitStructure;//DMA��ʼ�������ṹ��
+
+ CMU_PERCLK_SetableEx(DMACLK, ENABLE);//DMAʱ��ʹ��
+ DMA_GCR_DMAEN_Setable(ENABLE);//DMA��ʹ��
+
+ DMA_InitStructure.CHx = WRC_DMA_CHX;//DMAͨ��������
+ DMA_InitStructure.CHxPRI = DMA_CHxCR_CHxPRI_HIGH;//ͨ�����ȼ�����
+ DMA_InitStructure.CHxINC = DMA_CHxCR_CHxINC_INCREASE;//ͨ����ַ��������
+ DMA_InitStructure.CHxSSEL = DMA_CHxCR_CH3SSEL_UART1_RX;//����ͨ��ѡ��
+ DMA_InitStructure.CHxDIR = DMA_CHxCR_DIR_TO_RAM;//���ݴ��䷽������
+ DMA_InitStructure.CHxTSIZE = WRC_RECV_BUFF_LEN_MAX - 1;//ͨ�����䳤��
+ DMA_InitStructure.CHxRAMAD = (uint32)WRC_recv_buff;//Ŀ���ַ
+ DMA_InitStructure.CHxBDW = DMA_CHxCR_BDW_8BITS;//ͨ���������
+
+ DMA_InitStructure.CHxFTIE = DISABLE; //ͨ����������ж�ʹ��
+ DMA_InitStructure.CHxHTIE = DISABLE; //ͨ���������ն�ʹ��
+
+ DMA_InitStructure.CHxEN = ENABLE; //ͨ��ʹ��
+
+ NVIC_DisableIRQ(DMA_IRQn);
+// NVIC_SetPriority(DMA_IRQn,3);//�ж����ȼ�����
+// NVIC_EnableIRQ(DMA_IRQn);
+
+// DMA_CHxCR_CHxFTIE_Setable(MODBUS_DMA_RX_CHANNEL,ENABLE);//ͨ����������ж�ʹ��
+
+ DMA_ISR_DMACHFT_Clr(WRC_DMA_CHX);
+
+ DMA_Init(&DMA_InitStructure);//DMA���ò���д��
+}
+
+void WRC_RX_DMA_CH3_reload(void)
+{
+ DMA_ISR_DMACHFT_Clr(WRC_DMA_CHX);
+ DMA_CHxCR_ChxEN_Setable(WRC_DMA_CHX, DISABLE); //ͨ��ʧ��
+
+ memset(WRC_recv_buff,0,sizeof(WRC_recv_buff));
+
+ DMA_CHxMAR_Write(WRC_DMA_CHX, (uint32)WRC_recv_buff);
+
+ DMA_CHxCR_ChxEN_Setable(WRC_DMA_CHX, ENABLE); //ͨ��ʹ��
+}
+
/*��ͨ������ʽ����������*/
--
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