From 72def895431ad7a08e635b11f3da738e2b2c4618 Mon Sep 17 00:00:00 2001
From: wujiazhi <1147861305@qq.com>
Date: Thu, 13 Jun 2024 11:31:04 +0800
Subject: [PATCH] add lower model test
---
HARDWARE/SPI/SPI.c | 63 +++++++++++++------------------
1 files changed, 27 insertions(+), 36 deletions(-)
diff --git a/HARDWARE/SPI/SPI.c b/HARDWARE/SPI/SPI.c
index 65cb29a..d8761c7 100644
--- a/HARDWARE/SPI/SPI.c
+++ b/HARDWARE/SPI/SPI.c
@@ -1,56 +1,46 @@
#include "spi.h"
#include "gpio.h"
-void SPI3_Init(void)
+void SPI0_Init(void)
{
CMU_PERCLK_SetableEx(PADCLK, ENABLE); //PADʱ�ӣ�GPIO��ʹ�ܺ���
// AltFunIO(GPIOF, GPIO_Pin_15, ALTFUN_NORMAL); // SSN
- AltFunIO(SPI3_PORT, SPI3_SCK_PIN, ALTFUN_NORMAL); // SCK
- AltFunIO(SPI3_PORT, SPI3_MISO_PIN, ALTFUN_NORMAL); // MISO
- AltFunIO(SPI3_PORT, SPI3_MOSI_PIN, ALTFUN_NORMAL); // MOSI
+ AltFunIO(SPI0_PORT, SPI0_SCK_PIN, ALTFUN_NORMAL); // SCK
+ AltFunIO(SPI0_PORT, SPI0_MISO_PIN, ALTFUN_NORMAL); // MISO
+ AltFunIO(SPI0_PORT, SPI0_MOSI_PIN, ALTFUN_NORMAL); // MOSI
- CMU_PERCLK_SetableEx(SPI3CLK, ENABLE); //����SPI3����ʱ��
+ CMU_PERCLK_SetableEx(SPI0CLK, ENABLE); //����SPI0����ʱ��
- SPIx_CR1_IOSWAP_Set(SPI3, SPIx_CR1_IOSWAP_DEFAULT); // MISO��MOSIĬ������ ������
- SPIx_CR1_MM_Set(SPI3, SPIx_CR1_MM_MASTER); //masterģʽ
- SPIx_CR1_WAIT_Set(SPI3, SPIx_CR1_WAIT_1WAIT); // ÿ������һ֡�����һ��CLK
- SPIx_CR1_BAUD_Set(SPI3, SPIx_CR1_BAUD_DIV4); //����������Ϊ����ʱ��2��Ƶ
- SPIx_CR1_LSBF_Set(SPI3, SPIx_CR1_LSBF_MSB); //֡��ʽ�ȷ���MSB
- SPIx_CR1_CPHOL_Set(SPI3, SPIx_CR1_CPHOL_LOW); //CLKֹͣ�ڵ͵�ƽ
- SPIx_CR1_CPHA_Set(SPI3, SPIx_CR1_CPHA_1CLOCK); //��һ��ʱ�ӱ��ز�
- SPIx_CR2_SSNSEN_Setable(SPI3, DISABLE); //SSN��Ӳ������
+ SPIx_CR1_IOSWAP_Set(SPI0, SPIx_CR1_IOSWAP_DEFAULT); // MISO��MOSIĬ������ ������
+ SPIx_CR1_MM_Set(SPI0, SPIx_CR1_MM_MASTER); //masterģʽ
+ SPIx_CR1_WAIT_Set(SPI0, SPIx_CR1_WAIT_1WAIT); // ÿ������һ֡�����һ��CLK
+ SPIx_CR1_BAUD_Set(SPI0, SPIx_CR1_BAUD_DIV4); //����������Ϊ����ʱ��2��Ƶ
+ SPIx_CR1_LSBF_Set(SPI0, SPIx_CR1_LSBF_MSB); //֡��ʽ�ȷ���MSB
+ SPIx_CR1_CPHOL_Set(SPI0, SPIx_CR1_CPHOL_LOW); //CLKֹͣ�ڵ͵�ƽ
+ SPIx_CR1_CPHA_Set(SPI0, SPIx_CR1_CPHA_1CLOCK); //��һ��ʱ�ӱ��ز�
+ SPIx_CR2_SSNSEN_Setable(SPI0, DISABLE); //SSN��Ӳ������
- SPIx_CR2_RXO_Setable(SPI3, DISABLE); //SPI����Ϊȫ˫��
- SPIx_CR2_DLEN_Set(SPI3, SPIx_CR2_DLEN_8BIT); //ͨ�������ֳ�8bit
- SPIx_CR2_HALFDUPLEX_Set(SPI3, SPIx_CR2_HALFDUPLEX_SPI); //SPI����Ϊ��SPIģʽ
- SPIx_CR2_SSNM_Set(SPI3, SPIx_CR2_SSNM_LOW); //ÿ�η���master��ssn���ֵ�
- SPIx_CR2_TXO_AC_Setable(SPI3, DISABLE); //�ر�TXONLY�Զ���0
- SPIx_CR2_TXO_Setable(SPI3, DISABLE); //�ر�TXONLYģʽ
- // SPIx_CR2_SSN_Set(SPI3, SPIx_CR2_SSN_HIGH); //SSNSENΪ��ʱSNN����ߵ�ƽ
+ SPIx_CR2_RXO_Setable(SPI0, DISABLE); //SPI����Ϊȫ˫��
+ SPIx_CR2_DLEN_Set(SPI0, SPIx_CR2_DLEN_8BIT); //ͨ�������ֳ�8bit
+ SPIx_CR2_HALFDUPLEX_Set(SPI0, SPIx_CR2_HALFDUPLEX_SPI); //SPI����Ϊ��SPIģʽ
+ SPIx_CR2_SSNM_Set(SPI0, SPIx_CR2_SSNM_LOW); //ÿ�η���master��ssn���ֵ�
+ SPIx_CR2_TXO_AC_Setable(SPI0, DISABLE); //�ر�TXONLY�Զ���0
+ SPIx_CR2_TXO_Setable(SPI0, DISABLE); //�ر�TXONLYģʽ
+ // SPIx_CR2_SSN_Set(SPI0, SPIx_CR2_SSN_HIGH); //SSNSENΪ��ʱSNN����ߵ�ƽ
- SPIx_CR3_SERRC_Clr(SPI3); //����ӻ������־
- SPIx_CR3_MERRC_Clr(SPI3); //������������־
- SPIx_CR3_RXBFC_Clr(SPI3); //���RXBUF
- SPIx_CR3_TXBFC_Clr(SPI3); //���TXBUF
+ SPIx_CR3_SERRC_Clr(SPI0); //����ӻ������־
+ SPIx_CR3_MERRC_Clr(SPI0); //������������־
+ SPIx_CR3_RXBFC_Clr(SPI0); //���RXBUF
+ SPIx_CR3_TXBFC_Clr(SPI0); //���TXBUF
- SPIx_CR2_SPIEN_Setable(SPI3, ENABLE); //ʹ��SPI3
+ SPIx_CR2_SPIEN_Setable(SPI0, ENABLE); //ʹ��SPI0
}
-void SPI3_sleep(void)
-{
- CMU_PERCLK_SetableEx(SPI3CLK, DISABLE); //����SPI3����ʱ��
-
- SPIx_CR2_SPIEN_Setable(SPI3, DISABLE); //ʧ��SPI3
-
- CloseIO(SPI3_PORT, SPI3_SCK_PIN); // SCK
- CloseIO(SPI3_PORT, SPI3_MISO_PIN); // MISO
- CloseIO(SPI3_PORT, SPI3_MOSI_PIN); // MOSI
-}
-
+//-------------------------------------------------------------------------
uint8_t SpiWriteAndRead(uint32_t data)
{
SPIx_TXBUF_Write(SPI3, data);
@@ -60,6 +50,7 @@
return data;
}
+//----------------------------------------------------------------------
void SpiWrite(uint8_t *data, uint32_t length)
{
--
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