From 72def895431ad7a08e635b11f3da738e2b2c4618 Mon Sep 17 00:00:00 2001
From: wujiazhi <1147861305@qq.com>
Date: Thu, 13 Jun 2024 11:31:04 +0800
Subject: [PATCH] add lower model test
---
HARDWARE/ADC/ADC.c | 326 ++++++++++++++++++++++++-----------------------------
1 files changed, 149 insertions(+), 177 deletions(-)
diff --git a/HARDWARE/ADC/ADC.c b/HARDWARE/ADC/ADC.c
index 1f82dda..478098a 100644
--- a/HARDWARE/ADC/ADC.c
+++ b/HARDWARE/ADC/ADC.c
@@ -1,229 +1,201 @@
#include "adc.h"
#include "gpio.h"
+#include "power_manage.h"
+// �ڲ��ۼ� �¶�б��
+// float const_TmpeK = 4.5295; //0X640 ADC�
+// float const_30_top = 30.0;
-//�ڲ��ۼ� �¶�б��
-//float const_TmpeK = 4.5295; //0X640 ADC�
-//float const_30_top = 30.0;
-
-
-//�ⲿ�ۼ� �¶�б��
-float const_TmpeK_14BIT = 23.0247; //14BIT ADC�
-float const_30_top = 30.0;
-
+// �ⲿ�ۼ� �¶�б��
+float const_TmpeK_14BIT = 23.0247; // 14BIT ADC�
+float const_30_top = 30.0;
void ADC_LithIO_Init(void)
{
- CMU_PERCLK_SetableEx(PADCLK, ENABLE); //PADʱ�ӣ�GPIO��ʹ�ܺ���
-// AnalogIO(LIT_PWR_UNDER_PORT,LIT_PWR_UNDER_PIN);//ADC_5
-// GPIOx_ANEN_Setable(LIT_PWR_UNDER_PORT,LIT_PWR_UNDER_PIN,ENABLE);
- AnalogIO(LIT_ADC_PORT,LIT_ADC_PIN);//ADC_IN4
- GPIOx_ANEN_Setable(LIT_ADC_PORT,LIT_ADC_PIN,ENABLE);
-
+ CMU_PERCLK_SetableEx(PADCLK, ENABLE); // PADʱ�ӣ�GPIO��ʹ�ܺ���
+ // AnalogIO(LIT_PWR_UNDER_PORT,LIT_PWR_UNDER_PIN);//ADC_5
+ // GPIOx_ANEN_Setable(LIT_PWR_UNDER_PORT,LIT_PWR_UNDER_PIN,ENABLE);
+ AnalogIO(LIT_ADC_PORT, LIT_ADC_PIN); // ADC_IN4
+ GPIOx_ANEN_Setable(LIT_ADC_PORT, LIT_ADC_PIN, ENABLE);
}
void ADC_AlkaIO_Init(void)
{
- CMU_PERCLK_SetableEx(PADCLK, ENABLE); //PADʱ�ӣ�GPIO��ʹ�ܺ���
- AnalogIO_H(ALK_ADC_PIN);//ADC_IN8
-// GPIOx_ANEN_Setable(ALK_ADC_PORT,ALK_ADC_PIN,ENABLE); //?û��H�ڣ���ʱ��֪����ô����
+ CMU_PERCLK_SetableEx(PADCLK, ENABLE); // PADʱ�ӣ�GPIO��ʹ�ܺ���
+ AnalogIO(ALK_ADC_PORT, ALK_ADC_PIN); // ADC_IN8
+ GPIOx_ANEN_Setable(ALK_ADC_PORT, ALK_ADC_PIN, ENABLE);
}
void ADC_IN5_Init(void)
{
- CDIF_CR_INTF_EN_Setable(ENABLE); //���Դ��ӿ�ʹ��
- VRTC_Init_RCMF_Trim();
- VRTC_RCMFCR_EN_Setable(ENABLE);
- VRTC_ADCCR_CKS_Set(VRTC_ADCCR_CKS_RCMF_2); //ADC����ʱ��ѡ��
- VRTC_ADCCR_CKE_Setable(ENABLE); //ADC����ʱ��ʹ��
- ADC_CFGR_BUFSEL_Set(ADC_CFGR_BUFSEL_ADC_IN5); //ADC����ͨ��ѡ��
-
- ADC_CFGR_BUFEN_Setable(ENABLE); //ADC����ͨ��bufferʹ��/��ֹ
- ADC_CR_MODE_Set(ADC_CR_MODE_EXTERNAL); //ADC����ģʽѡ���ⲿ�ۼ���
- ADC_CR_RSTCTRL_EN_Setable(ENABLE); //����������ⲿ��λ
- ADC_CFGR_ACC_PERIOD_Set(ADC_CFGR_ACC_PERIOD_14BITS); //�ⲿ�ۼ����ۼ���������
- ADC_CR_HPEN_Set(ADC_CR_HPEN_1MHZ);
-
- ADC_TRIM_Write(0X7FF); //adcƵ��1M ʱ ����ʱ��4ms
-// ADC_TRIM_Write(0X3FF); //adcƵ��1M ʱ ����ʱ��2ms
-// ADC_TRIM_Write(0X1FF); //adcƵ��1M ʱ ����ʱ��1ms
-
- ADC_CR_ACC_IE_Setable(DISABLE); //�ⲿ�ۼ�ģʽ�жϽ�ֹ
- ADC_CR_EN_Setable(DISABLE); //ADC�ر�
-}
+ CDIF_CR_INTF_EN_Setable(ENABLE); // ���Դ��ӿ�ʹ��
+ VRTC_Init_RCMF_Trim();
+ VRTC_RCMFCR_EN_Setable(ENABLE);
+ VRTC_ADCCR_CKS_Set(VRTC_ADCCR_CKS_RCMF_2); // ADC����ʱ��ѡ��
+ VRTC_ADCCR_CKE_Setable(ENABLE); // ADC����ʱ��ʹ��
+ ADC_CFGR_BUFSEL_Set(ADC_CFGR_BUFSEL_ADC_IN5); // ADC����ͨ��ѡ��
-void ADC_IN4_Init(void)
-{
-
- CDIF_CR_INTF_EN_Setable(ENABLE); //���Դ��ӿ�ʹ��
- VRTC_Init_RCMF_Trim();
- VRTC_RCMFCR_EN_Setable(ENABLE);
- VRTC_ADCCR_CKS_Set(VRTC_ADCCR_CKS_RCMF_2); //ADC����ʱ��ѡ��
- VRTC_ADCCR_CKE_Setable(ENABLE); //ADC����ʱ��ʹ��
- ADC_CFGR_BUFSEL_Set(ADC_CFGR_BUFSEL_ADC_IN4); //ADC����ͨ��ѡ��
-
- ADC_CFGR_BUFEN_Setable(ENABLE); //ADC����ͨ��bufferʹ��/��ֹ
- ADC_CR_MODE_Set(ADC_CR_MODE_EXTERNAL); //ADC����ģʽѡ���ⲿ�ۼ���
- ADC_CR_RSTCTRL_EN_Setable(ENABLE); //����������ⲿ��λ
- ADC_CFGR_ACC_PERIOD_Set(ADC_CFGR_ACC_PERIOD_14BITS); //�ⲿ�ۼ����ۼ���������
- ADC_CR_HPEN_Set(ADC_CR_HPEN_1MHZ);
-
- ADC_TRIM_Write(0X7FF); //adcƵ��1M ʱ ����ʱ��4ms
-// ADC_TRIM_Write(0X3FF); //adcƵ��1M ʱ ����ʱ��2ms
-// ADC_TRIM_Write(0X1FF); //adcƵ��1M ʱ ����ʱ��1ms
-
- ADC_CR_ACC_IE_Setable(DISABLE); //�ⲿ�ۼ�ģʽ�жϽ�ֹ
- ADC_CR_EN_Setable(DISABLE); //ADC�ر�
-}
+ ADC_CFGR_BUFEN_Setable(ENABLE); // ADC����ͨ��bufferʹ��/��ֹ
+ ADC_CR_MODE_Set(ADC_CR_MODE_EXTERNAL); // ADC����ģʽѡ���ⲿ�ۼ���
+ ADC_CR_RSTCTRL_EN_Setable(ENABLE); // ����������ⲿ��λ
+ ADC_CFGR_ACC_PERIOD_Set(ADC_CFGR_ACC_PERIOD_14BITS); // �ⲿ�ۼ����ۼ���������
+ ADC_CR_HPEN_Set(ADC_CR_HPEN_1MHZ);
-void ADC_IN8_Init(void)
-{
-
- CDIF_CR_INTF_EN_Setable(ENABLE); //���Դ��ӿ�ʹ��
- VRTC_Init_RCMF_Trim();
- VRTC_RCMFCR_EN_Setable(ENABLE);
- VRTC_ADCCR_CKS_Set(VRTC_ADCCR_CKS_RCMF_2); //ADC����ʱ��ѡ��
- VRTC_ADCCR_CKE_Setable(ENABLE); //ADC����ʱ��ʹ��
- ADC_CFGR_BUFSEL_Set(ADC_CFGR_BUFSEL_ADC_IN8); //ADC����ͨ��ѡ��
-
- ADC_CFGR_BUFEN_Setable(ENABLE); //ADC����ͨ��bufferʹ��/��ֹ
- ADC_CR_MODE_Set(ADC_CR_MODE_EXTERNAL); //ADC����ģʽѡ���ⲿ�ۼ���
- ADC_CR_RSTCTRL_EN_Setable(ENABLE); //����������ⲿ��λ
- ADC_CFGR_ACC_PERIOD_Set(ADC_CFGR_ACC_PERIOD_14BITS); //�ⲿ�ۼ����ۼ���������
- ADC_CR_HPEN_Set(ADC_CR_HPEN_1MHZ);
-
- ADC_TRIM_Write(0X7FF); //adcƵ��1M ʱ ����ʱ��4ms
-// ADC_TRIM_Write(0X3FF); //adcƵ��1M ʱ ����ʱ��2ms
-// ADC_TRIM_Write(0X1FF); //adcƵ��1M ʱ ����ʱ��1ms
-
- ADC_CR_ACC_IE_Setable(DISABLE); //�ⲿ�ۼ�ģʽ�жϽ�ֹ
- ADC_CR_EN_Setable(DISABLE); //ADC�ر�
+ ADC_TRIM_Write(0X7FF); // adcƵ��1M ʱ ����ʱ��4ms
+ // ADC_TRIM_Write(0X3FF); //adcƵ��1M ʱ ����ʱ��2ms
+ // ADC_TRIM_Write(0X1FF); //adcƵ��1M ʱ ����ʱ��1ms
+
+ ADC_CR_ACC_IE_Setable(DISABLE); // �ⲿ�ۼ�ģʽ�жϽ�ֹ
+ ADC_CR_EN_Setable(DISABLE); // ADC�ر�
}
void ADC_IN10_Init(void)
{
-
- CDIF_CR_INTF_EN_Setable(ENABLE); //���Դ��ӿ�ʹ��
- VRTC_Init_RCMF_Trim();
- VRTC_RCMFCR_EN_Setable(ENABLE);
- VRTC_ADCCR_CKS_Set(VRTC_ADCCR_CKS_RCMF_2); //ADC����ʱ��ѡ��
- VRTC_ADCCR_CKE_Setable(ENABLE); //ADC����ʱ��ʹ��
- ADC_CFGR_BUFSEL_Set(ADC_CFGR_BUFSEL_ADC_IN10); //ADC����ͨ��ѡ��
-
- ADC_CFGR_BUFEN_Setable(ENABLE); //ADC����ͨ��bufferʹ��/��ֹ
- ADC_CR_MODE_Set(ADC_CR_MODE_EXTERNAL); //ADC����ģʽѡ���ⲿ�ۼ���
- ADC_CR_RSTCTRL_EN_Setable(ENABLE); //����������ⲿ��λ
- ADC_CFGR_ACC_PERIOD_Set(ADC_CFGR_ACC_PERIOD_14BITS); //�ⲿ�ۼ����ۼ���������
- ADC_CR_HPEN_Set(ADC_CR_HPEN_1MHZ);
-
- ADC_TRIM_Write(0X7FF); //adcƵ��1M ʱ ����ʱ��4ms
-// ADC_TRIM_Write(0X3FF); //adcƵ��1M ʱ ����ʱ��2ms
-// ADC_TRIM_Write(0X1FF); //adcƵ��1M ʱ ����ʱ��1ms
-
- ADC_CR_ACC_IE_Setable(DISABLE); //�ⲿ�ۼ�ģʽ�жϽ�ֹ
- ADC_CR_EN_Setable(DISABLE); //ADC�ر�
+
+ CDIF_CR_INTF_EN_Setable(ENABLE); // ���Դ��ӿ�ʹ��
+ VRTC_Init_RCMF_Trim();
+ VRTC_RCMFCR_EN_Setable(ENABLE);
+ VRTC_ADCCR_CKS_Set(VRTC_ADCCR_CKS_RCMF_2); // ADC����ʱ��ѡ��
+ VRTC_ADCCR_CKE_Setable(ENABLE); // ADC����ʱ��ʹ��
+ ADC_CFGR_BUFSEL_Set(ADC_CFGR_BUFSEL_ADC_IN10); // ADC����ͨ��ѡ��
+
+ ADC_CFGR_BUFEN_Setable(ENABLE); // ADC����ͨ��bufferʹ��/��ֹ
+ ADC_CR_MODE_Set(ADC_CR_MODE_EXTERNAL); // ADC����ģʽѡ���ⲿ�ۼ���
+ ADC_CR_RSTCTRL_EN_Setable(ENABLE); // ����������ⲿ��λ
+ ADC_CFGR_ACC_PERIOD_Set(ADC_CFGR_ACC_PERIOD_14BITS); // �ⲿ�ۼ����ۼ���������
+ ADC_CR_HPEN_Set(ADC_CR_HPEN_1MHZ);
+
+ ADC_TRIM_Write(0X7FF); // adcƵ��1M ʱ ����ʱ��4ms
+ // ADC_TRIM_Write(0X3FF); //adcƵ��1M ʱ ����ʱ��2ms
+ // ADC_TRIM_Write(0X1FF); //adcƵ��1M ʱ ����ʱ��1ms
+
+ ADC_CR_ACC_IE_Setable(DISABLE); // �ⲿ�ۼ�ģʽ�жϽ�ֹ
+ ADC_CR_EN_Setable(DISABLE); // ADC�ر�
+}
+
+void ADC_IN8_Init(void)
+{
+
+ CDIF_CR_INTF_EN_Setable(ENABLE); // ���Դ��ӿ�ʹ��
+ VRTC_Init_RCMF_Trim();
+ VRTC_RCMFCR_EN_Setable(ENABLE);
+ VRTC_ADCCR_CKS_Set(VRTC_ADCCR_CKS_RCMF_2); // ADC����ʱ��ѡ��
+ VRTC_ADCCR_CKE_Setable(ENABLE); // ADC����ʱ��ʹ��
+ ADC_CFGR_BUFSEL_Set(ADC_CFGR_BUFSEL_ADC_IN8); // ADC����ͨ��ѡ��
+
+ ADC_CFGR_BUFEN_Setable(ENABLE); // ADC����ͨ��bufferʹ��/��ֹ
+ ADC_CR_MODE_Set(ADC_CR_MODE_EXTERNAL); // ADC����ģʽѡ���ⲿ�ۼ���
+ ADC_CR_RSTCTRL_EN_Setable(ENABLE); // ����������ⲿ��λ
+ ADC_CFGR_ACC_PERIOD_Set(ADC_CFGR_ACC_PERIOD_14BITS); // �ⲿ�ۼ����ۼ���������
+ ADC_CR_HPEN_Set(ADC_CR_HPEN_1MHZ);
+
+ ADC_TRIM_Write(0X7FF); // adcƵ��1M ʱ ����ʱ��4ms
+ // ADC_TRIM_Write(0X3FF); //adcƵ��1M ʱ ����ʱ��2ms
+ // ADC_TRIM_Write(0X1FF); //adcƵ��1M ʱ ����ʱ��1ms
+
+ ADC_CR_ACC_IE_Setable(DISABLE); // �ⲿ�ۼ�ģʽ�жϽ�ֹ
+ ADC_CR_EN_Setable(DISABLE); // ADC�ر�
}
void ADC_Temp_Init(void)
{
- CDIF_CR_INTF_EN_Setable(ENABLE); //���Դ��ӿ�ʹ��
- VRTC_Init_RCMF_Trim();
- VRTC_RCMFCR_EN_Setable(ENABLE);
- VRTC_ADCCR_CKS_Set(VRTC_ADCCR_CKS_RCMF_2); //ADC����ʱ��ѡ��
- VRTC_ADCCR_CKE_Setable(ENABLE); //ADC����ʱ��ʹ��
- ADC_CFGR_BUFSEL_Set(ADC_CFGR_BUFSEL_TS); //ADC����ͨ��ѡ��
-
- ADC_CFGR_BUFEN_Setable(ENABLE); //ADC����ͨ��bufferʹ��/��ֹ
-
- ADC_CR_MODE_Set(ADC_CR_MODE_EXTERNAL); //ADC����ģʽѡ���ⲿ�ۼ���
-
- ADC_CR_RSTCTRL_EN_Setable(ENABLE); //����������ⲿ��λ �ڲ�ģʽdisable �ⲿģʽenable
-
- ADC_TRIM_Write(0x7FF); //�ⲿ�ۼ� ����д0x7FF
+ CDIF_CR_INTF_EN_Setable(ENABLE); // ���Դ��ӿ�ʹ��
+ VRTC_Init_RCMF_Trim();
+ VRTC_RCMFCR_EN_Setable(ENABLE);
+ VRTC_ADCCR_CKS_Set(VRTC_ADCCR_CKS_RCMF_2); // ADC����ʱ��ѡ��
+ VRTC_ADCCR_CKE_Setable(ENABLE); // ADC����ʱ��ʹ��
+ ADC_CFGR_BUFSEL_Set(ADC_CFGR_BUFSEL_TS); // ADC����ͨ��ѡ��
- ADC_CFGR_ACC_PERIOD_Set(ADC_CFGR_ACC_PERIOD_14BITS); //�ⲿ�ۼ����ۼ��������� �ڲ��ۼӿ�ע��
-
- ADC_CR_ACC_IE_Setable(DISABLE); //�ⲿ�ۼ�ģʽ�жϽ�ֹ
+ ADC_CFGR_BUFEN_Setable(ENABLE); // ADC����ͨ��bufferʹ��/��ֹ
- ADC_CR_EN_Setable(DISABLE); //ADC�ر�
+ ADC_CR_MODE_Set(ADC_CR_MODE_EXTERNAL); // ADC����ģʽѡ���ⲿ�ۼ���
+
+ ADC_CR_RSTCTRL_EN_Setable(ENABLE); // ����������ⲿ��λ �ڲ�ģʽdisable �ⲿģʽenable
+
+ ADC_TRIM_Write(0x7FF); // �ⲿ�ۼ� ����д0x7FF
+
+ ADC_CFGR_ACC_PERIOD_Set(ADC_CFGR_ACC_PERIOD_14BITS); // �ⲿ�ۼ����ۼ��������� �ڲ��ۼӿ�ע��
+
+ ADC_CR_ACC_IE_Setable(DISABLE); // �ⲿ�ۼ�ģʽ�жϽ�ֹ
+
+ ADC_CR_EN_Setable(DISABLE); // ADC�ر�
}
-
uint32_t adc_vol_cal(uint32_t adc_data)
{
- int32_t Volt = 0;
- Volt = (adc_data*const_adc_Slope/1000.0)+const_adc_Offset/100.0;
+ int32_t Volt = 0;
+ Volt = (adc_data * const_adc_Slope / 1000.0) + const_adc_Offset / 100.0;
- if(Volt<0) //VoltΪ��ֵ
- {
- Volt=0;
- }
- return Volt;
+ if (Volt < 0) // VoltΪ��ֵ
+ {
+ Volt = 0;
+ }
+ return Volt;
}
float adc_tem_cal(uint32_t adc_data)
{
- float T = 0;
-//�ڲ��ۼӼ���
-// if(adc_data >const_T_30 )
-// {
-// T=(adc_data-const_T_30)/const_TmpeK+const_30_top;
-// }
-// else
-// {
-// T=const_30_top-(const_T_30-adc_data)/const_TmpeK;
-// }
-
-//�ⲿ�ۼƼ���
- if(adc_data >const_T_30_14BIT )
- {
- T=(adc_data-const_T_30_14BIT)/const_TmpeK_14BIT+const_30_top-0.5;
- }
- else
- {
- T=const_30_top-(const_T_30_14BIT-adc_data)/const_TmpeK_14BIT-0.5;
- }
- return T;
+ float T = 0;
+ // �ڲ��ۼӼ���
+ // if(adc_data >const_T_30 )
+ // {
+ // T=(adc_data-const_T_30)/const_TmpeK+const_30_top;
+ // }
+ // else
+ // {
+ // T=const_30_top-(const_T_30-adc_data)/const_TmpeK;
+ // }
+
+ // �ⲿ�ۼƼ���
+ if (adc_data > const_T_30_14BIT)
+ {
+ T = (adc_data - const_T_30_14BIT) / const_TmpeK_14BIT + const_30_top - 0.5;
+ }
+ else
+ {
+ T = const_30_top - (const_T_30_14BIT - adc_data) / const_TmpeK_14BIT - 0.5;
+ }
+ return T;
}
uint08 adc_wait_finish(void)
{
- uint32 timeout=0;
- do
- {
- if(SET == ADC_ISR_ACC_IF_Chk()) return 0;//�ⲿ�ۼ�
- }while(timeout++ < 0xFFFFFFFFU);
- return 1;//��ʱ
+ uint32 timeout = 0;
+ do
+ {
+ if (SET == ADC_ISR_ACC_IF_Chk())
+ return 0; // �ⲿ�ۼ�
+ } while (timeout++ < 0xFFFFFFFFU);
+ return 1; // ��ʱ
}
uint32_t Get_AdcValue(void)
{
- volatile int32_t fVlotage = 0;
- uint32 fTempADC = 0;
- ADC_CR_EN_Setable(ENABLE); //ADC����
+ volatile int32_t fVlotage = 0;
+ uint32 fTempADC = 0;
+ ADC_CR_EN_Setable(ENABLE); // ADC����
- ADC_ISR_ACC_IF_Clr(); //�ⲿ�ۼ�����жϱ�־
- if(0 == adc_wait_finish()) //�ȴ�ת�����
- fTempADC = ADC_DR_Read(); //��ȡADֵ
- else
- return 0;
- fVlotage = adc_vol_cal(fTempADC);//ADֵת��Ϊ��ѹ,��Դ��ѹΪ5V
+ ADC_ISR_ACC_IF_Clr(); // �ⲿ�ۼ�����жϱ�־
+ if (0 == adc_wait_finish()) // �ȴ�ת�����
+ fTempADC = ADC_DR_Read(); // ��ȡADֵ
+ else
+ return 0;
+ fVlotage = adc_vol_cal(fTempADC); // ADֵת��Ϊ��ѹ,��Դ��ѹΪ5V
- return fVlotage;
+ return fVlotage;
}
float Get_AdcTempValue(void)
{
- float Temperature = 0;
- uint32 fTempADC = 0;
- ADC_CR_EN_Setable(ENABLE); //ADC����
+ float Temperature = 0;
+ uint32 fTempADC = 0;
+ ADC_CR_EN_Setable(ENABLE); // ADC����
- ADC_ISR_ACC_IF_Clr(); //�ⲿ�ۼ�����жϱ�־
- if(0 == adc_wait_finish()) //�ȴ�ת�����
- fTempADC = ADC_DR_Read(); //��ȡADֵ
- else
- return 0;
- Temperature = adc_tem_cal(fTempADC);
-
- return Temperature;
+ ADC_ISR_ACC_IF_Clr(); // �ⲿ�ۼ�����жϱ�־
+ if (0 == adc_wait_finish()) // �ȴ�ת�����
+ fTempADC = ADC_DR_Read(); // ��ȡADֵ
+ else
+ return 0;
+ Temperature = adc_tem_cal(fTempADC);
+ return Temperature;
}
--
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