From 72def895431ad7a08e635b11f3da738e2b2c4618 Mon Sep 17 00:00:00 2001
From: wujiazhi <1147861305@qq.com>
Date: Thu, 13 Jun 2024 11:31:04 +0800
Subject: [PATCH] add lower model test
---
Function/IR_NEC/ir_nec.c | 42 ++++++++++++++++++++++++++++++++++++++++++
1 files changed, 42 insertions(+), 0 deletions(-)
diff --git a/Function/IR_NEC/ir_nec.c b/Function/IR_NEC/ir_nec.c
new file mode 100644
index 0000000..c452135
--- /dev/null
+++ b/Function/IR_NEC/ir_nec.c
@@ -0,0 +1,42 @@
+#include "ir_nec.h"
+#include "gpio.h"
+#include "uart.h"
+#include "upper_computer.h"
+
+/*����FM33A0û�д��ڿ����жϣ���������DMA�Ĵ���ָ�벻�ƶ����ж��Ƿ�������*/
+ErrorStatus_STM32 IR_Uart5_Rx_DMA_CH5_Check(void)
+{
+ uint16_t timeout_cnt = 0, dma_recv_cnt;
+ uint32_t dma_mar_reg_read = DMA_CHxMAR_Read(DMA_CH5);
+
+ if (dma_mar_reg_read != (uint32)uc_recv_para_g.uc_recv_buf_union.uc_recv_buf)
+ {
+ delay_ms(2);
+ while (dma_mar_reg_read != DMA_CHxMAR_Read(DMA_CH5))
+ {
+ dma_mar_reg_read = DMA_CHxMAR_Read(DMA_CH5);
+ delay_ms(2);
+ if (timeout_cnt++ > 100)
+ break;
+ }
+ }
+ else
+ return ERROR_1;
+
+ dma_recv_cnt = dma_mar_reg_read - (uint32)uc_recv_para_g.uc_recv_buf_union.uc_recv_buf;
+ if (dma_recv_cnt)
+ {
+ uc_recv_para_g.uc_recv_length = dma_recv_cnt;
+ // ����RAM��ַ����
+ DMA_ISR_DMACHFT_Clr(DMA_CH5);
+ DMA_CHxCR_ChxEN_Setable(DMA_CH5, DISABLE); // ͨ��ʧ��
+
+ DMA_CHxMAR_Write(DMA_CH5, (uint32)uc_recv_para_g.uc_recv_buf_union.uc_recv_buf);
+
+ DMA_CHxCR_ChxEN_Setable(DMA_CH5, ENABLE); // ͨ��ʹ��
+ uc_recv_para_g.uc_recv_flag = SET; // �������
+ return SUCCESS_0;
+ // DMA_GCR_DMAEN_Setable(DISABLE);//DMA��ʹ��
+ }
+ return ERROR_1;
+}
--
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