From 6c7e61a54ef9b96f79704f0b965664e89f57dd52 Mon Sep 17 00:00:00 2001
From: jinlicong <493886250@qq.com>
Date: Wed, 29 May 2024 17:41:52 +0800
Subject: [PATCH] 增加休眠，开始上板测试
---
HARDWARE/ADC/ADC.c | 28 ++++++++++++++++++++++++++--
1 files changed, 26 insertions(+), 2 deletions(-)
diff --git a/HARDWARE/ADC/ADC.c b/HARDWARE/ADC/ADC.c
index 8f224df..1f82dda 100644
--- a/HARDWARE/ADC/ADC.c
+++ b/HARDWARE/ADC/ADC.c
@@ -25,8 +25,8 @@
void ADC_AlkaIO_Init(void)
{
CMU_PERCLK_SetableEx(PADCLK, ENABLE); //PADʱ�ӣ�GPIO��ʹ�ܺ���
- AnalogIO(ALK_ADC_PORT,ALK_ADC_PIN);//ADC_IN8
- GPIOx_ANEN_Setable(ALK_ADC_PORT,ALK_ADC_PIN,ENABLE);
+ AnalogIO_H(ALK_ADC_PIN);//ADC_IN8
+// GPIOx_ANEN_Setable(ALK_ADC_PORT,ALK_ADC_PIN,ENABLE); //?û��H�ڣ���ʱ��֪����ô����
}
void ADC_IN5_Init(void)
@@ -100,6 +100,30 @@
ADC_CR_EN_Setable(DISABLE); //ADC�ر�
}
+void ADC_IN10_Init(void)
+{
+
+ CDIF_CR_INTF_EN_Setable(ENABLE); //���Դ��ӿ�ʹ��
+ VRTC_Init_RCMF_Trim();
+ VRTC_RCMFCR_EN_Setable(ENABLE);
+ VRTC_ADCCR_CKS_Set(VRTC_ADCCR_CKS_RCMF_2); //ADC����ʱ��ѡ��
+ VRTC_ADCCR_CKE_Setable(ENABLE); //ADC����ʱ��ʹ��
+ ADC_CFGR_BUFSEL_Set(ADC_CFGR_BUFSEL_ADC_IN10); //ADC����ͨ��ѡ��
+
+ ADC_CFGR_BUFEN_Setable(ENABLE); //ADC����ͨ��bufferʹ��/��ֹ
+ ADC_CR_MODE_Set(ADC_CR_MODE_EXTERNAL); //ADC����ģʽѡ���ⲿ�ۼ���
+ ADC_CR_RSTCTRL_EN_Setable(ENABLE); //����������ⲿ��λ
+ ADC_CFGR_ACC_PERIOD_Set(ADC_CFGR_ACC_PERIOD_14BITS); //�ⲿ�ۼ����ۼ���������
+ ADC_CR_HPEN_Set(ADC_CR_HPEN_1MHZ);
+
+ ADC_TRIM_Write(0X7FF); //adcƵ��1M ʱ ����ʱ��4ms
+// ADC_TRIM_Write(0X3FF); //adcƵ��1M ʱ ����ʱ��2ms
+// ADC_TRIM_Write(0X1FF); //adcƵ��1M ʱ ����ʱ��1ms
+
+ ADC_CR_ACC_IE_Setable(DISABLE); //�ⲿ�ۼ�ģʽ�жϽ�ֹ
+ ADC_CR_EN_Setable(DISABLE); //ADC�ر�
+}
+
void ADC_Temp_Init(void)
{
CDIF_CR_INTF_EN_Setable(ENABLE); //���Դ��ӿ�ʹ��
--
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