From 6b0d1f644233b2984d2a87553de598879cf05caf Mon Sep 17 00:00:00 2001
From: jinlicong <493886250@qq.com>
Date: Tue, 28 May 2024 17:24:59 +0800
Subject: [PATCH] 继续完善
---
HARDWARE/TIM/tim.c | 36 +++++++++++++++++-------------------
1 files changed, 17 insertions(+), 19 deletions(-)
diff --git a/HARDWARE/TIM/tim.c b/HARDWARE/TIM/tim.c
index 881d3a0..05fe5c3 100644
--- a/HARDWARE/TIM/tim.c
+++ b/HARDWARE/TIM/tim.c
@@ -1,31 +1,29 @@
#include "tim.h"
#include "rs485_read_data.h"
-
#include "gpio.h"
+#include "pulse_and_alarm_line.h"
uint8_t first_power_tim_cnt_g = 5;
void BTx_IRQHandler(void)
{
-// if( BTx_ISR_CMPHIF_Chk(BT1)==SET) //�춨����
-// {
-// BTx_ISR_CMPLIF_Clr(BT1);
-// BTx_ISR_CMPHIF_Clr(BT1);
-// sys_time_g.sys_cal_run_period = SET;//����ʱ��
-// }else if(BTx_ISR_CMPHIF_Chk(BT2)==SET)
-// {
-// BTx_ISR_CMPLIF_Clr(BT2);
-// BTx_ISR_CMPHIF_Clr(BT2);
-// ++first_power_tim_cnt_g;
-// if(first_power_tim_cnt_g % 5 == 0)
-// {
-// pwr_vol_g.lith_flag = LMS_PERIOD;//�״��ϵ磬��ѹ��μ���
-// if(++first_power_get_cnt_g >= FIRST_POWER_TIM_MAX)
-// BTx_CR1_CHEN_Setable(BT2,DISABLE);
-// }
-//
-// }
+ if( BTx_ISR_CMPHIF_Chk(BT1)==SET) //�춨����
+ {
+ BTx_ISR_CMPLIF_Clr(BT1);
+ BTx_ISR_CMPHIF_Clr(BT1);
+
+ BTx_CR1_CHEN_Setable(BT1,DISABLE);
+ pulse_exti_flag = RESET;
+
+ pulse_count +=1;
+
+ }else if(BTx_ISR_CMPHIF_Chk(BT2)==SET)
+ {
+ BTx_ISR_CMPLIF_Clr(BT2);
+ BTx_ISR_CMPHIF_Clr(BT2);
+
+ }
}
void BSTIM_IRQHandler(void)
--
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