From 65062d0d5b21f838aa0043a15ce54cfab8d72c43 Mon Sep 17 00:00:00 2001
From: wujiazhi <1147861305@qq.com>
Date: Tue, 11 Jun 2024 14:23:53 +0800
Subject: [PATCH] 1.Fixed communication failure between MCU and wireless module 2.Fix the wrong judgment of alkaline lithium power
---
HARDWARE/CLOCK/user_init.c | 235 ++++++++++++++++++++++++++++------------------------------
1 files changed, 115 insertions(+), 120 deletions(-)
diff --git a/HARDWARE/CLOCK/user_init.c b/HARDWARE/CLOCK/user_init.c
index 1bd3118..6472fcf 100644
--- a/HARDWARE/CLOCK/user_init.c
+++ b/HARDWARE/CLOCK/user_init.c
@@ -1,161 +1,156 @@
-#include "define_all.h"
+#include "define_all.h"
#include "gpio.h"
#define RCLP_TRIM (uint8_t)(*(uint32_t *)0X1FFFFB20UL)
-//У��Ĵ���
-unsigned char CheckSysReg( __IO uint32_t *RegAddr, uint32_t Value )
+// У��Ĵ���
+unsigned char CheckSysReg(__IO uint32_t *RegAddr, uint32_t Value)
{
- if( *RegAddr != Value )
- {
- *RegAddr = Value;
- return 1;
- }
- else
- {
- return 0;
- }
+ if (*RegAddr != Value)
+ {
+ *RegAddr = Value;
+ return 1;
+ }
+ else
+ {
+ return 0;
+ }
}
-//��ѯNVIC�Ĵ�����Ӧ�������ж��Ƿ��
-//1 ��
-//0 �ر�
-unsigned char CheckNvicIrqEn( IRQn_Type IRQn )
+// ��ѯNVIC�Ĵ�����Ӧ�������ж��Ƿ��
+// 1 ��
+// 0 �ر�
+unsigned char CheckNvicIrqEn(IRQn_Type IRQn)
{
- if( 0 == ( NVIC->ISER[0U] & ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)))) )
- return 0;
- else
- return 1;
+ if (0 == (NVIC->ISER[0U] & ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)))))
+ return 0;
+ else
+ return 1;
}
-
-
void IWDT_Clr(void)
{
- IWDT ->SERV =0x12345A5A;
+ IWDT->SERV = 0x12345A5A;
}
void IWDT_Init(void)
{
- CMU_PERCLK_SetableEx(IWDTCLK, ENABLE);
- IWDT->CFGR = 0x06; //����2S������2S
- IWDT_Clr(); //��ϵͳ���Ź�
+ CMU_PERCLK_SetableEx(IWDTCLK, ENABLE);
+ IWDT->CFGR = 0x06; // ����2S������2S
+ IWDT_Clr(); // ��ϵͳ���Ź�
}
-
-//ϵͳʱ������
-//ʹ��XTHF����ʱ��,define_all.h ��SYSCLKdef�����ϵͳʱ��Ƶ��
+// ϵͳʱ������
+// ʹ��XTHF����ʱ��,define_all.h ��SYSCLKdef�����ϵͳʱ��Ƶ��
void Init_SysClk(void)
{
- uint32_t i=0;
- CMU_SYSCLK_InitTypeDef SYSCLK_InitStruct;
-
- CMU_PERCLK_SetableEx(PADCLK, ENABLE); //PADʱ�ӣ�GPIO��ʹ�ܺ���
- AnalogIO(GPIOF,GPIO_Pin_1); //�����ֲ�9.4��֪ʹ��XTHF֮ǰ�轫PF1��PF2����Ϊģ���
- AnalogIO(GPIOF,GPIO_Pin_2);
-
- //ʹ��XTHF
- CMU_XTHFCR_XTHFEN_Setable(ENABLE); //ʹ��XTHF
- CMU_XTHFCR_XTHF_CFG_Set(CMU_XTHFCR_XTHF_CFG_MAX); //��ǿ��ѡ����ǿ
- delay_ms(5);//������Ҫʱ��
-
-// /*ϵͳʱ�ӳ���24M����Ҫ��wait*/
-// FLS_RDCR_WAIT_Set(FLS_RDCR_WAIT_2CYCLE);
-// IWDT_Clr();
- CMU_IER_HFDET_IE_Setable(ENABLE); //����XTHFͣ�𱨾��ж�
- //ϵͳʱ��ֱ��ʹ��XTHF
- while(!CMU_ISR_HFDETO_Chk())
- {
- if(i>=6400) //��ʱ��ƣ�������ʱ��ѡ��ֵͬ��������8M
- {
- break;
- }
- i++;
- }
-
-
- SYSCLK_InitStruct.SYSCLKSEL = CMU_SYSCLKCR_SYSCLKSEL_XTHF; //ѡ��XTHF����ʱ�ӣ��ⲿ����12Mhz��
- SYSCLK_InitStruct.AHBPRES = CMU_SYSCLKCR_AHBPRES_DIV1; //AHB����Ƶ
- SYSCLK_InitStruct.APBPRES = CMU_SYSCLKCR_APBPRES_DIV1; //APB1����Ƶ
- SYSCLK_InitStruct.SLP_ENEXTI = ENABLE;//����ģʽʹ���ⲿ�жϲ���
- CMU_SysClk_Init(&SYSCLK_InitStruct);
- delay_init(SYSCLOCK_U);
+ uint32_t i = 0;
+ CMU_SYSCLK_InitTypeDef SYSCLK_InitStruct;
+
+ CMU_PERCLK_SetableEx(PADCLK, ENABLE); // PADʱ�ӣ�GPIO��ʹ�ܺ���
+ AnalogIO(GPIOF, GPIO_Pin_1); // �����ֲ�9.4��֪ʹ��XTHF֮ǰ�轫PF1��PF2����Ϊģ���
+ AnalogIO(GPIOF, GPIO_Pin_2);
+
+ // ʹ��XTHF
+ CMU_XTHFCR_XTHFEN_Setable(ENABLE); // ʹ��XTHF
+ CMU_XTHFCR_XTHF_CFG_Set(CMU_XTHFCR_XTHF_CFG_MAX); // ��ǿ��ѡ����ǿ
+ delay_ms(5); // ������Ҫʱ��
+
+ // /*ϵͳʱ�ӳ���24M����Ҫ��wait*/
+ // FLS_RDCR_WAIT_Set(FLS_RDCR_WAIT_2CYCLE);
+ // IWDT_Clr();
+ CMU_IER_HFDET_IE_Setable(ENABLE); // ����XTHFͣ�𱨾��ж�
+ // ϵͳʱ��ֱ��ʹ��XTHF
+ while (!CMU_ISR_HFDETO_Chk())
+ {
+ if (i >= 6400) // ��ʱ��ƣ�������ʱ��ѡ��ֵͬ��������8M
+ {
+ break;
+ }
+ i++;
+ }
+
+ SYSCLK_InitStruct.SYSCLKSEL = CMU_SYSCLKCR_SYSCLKSEL_XTHF; // ѡ��XTHF����ʱ�ӣ��ⲿ����12Mhz��
+ SYSCLK_InitStruct.AHBPRES = CMU_SYSCLKCR_AHBPRES_DIV1; // AHB����Ƶ
+ SYSCLK_InitStruct.APBPRES = CMU_SYSCLKCR_APBPRES_DIV1; // APB1����Ƶ
+ SYSCLK_InitStruct.SLP_ENEXTI = ENABLE; // ����ģʽʹ���ⲿ�жϲ���
+ CMU_SysClk_Init(&SYSCLK_InitStruct);
+ delay_init(SYSCLOCK_U);
}
void Init_RCHF(void)
{
- CMU_RCHF_InitTypeDef RCHF_InitStruct;
+ CMU_RCHF_InitTypeDef RCHF_InitStruct;
- RCHF_InitStruct.FSEL = SYSCLKdef;//define_all.h ��SYSCLKdef�����ϵͳʱ��Ƶ��
- RCHF_InitStruct.RCHFEN = ENABLE;//��RCHF
+ RCHF_InitStruct.FSEL = SYSCLKdef; // define_all.h ��SYSCLKdef�����ϵͳʱ��Ƶ��
+ RCHF_InitStruct.RCHFEN = ENABLE; // ��RCHF
- CMU_RCHF_Init(&RCHF_InitStruct);
+ CMU_RCHF_Init(&RCHF_InitStruct);
- CMU_Init_RCHF_Trim(clkmode);//RCHF����Уֵ����(оƬ��λ���Զ�����8M��Уֵ)��ֻ�ǵ�УRCHF���¾���
+ CMU_Init_RCHF_Trim(clkmode); // RCHF����Уֵ����(оƬ��λ���Զ�����8M��Уֵ)��ֻ�ǵ�УRCHF���¾���
}
void Init_RCLP(void)
{
- CDIF->CR = 0X0A;
- VRTC->RCLPTR = RCLP_TRIM;
- CDIF->CR = 0X05;
-}
-
-void Init_SysClk_Gen( void ) //ʱ��ѡ�����
-{
- /*ϵͳʱ�ӳ���24M����Ҫ��wait*/
- if( RCHFCLKCFG > 24 )
- {
- FLS_RDCR_WAIT_Set(FLS_RDCR_WAIT_1CYCLE);
- if( RCHFCLKCFG > 48)
- {
- FLS_RDCR_WAIT_Set(FLS_RDCR_WAIT_2CYCLE);
- }
- }
- else
- {
- FLS_RDCR_WAIT_Set(FLS_RDCR_WAIT_0CYCLE);
- }
-
- Init_RCHF();
- Init_RCLP();
- /*ϵͳʱ������*/
- Init_SysClk();
+ CDIF->CR = 0X0A;
+ VRTC->RCLPTR = RCLP_TRIM;
+ CDIF->CR = 0X05;
}
+void Init_SysClk_Gen(void) // ʱ��ѡ�����
+{
+ /*ϵͳʱ�ӳ���24M����Ҫ��wait*/
+ if (RCHFCLKCFG > 24)
+ {
+ FLS_RDCR_WAIT_Set(FLS_RDCR_WAIT_1CYCLE);
+ if (RCHFCLKCFG > 48)
+ {
+ FLS_RDCR_WAIT_Set(FLS_RDCR_WAIT_2CYCLE);
+ }
+ }
+ else
+ {
+ FLS_RDCR_WAIT_Set(FLS_RDCR_WAIT_0CYCLE);
+ }
+
+ Init_RCHF();
+ Init_RCLP();
+ /*ϵͳʱ������*/
+ Init_SysClk();
+}
void CMU_IRQHandler(void)
{
- uint8_t i = 0;
+ // uint8_t i = 0;
}
void SysWakeUp_ClockCfg(void)
{
- uint32_t i=0;
- CMU_SYSCLK_InitTypeDef SYSCLK_InitStruct;
- //ʹ��XTHF
- CMU_XTHFCR_XTHFEN_Setable(ENABLE); //ʹ��XTHF
- CMU_XTHFCR_XTHF_CFG_Set(CMU_XTHFCR_XTHF_CFG_MAX); //��ǿ��ѡ����ǿ
- delay_ms(3);//������Ҫʱ��
-
-// /*ϵͳʱ�ӳ���24M����Ҫ��wait*/
-// FLS_RDCR_WAIT_Set(FLS_RDCR_WAIT_2CYCLE);
-// IWDT_Clr();
- CMU_IER_HFDET_IE_Setable(ENABLE); //����XTHFͣ�𱨾��ж�
- //ϵͳʱ��ֱ��ʹ��XTHF
- while(!CMU_ISR_HFDETO_Chk())
- {
- if(i>=6400) //��ʱ��ƣ�������ʱ��ѡ��ֵͬ��������8M
- {
- break;
- }
- i++;
- }
-
- SYSCLK_InitStruct.SYSCLKSEL = CMU_SYSCLKCR_SYSCLKSEL_XTHF; //ѡ��XTHF����ʱ�ӣ��ⲿ����12Mhz��
- SYSCLK_InitStruct.AHBPRES = CMU_SYSCLKCR_AHBPRES_DIV1; //AHB����Ƶ
- SYSCLK_InitStruct.APBPRES = CMU_SYSCLKCR_APBPRES_DIV1; //APB1����Ƶ
- SYSCLK_InitStruct.SLP_ENEXTI = ENABLE;//����ģʽʹ���ⲿ�жϲ���
- CMU_SysClk_Init(&SYSCLK_InitStruct);
- delay_init(SYSCLOCK_U);
+ uint32_t i = 0;
+ CMU_SYSCLK_InitTypeDef SYSCLK_InitStruct;
+ // ʹ��XTHF
+ CMU_XTHFCR_XTHFEN_Setable(ENABLE); // ʹ��XTHF
+ CMU_XTHFCR_XTHF_CFG_Set(CMU_XTHFCR_XTHF_CFG_MAX); // ��ǿ��ѡ����ǿ
+ delay_ms(3); // ������Ҫʱ��
+
+ // /*ϵͳʱ�ӳ���24M����Ҫ��wait*/
+ // FLS_RDCR_WAIT_Set(FLS_RDCR_WAIT_2CYCLE);
+ // IWDT_Clr();
+ CMU_IER_HFDET_IE_Setable(ENABLE); // ����XTHFͣ�𱨾��ж�
+ // ϵͳʱ��ֱ��ʹ��XTHF
+ while (!CMU_ISR_HFDETO_Chk())
+ {
+ if (i >= 6400) // ��ʱ��ƣ�������ʱ��ѡ��ֵͬ��������8M
+ {
+ break;
+ }
+ i++;
+ }
+
+ SYSCLK_InitStruct.SYSCLKSEL = CMU_SYSCLKCR_SYSCLKSEL_XTHF; // ѡ��XTHF����ʱ�ӣ��ⲿ����12Mhz��
+ SYSCLK_InitStruct.AHBPRES = CMU_SYSCLKCR_AHBPRES_DIV1; // AHB����Ƶ
+ SYSCLK_InitStruct.APBPRES = CMU_SYSCLKCR_APBPRES_DIV1; // APB1����Ƶ
+ SYSCLK_InitStruct.SLP_ENEXTI = ENABLE; // ����ģʽʹ���ⲿ�жϲ���
+ CMU_SysClk_Init(&SYSCLK_InitStruct);
+ delay_init(SYSCLOCK_U);
}
--
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