继续完善

jinlicong

2024-05-20 e61d1595ebb1fa76b499cddec2df4bd66ec92b97

 HARDWARE/UART/uart.c

@@ -5,6 +5,8 @@


uint8_t RS485_read_data_recv_buff[RS485_READ_DATA_RECV_BUFF_LEN_MAX] = {0};
uint8_t up_comm_recv_buff[UP_COMM_RECV_BUFF_LEN_MAX] = {0};
uint8_t WRC_recv_buff[WRC_RECV_BUFF_LEN_MAX] = {0};

u16 USART_RX_STA = 0; //½ÓÊÕ״̬±ê¼Ç
//void Usmart_RecvDataProcess(UC_RECV_PARA_T *usmart_recv_para_p)
@@ -88,13 +90,13 @@
   CMU_GetClocksFreq(&CMU_Clocks);  //»ñȡϵͳ¸÷ʱÖÓƵÂÊ  
   UART_SInit(RS485_READ_DATA_UARTX, &UART_para,&CMU_Clocks);   //³õʼ»¯uart   
   
//   UARTx_IER_RXBF_IE_Setable(MODBUS_UART, ENABLE);//½ÓÊÕ»º´æÂúÖжÏʹÄÜ ÐèҪʹÓýÓÊÕÖжϴò¿ª´Ë´¦ÉèÖÃ
//   UARTx_IER_TXSE_IE_Setable(MODBUS_UART, ENABLE)£»//·¢ËÍ»º´æ¿ÕÇÒ·¢ËÍÒÆλ¼Ä´æÆ÷¿ÕÖжÏʹÄÜ ÐèҪʹÓ÷¢ËÍÖжϴò¿ª´Ë´¦ÉèÖÃ
//   UARTx_IER_RXBF_IE_Setable(RS485_READ_DATA_UARTX, ENABLE);//½ÓÊÕ»º´æÂúÖжÏʹÄÜ ÐèҪʹÓýÓÊÕÖжϴò¿ª´Ë´¦ÉèÖÃ
//   UARTx_IER_TXSE_IE_Setable(RS485_READ_DATA_UARTX, ENABLE)£»//·¢ËÍ»º´æ¿ÕÇÒ·¢ËÍÒÆλ¼Ä´æÆ÷¿ÕÖжÏʹÄÜ ÐèҪʹÓ÷¢ËÍÖжϴò¿ª´Ë´¦ÉèÖÃ
   
   /*NVICÖжÏÓÅÏȼ¶ÒÔ¼°ÊÇ·ñ´ò¿ªÖжÏÅäÖÃ*/
   NVIC_DisableIRQ(RS485_READ_DATA_UARTX_IRQn);
//   NVIC_SetPriority(UART0_IRQn,2);//ÖжÏÓÅÏȼ¶ÅäÖÃ
//   NVIC_EnableIRQ(UART0_IRQn);      //ÖжϷþÎñº¯Êý¿ª
//   NVIC_SetPriority(RS485_READ_DATA_UARTX_IRQn,2);//ÖжÏÓÅÏȼ¶ÅäÖÃ
//   NVIC_EnableIRQ(RS485_READ_DATA_UARTX_IRQn);      //ÖжϷþÎñº¯Êý¿ª
   
   UARTx_CSR_RXEN_Setable(RS485_READ_DATA_UARTX, ENABLE);  //´ò¿ª½ÓÊÕʹÄÜ
   UARTx_CSR_TXEN_Setable(RS485_READ_DATA_UARTX, ENABLE);  //´ò¿ª·¢ËÍʹÄÜ
@@ -110,7 +112,7 @@
   CMU_PERCLK_SetableEx(DMACLK, ENABLE);//DMAʱÖÓʹÄÜ
   DMA_GCR_DMAEN_Setable(ENABLE);//DMA×ÜʹÄÜ
   
   DMA_InitStructure.CHx = DMA_CH3;//DMAͨµÀºÅÉèÖÃ
   DMA_InitStructure.CHx = RS485_READ_DATA_DMA_CHX;//DMAͨµÀºÅÉèÖÃ
   DMA_InitStructure.CHxPRI = DMA_CHxCR_CHxPRI_HIGH;//ͨµÀÓÅÏȼ¶ÉèÖÃ
   DMA_InitStructure.CHxINC = DMA_CHxCR_CHxINC_INCREASE;//ͨµÀµØÖ·Ôö³¤·½Ïò
   DMA_InitStructure.CHxSSEL = DMA_CHxCR_CH3SSEL_UART1_RX;//ÍâÉèͨµÀÑ¡Ôñ
@@ -130,57 +132,197 @@
   
//   DMA_CHxCR_CHxFTIE_Setable(MODBUS_DMA_RX_CHANNEL,ENABLE);//ͨµÀ´«ÊäÍê³ÉÖжÏʹÄÜ

   DMA_ISR_DMACHFT_Clr(DMA_CH3);
   DMA_ISR_DMACHFT_Clr(RS485_READ_DATA_DMA_CHX);

   DMA_Init(&DMA_InitStructure);//DMAÅäÖòÎÊýдÈë
}

void RS485_read_data_RX_DMA_CH3_reload(void)
{
   DMA_ISR_DMACHFT_Clr(DMA_CH3);
   DMA_CHxCR_ChxEN_Setable(DMA_CH3, DISABLE);    //ͨµÀʧÄÜ
   DMA_ISR_DMACHFT_Clr(RS485_READ_DATA_DMA_CHX);
   DMA_CHxCR_ChxEN_Setable(RS485_READ_DATA_DMA_CHX, DISABLE);    //ͨµÀʧÄÜ
   
   memset(RS485_read_data_recv_buff,0,sizeof(RS485_read_data_recv_buff));
   
   DMA_CHxMAR_Write(DMA_CH3, (uint32)RS485_read_data_recv_buff);
   DMA_CHxMAR_Write(RS485_READ_DATA_DMA_CHX, (uint32)RS485_read_data_recv_buff);
   
   DMA_CHxCR_ChxEN_Setable(DMA_CH3, ENABLE);    //ͨµÀʹÄÜ
   DMA_CHxCR_ChxEN_Setable(RS485_READ_DATA_DMA_CHX, ENABLE);    //ͨµÀʹÄÜ
}


void Uart5_RX_DMA_CH5_Init(void)
//ÉÏλ»ú½Ó¿Ú
void up_comm_uart_Init(uint32_t   BaudRate,UART_ParityBitTypeDef   ParityBit,UART_StopBitTypeDef      StopBit)
{
//   DMA_InitTypeDef DMA_InitStructure;//DMA³õʼ»¯²ÎÊý½á¹¹Ìå
//	
//   CMU_PERCLK_SetableEx(DMACLK, ENABLE);//DMAʱÖÓʹÄÜ
//   DMA_GCR_DMAEN_Setable(ENABLE);//DMA×ÜʹÄÜ
//	
//   DMA_InitStructure.CHx = DMA_CH5;//DMAͨµÀºÅÉèÖÃ
//   DMA_InitStructure.CHxPRI = DMA_CHxCR_CHxPRI_HIGH;//ͨµÀÓÅÏȼ¶ÉèÖÃ
//   DMA_InitStructure.CHxINC = DMA_CHxCR_CHxINC_INCREASE;//ͨµÀµØÖ·Ôö³¤·½Ïò
//   DMA_InitStructure.CHxSSEL = DMA_CHxCR_CH5SSEL_UART5_RX;//ÍâÉèͨµÀÑ¡Ôñ
//   DMA_InitStructure.CHxDIR = DMA_CHxCR_DIR_TO_RAM;//Êý¾Ý´«Êä·½ÏòÉèÖÃ
//   DMA_InitStructure.CHxTSIZE = GPRS_RECV_LEN_MAX - 1;//ͨµÀ´«Ê䳤¶È
//   DMA_InitStructure.CHxRAMAD = (uint32)gprs_module_para_g.gprs_recv_buf;//Ä¿±êµØÖ·
//   DMA_InitStructure.CHxBDW = DMA_CHxCR_BDW_8BITS;//ͨµÀ´«Êä´ø¿í
//	
//   DMA_InitStructure.CHxFTIE = DISABLE;   //ͨµÀ´«ÊäÍê³ÉÖжÏʹÄÜ
//   DMA_InitStructure.CHxHTIE = DISABLE;   //ͨµÀ´«Êä°ë³ÌÖÕ¶ËʹÄÜ
   UART_SInitTypeDef UART_para;//UART³õʼ»¯½á¹¹Ìå
  CMU_ClocksType CMU_Clocks;//ϵͳ¸÷ʱÖÓƵÂʽṹÌå  ÔÚ´ËÓë¼ÆË㲨ÌØÂÊÓйØ

//   DMA_InitStructure.CHxEN   = ENABLE;    //ͨµÀʹÄÜ
//	
//   NVIC_DisableIRQ(DMA_IRQn);
////   NVIC_SetPriority(DMA_IRQn,3);//ÖжÏÓÅÏȼ¶ÅäÖÃ
////   NVIC_EnableIRQ(DMA_IRQn);
//	
////   DMA_CHxCR_CHxFTIE_Setable(MODBUS_DMA_RX_CHANNEL,ENABLE);//ͨµÀ´«ÊäÍê³ÉÖжÏʹÄÜ
   /*UART0 IO ÅäÖÃ*/
   CMU_PERCLK_SetableEx(PADCLK, ENABLE);  //PADʱÖÓ£¨GPIO£©Ê¹Äܺ¯Êý
   AltFunIO(UP_COMM_TX_PORT, UP_COMM_TX_PIN, ALTFUN_NORMAL);		
   AltFunIO(UP_COMM_RX_PORT, UP_COMM_RX_PIN, ALTFUN_NORMAL);	

//   DMA_ISR_DMACHFT_Clr(DMA_CH5);
   OutputIO(UP_COMM_RE_PORT,UP_COMM_RE_PIN,OUT_PUSHPULL);
   UP_COMM_RE_RECV_EN;

//   DMA_Init(&DMA_InitStructure);//DMAÅäÖòÎÊýдÈë
   //UART¹¤×÷ʱÖÓÔ´Ñ¡Ôñ   Ö»ÓÐUART0¡¢1ÐèҪѡÔñ  ÆäËûUART¶Ë¿ÚÔݲ»ÐèÒª  Ö±½Ó×¢Êͼ´¿É
   if((UP_COMM_UARTX==UART0)||(UP_COMM_UARTX==UART1))
      UART_para.ClockSrc = CMU_OPCCR1_UART0CKS_APBCLK;      //UART0¹¤×÷ʱÖÓÑ¡Ôñ	
	
   UART_para.BaudRate = BaudRate;
   UART_para.ParityBit = ParityBit;         //ÆæżУÑé
   if(ParityBit==NONE)
      UART_para.DataBit = Eight8Bit;   //Êý¾ÝλÊý
   else
      UART_para.DataBit = Nine9Bit;   //Êý¾ÝλÊý
   UART_para.StopBit = StopBit;         //ֹͣλ
	
   CMU_GetClocksFreq(&CMU_Clocks);  //»ñȡϵͳ¸÷ʱÖÓƵÂÊ  
   UART_SInit(UP_COMM_UARTX, &UART_para,&CMU_Clocks);   //³õʼ»¯uart	
	
//   UARTx_IER_RXBF_IE_Setable(UP_COMM_UARTX, ENABLE);//½ÓÊÕ»º´æÂúÖжÏʹÄÜ ÐèҪʹÓýÓÊÕÖжϴò¿ª´Ë´¦ÉèÖÃ
//   UARTx_IER_TXSE_IE_Setable(UP_COMM_UARTX, ENABLE)£»//·¢ËÍ»º´æ¿ÕÇÒ·¢ËÍÒÆλ¼Ä´æÆ÷¿ÕÖжÏʹÄÜ ÐèҪʹÓ÷¢ËÍÖжϴò¿ª´Ë´¦ÉèÖÃ
	
   /*NVICÖжÏÓÅÏȼ¶ÒÔ¼°ÊÇ·ñ´ò¿ªÖжÏÅäÖÃ*/
   NVIC_DisableIRQ(UP_COMM_UARTX_IRQn);
//   NVIC_SetPriority(UP_COMM_UARTX_IRQn,2);//ÖжÏÓÅÏȼ¶ÅäÖÃ
//   NVIC_EnableIRQ(UP_COMM_UARTX_IRQn);      //ÖжϷþÎñº¯Êý¿ª
	
   UARTx_CSR_RXEN_Setable(UP_COMM_UARTX, ENABLE);  //´ò¿ª½ÓÊÕʹÄÜ
   UARTx_CSR_TXEN_Setable(UP_COMM_UARTX, ENABLE);  //´ò¿ª·¢ËÍʹÄÜ
	
   UARTx_ISR_RXBF_Clr(UP_COMM_UARTX);
}


void up_comm_RX_DMA_CH2_Init(void)
{
   DMA_InitTypeDef DMA_InitStructure;//DMA³õʼ»¯²ÎÊý½á¹¹Ìå
	
   CMU_PERCLK_SetableEx(DMACLK, ENABLE);//DMAʱÖÓʹÄÜ
   DMA_GCR_DMAEN_Setable(ENABLE);//DMA×ÜʹÄÜ
	
   DMA_InitStructure.CHx = UP_COMM_DMA_CHX;//DMAͨµÀºÅÉèÖÃ
   DMA_InitStructure.CHxPRI = DMA_CHxCR_CHxPRI_HIGH;//ͨµÀÓÅÏȼ¶ÉèÖÃ
   DMA_InitStructure.CHxINC = DMA_CHxCR_CHxINC_INCREASE;//ͨµÀµØÖ·Ôö³¤·½Ïò
   DMA_InitStructure.CHxSSEL = DMA_CHxCR_CH2SSEL_UART5_RX;//ÍâÉèͨµÀÑ¡Ôñ
   DMA_InitStructure.CHxDIR = DMA_CHxCR_DIR_TO_RAM;//Êý¾Ý´«Êä·½ÏòÉèÖÃ
   DMA_InitStructure.CHxTSIZE = UP_COMM_RECV_BUFF_LEN_MAX - 1;//ͨµÀ´«Ê䳤¶È
   DMA_InitStructure.CHxRAMAD = (uint32)up_comm_recv_buff;//Ä¿±êµØÖ·
   DMA_InitStructure.CHxBDW = DMA_CHxCR_BDW_8BITS;//ͨµÀ´«Êä´ø¿í
	
   DMA_InitStructure.CHxFTIE = DISABLE;   //ͨµÀ´«ÊäÍê³ÉÖжÏʹÄÜ
   DMA_InitStructure.CHxHTIE = DISABLE;   //ͨµÀ´«Êä°ë³ÌÖÕ¶ËʹÄÜ

   DMA_InitStructure.CHxEN   = ENABLE;    //ͨµÀʹÄÜ
	
   NVIC_DisableIRQ(DMA_IRQn);
//   NVIC_SetPriority(DMA_IRQn,3);//ÖжÏÓÅÏȼ¶ÅäÖÃ
//   NVIC_EnableIRQ(DMA_IRQn);
	
//   DMA_CHxCR_CHxFTIE_Setable(MODBUS_DMA_RX_CHANNEL,ENABLE);//ͨµÀ´«ÊäÍê³ÉÖжÏʹÄÜ

   DMA_ISR_DMACHFT_Clr(UP_COMM_DMA_CHX);

   DMA_Init(&DMA_InitStructure);//DMAÅäÖòÎÊýдÈë
}

void up_comm_RX_DMA_CH2_reload(void)
{
   DMA_ISR_DMACHFT_Clr(UP_COMM_DMA_CHX);
   DMA_CHxCR_ChxEN_Setable(UP_COMM_DMA_CHX, DISABLE);    //ͨµÀʧÄÜ
	
   memset(up_comm_recv_buff,0,sizeof(up_comm_recv_buff));
	
   DMA_CHxMAR_Write(UP_COMM_DMA_CHX, (uint32)up_comm_recv_buff);
	
   DMA_CHxCR_ChxEN_Setable(UP_COMM_DMA_CHX, ENABLE);    //ͨµÀʹÄÜ
}


void WRC_uart_Init(uint32_t   BaudRate,UART_ParityBitTypeDef   ParityBit,UART_StopBitTypeDef      StopBit)
{
   UART_SInitTypeDef UART_para;//UART³õʼ»¯½á¹¹Ìå
  CMU_ClocksType CMU_Clocks;//ϵͳ¸÷ʱÖÓƵÂʽṹÌå  ÔÚ´ËÓë¼ÆË㲨ÌØÂÊÓйØ
	
   /*UART0 IO ÅäÖÃ*/
   CMU_PERCLK_SetableEx(PADCLK, ENABLE);  //PADʱÖÓ£¨GPIO£©Ê¹Äܺ¯Êý
   AltFunIO(WRC_TX_PORT, WRC_TX_PIN, ALTFUN_NORMAL);		
   AltFunIO(WRC_RX_PORT, WRC_RX_PIN, ALTFUN_NORMAL);	
	
   //UART¹¤×÷ʱÖÓÔ´Ñ¡Ôñ   Ö»ÓÐUART0¡¢1ÐèҪѡÔñ  ÆäËûUART¶Ë¿ÚÔݲ»ÐèÒª  Ö±½Ó×¢Êͼ´¿É
   if((WRC_UARTX==UART0)||(WRC_UARTX==UART1))
      UART_para.ClockSrc = CMU_OPCCR1_UART0CKS_APBCLK;      //UART0¹¤×÷ʱÖÓÑ¡Ôñ	
	
   UART_para.BaudRate = BaudRate;
   UART_para.ParityBit = ParityBit;         //ÆæżУÑé
   if(ParityBit==NONE)
      UART_para.DataBit = Eight8Bit;   //Êý¾ÝλÊý
   else
      UART_para.DataBit = Nine9Bit;   //Êý¾ÝλÊý
   UART_para.StopBit = StopBit;         //ֹͣλ
	
   CMU_GetClocksFreq(&CMU_Clocks);  //»ñȡϵͳ¸÷ʱÖÓƵÂÊ  
   UART_SInit(WRC_UARTX, &UART_para,&CMU_Clocks);   //³õʼ»¯uart	
	
//   UARTx_IER_RXBF_IE_Setable(WRC_UARTX, ENABLE);//½ÓÊÕ»º´æÂúÖжÏʹÄÜ ÐèҪʹÓýÓÊÕÖжϴò¿ª´Ë´¦ÉèÖÃ
//   UARTx_IER_TXSE_IE_Setable(WRC_UARTX, ENABLE)£»//·¢ËÍ»º´æ¿ÕÇÒ·¢ËÍÒÆλ¼Ä´æÆ÷¿ÕÖжÏʹÄÜ ÐèҪʹÓ÷¢ËÍÖжϴò¿ª´Ë´¦ÉèÖÃ
	
   /*NVICÖжÏÓÅÏȼ¶ÒÔ¼°ÊÇ·ñ´ò¿ªÖжÏÅäÖÃ*/
   NVIC_DisableIRQ(WRC_UARTX_IRQn);
//   NVIC_SetPriority(WRC_UARTX_IRQn,2);//ÖжÏÓÅÏȼ¶ÅäÖÃ
//   NVIC_EnableIRQ(WRC_UARTX_IRQn);      //ÖжϷþÎñº¯Êý¿ª
	
   UARTx_CSR_RXEN_Setable(WRC_UARTX, ENABLE);  //´ò¿ª½ÓÊÕʹÄÜ
   UARTx_CSR_TXEN_Setable(WRC_UARTX, ENABLE);  //´ò¿ª·¢ËÍʹÄÜ
	
   UARTx_ISR_RXBF_Clr(WRC_UARTX);
}


void WRC_RX_DMA_CH0_Init(void)
{
   DMA_InitTypeDef DMA_InitStructure;//DMA³õʼ»¯²ÎÊý½á¹¹Ìå
	
   CMU_PERCLK_SetableEx(DMACLK, ENABLE);//DMAʱÖÓʹÄÜ
   DMA_GCR_DMAEN_Setable(ENABLE);//DMA×ÜʹÄÜ
	
   DMA_InitStructure.CHx = WRC_DMA_CHX;//DMAͨµÀºÅÉèÖÃ
   DMA_InitStructure.CHxPRI = DMA_CHxCR_CHxPRI_HIGH;//ͨµÀÓÅÏȼ¶ÉèÖÃ
   DMA_InitStructure.CHxINC = DMA_CHxCR_CHxINC_INCREASE;//ͨµÀµØÖ·Ôö³¤·½Ïò
   DMA_InitStructure.CHxSSEL = DMA_CHxCR_CH0SSEL_UART2_RX;//ÍâÉèͨµÀÑ¡Ôñ
   DMA_InitStructure.CHxDIR = DMA_CHxCR_DIR_TO_RAM;//Êý¾Ý´«Êä·½ÏòÉèÖÃ
   DMA_InitStructure.CHxTSIZE = WRC_RECV_BUFF_LEN_MAX - 1;//ͨµÀ´«Ê䳤¶È
   DMA_InitStructure.CHxRAMAD = (uint32)WRC_recv_buff;//Ä¿±êµØÖ·
   DMA_InitStructure.CHxBDW = DMA_CHxCR_BDW_8BITS;//ͨµÀ´«Êä´ø¿í
	
   DMA_InitStructure.CHxFTIE = DISABLE;   //ͨµÀ´«ÊäÍê³ÉÖжÏʹÄÜ
   DMA_InitStructure.CHxHTIE = DISABLE;   //ͨµÀ´«Êä°ë³ÌÖÕ¶ËʹÄÜ

   DMA_InitStructure.CHxEN   = ENABLE;    //ͨµÀʹÄÜ
	
   NVIC_DisableIRQ(DMA_IRQn);
//   NVIC_SetPriority(DMA_IRQn,3);//ÖжÏÓÅÏȼ¶ÅäÖÃ
//   NVIC_EnableIRQ(DMA_IRQn);
	
//   DMA_CHxCR_CHxFTIE_Setable(MODBUS_DMA_RX_CHANNEL,ENABLE);//ͨµÀ´«ÊäÍê³ÉÖжÏʹÄÜ

   DMA_ISR_DMACHFT_Clr(WRC_DMA_CHX);

   DMA_Init(&DMA_InitStructure);//DMAÅäÖòÎÊýдÈë
}

void WRC_RX_DMA_CH0_reload(void)
{
   DMA_ISR_DMACHFT_Clr(WRC_DMA_CHX);
   DMA_CHxCR_ChxEN_Setable(WRC_DMA_CHX, DISABLE);    //ͨµÀʧÄÜ
	
   memset(WRC_recv_buff,0,sizeof(WRC_recv_buff));
	
   DMA_CHxMAR_Write(WRC_DMA_CHX, (uint32)WRC_recv_buff);
	
   DMA_CHxCR_ChxEN_Setable(WRC_DMA_CHX, ENABLE);    //ͨµÀʹÄÜ
}



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