| | |
| | | #include "tim.h" |
| | | #include "rs485_read_data.h" |
| | | |
| | | #include "gpio.h" |
| | | #include "pulse_and_alarm_line.h" |
| | | |
| | | uint8_t first_power_tim_cnt_g = 5; |
| | | |
| | | |
| | | void BTx_IRQHandler(void) |
| | | { |
| | | // if( BTx_ISR_CMPHIF_Chk(BT1)==SET) //¼ì¶¨ÖÜÆÚ |
| | | // { |
| | | // BTx_ISR_CMPLIF_Clr(BT1); |
| | | // BTx_ISR_CMPHIF_Clr(BT1); |
| | | // sys_time_g.sys_cal_run_period = SET;//ÐÄÌøÊ±¼ä |
| | | // }else if(BTx_ISR_CMPHIF_Chk(BT2)==SET) |
| | | // { |
| | | // BTx_ISR_CMPLIF_Clr(BT2); |
| | | // BTx_ISR_CMPHIF_Clr(BT2); |
| | | // ++first_power_tim_cnt_g; |
| | | // if(first_power_tim_cnt_g % 5 == 0) |
| | | // { |
| | | // pwr_vol_g.lith_flag = LMS_PERIOD;//Ê×´ÎÉϵ磬µçѹ¶à´Î¼ì²â´¦Àí |
| | | // if(++first_power_get_cnt_g >= FIRST_POWER_TIM_MAX) |
| | | // BTx_CR1_CHEN_Setable(BT2,DISABLE); |
| | | // } |
| | | // |
| | | // } |
| | | if( BTx_ISR_CMPHIF_Chk(BT1)==SET) //¼ì¶¨ÖÜÆÚ |
| | | { |
| | | BTx_ISR_CMPLIF_Clr(BT1); |
| | | BTx_ISR_CMPHIF_Clr(BT1); |
| | | |
| | | BTx_CR1_CHEN_Setable(BT1,DISABLE); |
| | | pulse_exti_flag = RESET; |
| | | |
| | | pulse_count +=1; |
| | | |
| | | }else if(BTx_ISR_CMPHIF_Chk(BT2)==SET) |
| | | { |
| | | BTx_ISR_CMPLIF_Clr(BT2); |
| | | BTx_ISR_CMPHIF_Clr(BT2); |
| | | |
| | | } |
| | | } |
| | | |
| | | void BSTIM_IRQHandler(void) |
| | |
| | | BSTIM_ARR_Write(Arr - 1); |
| | | |
| | | NVIC_DisableIRQ(BSTIM_IRQn ); |
| | | NVIC_SetPriority(BSTIM_IRQn ,2); //ÖжÏÓÅÏȼ¶ÅäÖà |
| | | NVIC_SetPriority(BSTIM_IRQn ,5); //ÖжÏÓÅÏȼ¶ÅäÖà |
| | | NVIC_EnableIRQ(BSTIM_IRQn ); |
| | | |
| | | /*½â¾ö¿ªÆô¶¨Ê±Æ÷»áÖ±½Ó½øÈëÒ»´ÎÖжϵÄÎÊÌâ*/ |
| | |
| | | LPTIM_IER_OVIE_Setable(ENABLE); /* ¿ªÆô¼ÆÊýÆ÷ÖÐ¶Ï */ |
| | | |
| | | NVIC_DisableIRQ(LPTIM_IRQn); |
| | | NVIC_SetPriority(LPTIM_IRQn,2);//ÖжÏÓÅÏȼ¶ÅäÖà |
| | | NVIC_SetPriority(LPTIM_IRQn,6);//ÖжÏÓÅÏȼ¶ÅäÖà |
| | | NVIC_EnableIRQ(LPTIM_IRQn); |
| | | |
| | | LPTIM_CR_EN_Setable(ENABLE); /* ʹÄܼÆÊýÆ÷: */ |