forked from SZV10X_Software/SZV103_FM33A0xxEV_SiZhu
HARDWARE/SPI/SPI.c
@@ -1,56 +1,46 @@ #include "spi.h" #include "gpio.h" void SPI3_Init(void) void SPI0_Init(void) { CMU_PERCLK_SetableEx(PADCLK, ENABLE); //PADʱÖÓ£¨GPIO£©Ê¹Äܺ¯Êý // AltFunIO(GPIOF, GPIO_Pin_15, ALTFUN_NORMAL); // SSN AltFunIO(SPI3_PORT, SPI3_SCK_PIN, ALTFUN_NORMAL); // SCK AltFunIO(SPI3_PORT, SPI3_MISO_PIN, ALTFUN_NORMAL); // MISO AltFunIO(SPI3_PORT, SPI3_MOSI_PIN, ALTFUN_NORMAL); // MOSI AltFunIO(SPI0_PORT, SPI0_SCK_PIN, ALTFUN_NORMAL); // SCK AltFunIO(SPI0_PORT, SPI0_MISO_PIN, ALTFUN_NORMAL); // MISO AltFunIO(SPI0_PORT, SPI0_MOSI_PIN, ALTFUN_NORMAL); // MOSI CMU_PERCLK_SetableEx(SPI3CLK, ENABLE); //¿ªÆôSPI3×ÜÏßʱÖÓ CMU_PERCLK_SetableEx(SPI0CLK, ENABLE); //¿ªÆôSPI0×ÜÏßʱÖÓ SPIx_CR1_IOSWAP_Set(SPI3, SPIx_CR1_IOSWAP_DEFAULT); // MISO¡¢MOSIĬÈÏÒý½Å ²»½»»» SPIx_CR1_MM_Set(SPI3, SPIx_CR1_MM_MASTER); //masterģʽ SPIx_CR1_WAIT_Set(SPI3, SPIx_CR1_WAIT_1WAIT); // ÿ·¢ËÍÍêÒ»Ö¡ºó²åÈëÒ»¸öCLK SPIx_CR1_BAUD_Set(SPI3, SPIx_CR1_BAUD_DIV4); //²¨ÌØÂÊÉèÖÃΪÍâÉèʱÖÓ2·ÖƵ SPIx_CR1_LSBF_Set(SPI3, SPIx_CR1_LSBF_MSB); //Ö¡¸ñʽÏÈ·¢ËÍMSB SPIx_CR1_CPHOL_Set(SPI3, SPIx_CR1_CPHOL_LOW); //CLKÍ£Ö¹Ôڵ͵çƽ SPIx_CR1_CPHA_Set(SPI3, SPIx_CR1_CPHA_1CLOCK); //µÚÒ»¸öʱÖÓ±ßÑز¶×½ SPIx_CR2_SSNSEN_Setable(SPI3, DISABLE); //SSNÓÉÓ²¼þ¿ØÖÆ SPIx_CR1_IOSWAP_Set(SPI0, SPIx_CR1_IOSWAP_DEFAULT); // MISO¡¢MOSIĬÈÏÒý½Å ²»½»»» SPIx_CR1_MM_Set(SPI0, SPIx_CR1_MM_MASTER); //masterģʽ SPIx_CR1_WAIT_Set(SPI0, SPIx_CR1_WAIT_1WAIT); // ÿ·¢ËÍÍêÒ»Ö¡ºó²åÈëÒ»¸öCLK SPIx_CR1_BAUD_Set(SPI0, SPIx_CR1_BAUD_DIV4); //²¨ÌØÂÊÉèÖÃΪÍâÉèʱÖÓ2·ÖƵ SPIx_CR1_LSBF_Set(SPI0, SPIx_CR1_LSBF_MSB); //Ö¡¸ñʽÏÈ·¢ËÍMSB SPIx_CR1_CPHOL_Set(SPI0, SPIx_CR1_CPHOL_LOW); //CLKÍ£Ö¹Ôڵ͵çƽ SPIx_CR1_CPHA_Set(SPI0, SPIx_CR1_CPHA_1CLOCK); //µÚÒ»¸öʱÖÓ±ßÑز¶×½ SPIx_CR2_SSNSEN_Setable(SPI0, DISABLE); //SSNÓÉÓ²¼þ¿ØÖÆ SPIx_CR2_RXO_Setable(SPI3, DISABLE); //SPIÉèÖÃΪȫ˫¹¤ SPIx_CR2_DLEN_Set(SPI3, SPIx_CR2_DLEN_8BIT); //ͨÐÅÊý¾Ý×Ö³¤8bit SPIx_CR2_HALFDUPLEX_Set(SPI3, SPIx_CR2_HALFDUPLEX_SPI); //SPIÉèÖÃΪ±ê×¼SPIģʽ SPIx_CR2_SSNM_Set(SPI3, SPIx_CR2_SSNM_LOW); //ÿ´Î·¢Íêmasterºóssn±£³ÖµÍ SPIx_CR2_TXO_AC_Setable(SPI3, DISABLE); //¹Ø±ÕTXONLY×Ô¶¯Çå0 SPIx_CR2_TXO_Setable(SPI3, DISABLE); //¹Ø±ÕTXONLYģʽ // SPIx_CR2_SSN_Set(SPI3, SPIx_CR2_SSN_HIGH); //SSNSENΪ£±Ê±SNNÊä³ö¸ßµçƽ SPIx_CR2_RXO_Setable(SPI0, DISABLE); //SPIÉèÖÃΪȫ˫¹¤ SPIx_CR2_DLEN_Set(SPI0, SPIx_CR2_DLEN_8BIT); //ͨÐÅÊý¾Ý×Ö³¤8bit SPIx_CR2_HALFDUPLEX_Set(SPI0, SPIx_CR2_HALFDUPLEX_SPI); //SPIÉèÖÃΪ±ê×¼SPIģʽ SPIx_CR2_SSNM_Set(SPI0, SPIx_CR2_SSNM_LOW); //ÿ´Î·¢Íêmasterºóssn±£³ÖµÍ SPIx_CR2_TXO_AC_Setable(SPI0, DISABLE); //¹Ø±ÕTXONLY×Ô¶¯Çå0 SPIx_CR2_TXO_Setable(SPI0, DISABLE); //¹Ø±ÕTXONLYģʽ // SPIx_CR2_SSN_Set(SPI0, SPIx_CR2_SSN_HIGH); //SSNSENΪ£±Ê±SNNÊä³ö¸ßµçƽ SPIx_CR3_SERRC_Clr(SPI3); //Çå³ý´Ó»ú´íÎó±êÖ¾ SPIx_CR3_MERRC_Clr(SPI3); //Çå³ýÖ÷»ú´íÎó±êÖ¾ SPIx_CR3_RXBFC_Clr(SPI3); //Çå³ýRXBUF SPIx_CR3_TXBFC_Clr(SPI3); //Çå³ýTXBUF SPIx_CR3_SERRC_Clr(SPI0); //Çå³ý´Ó»ú´íÎó±êÖ¾ SPIx_CR3_MERRC_Clr(SPI0); //Çå³ýÖ÷»ú´íÎó±êÖ¾ SPIx_CR3_RXBFC_Clr(SPI0); //Çå³ýRXBUF SPIx_CR3_TXBFC_Clr(SPI0); //Çå³ýTXBUF SPIx_CR2_SPIEN_Setable(SPI3, ENABLE); //ʹÄÜSPI3 SPIx_CR2_SPIEN_Setable(SPI0, ENABLE); //ʹÄÜSPI0 } void SPI3_sleep(void) { CMU_PERCLK_SetableEx(SPI3CLK, DISABLE); //¿ªÆôSPI3×ÜÏßʱÖÓ SPIx_CR2_SPIEN_Setable(SPI3, DISABLE); //ʧÄÜSPI3 CloseIO(SPI3_PORT, SPI3_SCK_PIN); // SCK CloseIO(SPI3_PORT, SPI3_MISO_PIN); // MISO CloseIO(SPI3_PORT, SPI3_MOSI_PIN); // MOSI } //------------------------------------------------------------------------- uint8_t SpiWriteAndRead(uint32_t data) { SPIx_TXBUF_Write(SPI3, data); @@ -60,6 +50,7 @@ return data; } //---------------------------------------------------------------------- void SpiWrite(uint8_t *data, uint32_t length) {
