| | |
| | | } |
| | | |
| | | ///*--------------------------------ÖжϷþÎñº¯Êý--------------------------------------------------*/ |
| | | uint8_t RX_dat; |
| | | uint8_t RX_flag; |
| | | void UART1_IRQHandler(void) |
| | | { |
| | | |
| | | // ½ÓÊÕÖжϴ¦Àí |
| | | if ((ENABLE == UARTx_IER_RXBF_IE_Getable(UART1)) && (SET == UARTx_ISR_RXBF_Chk(UART1))) |
| | | if (UARTx_ISR_RXTO_Chk(UART1) == SET) |
| | | { |
| | | DMA_ISR_DMACHFT_Clr(DMA_CH3); |
| | | |
| | | DMA_CHxCR_ChxEN_Setable(DMA_CH3, DISABLE); // ͨµÀʧÄÜ |
| | | |
| | | DMA_CHxMAR_Write(DMA_CH3, (uint32)LinkDlg.UartBuff); |
| | | |
| | | DMA_CHxCR_ChxEN_Setable(DMA_CH3, ENABLE); // ͨµÀʹÄÜ |
| | | } |
| | | UARTx_ISR_RXTO_Clr(UART1); |
| | | } |
| | | } |
| | | |
| | | void UART5_IRQHandler(void) |
| | | { |
| | | |
| | | // ½ÓÊÕÖжϴ¦Àí |
| | | if ((ENABLE == UARTx_IER_RXBF_IE_Getable(UART5)) && (SET == UARTx_ISR_RXBF_Chk(UART5))) |
| | | { |
| | | |
| | | DMA_ISR_DMACHFT_Clr(DMA_CH5); |
| | | |
| | | DMA_CHxCR_ChxEN_Setable(DMA_CH5, DISABLE); // ͨµÀʧÄÜ |
| | | |
| | | DMA_CHxMAR_Write(DMA_CH5, (u32)(UTR_rec_buff)); |
| | | |
| | | DMA_CHxCR_ChxEN_Setable(DMA_CH5, ENABLE); // ͨµÀʹÄÜ |
| | | if (UARTx_ISR_RXTO_Chk(UART5) == SET) |
| | | { |
| | | UARTx_ISR_RXTO_Clr(UART5); |
| | | } |
| | | } |
| | | |
| | | void DMA_IRQHandler(void) |
| | | { |
| | | if ((ENABLE == DMA_CHxCR_CHxFTIE_Getable(DMA_CH3)) && (SET == DMA_ISR_DMACHFT_Chk(DMA_CH3))) |
| | | { |
| | | // ÖжÏת·¢½ÓÊÕµ½µÄÊý¾Ý |
| | | DMA_ISR_DMACHFT_Clr(DMA_CH3); |
| | | } |
| | | } |
| | | |
| | | ///*--------------------------------DMA½ÓÊÕÅжϺ¯Êý--------------------------------------------------*/ |
| | | /*Ô¶´«DMA½ÓÊպ˲é*/ |
| | | ErrorStatus_STM32 Gprs_Uart1_Rx_DMA_CH3_Check(void) |
| | | { |
| | | uint16_t timeout_cnt = 0; |
| | | uint16_t dma_recv_cnt; |
| | | uint32_t dma_mar_reg_read; |
| | | |
| | | dma_mar_reg_read = DMA_CHxMAR_Read(DMA_CH3); |
| | | |
| | | if (dma_mar_reg_read != (uint32)LinkDlg.UartBuff) |
| | | { |
| | | delay_ms(2); |
| | | while (dma_mar_reg_read != DMA_CHxMAR_Read(DMA_CH3)) |
| | | { |
| | | dma_mar_reg_read = DMA_CHxMAR_Read(DMA_CH3); |
| | | delay_ms(2); |
| | | if (timeout_cnt++ > 100) |
| | | break; |
| | | } |
| | | } |
| | | else |
| | | return ERROR_1; |
| | | |
| | | dma_recv_cnt = dma_mar_reg_read - (uint32)LinkDlg.UartBuff; |
| | | if (dma_recv_cnt) |
| | | { |
| | | LinkDlg.DataLen = dma_recv_cnt; |
| | | // ½ÓÊÕRAMµØÖ·ÖØÔØ |
| | | DMA_ISR_DMACHFT_Clr(DMA_CH3); |
| | | DMA_CHxCR_ChxEN_Setable(DMA_CH3, DISABLE); // ͨµÀʧÄÜ |
| | | |
| | | DMA_CHxMAR_Write(DMA_CH3, (uint32)LinkDlg.UartBuff); |
| | | |
| | | DMA_CHxCR_ChxEN_Setable(DMA_CH3, ENABLE); // ͨµÀʹÄÜ |
| | | |
| | | LinkDlg.Gprs_Finish_Flag = SET; // ½ÓÊÕÍê³É |
| | | return SUCCESS_0; |
| | | // DMA_GCR_DMAEN_Setable(DISABLE);//DMA×ÜʹÄÜ |
| | | } |
| | | return ERROR_1; |
| | | } |
| | | } |