/**
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******************************************************************************
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* @file fm33a0xxev_qspi.h
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* @author FM33A0XXEV Application Team
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* @version V1.0.0
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* @date 16-April-2020
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* @brief This file contains all the functions prototypes for the QSPI firmware library.
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __FM33A0XXEV_QSPI_H
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#define __FM33A0XXEV_QSPI_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "FM33A0XXEV.h"
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typedef struct
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{
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uint32_t Instruction;
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uint32_t Address;
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uint32_t AlternateByte;
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uint32_t AddressSize;
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uint32_t AlternateByteSize;
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uint32_t DummyCycles;
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uint32_t InstructionMode;
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uint32_t AddressMode;
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uint32_t AlternateByteMode;
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uint32_t DataMode;
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}QSPI_CmdTypeDef;
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#define QSPI_CR_PRESCALER_Pos 24
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#define QSPI_CR_PRESCALER_Msk (0xffU << QSPI_CR_PRESCALER_Pos)
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#define QSPI_CR_PMM_Pos 23 /* ÂÖѯƥÅäģʽ
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0£ºANDģʽ£¬ËùÓÐbit¶¼Æ¥Åä²ÅÖÃλSMF
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1£ºORģʽ£¬ÖÁÉÙ1bitÆ¥Åä¾Í»áÖÃλSMF */
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#define QSPI_CR_PMM_Msk (0x1U << QSPI_CR_PMM_Pos)
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#define QSPI_CR_PMM_AND (0x0U << QSPI_CR_PMM_Pos) /* ANDģʽ£¬ËùÓÐbit¶¼Æ¥Åä²ÅÖÃλSMF */
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#define QSPI_CR_PMM_OR (0x1U << QSPI_CR_PMM_Pos) /* ORģʽ£¬ÖÁÉÙ1bitÆ¥Åä¾Í»áÖÃλSMF */
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#define QSPI_CR_TOIE_Pos 20 /* ³¬Ê±ÖжÏʹÄÜ
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0£º½ûÖ¹³¬Ê±ÖжÏ
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1£ºÔÊÐí³¬Ê±ÖÐ¶Ï */
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#define QSPI_CR_TOIE_Msk (0x1U << QSPI_CR_TOIE_Pos)
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/* ½ûÖ¹³¬Ê±ÖÐ¶Ï */
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/* ÔÊÐí³¬Ê±ÖÐ¶Ï */
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#define QSPI_CR_SMIE_Pos 19 /* ״̬ƥÅäÖжÏʹÄÜ
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0£º½ûֹ״̬ƥÅäÖжÏ
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1£ºÔÊÐí״̬ƥÅäÖÐ¶Ï */
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#define QSPI_CR_SMIE_Msk (0x1U << QSPI_CR_SMIE_Pos)
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/* ½ûֹ״̬ƥÅäÖÐ¶Ï */
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/* ÔÊÐí״̬ƥÅäÖÐ¶Ï */
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#define QSPI_CR_FTIE_Pos 18 /* FIFOˮλÖжÏʹÄÜ
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0£º½ûÖ¹FIFOˮλÖжÏ
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1£ºÔÊÐíFIFOˮλÖÐ¶Ï */
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#define QSPI_CR_FTIE_Msk (0x1U << QSPI_CR_FTIE_Pos)
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/* ½ûÖ¹FIFOˮλÖÐ¶Ï */
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/* ÔÊÐíFIFOˮλÖÐ¶Ï */
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#define QSPI_CR_TCIE_Pos 17 /* ´«ÊäÍê³ÉÖжÏʹÄÜ
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0£º½ûÖ¹´«ÊäÍê³ÉÖжÏ
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1£ºÔÊÐí´«ÊäÍê³ÉÖÐ¶Ï */
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#define QSPI_CR_TCIE_Msk (0x1U << QSPI_CR_TCIE_Pos)
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/* ½ûÖ¹´«ÊäÍê³ÉÖÐ¶Ï */
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/* ÔÊÐí´«ÊäÍê³ÉÖÐ¶Ï */
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#define QSPI_CR_TEIE_Pos 16 /* ´«Êä´íÎóÖжÏʹÄÜ
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0£º½ûÖ¹´«Êä´íÎóÖжÏ
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1£ºÔÊÐí´«Êä´íÎóÖÐ¶Ï */
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#define QSPI_CR_TEIE_Msk (0x1U << QSPI_CR_TEIE_Pos)
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/* ½ûÖ¹´«Êä´íÎóÖÐ¶Ï */
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/* ÔÊÐí´«Êä´íÎóÖÐ¶Ï */
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#define QSPI_CR_FIFOTHR_Pos 8 /* FIFOˮλ¼Ä´æÆ÷£¬½öÍâÉèģʽÏÂÆðЧ
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ÍâÉèдģʽ£º
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0£ºFTFÔÚFIFO¿Õ×Ö½Ú´óÓÚµÈÓÚ1ʱÖÃλ
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1£ºFTFÔÚFIFO¿Õ×Ö½Ú´óÓÚµÈÓÚ2ʱÖÃλ
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¡¡
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15£ºFTFÔÚFIFO¿Õ×Ö½ÚµÈÓÚ16ʱÖÃλ
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ÍâÉè¶Áģʽ£º
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0£ºFTFÔÚFIFOÖÐ×Ö½ÚÊý´óÓÚµÈÓÚ1ʱÖÃλ
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1£ºFTFÔÚFIFOÖÐ×Ö½ÚÊý´óÓÚµÈÓÚ2ʱÖÃλ
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¡¡
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15£ºFTFÔÚFIFOÖÐ×Ö½ÚÊýµÈÓÚ16ʱÖÃλ */
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#define QSPI_CR_FIFOTHR_Msk (0xfU << QSPI_CR_FIFOTHR_Pos)
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#define QSPI_CR_FIFOTHR_1 (0x0U << QSPI_CR_FIFOTHR_Pos) /* FTFÔÚFIFO¿Õ×Ö½Ú´óÓÚµÈÓÚ1ʱÖÃλ */
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#define QSPI_CR_FIFOTHR_2 (0x1U << QSPI_CR_FIFOTHR_Pos) /* FTFÔÚFIFO¿Õ×Ö½Ú´óÓÚµÈÓÚ2ʱÖÃλ */
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#define QSPI_CR_FIFOTHR_3 (0x2U << QSPI_CR_FIFOTHR_Pos) /* FTFÔÚFIFO¿Õ×Ö½Ú´óÓÚµÈÓÚ3ʱÖÃλ */
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#define QSPI_CR_FIFOTHR_4 (0x3U << QSPI_CR_FIFOTHR_Pos) /* FTFÔÚFIFO¿Õ×Ö½Ú´óÓÚµÈÓÚ4ʱÖÃλ */
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#define QSPI_CR_FIFOTHR_5 (0x4U << QSPI_CR_FIFOTHR_Pos) /* FTFÔÚFIFO¿Õ×Ö½Ú´óÓÚµÈÓÚ5ʱÖÃλ */
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#define QSPI_CR_FIFOTHR_6 (0x5U << QSPI_CR_FIFOTHR_Pos) /* FTFÔÚFIFO¿Õ×Ö½Ú´óÓÚµÈÓÚ6ʱÖÃλ */
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#define QSPI_CR_FIFOTHR_7 (0x6U << QSPI_CR_FIFOTHR_Pos) /* FTFÔÚFIFO¿Õ×Ö½Ú´óÓÚµÈÓÚ7ʱÖÃλ */
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#define QSPI_CR_FIFOTHR_8 (0x7U << QSPI_CR_FIFOTHR_Pos) /* FTFÔÚFIFO¿Õ×Ö½Ú´óÓÚµÈÓÚ8ʱÖÃλ */
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#define QSPI_CR_FIFOTHR_9 (0x8U << QSPI_CR_FIFOTHR_Pos) /* FTFÔÚFIFO¿Õ×Ö½Ú´óÓÚµÈÓÚ9ʱÖÃλ */
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#define QSPI_CR_FIFOTHR_10 (0x9U << QSPI_CR_FIFOTHR_Pos) /* FTFÔÚFIFO¿Õ×Ö½Ú´óÓÚµÈÓÚ10ʱÖÃλ */
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#define QSPI_CR_FIFOTHR_11 (0x10U << QSPI_CR_FIFOTHR_Pos) /* FTFÔÚFIFO¿Õ×Ö½Ú´óÓÚµÈÓÚ11ʱÖÃλ */
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#define QSPI_CR_FIFOTHR_12 (0x11U << QSPI_CR_FIFOTHR_Pos) /* FTFÔÚFIFO¿Õ×Ö½Ú´óÓÚµÈÓÚ12ʱÖÃλ */
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#define QSPI_CR_FIFOTHR_13 (0x12U << QSPI_CR_FIFOTHR_Pos) /* FTFÔÚFIFO¿Õ×Ö½Ú´óÓÚµÈÓÚ13ʱÖÃλ */
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#define QSPI_CR_FIFOTHR_14 (0x13U << QSPI_CR_FIFOTHR_Pos) /* FTFÔÚFIFO¿Õ×Ö½Ú´óÓÚµÈÓÚ14ʱÖÃλ */
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#define QSPI_CR_FIFOTHR_15 (0x14U << QSPI_CR_FIFOTHR_Pos) /* FTFÔÚFIFO¿Õ×Ö½Ú´óÓÚµÈÓÚ15ʱÖÃλ */
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#define QSPI_CR_FIFOTHR_16 (0x15U << QSPI_CR_FIFOTHR_Pos) /* FTFÔÚFIFO¿Õ×Ö½ÚµÈÓÚ16ʱÖÃλ */
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#define QSPI_CR_SSHFT_Pos 4 /* ÑÓ³Ù²ÉÑùʹÄÜ
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0£º¹Ø±ÕÑÓ³Ù²ÉÑù¹¦ÄÜ
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1£ºÊ¹ÄÜÑÓ³Ù²ÉÑù¹¦ÄÜ */
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#define QSPI_CR_SSHFT_Msk (0x1U << QSPI_CR_SSHFT_Pos)
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/* ¹Ø±ÕÑÓ³Ù²ÉÑù¹¦ÄÜ */
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/* ʹÄÜÑÓ³Ù²ÉÑù¹¦ÄÜ */
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#define QSPI_CR_TCEN_Pos 3 /* ×ÜÏß³¬Ê±Ê¹ÄÜ£¬´Ë¼Ä´æÆ÷½öÔÚ´æ´¢Æ÷Ó³ÉäģʽÏÂÓÐЧ
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µ±BUSYÖÃλºó£¬Èç¹ûQuadSPI²»·¢Æð¶ÔQSPI´æ´¢Æ÷µÄ·ÃÎÊ£¬³¬Ê±¼Ä´æÆ÷¿ªÊ¼¼ÆÊý£¬¼ÆÊýÒç³ö³¤¶ÈÓÉTIMEOUT¼Ä´æÆ÷¶¨Òå¡£µ±QSPI×ÜÏß³¤Ê±¼äÎÞ¶¯×÷£¬¼ÆÊýÆ÷Òç³ö£¬nCS±»×Ô¶¯À¸ß£¬Ç¿ÖƽáÊøµ±Ç°´«Êä¹ý³Ì¡£
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0£º¹Ø±Õ³¬Ê±¹¦ÄÜ
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1£ºÊ¹Äܳ¬Ê±¹¦ÄÜ */
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#define QSPI_CR_TCEN_Msk (0x1U << QSPI_CR_TCEN_Pos)
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/* ¹Ø±Õ³¬Ê±¹¦ÄÜ */
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/* ʹÄܳ¬Ê±¹¦ÄÜ */
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#define QSPI_CR_DMAEN_Pos 2 /* DMAʹÄÜ
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0£ºDMA¹¦Äܹرգ¬QuadSPI²»»á·¢ËÍDMAÇëÇó
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1£ºDMA¹¦ÄÜ¿ªÆô£¬QuadSPIÔÚÂú×ãÌõ¼þʱ·¢ËÍDMAÇëÇó */
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#define QSPI_CR_DMAEN_Msk (0x1U << QSPI_CR_DMAEN_Pos)
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/* DMA¹¦Äܹرգ¬QuadSPI²»»á·¢ËÍDMAÇëÇó */
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/* DMA¹¦ÄÜ¿ªÆô£¬QuadSPIÔÚÂú×ãÌõ¼þʱ·¢ËÍDMAÇëÇó */
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#define QSPI_CR_ABORT_Pos 1 /* µ±Ç°´«ÊäÖÕÖ¹¼Ä´æÆ÷£¬Èí¼þд1ÖÕÖ¹´«Ê䣬Ӳ¼þÀ¸ßnCSºó×Ô¶¯ÇåÁã */
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#define QSPI_CR_ABORT_Msk (0x1U << QSPI_CR_ABORT_Pos)
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#define QSPI_CR_EN_Pos 0 /* QuadSPIÄ£¿éʹÄÜ
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0£º¹Ø±ÕQuadSPI
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1£ºÊ¹ÄÜQuadSPI */
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#define QSPI_CR_EN_Msk (0x1U << QSPI_CR_EN_Pos)
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/* ¹Ø±ÕQuadSPI */
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/* ʹÄÜQuadSPI */
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#define QSPI_CFG_CSHT_Pos 8 /* nCS×îС¸ßµçƽʱ¼ä£¬¶¨ÒåÁËÁ¬ÐøÁ½¸öÖ¡Ö®¼änCSËùÐè±£³Ö¸ßµçƽµÄ×î¶Ìʱ¼ä£¬ÒÔQSPI_CLKÖÜÆÚ¼ÆÊý
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0£ºÖÁÉÙ1 cycle
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1£ºÖÁÉÙ2 cycles
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¡¡
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7£ºÖÁÉÙ8 cycles */
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#define QSPI_CFG_CSHT_Msk (0x7U << QSPI_CFG_CSHT_Pos)
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#define QSPI_CFG_CSHT_1CYCLE (0x0U << QSPI_CFG_CSHT_Pos) /* ÖÁÉÙ1 cycle */
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#define QSPI_CFG_CSHT_2CYCLES (0x1U << QSPI_CFG_CSHT_Pos) /* ÖÁÉÙ2 cycles */
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#define QSPI_CFG_CSHT_3CYCLES (0x2U << QSPI_CFG_CSHT_Pos) /* ÖÁÉÙ3 cycles */
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#define QSPI_CFG_CSHT_4CYCLES (0x3U << QSPI_CFG_CSHT_Pos) /* ÖÁÉÙ4 cycles */
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#define QSPI_CFG_CSHT_5CYCLES (0x4U << QSPI_CFG_CSHT_Pos) /* ÖÁÉÙ5 cycles */
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#define QSPI_CFG_CSHT_6CYCLES (0x5U << QSPI_CFG_CSHT_Pos) /* ÖÁÉÙ6 cycles */
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#define QSPI_CFG_CSHT_7CYCLES (0x6U << QSPI_CFG_CSHT_Pos) /* ÖÁÉÙ7 cycles */
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#define QSPI_CFG_CSHT_8CYCLES (0x7U << QSPI_CFG_CSHT_Pos) /* ÖÁÉÙ8 cycles */
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#define QSPI_CFG_CKMODE_Pos 0 /* SPI Clock Mode¼Ä´æÆ÷
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0£ºmode 0
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1£ºmode 3 */
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#define QSPI_CFG_CKMODE_Msk (0x1U << QSPI_CFG_CKMODE_Pos)
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#define QSPI_CFG_CKMODE_MODE0 (0x0U << QSPI_CFG_CKMODE_Pos) /* mode 0 */
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#define QSPI_CFG_CKMODE_MODE3 (0x1U << QSPI_CFG_CKMODE_Pos) /* mode 3 */
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#define QSPI_SR_FIFOLVL_Pos 8 /* FIFOˮλ±êÖ¾
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´Ë¼Ä´æÆ÷±íʾµ±Ç°FIFOÖб£´æµÄÊý¾Ý×Ö½ÚÊý£¬0±íʾFIFO¿Õ£¬16±íʾFIFOÂú
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×Ô¶¯²éѯģʽÏ´˼ĴæÆ÷±£³Ö0 */
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#define QSPI_SR_FIFOLVL_Msk (0x1fU << QSPI_SR_FIFOLVL_Pos)
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#define QSPI_SR_BUSY_Pos 5 /* 1±íʾQuadSPI´«Êä½øÐÐÖУ¬Í¨ÐŽáÊøºó×Ô¶¯ÇåÁã */
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#define QSPI_SR_BUSY_Msk (0x1U << QSPI_SR_BUSY_Pos)
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#define QSPI_SR_TOF_Pos 4 /* ³¬Ê±±êÖ¾£¬Ó²¼þÖÃ룬Èí¼þд1ÇåÁã */
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#define QSPI_SR_TOF_Msk (0x1U << QSPI_SR_TOF_Pos)
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#define QSPI_SR_SMF_Pos 3 /* ×Ô¶¯²éѯģʽϱíÕ÷״̬¼Ä´æÆ÷Æ¥Åä³É¹¦£¬Ó²¼þÖÃ룬Èí¼þд1ÇåÁã */
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#define QSPI_SR_SMF_Msk (0x1U << QSPI_SR_SMF_Pos)
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#define QSPI_SR_FTF_Pos 2 /* FIFO threshold±êÖ¾£¬FIFOˮλ¸ßÓÚÉ趨ãÐֵʱ×Ô¶¯ÖÃ룬µÍÓÚãÐֵʱ×Ô¶¯ÇåÁã
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×Ô¶¯²éѯģʽÏ£¬Ã¿´Î¶Á»ØÒ»×é״ֵ̬ºó¶¼»á×Ô¶¯ÖÃλFTF£¬Èç¹ûÈí¼þ¶ÁÈ¡QSPI_DATA¼Ä´æÆ÷ÔòFTFÇåÁã */
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#define QSPI_SR_FTF_Msk (0x1U << QSPI_SR_FTF_Pos)
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#define QSPI_SR_TCF_Pos 1 /* ´«ÊäÍê³É±êÖ¾£¬Ó²¼þÖÃ룬Èí¼þд1ÇåÁã */
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#define QSPI_SR_TCF_Msk (0x1U << QSPI_SR_TCF_Pos)
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#define QSPI_DATALEN_QSPI_DATALEN_Pos 0 /* ´«ÊäÊý¾Ý³¤¶ÈΪDATALEN+1£¨bytes£© */
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#define QSPI_DATALEN_QSPI_DATALEN_Msk (0xffffffffU << QSPI_DATALEN_QSPI_DATALEN_Pos)
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#define QSPI_CCR_CRM_Pos 28 /* Continuous Read Mode
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0£ºÃ¿´ÎͨÐÅ·¢Æðʱ¶¼Òª·¢ËÍÖ¸Áî
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1£ºÖ»ÔÚµÚÒ»´ÎͨÐÅʱ·¢ËÍÖ¸Áî */
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#define QSPI_CCR_CRM_Msk (0x1U << QSPI_CCR_CRM_Pos)
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#define QSPI_CCR_CRM_ALWAYS (0x0U << QSPI_CCR_CRM_Pos) /* ÿ´ÎͨÐÅ·¢Æðʱ¶¼Òª·¢ËÍÖ¸Áî */
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#define QSPI_CCR_CRM_ONLY (0x1U << QSPI_CCR_CRM_Pos) /* Ö»ÔÚµÚÒ»´ÎͨÐÅʱ·¢ËÍÖ¸Áî */
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#define QSPI_CCR_OPMODE_Pos 26 /* ²Ù×÷ģʽ
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00£ºÍâÉèдģʽ
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01£ºÍâÉè¶Áģʽ
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10£º×Ô¶¯²éѯģʽ
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11£º´æ´¢Æ÷Ó³Éäģʽ */
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#define QSPI_CCR_OPMODE_Msk (0x3U << QSPI_CCR_OPMODE_Pos)
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#define QSPI_CCR_OPMODE_WRITE (0x0U << QSPI_CCR_OPMODE_Pos) /* ÍâÉèдģʽ */
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#define QSPI_CCR_OPMODE_READ (0x1U << QSPI_CCR_OPMODE_Pos) /* ÍâÉè¶Áģʽ */
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#define QSPI_CCR_OPMODE_QUERY (0x2U << QSPI_CCR_OPMODE_Pos) /* ×Ô¶¯²éѯģʽ */
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#define QSPI_CCR_OPMODE_MAP (0x3U << QSPI_CCR_OPMODE_Pos) /* ´æ´¢Æ÷Ó³Éäģʽ */
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#define QSPI_CCR_DMODE_Pos 24 /* Êý¾ÝͨÐÅģʽ£¨data phase£©
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00£ºÎÞÊý¾Ý
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01£ºµ¥Ïß
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10£ºË«Ïß
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11£ºËÄÏß */
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#define QSPI_CCR_DMODE_Msk (0x3U << QSPI_CCR_DMODE_Pos)
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#define QSPI_CCR_DMODE_NONE (0x0U << QSPI_CCR_DMODE_Pos) /* ÎÞÊý¾Ý */
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#define QSPI_CCR_DMODE_SINGLE (0x1U << QSPI_CCR_DMODE_Pos) /* µ¥Ïß */
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#define QSPI_CCR_DMODE_DOUBLE (0x2U << QSPI_CCR_DMODE_Pos) /* Ë«Ïß */
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#define QSPI_CCR_DMODE_FOUR (0x3U << QSPI_CCR_DMODE_Pos) /* ËÄÏß */
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#define QSPI_CCR_DUMCYC_Pos 18 /* Dummy cycle¸öÊýÅäÖã¨ÒÔQSPI_CLKÖÜÆÚ¼ÆË㣩£¬0~31 */
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#define QSPI_CCR_DUMCYC_Msk (0x1fU << QSPI_CCR_DUMCYC_Pos)
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#define QSPI_CCR_ABSIZE_Pos 16 /* Alternate bytes¸öÊý
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00£º8bits alternate bytes
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01£º16bits alternate bytes
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10£º24bits alternate bytes
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11£º32bits alternate bytes */
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#define QSPI_CCR_ABSIZE_Msk (0x3U << QSPI_CCR_ABSIZE_Pos)
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#define QSPI_CCR_ABSIZE_8BITS (0x0U << QSPI_CCR_ABSIZE_Pos) /* 8bits alternate bytes */
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#define QSPI_CCR_ABSIZE_16BITS (0x1U << QSPI_CCR_ABSIZE_Pos) /* 16bits alternate bytes */
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#define QSPI_CCR_ABSIZE_24BITS (0x2U << QSPI_CCR_ABSIZE_Pos) /* 24bits alternate bytes */
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#define QSPI_CCR_ABSIZE_32BITS (0x3U << QSPI_CCR_ABSIZE_Pos) /* 32bits alternate bytes */
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#define QSPI_CCR_ABMODE_Pos 14 /* Alternate bytes·¢ËÍģʽ
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00£ºÎÞalternate bytes
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01£ºµ¥Ïß
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10£ºË«Ïß
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11£ºËÄÏß */
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#define QSPI_CCR_ABMODE_Msk (0x3U << QSPI_CCR_ABMODE_Pos)
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#define QSPI_CCR_ABMODE_NONE (0x0U << QSPI_CCR_ABMODE_Pos) /* ÎÞalternate bytes */
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#define QSPI_CCR_ABMODE_SINGLE (0x1U << QSPI_CCR_ABMODE_Pos) /* µ¥Ïß */
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#define QSPI_CCR_ABMODE_DOUBLE (0x2U << QSPI_CCR_ABMODE_Pos) /* Ë«Ïß */
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#define QSPI_CCR_ABMODE_FOUR (0x3U << QSPI_CCR_ABMODE_Pos) /* ËÄÏß */
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#define QSPI_CCR_ADSIZE_Pos 12 /* µØÖ·×Ö½Ú³¤¶È
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00£º8bitsµØÖ·
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01£º16bitsµØÖ·
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10£º24bitsµØÖ·
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11£º32bitsµØÖ· */
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#define QSPI_CCR_ADSIZE_Msk (0x3U << QSPI_CCR_ADSIZE_Pos)
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#define QSPI_CCR_ADSIZE_8BITS (0x0U << QSPI_CCR_ADSIZE_Pos) /* 8bitsµØÖ· */
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#define QSPI_CCR_ADSIZE_16BITS (0x1U << QSPI_CCR_ADSIZE_Pos) /* 16bitsµØÖ· */
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#define QSPI_CCR_ADSIZE_24BITS (0x2U << QSPI_CCR_ADSIZE_Pos) /* 24bitsµØÖ· */
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#define QSPI_CCR_ADSIZE_32BITS (0x3U << QSPI_CCR_ADSIZE_Pos) /* 32bitsµØÖ· */
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#define QSPI_CCR_ADMODE_Pos 10 /* µØÖ·×Ö½Ú·¢ËÍģʽ
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00£ºÎÞµØÖ·×Ö½Ú
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01£ºµ¥Ïß
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10£ºË«Ïß
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11£ºËÄÏß */
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#define QSPI_CCR_ADMODE_Msk (0x3U << QSPI_CCR_ADMODE_Pos)
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#define QSPI_CCR_ADMODE_NONE (0x0U << QSPI_CCR_ADMODE_Pos) /* ÎÞµØÖ·×Ö½Ú */
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#define QSPI_CCR_ADMODE_SINGLE (0x1U << QSPI_CCR_ADMODE_Pos) /* µ¥Ïß */
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#define QSPI_CCR_ADMODE_DOUBLE (0x2U << QSPI_CCR_ADMODE_Pos) /* Ë«Ïß */
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#define QSPI_CCR_ADMODE_FOUR (0x3U << QSPI_CCR_ADMODE_Pos) /* ËÄÏß */
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#define QSPI_CCR_IMODE_Pos 8 /* Ö¸Áî·¢ËÍģʽ
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00£ºÎÞÖ¸Áî×Ö½Ú
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01£ºµ¥Ïß
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10£ºË«Ïß
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11£ºËÄÏß */
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#define QSPI_CCR_IMODE_Msk (0x3U << QSPI_CCR_IMODE_Pos)
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#define QSPI_CCR_IMODE_NONE (0x0U << QSPI_CCR_IMODE_Pos) /* ÎÞÖ¸Áî×Ö½Ú */
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#define QSPI_CCR_IMODE_SINGLE (0x1U << QSPI_CCR_IMODE_Pos) /* µ¥Ïß */
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#define QSPI_CCR_IMODE_DOUBLE (0x2U << QSPI_CCR_IMODE_Pos) /* Ë«Ïß */
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#define QSPI_CCR_IMODE_FOUR (0x3U << QSPI_CCR_IMODE_Pos) /* ËÄÏß */
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#define QSPI_CCR_INSTRUCTION_Pos 0 /* QuadSPI·¢Ë͵ÄÖ¸Áî×Ö½Ú */
|
#define QSPI_CCR_INSTRUCTION_Msk (0xffU << QSPI_CCR_INSTRUCTION_Pos)
|
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#define QSPI_ADDR_QSPI_ADDR_Pos 0 /* ·¢Ë͸øQSPI´æ´¢Æ÷µÄµØÖ·£¬ÔÚ´æ´¢Æ÷Ó³ÉäģʽÏÂÎÞЧ */
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#define QSPI_ADDR_QSPI_ADDR_Msk (0xffffffffU << QSPI_ADDR_QSPI_ADDR_Pos)
|
|
#define QSPI_ABR_QSPI_ABR_Pos 0 /* ·¢Ë͸øQSPI´æ´¢Æ÷µÄalternate bytes */
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#define QSPI_ABR_QSPI_ABR_Msk (0xffffffffU << QSPI_ABR_QSPI_ABR_Pos)
|
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#define QSPI_DR_QSPI_DATA_Pos 0 /* QSPIÊý¾Ý¼Ä´æÆ÷
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ÍâÉèģʽд²Ù×÷ʱ£¬¶ÔQSPI_DR¼Ä´æÆ÷дÈëµÄÊý¾Ý½«±»push FIFO£¬Ö§³Ö×Ö½Ú¡¢°ë×Ö¡¢×ÖдÈ룬·Ö±ð¶ÔFIFOѹÈë1¡¢2¡¢4×Ö½Ú£»Èç¹ûдÈë×Ö½ÚÊý´óÓÚFIFOÖпÕ×Ö½ÚÊý£¬µ±Ç°Ð´²Ù×÷±»¹ÒÆð£¬Ö±µ½FIFOÖÐÓÐ×ã¹»¿Õ¼äÈÝÄɵ±Ç°Ð´ÈëÊý¾Ý¡£
|
ÍâÉèģʽ¶Á²Ù×÷ʱ£¬¶ÁÈ¡QSPI_DR¼Ä´æÆ÷½«pop FIFO£¬Ö§³Ö×Ö½Ú¡¢°ë×Ö¡¢×Ö¶ÁÈ¡£¬·Ö±ð´ÓFIFOµ¯³ö1¡¢2¡¢4×Ö½Ú£»Èç¹û¶ÁÈ¡×Ö½ÚÊý´óÓÚFIFOÖÐÓÐЧ×Ö½ÚÊý£¬µ±Ç°¶Á²Ù×÷±»¹ÒÆð£¬Ö±µ½FIFOÖÐÓÐ×ã¹»×Ö½Ú¿ÉÒÔ±»¶ÁÈ¡£¬»òÕß´«ÊäÍê³É£¬ºóÒ»ÖÖÇé¿öÏÂÖ»µ¯³ö×îºó¼¸¸öʵ¼ÊÓÐЧ×Ö½Ú¡£
|
¶ÔQSPI_DRµÄ·ÃÎʱØÐë¶ÔÆëµÍµØÖ·£¬¼´×Ö½Ú·ÃÎʱØÐë¶ÔÆëQSPI_DR[7:0]£¬°ë×Ö·ÃÎʱØÐë¶ÔÆëQSPI_DR[15:0] */
|
#define QSPI_DR_QSPI_DATA_Msk (0xffffffffU << QSPI_DR_QSPI_DATA_Pos)
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#define QSPI_SMSK_QSPI_SMSK_Pos 0 /* ×Ô¶¯×´Ì¬²éѯģʽϵÄ״̬mask¼Ä´æÆ÷£¬¶ÔÓ¦bitд0ÆÁ±ÎÏàӦ״̬λ */
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#define QSPI_SMSK_QSPI_SMSK_Msk (0xffffffffU << QSPI_SMSK_QSPI_SMSK_Pos)
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#define QSPI_SMAT_QSPI_SMAT_Pos 0 /* ×Ô¶¯×´Ì¬²éѯģʽϵÄ״̬ƥÅä¼Ä´æÆ÷
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±È½Ï¶ÔÏóÊÇQSPI_DATA & QSPI_SMSK */
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#define QSPI_SMAT_QSPI_SMAT_Msk (0xffffffffU << QSPI_SMAT_QSPI_SMAT_Pos)
|
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#define QSPI_PITV_QSPI_PITV_Pos 0 /* ×Ô¶¯×´Ì¬²éѯģʽϵÄÂÖѯ¼ä¸ô£¨polling interval£©£¬¶¨ÒåΪQSPI_CLKÖÜÆÚÊý */
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#define QSPI_PITV_QSPI_PITV_Msk (0xffffU << QSPI_PITV_QSPI_PITV_Pos)
|
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#define QSPI_TO_QSPI_TO_Pos 0 /* ³¬Ê±ÖÜÆÚÉèÖ㬶¨ÒåΪQSPI_CLKÖÜÆÚÊý£¬½öÔÚ´æ´¢Æ÷Ó³ÉäģʽÏÂÓÐЧ
|
µ±FIFOÂúÖ®ºó£¬QSPI×ÜÏßÐÐΪֹͣ£¬³¬Ê±¼ÆÊýÆ÷¿ªÊ¼¼ÆÊý£¬¼ÆÊýÖµµ½´ïQSPI_TOÉ趨ֵ֮ºó£¬À¸ßnCS */
|
#define QSPI_TO_QSPI_TO_Msk (0xffffU << QSPI_TO_QSPI_TO_Pos)
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//Macro_End
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/* Exported functions --------------------------------------------------------*/
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extern void QSPI_Deinit(void);
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extern void QSPI_CR_PRESCALER_Set(uint32_t SetValue);
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extern uint32_t QSPI_CR_PRESCALER_Get(void);
|
|
/* ÂÖѯƥÅäģʽ
|
0£ºANDģʽ£¬ËùÓÐbit¶¼Æ¥Åä²ÅÖÃλSMF
|
1£ºORģʽ£¬ÖÁÉÙ1bitÆ¥Åä¾Í»áÖÃλSMF Ïà¹Øº¯Êý */
|
extern void QSPI_CR_PMM_Set(uint32_t SetValue);
|
extern uint32_t QSPI_CR_PMM_Get(void);
|
|
/* ³¬Ê±ÖжÏʹÄÜ
|
0£º½ûÖ¹³¬Ê±ÖжÏ
|
1£ºÔÊÐí³¬Ê±ÖÐ¶Ï Ïà¹Øº¯Êý */
|
extern void QSPI_CR_TOIE_Setable(FunState NewState);
|
extern FunState QSPI_CR_TOIE_Getable(void);
|
|
/* ״̬ƥÅäÖжÏʹÄÜ
|
0£º½ûֹ״̬ƥÅäÖжÏ
|
1£ºÔÊÐí״̬ƥÅäÖÐ¶Ï Ïà¹Øº¯Êý */
|
extern void QSPI_CR_SMIE_Setable(FunState NewState);
|
extern FunState QSPI_CR_SMIE_Getable(void);
|
|
/* FIFOˮλÖжÏʹÄÜ
|
0£º½ûÖ¹FIFOˮλÖжÏ
|
1£ºÔÊÐíFIFOˮλÖÐ¶Ï Ïà¹Øº¯Êý */
|
extern void QSPI_CR_FTIE_Setable(FunState NewState);
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extern FunState QSPI_CR_FTIE_Getable(void);
|
|
/* ´«ÊäÍê³ÉÖжÏʹÄÜ
|
0£º½ûÖ¹´«ÊäÍê³ÉÖжÏ
|
1£ºÔÊÐí´«ÊäÍê³ÉÖÐ¶Ï Ïà¹Øº¯Êý */
|
extern void QSPI_CR_TCIE_Setable(FunState NewState);
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extern FunState QSPI_CR_TCIE_Getable(void);
|
|
/* ´«Êä´íÎóÖжÏʹÄÜ
|
0£º½ûÖ¹´«Êä´íÎóÖжÏ
|
1£ºÔÊÐí´«Êä´íÎóÖÐ¶Ï Ïà¹Øº¯Êý */
|
extern void QSPI_CR_TEIE_Setable(FunState NewState);
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extern FunState QSPI_CR_TEIE_Getable(void);
|
|
/* FIFOˮλ¼Ä´æÆ÷£¬½öÍâÉèģʽÏÂÆðЧ
|
ÍâÉèдģʽ£º
|
0£ºFTFÔÚFIFO¿Õ×Ö½Ú´óÓÚµÈÓÚ1ʱÖÃλ
|
1£ºFTFÔÚFIFO¿Õ×Ö½Ú´óÓÚµÈÓÚ2ʱÖÃλ
|
¡¡
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15£ºFTFÔÚFIFO¿Õ×Ö½ÚµÈÓÚ16ʱÖÃλ
|
ÍâÉè¶Áģʽ£º
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0£ºFTFÔÚFIFOÖÐ×Ö½ÚÊý´óÓÚµÈÓÚ1ʱÖÃλ
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1£ºFTFÔÚFIFOÖÐ×Ö½ÚÊý´óÓÚµÈÓÚ2ʱÖÃλ
|
¡¡
|
15£ºFTFÔÚFIFOÖÐ×Ö½ÚÊýµÈÓÚ16ʱÖÃλ Ïà¹Øº¯Êý */
|
extern void QSPI_CR_FIFOTHR_Set(uint32_t SetValue);
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extern uint32_t QSPI_CR_FIFOTHR_Get(void);
|
|
/* ÑÓ³Ù²ÉÑùʹÄÜ
|
0£º¹Ø±ÕÑÓ³Ù²ÉÑù¹¦ÄÜ
|
1£ºÊ¹ÄÜÑÓ³Ù²ÉÑù¹¦ÄÜ Ïà¹Øº¯Êý */
|
extern void QSPI_CR_SSHFT_Setable(FunState NewState);
|
extern FunState QSPI_CR_SSHFT_Getable(void);
|
|
/* ×ÜÏß³¬Ê±Ê¹ÄÜ£¬´Ë¼Ä´æÆ÷½öÔÚ´æ´¢Æ÷Ó³ÉäģʽÏÂÓÐЧ
|
µ±BUSYÖÃλºó£¬Èç¹ûQuadSPI²»·¢Æð¶ÔQSPI´æ´¢Æ÷µÄ·ÃÎÊ£¬³¬Ê±¼Ä´æÆ÷¿ªÊ¼¼ÆÊý£¬¼ÆÊýÒç³ö³¤¶ÈÓÉTIMEOUT¼Ä´æÆ÷¶¨Òå¡£µ±QSPI×ÜÏß³¤Ê±¼äÎÞ¶¯×÷£¬¼ÆÊýÆ÷Òç³ö£¬nCS±»×Ô¶¯À¸ß£¬Ç¿ÖƽáÊøµ±Ç°´«Êä¹ý³Ì¡£
|
0£º¹Ø±Õ³¬Ê±¹¦ÄÜ
|
1£ºÊ¹Äܳ¬Ê±¹¦ÄÜ Ïà¹Øº¯Êý */
|
extern void QSPI_CR_TCEN_Setable(FunState NewState);
|
extern FunState QSPI_CR_TCEN_Getable(void);
|
|
/* DMAʹÄÜ
|
0£ºDMA¹¦Äܹرգ¬QuadSPI²»»á·¢ËÍDMAÇëÇó
|
1£ºDMA¹¦ÄÜ¿ªÆô£¬QuadSPIÔÚÂú×ãÌõ¼þʱ·¢ËÍDMAÇëÇó Ïà¹Øº¯Êý */
|
extern void QSPI_CR_DMAEN_Setable(FunState NewState);
|
extern FunState QSPI_CR_DMAEN_Getable(void);
|
|
/* µ±Ç°´«ÊäÖÕÖ¹¼Ä´æÆ÷£¬Èí¼þд1ÖÕÖ¹´«Ê䣬Ӳ¼þÀ¸ßnCSºó×Ô¶¯ÇåÁã Ïà¹Øº¯Êý */
|
extern void QSPI_CR_ABORT_Setable(FunState NewState);
|
extern FunState QSPI_CR_ABORT_Getable(void);
|
|
/* QuadSPIÄ£¿éʹÄÜ
|
0£º¹Ø±ÕQuadSPI
|
1£ºÊ¹ÄÜQuadSPI Ïà¹Øº¯Êý */
|
extern void QSPI_CR_EN_Setable(FunState NewState);
|
extern FunState QSPI_CR_EN_Getable(void);
|
|
/* nCS×îС¸ßµçƽʱ¼ä£¬¶¨ÒåÁËÁ¬ÐøÁ½¸öÖ¡Ö®¼änCSËùÐè±£³Ö¸ßµçƽµÄ×î¶Ìʱ¼ä£¬ÒÔQSPI_CLKÖÜÆÚ¼ÆÊý
|
0£ºÖÁÉÙ1 cycle
|
1£ºÖÁÉÙ2 cycles
|
¡¡
|
7£ºÖÁÉÙ8 cycles Ïà¹Øº¯Êý */
|
extern void QSPI_CFG_CSHT_Set(uint32_t SetValue);
|
extern uint32_t QSPI_CFG_CSHT_Get(void);
|
|
/* SPI Clock Mode¼Ä´æÆ÷
|
0£ºmode 0
|
1£ºmode 3 Ïà¹Øº¯Êý */
|
extern void QSPI_CFG_CKMODE_Set(uint32_t SetValue);
|
extern uint32_t QSPI_CFG_CKMODE_Get(void);
|
|
/* FIFOˮλ±êÖ¾
|
´Ë¼Ä´æÆ÷±íʾµ±Ç°FIFOÖб£´æµÄÊý¾Ý×Ö½ÚÊý£¬0±íʾFIFO¿Õ£¬16±íʾFIFOÂú
|
×Ô¶¯²éѯģʽÏ´˼ĴæÆ÷±£³Ö0 Ïà¹Øº¯Êý */
|
extern uint32_t QSPI_SR_FIFOLVL_Get(void);
|
|
/* 1±íʾQuadSPI´«Êä½øÐÐÖУ¬Í¨ÐŽáÊøºó×Ô¶¯ÇåÁã Ïà¹Øº¯Êý */
|
extern FlagStatus QSPI_SR_BUSY_Chk(void);
|
|
/* ³¬Ê±±êÖ¾£¬Ó²¼þÖÃ룬Èí¼þд1ÇåÁã Ïà¹Øº¯Êý */
|
extern void QSPI_SR_TOF_Clr(void);
|
extern FlagStatus QSPI_SR_TOF_Chk(void);
|
|
/* ×Ô¶¯²éѯģʽϱíÕ÷״̬¼Ä´æÆ÷Æ¥Åä³É¹¦£¬Ó²¼þÖÃ룬Èí¼þд1ÇåÁã Ïà¹Øº¯Êý */
|
extern void QSPI_SR_SMF_Clr(void);
|
extern FlagStatus QSPI_SR_SMF_Chk(void);
|
|
/* FIFO threshold±êÖ¾£¬FIFOˮλ¸ßÓÚÉ趨ãÐֵʱ×Ô¶¯ÖÃ룬µÍÓÚãÐֵʱ×Ô¶¯ÇåÁã
|
×Ô¶¯²éѯģʽÏ£¬Ã¿´Î¶Á»ØÒ»×é״ֵ̬ºó¶¼»á×Ô¶¯ÖÃλFTF£¬Èç¹ûÈí¼þ¶ÁÈ¡QSPI_DATA¼Ä´æÆ÷ÔòFTFÇåÁã Ïà¹Øº¯Êý */
|
extern FlagStatus QSPI_SR_FTF_Chk(void);
|
|
/* ´«ÊäÍê³É±êÖ¾£¬Ó²¼þÖÃ룬Èí¼þд1ÇåÁã Ïà¹Øº¯Êý */
|
extern void QSPI_SR_TCF_Clr(void);
|
extern FlagStatus QSPI_SR_TCF_Chk(void);
|
|
/* ´«ÊäÊý¾Ý³¤¶ÈΪDATALEN+1£¨bytes£© Ïà¹Øº¯Êý */
|
extern void QSPI_DATALEN_Write(uint32_t SetValue);
|
extern uint32_t QSPI_DATALEN_Read(void);
|
|
/* QuadSPI ͨÐÅ¿ØÖƼĴæÆ÷ Ïà¹Øº¯Êý */
|
#define QSPI_CCR_DUMCYC_SET(value) ((value << QSPI_CCR_DUMCYC_Pos) & QSPI_CCR_DUMCYC_Msk)
|
#define QSPI_CCR_DUMCYC_GET(value) ((value >> QSPI_CCR_DUMCYC_Pos) & QSPI_CCR_DUMCYC_Msk)
|
#define QSPI_CCR_INSTRUCTION_SET(value) ((value << QSPI_CCR_INSTRUCTION_Pos) & QSPI_CCR_INSTRUCTION_Msk)
|
#define QSPI_CCR_INSTRUCTION_GET(value) ((value >> QSPI_CCR_INSTRUCTION_Pos) & QSPI_CCR_INSTRUCTION_Msk)
|
|
extern void QSPI_CCR_Write(uint32_t SetValue);
|
extern uint32_t QSPI_CCR_Read(void);
|
|
/* ·¢Ë͸øQSPI´æ´¢Æ÷µÄµØÖ·£¬ÔÚ´æ´¢Æ÷Ó³ÉäģʽÏÂÎÞЧ Ïà¹Øº¯Êý */
|
extern void QSPI_ADDR_Write(uint32_t SetValue);
|
extern uint32_t QSPI_ADDR_Read(void);
|
|
/* ·¢Ë͸øQSPI´æ´¢Æ÷µÄalternate bytes Ïà¹Øº¯Êý */
|
extern void QSPI_ABR_Write(uint32_t SetValue);
|
extern uint32_t QSPI_ABR_Read(void);
|
|
/* QSPIÊý¾Ý¼Ä´æÆ÷
|
ÍâÉèģʽд²Ù×÷ʱ£¬¶ÔQSPI_DR¼Ä´æÆ÷дÈëµÄÊý¾Ý½«±»push FIFO£¬Ö§³Ö×Ö½Ú¡¢°ë×Ö¡¢×ÖдÈ룬·Ö±ð¶ÔFIFOѹÈë1¡¢2¡¢4×Ö½Ú£»Èç¹ûдÈë×Ö½ÚÊý´óÓÚFIFOÖпÕ×Ö½ÚÊý£¬µ±Ç°Ð´²Ù×÷±»¹ÒÆð£¬Ö±µ½FIFOÖÐÓÐ×ã¹»¿Õ¼äÈÝÄɵ±Ç°Ð´ÈëÊý¾Ý¡£
|
ÍâÉèģʽ¶Á²Ù×÷ʱ£¬¶ÁÈ¡QSPI_DR¼Ä´æÆ÷½«pop FIFO£¬Ö§³Ö×Ö½Ú¡¢°ë×Ö¡¢×Ö¶ÁÈ¡£¬·Ö±ð´ÓFIFOµ¯³ö1¡¢2¡¢4×Ö½Ú£»Èç¹û¶ÁÈ¡×Ö½ÚÊý´óÓÚFIFOÖÐÓÐЧ×Ö½ÚÊý£¬µ±Ç°¶Á²Ù×÷±»¹ÒÆð£¬Ö±µ½FIFOÖÐÓÐ×ã¹»×Ö½Ú¿ÉÒÔ±»¶ÁÈ¡£¬»òÕß´«ÊäÍê³É£¬ºóÒ»ÖÖÇé¿öÏÂÖ»µ¯³ö×îºó¼¸¸öʵ¼ÊÓÐЧ×Ö½Ú¡£
|
¶ÔQSPI_DRµÄ·ÃÎʱØÐë¶ÔÆëµÍµØÖ·£¬¼´×Ö½Ú·ÃÎʱØÐë¶ÔÆëQSPI_DR[7:0]£¬°ë×Ö·ÃÎʱØÐë¶ÔÆëQSPI_DR[15:0] Ïà¹Øº¯Êý */
|
extern void QSPI_DR_WriteByte(uint8_t SetValue);
|
extern uint8_t QSPI_DR_ReadByte(void);
|
extern void QSPI_DR_WriteHalfword(uint16_t SetValue);
|
extern uint16_t QSPI_DR_ReadHalfword(void);
|
extern void QSPI_DR_WriteWord(uint32_t SetValue);
|
extern uint32_t QSPI_DR_ReadWord(void);
|
|
/* ×Ô¶¯×´Ì¬²éѯģʽϵÄ״̬mask¼Ä´æÆ÷£¬¶ÔÓ¦bitд0ÆÁ±ÎÏàӦ״̬λ Ïà¹Øº¯Êý */
|
extern void QSPI_SMSK_Write(uint32_t SetValue);
|
extern uint32_t QSPI_SMSK_Read(void);
|
|
/* ×Ô¶¯×´Ì¬²éѯģʽϵÄ״̬ƥÅä¼Ä´æÆ÷
|
±È½Ï¶ÔÏóÊÇQSPI_DATA & QSPI_SMSK Ïà¹Øº¯Êý */
|
extern void QSPI_SMAT_Write(uint32_t SetValue);
|
extern uint32_t QSPI_SMAT_Read(void);
|
|
/* ×Ô¶¯×´Ì¬²éѯģʽϵÄÂÖѯ¼ä¸ô£¨polling interval£©£¬¶¨ÒåΪQSPI_CLKÖÜÆÚÊý Ïà¹Øº¯Êý */
|
extern void QSPI_PITV_Write(uint32_t SetValue);
|
extern uint32_t QSPI_PITV_Read(void);
|
|
/* ³¬Ê±ÖÜÆÚÉèÖ㬶¨ÒåΪQSPI_CLKÖÜÆÚÊý£¬½öÔÚ´æ´¢Æ÷Ó³ÉäģʽÏÂÓÐЧ
|
µ±FIFOÂúÖ®ºó£¬QSPI×ÜÏßÐÐΪֹͣ£¬³¬Ê±¼ÆÊýÆ÷¿ªÊ¼¼ÆÊý£¬¼ÆÊýÖµµ½´ïQSPI_TOÉ趨ֵ֮ºó£¬À¸ßnCS Ïà¹Øº¯Êý */
|
extern void QSPI_TO_Write(uint32_t SetValue);
|
extern uint32_t QSPI_TO_Read(void);
|
|
//Announce_End
|
void QSPI_Deinit(void);
|
void QSPI_Init(void);
|
|
|
#ifdef __cplusplus
|
}
|
#endif
|
|
#endif /* __FM33A0XXEV_QSPI_H */
|
