/**
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******************************************************************************
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* @file fm33a0xxev_adc.h
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* @author FM33A0XXEV Application Team
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* @version V1.0.0
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* @date 16-April-2020
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* @brief This file contains all the functions prototypes for the ADC firmware library.
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __FM33A0XXEV_ADC_H
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#define __FM33A0XXEV_ADC_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "FM33A0XXEV.h"
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#define ADC_CR_ADC_IE_Pos 7 /* ADCÄÚ²¿ÀÛ¼ÓģʽÖжÏʹÄÜ */
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#define ADC_CR_ADC_IE_Msk (0x1U << ADC_CR_ADC_IE_Pos)
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#define ADC_CR_ACC_IE_Pos 6 /* ADCÍⲿÀÛ¼ÓģʽÖжÏʹÄÜ */
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#define ADC_CR_ACC_IE_Msk (0x1U << ADC_CR_ACC_IE_Pos)
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#define ADC_CR_HPEN_Pos 3 /* ADC¹¦ºÄģʽ
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0£ºµÍ¹¦ºÄģʽ£¬¹¤×÷ʱÖÓ×î¸ß1MHz
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1£º¸ß¹¦ºÄģʽ£¬¹¤×÷ʱÖÓ×î¸ß2MHz */
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#define ADC_CR_HPEN_Msk (0x1U << ADC_CR_HPEN_Pos)
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#define ADC_CR_HPEN_1MHZ (0x0U << ADC_CR_HPEN_Pos) /* µÍ¹¦ºÄģʽ£¬¹¤×÷ʱÖÓ×î¸ß1MHz */
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#define ADC_CR_HPEN_2MHZ (0x1U << ADC_CR_HPEN_Pos) /* ¸ß¹¦ºÄģʽ£¬¹¤×÷ʱÖÓ×î¸ß2MHz */
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#define ADC_CR_MODE_Pos 2 /* ADC¹¤×÷ģʽ
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0£ºÄÚ²¿ÀÛ¼ÓÆ÷ģʽ
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1£ºÍⲿÀÛ¼ÓÆ÷»òCICģʽ */
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#define ADC_CR_MODE_Msk (0x1U << ADC_CR_MODE_Pos)
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#define ADC_CR_MODE_INNER (0x0U << ADC_CR_MODE_Pos) /* ÄÚ²¿ÀÛ¼ÓÆ÷ģʽ */
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#define ADC_CR_MODE_EXTERNAL (0x1U << ADC_CR_MODE_Pos) /* ÍⲿÀÛ¼ÓÆ÷»òCICģʽ */
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#define ADC_CR_RSTCTRL_EN_Pos 1 /* »ý·ÖÆ÷¸´Î»Ê¹ÄÜ£¬ÔÚMODE=1²¢ÇÒʹÓÃÍⲿÀÛ¼ÓÆ÷ʱ£¬±ØÐëÖÃ룬ÆäËûÌõ¼þϱØÐë±£³ÖΪ0
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0£º½ûÖ¹»ý·ÖÆ÷Íⲿ¸´Î»
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1£ºÔÊÐí»ý·ÖÆ÷Íⲿ¸´Î» */
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#define ADC_CR_RSTCTRL_EN_Msk (0x1U << ADC_CR_RSTCTRL_EN_Pos)
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/* ½ûÖ¹»ý·ÖÆ÷Íⲿ¸´Î» */
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/* ÔÊÐí»ý·ÖÆ÷Íⲿ¸´Î» */
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#define ADC_CR_EN_Pos 0 /* ADCʹÄÜÐźÅ
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0£ºADC²»Ê¹ÄÜ
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1£ºADCʹÄÜ
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×¢Ò⣺RTCÖ´ÐÐ×Ô¶¯Î²¹Ê±£¬Ó²¼þ»áÖÜÆÚÐÔ×Ô¶¯Ê¹ÄÜADC */
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#define ADC_CR_EN_Msk (0x1U << ADC_CR_EN_Pos)
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/* ADC²»Ê¹ÄÜ */
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/* ADCʹÄÜ */
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/* RTCÖ´ÐÐ×Ô¶¯Î²¹Ê±£¬Ó²¼þ»áÖÜÆÚÐÔ×Ô¶¯Ê¹ÄÜADC */
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#define ADC_TRIM_ADC_TRIM_Pos 0 /* ADC TRIMÖµ£¬½öÕë¶ÔÄÚ²¿ÀÛ¼ÓÆ÷ģʽÊä³ö
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ÄÚ²¿ÀÛ¼ÓÆ÷ÀÛ¼ÓÖÜÆÚ£ºPeriod = TRIM*2*TADC_CLK
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ÀÛ¼ÓÖÜÆÚ¾ö¶¨ÁËÊä³öÊý¾Ýλ¿í£¬µ±TRIM=0x7FF×î´óֵʱ£¬Êµ¼ÊÀÛ¼ÓÖÜÆÚΪ4095 cycle£¬¼´ADCÊä³öÊý¾Ý×î´óÓÐЧλ¿íÊÇ12bit */
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#define ADC_TRIM_ADC_TRIM_Msk (0x7ffU << ADC_TRIM_ADC_TRIM_Pos)
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#define ADC_DR_ADC_DATA_Pos 0 /* ADCÊä³öÊý¾Ý£¬ÎªÂëÁ÷ÀÛ¼Ó½á¹û£¬Î´¾½µ²ÉÑùÂ˲¨Æ÷´¦Àí
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µ±MODE=0ʱ£¬Êä³öΪADCÄÚ²¿ÀÛ¼Ó½á¹û£¬×î¸ß12bit£¬Î»ÊýÓÉADC_TRIM¾ö¶¨
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µ±MODE=1ʱ£¬Êä³öλADCÍⲿÀÛ¼Ó½á¹û£¬×î¸ß14bit£¬Î»ÊýÓÉACC_PERIOD¾ö¶¨ */
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#define ADC_DR_ADC_DATA_Msk (0xffffU << ADC_DR_ADC_DATA_Pos)
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#define ADC_ISR_INIT_RDY_Pos 9 /* ADC³õʼ»¯Íê³É±êÖ¾£¬½öMODE=1ʱÓÐЧ£¨²»²úÉúÖжϣ©
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0£ºADC»¹Î´Íê³É³õʼ»¯
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1£ºADCÍê³É³õʼ»¯
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×¢£ºMODE=1£¬ADC_ENÖÃλºó£¬µÈ´ýMODE_CTRL_DELAYʱ¼äÖ®ºó£¬´Ë±êÖ¾ÖÃ룬±íʾADCÄÚ²¿»ý·ÖÆ÷½¨Á¢Íê³É¡£MODE=0ʱ£¬¹¤×÷ʱÐòÓÉADCÄÚ²¿×ÔÐпØÖÆ£¬´Ë±êÖ¾ÎÞЧ¡£ */
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#define ADC_ISR_INIT_RDY_Msk (0x1U << ADC_ISR_INIT_RDY_Pos)
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#define ADC_ISR_ACC_IF_Pos 8 /* ÀÛ¼ÓÆ÷Íê³ÉÖжϱêÖ¾£¬Ó²¼þÖÃ룬Èí¼þд1ÇåÁ㣬д0ÎÞЧ */
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#define ADC_ISR_ACC_IF_Msk (0x1U << ADC_ISR_ACC_IF_Pos)
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#define ADC_ISR_ADC_DONE_Pos 1 /* ADCת»»Íê³ÉÊä³ö£¬Èí¼þÖ»¶Á£¨²»²úÉúÖжϣ©
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ת»»Íê³Éºó´ËÐźű£³ÖΪ¸ßµçƽ£¬Ö»ÓйرÕADC²Å»áÇå0 */
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#define ADC_ISR_ADC_DONE_Msk (0x1U << ADC_ISR_ADC_DONE_Pos)
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#define ADC_ISR_ADC_IF_Pos 0 /* ADCת»»Íê³ÉÖжϱêÖ¾£¬Ó²¼þÖÃ룬Èí¼þд1ÇåÁ㣬д0ÎÞЧ */
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#define ADC_ISR_ADC_IF_Msk (0x1U << ADC_ISR_ADC_IF_Pos)
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#define ADC_CFGR_ACC_PERIOD_Pos 16 /* ÍⲿÀÛ¼ÓÆ÷ÀÛ¼ÓÖÜÆÚÅäÖ㬵¥Î»ADC_CLK
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000£º1023£¨¶ÔÓ¦½á¹û10bit£©
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001£º2047£¨¶ÔÓ¦½á¹û11bit£©
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010£º4095£¨¶ÔÓ¦½á¹û12bit£©
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011£º8191£¨¶ÔÓ¦½á¹û13bit£©
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100£º16383£¨¶ÔÓ¦½á¹û14bit£©
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Others£º4095 */
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#define ADC_CFGR_ACC_PERIOD_Msk (0x7U << ADC_CFGR_ACC_PERIOD_Pos)
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#define ADC_CFGR_ACC_PERIOD_10BITS (0x0U << ADC_CFGR_ACC_PERIOD_Pos) /* 1023£¨¶ÔÓ¦½á¹û10bit£© */
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#define ADC_CFGR_ACC_PERIOD_11BITS (0x1U << ADC_CFGR_ACC_PERIOD_Pos) /* 2047£¨¶ÔÓ¦½á¹û11bit£© */
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#define ADC_CFGR_ACC_PERIOD_12BITS (0x2U << ADC_CFGR_ACC_PERIOD_Pos) /* 4095£¨¶ÔÓ¦½á¹û12bit£© */
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#define ADC_CFGR_ACC_PERIOD_13BITS (0x3U << ADC_CFGR_ACC_PERIOD_Pos) /* 8191£¨¶ÔÓ¦½á¹û13bit£© */
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#define ADC_CFGR_ACC_PERIOD_14BITS (0x4U << ADC_CFGR_ACC_PERIOD_Pos) /* 16383£¨¶ÔÓ¦½á¹û14bit£© */
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#define ADC_CFGR_RST_CTRL_DELAY_Pos 8 /* SDADCʹÄܺómode_ctrlÑÓ³Ù³¤¶ÈÅäÖ㬵¥Î»ÊÇADC_CLKÖÜÆÚ
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0x00£º²»ÑÓ³Ù
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0xFF£ºÑÓ³Ù255¸öADC_CLK
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×¢Ò⣺¸´Î»ÖµÎª16¸öʱÖÓÖÜÆÚ£¬²»µÃÐÞ¸ÄΪСÓÚ16µÄÊýÖµ */
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#define ADC_CFGR_RST_CTRL_DELAY_Msk (0xffU << ADC_CFGR_RST_CTRL_DELAY_Pos)
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#define ADC_CFGR_BUFEN_Pos 5 /* ADCÊäÈëͨµÀBufferʹÄÜ */
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#define ADC_CFGR_BUFEN_Msk (0x1U << ADC_CFGR_BUFEN_Pos)
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#define ADC_CFGR_BUFSEL_Pos 0 /* ADCÊäÈëͨµÀÑ¡Ôñ
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0000£ºADC_IN0
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0001£ºADC_IN1
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0010£ºADC_IN2
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0011£ºADC_IN3
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0100£ºADC_IN4
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0101£ºADC_IN5
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0110£ºADC_IN6
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0111£ºADC_IN7
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1000£ºADC_IN8
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1001£ºADC_IN9
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1010£ºADC_IN10
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1011£ºADC_IN11
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1100£ºADC_IN12
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1101£ºADC_IN13
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1110£ºVBAT
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1111£ºTS */
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#define ADC_CFGR_BUFSEL_Msk (0xfU << ADC_CFGR_BUFSEL_Pos)
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#define ADC_CFGR_BUFSEL_ADC_IN1 (0x1U << ADC_CFGR_BUFSEL_Pos) /* ADC_IN1 */
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#define ADC_CFGR_BUFSEL_ADC_IN2 (0x2U << ADC_CFGR_BUFSEL_Pos) /* ADC_IN2 */
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#define ADC_CFGR_BUFSEL_ADC_IN3 (0x3U << ADC_CFGR_BUFSEL_Pos) /* ADC_IN3 */
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#define ADC_CFGR_BUFSEL_ADC_IN4 (0x4U << ADC_CFGR_BUFSEL_Pos) /* ADC_IN4 */
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#define ADC_CFGR_BUFSEL_ADC_IN5 (0x5U << ADC_CFGR_BUFSEL_Pos) /* ADC_IN5 */
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#define ADC_CFGR_BUFSEL_ADC_IN6 (0x6U << ADC_CFGR_BUFSEL_Pos) /* ADC_IN6 */
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#define ADC_CFGR_BUFSEL_ADC_IN7 (0x7U << ADC_CFGR_BUFSEL_Pos) /* ADC_IN7 */
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#define ADC_CFGR_BUFSEL_ADC_IN8 (0x8U << ADC_CFGR_BUFSEL_Pos) /* ADC_IN8 */
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#define ADC_CFGR_BUFSEL_ADC_IN9 (0x9U << ADC_CFGR_BUFSEL_Pos) /* ADC_IN9 */
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#define ADC_CFGR_BUFSEL_ADC_IN10 (0xaU << ADC_CFGR_BUFSEL_Pos) /* ADC_IN10 */
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#define ADC_CFGR_BUFSEL_ADC_IN11 (0xbU << ADC_CFGR_BUFSEL_Pos) /* ADC_IN11 */
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#define ADC_CFGR_BUFSEL_ADC_IN12 (0xcU << ADC_CFGR_BUFSEL_Pos) /* ADC_IN12 */
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#define ADC_CFGR_BUFSEL_VBAT (0xeU << ADC_CFGR_BUFSEL_Pos) /* VBAT */
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#define ADC_CFGR_BUFSEL_TS (0xfU << ADC_CFGR_BUFSEL_Pos) /* TS */
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#define CIC_DR_ADC_CIC_DATA_Pos 0 /* CICÂ˲¨Æ÷Êä³öÊý¾Ý£¬¸üÐÂƵÂÊÓÉADC¹¤×÷ʱÖÓºÍOSR¹²Í¬¾ö¶¨£»×¢ÒâÕâ¸öÊý¾ÝÊÇÓзûºÅÊý£¬¸ñʽΪ¶þ½øÖƲ¹Âë¡£ */
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#define CIC_DR_ADC_CIC_DATA_Msk (0xffffffU << CIC_DR_ADC_CIC_DATA_Pos)
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#define CIC_OS_ADC_CIC_OS_Pos 0 /* CICÂ˲¨Æ÷Êä³öÊý¾Ýoffsetµ÷Õû¼Ä´æÆ÷£¬Èí¼þдÈëoffsetÖµ£¬Ó²¼þ½«ADC_CIC_DR¼ÓÉÏOSºó¿ÉÒԵõ½ÎÞ·ûºÅ½á¹û */
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#define CIC_OS_ADC_CIC_OS_Msk (0xffffffU << CIC_OS_ADC_CIC_OS_Pos)
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#define CIC_USDR_ADC_CIC_USDR_Pos 0 /* ADC_CIC_DR + ADC_CIC_OSµÃµ½µÄÎÞ·ûºÅÊý½á¹û */
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#define CIC_USDR_ADC_CIC_USDR_Msk (0xffffffU << CIC_USDR_ADC_CIC_USDR_Pos)
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#define CIC_CR_CIC_EN_Pos 31 /* CICÂ˲¨Æ÷ʹÄÜ (CIC enable)
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0£º¹Ø±ÕCIC
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1£ºÊ¹ÄÜCIC */
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#define CIC_CR_CIC_EN_Msk (0x1U << CIC_CR_CIC_EN_Pos)
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/* ¹Ø±ÕCIC */
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/* ʹÄÜCIC */
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#define CIC_CR_NS_DISC_Pos 8 /* CICʹÄܺó¶ªÆúµÄÊä³öµãÊý (Number of Samples to be Discarded)
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¿ÉÒÔ¶ªÆúADCʹÄܺó¿ªÍ·Êä³öµÄ0~255¸ö²ÉÑùµã
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ĬÈÏÖµ0x4£¬¼´¶ªÆúÇ°4¸öת»»½á¹û£¬´ÓµÚ5¸ö½á¹û¿ªÊ¼²úÉúCIC_IF */
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#define CIC_CR_NS_DISC_Msk (0xffU << CIC_CR_NS_DISC_Pos)
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#define CIC_CR_OVR_IE_Pos 7 /* CIC Overrun Interrupt enable
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0£º½ûÖ¹CICÒç³öÖжÏ
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1£ºÔÊÐíCICÒç³öÖÐ¶Ï */
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#define CIC_CR_OVR_IE_Msk (0x1U << CIC_CR_OVR_IE_Pos)
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/* ½ûÖ¹CICÒç³öÖÐ¶Ï */
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/* ÔÊÐíCICÒç³öÖÐ¶Ï */
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#define CIC_CR_CIC_IE_Pos 6 /* CICÖжÏʹÄÜ (CIC interrupt enable)
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0£º½ûÖ¹CICÖжÏ
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1£ºÔÊÐíCICÖжϣ¬µ±CIC_IFÖÃλʱ²úÉúÖжÏʼþ */
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#define CIC_CR_CIC_IE_Msk (0x1U << CIC_CR_CIC_IE_Pos)
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/* ½ûÖ¹CICÖÐ¶Ï */
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/* ÔÊÐíCICÖжϣ¬µ±CIC_IFÖÃλʱ²úÉúÖжÏʼþ */
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#define CIC_CR_TRUNC_Pos 3 /* Êä³öÊý¾Ý½ØÈ¡¿ØÖÆ (Truncate)£¬ÅäÖÃ×îÖÕ½á¹ûÖжªÆú×îµÍλµÄλÊý£»
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±ÈÈçTRUNC=0x4£¬×îÖÕ½á¹û¶ªÆú×îµÍ4bitºó´æÈëADC_CIC_DATA¼Ä´æÆ÷ */
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#define CIC_CR_TRUNC_Msk (0x7U << CIC_CR_TRUNC_Pos)
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#define CIC_CR_OSR_Pos 0 /* ¹ý²ÉÑùÂÊÅäÖà (Over Sampling Rate)
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000£ºx8
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001£ºx16
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010£ºx32
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011£ºx64
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100£ºx128
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101£ºx256
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110£ºx512
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111£ºx1024 */
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#define CIC_CR_OSR_Msk (0x7U << CIC_CR_OSR_Pos)
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#define CIC_CR_OSR_X8 (0x0U << CIC_CR_OSR_Pos) /* x8 */
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#define CIC_CR_OSR_X16 (0x1U << CIC_CR_OSR_Pos) /* x16 */
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#define CIC_CR_OSR_X32 (0x2U << CIC_CR_OSR_Pos) /* x32 */
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#define CIC_CR_OSR_X64 (0x3U << CIC_CR_OSR_Pos) /* x64 */
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#define CIC_CR_OSR_X128 (0x4U << CIC_CR_OSR_Pos) /* x128 */
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#define CIC_CR_OSR_X256 (0x5U << CIC_CR_OSR_Pos) /* x256 */
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#define CIC_CR_OSR_X512 (0x6U << CIC_CR_OSR_Pos) /* x512 */
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#define CIC_CR_OSR_X1024 (0x7U << CIC_CR_OSR_Pos) /* x1024 */
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#define CIC_ISR_CIC_OVR_Pos 1
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#define CIC_ISR_CIC_OVR_Msk (0x1U << CIC_ISR_CIC_OVR_Pos)
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#define CIC_ISR_CIC_IF_Pos 0
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#define CIC_ISR_CIC_IF_Msk (0x1U << CIC_ISR_CIC_IF_Pos)
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//Macro_End
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/* Exported functions --------------------------------------------------------*/
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extern void ADC_Deinit(void);
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/* ADCÄÚ²¿ÀÛ¼ÓģʽÖжÏʹÄÜ Ïà¹Øº¯Êý */
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extern void ADC_CR_ADC_IE_Setable(FunState NewState);
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extern FunState ADC_CR_ADC_IE_Getable(void);
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/* ADCÍⲿÀÛ¼ÓģʽÖжÏʹÄÜ Ïà¹Øº¯Êý */
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extern void ADC_CR_ACC_IE_Setable(FunState NewState);
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extern FunState ADC_CR_ACC_IE_Getable(void);
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/* ADC¹¦ºÄģʽ
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0£ºµÍ¹¦ºÄģʽ£¬¹¤×÷ʱÖÓ×î¸ß1MHz
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1£º¸ß¹¦ºÄģʽ£¬¹¤×÷ʱÖÓ×î¸ß2MHz Ïà¹Øº¯Êý */
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extern void ADC_CR_HPEN_Set(uint32_t SetValue);
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extern uint32_t ADC_CR_HPEN_Get(void);
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/* ADC¹¤×÷ģʽ
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0£ºÄÚ²¿ÀÛ¼ÓÆ÷ģʽ
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1£ºÍⲿÀÛ¼ÓÆ÷»òCICģʽ Ïà¹Øº¯Êý */
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extern void ADC_CR_MODE_Set(uint32_t SetValue);
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extern uint32_t ADC_CR_MODE_Get(void);
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/* »ý·ÖÆ÷¸´Î»Ê¹ÄÜ£¬ÔÚMODE=1²¢ÇÒʹÓÃÍⲿÀÛ¼ÓÆ÷ʱ£¬±ØÐëÖÃ룬ÆäËûÌõ¼þϱØÐë±£³ÖΪ0
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0£º½ûÖ¹»ý·ÖÆ÷Íⲿ¸´Î»
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1£ºÔÊÐí»ý·ÖÆ÷Íⲿ¸´Î» Ïà¹Øº¯Êý */
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extern void ADC_CR_RSTCTRL_EN_Setable(FunState NewState);
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extern FunState ADC_CR_RSTCTRL_EN_Getable(void);
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/* ADCʹÄÜÐźÅ
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0£ºADC²»Ê¹ÄÜ
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1£ºADCʹÄÜ
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×¢Ò⣺RTCÖ´ÐÐ×Ô¶¯Î²¹Ê±£¬Ó²¼þ»áÖÜÆÚÐÔ×Ô¶¯Ê¹ÄÜADC Ïà¹Øº¯Êý */
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extern void ADC_CR_EN_Setable(FunState NewState);
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extern FunState ADC_CR_EN_Getable(void);
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/* ADC TRIMÖµ£¬½öÕë¶ÔÄÚ²¿ÀÛ¼ÓÆ÷ģʽÊä³ö
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ÄÚ²¿ÀÛ¼ÓÆ÷ÀÛ¼ÓÖÜÆÚ£ºPeriod = TRIM*2*TADC_CLK
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ÀÛ¼ÓÖÜÆÚ¾ö¶¨ÁËÊä³öÊý¾Ýλ¿í£¬µ±TRIM=0x7FF×î´óֵʱ£¬Êµ¼ÊÀÛ¼ÓÖÜÆÚΪ4095 cycle£¬¼´ADCÊä³öÊý¾Ý×î´óÓÐЧλ¿íÊÇ12bit Ïà¹Øº¯Êý */
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extern void ADC_TRIM_Write(uint32_t SetValue);
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extern uint32_t ADC_TRIM_Read(void);
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/* ADCÊä³öÊý¾Ý£¬ÎªÂëÁ÷ÀÛ¼Ó½á¹û£¬Î´¾½µ²ÉÑùÂ˲¨Æ÷´¦Àí
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µ±MODE=0ʱ£¬Êä³öΪADCÄÚ²¿ÀÛ¼Ó½á¹û£¬×î¸ß12bit£¬Î»ÊýÓÉADC_TRIM¾ö¶¨
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µ±MODE=1ʱ£¬Êä³öλADCÍⲿÀÛ¼Ó½á¹û£¬×î¸ß14bit£¬Î»ÊýÓÉACC_PERIOD¾ö¶¨ Ïà¹Øº¯Êý */
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extern uint32_t ADC_DR_Read(void);
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/* ADC³õʼ»¯Íê³É±êÖ¾£¬½öMODE=1ʱÓÐЧ£¨²»²úÉúÖжϣ©
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0£ºADC»¹Î´Íê³É³õʼ»¯
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1£ºADCÍê³É³õʼ»¯
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×¢£ºMODE=1£¬ADC_ENÖÃλºó£¬µÈ´ýMODE_CTRL_DELAYʱ¼äÖ®ºó£¬´Ë±êÖ¾ÖÃ룬±íʾADCÄÚ²¿»ý·ÖÆ÷½¨Á¢Íê³É¡£MODE=0ʱ£¬¹¤×÷ʱÐòÓÉADCÄÚ²¿×ÔÐпØÖÆ£¬´Ë±êÖ¾ÎÞЧ¡£ Ïà¹Øº¯Êý */
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extern FlagStatus ADC_ISR_INIT_RDY_Chk(void);
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/* ÀÛ¼ÓÆ÷Íê³ÉÖжϱêÖ¾£¬Ó²¼þÖÃ룬Èí¼þд1ÇåÁ㣬д0ÎÞЧ Ïà¹Øº¯Êý */
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extern void ADC_ISR_ACC_IF_Clr(void);
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extern FlagStatus ADC_ISR_ACC_IF_Chk(void);
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/* ADCת»»Íê³ÉÊä³ö£¬Èí¼þÖ»¶Á£¨²»²úÉúÖжϣ©
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ת»»Íê³Éºó´ËÐźű£³ÖΪ¸ßµçƽ£¬Ö»ÓйرÕADC²Å»áÇå0 Ïà¹Øº¯Êý */
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extern FlagStatus ADC_ISR_ADC_DONE_Chk(void);
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/* ADCת»»Íê³ÉÖжϱêÖ¾£¬Ó²¼þÖÃ룬Èí¼þд1ÇåÁ㣬д0ÎÞЧ Ïà¹Øº¯Êý */
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extern void ADC_ISR_ADC_IF_Clr(void);
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extern FlagStatus ADC_ISR_ADC_IF_Chk(void);
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/* ÍⲿÀÛ¼ÓÆ÷ÀÛ¼ÓÖÜÆÚÅäÖ㬵¥Î»ADC_CLK
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000£º1023£¨¶ÔÓ¦½á¹û10bit£©
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001£º2047£¨¶ÔÓ¦½á¹û11bit£©
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100£º16383£¨¶ÔÓ¦½á¹û14bit£©
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Others£º4095 Ïà¹Øº¯Êý */
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extern void ADC_CFGR_ACC_PERIOD_Set(uint32_t SetValue);
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extern uint32_t ADC_CFGR_ACC_PERIOD_Get(void);
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/* SDADCʹÄܺómode_ctrlÑÓ³Ù³¤¶ÈÅäÖ㬵¥Î»ÊÇADC_CLKÖÜÆÚ
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0x00£º²»ÑÓ³Ù
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0xFF£ºÑÓ³Ù255¸öADC_CLK
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×¢Ò⣺¸´Î»ÖµÎª16¸öʱÖÓÖÜÆÚ£¬²»µÃÐÞ¸ÄΪСÓÚ16µÄÊýÖµ Ïà¹Øº¯Êý */
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extern void ADC_CFGR_RST_CTRL_DELAY_Set(uint32_t SetValue);
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extern uint32_t ADC_CFGR_RST_CTRL_DELAY_Get(void);
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/* ADCÊäÈëͨµÀBufferʹÄÜ Ïà¹Øº¯Êý */
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extern void ADC_CFGR_BUFEN_Setable(FunState NewState);
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extern FunState ADC_CFGR_BUFEN_Getable(void);
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/* ADCÊäÈëͨµÀÑ¡Ôñ
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0000£ºADC_IN0
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0001£ºADC_IN1
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0010£ºADC_IN2
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0011£ºADC_IN3
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0100£ºADC_IN4
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0101£ºADC_IN5
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0110£ºADC_IN6
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0111£ºADC_IN7
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1000£ºADC_IN8
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1001£ºADC_IN9
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1010£ºADC_IN10
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1011£ºADC_IN11
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1100£ºADC_IN12
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1101£ºADC_IN13
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1110£ºVBAT
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1111£ºTS Ïà¹Øº¯Êý */
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extern void ADC_CFGR_BUFSEL_Set(uint32_t SetValue);
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extern uint32_t ADC_CFGR_BUFSEL_Get(void);
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/* CICÂ˲¨Æ÷Êä³öÊý¾Ý£¬¸üÐÂƵÂÊÓÉADC¹¤×÷ʱÖÓºÍOSR¹²Í¬¾ö¶¨£»×¢ÒâÕâ¸öÊý¾ÝÊÇÓзûºÅÊý£¬¸ñʽΪ¶þ½øÖƲ¹Âë¡£ Ïà¹Øº¯Êý */
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extern uint32_t CIC_DR_Read(void);
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/* CICÂ˲¨Æ÷Êä³öÊý¾Ýoffsetµ÷Õû¼Ä´æÆ÷£¬Èí¼þдÈëoffsetÖµ£¬Ó²¼þ½«ADC_CIC_DR¼ÓÉÏOSºó¿ÉÒԵõ½ÎÞ·ûºÅ½á¹û Ïà¹Øº¯Êý */
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extern void ACIC_OS_Write(uint32_t SetValue);
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extern uint32_t CIC_OS_Read(void);
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/* ADC_CIC_DR + ADC_CIC_OSµÃµ½µÄÎÞ·ûºÅÊý½á¹û Ïà¹Øº¯Êý */
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extern uint32_t CIC_USDR_Read(void);
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/* CICÂ˲¨Æ÷ʹÄÜ (CIC enable)
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0£º¹Ø±ÕCIC
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1£ºÊ¹ÄÜCIC Ïà¹Øº¯Êý */
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extern void CIC_CR_CIC_EN_Setable(FunState NewState);
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extern FunState CIC_CR_CIC_EN_Getable(void);
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/* CICʹÄܺó¶ªÆúµÄÊä³öµãÊý (Number of Samples to be Discarded)
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¿ÉÒÔ¶ªÆúADCʹÄܺó¿ªÍ·Êä³öµÄ0~255¸ö²ÉÑùµã
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ĬÈÏÖµ0x4£¬¼´¶ªÆúÇ°4¸öת»»½á¹û£¬´ÓµÚ5¸ö½á¹û¿ªÊ¼²úÉúCIC_IF Ïà¹Øº¯Êý */
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extern void ACIC_CR_NS_DISC_Set(uint32_t SetValue);
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extern uint32_t CIC_CR_NS_DISC_Get(void);
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/* CIC Overrun Interrupt enable
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0£º½ûÖ¹CICÒç³öÖжÏ
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1£ºÔÊÐíCICÒç³öÖÐ¶Ï Ïà¹Øº¯Êý */
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extern void CIC_CR_OVR_IE_Setable(FunState NewState);
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extern FunState CIC_CR_OVR_IE_Getable(void);
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/* CICÖжÏʹÄÜ (CIC interrupt enable)
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0£º½ûÖ¹CICÖжÏ
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1£ºÔÊÐíCICÖжϣ¬µ±CIC_IFÖÃλʱ²úÉúÖжÏʼþ Ïà¹Øº¯Êý */
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extern void CIC_CR_CIC_IE_Setable(FunState NewState);
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extern FunState IC_CR_CIC_IE_Getable(void);
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/* Êä³öÊý¾Ý½ØÈ¡¿ØÖÆ (Truncate)£¬ÅäÖÃ×îÖÕ½á¹ûÖжªÆú×îµÍλµÄλÊý£»
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±ÈÈçTRUNC=0x4£¬×îÖÕ½á¹û¶ªÆú×îµÍ4bitºó´æÈëADC_CIC_DATA¼Ä´æÆ÷ Ïà¹Øº¯Êý */
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extern void CIC_CR_TRUNC_Set(uint32_t SetValue);
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extern uint32_t CIC_CR_TRUNC_Get(void);
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/* ¹ý²ÉÑùÂÊÅäÖà (Over Sampling Rate)
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000£ºx8
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001£ºx16
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010£ºx32
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011£ºx64
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100£ºx128
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101£ºx256
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110£ºx512
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111£ºx1024 Ïà¹Øº¯Êý */
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extern void CIC_CR_OSR_Set(uint32_t SetValue);
|
extern uint32_t CIC_CR_OSR_Get(void);
|
extern void CIC_ISR_CIC_OVR_Clr(void);
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extern FlagStatus CIC_ISR_CIC_OVR_Chk(void);
|
extern void CIC_ISR_CIC_IF_Clr(void);
|
extern FlagStatus CIC_ISR_CIC_IF_Chk(void);
|
|
#ifdef __cplusplus
|
}
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#endif
|
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#endif /* __FM33A0XXEV_ADC_H */
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