/**
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******************************************************************************
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* @file fm33a0xxev_lpuart.c
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* @author FM33A0XXEV Application Team
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* @version V1.0.0
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* @date 16-April-2020
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* @brief This file provides firmware functions to manage the following
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* functionalities of....:
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*
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "fm33a0xxev_lpuart.h"
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/** @addtogroup fm33a0xxev_StdPeriph_Driver
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* @{
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*/
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/** @defgroup LPUART
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* @brief LPUART driver modules
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* @{
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*/
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/* LPUARTͨÐűêÖ¾£¬Ö»¶Á (Busy)
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1£ºLPUARTÕýÔÚͨÐÅÖÐ
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0£ºLPUART¿ÕÏÐ Ïà¹Øº¯Êý */
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FlagStatus LPUARTx_CSR_BUSY_Chk(LPUART_Type* LPUARTx)
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{
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if (LPUARTx ->CSR & LPUARTx_CSR_BUSY_Msk)
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{
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return SET;
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}
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else
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{
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return RESET;
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}
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}
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/* Êý¾Ý½ÓÊÕ»½ÐÑÌõ¼þÅäÖà Ïà¹Øº¯Êý */
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void LPUARTx_CSR_WKBYTECFG_Setable(LPUART_Type* LPUARTx, FunState NewState)
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{
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if (NewState == ENABLE)
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{
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LPUARTx->CSR |= (LPUARTx_CSR_WKBYTECFG_Msk);
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}
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else
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{
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LPUARTx->CSR &= ~(LPUARTx_CSR_WKBYTECFG_Msk);
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}
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}
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/* Êý¾Ý½ÓÊÕ»½ÐÑÌõ¼þÅäÖà (Wakeup Byte Config)
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1£º½ÓÊÕÍê1×Ö½Ú£¬²¢ÇÒÆæżУÑéºÍSTOPλ¶¼ÕýÈ·£¬²Å´¥·¢»½ÐÑÖжÏ
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0£º½ÓÊÕÍê1×Ö½Ú£¬²»¼ì²éУÑéλºÍSTOPλ£¬Ö±½Ó´¥·¢»½ÐÑÖÐ¶Ï Ïà¹Øº¯Êý */
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FlagStatus LPUARTx_CSR_WKBYTECFG_Chk(LPUART_Type* LPUARTx)
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{
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if (LPUARTx ->CSR & LPUARTx_CSR_WKBYTECFG_Msk)
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{
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return SET;
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}
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else
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{
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return RESET;
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}
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}
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/* »½ÐÑÖжÏʼþÅäÖã¬ÓÃÓÚ¿ØÖƺÎÖÖʼþÏÂÏòCPUÌṩ»½ÐÑÖжÏ
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(Receive Wakeup Event)
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00£ºSTARTλ¼ì²â»½ÐÑ
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01£º1byteÊý¾Ý½ÓÊÕÍê³É
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10£º½ÓÊÕÊý¾ÝÆ¥Åä³É¹¦
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11£ºRXDϽµÑؼì²â Ïà¹Øº¯Êý */
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void LPUARTx_CSR_RXEV_Set(LPUART_Type* LPUARTx,uint32_t SetValue)
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{
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uint32_t tmpreg;
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tmpreg = LPUARTx ->CSR;
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tmpreg &= ~(LPUARTx_CSR_RXEV_Msk);
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tmpreg |= (SetValue & LPUARTx_CSR_RXEV_Msk);
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LPUARTx ->CSR = tmpreg;
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}
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uint32_t LPUARTx_CSR_RXEV_Get(LPUART_Type* LPUARTx)
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{
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return (LPUARTx ->CSR & LPUARTx_CSR_RXEV_Msk);
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}
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/* RXÓëTXÒý½Å½»»»
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0£ºÄ¬ÈÏ
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1£º½»»» */
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void LPUARTx_CSR_IOSWAP_Set(LPUART_Type* LPUARTx,uint32_t SetValue)
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{
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uint32_t tmpreg;
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tmpreg = LPUARTx ->CSR;
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tmpreg &= ~(LPUARTx_CSR_IOSWAP_Msk);
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tmpreg |= (SetValue & LPUARTx_CSR_IOSWAP_Msk);
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LPUARTx ->CSR = tmpreg;
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}
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uint32_t LPUARTx_CSR_IOSWAP_Get(LPUART_Type* LPUARTx)
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{
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return (LPUARTx ->CSR & LPUARTx_CSR_IOSWAP_Msk);
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}
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/* DMA·¢ËÍÍê³ÉÖжÏʹÄÜ£¬½öÔÚLPUARTͨ¹ýDMA½øÐз¢ËÍʱÓÐЧ (DMA Transmit Interrupt Config)
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1£ºIE=1µÄÇé¿öÏ£¬DMAģʽÏ·¢ËÍÍê×îºóÒ»Ö¡ºó£¬ÔÊÐíÖжÏÐźÅÊä³ö£»×îºóһ֮֡ǰµÄÊý¾ÝÖ¡·¢ËÍÍê³Éºó²»ÔÊÐíÖжÏÐźÅÊä³ö
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0£ºÊÇ·ñÔÊÐíÖжÏÐźÅÊä³ö½öÓÉIE¾ö¶¨ Ïà¹Øº¯Êý */
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void LPUARTx_CSR_DMATXIFCFG_Setable(LPUART_Type* LPUARTx,FunState NewState)
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{
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if (NewState == ENABLE)
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{
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LPUARTx ->CSR |= (LPUARTx_CSR_DMATXIFCFG_Msk);
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}
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else
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{
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LPUARTx ->CSR &= ~(LPUARTx_CSR_DMATXIFCFG_Msk);
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}
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}
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FunState LPUARTx_CSR_DMATXIFCFG_Getable(LPUART_Type* LPUARTx)
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{
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if (LPUARTx ->CSR & (LPUARTx_CSR_DMATXIFCFG_Msk))
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{
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return ENABLE;
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}
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else
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{
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return DISABLE;
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}
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}
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/* Êý¾Ý·¢ËÍ/½ÓÊÕʱµÄλ˳Ðò (Bit Order)
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0£ºLSB first
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1£ºMSB first Ïà¹Øº¯Êý */
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void LPUARTx_CSR_BITORD_Set(LPUART_Type* LPUARTx,uint32_t SetValue)
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{
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uint32_t tmpreg;
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tmpreg = LPUARTx ->CSR;
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tmpreg &= ~(LPUARTx_CSR_BITORD_Msk);
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tmpreg |= (SetValue & LPUARTx_CSR_BITORD_Msk);
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LPUARTx ->CSR = tmpreg;
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}
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uint32_t LPUARTx_CSR_BITORD_Get(LPUART_Type* LPUARTx)
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{
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return (LPUARTx ->CSR & LPUARTx_CSR_BITORD_Msk);
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}
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/* ֹͣλ¿í¶ÈÅäÖ㬽ö¶Ô·¢ËÍÖ¡¸ñʽÓÐЧ£¬½ÓÊÕʱ²»ÅжÏֹͣλ¸öÊý (Stop bit Config)
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0£º1λֹͣλ
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1£º2λֹͣλ Ïà¹Øº¯Êý */
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void LPUARTx_CSR_STOPCFG_Set(LPUART_Type* LPUARTx,uint32_t SetValue)
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{
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uint32_t tmpreg;
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tmpreg = LPUARTx ->CSR;
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tmpreg &= ~(LPUARTx_CSR_STOPCFG_Msk);
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tmpreg |= (SetValue & LPUARTx_CSR_STOPCFG_Msk);
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LPUARTx ->CSR = tmpreg;
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}
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uint32_t LPUARTx_CSR_STOPCFG_Get(LPUART_Type* LPUARTx)
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{
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return (LPUARTx ->CSR & LPUARTx_CSR_STOPCFG_Msk);
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}
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/* ÿ֡Êý¾Ý³¤¶ÈÑ¡Ôñ£»´Ë¼Ä´æÆ÷¶ÔÊý¾Ý·¢ËͺͽÓÊÕͬʱÓÐЧ
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(Payload Data length Select)
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00£º7λÊý¾Ý
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01£º8λÊý¾Ý
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10£º9λÊý¾Ý
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11£º6λÊý¾Ý Ïà¹Øº¯Êý */
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void LPUARTx_CSR_PDSEL_Set(LPUART_Type* LPUARTx,uint32_t SetValue)
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{
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uint32_t tmpreg;
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tmpreg = LPUARTx ->CSR;
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tmpreg &= ~(LPUARTx_CSR_PDSEL_Msk);
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tmpreg |= (SetValue & LPUARTx_CSR_PDSEL_Msk);
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LPUARTx ->CSR = tmpreg;
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}
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uint32_t LPUARTx_CSR_PDSEL_Get(LPUART_Type* LPUARTx)
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{
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return (LPUARTx ->CSR & LPUARTx_CSR_PDSEL_Msk);
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}
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/* УÑéλÅäÖ㻴˼ĴæÆ÷¶ÔÊý¾Ý·¢ËͺͽÓÊÕͬʱÓÐЧ (Parity)
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00£ºÎÞУÑéλ
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01£ºÅ¼Ð£Ñé
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10£ºÆæУÑé
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11£ºRFU Ïà¹Øº¯Êý */
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void LPUARTx_CSR_PARITY_Set(LPUART_Type* LPUARTx,uint32_t SetValue)
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{
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uint32_t tmpreg;
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tmpreg = LPUARTx ->CSR;
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tmpreg &= ~(LPUARTx_CSR_PARITY_Msk);
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tmpreg |= (SetValue & LPUARTx_CSR_PARITY_Msk);
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LPUARTx ->CSR = tmpreg;
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}
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uint32_t LPUARTx_CSR_PARITY_Get(LPUART_Type* LPUARTx)
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{
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return (LPUARTx ->CSR & LPUARTx_CSR_PARITY_Msk);
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}
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/* ½ÓÊÕÊý¾Ý¼«ÐÔÅäÖà (Receive Polarity)
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0£ºÕýÏò
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1£ºÈ¡·´ Ïà¹Øº¯Êý */
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void LPUARTx_CSR_RXPOL_Set(LPUART_Type* LPUARTx,uint32_t SetValue)
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{
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uint32_t tmpreg;
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tmpreg = LPUARTx ->CSR;
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tmpreg &= ~(LPUARTx_CSR_RXPOL_Msk);
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tmpreg |= (SetValue & LPUARTx_CSR_RXPOL_Msk);
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LPUARTx ->CSR = tmpreg;
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}
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uint32_t LPUARTx_CSR_RXPOL_Get(LPUART_Type* LPUARTx)
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{
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return (LPUARTx ->CSR & LPUARTx_CSR_RXPOL_Msk);
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}
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/* ·¢ËÍÊý¾Ý¼«ÐÔÅäÖà (Transmit Polarity)
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0£ºÕýÏò
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1£ºÈ¡·´ Ïà¹Øº¯Êý */
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void LPUARTx_CSR_TXPOL_Set(LPUART_Type* LPUARTx,uint32_t SetValue)
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{
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uint32_t tmpreg;
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tmpreg = LPUARTx ->CSR;
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tmpreg &= ~(LPUARTx_CSR_TXPOL_Msk);
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tmpreg |= (SetValue & LPUARTx_CSR_TXPOL_Msk);
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LPUARTx ->CSR = tmpreg;
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}
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uint32_t LPUARTx_CSR_TXPOL_Get(LPUART_Type* LPUARTx)
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{
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return (LPUARTx ->CSR & LPUARTx_CSR_TXPOL_Msk);
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}
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/* ½ÓÊÕʹÄÜ£¬1ÓÐЧ (Receive Enable) Ïà¹Øº¯Êý */
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void LPUARTx_CSR_RXEN_Setable(LPUART_Type* LPUARTx,FunState NewState)
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{
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if (NewState == ENABLE)
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{
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LPUARTx ->CSR |= (LPUARTx_CSR_RXEN_Msk);
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}
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else
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{
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LPUARTx ->CSR &= ~(LPUARTx_CSR_RXEN_Msk);
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}
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}
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FunState LPUARTx_CSR_RXEN_Getable(LPUART_Type* LPUARTx)
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{
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if (LPUARTx ->CSR & (LPUARTx_CSR_RXEN_Msk))
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{
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return ENABLE;
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}
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else
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{
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return DISABLE;
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}
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}
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/* ·¢ËÍʹÄÜ£¬1ÓÐЧ (Transmit Enable) Ïà¹Øº¯Êý */
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void LPUARTx_CSR_TXEN_Setable(LPUART_Type* LPUARTx,FunState NewState)
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{
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if (NewState == ENABLE)
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{
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LPUARTx ->CSR |= (LPUARTx_CSR_TXEN_Msk);
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}
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else
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{
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LPUARTx ->CSR &= ~(LPUARTx_CSR_TXEN_Msk);
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}
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}
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FunState LPUARTx_CSR_TXEN_Getable(LPUART_Type* LPUARTx)
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{
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if (LPUARTx ->CSR & (LPUARTx_CSR_TXEN_Msk))
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{
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return ENABLE;
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}
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else
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{
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return DISABLE;
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}
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}
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/* ½ÓÊÕ»½ÐÑʼþÖжÏʹÄÜ£¬1ÓÐЧ (Receive Event Interrupt Enable) Ïà¹Øº¯Êý */
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void LPUARTx_IER_RXEV_IE_Setable(LPUART_Type* LPUARTx,FunState NewState)
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{
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if (NewState == ENABLE)
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{
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LPUARTx ->IER |= (LPUARTx_IER_RXEV_IE_Msk);
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}
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else
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{
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LPUARTx ->IER &= ~(LPUARTx_IER_RXEV_IE_Msk);
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}
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}
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FunState LPUARTx_IER_RXEV_IE_Getable(LPUART_Type* LPUARTx)
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{
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if (LPUARTx ->IER & (LPUARTx_IER_RXEV_IE_Msk))
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{
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return ENABLE;
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}
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else
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{
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return DISABLE;
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}
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}
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/* ½ÓÊÕ´íÎóÖжÏʹÄÜ£¬1ÓÐЧ (Receive Error Interrupt Enable) Ïà¹Øº¯Êý */
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void LPUARTx_IER_RXERR_IE_Setable(LPUART_Type* LPUARTx,FunState NewState)
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{
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if (NewState == ENABLE)
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{
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LPUARTx ->IER |= (LPUARTx_IER_RXERR_IE_Msk);
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}
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else
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{
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LPUARTx ->IER &= ~(LPUARTx_IER_RXERR_IE_Msk);
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}
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}
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FunState LPUARTx_IER_RXERR_IE_Getable(LPUART_Type* LPUARTx)
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{
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if (LPUARTx ->IER & (LPUARTx_IER_RXERR_IE_Msk))
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{
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return ENABLE;
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}
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else
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{
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return DISABLE;
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}
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}
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/* ½ÓÊÕ»º´æÂúÖжÏʹÄÜ£¬1ÓÐЧ (Receive Buffer Full Interrupt Enable) Ïà¹Øº¯Êý */
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void LPUARTx_IER_RXBF_IE_Setable(LPUART_Type* LPUARTx,FunState NewState)
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{
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if (NewState == ENABLE)
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{
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LPUARTx ->IER |= (LPUARTx_IER_RXBF_IE_Msk);
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}
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else
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{
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LPUARTx ->IER &= ~(LPUARTx_IER_RXBF_IE_Msk);
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}
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}
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FunState LPUARTx_IER_RXBF_IE_Getable(LPUART_Type* LPUARTx)
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{
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if (LPUARTx ->IER & (LPUARTx_IER_RXBF_IE_Msk))
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{
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return ENABLE;
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}
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else
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{
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return DISABLE;
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}
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}
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/* ·¢ËÍ»º´æ¿ÕÖжÏʹÄÜ£¬1ÓÐЧ (Transmit Buffer Empty Interrupt Enable) Ïà¹Øº¯Êý */
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void LPUARTx_IER_TXBE_IE_Setable(LPUART_Type* LPUARTx,FunState NewState)
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{
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if (NewState == ENABLE)
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{
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LPUARTx ->IER |= (LPUARTx_IER_TXBE_IE_Msk);
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}
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else
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{
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LPUARTx ->IER &= ~(LPUARTx_IER_TXBE_IE_Msk);
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}
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}
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FunState LPUARTx_IER_TXBE_IE_Getable(LPUART_Type* LPUARTx)
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{
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if (LPUARTx ->IER & (LPUARTx_IER_TXBE_IE_Msk))
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{
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return ENABLE;
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}
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else
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{
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return DISABLE;
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}
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}
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/* ·¢ËÍ»º´æ¿ÕÇÒ·¢ËÍÒÆλ¼Ä´æÆ÷¿ÕÖжÏʹÄÜ£¬1ÓÐЧ (Transmit Shift register Interrupt Enable) Ïà¹Øº¯Êý */
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void LPUARTx_IER_TXSE_IE_Setable(LPUART_Type* LPUARTx,FunState NewState)
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{
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if (NewState == ENABLE)
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{
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LPUARTx ->IER |= (LPUARTx_IER_TXSE_IE_Msk);
|
}
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else
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{
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LPUARTx ->IER &= ~(LPUARTx_IER_TXSE_IE_Msk);
|
}
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}
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FunState LPUARTx_IER_TXSE_IE_Getable(LPUART_Type* LPUARTx)
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{
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if (LPUARTx ->IER & (LPUARTx_IER_TXSE_IE_Msk))
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{
|
return ENABLE;
|
}
|
else
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{
|
return DISABLE;
|
}
|
}
|
|
/* ½ÓÊÕ»½ÐÑʼþÖжϱêÖ¾£¬Ó²¼þÖÃ룬Èí¼þд1ÇåÁã (Receive Event Interrupt Flag)
|
ÖжϱêÖ¾´¥·¢Ô´ÓÉLPUxCR.RXEV¼Ä´æÆ÷ÅäÖᣠÏà¹Øº¯Êý */
|
void LPUARTx_ISR_RXEVF_Clr(LPUART_Type* LPUARTx)
|
{
|
LPUARTx ->ISR = LPUARTx_ISR_RXEVF_Msk;
|
}
|
|
FlagStatus LPUARTx_ISR_RXEVF_Chk(LPUART_Type* LPUARTx)
|
{
|
if (LPUARTx ->ISR & LPUARTx_ISR_RXEVF_Msk)
|
{
|
return SET;
|
}
|
else
|
{
|
return RESET;
|
}
|
}
|
|
/* ·¢ËÍ»º´æÒç³ö´íÎó£¬Ó²¼þÖÃ룬Èí¼þд1ÇåÁã (Transmit Overflow Error)
|
µ±·¢ËÍ»º´æÖеÄÊý¾Ý»¹Î´½øÈëÒÆλ¼Ä´æÆ÷·¢ËÍʱ£¬Èí¼þÏò·¢ËÍ»º´æдÈëÐÂÊý¾Ý£¬½«´¥·¢TXOV±êÖ¾ÖÃλ¡£ Ïà¹Øº¯Êý */
|
void LPUARTx_ISR_TXOV_Clr(LPUART_Type* LPUARTx)
|
{
|
LPUARTx ->ISR = LPUARTx_ISR_TXOV_Msk;
|
}
|
|
FlagStatus LPUARTx_ISR_TXOV_Chk(LPUART_Type* LPUARTx)
|
{
|
if (LPUARTx ->ISR & LPUARTx_ISR_TXOV_Msk)
|
{
|
return SET;
|
}
|
else
|
{
|
return RESET;
|
}
|
}
|
|
/* ÆæżУÑé´íÎóÖжϱêÖ¾£¬Ó²¼þÖÃ룬Èí¼þд1ÇåÁã (Parity Error) Ïà¹Øº¯Êý */
|
void LPUARTx_ISR_PERR_Clr(LPUART_Type* LPUARTx)
|
{
|
LPUARTx ->ISR = LPUARTx_ISR_PERR_Msk;
|
}
|
|
FlagStatus LPUARTx_ISR_PERR_Chk(LPUART_Type* LPUARTx)
|
{
|
if (LPUARTx ->ISR & LPUARTx_ISR_PERR_Msk)
|
{
|
return SET;
|
}
|
else
|
{
|
return RESET;
|
}
|
}
|
|
/* Ö¡¸ñʽ´íÎóÖжϱêÖ¾£¬Ó²¼þÖÃ룬Èí¼þд1ÇåÁã (Frame Error) Ïà¹Øº¯Êý */
|
void LPUARTx_ISR_FERR_Clr(LPUART_Type* LPUARTx)
|
{
|
LPUARTx ->ISR = LPUARTx_ISR_FERR_Msk;
|
}
|
|
FlagStatus LPUARTx_ISR_FERR_Chk(LPUART_Type* LPUARTx)
|
{
|
if (LPUARTx ->ISR & LPUARTx_ISR_FERR_Msk)
|
{
|
return SET;
|
}
|
else
|
{
|
return RESET;
|
}
|
}
|
|
/* ½ÓÊÕ»º´æÒç³ö´íÎóÖжϱêÖ¾£¬µ±½ÓÊÕ»º´æÂúµÄÇé¿öÏ£¬ÊÕµ½ÐµÄÊý¾ÝʱÖÃλ£»Ó²¼þÖÃ룬Èí¼þд1ÇåÁã (Receive Buffer Overflow Error) Ïà¹Øº¯Êý */
|
void LPUARTx_ISR_OERR_Clr(LPUART_Type* LPUARTx)
|
{
|
LPUARTx ->ISR = LPUARTx_ISR_OERR_Msk;
|
}
|
|
FlagStatus LPUARTx_ISR_OERR_Chk(LPUART_Type* LPUARTx)
|
{
|
if (LPUARTx ->ISR & LPUARTx_ISR_OERR_Msk)
|
{
|
return SET;
|
}
|
else
|
{
|
return RESET;
|
}
|
}
|
|
/* ½ÓÊÕ»º´æÂúÖжϱêÖ¾£¬Ó²¼þÖÃ룬Èí¼þд1»òÕ߶ÁÈ¡RXBUFʱÇåÁã (Receive Buffer Full) Ïà¹Øº¯Êý */
|
void LPUARTx_ISR_RXBF_Clr(LPUART_Type* LPUARTx)
|
{
|
LPUARTx ->ISR = LPUARTx_ISR_RXBF_Msk;
|
}
|
|
FlagStatus LPUARTx_ISR_RXBF_Chk(LPUART_Type* LPUARTx)
|
{
|
if (LPUARTx ->ISR & LPUARTx_ISR_RXBF_Msk)
|
{
|
return SET;
|
}
|
else
|
{
|
return RESET;
|
}
|
}
|
|
/* ·¢ËÍ»º´æ¿ÕÖжϱêÖ¾£¬Ó²¼þÖÃλ£¬Ð´ÈëTXBUFʱÇåÁã (Transmit Buffer Empty) Ïà¹Øº¯Êý */
|
FlagStatus LPUARTx_ISR_TXBE_Chk(LPUART_Type* LPUARTx)
|
{
|
if (LPUARTx ->ISR & LPUARTx_ISR_TXBE_Msk)
|
{
|
return SET;
|
}
|
else
|
{
|
return RESET;
|
}
|
}
|
|
/* ·¢ËÍ»º´æ¿ÕÇÒ·¢ËÍÒÆλ¼Ä´æÆ÷¿ÕÖжϱêÖ¾£¬Ó²¼þÖÃ룬Èí¼þд1»òÕß·¢ËÍÊý¾Ý±»ÔØÈëÒÆλ¼Ä´æÆ÷ʱÇåÁã (Transmit Shift register Empty) Ïà¹Øº¯Êý */
|
void LPUARTx_ISR_TXSE_Clr(LPUART_Type* LPUARTx)
|
{
|
LPUARTx ->ISR = LPUARTx_ISR_TXSE_Msk;
|
}
|
|
FlagStatus LPUARTx_ISR_TXSE_Chk(LPUART_Type* LPUARTx)
|
{
|
if (LPUARTx ->ISR & LPUARTx_ISR_TXSE_Msk)
|
{
|
return SET;
|
}
|
else
|
{
|
return RESET;
|
}
|
}
|
|
/* LPUARTÿ¸öbitµÄλ¿íµ÷ÖÆ¿ØÖÆÐźţ¬²Î¼û´íÎó!δÕÒµ½ÒýÓÃÔ´¡£´íÎó!δÕÒµ½ÒýÓÃÔ´¡£ (Bit Modulation Control) Ïà¹Øº¯Êý */
|
void LPUARTx_BMR_MCTL_Set(LPUART_Type* LPUARTx,uint32_t SetValue)
|
{
|
uint32_t tmpreg;
|
tmpreg = LPUARTx ->BMR;
|
tmpreg &= ~(LPUARTx_BMR_MCTL_Msk);
|
tmpreg |= (SetValue & LPUARTx_BMR_MCTL_Msk);
|
LPUARTx ->BMR = tmpreg;
|
}
|
|
uint32_t LPUARTx_BMR_MCTL_Get(LPUART_Type* LPUARTx)
|
{
|
return (LPUARTx ->BMR & LPUARTx_BMR_MCTL_Msk);
|
}
|
|
/* ²¨ÌØÂÊ¿ØÖÆ£¨bps£©
|
000£º9600
|
001£º4800
|
010£º2400
|
011£º1200
|
100£º600
|
101/110/111£º300 Ïà¹Øº¯Êý */
|
void LPUARTx_BMR_BAUD_Set(LPUART_Type* LPUARTx,uint32_t SetValue)
|
{
|
uint32_t tmpreg;
|
tmpreg = LPUARTx ->BMR;
|
tmpreg &= ~(LPUARTx_BMR_BAUD_Msk);
|
tmpreg |= (SetValue & LPUARTx_BMR_BAUD_Msk);
|
LPUARTx ->BMR = tmpreg;
|
}
|
|
uint32_t LPUARTx_BMR_BAUD_Get(LPUART_Type* LPUARTx)
|
{
|
return (LPUARTx ->BMR & LPUARTx_BMR_BAUD_Msk);
|
}
|
|
/* ½ÓÊÕÊý¾Ý»º´æ¼Ä´æÆ÷ (Receive Buffer) Ïà¹Øº¯Êý */
|
uint32_t LPUARTx_RXBUF_Read(LPUART_Type* LPUARTx)
|
{
|
return (LPUARTx ->RXBUF & LPUARTx_RXBUF_RXBUF_Msk);
|
}
|
|
/* ·¢ËÍÊý¾Ý»º´æ¼Ä´æÆ÷ (Transmit Buffer) Ïà¹Øº¯Êý */
|
void LPUARTx_TXBUF_Write(LPUART_Type* LPUARTx,uint32_t SetValue)
|
{
|
LPUARTx ->TXBUF = (SetValue & LPUARTx_TXBUF_TXBUF_Msk);
|
}
|
|
/* µÚÒ»Ö¡½ÓÊձȽÏÊý¾Ý£¬Èç¹ûRXEV=10£¬µ±½ÓÊÕµ½µÄµÚÒ»Ö¡Êý¾ÝÓëMATDÏàͬʱ£¬´¥·¢RXEVFÖжϣ¬¿ÉÒÔÓÃÓÚÐÝÃßģʽϵÄÊý¾Ý½ÓÊÕ»½ÐÑ¡£
|
(Matched Data) Ïà¹Øº¯Êý */
|
void LPUARTx_DMR_Write(LPUART_Type* LPUARTx,uint32_t SetValue)
|
{
|
LPUARTx ->DMR = (SetValue & LPUARTx_DMR_MATD_Msk);
|
}
|
|
uint32_t LPUARTx_DMR_Read(LPUART_Type* LPUARTx)
|
{
|
return (LPUARTx ->DMR & LPUARTx_DMR_MATD_Msk);
|
}
|
|
|
void LPUARTx_Deinit(LPUART_Type* LPUARTx)
|
{
|
//LPUARTx ->CSR = 0x00000000;
|
//LPUARTx ->IER = 0x00000000;
|
//LPUARTx ->ISR = 0x00000002;
|
//LPUARTx ->BMR = 0x00000000;
|
//LPUARTx ->RXBUF = ;
|
//LPUARTx ->TXBUF = ;
|
//LPUARTx ->DMR = ;
|
}
|
|
/******END OF FILE****/
|
