/**
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******************************************************************************
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* @file fm33a0xxev_cmu.h
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* @author FM33A0XXEV Application Team
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* @version V1.0.0
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* @date 16-April-2020
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* @brief This file contains all the functions prototypes for the CMU firmware library.
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __FM33A0XXEV_CMU_H
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#define __FM33A0XXEV_CMU_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "FM33A0XXEV.h"
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/* Defines------------------------------------------------------------------*/
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#define HXVAR(object, addr) (*((object *) (addr)))
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#define const_rchf_Trim8 HXVAR( uint32_t, 0x1FFFFB40 ) //RCHF 8MHzµ÷Уֵ
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#define const_rchf_Trim16 HXVAR( uint32_t, 0x1FFFFB3C ) //RCHF 16MHzµ÷Уֵ
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#define const_rchf_Trim24 HXVAR( uint32_t, 0x1FFFFB38 ) //RCHF 24MHzµ÷Уֵ
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#define const_rchf_Trim32 HXVAR( uint32_t, 0x1FFFFB34) //RCHF 32MHzµ÷Уֵ
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#define __XTHF_CLOCK (12000000) //ĬÈÏΪ8M£¬Ð޸ijÉʵ¼ÊµÄ12M
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/* Exported constants --------------------------------------------------------*/
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/* Exported types ------------------------------------------------------------*/
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typedef struct
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{
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uint32_t FSEL; /*!<RCHFƵÂÊ */
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FunState RCHFEN; /*!<RCHFʹÄÜ¿ØÖÆ */
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}CMU_RCHF_InitTypeDef;
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typedef struct
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{
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uint32_t PLLLDB; /*!<PLL±¶Æµ±È×î´ó1023,pll±¶ÆµÊý = PLLDB + 1 */
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FunState PLLL_EN; /*!<PLLʹÄÜ¿ØÖÆ */
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}CMU_PLL_L_InitTypeDef;
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typedef struct
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{
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uint32_t PLLHDB; /*!<PLL±¶Æµ±È×î´ó1023,pll±¶ÆµÊý = PLLDB + 1 */
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uint32_t REFPRSC; /*!<PLLH²Î¿¼Ê±ÖÓÔ¤·ÖƵ */
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uint32_t PLLH_OSEL; /*!<PLLÊä³öÑ¡Ôñ£¬µ±ÐèÒªÊä³ö³¬¹ý1024±¶Ê±¿ªÆôÁ½±¶Êä³öģʽ */
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uint32_t PLLH_INSEL; /*!<PLLÊäÈëÔ´Ñ¡Ôñ */
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FunState PLLH_EN; /*!<PLLʹÄÜ¿ØÖÆ */
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}CMU_PLL_H_InitTypeDef;
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typedef struct
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{
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uint32_t SYSCLKSEL; /*!<ϵͳʱÖÓÑ¡Ôñ£¬´ÓÐÝÃß״̬»½ÐѺó»á×Ô¶¯»Ö¸´ÎªRCHF8M */
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uint32_t AHBPRES; /*!<AHBʱÖÓ·ÖƵѡÔñ */
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uint32_t APBPRES; /*!<APBʱÖÓ·ÖƵѡÔñ */
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FunState SLP_ENEXTI; /*!<Sleep/DeepSleepģʽÏÂEXTI²ÉÑùÉèÖà */
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}CMU_SYSCLK_InitTypeDef;
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typedef struct
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{
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uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency expressed in Hz */
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uint32_t AHBCLK_Frequency; /*!< AHB clock frequency expressed in Hz */
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uint32_t APBCLK_Frequency; /*!< APB clock frequency expressed in Hz */
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uint32_t RCHF_Frequency; /*!< RCHF clock frequency expressed in Hz */
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uint32_t PLL_H_Frequency; /*!< PLL H clock frequency expressed in Hz */
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uint32_t XTHF_Frequency; /*!< XTHF clock frequency expressed in Hz */
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uint32_t LSCLK_Frequency; /*!< LSCLK clock frequency expressed in Hz */
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}CMU_ClocksType;
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#define CMU_SYSCLKCR_SLP_ENEXTI_Pos 25
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#define CMU_SYSCLKCR_SLP_ENEXTI_Msk (0x1U << CMU_SYSCLKCR_SLP_ENEXTI_Pos)
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#define CMU_SYSCLKCR_APBPRES_Pos 16 /* APBʱÖÓ·ÖƵѡÔñ (APB1bus clock Prescaler)
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000/001/010/011£º²»·ÖƵ
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100£º2·ÖƵ
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101£º4·ÖƵ
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110£º8·ÖƵ
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111£º16·ÖƵ */
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#define CMU_SYSCLKCR_APBPRES_Msk (0x7U << CMU_SYSCLKCR_APBPRES_Pos)
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#define CMU_SYSCLKCR_APBPRES_DIV1 (0x0U << CMU_SYSCLKCR_APBPRES_Pos) /* ²»·ÖƵ */
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#define CMU_SYSCLKCR_APBPRES_DIV2 (0x4U << CMU_SYSCLKCR_APBPRES_Pos) /* 2·ÖƵ */
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#define CMU_SYSCLKCR_APBPRES_DIV4 (0x5U << CMU_SYSCLKCR_APBPRES_Pos) /* 4·ÖƵ */
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#define CMU_SYSCLKCR_APBPRES_DIV8 (0x6U << CMU_SYSCLKCR_APBPRES_Pos) /* 8·ÖƵ */
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#define CMU_SYSCLKCR_APBPRES_DIV16 (0x7U << CMU_SYSCLKCR_APBPRES_Pos) /* 16·ÖƵ */
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#define CMU_SYSCLKCR_AHBPRES_Pos 8 /* AHBʱÖÓ·ÖƵѡÔñ (AHB bus clock Prescaler)
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000/001/010/011£º²»·ÖƵ
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100£º2·ÖƵ
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101£º4·ÖƵ
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110£º8·ÖƵ
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111£º16·ÖƵ */
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#define CMU_SYSCLKCR_AHBPRES_Msk (0x7U << CMU_SYSCLKCR_AHBPRES_Pos)
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#define CMU_SYSCLKCR_AHBPRES_DIV1 (0x0U << CMU_SYSCLKCR_AHBPRES_Pos) /* ²»·ÖƵ */
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#define CMU_SYSCLKCR_AHBPRES_DIV2 (0x4U << CMU_SYSCLKCR_AHBPRES_Pos) /* 2·ÖƵ */
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#define CMU_SYSCLKCR_AHBPRES_DIV4 (0x5U << CMU_SYSCLKCR_AHBPRES_Pos) /* 4·ÖƵ */
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#define CMU_SYSCLKCR_AHBPRES_DIV8 (0x6U << CMU_SYSCLKCR_AHBPRES_Pos) /* 8·ÖƵ */
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#define CMU_SYSCLKCR_AHBPRES_DIV16 (0x7U << CMU_SYSCLKCR_AHBPRES_Pos) /* 16·ÖƵ */
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#define CMU_SYSCLKCR_STCLKSEL_Pos 6 /* CPUÄÚºËsystick¹¤×÷ʱÖÓÑ¡Ôñ (Systick clock select)
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00£ºSCLK
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01£ºLSCLK
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10£ºRC4M
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11£ºSYSCLK */
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#define CMU_SYSCLKCR_STCLKSEL_Msk (0x3U << CMU_SYSCLKCR_STCLKSEL_Pos)
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#define CMU_SYSCLKCR_STCLKSEL_SCLK (0x0U << CMU_SYSCLKCR_STCLKSEL_Pos) /* SCLK */
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#define CMU_SYSCLKCR_STCLKSEL_LSCLK (0x1U << CMU_SYSCLKCR_STCLKSEL_Pos) /* LSCLK */
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#define CMU_SYSCLKCR_STCLKSEL_RC4M (0x2U << CMU_SYSCLKCR_STCLKSEL_Pos) /* RC4M */
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#define CMU_SYSCLKCR_STCLKSEL_SYSCLK (0x3U << CMU_SYSCLKCR_STCLKSEL_Pos) /* SYSCLK */
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#define CMU_SYSCLKCR_SYSCLKSEL_Pos 0 /* ϵͳʱÖÓÔ´Ñ¡Ôñ */
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#define CMU_SYSCLKCR_SYSCLKSEL_Msk (0x7U << CMU_SYSCLKCR_SYSCLKSEL_Pos)
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#define CMU_SYSCLKCR_SYSCLKSEL_RCHF (0x0U << CMU_SYSCLKCR_SYSCLKSEL_Pos) /* RCHF */
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#define CMU_SYSCLKCR_SYSCLKSEL_XTHF (0x1U << CMU_SYSCLKCR_SYSCLKSEL_Pos) /* XTHF */
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#define CMU_SYSCLKCR_SYSCLKSEL_PLL_H (0x2U << CMU_SYSCLKCR_SYSCLKSEL_Pos) /* PLL_H */
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#define CMU_SYSCLKCR_SYSCLKSEL_LSCLK (0x3U << CMU_SYSCLKCR_SYSCLKSEL_Pos) /* LSCLK */
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#define CMU_RCHFCR_FSEL_Pos 16 /* RCHFƵÂÊÑ¡Ôñ¼Ä´æÆ÷0000£º8MHz
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0001£º16MHz
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0010£º24MHz
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0011£º32MHz
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0111£º40MHz
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1111£º48MHz
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ÆäËû£ºRFU */
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#define CMU_RCHFCR_FSEL_Msk (0xfU << CMU_RCHFCR_FSEL_Pos)
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#define CMU_RCHFCR_FSEL_8MHZ (0x0U << CMU_RCHFCR_FSEL_Pos) /* 8MHz */
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#define CMU_RCHFCR_FSEL_16MHZ (0x1U << CMU_RCHFCR_FSEL_Pos) /* 16MHz */
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#define CMU_RCHFCR_FSEL_24MHZ (0x2U << CMU_RCHFCR_FSEL_Pos) /* 24MHz */
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#define CMU_RCHFCR_FSEL_32MHZ (0x3U << CMU_RCHFCR_FSEL_Pos) /* 32MHZ */
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#define CMU_RCHFCR_RCHFEN_Pos 0 /* RCHFʹÄܼĴæÆ÷ (RCHF Enable)
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1£ºÊ¹ÄÜRCHF
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0£º¹Ø±ÕRCHF */
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#define CMU_RCHFCR_RCHFEN_Msk (0x1U << CMU_RCHFCR_RCHFEN_Pos)
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/* ʹÄÜRCHF */
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/* ¹Ø±ÕRCHF */
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#define CMU_RCHFTR_RCHFTRIM_Pos 0 /* RCHFƵÂʵ÷У¼Ä´æÆ÷£¬8¡¯h00±íʾƵÂÊ×îµÍ£¬8¡¯hFF±íʾƵÂÊ×î¸ß£¬µ÷У·¶Î§ÎªÖÐÐÄƵÂÊ+/-30%£¬µ÷У²½³¤ÎªÖÐÐÄƵÂÊ0.25%
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ÉϵçºóоƬ×Ô¶¯´ÓLDT0¶ÁÈ¡8MHzµ÷Уֵ²¢Ð´Èë´Ë¼Ä´æÆ÷
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Èí¼þʹÓÃÆäËûƵÂÊʱ£¬¿ÉÒÔ×ÔÐдÓLDT0Ö¸¶¨µØÖ·¶ÁÈ¡µ÷УÐÅÏ¢²¢Ð´Èë´Ë¼Ä´æÆ÷£¬´Ó¶øÈ·±£Êä³öƵÂÊ׼ȷ¡£ */
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#define CMU_RCHFTR_RCHFTRIM_Msk (0xffU << CMU_RCHFTR_RCHFTRIM_Pos)
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#define CMU_PLLLCR_PLLDB_Pos 16
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#define CMU_PLLLCR_PLLDB_Msk (0x3ffU << CMU_PLLLCR_PLLDB_Pos)
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#define CMU_PLLLCR_LOCKED_Pos 7
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#define CMU_PLLLCR_LOCKED_Msk (0x1U << CMU_PLLLCR_LOCKED_Pos)
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#define CMU_PLLLCR_PLLEN_Pos 0 /* PLLʹÄܼĴæÆ÷
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1£ºÊ¹ÄÜPLL
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0£º¹Ø±ÕPLL */
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#define CMU_PLLLCR_PLLEN_Msk (0x1U << CMU_PLLLCR_PLLEN_Pos)
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#define CMU_PLLHCR_PLLHDB_Pos 16 /* PLLH±¶Æµ±È£¬²Î¿¼Ê±ÖÓ1Mhz
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0000011111£ºÊä³ö32±¶Æµ
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0101111£ºÊä³ö48±¶Æµ */
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#define CMU_PLLHCR_PLLHDB_Msk (0x3ffU << CMU_PLLHCR_PLLHDB_Pos)
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#define CMU_PLLHCR_PLLHDB_X32 (0x1fU << CMU_PLLHCR_PLLHDB_Pos) /* Êä³ö32±¶Æµ */
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#define CMU_PLLHCR_PLLHDB_X48 (0x2fU << CMU_PLLHCR_PLLHDB_Pos) /* Êä³ö48±¶Æµ */
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#define CMU_PLLHCR_PLLHDB_X64 (0x3fU << CMU_PLLHCR_PLLHDB_Pos) /* Êä³ö64±¶Æµ */
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#define CMU_PLLHCR_LOCKED_Pos 7 /* PLLHËø¶¨±êÖ¾£¬Èí¼þͨ¹ý²éѯ´Ë¼Ä´æÆ÷È·ÈÏPLLÒѾ´¦ÓÚËø¶¨×´Ì¬
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1£ºPLLÒÑËø¶¨
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0£ºPLLδËø¶¨ */
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#define CMU_PLLHCR_LOCKED_Msk (0x1U << CMU_PLLHCR_LOCKED_Pos)
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#define CMU_PLLHCR_REFPRSC_Pos 4 /* PLLH²Î¿¼Ê±ÖÓÔ¤·ÖƵ£¨Ä¿±êÊDzúÉú1MHz²Î¿¼Ê±ÖÓ¸øPLL£©
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000£º²»·ÖƵ
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001£º2·ÖƵ
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010£º4·ÖƵ
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011£º8·ÖƵ
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100£º12·ÖƵ
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101£º16·ÖƵ
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110£º24·ÖƵ
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111£º32·ÖƵ */
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#define CMU_PLLHCR_REFPRSC_Msk (0x7U << CMU_PLLHCR_REFPRSC_Pos)
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#define CMU_PLLHCR_REFPRSC_DIV1 (0x0U << CMU_PLLHCR_REFPRSC_Pos) /* ²»·ÖƵ */
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#define CMU_PLLHCR_REFPRSC_DIV2 (0x1U << CMU_PLLHCR_REFPRSC_Pos) /* 2·ÖƵ */
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#define CMU_PLLHCR_REFPRSC_DIV4 (0x2U << CMU_PLLHCR_REFPRSC_Pos) /* 4·ÖƵ */
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#define CMU_PLLHCR_REFPRSC_DIV8 (0x3U << CMU_PLLHCR_REFPRSC_Pos) /* 8·ÖƵ */
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#define CMU_PLLHCR_REFPRSC_DIV12 (0x4U << CMU_PLLHCR_REFPRSC_Pos) /* 12·ÖƵ */
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#define CMU_PLLHCR_REFPRSC_DIV16 (0x5U << CMU_PLLHCR_REFPRSC_Pos) /* 16·ÖƵ */
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#define CMU_PLLHCR_REFPRSC_DIV24 (0x6U << CMU_PLLHCR_REFPRSC_Pos) /* 24·ÖƵ */
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#define CMU_PLLHCR_REFPRSC_DIV32 (0x7U << CMU_PLLHCR_REFPRSC_Pos) /* 32·ÖƵ */
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#define CMU_PLLHCR_OSEL_Pos 3 /* PLLHÊä³öÑ¡Ôñ¼Ä´æÆ÷
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0£ºÑ¡ÔñPLLHÒ»±¶Êä³ö×÷ΪÊý×Öµç·ÄÚµÄPLLʱÖÓ
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1£ºÑ¡ÔñPLLHÁ½±¶Êä³ö×÷ΪÊý×Öµç·ÄÚµÄPLLʱÖÓ */
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#define CMU_PLLHCR_OSEL_Msk (0x1U << CMU_PLLHCR_OSEL_Pos)
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#define CMU_PLLHCR_OSEL_X1 (0x0U << CMU_PLLHCR_OSEL_Pos)
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#define CMU_PLLHCR_OSEL_X2 (0x1U << CMU_PLLHCR_OSEL_Pos)
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#define CMU_PLLHCR_INSEL_Pos 1 /* PLLHÊäÈëÑ¡Ôñ¼Ä´æÆ÷
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0£ºRCHF
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1£ºXTHF */
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#define CMU_PLLHCR_INSEL_Msk (0x1U << CMU_PLLHCR_INSEL_Pos)
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#define CMU_PLLHCR_INSEL_RCHF (0x0U << CMU_PLLHCR_INSEL_Pos)
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#define CMU_PLLHCR_INSEL_XTHF (0x1U << CMU_PLLHCR_INSEL_Pos)
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#define CMU_PLLHCR_EN_Pos 0 /* PLLHʹÄܼĴæÆ÷
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1£ºÊ¹ÄÜPLLH
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0£º¹Ø±ÕPLLH */
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#define CMU_PLLHCR_EN_Msk (0x1U << CMU_PLLHCR_EN_Pos)
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#define CMU_XTHFCR_XTHF_CFG_Pos 8 /* XTHFÕñµ´Ç¿¶ÈÅäÖÃ
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000£º×îÈõ
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111£º×îÇ¿ */
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#define CMU_XTHFCR_XTHF_CFG_Msk (0x7U << CMU_XTHFCR_XTHF_CFG_Pos)
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#define CMU_XTHFCR_XTHF_CFG_MIN (0x0U << CMU_XTHFCR_XTHF_CFG_Pos) /* ×îÈõ */
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#define CMU_XTHFCR_XTHF_CFG_MAX (0x7U << CMU_XTHFCR_XTHF_CFG_Pos) /* ×îÇ¿ */
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#define CMU_XTHFCR_XTHFEN_Pos 0 /* XTHFʹÄܼĴæÆ÷
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0£º¹Ø±ÕXTHF
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1£ºÊ¹ÄÜXTHF */
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#define CMU_XTHFCR_XTHFEN_Msk (0x1U << CMU_XTHFCR_XTHFEN_Pos)
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/* ¹Ø±ÕXTHF */
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/* ʹÄÜXTHF */
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#define CMU_IER_SYSCSE_IE_Pos 1
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#define CMU_IER_SYSCSE_IE_Msk (0x1U << CMU_IER_SYSCSE_IE_Pos)
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#define CMU_IER_HFDET_IE_Pos 0
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#define CMU_IER_HFDET_IE_Msk (0x1U << CMU_IER_HFDET_IE_Pos)
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#define CMU_ISR_HFDETO_Pos 8 /* ¸ßƵ¾§ÌåÍ£Õñ¼ì²âÄ£¿éÊä³ö
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1£ºXTHFδͣÕñ
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0£ºXTHFÍ£Õñ */
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#define CMU_ISR_HFDETO_Msk (0x1U << CMU_ISR_HFDETO_Pos)
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#define CMU_ISR_SYSCSE_IF_Pos 1/* SYSCLKʱÖÓÑ¡Ôñ´íÎóÖжϱêÖ¾¼Ä´æÆ÷£»µ±±»Ñ¡ÖеÄʱÖÓԴûÓÐʹÄÜʱ£¬´ËÖжϱêÖ¾ÖÃ룬Èí¼þд1ÇåÁã¡£ */
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#define CMU_ISR_SYSCSE_IF_Msk (0x1U << CMU_ISR_SYSCSE_IF_Pos)
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#define CMU_ISR_HFDET_IF_Pos 0 /* ¸ßƵͣÕñ¼ì²âÖжϱêÖ¾¼Ä´æÆ÷£¬XTHFÍ£ÕñʱӲ¼þÒì²½ÖÃ룬Èí¼þд1ÇåÁ㣻ֻÓÐÔÚFFDETO²»Îª0µÄÇé¿öϲÅÄܹ»Çå³ý´Ë¼Ä´æÆ÷ */
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#define CMU_ISR_HFDET_IF_Msk (0x1U << CMU_ISR_HFDET_IF_Pos)
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#define CMU_PCLKCR1_COMP_PCE_Pos 9 /* COMP×ÜÏßʱÖÓʹÄÜ£¬¸ßʹÄÜ */
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#define CMU_PCLKCR1_COMP_PCE_Msk (0x1U << CMU_PCLKCR1_COMP_PCE_Pos)
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#define CMU_PCLKCR1_SVD_PCE_Pos 8 /* SVD×ÜÏßʱÖÓʹÄÜ£¬¸ßʹÄÜ */
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#define CMU_PCLKCR1_SVD_PCE_Msk (0x1U << CMU_PCLKCR1_SVD_PCE_Pos)
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#define CMU_PCLKCR1_PAD_PCE_Pos 7 /* PADCFG×ÜÏßʱÖÓʹÄÜ£¬¸ßʹÄÜ */
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#define CMU_PCLKCR1_PAD_PCE_Msk (0x1U << CMU_PCLKCR1_PAD_PCE_Pos)
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#define CMU_PCLKCR1_ANAC_PCE_Pos 6 /* ANAC×ÜÏßʱÖÓʹÄÜ£¬¸ßʹÄÜ
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´Ë¼Ä´æÆ÷ÓÃÓÚ¿ØÖÆSVD¡¢±È½ÏÆ÷µÄ×ÜÏßʱÖÓ */
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#define CMU_PCLKCR1_ANAC_PCE_Msk (0x1U << CMU_PCLKCR1_ANAC_PCE_Pos)
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#define CMU_PCLKCR1_IWDT_PCE_Pos 5 /* IWDT×ÜÏßʱÖÓʹÄÜ£¬¸ßʹÄÜ */
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#define CMU_PCLKCR1_IWDT_PCE_Msk (0x1U << CMU_PCLKCR1_IWDT_PCE_Pos)
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#define CMU_PCLKCR1_SCU_PCE_Pos 4 /* SCU×ÜÏßʱÖÓʹÄÜ£¬¸ßʹÄÜ */
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#define CMU_PCLKCR1_SCU_PCE_Msk (0x1U << CMU_PCLKCR1_SCU_PCE_Pos)
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#define CMU_PCLKCR1_PMU_PCE_Pos 3 /* PMU×ÜÏßʱÖÓʹÄÜ£¬¸ßʹÄÜ */
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#define CMU_PCLKCR1_PMU_PCE_Msk (0x1U << CMU_PCLKCR1_PMU_PCE_Pos)
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#define CMU_PCLKCR1_RTC_PCE_Pos 2 /* RTC×ÜÏßʱÖÓʹÄÜ£¬¸ßʹÄÜ */
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#define CMU_PCLKCR1_RTC_PCE_Msk (0x1U << CMU_PCLKCR1_RTC_PCE_Pos)
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#define CMU_PCLKCR1_LPT_PCE_Pos 0 /* _32×ÜÏßʱÖÓʹÄÜ£¬¸ßʹÄÜ */
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#define CMU_PCLKCR1_LPT_PCE_Msk (0x1U << CMU_PCLKCR1_LPT_PCE_Pos)
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#define CMU_PCLKCR2_PAE_PCE_Pos 17
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#define CMU_PCLKCR2_PAE_PCE_Msk (0x1U << CMU_PCLKCR2_PAE_PCE_Pos)
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#define CMU_PCLKCR2_SHA_PCE_Pos 16
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#define CMU_PCLKCR2_SHA_PCE_Msk (0x1U << CMU_PCLKCR2_SHA_PCE_Pos)
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#define CMU_PCLKCR2_CIC_PCE_Pos 8 /* ADC×ÜÏßʱÖÓʹÄÜ£¬¸ßʹÄÜ */
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#define CMU_PCLKCR2_CIC_PCE_Msk (0x1U << CMU_PCLKCR2_CIC_PCE_Pos)
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#define CMU_PCLKCR2_WWDT_PCE_Pos 7 /* WWDT×ÜÏßʱÖÓʹÄÜ£¬¸ßʹÄÜ */
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#define CMU_PCLKCR2_WWDT_PCE_Msk (0x1U << CMU_PCLKCR2_WWDT_PCE_Pos)
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#define CMU_PCLKCR2_RAMBIST_PCE_Pos 6 /* RAMBIST×ÜÏßʱÖÓʹÄÜ£¬¸ßʹÄÜ */
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#define CMU_PCLKCR2_RAMBIST_PCE_Msk (0x1U << CMU_PCLKCR2_RAMBIST_PCE_Pos)
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#define CMU_PCLKCR2_NVM_PCE_Pos 5 /* NVMIF£¨Flash²Áд¿ØÖÆÆ÷£©×ÜÏßʱÖÓʹÄÜ£¬¸ßʹÄÜ */
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#define CMU_PCLKCR2_NVM_PCE_Msk (0x1U << CMU_PCLKCR2_NVM_PCE_Pos)
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#define CMU_PCLKCR2_DMA_PCE_Pos 4 /* DMA×ÜÏßʱÖÓʹÄÜ£¬¸ßʹÄÜ */
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#define CMU_PCLKCR2_DMA_PCE_Msk (0x1U << CMU_PCLKCR2_DMA_PCE_Pos)
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#define CMU_PCLKCR2_LCD_PCE_Pos 3 /* LCD×ÜÏßʱÖÓʹÄÜ£¬¸ßʹÄÜ */
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#define CMU_PCLKCR2_LCD_PCE_Msk (0x1U << CMU_PCLKCR2_LCD_PCE_Pos)
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#define CMU_PCLKCR2_AES_PCE_Pos 2 /* AES×ÜÏßʱÖÓʹÄÜ£¬¸ßʹÄÜ */
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#define CMU_PCLKCR2_AES_PCE_Msk (0x1U << CMU_PCLKCR2_AES_PCE_Pos)
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#define CMU_PCLKCR2_TRNG_PCE_Pos 1 /* RNG×ÜÏßʱÖÓʹÄÜ£¬¸ßʹÄÜ */
|
#define CMU_PCLKCR2_TRNG_PCE_Msk (0x1U << CMU_PCLKCR2_TRNG_PCE_Pos)
|
|
#define CMU_PCLKCR2_CRC_PCE_Pos 0 /* CRC×ÜÏßʱÖÓʹÄÜ£¬¸ßʹÄÜ */
|
#define CMU_PCLKCR2_CRC_PCE_Msk (0x1U << CMU_PCLKCR2_CRC_PCE_Pos)
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|
#define CMU_PCLKCR3_I2C1_PCE_Pos 25 /* I2C1×ÜÏßʱÖÓʹÄÜ£¬¸ßÓÐЧ */
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#define CMU_PCLKCR3_I2C1_PCE_Msk (0x1U << CMU_PCLKCR3_I2C1_PCE_Pos)
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|
#define CMU_PCLKCR3_I2C0_PCE_Pos 24 /* I2C0×ÜÏßʱÖÓʹÄÜ£¬¸ßÓÐЧ */
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#define CMU_PCLKCR3_I2C0_PCE_Msk (0x1U << CMU_PCLKCR3_I2C0_PCE_Pos)
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|
#define CMU_PCLKCR3_LPUART1_PCE_Pos 18 /* LPUART1×ÜÏßʱÖÓʹÄÜ£¬¸ßÓÐЧ */
|
#define CMU_PCLKCR3_LPUART1_PCE_Msk (0x1U << CMU_PCLKCR3_LPUART1_PCE_Pos)
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|
#define CMU_PCLKCR3_U7816_PCE_Pos 16 /* 7816×ÜÏßʱÖÓʹÄÜ£¬¸ßÓÐЧ */
|
#define CMU_PCLKCR3_U7816_PCE_Msk (0x1U << CMU_PCLKCR3_U7816_PCE_Pos)
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|
#define CMU_PCLKCR3_LPUART0_PCE_Pos 15 /* LPUART0×ÜÏßʱÖÓʹÄÜ£¬¸ßÓÐЧ */
|
#define CMU_PCLKCR3_LPUART0_PCE_Msk (0x1U << CMU_PCLKCR3_LPUART0_PCE_Pos)
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|
#define CMU_PCLKCR3_UICR_PCE_Pos 14 /* UARTºìÍâµ÷ÖÆ×ÜÏßʹÄÜ£¬¸ßÓÐЧ */
|
#define CMU_PCLKCR3_UICR_PCE_Msk (0x1U << CMU_PCLKCR3_UICR_PCE_Pos)
|
|
#define CMU_PCLKCR3_UART5_PCE_Pos 13 /* UART5×ÜÏßʱÖÓʹÄÜ£¬¸ßÓÐЧ */
|
#define CMU_PCLKCR3_UART5_PCE_Msk (0x1U << CMU_PCLKCR3_UART5_PCE_Pos)
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|
#define CMU_PCLKCR3_UART4_PCE_Pos 12 /* UART4×ÜÏßʱÖÓʹÄÜ£¬¸ßÓÐЧ */
|
#define CMU_PCLKCR3_UART4_PCE_Msk (0x1U << CMU_PCLKCR3_UART4_PCE_Pos)
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|
#define CMU_PCLKCR3_UART3_PCE_Pos 11 /* UART3×ÜÏßʱÖÓʹÄÜ£¬¸ßÓÐЧ */
|
#define CMU_PCLKCR3_UART3_PCE_Msk (0x1U << CMU_PCLKCR3_UART3_PCE_Pos)
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|
#define CMU_PCLKCR3_UART2_PCE_Pos 10 /* UART2×ÜÏßʱÖÓʹÄÜ£¬¸ßÓÐЧ */
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#define CMU_PCLKCR3_UART2_PCE_Msk (0x1U << CMU_PCLKCR3_UART2_PCE_Pos)
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#define CMU_PCLKCR3_UART1_PCE_Pos 9 /* UART1×ÜÏßʱÖÓʹÄÜ£¬¸ßÓÐЧ */
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#define CMU_PCLKCR3_UART1_PCE_Msk (0x1U << CMU_PCLKCR3_UART1_PCE_Pos)
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#define CMU_PCLKCR3_UART0_PCE_Pos 8 /* UART0×ÜÏßʱÖÓʹÄÜ£¬¸ßÓÐЧ */
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#define CMU_PCLKCR3_UART0_PCE_Msk (0x1U << CMU_PCLKCR3_UART0_PCE_Pos)
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#define CMU_PCLKCR3_QSPI_PCE_Pos 7 /* QuadSPI×ÜÏßʱÖÓʹÄÜ£¬¸ßÓÐЧ */
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#define CMU_PCLKCR3_QSPI_PCE_Msk (0x1U << CMU_PCLKCR3_QSPI_PCE_Pos)
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#define CMU_PCLKCR3_SPI4_PCE_Pos 4 /* SPI4×ÜÏßʱÖÓʹÄÜ£¬¸ßÓÐЧ */
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#define CMU_PCLKCR3_SPI4_PCE_Msk (0x1U << CMU_PCLKCR3_SPI4_PCE_Pos)
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#define CMU_PCLKCR3_SPI3_PCE_Pos 3 /* SPI3×ÜÏßʱÖÓʹÄÜ£¬¸ßÓÐЧ */
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#define CMU_PCLKCR3_SPI3_PCE_Msk (0x1U << CMU_PCLKCR3_SPI3_PCE_Pos)
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#define CMU_PCLKCR3_SPI2_PCE_Pos 2 /* SPI2×ÜÏßʱÖÓʹÄÜ£¬¸ßÓÐЧ */
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#define CMU_PCLKCR3_SPI2_PCE_Msk (0x1U << CMU_PCLKCR3_SPI2_PCE_Pos)
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#define CMU_PCLKCR3_SPI1_PCE_Pos 1 /* SPI1×ÜÏßʱÖÓʹÄÜ£¬¸ßÓÐЧ */
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#define CMU_PCLKCR3_SPI1_PCE_Msk (0x1U << CMU_PCLKCR3_SPI1_PCE_Pos)
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#define CMU_PCLKCR3_SPI0_PCE_Pos 0 /* SPI0×ÜÏßʱÖÓʹÄÜ£¬¸ßÓÐЧ */
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#define CMU_PCLKCR3_SPI0_PCE_Msk (0x1U << CMU_PCLKCR3_SPI0_PCE_Pos)
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#define CMU_PCLKCR4_ET4_PCE_Pos 6 /* Etimer4ʱÖÓʹÄÜ£¬¸ßʹÄÜ */
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#define CMU_PCLKCR4_ET4_PCE_Msk (0x1U << CMU_PCLKCR4_ET4_PCE_Pos)
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#define CMU_PCLKCR4_ET3_PCE_Pos 5 /* Etimer3ʱÖÓʹÄÜ£¬¸ßʹÄÜ */
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#define CMU_PCLKCR4_ET3_PCE_Msk (0x1U << CMU_PCLKCR4_ET3_PCE_Pos)
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#define CMU_PCLKCR4_ET2_PCE_Pos 4 /* Etimer2ʱÖÓʹÄÜ£¬¸ßʹÄÜ */
|
#define CMU_PCLKCR4_ET2_PCE_Msk (0x1U << CMU_PCLKCR4_ET2_PCE_Pos)
|
|
#define CMU_PCLKCR4_ET1_PCE_Pos 3 /* Etimer1ʱÖÓʹÄÜ£¬¸ßʹÄÜ */
|
#define CMU_PCLKCR4_ET1_PCE_Msk (0x1U << CMU_PCLKCR4_ET1_PCE_Pos)
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#define CMU_PCLKCR4_BT2_PCE_Pos 2 /* BaseTimer2ʱÖÓʹÄÜ£¬¸ßʹÄÜ */
|
#define CMU_PCLKCR4_BT2_PCE_Msk (0x1U << CMU_PCLKCR4_BT2_PCE_Pos)
|
|
#define CMU_PCLKCR4_BT1_PCE_Pos 1 /* BaseTimer1ʱÖÓʹÄÜ£¬¸ßʹÄÜ */
|
#define CMU_PCLKCR4_BT1_PCE_Msk (0x1U << CMU_PCLKCR4_BT1_PCE_Pos)
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|
#define CMU_PCLKCR4_BSTIM_PCE_Pos 0 /* »ù±¾¶¨Ê±Æ÷BSTIM×ÜÏßʱÖÓʹÄÜ£¬¸ßʹÄÜ */
|
#define CMU_PCLKCR4_BSTIM_PCE_Msk (0x1U << CMU_PCLKCR4_BSTIM_PCE_Pos)
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|
#define CMU_OPCCR1_EXTICKE_Pos 31 /* EXTI¹¤×÷ʱÖÓʹÄÜ£¬¸ßÓÐЧ */
|
#define CMU_OPCCR1_EXTICKE_Msk (0x1U << CMU_OPCCR1_EXTICKE_Pos)
|
|
#define CMU_OPCCR1_EXTICKSEL_Pos 30 /* EXTIÖжϲÉÑùʱÖÓÑ¡Ôñ */
|
#define CMU_OPCCR1_EXTICKSEL_Msk (0x1U << CMU_OPCCR1_EXTICKSEL_Pos)
|
#define CMU_OPCCR1_EXTICKSEL_LSCLK (0x1U << CMU_OPCCR1_EXTICKSEL_Pos) /* 1£ºÍⲿÒý½ÅÖжÏʹÓÃLSCLK²ÉÑù */
|
#define CMU_OPCCR1_EXTICKSEL_HCLK (0x0U << CMU_OPCCR1_EXTICKSEL_Pos) /* 0£ºÍⲿÒý½ÅÖжÏʹÓÃHCLK²ÉÑù */
|
|
#define CMU_OPCCR1_LPUART1CKE_Pos 29 /* LPUART1¹¤×÷ʱÖÓʹÄÜ£¬¸ßÓÐЧ */
|
#define CMU_OPCCR1_LPUART1CKE_Msk (0x1U << CMU_OPCCR1_LPUART1CKE_Pos)
|
|
#define CMU_OPCCR1_LPUART0CKE_Pos 28 /* LPUART0¹¤×÷ʱÖÓʹÄÜ£¬¸ßÓÐЧ */
|
#define CMU_OPCCR1_LPUART0CKE_Msk (0x1U << CMU_OPCCR1_LPUART0CKE_Pos)
|
|
#define CMU_OPCCR1_LPUART1CKS_Pos 26 /* LPUART1¹¤×÷ʱÖÓÑ¡Ôñ
|
00£ºLSCLK
|
01£ºRCHF·ÖƵ£¨¸ù¾ÝRCHFµµÎ»×Ô¶¯·ÖƵµ½32768Hz¸½½ü£©
|
10£ºRFU
|
11£ºRFU */
|
#define CMU_OPCCR1_LPUART1CKS_Msk (0x3U << CMU_OPCCR1_LPUART1CKS_Pos)
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#define CMU_OPCCR1_LPUART1CKS_LSCLK (0x0U << CMU_OPCCR1_LPUART1CKS_Pos) /* LSCLK */
|
#define CMU_OPCCR1_LPUART1CKS_RCHF (0x1U << CMU_OPCCR1_LPUART1CKS_Pos) /* RCHF·ÖƵ£¨¸ù¾ÝRCHFµµÎ»×Ô¶¯·ÖƵµ½32768Hz¸½½ü£© */
|
|
#define CMU_OPCCR1_LPUART0CKS_Pos 24 /* LPUART0¹¤×÷ʱÖÓÑ¡Ôñ
|
00£ºLSCLK
|
01£ºRCHF·ÖƵ£¨¸ù¾ÝRCHFµµÎ»×Ô¶¯·ÖƵµ½32768Hz¸½½ü£©
|
10£ºRFU
|
11£ºRFU */
|
#define CMU_OPCCR1_LPUART0CKS_Msk (0x3U << CMU_OPCCR1_LPUART0CKS_Pos)
|
#define CMU_OPCCR1_LPUART0CKS_LSCLK (0x0U << CMU_OPCCR1_LPUART0CKS_Pos) /* LSCLK */
|
#define CMU_OPCCR1_LPUART0CKS_RCHF (0x1U << CMU_OPCCR1_LPUART0CKS_Pos) /* RCHF·ÖƵ£¨¸ù¾ÝRCHFµµÎ»×Ô¶¯·ÖƵµ½32768Hz¸½½ü£© */
|
|
#define CMU_OPCCR1_I2C1CKE_Pos 21 /* I2C1¹¤×÷ʱÖÓʹÄÜ */
|
#define CMU_OPCCR1_I2C1CKE_Msk (0x1U << CMU_OPCCR1_I2C1CKE_Pos)
|
|
#define CMU_OPCCR1_I2C0CKE_Pos 20 /* I2C0¹¤×÷ʱÖÓʹÄÜ */
|
#define CMU_OPCCR1_I2C0CKE_Msk (0x1U << CMU_OPCCR1_I2C0CKE_Pos)
|
|
#define CMU_OPCCR1_I2C1CKS_Pos 18 /* I2C1Ö÷»ú¹¤×÷ʱÖÓÑ¡Ôñ
|
00£ºAPBCLK
|
01£ºRCHF
|
10£ºSYSCLK
|
11£ºAPBCLK */
|
#define CMU_OPCCR1_I2C1CKS_Msk (0x3U << CMU_OPCCR1_I2C1CKS_Pos)
|
#define CMU_OPCCR1_I2C1CKS_APBCLK (0x0U << CMU_OPCCR1_I2C1CKS_Pos) /* APBCLK */
|
#define CMU_OPCCR1_I2C1CKS_RCHF (0x1U << CMU_OPCCR1_I2C1CKS_Pos) /* RCHF */
|
#define CMU_OPCCR1_I2C1CKS_SYSCLK (0x2U << CMU_OPCCR1_I2C1CKS_Pos) /* SYSCLK */
|
|
#define CMU_OPCCR1_I2C0CKS_Pos 16 /* I2C0Ö÷»ú¹¤×÷ʱÖÓÑ¡Ôñ
|
00£ºAPBCLK
|
01£ºRCHF
|
10£ºSYSCLK
|
11£ºAPBCLK */
|
#define CMU_OPCCR1_I2C0CKS_Msk (0x3U << CMU_OPCCR1_I2C0CKS_Pos)
|
#define CMU_OPCCR1_I2C0CKS_APBCLK (0x0U << CMU_OPCCR1_I2C0CKS_Pos) /* APBCLK */
|
#define CMU_OPCCR1_I2C0CKS_RCHF (0x1U << CMU_OPCCR1_I2C0CKS_Pos) /* RCHF */
|
#define CMU_OPCCR1_I2C0CKS_SYSCLK (0x2U << CMU_OPCCR1_I2C0CKS_Pos) /* SYSCLK */
|
|
#define CMU_OPCCR1_UART1CKE_Pos 9 /* UART1¹¤×÷ʱÖÓʹÄÜ£¬¸ßÓÐЧ */
|
#define CMU_OPCCR1_UART1CKE_Msk (0x1U << CMU_OPCCR1_UART1CKE_Pos)
|
|
#define CMU_OPCCR1_UART0CKE_Pos 8 /* UART0¹¤×÷ʱÖÓʹÄÜ£¬¸ßÓÐЧ */
|
#define CMU_OPCCR1_UART0CKE_Msk (0x1U << CMU_OPCCR1_UART0CKE_Pos)
|
|
#define CMU_OPCCR1_UART1CKS_Pos 2 /* UART1¹¤×÷ʱÖÓÑ¡Ôñ
|
00£ºAPBCLK
|
01£ºRCHF
|
10£ºSYSCLK
|
11£ºRFU */
|
#define CMU_OPCCR1_UART1CKS_Msk (0x3U << CMU_OPCCR1_UART1CKS_Pos)
|
#define CMU_OPCCR1_UART1CKS_APBCLK (0x0U << CMU_OPCCR1_UART1CKS_Pos) /* APBCLK */
|
#define CMU_OPCCR1_UART1CKS_RCHF (0x1U << CMU_OPCCR1_UART1CKS_Pos) /* RCHF */
|
#define CMU_OPCCR1_UART1CKS_SYSCLK (0x2U << CMU_OPCCR1_UART1CKS_Pos) /* SYSCLK */
|
|
#define CMU_OPCCR1_UART0CKS_Pos 0 /* UART0¹¤×÷ʱÖÓÑ¡Ôñ
|
00£ºAPBCLK
|
01£ºRCHF
|
10£ºSYSCLK
|
11£ºRFU */
|
#define CMU_OPCCR1_UART0CKS_Msk (0x3U << CMU_OPCCR1_UART0CKS_Pos)
|
#define CMU_OPCCR1_UART0CKS_APBCLK (0x0U << CMU_OPCCR1_UART0CKS_Pos) /* APBCLK */
|
#define CMU_OPCCR1_UART0CKS_RCHF (0x1U << CMU_OPCCR1_UART0CKS_Pos) /* RCHF */
|
#define CMU_OPCCR1_UART0CKS_SYSCLK (0x2U << CMU_OPCCR1_UART0CKS_Pos) /* SYSCLK */
|
|
#define CMU_OPCCR2_RNGPRSC_Pos 28 /* Ëæ»úÊý·¢ÉúÆ÷¹¤×÷ʱÖÓ·ÖƵ
|
000£º²»·ÖƵ
|
001£º2·ÖƵ
|
010£º4·ÖƵ
|
011£º8·ÖƵ
|
100£º16·ÖƵ
|
101£º32·ÖƵ
|
110, 111£ºRFU */
|
#define CMU_OPCCR2_RNGPRSC_Msk (0x7U << CMU_OPCCR2_RNGPRSC_Pos)
|
#define CMU_OPCCR2_RNGPRSC_DIV1 (0x0U << CMU_OPCCR2_RNGPRSC_Pos) /* ²»·ÖƵ */
|
#define CMU_OPCCR2_RNGPRSC_DIV2 (0x1U << CMU_OPCCR2_RNGPRSC_Pos) /* 2·ÖƵ */
|
#define CMU_OPCCR2_RNGPRSC_DIV4 (0x2U << CMU_OPCCR2_RNGPRSC_Pos) /* 4·ÖƵ */
|
#define CMU_OPCCR2_RNGPRSC_DIV8 (0x3U << CMU_OPCCR2_RNGPRSC_Pos) /* 8·ÖƵ */
|
#define CMU_OPCCR2_RNGPRSC_DIV16 (0x4U << CMU_OPCCR2_RNGPRSC_Pos) /* 16·ÖƵ */
|
#define CMU_OPCCR2_RNGPRSC_DIV32 (0x5U << CMU_OPCCR2_RNGPRSC_Pos) /* 32·ÖƵ */
|
|
#define CMU_OPCCR2_NVMCKE_Pos 22 /* Flash²ÁдʱÖÓʹÄÜ£¬¸ßÓÐЧ */
|
#define CMU_OPCCR2_NVMCKE_Msk (0x1U << CMU_OPCCR2_NVMCKE_Pos)
|
|
#define CMU_OPCCR2_RNGCKE_Pos 21 /* Ëæ»úÊý·¢ÉúÆ÷¹¤×÷ʱÖÓʹÄÜ£¬¸ßÓÐЧ */
|
#define CMU_OPCCR2_RNGCKE_Msk (0x1U << CMU_OPCCR2_RNGCKE_Pos)
|
|
#define CMU_OPCCR2_LPTCKE_Pos 12 /* _¹¤×÷ʱÖÓʹÄÜ£¬¸ßÓÐЧ */
|
#define CMU_OPCCR2_LPTCKE_Msk (0x1U << CMU_OPCCR2_LPTCKE_Pos)
|
|
#define CMU_OPCCR2_LPTCKS_Pos 8 /* _¹¤×÷ʱÖÓÑ¡Ôñ
|
00£ºAPBCLK
|
01£ºLSCLK
|
10£ºRCLP
|
11£ºPLL_L */
|
#define CMU_OPCCR2_LPTCKS_Msk (0x3U << CMU_OPCCR2_LPTCKS_Pos)
|
#define CMU_OPCCR2_LPTCKS_APBCLK (0x0U << CMU_OPCCR2_LPTCKS_Pos) /* APBCLK */
|
#define CMU_OPCCR2_LPTCKS_LSCLK (0x1U << CMU_OPCCR2_LPTCKS_Pos) /* LSCLK */
|
#define CMU_OPCCR2_LPTCKS_RCLP (0x2U << CMU_OPCCR2_LPTCKS_Pos) /* RCLP */
|
#define CMU_OPCCR2_LPTCKS_PLL_L (0x3U << CMU_OPCCR2_LPTCKS_Pos) /* PLL_L */
|
|
#define CMU_OPCCR2_BSTCKE_Pos 4 /* BSTIM¹¤×÷ʱÖÓʹÄÜ£¬¸ßÓÐЧ */
|
#define CMU_OPCCR2_BSTCKE_Msk (0x1U << CMU_OPCCR2_BSTCKE_Pos)
|
|
#define CMU_OPCCR2_BSTCKS_Pos 0 /* BSTIM¹¤×÷ʱÖÓÔ´Ñ¡Ôñ
|
00£ºAPBCLK
|
01£ºLSCLK
|
10£ºRCLP
|
11£ºSYSCLK */
|
#define CMU_OPCCR2_BSTCKS_Msk (0x3U << CMU_OPCCR2_BSTCKS_Pos)
|
#define CMU_OPCCR2_BSTCKS_APBCLK (0x0U << CMU_OPCCR2_BSTCKS_Pos) /* APBCLK */
|
#define CMU_OPCCR2_BSTCKS_LSCLK (0x1U << CMU_OPCCR2_BSTCKS_Pos) /* LSCLK */
|
#define CMU_OPCCR2_BSTCKS_RCLP (0x2U << CMU_OPCCR2_BSTCKS_Pos) /* RCLP */
|
#define CMU_OPCCR2_BSTCKS_SYSCLK (0x3U << CMU_OPCCR2_BSTCKS_Pos) /* SYSCLK */
|
//Macro_End
|
|
/* Exported functions --------------------------------------------------------*/
|
extern void CMU_Deinit(void);
|
extern void CMU_SYSCLKCR_SLP_ENEXTI_Setable(FunState NewState);
|
extern FunState CMU_SYSCLKCR_SLP_ENEXTI_Getable(void);
|
|
/* APBʱÖÓ·ÖƵѡÔñ (APBbus clock Prescaler)
|
000/001/010/011£º²»·ÖƵ
|
100£º2·ÖƵ
|
101£º4·ÖƵ
|
110£º8·ÖƵ
|
111£º16·ÖƵ Ïà¹Øº¯Êý */
|
extern void CMU_SYSCLKCR_APBPRES_Set(uint32_t SetValue);
|
extern uint32_t CMU_SYSCLKCR_APBPRES_Get(void);
|
|
/* AHBʱÖÓ·ÖƵѡÔñ (AHB bus clock Prescaler)
|
000/001/010/011£º²»·ÖƵ
|
100£º2·ÖƵ
|
101£º4·ÖƵ
|
110£º8·ÖƵ
|
111£º16·ÖƵ Ïà¹Øº¯Êý */
|
extern void CMU_SYSCLKCR_AHBPRES_Set(uint32_t SetValue);
|
extern uint32_t CMU_SYSCLKCR_AHBPRES_Get(void);
|
|
/* CPUÄÚºËsystick¹¤×÷ʱÖÓÑ¡Ôñ (Systick clock select)
|
00£ºSCLK
|
01£ºLSCLK
|
10£ºRC4M
|
11£ºSYSCLK Ïà¹Øº¯Êý */
|
extern void CMU_SYSCLKCR_STCLKSEL_Set(uint32_t SetValue);
|
extern uint32_t CMU_SYSCLKCR_STCLKSEL_Get(void);
|
|
/* ϵͳʱÖÓÔ´Ñ¡Ôñ Ïà¹Øº¯Êý */
|
extern void CMU_SYSCLKCR_SYSCLKSEL_Set(uint32_t SetValue);
|
extern uint32_t CMU_SYSCLKCR_SYSCLKSEL_Get(void);
|
|
/* RCHFƵÂÊÑ¡Ôñ¼Ä´æÆ÷0000£º8MHz
|
0001£º16MHz
|
0010£º24MHz
|
0011£º32MHz
|
0111£º40MHz
|
1111£º48MHz
|
ÆäËû£ºRFU Ïà¹Øº¯Êý */
|
extern void CMU_RCHFCR_FSEL_Set(uint32_t SetValue);
|
extern uint32_t CMU_RCHFCR_FSEL_Get(void);
|
|
/* RCHFʹÄܼĴæÆ÷ (RCHF Enable)
|
1£ºÊ¹ÄÜRCHF
|
0£º¹Ø±ÕRCHF Ïà¹Øº¯Êý */
|
extern void CMU_RCHFCR_RCHFEN_Setable(FunState NewState);
|
extern FunState CMU_RCHFCR_RCHFEN_Getable(void);
|
|
/* RCHFƵÂʵ÷У¼Ä´æÆ÷£¬8¡¯h00±íʾƵÂÊ×îµÍ£¬8¡¯hFF±íʾƵÂÊ×î¸ß£¬µ÷У·¶Î§ÎªÖÐÐÄƵÂÊ+/-30%£¬µ÷У²½³¤ÎªÖÐÐÄƵÂÊ0.25%
|
ÉϵçºóоƬ×Ô¶¯´ÓLDT0¶ÁÈ¡8MHzµ÷Уֵ²¢Ð´Èë´Ë¼Ä´æÆ÷
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Èí¼þʹÓÃÆäËûƵÂÊʱ£¬¿ÉÒÔ×ÔÐдÓLDT0Ö¸¶¨µØÖ·¶ÁÈ¡µ÷УÐÅÏ¢²¢Ð´Èë´Ë¼Ä´æÆ÷£¬´Ó¶øÈ·±£Êä³öƵÂÊ׼ȷ¡£ Ïà¹Øº¯Êý */
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extern void CMU_RCHFTR_RCHFTRIM_Set(uint32_t SetValue);
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extern uint32_t CMU_RCHFTR_RCHFTRIM_Get(void);
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extern FlagStatus CMU_PLLLCR_LOCKED_Chk(void);
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extern void CMU_PLLLCR_PLLDB_Set(uint32_t SetValue);
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extern uint32_t CMU_PLLLCR_PLLDB_Get(void);
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/* PLLʹÄܼĴæÆ÷
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1£ºÊ¹ÄÜPLL
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0£º¹Ø±ÕPLL Ïà¹Øº¯Êý */
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extern void CMU_PLLLCR_PLLEN_Setable(FunState NewState);
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extern FunState CMU_PLLLCR_PLLEN_Getable(void);
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/* PLLH±¶Æµ±È£¬²Î¿¼Ê±ÖÓ1Mhz
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0000011111£ºÊä³ö32±¶Æµ
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0101111£ºÊä³ö48±¶Æµ Ïà¹Øº¯Êý */
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extern void CMU_PLLHCR_PLLHDB_Set(uint32_t SetValue);
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extern uint32_t CMU_PLLHCR_PLLHDB_Get(void);
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/* PLLHËø¶¨±êÖ¾£¬Èí¼þͨ¹ý²éѯ´Ë¼Ä´æÆ÷È·ÈÏPLLÒѾ´¦ÓÚËø¶¨×´Ì¬
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1£ºPLLÒÑËø¶¨
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0£ºPLLδËø¶¨ Ïà¹Øº¯Êý */
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extern FlagStatus CMU_PLLHCR_LOCKED_Chk(void);
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/* PLLH²Î¿¼Ê±ÖÓÔ¤·ÖƵ£¨Ä¿±êÊDzúÉú1MHz²Î¿¼Ê±ÖÓ¸øPLL£©
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000£º²»·ÖƵ
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001£º2·ÖƵ
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010£º4·ÖƵ
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011£º8·ÖƵ
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100£º12·ÖƵ
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101£º16·ÖƵ
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110£º24·ÖƵ
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111£º32·ÖƵ Ïà¹Øº¯Êý */
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extern void CMU_PLLHCR_REFPRSC_Set(uint32_t SetValue);
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extern uint32_t CMU_PLLHCR_REFPRSC_Get(void);
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/* PLLHÊä³öÑ¡Ôñ¼Ä´æÆ÷
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0£ºÑ¡ÔñPLLHÒ»±¶Êä³ö×÷ΪÊý×Öµç·ÄÚµÄPLLʱÖÓ
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1£ºÑ¡ÔñPLLHÁ½±¶Êä³ö×÷ΪÊý×Öµç·ÄÚµÄPLLʱÖÓ Ïà¹Øº¯Êý */
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extern void CMU_PLLHCR_OSEL_Set(uint32_t SetValue);
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extern uint32_t CMU_PLLHCR_OSEL_Get(void);
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/* PLLHÊäÈëÑ¡Ôñ¼Ä´æÆ÷
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00/11£ºRCHF
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01£ºPLL_L
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10£ºXTHF Ïà¹Øº¯Êý */
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extern void CMU_PLLHCR_INSEL_Set(uint32_t SetValue);
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extern uint32_t CMU_PLLHCR_INSEL_Get(void);
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/* PLLHʹÄܼĴæÆ÷
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1£ºÊ¹ÄÜPLLH
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0£º¹Ø±ÕPLLH Ïà¹Øº¯Êý */
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extern void CMU_PLLHCR_EN_Setable(FunState NewState);
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extern FunState CMU_PLLHCR_EN_Getable(void);
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/* XTHFÕñµ´Ç¿¶ÈÅäÖÃ
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000£º×îÈõ
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111£º×îÇ¿ Ïà¹Øº¯Êý */
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extern void CMU_XTHFCR_XTHF_CFG_Set(uint32_t SetValue);
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extern uint32_t CMU_XTHFCR_XTHF_CFG_Get(void);
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/* XTHFʹÄܼĴæÆ÷
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0£º¹Ø±ÕXTHF
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1£ºÊ¹ÄÜXTHF Ïà¹Øº¯Êý */
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extern void CMU_XTHFCR_XTHFEN_Setable(FunState NewState);
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extern FunState CMU_XTHFCR_XTHFEN_Getable(void);
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extern void CMU_IER_SYSCSE_IE_Setable(FunState NewState);
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extern FunState CMU_IER_SYSCSE_IE_Getable(void);
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extern void CMU_IER_HFDET_IE_Setable(FunState NewState);
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extern FunState CMU_IER_HFDET_IE_Getable(void);
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/* ¸ßƵ¾§ÌåÍ£Õñ¼ì²âÄ£¿éÊä³ö
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1£ºXTHFδͣÕñ
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0£ºXTHFÍ£Õñ Ïà¹Øº¯Êý */
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extern FlagStatus CMU_ISR_HFDETO_Chk(void);
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/* µÍƵ¾§ÌåÍ£Õñ¼ì²âÄ£¿éÊä³ö
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1£ºXTLFδͣÕñ
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0£ºXTLFÍ£Õñ Ïà¹Øº¯Êý */
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extern FlagStatus CMU_ISR_LFDETO_Chk(void);
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/* SYSCLKʱÖÓÑ¡Ôñ´íÎóÖжϱêÖ¾¼Ä´æÆ÷£»µ±±»Ñ¡ÖеÄʱÖÓԴûÓÐʹÄÜʱ£¬´ËÖжϱêÖ¾ÖÃ룬Èí¼þд1ÇåÁã¡£ Ïà¹Øº¯Êý */
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extern void CMU_ISR_SYSCSE_IF_Clr(void);
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extern FlagStatus CMU_ISR_SYSCSE_IF_Chk(void);
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/* ¸ßƵͣÕñ¼ì²âÖжϱêÖ¾¼Ä´æÆ÷£¬XTHFÍ£ÕñʱӲ¼þÒì²½ÖÃ룬Èí¼þд1ÇåÁ㣻ֻÓÐÔÚFFDETO²»Îª0µÄÇé¿öϲÅÄܹ»Çå³ý´Ë¼Ä´æÆ÷ Ïà¹Øº¯Êý */
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extern void CMU_ISR_HFDET_IF_Clr(void);
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extern FlagStatus CMU_ISR_HFDET_IF_Chk(void);
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/* EXTI¹¤×÷ʱÖÓʹÄÜ£¬¸ßÓÐЧ Ïà¹Øº¯Êý */
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extern void CMU_OPCCR1_EXTICKE_Setable(FunState NewState);
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extern FunState CMU_OPCCR1_EXTICKE_Getable(void);
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/* EXTIÖжϲÉÑùʱÖÓÑ¡Ôñ */
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extern void CMU_OPCCR1_EXTICKSEL_Set(uint32_t SetValue);
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extern uint32_t CMU_OPCCR1_EXTICKSEL_Get(void);
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/* LPUART1¹¤×÷ʱÖÓʹÄÜ£¬¸ßÓÐЧ Ïà¹Øº¯Êý */
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extern void CMU_OPCCR1_LPUART1CKE_Setable(FunState NewState);
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extern FunState CMU_OPCCR1_LPUART1CKE_Getable(void);
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/* LPUART0¹¤×÷ʱÖÓʹÄÜ£¬¸ßÓÐЧ Ïà¹Øº¯Êý */
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extern void CMU_OPCCR1_LPUART0CKE_Setable(FunState NewState);
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extern FunState CMU_OPCCR1_LPUART0CKE_Getable(void);
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/* LPUART1¹¤×÷ʱÖÓÑ¡Ôñ
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00£ºLSCLK
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01£ºRCHF·ÖƵ£¨¸ù¾ÝRCHFµµÎ»×Ô¶¯·ÖƵµ½32768Hz¸½½ü£©
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10£ºRFU
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11£ºRFU Ïà¹Øº¯Êý */
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extern void CMU_OPCCR1_LPUART1CKS_Set(uint32_t SetValue);
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extern uint32_t CMU_OPCCR1_LPUART1CKS_Get(void);
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/* LPUART0¹¤×÷ʱÖÓÑ¡Ôñ
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00£ºLSCLK
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01£ºRCHF·ÖƵ£¨¸ù¾ÝRCHFµµÎ»×Ô¶¯·ÖƵµ½32768Hz¸½½ü£©
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10£ºRFU
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11£ºRFU Ïà¹Øº¯Êý */
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extern void CMU_OPCCR1_LPUART0CKS_Set(uint32_t SetValue);
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extern uint32_t CMU_OPCCR1_LPUART0CKS_Get(void);
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/* I2C1¹¤×÷ʱÖÓʹÄÜ Ïà¹Øº¯Êý */
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extern void CMU_OPCCR1_I2C1CKE_Setable(FunState NewState);
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extern FunState CMU_OPCCR1_I2C1CKE_Getable(void);
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/* I2C0¹¤×÷ʱÖÓʹÄÜ Ïà¹Øº¯Êý */
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extern void CMU_OPCCR1_I2C0CKE_Setable(FunState NewState);
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extern FunState CMU_OPCCR1_I2C0CKE_Getable(void);
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/* I2C1Ö÷»ú¹¤×÷ʱÖÓÑ¡Ôñ
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00£ºAPBCLK
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01£ºRCHF
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10£ºSYSCLK
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11£ºAPBCLK Ïà¹Øº¯Êý */
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extern void CMU_OPCCR1_I2C1CKS_Set(uint32_t SetValue);
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extern uint32_t CMU_OPCCR1_I2C1CKS_Get(void);
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/* I2C0Ö÷»ú¹¤×÷ʱÖÓÑ¡Ôñ
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00£ºAPBCLK
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01£ºRCHF
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10£ºSYSCLK
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11£ºAPBCLK Ïà¹Øº¯Êý */
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extern void CMU_OPCCR1_I2C0CKS_Set(uint32_t SetValue);
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extern uint32_t CMU_OPCCR1_I2C0CKS_Get(void);
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/* UART1¹¤×÷ʱÖÓʹÄÜ£¬¸ßÓÐЧ Ïà¹Øº¯Êý */
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extern void CMU_OPCCR1_UART1CKE_Setable(FunState NewState);
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extern FunState CMU_OPCCR1_UART1CKE_Getable(void);
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/* UART0¹¤×÷ʱÖÓʹÄÜ£¬¸ßÓÐЧ Ïà¹Øº¯Êý */
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extern void CMU_OPCCR1_UART0CKE_Setable(FunState NewState);
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extern FunState CMU_OPCCR1_UART0CKE_Getable(void);
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/* UART1¹¤×÷ʱÖÓÑ¡Ôñ
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00£ºAPBCLK
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01£ºRCHF
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10£ºSYSCLK
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11£ºRFU Ïà¹Øº¯Êý */
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extern void CMU_OPCCR1_UART1CKS_Set(uint32_t SetValue);
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extern uint32_t CMU_OPCCR1_UART1CKS_Get(void);
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/* UART0¹¤×÷ʱÖÓÑ¡Ôñ
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00£ºAPBCLK
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01£ºRCHF
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10£ºSYSCLK
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11£ºRFU Ïà¹Øº¯Êý */
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extern void CMU_OPCCR1_UART0CKS_Set(uint32_t SetValue);
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extern uint32_t CMU_OPCCR1_UART0CKS_Get(void);
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/* Ëæ»úÊý·¢ÉúÆ÷¹¤×÷ʱÖÓ·ÖƵ
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000£º²»·ÖƵ
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001£º2·ÖƵ
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010£º4·ÖƵ
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011£º8·ÖƵ
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100£º16·ÖƵ
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101£º32·ÖƵ
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110, 111£ºRFU Ïà¹Øº¯Êý */
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extern void CMU_OPCCR2_RNGPRSC_Set(uint32_t SetValue);
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extern uint32_t CMU_OPCCR2_RNGPRSC_Get(void);
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/* Flash²ÁдʱÖÓʹÄÜ£¬¸ßÓÐЧ Ïà¹Øº¯Êý */
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extern void CMU_OPCCR2_NVMCKE_Setable(FunState NewState);
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extern FunState CMU_OPCCR2_NVMCKE_Getable(void);
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/* Ëæ»úÊý·¢ÉúÆ÷¹¤×÷ʱÖÓʹÄÜ£¬¸ßÓÐЧ Ïà¹Øº¯Êý */
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extern void CMU_OPCCR2_RNGCKE_Setable(FunState NewState);
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extern FunState CMU_OPCCR2_RNGCKE_Getable(void);
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/* _¹¤×÷ʱÖÓʹÄÜ£¬¸ßÓÐЧ Ïà¹Øº¯Êý */
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extern void CMU_OPCCR2_LPTCKE_Setable(FunState NewState);
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extern FunState CMU_OPCCR2_LPTCKE_Getable(void);
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/* _¹¤×÷ʱÖÓÑ¡Ôñ
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00£ºAPBCLK
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01£ºLSCLK
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10£ºRCLP
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11£ºPLL_L Ïà¹Øº¯Êý */
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extern void CMU_OPCCR2_LPTCKS_Set(uint32_t SetValue);
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extern uint32_t CMU_OPCCR2_LPTCKS_Get(void);
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/* BSTIM¹¤×÷ʱÖÓʹÄÜ£¬¸ßÓÐЧ Ïà¹Øº¯Êý */
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extern void CMU_OPCCR2_BSTCKE_Setable(FunState NewState);
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extern FunState CMU_OPCCR2_BSTCKE_Getable(void);
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/* BSTIM¹¤×÷ʱÖÓÔ´Ñ¡Ôñ
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00£ºAPBCLK
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01£ºLSCLK
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10£ºRCLP
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11£ºSYSCLK Ïà¹Øº¯Êý */
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extern void CMU_OPCCR2_BSTCKS_Set(uint32_t SetValue);
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extern uint32_t CMU_OPCCR2_BSTCKS_Get(void);
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//Announce_End
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/* »ñȡоƬÒÑÉèÖõIJ»Í¬Ê±ÖÓƵÂʺ¯Êý */
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extern void CMU_GetClocksFreq(CMU_ClocksType* para);
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/* RCHF³õʼ»¯º¯Êý */
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extern void CMU_RCHF_Init(CMU_RCHF_InitTypeDef* para);
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/* PLL H³õʼ»¯º¯Êý */
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void CMU_PLL_H_Init(CMU_PLL_H_InitTypeDef* para);
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/* rchf³£ÎÂУ׼ֵÔØÈ뺯Êý */
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extern void CMU_Init_RCHF_Trim( uint8_t ClkMode );
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/* ϵͳʱÖÓ³õʼ»¯ */
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extern void CMU_SysClk_Init(CMU_SYSCLK_InitTypeDef* para);
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/* ÍâÉèʱÖÓ¿ØÖƲÎÊý¶¨Òå */
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#define COMPCLK (0x01000000 + CMU_PCLKCR1_COMP_PCE_Pos) //9 /* COMP×ÜÏßʱÖÓʹÄÜ£¬¸ßʹÄÜ */
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#define SVDCLK (0x01000000 + CMU_PCLKCR1_SVD_PCE_Pos) //8 /* SVD×ÜÏßʱÖÓʹÄÜ£¬¸ßʹÄÜ */
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#define PADCLK (0x01000000 + CMU_PCLKCR1_PAD_PCE_Pos) //7 /* PADCFG×ÜÏßʱÖÓʹÄÜ£¬¸ßʹÄÜ */
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#define ANACCLK (0x01000000 + CMU_PCLKCR1_ANAC_PCE_Pos) //6 /* ANAC×ÜÏßʱÖÓʹÄÜ£¬¸ßʹÄܴ˼ĴæÆ÷ÓÃÓÚ¿ØÖÆSVD¡¢±È½ÏÆ÷µÄ×ÜÏßʱÖÓ */
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#define IWDTCLK (0x01000000 + CMU_PCLKCR1_IWDT_PCE_Pos) //5 /* IWDT×ÜÏßʱÖÓʹÄÜ£¬¸ßʹÄÜ */
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#define SCUCLK (0x01000000 + CMU_PCLKCR1_SCU_PCE_Pos) //4 /* SCU×ÜÏßʱÖÓʹÄÜ£¬¸ßʹÄÜ */
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#define PMUCLK (0x01000000 + CMU_PCLKCR1_PMU_PCE_Pos) //3 /* PMU×ÜÏßʱÖÓʹÄÜ£¬¸ßʹÄÜ */
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#define RTCCLK (0x01000000 + CMU_PCLKCR1_RTC_PCE_Pos) //2 /* RTC×ÜÏßʱÖÓʹÄÜ£¬¸ßʹÄÜ */
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#define LPTCLK (0x01000000 + CMU_PCLKCR1_LPT_PCE_Pos) //0 /* LPTIM×ÜÏßʱÖÓʹÄÜ£¬¸ßʹÄÜ */
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#define PAECLK (0x02000000 + CMU_PCLKCR2_PAE_PCE_Pos) //17 /* PAE×ÜÏßʱÖÓʹÄÜ£¬¸ßʹÄÜ */
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#define SHACLK (0x02000000 + CMU_PCLKCR2_SHA_PCE_Pos) //16 /* SHA×ÜÏßʱÖÓʹÄÜ£¬¸ßʹÄÜ */
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#define CICCLK (0x02000000 + CMU_PCLKCR2_CIC_PCE_Pos) //8 /* CIC×ÜÏßʱÖÓʹÄÜ£¬¸ßʹÄÜ */
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#define WWDTCLK (0x02000000 + CMU_PCLKCR2_WWDT_PCE_Pos) //7 /* WWDTʱÖÓʹÄÜ£¬¸ßʹÄÜ */
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#define RAMBISTCLK (0x02000000 + CMU_PCLKCR2_RAMBIST_PCE_Pos) //6 /* RAMBISTʱÖÓʹÄÜ£¬¸ßʹÄÜ */
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#define FLASHCLK (0x02000000 + CMU_PCLKCR2_NVM_PCE_Pos) //5 /* FLSC£¨Flash²Áд¿ØÖÆÆ÷£©Ê±ÖÓʹÄÜ£¬¸ßʹÄÜ */
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#define DMACLK (0x02000000 + CMU_PCLKCR2_DMA_PCE_Pos) //4 /* DMAʱÖÓʹÄÜ£¬¸ßʹÄÜ */
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#define LCDCLK (0x02000000 + CMU_PCLKCR2_LCD_PCE_Pos) //3 /* LCDʱÖÓʹÄÜ£¬¸ßʹÄÜ */
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#define AESCLK (0x02000000 + CMU_PCLKCR2_AES_PCE_Pos) //2 /* AESʱÖÓʹÄÜ£¬¸ßʹÄÜ */
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#define TRNGCLK (0x02000000 + CMU_PCLKCR2_TRNG_PCE_Pos) //1 /* RNGʱÖÓʹÄÜ£¬¸ßʹÄÜ */
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#define CRCCLK (0x02000000 + CMU_PCLKCR2_CRC_PCE_Pos) //0 /* CRCʱÖÓʹÄÜ£¬¸ßʹÄÜ */
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#define I2C1CLK (0x03000000 + CMU_PCLKCR3_I2C1_PCE_Pos) //25 /* I2C1ʱÖÓʹÄÜ */
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#define I2C0CLK (0x03000000 + CMU_PCLKCR3_I2C0_PCE_Pos) //24 /* I2C0ʱÖÓʹÄÜ */
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#define LPUART1CLK (0x03000000 + CMU_PCLKCR3_LPUART1_PCE_Pos) //18 /* LPUART1¹¦ÄÜʱÖÓʹÄÜ */
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#define U7816CLK (0x03000000 + CMU_PCLKCR3_U7816_PCE_Pos) //16 /* U7816-0ʱÖÓʹÄÜ */
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#define LPUART0CLK (0x03000000 + CMU_PCLKCR3_LPUART0_PCE_Pos) //15 /* LPUART0¼Ä´æÆ÷×ÜÏßʱÖÓʹÄÜ */
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#define UARTIRCLK (0x03000000 + CMU_PCLKCR3_UICR_PCE_Pos) //14 /* UARTºìÍâ×ÜÏßʹÄÜ£¬¸ßʹÄÜ*/
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#define UART5CLK (0x03000000 + CMU_PCLKCR3_UART5_PCE_Pos) //13 /* UART5ʱÖÓʹÄÜ */
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#define UART4CLK (0x03000000 + CMU_PCLKCR3_UART4_PCE_Pos) //12 /* UART4ʱÖÓʹÄÜ */
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#define UART3CLK (0x03000000 + CMU_PCLKCR3_UART3_PCE_Pos) //11 /* UART3ʱÖÓʹÄÜ */
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#define UART2CLK (0x03000000 + CMU_PCLKCR3_UART2_PCE_Pos) //10 /* UART2ʱÖÓʹÄÜ */
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#define UART1CLK (0x03000000 + CMU_PCLKCR3_UART1_PCE_Pos) //9 /* UART1ʱÖÓʹÄÜ */
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#define UART0CLK (0x03000000 + CMU_PCLKCR3_UART0_PCE_Pos) //8 /* UART0ʱÖÓʹÄÜ */
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#define QSPICLK (0x03000000 + CMU_PCLKCR3_QSPI_PCE_Pos) //7 /* QSPI×ÜÏßʱÖÓʹÄÜ */
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#define SPI4CLK (0x03000000 + CMU_PCLKCR3_SPI4_PCE_Pos) //4 /* SPI4ʱÖÓʹÄÜ */
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#define SPI3CLK (0x03000000 + CMU_PCLKCR3_SPI3_PCE_Pos) //3 /* SPI3ʱÖÓʹÄÜ */
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#define SPI2CLK (0x03000000 + CMU_PCLKCR3_SPI2_PCE_Pos) //2 /* SPI2ʱÖÓʹÄÜ */
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#define SPI1CLK (0x03000000 + CMU_PCLKCR3_SPI1_PCE_Pos) //1 /* SPI1ʱÖÓʹÄÜ */
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#define SPI0CLK (0x03000000 + CMU_PCLKCR3_SPI0_PCE_Pos) //0 /* SPI0ʱÖÓʹÄÜ */
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#define ET4CLK (0x04000000 + CMU_PCLKCR4_ET4_PCE_Pos) //6 /* Etimer4ʱÖÓʹÄÜ£¬¸ßʹÄÜ */
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#define ET3CLK (0x04000000 + CMU_PCLKCR4_ET3_PCE_Pos) //5 /* Etimer3ʱÖÓʹÄÜ£¬¸ßʹÄÜ */
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#define ET2CLK (0x04000000 + CMU_PCLKCR4_ET2_PCE_Pos) //4 /* Etimer2ʱÖÓʹÄÜ£¬¸ßʹÄÜ */
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#define ET1CLK (0x04000000 + CMU_PCLKCR4_ET1_PCE_Pos) //3 /* Etimer1ʱÖÓʹÄÜ£¬¸ßʹÄÜ */
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#define BT2CLK (0x04000000 + CMU_PCLKCR4_BT2_PCE_Pos) //2 /* BaseTimer2ʱÖÓʹÄÜ£¬¸ßʹÄÜ */
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#define BT1CLK (0x04000000 + CMU_PCLKCR4_BT1_PCE_Pos) //1 /* BaseTimer1ʱÖÓʹÄÜ£¬¸ßʹÄÜ */
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#define BSTIMCLK (0x04000000 + CMU_PCLKCR4_BSTIM_PCE_Pos) //0 /* »ù±¾¶¨Ê±Æ÷BSTIM×ÜÏßʱÖÓʹÄÜ£¬¸ßʹÄÜ */
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/* ÍâÉèʱÖÓʹÄܺ¯Êý */
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extern void CMU_PERCLK_SetableEx(uint32_t periph_def, FunState NewState);
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#ifdef __cplusplus
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}
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#endif
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#endif /* __FM33A0XXEV_CMU_H */
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