金礼聪移植周巍修改后首次提交

jinlicong

2024-04-18 de0f427ee76ab84d3afb22c92a2b065b1ce06d3e

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..\\Drivers\\fm33a0xxev_qspi.cComponent: ARM Compiler 5.06 update 7 for Certification (build 960) Tool: armasm [4d35fa]E:\GasFlowmeter\Internet_of_things_valve\SZV103\SZV103_FM33A0xxEV_SiZhu_jlcGai\KEIL_MDKARM__asm___17_fm33a0xxev_qspi_c_d96e7cd4____REV16P9

 




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__DATE__ "Apr 16 2024"
__TIME__ "19:58:50"
__STDC__ 1
__STDC_VERSION__ 199901L
__STDC_HOSTED__ 1
__STDC_ISO_10646__ 200607
__EDG__ 1
__EDG_VERSION__ 407
__EDG_SIZE_TYPE__ unsigned int
__EDG_PTRDIFF_TYPE__ int
__GNUC__ 4
__GNUC_STDC_INLINE__ 1
__GNUC_MINOR__ 7
__GNUC_PATCHLEVEL__ 0
__VERSION__ "4.7 (EDG gcc mode)"
__CHAR16_TYPE__ unsigned short
__CHAR32_TYPE__ unsigned int
__USER_LABEL_PREFIX__ 
__CHAR_UNSIGNED__ 1
__WCHAR_UNSIGNED__ 1
__SIZE_TYPE__ unsigned int
__PTRDIFF_TYPE__ int
__WCHAR_TYPE__ unsigned short
__WINT_TYPE__ unsigned short
__INTMAX_TYPE__ long long
__UINTMAX_TYPE__ unsigned long long
__sizeof_int 4
__sizeof_long 4
__sizeof_ptr 4
__ARMCC_VERSION 5060960
__TARGET_CPU_CORTEX_M0 1
__TARGET_FPU_SOFTVFP 1
__TARGET_FPU_SOFTVFP 1
__MICROLIB 1
__UVISION_VERSION 538
_RTE_ 1
_RTE_ 1
__VTOR_PRESENT 1
__CC_ARM 1
__arm 1
__arm__ 1
__TARGET_ARCH_6S_M 1
__TARGET_ARCH_ARM 0
__TARGET_ARCH_THUMB 3
__TARGET_ARCH_A64 0
__TARGET_ARCH_AARCH32 1
__TARGET_PROFILE_M 1
__TARGET_FEATURE_HALFWORD 1
__TARGET_FEATURE_THUMB 1
__TARGET_FEATURE_DMB 1
__TARGET_FEATURE_EXTENSION_REGISTER_COUNT 0
__APCS_INTERWORK 1
__thumb 1
__thumb__ 1
__t32__ 1
__OPTIMISE_SPACE 1
__OPTIMIZE_SIZE__ 1
__OPTIMISE_LEVEL 0
__SOFTFP__ 1
(<
ëQSPI_CR_PRESCALER_Set(0
ëQSPI_CR_PRESCALER_Get"4
ëQSPI_CR_PMM_Set",
ëQSPI_CR_PMM_Get',
ëQSPI_CR_TOIE_Setable'0
ëQSPI_CR_TOIE_Getable',
ëQSPI_CR_SMIE_Setable'0
ëQSPI_CR_SMIE_Getable',
ëQSPI_CR_FTIE_Setable'0
ëQSPI_CR_FTIE_Getable',
ëQSPI_CR_TCIE_Setable'0
ëQSPI_CR_TCIE_Getable',
ëQSPI_CR_TEIE_Setable'0
ëQSPI_CR_TEIE_Getable&<
ëQSPI_CR_FIFOTHR_Set&0
ëQSPI_CR_FIFOTHR_Get(,
ëQSPI_CR_SSHFT_Setable(4
ëQSPI_CR_SSHFT_Getable',
ëQSPI_CR_TCEN_Setable'0
ëQSPI_CR_TCEN_Getable(,
ëQSPI_CR_DMAEN_Setable(4
ëQSPI_CR_DMAEN_Getable(,
ëQSPI_CR_ABORT_Setable(4
ëQSPI_CR_ABORT_Getable%(
ëQSPI_CR_EN_Setable%0
ëQSPI_CR_EN_Getable$8
ëQSPI_CFG_CSHT_Set$,
ëQSPI_CFG_CSHT_Get&<
ëQSPI_CFG_CKMODE_Set&0
ëQSPI_CFG_CKMODE_Get&0
ëQSPI_SR_FIFOLVL_Get#,
ëQSPI_SR_BUSY_Chk"
ëQSPI_SR_TOF_Clr",
ëQSPI_SR_TOF_Chk"
ëQSPI_SR_SMF_Clr",
ëQSPI_SR_SMF_Chk",
ëQSPI_SR_FTF_Chk"
ëQSPI_SR_TCF_Clr",
ëQSPI_SR_TCF_Chk%(
ëQSPI_DATALEN_Write$,
ëQSPI_DATALEN_Read!$
ëQSPI_CCR_Write (
ëQSPI_CCR_Read"(
ëQSPI_ADDR_Write!,
ëQSPI_ADDR_Read!$
ëQSPI_ABR_Write (
ëQSPI_ABR_Read$(
ëQSPI_DR_WriteByte#,
ëQSPI_DR_ReadByte(,
ëQSPI_DR_WriteHalfword'0
ëQSPI_DR_ReadHalfword$(
ëQSPI_DR_WriteWord#,
ëQSPI_DR_ReadWord"(
ëQSPI_SMSK_Write!,
ëQSPI_SMSK_Read"(
ëQSPI_SMAT_Write!,
ëQSPI_SMAT_Read"(
ëQSPI_PITV_Write!,
ëQSPI_PITV_Read $
ëQSPI_TO_Write(
ëQSPI_TO_Read
ëQSPI_Deinit
ëQSPI_Init
‡


%

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__stdint_h 
__ARMCLIB_VERSION 5060044
__INT64 __int64
__INT64_C_SUFFIX__ ll
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__PASTE(x,y) __PASTE2(x, y)
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__LONGLONG long long
#__STDINT_DECLS %__CLIBNS
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sINT8_MIN -128
tINT16_MIN -32768
uINT32_MIN (~0x7fffffff)
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yINT8_MAX 127
zINT16_MAX 32767
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INT_LEAST8_MAX 127
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INT_FAST8_MAX 2147483647
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INT_FAST32_MAX 2147483647
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UINT_FAST8_MAX 4294967295u
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UINT_FAST16_MAX 4294967295u
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UINT_FAST32_MAX 4294967295u
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INTPTR_MIN INT32_MIN
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UINTPTR_MAX UINT32_MAX
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INTMAX_MIN __ESCAPE__(~0x7fffffffffffffffll)
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INTMAX_MAX __ESCAPE__(9223372036854775807ll)
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PTRDIFF_MIN INT32_MIN
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Ú
SIG_ATOMIC_MIN (~0x7fffffff)
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SIG_ATOMIC_MAX 2147483647
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SIZE_MAX UINT32_MAXç
WCHAR_MINè
WCHAR_MAX
î
WCHAR_MIN 0
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WCHAR_MAX 65535
ó
WINT_MIN (~0x7fffffff)
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†INTMAX_C(x) __ESCAPE__(x ## ll)
‡UINTMAX_C(x) __ESCAPE__(x ## ull)²__INT64³__LONGLONGXO
 




D:\Program Files\MDK5\ARM\ARMCC\Bin\..\include\stdint.h


tD:\Program Files\MDK5\ARM\ARMCC\Bin\..\include\stdint.hComponent: ARM Compiler 5.06 update 7 for Certification (build 960) Tool: ArmCC [4d365d]
signed charshortintlong long
unsigned charunsigned shortunsigned intunsigned long longPint8_t§
8 Pint16_t¶
9 Pint32_t¿
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? Puint32_tö
@ Puint64_t

A Pint_least8_t§
G Pint_least16_t¶
H Pint_least32_t¿
I Pint_least64_tÆ
J Puint_least8_tÓ
M Puint_least16_tä
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P Pint_fast8_t¿
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f Pintmax_tÆ
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k!Pu8Ó
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'__CORE_CMINSTR_H 
<__NOP __nop
D__WFI __wfi
L__WFE __wfe
S__SEV __sev
\__ISB() do { __schedule_barrier(); __isb(0xF); __schedule_barrier(); } while (0)
g__DSB() do { __schedule_barrier(); __dsb(0xF); __schedule_barrier(); } while (0)
r__DMB() do { __schedule_barrier(); __dmb(0xF); __schedule_barrier(); } while (0)
__REV __rev
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__BKPT(value) __breakpoint(value)
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__CLZ __clz@6
 




..\Core\Include\core_cminstr.h


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..\Core\Include\core_cmfunc.h


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..\Core\Include\core_cmfunc.hComponent: ARM Compiler 5.06 update 7 for Certification (build 960) Tool: ArmCC [4d365d]E:\GasFlowmeter\Internet_of_things_valve\SZV103\SZV103_FM33A0xxEV_SiZhu_jlcGai\KEIL_MDKARM;¨
@__get_CONTROLv
a__resultv

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Z__get_IPSRv
a__resultv

Y__regIPSRv

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g__get_APSRv
a__resultv

Y__regAPSRv

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t__get_xPSRv
a__resultv

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a__resultv

Y__regProcessStackPointerv

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__set_PSP$v
topOfProcStackY__regProcessStackPointerv

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a__resultv

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 __CORE_CM0PLUS_H_GENERIC "
@__CM0PLUS_CMSIS_VERSION_MAIN ( 5U)
A__CM0PLUS_CMSIS_VERSION_SUB ( 0U)
B__CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | __CM0PLUS_CMSIS_VERSION_SUB )
E__CORTEX_M (0U)
Q__ASM __asm
R__INLINE __inline
S__STATIC_INLINE static __inline
T__NO_RETURN __declspec(noreturn)
U__USED __attribute__((used))
V__WEAK __attribute__((weak))
W__UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
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__FPU_USED 0UÆ
Ç

Ò
__CORE_CM0PLUS_H_DEPENDANT 
ÿ
__I volatile const
__O volatile
‚__IO volatile
…__IM volatile const
†__OM volatile
‡__IOM volatile
³APSR_N_Pos 31U
´APSR_N_Msk (1UL << APSR_N_Pos)
¶APSR_Z_Pos 30U
·APSR_Z_Msk (1UL << APSR_Z_Pos)
¹APSR_C_Pos 29U
ºAPSR_C_Msk (1UL << APSR_C_Pos)
¼APSR_V_Pos 28U
½APSR_V_Msk (1UL << APSR_V_Pos)
ÎIPSR_ISR_Pos 0U
ÏIPSR_ISR_Msk (0x1FFUL )
æxPSR_N_Pos 31U
çxPSR_N_Msk (1UL << xPSR_N_Pos)
éxPSR_Z_Pos 30U
êxPSR_Z_Msk (1UL << xPSR_Z_Pos)
ìxPSR_C_Pos 29U
íxPSR_C_Msk (1UL << xPSR_C_Pos)
ïxPSR_V_Pos 28U
ðxPSR_V_Msk (1UL << xPSR_V_Pos)
òxPSR_T_Pos 24U
óxPSR_T_Msk (1UL << xPSR_T_Pos)
õxPSR_ISR_Pos 0U
öxPSR_ISR_Msk (0x1FFUL )
ˆCONTROL_SPSEL_Pos 1U
‰CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)
‹CONTROL_nPRIV_Pos 0U
ŒCONTROL_nPRIV_Msk (1UL )
ÈSCB_CPUID_IMPLEMENTER_Pos 24U
ÉSCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
ËSCB_CPUID_VARIANT_Pos 20U
ÌSCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
ÎSCB_CPUID_ARCHITECTURE_Pos 16U
ÏSCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
ÑSCB_CPUID_PARTNO_Pos 4U
ÒSCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
ÔSCB_CPUID_REVISION_Pos 0U
ÕSCB_CPUID_REVISION_Msk (0xFUL )
ØSCB_ICSR_NMIPENDSET_Pos 31U
ÙSCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)
ÛSCB_ICSR_PENDSVSET_Pos 28U
ÜSCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
ÞSCB_ICSR_PENDSVCLR_Pos 27U
ßSCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
áSCB_ICSR_PENDSTSET_Pos 26U
âSCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
äSCB_ICSR_PENDSTCLR_Pos 25U
åSCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
çSCB_ICSR_ISRPREEMPT_Pos 23U
èSCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
êSCB_ICSR_ISRPENDING_Pos 22U
ëSCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
íSCB_ICSR_VECTPENDING_Pos 12U
îSCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
ðSCB_ICSR_VECTACTIVE_Pos 0U
ñSCB_ICSR_VECTACTIVE_Msk (0x1FFUL )
õSCB_VTOR_TBLOFF_Pos 8U
öSCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)
úSCB_AIRCR_VECTKEY_Pos 16U
ûSCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
ýSCB_AIRCR_VECTKEYSTAT_Pos 16U
þSCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
€SCB_AIRCR_ENDIANESS_Pos 15U
SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
ƒSCB_AIRCR_SYSRESETREQ_Pos 2U
„SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
†SCB_AIRCR_VECTCLRACTIVE_Pos 1U
‡SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
ŠSCB_SCR_SEVONPEND_Pos 4U
‹SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
SCB_SCR_SLEEPDEEP_Pos 2U
ŽSCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
SCB_SCR_SLEEPONEXIT_Pos 1U
‘SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
”SCB_CCR_STKALIGN_Pos 9U
•SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)
—SCB_CCR_UNALIGN_TRP_Pos 3U
˜SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
›SCB_SHCSR_SVCALLPENDED_Pos 15U
œSCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
´SysTick_CTRL_COUNTFLAG_Pos 16U
µSysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
·SysTick_CTRL_CLKSOURCE_Pos 2U
¸SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
ºSysTick_CTRL_TICKINT_Pos 1U
»SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
½SysTick_CTRL_ENABLE_Pos 0U
¾SysTick_CTRL_ENABLE_Msk (1UL )
ÁSysTick_LOAD_RELOAD_Pos 0U
ÂSysTick_LOAD_RELOAD_Msk (0xFFFFFFUL )
ÅSysTick_VAL_CURRENT_Pos 0U
ÆSysTick_VAL_CURRENT_Msk (0xFFFFFFUL )
ÉSysTick_CALIB_NOREF_Pos 31U
ÊSysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)
ÌSysTick_CALIB_SKEW_Pos 30U
ÍSysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)
ÏSysTick_CALIB_TENMS_Pos 0U
ÐSysTick_CALIB_TENMS_Msk (0xFFFFFFUL )
éMPU_TYPE_IREGION_Pos 16U
êMPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
ìMPU_TYPE_DREGION_Pos 8U
íMPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
ïMPU_TYPE_SEPARATE_Pos 0U
ðMPU_TYPE_SEPARATE_Msk (1UL )
óMPU_CTRL_PRIVDEFENA_Pos 2U
ôMPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
öMPU_CTRL_HFNMIENA_Pos 1U
÷MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
ùMPU_CTRL_ENABLE_Pos 0U
úMPU_CTRL_ENABLE_Msk (1UL )
ýMPU_RNR_REGION_Pos 0U
þMPU_RNR_REGION_Msk (0xFFUL )
MPU_RBAR_ADDR_Pos 8U
‚MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)
„MPU_RBAR_VALID_Pos 4U
…MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos)
‡MPU_RBAR_REGION_Pos 0U
ˆMPU_RBAR_REGION_Msk (0xFUL )
‹MPU_RASR_ATTRS_Pos 16U
ŒMPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos)
ŽMPU_RASR_XN_Pos 28U
MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos)
‘MPU_RASR_AP_Pos 24U
’MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos)
”MPU_RASR_TEX_Pos 19U
•MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos)
—MPU_RASR_S_Pos 18U
˜MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos)
šMPU_RASR_C_Pos 17U
›MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos)
MPU_RASR_B_Pos 16U
žMPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos)
 MPU_RASR_SRD_Pos 8U
¡MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos)
£MPU_RASR_SIZE_Pos 1U
¤MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos)
¦MPU_RASR_ENABLE_Pos 0U
§MPU_RASR_ENABLE_Msk (1UL )
Ä_VAL2FLD(field,value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
Ì_FLD2VAL(field,value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
ÙSCS_BASE (0xE000E000UL)
ÚSysTick_BASE (SCS_BASE + 0x0010UL)
ÛNVIC_BASE (SCS_BASE + 0x0100UL)
ÜSCB_BASE (SCS_BASE + 0x0D00UL)
ÞSCB ((SCB_Type *) SCB_BASE )
ßSysTick ((SysTick_Type *) SysTick_BASE )
àNVIC ((NVIC_Type *) NVIC_BASE )
ãMPU_BASE (SCS_BASE + 0x0D90UL)
äMPU ((MPU_Type *) MPU_BASE )
‚_BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
ƒ_SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
„_IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) •
 




..\Core\Include\D:\Program Files\MDK5\ARM\ARMCC\Bin\..\include\core_cm0plus.h
stdint.hcore_cminstr.h
core_cmfunc.h


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..\Core\Include\core_cm0plus.hComponent: ARM Compiler 5.06 update 7 for Certification (build 960) Tool: ArmCC [4d365d]E:\GasFlowmeter\Internet_of_things_valve\SZV103\SZV103_FM33A0xxEV_SiZhu_jlcGai\KEIL_MDKARM*½!_reserved0v
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ÏNVIC_ClearPendingIRQ$QIRQn<Ÿ
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__stdio_h 
__ARMCLIB_VERSION 5060044
"_ARMABI __declspec(__nothrow)
%__STDIO_DECLS '__CLIBNS
-__CLIBNS <NULL
=NULL 0
g_SYS_OPEN 16
¥
stdin (&__CLIBNS __stdin)
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stdout (&__CLIBNS __stdout)
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¬
_IOFBF 0x100
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_IOLBF 0x200
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BUFSIZ (512)
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FOPEN_MAX _SYS_OPEN
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L_tmpnam FILENAME_MAX
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EOF (-1)
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SEEK_SET 0
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__STDIN_BUFSIZ (64)
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D:\Program Files\MDK5\ARM\ARMCC\Bin\..\include\stdio.h


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D:\Program Files\MDK5\ARM\ARMCC\Bin\..\include\stdio.hComponent: ARM Compiler 5.06 update 7 for Certification (build 960) Tool: ArmCC [4d365d]unsigned intunsigned long longPsize_t¦
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$FM33A0XXEV_H 
.__RCHF_INITIAL_CLOCK (8000000)
/__RCMF_CLOCK (2000000)
0__RCLP_CLOCK (32000)
1__XTLF_CLOCK (32768)
n__CM0_REV 0x0100
o__MPU_PRESENT 1
p__VTOR_PRESENT 1
q__NVIC_PRIO_BITS 2
r__Vendor_SysTickConfig 0uv
¿FLASH_BASE (( uint32_t)0x00000000)
ÀSRAM_BASE (( uint32_t)0x20000000)
ÁPERIPH_BASE (( uint32_t)0x40000000)
ÊPMU_BASE (PERIPH_BASE +0x00002000)
ËDBG_BASE (PERIPH_BASE +0x00000000)
ÌFLS_BASE (PERIPH_BASE +0x00001000)
ÍRMU_BASE (PERIPH_BASE +0x00002800)
ÎIWDT_BASE (PERIPH_BASE +0x00011400)
ÏWWDT_BASE (PERIPH_BASE +0x00011800)
ÐCMU_BASE (PERIPH_BASE +0x00002400)
ÑCDIF_BASE (PERIPH_BASE +0x0001E000)
ÒVRTC_BASE (PERIPH_BASE +0x0001F800)
ÓSVD_BASE (PERIPH_BASE +0x00012800)
ÔAES_BASE (PERIPH_BASE +0x00013800)
ÕPAE_BASE (PERIPH_BASE +0x00001400)
ÖHASH_BASE (PERIPH_BASE +0x00001800)
×RNG_BASE (PERIPH_BASE +0x00013C00)
ØCOMP_BASE (PERIPH_BASE +0x00015400)
ÙI2C0_BASE (PERIPH_BASE +0x00012400)
ÚI2C1_BASE (PERIPH_BASE +0x00015000)
ÛUARTIR_BASE (PERIPH_BASE +0x00017C00)
ÜUART0_BASE (PERIPH_BASE +0x00012000)
ÝUART1_BASE (PERIPH_BASE +0x00016800)
ÞUART2_BASE (PERIPH_BASE +0x00016C00)
ßUART3_BASE (PERIPH_BASE +0x00017000)
àUART4_BASE (PERIPH_BASE +0x00017400)
áUART5_BASE (PERIPH_BASE +0x00017800)
âLPUART0_BASE (PERIPH_BASE +0x00014000)
ãLPUART1_BASE (PERIPH_BASE +0x00014400)
äSPI0_BASE (PERIPH_BASE +0x00010400)
åSPI1_BASE (PERIPH_BASE +0x00010800)
æSPI2_BASE (PERIPH_BASE +0x00014800)
çSPI3_BASE (PERIPH_BASE +0x00014C00)
èSPI4_BASE (PERIPH_BASE +0x00016400)
éU7816_BASE (PERIPH_BASE +0x00011C00)
êQSPI_BASE (PERIPH_BASE +0x00000800)
ëDMA_BASE (PERIPH_BASE +0x00000400)
ìCRC_BASE (PERIPH_BASE +0x00010000)
íBT1_BASE (PERIPH_BASE +0x00013000)
îBT2_BASE (PERIPH_BASE +0x00013044)
ïET1_BASE (PERIPH_BASE +0x00013090)
ðET2_BASE (PERIPH_BASE +0x000130B0)
ñET3_BASE (PERIPH_BASE +0x000130D0)
òET4_BASE (PERIPH_BASE +0x000130F0)
óETCNT_BASE (PERIPH_BASE +0x00013110)
ôBSTIM_BASE (PERIPH_BASE +0x00016000)
õLPTIM_BASE (PERIPH_BASE +0x00013400)
öRTC_BASE (PERIPH_BASE +0x00011000)
÷LCD_BASE (PERIPH_BASE +0x00010C00)
øADC_BASE (PERIPH_BASE +0x0001FA00)
ùCIC_BASE (PERIPH_BASE +0x00015C00)
úGPIOA_BASE (PERIPH_BASE +0x00000C00)
ûGPIOB_BASE (PERIPH_BASE +0x00000C40)
üGPIOC_BASE (PERIPH_BASE +0x00000C80)
ýGPIOD_BASE (PERIPH_BASE +0x00000CC0)
þGPIOE_BASE (PERIPH_BASE +0x00000D00)
ÿGPIOF_BASE (PERIPH_BASE +0x00000D40)
€GPIOG_BASE (PERIPH_BASE +0x00000D80)
GPIOH_BASE (PERIPH_BASE +0x0001FC00)
‚GPIO_BASE (PERIPH_BASE +0x00000DC0)
ˆPMU ((PMU_Type *) PMU_BASE )
‰DBG ((DBG_Type *) DBG_BASE )
ŠFLS ((FLS_Type *) FLS_BASE )
‹RMU ((RMU_Type *) RMU_BASE )
ŒIWDT ((IWDT_Type *) IWDT_BASE )
WWDT ((WWDT_Type *) WWDT_BASE )
ŽCMU ((CMU_Type *) CMU_BASE )
CDIF ((CDIF_Type *) CDIF_BASE )
VRTC ((VRTC_Type *) VRTC_BASE )
‘SVD ((SVD_Type *) SVD_BASE )
’AES ((AES_Type *) AES_BASE )
“PAE ((PAE_Type *) PAE_BASE )
”HASH ((HASH_Type *) HASH_BASE )
•RNG ((RNG_Type *) RNG_BASE )
–COMP ((COMP_Type *) COMP_BASE )
—I2C0 ((I2C_Type *) I2C0_BASE )
˜I2C1 ((I2C_Type *) I2C1_BASE )
™UARTIR ((UARTIR_Type *) UARTIR_BASE )
šUART0 ((UART_Type *) UART0_BASE )
›UART1 ((UART_Type *) UART1_BASE )
œUART2 ((UART_Type *) UART2_BASE )
UART3 ((UART_Type *) UART3_BASE )
žUART4 ((UART_Type *) UART4_BASE )
ŸUART5 ((UART_Type *) UART5_BASE )
 LPUART0 ((LPUART_Type *) LPUART0_BASE )
¡LPUART1 ((LPUART_Type *) LPUART1_BASE )
¢SPI0 ((SPI_Type *) SPI0_BASE )
£SPI1 ((SPI_Type *) SPI1_BASE )
¤SPI2 ((SPI_Type *) SPI2_BASE )
¥SPI3 ((SPI_Type *) SPI3_BASE )
¦SPI4 ((SPI_Type *) SPI4_BASE )
§U7816 ((U7816_Type *) U7816_BASE )
¨QSPI ((QSPI_Type *) QSPI_BASE )
©DMA ((DMA_Type *) DMA_BASE )
ªCRC ((CRC_Type *) CRC_BASE )
«BT1 ((BT_Type *) BT1_BASE )
¬BT2 ((BT_Type *) BT2_BASE )
­ET1 ((ET_Type *) ET1_BASE )
®ET2 ((ET_Type *) ET2_BASE )
¯ET3 ((ET_Type *) ET3_BASE )
°ET4 ((ET_Type *) ET4_BASE )
±ETCNT ((ETCNT_Type *) ETCNT_BASE )
²BSTIM ((BSTIM_Type *) BSTIM_BASE )
³LPTIM ((LPTIM_Type *) LPTIM_BASE )
´RTC ((RTC_Type *) RTC_BASE )
µLCD ((LCD_Type *) LCD_BASE )
¶ADC ((ADC_Type *) ADC_BASE )
·CIC ((CIC_Type *) CIC_BASE )
¸GPIOA ((GPIO_Type *) GPIOA_BASE )
¹GPIOB ((GPIO_Type *) GPIOB_BASE )
ºGPIOC ((GPIO_Type *) GPIOC_BASE )
»GPIOD ((GPIO_Type *) GPIOD_BASE )
¼GPIOE ((GPIO_Type *) GPIOE_BASE )
½GPIOF ((GPIO_Type *) GPIOF_BASE )
¾GPIOG ((GPIO_Type *) GPIOG_BASE )
¿GPIOH ((GPIOH_Type *) GPIOH_BASE )
ÀGPIO ((GPIO_COMMON_Type *) GPIO_BASE )h]
 




..\Core\Include\FM33A0XXEV.h
core_cm0plus.h
system_FM33A0XXEV.h


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..\Core\Include\FM33A0XXEV.hComponent: ARM Compiler 5.06 update 7 for Certification (build 960) Tool: ArmCC [4d365d]E:\GasFlowmeter\Internet_of_things_valve\SZV103\SZV103_FM33A0xxEV_SiZhu_jlcGai\KEIL_MDKARMü

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UART2_IRQnUART3_IRQnUART4_IRQn UART5_IRQnU7816_IRQnLPUART0_IRQnI2Cx_IRQnRSV_IRQnCRYPTO_IRQnLPTIM_IRQnDMA_IRQnWKUPx_IRQnCOMP_IRQnBTx_IRQnQSPI_IRQnETx_IRQnBSTIM_IRQnSPI3_IRQnSPI4_IRQnGPIO_IRQnLPUART1_IRQnPIRQn_Typep

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(SYSTEM_FM33A0XXEV_H 234
O__SYSTEM_CLOCK (8000000)
PDELAY_US (__SYSTEM_CLOCK/1000000)
QDELAY_MS (__SYSTEM_CLOCK/1000)
TDo_DelayStart() { uint32_t LastTick = SysTick->VAL; do {
WWhile_DelayMsEnd(Count) }while(((LastTick - SysTick->VAL)&0xFFFFFF)<DELAY_MS*Count); }
ZWhile_DelayUsEnd(Count) }while(((LastTick - SysTick->VAL)&0xFFFFFF)<DELAY_US*Count); }œ’
 




..\Core\Include\D:\Program Files\MDK5\ARM\ARMCC\Bin\..\include\system_FM33A0XXEV.h
stdint.hstdio.hFM33A0XXEV.h




..\Core\Include\system_FM33A0XXEV.hComponent: ARM Compiler 5.06 update 7 for Certification (build 960) Tool: ArmCC [4d365d]E:\GasFlowmeter\Internet_of_things_valve\SZV103\SZV103_FM33A0xxEV_SiZhu_jlcGai\KEIL_MDKARMqSystemCoreClockv


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îSystemCoreClock
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__FM33A0XXEV_QSPI_H 
)QSPI_CR_PRESCALER_Pos 24
*QSPI_CR_PRESCALER_Msk (0xffU << QSPI_CR_PRESCALER_Pos)
,QSPI_CR_PMM_Pos 23
/QSPI_CR_PMM_Msk (0x1U << QSPI_CR_PMM_Pos)
0QSPI_CR_PMM_AND (0x0U << QSPI_CR_PMM_Pos)
1QSPI_CR_PMM_OR (0x1U << QSPI_CR_PMM_Pos)
3QSPI_CR_TOIE_Pos 20
6QSPI_CR_TOIE_Msk (0x1U << QSPI_CR_TOIE_Pos)
:QSPI_CR_SMIE_Pos 19
=QSPI_CR_SMIE_Msk (0x1U << QSPI_CR_SMIE_Pos)
AQSPI_CR_FTIE_Pos 18
DQSPI_CR_FTIE_Msk (0x1U << QSPI_CR_FTIE_Pos)
HQSPI_CR_TCIE_Pos 17
KQSPI_CR_TCIE_Msk (0x1U << QSPI_CR_TCIE_Pos)
OQSPI_CR_TEIE_Pos 16
RQSPI_CR_TEIE_Msk (0x1U << QSPI_CR_TEIE_Pos)
VQSPI_CR_FIFOTHR_Pos 8
aQSPI_CR_FIFOTHR_Msk (0xfU << QSPI_CR_FIFOTHR_Pos)
bQSPI_CR_FIFOTHR_1 (0x0U << QSPI_CR_FIFOTHR_Pos)
cQSPI_CR_FIFOTHR_2 (0x1U << QSPI_CR_FIFOTHR_Pos)
dQSPI_CR_FIFOTHR_3 (0x2U << QSPI_CR_FIFOTHR_Pos)
eQSPI_CR_FIFOTHR_4 (0x3U << QSPI_CR_FIFOTHR_Pos)
fQSPI_CR_FIFOTHR_5 (0x4U << QSPI_CR_FIFOTHR_Pos)
gQSPI_CR_FIFOTHR_6 (0x5U << QSPI_CR_FIFOTHR_Pos)
hQSPI_CR_FIFOTHR_7 (0x6U << QSPI_CR_FIFOTHR_Pos)
iQSPI_CR_FIFOTHR_8 (0x7U << QSPI_CR_FIFOTHR_Pos)
jQSPI_CR_FIFOTHR_9 (0x8U << QSPI_CR_FIFOTHR_Pos)
kQSPI_CR_FIFOTHR_10 (0x9U << QSPI_CR_FIFOTHR_Pos)
lQSPI_CR_FIFOTHR_11 (0x10U << QSPI_CR_FIFOTHR_Pos)
mQSPI_CR_FIFOTHR_12 (0x11U << QSPI_CR_FIFOTHR_Pos)
nQSPI_CR_FIFOTHR_13 (0x12U << QSPI_CR_FIFOTHR_Pos)
oQSPI_CR_FIFOTHR_14 (0x13U << QSPI_CR_FIFOTHR_Pos)
pQSPI_CR_FIFOTHR_15 (0x14U << QSPI_CR_FIFOTHR_Pos)
qQSPI_CR_FIFOTHR_16 (0x15U << QSPI_CR_FIFOTHR_Pos)
sQSPI_CR_SSHFT_Pos 4
vQSPI_CR_SSHFT_Msk (0x1U << QSPI_CR_SSHFT_Pos)
zQSPI_CR_TCEN_Pos 3
~QSPI_CR_TCEN_Msk (0x1U << QSPI_CR_TCEN_Pos)
‚
QSPI_CR_DMAEN_Pos 2
…
QSPI_CR_DMAEN_Msk (0x1U << QSPI_CR_DMAEN_Pos)
‰
QSPI_CR_ABORT_Pos 1
Š
QSPI_CR_ABORT_Msk (0x1U << QSPI_CR_ABORT_Pos)
Œ
QSPI_CR_EN_Pos 0

QSPI_CR_EN_Msk (0x1U << QSPI_CR_EN_Pos)
“
QSPI_CFG_CSHT_Pos 8
˜
QSPI_CFG_CSHT_Msk (0x7U << QSPI_CFG_CSHT_Pos)
™
QSPI_CFG_CSHT_1CYCLE (0x0U << QSPI_CFG_CSHT_Pos)
š
QSPI_CFG_CSHT_2CYCLES (0x1U << QSPI_CFG_CSHT_Pos)
›
QSPI_CFG_CSHT_3CYCLES (0x2U << QSPI_CFG_CSHT_Pos)
œ
QSPI_CFG_CSHT_4CYCLES (0x3U << QSPI_CFG_CSHT_Pos)

QSPI_CFG_CSHT_5CYCLES (0x4U << QSPI_CFG_CSHT_Pos)
ž
QSPI_CFG_CSHT_6CYCLES (0x5U << QSPI_CFG_CSHT_Pos)
Ÿ
QSPI_CFG_CSHT_7CYCLES (0x6U << QSPI_CFG_CSHT_Pos)
 
QSPI_CFG_CSHT_8CYCLES (0x7U << QSPI_CFG_CSHT_Pos)
¢
QSPI_CFG_CKMODE_Pos 0
¥
QSPI_CFG_CKMODE_Msk (0x1U << QSPI_CFG_CKMODE_Pos)
¦
QSPI_CFG_CKMODE_MODE0 (0x0U << QSPI_CFG_CKMODE_Pos)
§
QSPI_CFG_CKMODE_MODE3 (0x1U << QSPI_CFG_CKMODE_Pos)
©
QSPI_SR_FIFOLVL_Pos 8
¬
QSPI_SR_FIFOLVL_Msk (0x1fU << QSPI_SR_FIFOLVL_Pos)
®
QSPI_SR_BUSY_Pos 5
¯
QSPI_SR_BUSY_Msk (0x1U << QSPI_SR_BUSY_Pos)
±
QSPI_SR_TOF_Pos 4
²
QSPI_SR_TOF_Msk (0x1U << QSPI_SR_TOF_Pos)
´
QSPI_SR_SMF_Pos 3
µ
QSPI_SR_SMF_Msk (0x1U << QSPI_SR_SMF_Pos)
·
QSPI_SR_FTF_Pos 2
¹
QSPI_SR_FTF_Msk (0x1U << QSPI_SR_FTF_Pos)
»
QSPI_SR_TCF_Pos 1
¼
QSPI_SR_TCF_Msk (0x1U << QSPI_SR_TCF_Pos)
¾
QSPI_DATALEN_QSPI_DATALEN_Pos 0
¿
QSPI_DATALEN_QSPI_DATALEN_Msk (0xffffffffU << QSPI_DATALEN_QSPI_DATALEN_Pos)
Á
QSPI_CCR_CRM_Pos 28
Ä
QSPI_CCR_CRM_Msk (0x1U << QSPI_CCR_CRM_Pos)
Å
QSPI_CCR_CRM_ALWAYS (0x0U << QSPI_CCR_CRM_Pos)
Æ
QSPI_CCR_CRM_ONLY (0x1U << QSPI_CCR_CRM_Pos)
È
QSPI_CCR_OPMODE_Pos 26
Í
QSPI_CCR_OPMODE_Msk (0x3U << QSPI_CCR_OPMODE_Pos)
Î
QSPI_CCR_OPMODE_WRITE (0x0U << QSPI_CCR_OPMODE_Pos)
Ï
QSPI_CCR_OPMODE_READ (0x1U << QSPI_CCR_OPMODE_Pos)
Ð
QSPI_CCR_OPMODE_QUERY (0x2U << QSPI_CCR_OPMODE_Pos)
Ñ
QSPI_CCR_OPMODE_MAP (0x3U << QSPI_CCR_OPMODE_Pos)
Ó
QSPI_CCR_DMODE_Pos 24
Ø
QSPI_CCR_DMODE_Msk (0x3U << QSPI_CCR_DMODE_Pos)
Ù
QSPI_CCR_DMODE_NONE (0x0U << QSPI_CCR_DMODE_Pos)
Ú
QSPI_CCR_DMODE_SINGLE (0x1U << QSPI_CCR_DMODE_Pos)
Û
QSPI_CCR_DMODE_DOUBLE (0x2U << QSPI_CCR_DMODE_Pos)
Ü
QSPI_CCR_DMODE_FOUR (0x3U << QSPI_CCR_DMODE_Pos)
Þ
QSPI_CCR_DUMCYC_Pos 18
ß
QSPI_CCR_DUMCYC_Msk (0x1fU << QSPI_CCR_DUMCYC_Pos)
á
QSPI_CCR_ABSIZE_Pos 16
æ
QSPI_CCR_ABSIZE_Msk (0x3U << QSPI_CCR_ABSIZE_Pos)
ç
QSPI_CCR_ABSIZE_8BITS (0x0U << QSPI_CCR_ABSIZE_Pos)
è
QSPI_CCR_ABSIZE_16BITS (0x1U << QSPI_CCR_ABSIZE_Pos)
é
QSPI_CCR_ABSIZE_24BITS (0x2U << QSPI_CCR_ABSIZE_Pos)
ê
QSPI_CCR_ABSIZE_32BITS (0x3U << QSPI_CCR_ABSIZE_Pos)
ì
QSPI_CCR_ABMODE_Pos 14
ñ
QSPI_CCR_ABMODE_Msk (0x3U << QSPI_CCR_ABMODE_Pos)
ò
QSPI_CCR_ABMODE_NONE (0x0U << QSPI_CCR_ABMODE_Pos)
ó
QSPI_CCR_ABMODE_SINGLE (0x1U << QSPI_CCR_ABMODE_Pos)
ô
QSPI_CCR_ABMODE_DOUBLE (0x2U << QSPI_CCR_ABMODE_Pos)
õ
QSPI_CCR_ABMODE_FOUR (0x3U << QSPI_CCR_ABMODE_Pos)
÷
QSPI_CCR_ADSIZE_Pos 12
ü
QSPI_CCR_ADSIZE_Msk (0x3U << QSPI_CCR_ADSIZE_Pos)
ý
QSPI_CCR_ADSIZE_8BITS (0x0U << QSPI_CCR_ADSIZE_Pos)
þ
QSPI_CCR_ADSIZE_16BITS (0x1U << QSPI_CCR_ADSIZE_Pos)
ÿ
QSPI_CCR_ADSIZE_24BITS (0x2U << QSPI_CCR_ADSIZE_Pos)
€QSPI_CCR_ADSIZE_32BITS (0x3U << QSPI_CCR_ADSIZE_Pos)
‚QSPI_CCR_ADMODE_Pos 10
‡QSPI_CCR_ADMODE_Msk (0x3U << QSPI_CCR_ADMODE_Pos)
ˆQSPI_CCR_ADMODE_NONE (0x0U << QSPI_CCR_ADMODE_Pos)
‰QSPI_CCR_ADMODE_SINGLE (0x1U << QSPI_CCR_ADMODE_Pos)
ŠQSPI_CCR_ADMODE_DOUBLE (0x2U << QSPI_CCR_ADMODE_Pos)
‹QSPI_CCR_ADMODE_FOUR (0x3U << QSPI_CCR_ADMODE_Pos)
QSPI_CCR_IMODE_Pos 8
’QSPI_CCR_IMODE_Msk (0x3U << QSPI_CCR_IMODE_Pos)
“QSPI_CCR_IMODE_NONE (0x0U << QSPI_CCR_IMODE_Pos)
”QSPI_CCR_IMODE_SINGLE (0x1U << QSPI_CCR_IMODE_Pos)
•QSPI_CCR_IMODE_DOUBLE (0x2U << QSPI_CCR_IMODE_Pos)
–QSPI_CCR_IMODE_FOUR (0x3U << QSPI_CCR_IMODE_Pos)
˜QSPI_CCR_INSTRUCTION_Pos 0
™QSPI_CCR_INSTRUCTION_Msk (0xffU << QSPI_CCR_INSTRUCTION_Pos)
›QSPI_ADDR_QSPI_ADDR_Pos 0
œQSPI_ADDR_QSPI_ADDR_Msk (0xffffffffU << QSPI_ADDR_QSPI_ADDR_Pos)
žQSPI_ABR_QSPI_ABR_Pos 0
ŸQSPI_ABR_QSPI_ABR_Msk (0xffffffffU << QSPI_ABR_QSPI_ABR_Pos)
¡QSPI_DR_QSPI_DATA_Pos 0
¥QSPI_DR_QSPI_DATA_Msk (0xffffffffU << QSPI_DR_QSPI_DATA_Pos)
§QSPI_SMSK_QSPI_SMSK_Pos 0
¨QSPI_SMSK_QSPI_SMSK_Msk (0xffffffffU << QSPI_SMSK_QSPI_SMSK_Pos)
ªQSPI_SMAT_QSPI_SMAT_Pos 0
¬QSPI_SMAT_QSPI_SMAT_Msk (0xffffffffU << QSPI_SMAT_QSPI_SMAT_Pos)
®QSPI_PITV_QSPI_PITV_Pos 0
¯QSPI_PITV_QSPI_PITV_Msk (0xffffU << QSPI_PITV_QSPI_PITV_Pos)
±QSPI_TO_QSPI_TO_Pos 0
³QSPI_TO_QSPI_TO_Msk (0xffffU << QSPI_TO_QSPI_TO_Pos)
µQSPI_CCR_DUMCYC_SET(value) ((value << QSPI_CCR_DUMCYC_Pos) & QSPI_CCR_DUMCYC_Msk)
¶QSPI_CCR_DUMCYC_GET(value) ((value >> QSPI_CCR_DUMCYC_Pos) & QSPI_CCR_DUMCYC_Msk)
·QSPI_CCR_INSTRUCTION_SET(value) ((value << QSPI_CCR_INSTRUCTION_Pos) & QSPI_CCR_INSTRUCTION_Msk)
¸QSPI_CCR_INSTRUCTION_GET(value) ((value >> QSPI_CCR_INSTRUCTION_Pos) & QSPI_CCR_INSTRUCTION_Msk)`U
 




..\Drivers\..\Core\Include\fm33a0xxev_qspi.h
FM33A0XXEV.h

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..\Drivers\fm33a0xxev_qspi.hComponent: ARM Compiler 5.06 update 7 for Certification (build 960) Tool: ArmCC [4d365d]E:\GasFlowmeter\Internet_of_things_valve\SZV103\SZV103_FM33A0xxEV_SiZhu_jlcGai\KEIL_MDKARM*É(Instructionv
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#$PQSPI_CmdTypeDefç
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__FM33A0XXEV_RMU_H 
RMU_PDRCR_PDRCFG_Pos 1
RMU_PDRCR_PDRCFG_Msk (0x3U << RMU_PDRCR_PDRCFG_Pos)
RMU_PDRCR_PDRCFG_1P5V (0x0U << RMU_PDRCR_PDRCFG_Pos)
RMU_PDRCR_PDRCFG_1P25V (0x1U << RMU_PDRCR_PDRCFG_Pos)
RMU_PDRCR_PDRCFG_1P35V (0x2U << RMU_PDRCR_PDRCFG_Pos)
RMU_PDRCR_PDRCFG_1P4V (0x3U << RMU_PDRCR_PDRCFG_Pos)
 RMU_PDRCR_PDREN_Pos 0
!RMU_PDRCR_PDREN_Msk (0x1U << RMU_PDRCR_PDREN_Pos)
%RMU_BORCR_BOR_PDRCFG_Pos 1
&RMU_BORCR_BOR_PDRCFG_Msk (0x3U << RMU_BORCR_BOR_PDRCFG_Pos)
'RMU_BORCR_BOR_PDRCFG_1P7V (0x0U << RMU_BORCR_BOR_PDRCFG_Pos)
(RMU_BORCR_BOR_PDRCFG_1P6V (0x1U << RMU_BORCR_BOR_PDRCFG_Pos)
)RMU_BORCR_BOR_PDRCFG_1P65V (0x2U << RMU_BORCR_BOR_PDRCFG_Pos)
*RMU_BORCR_BOR_PDRCFG_1P75V (0x3U << RMU_BORCR_BOR_PDRCFG_Pos)
,RMU_BORCR_OFF_BOR_Pos 0
-RMU_BORCR_OFF_BOR_Msk (0x1U << RMU_BORCR_OFF_BOR_Pos)
1RMU_RSTCFGR_LKUPRST_EN_Pos 1
2RMU_RSTCFGR_LKUPRST_EN_Msk (0x1U << RMU_RSTCFGR_LKUPRST_EN_Pos)
6RMU_SOFTRST_SOFTRST_Pos 0
7RMU_SOFTRST_SOFTRST_Msk (0xffffffffU << RMU_SOFTRST_SOFTRST_Pos)
9RMU_RSR_NRSTN_FLAG_Pos 11
:RMU_RSR_NRSTN_FLAG_Msk (0x1U << RMU_RSR_NRSTN_FLAG_Pos)
<RMU_RSR_TESTN_FLAG_Pos 10
=RMU_RSR_TESTN_FLAG_Msk (0x1U << RMU_RSR_TESTN_FLAG_Pos)
?RMU_RSR_PORN_FLAG_Pos 9
@RMU_RSR_PORN_FLAG_Msk (0x1U << RMU_RSR_PORN_FLAG_Pos)
BRMU_RSR_PDRN_FLAG_Pos 8
CRMU_RSR_PDRN_FLAG_Msk (0x1U << RMU_RSR_PDRN_FLAG_Pos)
ERMU_RSR_SOFTN_FLAG_Pos 5
FRMU_RSR_SOFTN_FLAG_Msk (0x1U << RMU_RSR_SOFTN_FLAG_Pos)
HRMU_RSR_IWDTN_FLAG_Pos 4
IRMU_RSR_IWDTN_FLAG_Msk (0x1U << RMU_RSR_IWDTN_FLAG_Pos)
KRMU_RSR_WWDTN_FLAG_Pos 2
LRMU_RSR_WWDTN_FLAG_Msk (0x1U << RMU_RSR_WWDTN_FLAG_Pos)
NRMU_RSR_LKUPN_FLAG_Pos 1
ORMU_RSR_LKUPN_FLAG_Msk (0x1U << RMU_RSR_LKUPN_FLAG_Pos)
QRMU_RSR_NVICN_FLAG_Pos 0
RRMU_RSR_NVICN_FLAG_Msk (0x1U << RMU_RSR_NVICN_FLAG_Pos)
TRMU_PRSTEN_PERHRSTEN_Pos 0
URMU_PRSTEN_PERHRSTEN_Msk (0xffffffffU << RMU_PRSTEN_PERHRSTEN_Pos)
WRMU_AHBRST_HASHRST_Pos 2
XRMU_AHBRST_HASHRST_Msk (0x1U << RMU_AHBRST_HASHRST_Pos)
\RMU_AHBRST_PAERST_Pos 1
]RMU_AHBRST_PAERST_Msk (0x1U << RMU_AHBRST_PAERST_Pos)
aRMU_AHBRST_DMARST_Pos 0
bRMU_AHBRST_DMARST_Msk (0x1U << RMU_AHBRST_DMARST_Pos)
fRMU_APBRST1_UART5RST_Pos 31
gRMU_APBRST1_UART5RST_Msk (0x1U << RMU_APBRST1_UART5RST_Pos)
kRMU_APBRST1_UART4RST_Pos 30
lRMU_APBRST1_UART4RST_Msk (0x1U << RMU_APBRST1_UART4RST_Pos)
pRMU_APBRST1_UART3RST_Pos 29
qRMU_APBRST1_UART3RST_Msk (0x1U << RMU_APBRST1_UART3RST_Pos)
uRMU_APBRST1_UART2RST_Pos 28
vRMU_APBRST1_UART2RST_Msk (0x1U << RMU_APBRST1_UART2RST_Pos)
zRMU_APBRST1_TIMARST_Pos 23
{RMU_APBRST1_TIMARST_Msk (0x1U << RMU_APBRST1_TIMARST_Pos)
RMU_APBRST1_LCDRST_Pos 16
€
RMU_APBRST1_LCDRST_Msk (0x1U << RMU_APBRST1_LCDRST_Pos)
„
RMU_APBRST1_U7816RST_Pos 14
…
RMU_APBRST1_U7816RST_Msk (0x1U << RMU_APBRST1_U7816RST_Pos)
‰
RMU_APBRST1_SPI4RST_Pos 12
Š
RMU_APBRST1_SPI4RST_Msk (0x1U << RMU_APBRST1_SPI4RST_Pos)
Ž
RMU_APBRST1_SPI3RST_Pos 11

RMU_APBRST1_SPI3RST_Msk (0x1U << RMU_APBRST1_SPI3RST_Pos)
“
RMU_APBRST1_SPI2RST_Pos 10
”
RMU_APBRST1_SPI2RST_Msk (0x1U << RMU_APBRST1_SPI2RST_Pos)
˜
RMU_APBRST1_LPUART0RST_Pos 6
™
RMU_APBRST1_LPUART0RST_Msk (0x1U << RMU_APBRST1_LPUART0RST_Pos)

RMU_APBRST1_I2C1RST_Pos 3
ž
RMU_APBRST1_I2C1RST_Msk (0x1U << RMU_APBRST1_I2C1RST_Pos)
¢
RMU_APBRST1_LPTRST_Pos 0
£
RMU_APBRST1_LPTRST_Msk (0x1U << RMU_APBRST1_LPTRST_Pos)
§
RMU_APBRST2_UART1RST_Pos 31
¨
RMU_APBRST2_UART1RST_Msk (0x1U << RMU_APBRST2_UART1RST_Pos)
¬
RMU_APBRST2_UART0RST_Pos 30
­
RMU_APBRST2_UART0RST_Msk (0x1U << RMU_APBRST2_UART0RST_Pos)
±
RMU_APBRST2_UARTIRRST_Pos 29
²
RMU_APBRST2_UARTIRRST_Msk (0x1U << RMU_APBRST2_UARTIRRST_Pos)
¶
RMU_APBRST2_BSTRST_Pos 28
·
RMU_APBRST2_BSTRST_Msk (0x1U << RMU_APBRST2_BSTRST_Pos)
»
RMU_APBRST2_CICRST_Pos 24
¼
RMU_APBRST2_CICRST_Msk (0x1U << RMU_APBRST2_CICRST_Pos)
À
RMU_APBRST2_ADCRST_Pos 23
Á
RMU_APBRST2_ADCRST_Msk (0x1U << RMU_APBRST2_ADCRST_Pos)
Å
RMU_APBRST2_AESRST_Pos 18
Æ
RMU_APBRST2_AESRST_Msk (0x1U << RMU_APBRST2_AESRST_Pos)
Ê
RMU_APBRST2_CRCRST_Pos 17
Ë
RMU_APBRST2_CRCRST_Msk (0x1U << RMU_APBRST2_CRCRST_Pos)
Ï
RMU_APBRST2_RNGRST_Pos 16
Ð
RMU_APBRST2_RNGRST_Msk (0x1U << RMU_APBRST2_RNGRST_Pos)
Ô
RMU_APBRST2_SPI1RST_Pos 9
Õ
RMU_APBRST2_SPI1RST_Msk (0x1U << RMU_APBRST2_SPI1RST_Pos)
Ù
RMU_APBRST2_SPI0RST_Pos 8
Ú
RMU_APBRST2_SPI0RST_Msk (0x1U << RMU_APBRST2_SPI0RST_Pos)
Þ
RMU_APBRST2_LPUART1RST_Pos 7
ß
RMU_APBRST2_LPUART1RST_Msk (0x1U << RMU_APBRST2_LPUART1RST_Pos)
ã
RMU_APBRST2_I2C0RST_Pos 4
ä
RMU_APBRST2_I2C0RST_Msk (0x1U << RMU_APBRST2_I2C0RST_Pos)
è
RMU_APBRST2_SVDRST_Pos 1
é
RMU_APBRST2_SVDRST_Msk (0x1U << RMU_APBRST2_SVDRST_Pos)
í
RMU_APBRST2_COMPRST_Pos 0
î
RMU_APBRST2_COMPRST_Msk (0x1U << RMU_APBRST2_COMPRST_Pos)`T
 




..\Drivers\..\Core\Include\fm33a0xxev_rmu.h
FM33A0XXEV.h

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..\Drivers\fm33a0xxev_rmu.hComponent: ARM Compiler 5.06 update 7 for Certification (build 960) Tool: ArmCC [4d365d]E:\GasFlowmeter\Internet_of_things_valve\SZV103\SZV103_FM33A0xxEV_SiZhu_jlcGai\KEIL_MDKARM
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..\Drivers\..\Drivers\fm33a0xxev_qspi.cfm33a0xxev_qspi.h
fm33a0xxev_rmu.h


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Input Comments:p5eb8-3Component: ARM Compiler 5.06 update 7 for Certification (build 960) Tool: armasm [4d35fa]armasm --debug --diag_suppress=9931,9931,1602,1073 --cpu=Cortex-M0 --fpu=SoftVFP --apcs=/interwork/interwork --no_divide fm33a0xxev_qspi.oComponent: ARM Compiler 5.06 update 7 for Certification (build 960) Tool: ArmCC [4d365d]ArmCC --c99 --split_sections --debug -c --gnu -o.\objects\fm33a0xxev_qspi.o --depend=.\objects\fm33a0xxev_qspi.d --cpu=Cortex-M0 --apcs=interwork -O0 --diag_suppress=9931 -I..\Core -I..\Drivers -I..\Core\Include -I..\Hardware -I.\RTE\Device -I..\Hardware\CLOCK -I..\Hardware\DELAY -I..\Hardware\GPIO -I..\Hardware\UART -I..\Hardware\TIM -I..\Function\KEY -I..\Hardware\EXTI -I..\Hardware\RTC -I..\Hardware\ADC -I..\Hardware\I2C -I..\Function\LCD -I..\Function\EXTERN_RTC -I..\Hardware\SPI -I..\Function\GPRS -I..\Function\HARDWARE_WATCHDOG -I..\Function\IR_NEC -I..\Function\MEASURE_INTERACTION -I..\Function\POWER_MANAGE -I..\Function\STORAGE -I..\Function\UPPER_COMPUTER -I..\Function\VALVE -I..\Soft -I..\MultiButton -I..\USMART -I..\Hardware\DMA -I..\Hardware\ON_CHIP_FLASH -I..\Hardware\SVD -I..\Function\OFF_CHIP_FLASH -I..\Hardware\CRC -I..\Function\BOOTLOADER_IAP -I..\Hardware\COMP -I..\CmBackTrace -I..\Function\E2P -I.\RTE\_UFG220_FM33A0_MainSystem -I"D:\Program Files\MDK5\Packs\Keil\FM33A0XXEV_DFP\0.0.4\Device\Include" -D__MICROLIB -D__UVISION_VERSION=538 -D_RTE_ -D_RTE_ -D__VTOR_PRESENT --omf_browse=.\objects\fm33a0xxev_qspi.crf ..\Drivers\fm33a0xxev_qspi.cl2
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