金礼聪移植周巍修改后首次提交

jinlicong

2024-04-18 de0f427ee76ab84d3afb22c92a2b065b1ce06d3e

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..\\Hardware\\DELAY\\delay.cComponent: ARM Compiler 5.06 update 7 for Certification (build 960) Tool: armasm [4d35fa]E:\GasFlowmeter\Internet_of_things_valve\SZV103\SZV103_FM33A0xxEV_SiZhu_jlcGai\KEIL_MDKARM__asm___7_delay_c_f6a9c549____REV16P9

 




..\\Core\\Include\\core_cminstr.h
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..\\Hardware\\DELAY\\delay.cComponent: ARM Compiler 5.06 update 7 for Certification (build 960) Tool: armasm [4d35fa]E:\GasFlowmeter\Internet_of_things_valve\SZV103\SZV103_FM33A0xxEV_SiZhu_jlcGai\KEIL_MDKARM__asm___7_delay_c_f6a9c549____REVSHP9

 




..\\Core\\Include\\core_cminstr.h
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..\Hardware\DELAY\delay.cComponent: ARM Compiler 5.06 update 7 for Certification (build 960) Tool: ArmCC [4d365d]E:\GasFlowmeter\Internet_of_things_valve\SZV103\SZV103_FM33A0xxEV_SiZhu_jlcGai\KEIL_MDKARM
..\Hardware\DELAY\delay.cComponent: ARM Compiler 5.06 update 7 for Certification (build 960) Tool: ArmCC [4d365d]E:\GasFlowmeter\Internet_of_things_valve\SZV103\SZV103_FM33A0xxEV_SiZhu_jlcGai\KEIL_MDKARMYfac_usW
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..\Hardware\DELAY\delay.cComponent: ARM Compiler 5.06 update 7 for Certification (build 960) Tool: ArmCC [4d365d]E:\GasFlowmeter\Internet_of_things_valve\SZV103\SZV103_FM33A0xxEV_SiZhu_jlcGai\KEIL_MDKARM8?›
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..\Hardware\DELAY\delay.cComponent: ARM Compiler 5.06 update 7 for Certification (build 960) Tool: ArmCC [4d365d]E:\GasFlowmeter\Internet_of_things_valve\SZV103\SZV103_FM33A0xxEV_SiZhu_jlcGai\KEIL_MDKARMF? 
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..\Hardware\DELAY\delay.cComponent: ARM Compiler 5.06 update 7 for Certification (build 960) Tool: ArmCC [4d365d]E:\GasFlowmeter\Internet_of_things_valve\SZV103\SZV103_FM33A0xxEV_SiZhu_jlcGai\KEIL_MDKARMF? 
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__DATE__ "Apr 16 2024"
__TIME__ "19:58:48"
__STDC__ 1
__STDC_VERSION__ 199901L
__STDC_HOSTED__ 1
__STDC_ISO_10646__ 200607
__EDG__ 1
__EDG_VERSION__ 407
__EDG_SIZE_TYPE__ unsigned int
__EDG_PTRDIFF_TYPE__ int
__GNUC__ 4
__GNUC_STDC_INLINE__ 1
__GNUC_MINOR__ 7
__GNUC_PATCHLEVEL__ 0
__VERSION__ "4.7 (EDG gcc mode)"
__CHAR16_TYPE__ unsigned short
__CHAR32_TYPE__ unsigned int
__USER_LABEL_PREFIX__ 
__CHAR_UNSIGNED__ 1
__WCHAR_UNSIGNED__ 1
__SIZE_TYPE__ unsigned int
__PTRDIFF_TYPE__ int
__WCHAR_TYPE__ unsigned short
__WINT_TYPE__ unsigned short
__INTMAX_TYPE__ long long
__UINTMAX_TYPE__ unsigned long long
__sizeof_int 4
__sizeof_long 4
__sizeof_ptr 4
__ARMCC_VERSION 5060960
__TARGET_CPU_CORTEX_M0 1
__TARGET_FPU_SOFTVFP 1
__TARGET_FPU_SOFTVFP 1
__MICROLIB 1
__UVISION_VERSION 538
_RTE_ 1
_RTE_ 1
__VTOR_PRESENT 1
__CC_ARM 1
__arm 1
__arm__ 1
__TARGET_ARCH_6S_M 1
__TARGET_ARCH_ARM 0
__TARGET_ARCH_THUMB 3
__TARGET_ARCH_A64 0
__TARGET_ARCH_AARCH32 1
__TARGET_PROFILE_M 1
__TARGET_FEATURE_HALFWORD 1
__TARGET_FEATURE_THUMB 1
__TARGET_FEATURE_DMB 1
__TARGET_FEATURE_EXTENSION_REGISTER_COUNT 0
__APCS_INTERWORK 1
__thumb 1
__thumb__ 1
__t32__ 1
__OPTIMISE_SPACE 1
__OPTIMIZE_SIZE__ 1
__OPTIMISE_LEVEL 0
__SOFTFP__ 1
 
èdelay_init$
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#$%

__stdint_h 
__ARMCLIB_VERSION 5060044
__INT64 __int64
__INT64_C_SUFFIX__ ll
__PASTE2(x,y) x ## y
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__INT64_C(x) __ESCAPE__(__PASTE(x, __INT64_C_SUFFIX__))
__UINT64_C(x) __ESCAPE__(__PASTE(x ## u, __INT64_C_SUFFIX__))
__LONGLONG long long
#__STDINT_DECLS %__CLIBNS
,__CLIBNS 
sINT8_MIN -128
tINT16_MIN -32768
uINT32_MIN (~0x7fffffff)
vINT64_MIN __INT64_C(~0x7fffffffffffffff)
yINT8_MAX 127
zINT16_MAX 32767
{INT32_MAX 2147483647
|INT64_MAX __INT64_C(9223372036854775807)
UINT8_MAX 255
€
UINT16_MAX 65535

UINT32_MAX 4294967295u
‚
UINT64_MAX __UINT64_C(18446744073709551615)
‡
INT_LEAST8_MIN -128
ˆ
INT_LEAST16_MIN -32768
‰
INT_LEAST32_MIN (~0x7fffffff)
Š
INT_LEAST64_MIN __INT64_C(~0x7fffffffffffffff)

INT_LEAST8_MAX 127
Ž
INT_LEAST16_MAX 32767

INT_LEAST32_MAX 2147483647

INT_LEAST64_MAX __INT64_C(9223372036854775807)
“
UINT_LEAST8_MAX 255
”
UINT_LEAST16_MAX 65535
•
UINT_LEAST32_MAX 4294967295u
–
UINT_LEAST64_MAX __UINT64_C(18446744073709551615)
›
INT_FAST8_MIN (~0x7fffffff)
œ
INT_FAST16_MIN (~0x7fffffff)

INT_FAST32_MIN (~0x7fffffff)
ž
INT_FAST64_MIN __INT64_C(~0x7fffffffffffffff)
¡
INT_FAST8_MAX 2147483647
¢
INT_FAST16_MAX 2147483647
£
INT_FAST32_MAX 2147483647
¤
INT_FAST64_MAX __INT64_C(9223372036854775807)
§
UINT_FAST8_MAX 4294967295u
¨
UINT_FAST16_MAX 4294967295u
©
UINT_FAST32_MAX 4294967295u
ª
UINT_FAST64_MAX __UINT64_C(18446744073709551615)
²
INTPTR_MIN INT32_MIN
¹
INTPTR_MAX INT32_MAX
À
UINTPTR_MAX UINT32_MAX
Æ
INTMAX_MIN __ESCAPE__(~0x7fffffffffffffffll)
É
INTMAX_MAX __ESCAPE__(9223372036854775807ll)
Ì
UINTMAX_MAX __ESCAPE__(18446744073709551615ull)
Õ
PTRDIFF_MIN INT32_MIN
Ö
PTRDIFF_MAX INT32_MAX
Ú
SIG_ATOMIC_MIN (~0x7fffffff)
Û
SIG_ATOMIC_MAX 2147483647
á
SIZE_MAX UINT32_MAXç
WCHAR_MINè
WCHAR_MAX
î
WCHAR_MIN 0
ï
WCHAR_MAX 65535
ó
WINT_MIN (~0x7fffffff)
ô
WINT_MAX 2147483647
û
INT8_C(x) (x)
ü
INT16_C(x) (x)
ý
INT32_C(x) (x)
þ
INT64_C(x) __INT64_C(x)
€UINT8_C(x) (x ## u)
UINT16_C(x) (x ## u)
‚UINT32_C(x) (x ## u)
ƒUINT64_C(x) __UINT64_C(x)
†INTMAX_C(x) __ESCAPE__(x ## ll)
‡UINTMAX_C(x) __ESCAPE__(x ## ull)²__INT64³__LONGLONGXO
 




D:\Program Files\MDK5\ARM\ARMCC\Bin\..\include\stdint.h


tD:\Program Files\MDK5\ARM\ARMCC\Bin\..\include\stdint.hComponent: ARM Compiler 5.06 update 7 for Certification (build 960) Tool: ArmCC [4d365d]
signed charshortintlong long
unsigned charunsigned shortunsigned intunsigned long longPint8_t§
8 Pint16_t¶
9 Pint32_t¿
: Pint64_tÆ
; Puint8_tÓ
> Puint16_tä
? Puint32_tö
@ Puint64_t

A Pint_least8_t§
G Pint_least16_t¶
H Pint_least32_t¿
I Pint_least64_tÆ
J Puint_least8_tÓ
M Puint_least16_tä
N Puint_least32_tö
O Puint_least64_t

P Pint_fast8_t¿
U Pint_fast16_t¿
V Pint_fast32_t¿
W Pint_fast64_tÆ
X Puint_fast8_tö
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µ Pu16ä
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· Puint8Ó
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º Puint32ö
» 
'()

'__CORE_CMINSTR_H 
<__NOP __nop
D__WFI __wfi
L__WFE __wfe
S__SEV __sev
\__ISB() do { __schedule_barrier(); __isb(0xF); __schedule_barrier(); } while (0)
g__DSB() do { __schedule_barrier(); __dsb(0xF); __schedule_barrier(); } while (0)
r__DMB() do { __schedule_barrier(); __dmb(0xF); __schedule_barrier(); } while (0)
__REV __rev
©
__ROR __ror
´
__BKPT(value) __breakpoint(value)
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__CLZ __clz@6
 




..\Core\Include\core_cminstr.h


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..\Core\Include\core_cminstr.hComponent: ARM Compiler 5.06 update 7 for Certification (build 960) Tool: ArmCC [4d365d]E:\GasFlowmeter\Internet_of_things_valve\SZV103\SZV103_FM33A0xxEV_SiZhu_jlcGai\KEIL_MDKARM;¯
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valuea__resultv

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..\Core\Include\core_cmfunc.h


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..\Core\Include\core_cmfunc.hComponent: ARM Compiler 5.06 update 7 for Certification (build 960) Tool: ArmCC [4d365d]E:\GasFlowmeter\Internet_of_things_valve\SZV103\SZV103_FM33A0xxEV_SiZhu_jlcGai\KEIL_MDKARM;¨
@__get_CONTROLv
a__resultv

Y__regControlv

P<á
M__set_CONTROL$v
controlY__regControlv

P;›
Z__get_IPSRv
a__resultv

Y__regIPSRv

P;Õ
g__get_APSRv
a__resultv

Y__regAPSRv

P;
t__get_xPSRv
a__resultv

Y__regXPSRv

P;Ø
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__get_PSPv
a__resultv

Y__regProcessStackPointerv

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__set_PSP$v
topOfProcStackY__regProcessStackPointerv

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__get_MSPv
a__resultv

Y__regMainStackPointerv

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__set_MSP$v
topOfMainStackY__regMainStackPointerv

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__get_PRIMASKv
a__resultv

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priMaskY__regPriMaskv

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/01

 __CORE_CM0PLUS_H_GENERIC "
@__CM0PLUS_CMSIS_VERSION_MAIN ( 5U)
A__CM0PLUS_CMSIS_VERSION_SUB ( 0U)
B__CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | __CM0PLUS_CMSIS_VERSION_SUB )
E__CORTEX_M (0U)
Q__ASM __asm
R__INLINE __inline
S__STATIC_INLINE static __inline
T__NO_RETURN __declspec(noreturn)
U__USED __attribute__((used))
V__WEAK __attribute__((weak))
W__UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
Ÿ
__FPU_USED 0UÆ
Ç

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__CORE_CM0PLUS_H_DEPENDANT 
ÿ
__I volatile const
__O volatile
‚__IO volatile
…__IM volatile const
†__OM volatile
‡__IOM volatile
³APSR_N_Pos 31U
´APSR_N_Msk (1UL << APSR_N_Pos)
¶APSR_Z_Pos 30U
·APSR_Z_Msk (1UL << APSR_Z_Pos)
¹APSR_C_Pos 29U
ºAPSR_C_Msk (1UL << APSR_C_Pos)
¼APSR_V_Pos 28U
½APSR_V_Msk (1UL << APSR_V_Pos)
ÎIPSR_ISR_Pos 0U
ÏIPSR_ISR_Msk (0x1FFUL )
æxPSR_N_Pos 31U
çxPSR_N_Msk (1UL << xPSR_N_Pos)
éxPSR_Z_Pos 30U
êxPSR_Z_Msk (1UL << xPSR_Z_Pos)
ìxPSR_C_Pos 29U
íxPSR_C_Msk (1UL << xPSR_C_Pos)
ïxPSR_V_Pos 28U
ðxPSR_V_Msk (1UL << xPSR_V_Pos)
òxPSR_T_Pos 24U
óxPSR_T_Msk (1UL << xPSR_T_Pos)
õxPSR_ISR_Pos 0U
öxPSR_ISR_Msk (0x1FFUL )
ˆCONTROL_SPSEL_Pos 1U
‰CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)
‹CONTROL_nPRIV_Pos 0U
ŒCONTROL_nPRIV_Msk (1UL )
ÈSCB_CPUID_IMPLEMENTER_Pos 24U
ÉSCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
ËSCB_CPUID_VARIANT_Pos 20U
ÌSCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
ÎSCB_CPUID_ARCHITECTURE_Pos 16U
ÏSCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
ÑSCB_CPUID_PARTNO_Pos 4U
ÒSCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
ÔSCB_CPUID_REVISION_Pos 0U
ÕSCB_CPUID_REVISION_Msk (0xFUL )
ØSCB_ICSR_NMIPENDSET_Pos 31U
ÙSCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)
ÛSCB_ICSR_PENDSVSET_Pos 28U
ÜSCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
ÞSCB_ICSR_PENDSVCLR_Pos 27U
ßSCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
áSCB_ICSR_PENDSTSET_Pos 26U
âSCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
äSCB_ICSR_PENDSTCLR_Pos 25U
åSCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
çSCB_ICSR_ISRPREEMPT_Pos 23U
èSCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
êSCB_ICSR_ISRPENDING_Pos 22U
ëSCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
íSCB_ICSR_VECTPENDING_Pos 12U
îSCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
ðSCB_ICSR_VECTACTIVE_Pos 0U
ñSCB_ICSR_VECTACTIVE_Msk (0x1FFUL )
õSCB_VTOR_TBLOFF_Pos 8U
öSCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)
úSCB_AIRCR_VECTKEY_Pos 16U
ûSCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
ýSCB_AIRCR_VECTKEYSTAT_Pos 16U
þSCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
€SCB_AIRCR_ENDIANESS_Pos 15U
SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
ƒSCB_AIRCR_SYSRESETREQ_Pos 2U
„SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
†SCB_AIRCR_VECTCLRACTIVE_Pos 1U
‡SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
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‹SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
SCB_SCR_SLEEPDEEP_Pos 2U
ŽSCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
SCB_SCR_SLEEPONEXIT_Pos 1U
‘SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
”SCB_CCR_STKALIGN_Pos 9U
•SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)
—SCB_CCR_UNALIGN_TRP_Pos 3U
˜SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
›SCB_SHCSR_SVCALLPENDED_Pos 15U
œSCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
´SysTick_CTRL_COUNTFLAG_Pos 16U
µSysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
·SysTick_CTRL_CLKSOURCE_Pos 2U
¸SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
ºSysTick_CTRL_TICKINT_Pos 1U
»SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
½SysTick_CTRL_ENABLE_Pos 0U
¾SysTick_CTRL_ENABLE_Msk (1UL )
ÁSysTick_LOAD_RELOAD_Pos 0U
ÂSysTick_LOAD_RELOAD_Msk (0xFFFFFFUL )
ÅSysTick_VAL_CURRENT_Pos 0U
ÆSysTick_VAL_CURRENT_Msk (0xFFFFFFUL )
ÉSysTick_CALIB_NOREF_Pos 31U
ÊSysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)
ÌSysTick_CALIB_SKEW_Pos 30U
ÍSysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)
ÏSysTick_CALIB_TENMS_Pos 0U
ÐSysTick_CALIB_TENMS_Msk (0xFFFFFFUL )
éMPU_TYPE_IREGION_Pos 16U
êMPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
ìMPU_TYPE_DREGION_Pos 8U
íMPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
ïMPU_TYPE_SEPARATE_Pos 0U
ðMPU_TYPE_SEPARATE_Msk (1UL )
óMPU_CTRL_PRIVDEFENA_Pos 2U
ôMPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
öMPU_CTRL_HFNMIENA_Pos 1U
÷MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
ùMPU_CTRL_ENABLE_Pos 0U
úMPU_CTRL_ENABLE_Msk (1UL )
ýMPU_RNR_REGION_Pos 0U
þMPU_RNR_REGION_Msk (0xFFUL )
MPU_RBAR_ADDR_Pos 8U
‚MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)
„MPU_RBAR_VALID_Pos 4U
…MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos)
‡MPU_RBAR_REGION_Pos 0U
ˆMPU_RBAR_REGION_Msk (0xFUL )
‹MPU_RASR_ATTRS_Pos 16U
ŒMPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos)
ŽMPU_RASR_XN_Pos 28U
MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos)
‘MPU_RASR_AP_Pos 24U
’MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos)
”MPU_RASR_TEX_Pos 19U
•MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos)
—MPU_RASR_S_Pos 18U
˜MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos)
šMPU_RASR_C_Pos 17U
›MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos)
MPU_RASR_B_Pos 16U
žMPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos)
 MPU_RASR_SRD_Pos 8U
¡MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos)
£MPU_RASR_SIZE_Pos 1U
¤MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos)
¦MPU_RASR_ENABLE_Pos 0U
§MPU_RASR_ENABLE_Msk (1UL )
Ä_VAL2FLD(field,value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
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ÙSCS_BASE (0xE000E000UL)
ÚSysTick_BASE (SCS_BASE + 0x0010UL)
ÛNVIC_BASE (SCS_BASE + 0x0100UL)
ÜSCB_BASE (SCS_BASE + 0x0D00UL)
ÞSCB ((SCB_Type *) SCB_BASE )
ßSysTick ((SysTick_Type *) SysTick_BASE )
àNVIC ((NVIC_Type *) NVIC_BASE )
ãMPU_BASE (SCS_BASE + 0x0D90UL)
äMPU ((MPU_Type *) MPU_BASE )
‚_BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
ƒ_SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
„_IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) •
 




..\Core\Include\D:\Program Files\MDK5\ARM\ARMCC\Bin\..\include\core_cm0plus.h
stdint.hcore_cminstr.h
core_cmfunc.h


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..\Core\Include\core_cm0plus.hComponent: ARM Compiler 5.06 update 7 for Certification (build 960) Tool: ArmCC [4d365d]E:\GasFlowmeter\Internet_of_things_valve\SZV103\SZV103_FM33A0xxEV_SiZhu_jlcGai\KEIL_MDKARM*½!_reserved0v
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__stdio_h 
__ARMCLIB_VERSION 5060044
"_ARMABI __declspec(__nothrow)
%__STDIO_DECLS '__CLIBNS
-__CLIBNS <NULL
=NULL 0
g_SYS_OPEN 16
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stdin (&__CLIBNS __stdin)
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stdout (&__CLIBNS __stdout)
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stderr (&__CLIBNS __stderr)
¬
_IOFBF 0x100
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__STDIN_BUFSIZ (64)
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D:\Program Files\MDK5\ARM\ARMCC\Bin\..\include\stdio.h


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D:\Program Files\MDK5\ARM\ARMCC\Bin\..\include\stdio.hComponent: ARM Compiler 5.06 update 7 for Certification (build 960) Tool: ArmCC [4d365d]unsigned intunsigned long longPsize_t¦
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$FM33A0XXEV_H 
.__RCHF_INITIAL_CLOCK (8000000)
/__RCMF_CLOCK (2000000)
0__RCLP_CLOCK (32000)
1__XTLF_CLOCK (32768)
n__CM0_REV 0x0100
o__MPU_PRESENT 1
p__VTOR_PRESENT 1
q__NVIC_PRIO_BITS 2
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¿FLASH_BASE (( uint32_t)0x00000000)
ÀSRAM_BASE (( uint32_t)0x20000000)
ÁPERIPH_BASE (( uint32_t)0x40000000)
ÊPMU_BASE (PERIPH_BASE +0x00002000)
ËDBG_BASE (PERIPH_BASE +0x00000000)
ÌFLS_BASE (PERIPH_BASE +0x00001000)
ÍRMU_BASE (PERIPH_BASE +0x00002800)
ÎIWDT_BASE (PERIPH_BASE +0x00011400)
ÏWWDT_BASE (PERIPH_BASE +0x00011800)
ÐCMU_BASE (PERIPH_BASE +0x00002400)
ÑCDIF_BASE (PERIPH_BASE +0x0001E000)
ÒVRTC_BASE (PERIPH_BASE +0x0001F800)
ÓSVD_BASE (PERIPH_BASE +0x00012800)
ÔAES_BASE (PERIPH_BASE +0x00013800)
ÕPAE_BASE (PERIPH_BASE +0x00001400)
ÖHASH_BASE (PERIPH_BASE +0x00001800)
×RNG_BASE (PERIPH_BASE +0x00013C00)
ØCOMP_BASE (PERIPH_BASE +0x00015400)
ÙI2C0_BASE (PERIPH_BASE +0x00012400)
ÚI2C1_BASE (PERIPH_BASE +0x00015000)
ÛUARTIR_BASE (PERIPH_BASE +0x00017C00)
ÜUART0_BASE (PERIPH_BASE +0x00012000)
ÝUART1_BASE (PERIPH_BASE +0x00016800)
ÞUART2_BASE (PERIPH_BASE +0x00016C00)
ßUART3_BASE (PERIPH_BASE +0x00017000)
àUART4_BASE (PERIPH_BASE +0x00017400)
áUART5_BASE (PERIPH_BASE +0x00017800)
âLPUART0_BASE (PERIPH_BASE +0x00014000)
ãLPUART1_BASE (PERIPH_BASE +0x00014400)
äSPI0_BASE (PERIPH_BASE +0x00010400)
åSPI1_BASE (PERIPH_BASE +0x00010800)
æSPI2_BASE (PERIPH_BASE +0x00014800)
çSPI3_BASE (PERIPH_BASE +0x00014C00)
èSPI4_BASE (PERIPH_BASE +0x00016400)
éU7816_BASE (PERIPH_BASE +0x00011C00)
êQSPI_BASE (PERIPH_BASE +0x00000800)
ëDMA_BASE (PERIPH_BASE +0x00000400)
ìCRC_BASE (PERIPH_BASE +0x00010000)
íBT1_BASE (PERIPH_BASE +0x00013000)
îBT2_BASE (PERIPH_BASE +0x00013044)
ïET1_BASE (PERIPH_BASE +0x00013090)
ðET2_BASE (PERIPH_BASE +0x000130B0)
ñET3_BASE (PERIPH_BASE +0x000130D0)
òET4_BASE (PERIPH_BASE +0x000130F0)
óETCNT_BASE (PERIPH_BASE +0x00013110)
ôBSTIM_BASE (PERIPH_BASE +0x00016000)
õLPTIM_BASE (PERIPH_BASE +0x00013400)
öRTC_BASE (PERIPH_BASE +0x00011000)
÷LCD_BASE (PERIPH_BASE +0x00010C00)
øADC_BASE (PERIPH_BASE +0x0001FA00)
ùCIC_BASE (PERIPH_BASE +0x00015C00)
úGPIOA_BASE (PERIPH_BASE +0x00000C00)
ûGPIOB_BASE (PERIPH_BASE +0x00000C40)
üGPIOC_BASE (PERIPH_BASE +0x00000C80)
ýGPIOD_BASE (PERIPH_BASE +0x00000CC0)
þGPIOE_BASE (PERIPH_BASE +0x00000D00)
ÿGPIOF_BASE (PERIPH_BASE +0x00000D40)
€GPIOG_BASE (PERIPH_BASE +0x00000D80)
GPIOH_BASE (PERIPH_BASE +0x0001FC00)
‚GPIO_BASE (PERIPH_BASE +0x00000DC0)
ˆPMU ((PMU_Type *) PMU_BASE )
‰DBG ((DBG_Type *) DBG_BASE )
ŠFLS ((FLS_Type *) FLS_BASE )
‹RMU ((RMU_Type *) RMU_BASE )
ŒIWDT ((IWDT_Type *) IWDT_BASE )
WWDT ((WWDT_Type *) WWDT_BASE )
ŽCMU ((CMU_Type *) CMU_BASE )
CDIF ((CDIF_Type *) CDIF_BASE )
VRTC ((VRTC_Type *) VRTC_BASE )
‘SVD ((SVD_Type *) SVD_BASE )
’AES ((AES_Type *) AES_BASE )
“PAE ((PAE_Type *) PAE_BASE )
”HASH ((HASH_Type *) HASH_BASE )
•RNG ((RNG_Type *) RNG_BASE )
–COMP ((COMP_Type *) COMP_BASE )
—I2C0 ((I2C_Type *) I2C0_BASE )
˜I2C1 ((I2C_Type *) I2C1_BASE )
™UARTIR ((UARTIR_Type *) UARTIR_BASE )
šUART0 ((UART_Type *) UART0_BASE )
›UART1 ((UART_Type *) UART1_BASE )
œUART2 ((UART_Type *) UART2_BASE )
UART3 ((UART_Type *) UART3_BASE )
žUART4 ((UART_Type *) UART4_BASE )
ŸUART5 ((UART_Type *) UART5_BASE )
 LPUART0 ((LPUART_Type *) LPUART0_BASE )
¡LPUART1 ((LPUART_Type *) LPUART1_BASE )
¢SPI0 ((SPI_Type *) SPI0_BASE )
£SPI1 ((SPI_Type *) SPI1_BASE )
¤SPI2 ((SPI_Type *) SPI2_BASE )
¥SPI3 ((SPI_Type *) SPI3_BASE )
¦SPI4 ((SPI_Type *) SPI4_BASE )
§U7816 ((U7816_Type *) U7816_BASE )
¨QSPI ((QSPI_Type *) QSPI_BASE )
©DMA ((DMA_Type *) DMA_BASE )
ªCRC ((CRC_Type *) CRC_BASE )
«BT1 ((BT_Type *) BT1_BASE )
¬BT2 ((BT_Type *) BT2_BASE )
­ET1 ((ET_Type *) ET1_BASE )
®ET2 ((ET_Type *) ET2_BASE )
¯ET3 ((ET_Type *) ET3_BASE )
°ET4 ((ET_Type *) ET4_BASE )
±ETCNT ((ETCNT_Type *) ETCNT_BASE )
²BSTIM ((BSTIM_Type *) BSTIM_BASE )
³LPTIM ((LPTIM_Type *) LPTIM_BASE )
´RTC ((RTC_Type *) RTC_BASE )
µLCD ((LCD_Type *) LCD_BASE )
¶ADC ((ADC_Type *) ADC_BASE )
·CIC ((CIC_Type *) CIC_BASE )
¸GPIOA ((GPIO_Type *) GPIOA_BASE )
¹GPIOB ((GPIO_Type *) GPIOB_BASE )
ºGPIOC ((GPIO_Type *) GPIOC_BASE )
»GPIOD ((GPIO_Type *) GPIOD_BASE )
¼GPIOE ((GPIO_Type *) GPIOE_BASE )
½GPIOF ((GPIO_Type *) GPIOF_BASE )
¾GPIOG ((GPIO_Type *) GPIOG_BASE )
¿GPIOH ((GPIOH_Type *) GPIOH_BASE )
ÀGPIO ((GPIO_COMMON_Type *) GPIO_BASE )h]
 




..\Core\Include\FM33A0XXEV.h
core_cm0plus.h
system_FM33A0XXEV.h


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..\Core\Include\FM33A0XXEV.hComponent: ARM Compiler 5.06 update 7 for Certification (build 960) Tool: ArmCC [4d365d]E:\GasFlowmeter\Internet_of_things_valve\SZV103\SZV103_FM33A0xxEV_SiZhu_jlcGai\KEIL_MDKARMü

RESETSET
PFlagStatusç
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UART2_IRQnUART3_IRQnUART4_IRQn UART5_IRQnU7816_IRQnLPUART0_IRQnI2Cx_IRQnRSV_IRQnCRYPTO_IRQnLPTIM_IRQnDMA_IRQnWKUPx_IRQnCOMP_IRQnBTx_IRQnQSPI_IRQnETx_IRQnBSTIM_IRQnSPI3_IRQnSPI4_IRQnGPIO_IRQnLPUART1_IRQnPIRQn_Typep

b*ŸCRŸ#WKTRŸ#WKFRŸ#IERŸ#ISRŸ#tv
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(SYSTEM_FM33A0XXEV_H 234
O__SYSTEM_CLOCK (8000000)
PDELAY_US (__SYSTEM_CLOCK/1000000)
QDELAY_MS (__SYSTEM_CLOCK/1000)
TDo_DelayStart() { uint32_t LastTick = SysTick->VAL; do {
WWhile_DelayMsEnd(Count) }while(((LastTick - SysTick->VAL)&0xFFFFFF)<DELAY_MS*Count); }
ZWhile_DelayUsEnd(Count) }while(((LastTick - SysTick->VAL)&0xFFFFFF)<DELAY_US*Count); }œ’
 




..\Core\Include\D:\Program Files\MDK5\ARM\ARMCC\Bin\..\include\system_FM33A0XXEV.h
stdint.hstdio.hFM33A0XXEV.h




..\Core\Include\system_FM33A0XXEV.hComponent: ARM Compiler 5.06 update 7 for Certification (build 960) Tool: ArmCC [4d365d]E:\GasFlowmeter\Internet_of_things_valve\SZV103\SZV103_FM33A0xxEV_SiZhu_jlcGai\KEIL_MDKARMqSystemCoreClockv


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îSystemCoreClock
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__FM33A0XXEV_CMU_H 
HXVAR(object,addr) (*((object *) (addr)))
const_rchf_Trim8 HXVAR( uint32_t, 0x1FFFFB40 )
const_rchf_Trim16 HXVAR( uint32_t, 0x1FFFFB3C )
const_rchf_Trim24 HXVAR( uint32_t, 0x1FFFFB38 )
const_rchf_Trim32 HXVAR( uint32_t, 0x1FFFFB34)
!__XTHF_CLOCK (12000000)
RCMU_SYSCLKCR_SLP_ENEXTI_Pos 25
SCMU_SYSCLKCR_SLP_ENEXTI_Msk (0x1U << CMU_SYSCLKCR_SLP_ENEXTI_Pos)
UCMU_SYSCLKCR_APBPRES_Pos 16
[CMU_SYSCLKCR_APBPRES_Msk (0x7U << CMU_SYSCLKCR_APBPRES_Pos)
\CMU_SYSCLKCR_APBPRES_DIV1 (0x0U << CMU_SYSCLKCR_APBPRES_Pos)
]CMU_SYSCLKCR_APBPRES_DIV2 (0x4U << CMU_SYSCLKCR_APBPRES_Pos)
^CMU_SYSCLKCR_APBPRES_DIV4 (0x5U << CMU_SYSCLKCR_APBPRES_Pos)
_CMU_SYSCLKCR_APBPRES_DIV8 (0x6U << CMU_SYSCLKCR_APBPRES_Pos)
`CMU_SYSCLKCR_APBPRES_DIV16 (0x7U << CMU_SYSCLKCR_APBPRES_Pos)
bCMU_SYSCLKCR_AHBPRES_Pos 8
hCMU_SYSCLKCR_AHBPRES_Msk (0x7U << CMU_SYSCLKCR_AHBPRES_Pos)
iCMU_SYSCLKCR_AHBPRES_DIV1 (0x0U << CMU_SYSCLKCR_AHBPRES_Pos)
jCMU_SYSCLKCR_AHBPRES_DIV2 (0x4U << CMU_SYSCLKCR_AHBPRES_Pos)
kCMU_SYSCLKCR_AHBPRES_DIV4 (0x5U << CMU_SYSCLKCR_AHBPRES_Pos)
lCMU_SYSCLKCR_AHBPRES_DIV8 (0x6U << CMU_SYSCLKCR_AHBPRES_Pos)
mCMU_SYSCLKCR_AHBPRES_DIV16 (0x7U << CMU_SYSCLKCR_AHBPRES_Pos)
oCMU_SYSCLKCR_STCLKSEL_Pos 6
tCMU_SYSCLKCR_STCLKSEL_Msk (0x3U << CMU_SYSCLKCR_STCLKSEL_Pos)
uCMU_SYSCLKCR_STCLKSEL_SCLK (0x0U << CMU_SYSCLKCR_STCLKSEL_Pos)
vCMU_SYSCLKCR_STCLKSEL_LSCLK (0x1U << CMU_SYSCLKCR_STCLKSEL_Pos)
wCMU_SYSCLKCR_STCLKSEL_RC4M (0x2U << CMU_SYSCLKCR_STCLKSEL_Pos)
xCMU_SYSCLKCR_STCLKSEL_SYSCLK (0x3U << CMU_SYSCLKCR_STCLKSEL_Pos)
zCMU_SYSCLKCR_SYSCLKSEL_Pos 0
{CMU_SYSCLKCR_SYSCLKSEL_Msk (0x7U << CMU_SYSCLKCR_SYSCLKSEL_Pos)
|CMU_SYSCLKCR_SYSCLKSEL_RCHF (0x0U << CMU_SYSCLKCR_SYSCLKSEL_Pos)
}CMU_SYSCLKCR_SYSCLKSEL_XTHF (0x1U << CMU_SYSCLKCR_SYSCLKSEL_Pos)
~CMU_SYSCLKCR_SYSCLKSEL_PLL_H (0x2U << CMU_SYSCLKCR_SYSCLKSEL_Pos)
CMU_SYSCLKCR_SYSCLKSEL_LSCLK (0x3U << CMU_SYSCLKCR_SYSCLKSEL_Pos)

CMU_RCHFCR_FSEL_Pos 16
ˆ
CMU_RCHFCR_FSEL_Msk (0xfU << CMU_RCHFCR_FSEL_Pos)
‰
CMU_RCHFCR_FSEL_8MHZ (0x0U << CMU_RCHFCR_FSEL_Pos)
Š
CMU_RCHFCR_FSEL_16MHZ (0x1U << CMU_RCHFCR_FSEL_Pos)
‹
CMU_RCHFCR_FSEL_24MHZ (0x2U << CMU_RCHFCR_FSEL_Pos)
Œ
CMU_RCHFCR_FSEL_32MHZ (0x3U << CMU_RCHFCR_FSEL_Pos)
Ž
CMU_RCHFCR_RCHFEN_Pos 0
‘
CMU_RCHFCR_RCHFEN_Msk (0x1U << CMU_RCHFCR_RCHFEN_Pos)
•
CMU_RCHFTR_RCHFTRIM_Pos 0
˜
CMU_RCHFTR_RCHFTRIM_Msk (0xffU << CMU_RCHFTR_RCHFTRIM_Pos)
š
CMU_PLLLCR_PLLDB_Pos 16
›
CMU_PLLLCR_PLLDB_Msk (0x3ffU << CMU_PLLLCR_PLLDB_Pos)

CMU_PLLLCR_LOCKED_Pos 7
ž
CMU_PLLLCR_LOCKED_Msk (0x1U << CMU_PLLLCR_LOCKED_Pos)
 
CMU_PLLLCR_PLLEN_Pos 0
£
CMU_PLLLCR_PLLEN_Msk (0x1U << CMU_PLLLCR_PLLEN_Pos)
¥
CMU_PLLHCR_PLLHDB_Pos 16
¨
CMU_PLLHCR_PLLHDB_Msk (0x3ffU << CMU_PLLHCR_PLLHDB_Pos)
©
CMU_PLLHCR_PLLHDB_X32 (0x1fU << CMU_PLLHCR_PLLHDB_Pos)
ª
CMU_PLLHCR_PLLHDB_X48 (0x2fU << CMU_PLLHCR_PLLHDB_Pos)
«
CMU_PLLHCR_PLLHDB_X64 (0x3fU << CMU_PLLHCR_PLLHDB_Pos)
­
CMU_PLLHCR_LOCKED_Pos 7
°
CMU_PLLHCR_LOCKED_Msk (0x1U << CMU_PLLHCR_LOCKED_Pos)
²
CMU_PLLHCR_REFPRSC_Pos 4
»
CMU_PLLHCR_REFPRSC_Msk (0x7U << CMU_PLLHCR_REFPRSC_Pos)
¼
CMU_PLLHCR_REFPRSC_DIV1 (0x0U << CMU_PLLHCR_REFPRSC_Pos)
½
CMU_PLLHCR_REFPRSC_DIV2 (0x1U << CMU_PLLHCR_REFPRSC_Pos)
¾
CMU_PLLHCR_REFPRSC_DIV4 (0x2U << CMU_PLLHCR_REFPRSC_Pos)
¿
CMU_PLLHCR_REFPRSC_DIV8 (0x3U << CMU_PLLHCR_REFPRSC_Pos)
À
CMU_PLLHCR_REFPRSC_DIV12 (0x4U << CMU_PLLHCR_REFPRSC_Pos)
Á
CMU_PLLHCR_REFPRSC_DIV16 (0x5U << CMU_PLLHCR_REFPRSC_Pos)
Â
CMU_PLLHCR_REFPRSC_DIV24 (0x6U << CMU_PLLHCR_REFPRSC_Pos)
Ã
CMU_PLLHCR_REFPRSC_DIV32 (0x7U << CMU_PLLHCR_REFPRSC_Pos)
Å
CMU_PLLHCR_OSEL_Pos 3
È
CMU_PLLHCR_OSEL_Msk (0x1U << CMU_PLLHCR_OSEL_Pos)
É
CMU_PLLHCR_OSEL_X1 (0x0U << CMU_PLLHCR_OSEL_Pos)
Ê
CMU_PLLHCR_OSEL_X2 (0x1U << CMU_PLLHCR_OSEL_Pos)
Ì
CMU_PLLHCR_INSEL_Pos 1
Ï
CMU_PLLHCR_INSEL_Msk (0x1U << CMU_PLLHCR_INSEL_Pos)
Ð
CMU_PLLHCR_INSEL_RCHF (0x0U << CMU_PLLHCR_INSEL_Pos)
Ñ
CMU_PLLHCR_INSEL_XTHF (0x1U << CMU_PLLHCR_INSEL_Pos)
Ó
CMU_PLLHCR_EN_Pos 0
Ö
CMU_PLLHCR_EN_Msk (0x1U << CMU_PLLHCR_EN_Pos)
Ø
CMU_XTHFCR_XTHF_CFG_Pos 8
Û
CMU_XTHFCR_XTHF_CFG_Msk (0x7U << CMU_XTHFCR_XTHF_CFG_Pos)
Ü
CMU_XTHFCR_XTHF_CFG_MIN (0x0U << CMU_XTHFCR_XTHF_CFG_Pos)
Ý
CMU_XTHFCR_XTHF_CFG_MAX (0x7U << CMU_XTHFCR_XTHF_CFG_Pos)
ß
CMU_XTHFCR_XTHFEN_Pos 0
â
CMU_XTHFCR_XTHFEN_Msk (0x1U << CMU_XTHFCR_XTHFEN_Pos)
æ
CMU_IER_SYSCSE_IE_Pos 1
ç
CMU_IER_SYSCSE_IE_Msk (0x1U << CMU_IER_SYSCSE_IE_Pos)
é
CMU_IER_HFDET_IE_Pos 0
ê
CMU_IER_HFDET_IE_Msk (0x1U << CMU_IER_HFDET_IE_Pos)
í
CMU_ISR_HFDETO_Pos 8
ð
CMU_ISR_HFDETO_Msk (0x1U << CMU_ISR_HFDETO_Pos)
ò
CMU_ISR_SYSCSE_IF_Pos 1
ó
CMU_ISR_SYSCSE_IF_Msk (0x1U << CMU_ISR_SYSCSE_IF_Pos)
õ
CMU_ISR_HFDET_IF_Pos 0
ö
CMU_ISR_HFDET_IF_Msk (0x1U << CMU_ISR_HFDET_IF_Pos)
ø
CMU_PCLKCR1_COMP_PCE_Pos 9
ù
CMU_PCLKCR1_COMP_PCE_Msk (0x1U << CMU_PCLKCR1_COMP_PCE_Pos)
û
CMU_PCLKCR1_SVD_PCE_Pos 8
ü
CMU_PCLKCR1_SVD_PCE_Msk (0x1U << CMU_PCLKCR1_SVD_PCE_Pos)
þ
CMU_PCLKCR1_PAD_PCE_Pos 7
ÿ
CMU_PCLKCR1_PAD_PCE_Msk (0x1U << CMU_PCLKCR1_PAD_PCE_Pos)
CMU_PCLKCR1_ANAC_PCE_Pos 6
ƒCMU_PCLKCR1_ANAC_PCE_Msk (0x1U << CMU_PCLKCR1_ANAC_PCE_Pos)
…CMU_PCLKCR1_IWDT_PCE_Pos 5
†CMU_PCLKCR1_IWDT_PCE_Msk (0x1U << CMU_PCLKCR1_IWDT_PCE_Pos)
ˆCMU_PCLKCR1_SCU_PCE_Pos 4
‰CMU_PCLKCR1_SCU_PCE_Msk (0x1U << CMU_PCLKCR1_SCU_PCE_Pos)
‹CMU_PCLKCR1_PMU_PCE_Pos 3
ŒCMU_PCLKCR1_PMU_PCE_Msk (0x1U << CMU_PCLKCR1_PMU_PCE_Pos)
ŽCMU_PCLKCR1_RTC_PCE_Pos 2
CMU_PCLKCR1_RTC_PCE_Msk (0x1U << CMU_PCLKCR1_RTC_PCE_Pos)
‘CMU_PCLKCR1_LPT_PCE_Pos 0
’CMU_PCLKCR1_LPT_PCE_Msk (0x1U << CMU_PCLKCR1_LPT_PCE_Pos)
”CMU_PCLKCR2_PAE_PCE_Pos 17
•CMU_PCLKCR2_PAE_PCE_Msk (0x1U << CMU_PCLKCR2_PAE_PCE_Pos)
—CMU_PCLKCR2_SHA_PCE_Pos 16
˜CMU_PCLKCR2_SHA_PCE_Msk (0x1U << CMU_PCLKCR2_SHA_PCE_Pos)
šCMU_PCLKCR2_CIC_PCE_Pos 8
›CMU_PCLKCR2_CIC_PCE_Msk (0x1U << CMU_PCLKCR2_CIC_PCE_Pos)
CMU_PCLKCR2_WWDT_PCE_Pos 7
žCMU_PCLKCR2_WWDT_PCE_Msk (0x1U << CMU_PCLKCR2_WWDT_PCE_Pos)
 CMU_PCLKCR2_RAMBIST_PCE_Pos 6
¡CMU_PCLKCR2_RAMBIST_PCE_Msk (0x1U << CMU_PCLKCR2_RAMBIST_PCE_Pos)
£CMU_PCLKCR2_NVM_PCE_Pos 5
¤CMU_PCLKCR2_NVM_PCE_Msk (0x1U << CMU_PCLKCR2_NVM_PCE_Pos)
¦CMU_PCLKCR2_DMA_PCE_Pos 4
§CMU_PCLKCR2_DMA_PCE_Msk (0x1U << CMU_PCLKCR2_DMA_PCE_Pos)
©CMU_PCLKCR2_LCD_PCE_Pos 3
ªCMU_PCLKCR2_LCD_PCE_Msk (0x1U << CMU_PCLKCR2_LCD_PCE_Pos)
¬CMU_PCLKCR2_AES_PCE_Pos 2
­CMU_PCLKCR2_AES_PCE_Msk (0x1U << CMU_PCLKCR2_AES_PCE_Pos)
¯CMU_PCLKCR2_TRNG_PCE_Pos 1
°CMU_PCLKCR2_TRNG_PCE_Msk (0x1U << CMU_PCLKCR2_TRNG_PCE_Pos)
²CMU_PCLKCR2_CRC_PCE_Pos 0
³CMU_PCLKCR2_CRC_PCE_Msk (0x1U << CMU_PCLKCR2_CRC_PCE_Pos)
µCMU_PCLKCR3_I2C1_PCE_Pos 25
¶CMU_PCLKCR3_I2C1_PCE_Msk (0x1U << CMU_PCLKCR3_I2C1_PCE_Pos)
¸CMU_PCLKCR3_I2C0_PCE_Pos 24
¹CMU_PCLKCR3_I2C0_PCE_Msk (0x1U << CMU_PCLKCR3_I2C0_PCE_Pos)
»CMU_PCLKCR3_LPUART1_PCE_Pos 18
¼CMU_PCLKCR3_LPUART1_PCE_Msk (0x1U << CMU_PCLKCR3_LPUART1_PCE_Pos)
¾CMU_PCLKCR3_U7816_PCE_Pos 16
¿CMU_PCLKCR3_U7816_PCE_Msk (0x1U << CMU_PCLKCR3_U7816_PCE_Pos)
ÁCMU_PCLKCR3_LPUART0_PCE_Pos 15
ÂCMU_PCLKCR3_LPUART0_PCE_Msk (0x1U << CMU_PCLKCR3_LPUART0_PCE_Pos)
ÄCMU_PCLKCR3_UICR_PCE_Pos 14
ÅCMU_PCLKCR3_UICR_PCE_Msk (0x1U << CMU_PCLKCR3_UICR_PCE_Pos)
ÇCMU_PCLKCR3_UART5_PCE_Pos 13
ÈCMU_PCLKCR3_UART5_PCE_Msk (0x1U << CMU_PCLKCR3_UART5_PCE_Pos)
ÊCMU_PCLKCR3_UART4_PCE_Pos 12
ËCMU_PCLKCR3_UART4_PCE_Msk (0x1U << CMU_PCLKCR3_UART4_PCE_Pos)
ÍCMU_PCLKCR3_UART3_PCE_Pos 11
ÎCMU_PCLKCR3_UART3_PCE_Msk (0x1U << CMU_PCLKCR3_UART3_PCE_Pos)
ÐCMU_PCLKCR3_UART2_PCE_Pos 10
ÑCMU_PCLKCR3_UART2_PCE_Msk (0x1U << CMU_PCLKCR3_UART2_PCE_Pos)
ÓCMU_PCLKCR3_UART1_PCE_Pos 9
ÔCMU_PCLKCR3_UART1_PCE_Msk (0x1U << CMU_PCLKCR3_UART1_PCE_Pos)
ÖCMU_PCLKCR3_UART0_PCE_Pos 8
×CMU_PCLKCR3_UART0_PCE_Msk (0x1U << CMU_PCLKCR3_UART0_PCE_Pos)
ÙCMU_PCLKCR3_QSPI_PCE_Pos 7
ÚCMU_PCLKCR3_QSPI_PCE_Msk (0x1U << CMU_PCLKCR3_QSPI_PCE_Pos)
ÜCMU_PCLKCR3_SPI4_PCE_Pos 4
ÝCMU_PCLKCR3_SPI4_PCE_Msk (0x1U << CMU_PCLKCR3_SPI4_PCE_Pos)
ßCMU_PCLKCR3_SPI3_PCE_Pos 3
àCMU_PCLKCR3_SPI3_PCE_Msk (0x1U << CMU_PCLKCR3_SPI3_PCE_Pos)
âCMU_PCLKCR3_SPI2_PCE_Pos 2
ãCMU_PCLKCR3_SPI2_PCE_Msk (0x1U << CMU_PCLKCR3_SPI2_PCE_Pos)
åCMU_PCLKCR3_SPI1_PCE_Pos 1
æCMU_PCLKCR3_SPI1_PCE_Msk (0x1U << CMU_PCLKCR3_SPI1_PCE_Pos)
èCMU_PCLKCR3_SPI0_PCE_Pos 0
éCMU_PCLKCR3_SPI0_PCE_Msk (0x1U << CMU_PCLKCR3_SPI0_PCE_Pos)
ëCMU_PCLKCR4_ET4_PCE_Pos 6
ìCMU_PCLKCR4_ET4_PCE_Msk (0x1U << CMU_PCLKCR4_ET4_PCE_Pos)
îCMU_PCLKCR4_ET3_PCE_Pos 5
ïCMU_PCLKCR4_ET3_PCE_Msk (0x1U << CMU_PCLKCR4_ET3_PCE_Pos)
ñCMU_PCLKCR4_ET2_PCE_Pos 4
òCMU_PCLKCR4_ET2_PCE_Msk (0x1U << CMU_PCLKCR4_ET2_PCE_Pos)
ôCMU_PCLKCR4_ET1_PCE_Pos 3
õCMU_PCLKCR4_ET1_PCE_Msk (0x1U << CMU_PCLKCR4_ET1_PCE_Pos)
÷CMU_PCLKCR4_BT2_PCE_Pos 2
øCMU_PCLKCR4_BT2_PCE_Msk (0x1U << CMU_PCLKCR4_BT2_PCE_Pos)
úCMU_PCLKCR4_BT1_PCE_Pos 1
ûCMU_PCLKCR4_BT1_PCE_Msk (0x1U << CMU_PCLKCR4_BT1_PCE_Pos)
ýCMU_PCLKCR4_BSTIM_PCE_Pos 0
þCMU_PCLKCR4_BSTIM_PCE_Msk (0x1U << CMU_PCLKCR4_BSTIM_PCE_Pos)
€CMU_OPCCR1_EXTICKE_Pos 31
CMU_OPCCR1_EXTICKE_Msk (0x1U << CMU_OPCCR1_EXTICKE_Pos)
ƒCMU_OPCCR1_EXTICKSEL_Pos 30
„CMU_OPCCR1_EXTICKSEL_Msk (0x1U << CMU_OPCCR1_EXTICKSEL_Pos)
…CMU_OPCCR1_EXTICKSEL_LSCLK (0x1U << CMU_OPCCR1_EXTICKSEL_Pos)
†CMU_OPCCR1_EXTICKSEL_HCLK (0x0U << CMU_OPCCR1_EXTICKSEL_Pos)
ˆCMU_OPCCR1_LPUART1CKE_Pos 29
‰CMU_OPCCR1_LPUART1CKE_Msk (0x1U << CMU_OPCCR1_LPUART1CKE_Pos)
‹CMU_OPCCR1_LPUART0CKE_Pos 28
ŒCMU_OPCCR1_LPUART0CKE_Msk (0x1U << CMU_OPCCR1_LPUART0CKE_Pos)
ŽCMU_OPCCR1_LPUART1CKS_Pos 26
“CMU_OPCCR1_LPUART1CKS_Msk (0x3U << CMU_OPCCR1_LPUART1CKS_Pos)
”CMU_OPCCR1_LPUART1CKS_LSCLK (0x0U << CMU_OPCCR1_LPUART1CKS_Pos)
•CMU_OPCCR1_LPUART1CKS_RCHF (0x1U << CMU_OPCCR1_LPUART1CKS_Pos)
—CMU_OPCCR1_LPUART0CKS_Pos 24
œCMU_OPCCR1_LPUART0CKS_Msk (0x3U << CMU_OPCCR1_LPUART0CKS_Pos)
CMU_OPCCR1_LPUART0CKS_LSCLK (0x0U << CMU_OPCCR1_LPUART0CKS_Pos)
žCMU_OPCCR1_LPUART0CKS_RCHF (0x1U << CMU_OPCCR1_LPUART0CKS_Pos)
 CMU_OPCCR1_I2C1CKE_Pos 21
¡CMU_OPCCR1_I2C1CKE_Msk (0x1U << CMU_OPCCR1_I2C1CKE_Pos)
£CMU_OPCCR1_I2C0CKE_Pos 20
¤CMU_OPCCR1_I2C0CKE_Msk (0x1U << CMU_OPCCR1_I2C0CKE_Pos)
¦CMU_OPCCR1_I2C1CKS_Pos 18
«CMU_OPCCR1_I2C1CKS_Msk (0x3U << CMU_OPCCR1_I2C1CKS_Pos)
¬CMU_OPCCR1_I2C1CKS_APBCLK (0x0U << CMU_OPCCR1_I2C1CKS_Pos)
­CMU_OPCCR1_I2C1CKS_RCHF (0x1U << CMU_OPCCR1_I2C1CKS_Pos)
®CMU_OPCCR1_I2C1CKS_SYSCLK (0x2U << CMU_OPCCR1_I2C1CKS_Pos)
°CMU_OPCCR1_I2C0CKS_Pos 16
µCMU_OPCCR1_I2C0CKS_Msk (0x3U << CMU_OPCCR1_I2C0CKS_Pos)
¶CMU_OPCCR1_I2C0CKS_APBCLK (0x0U << CMU_OPCCR1_I2C0CKS_Pos)
·CMU_OPCCR1_I2C0CKS_RCHF (0x1U << CMU_OPCCR1_I2C0CKS_Pos)
¸CMU_OPCCR1_I2C0CKS_SYSCLK (0x2U << CMU_OPCCR1_I2C0CKS_Pos)
ºCMU_OPCCR1_UART1CKE_Pos 9
»CMU_OPCCR1_UART1CKE_Msk (0x1U << CMU_OPCCR1_UART1CKE_Pos)
½CMU_OPCCR1_UART0CKE_Pos 8
¾CMU_OPCCR1_UART0CKE_Msk (0x1U << CMU_OPCCR1_UART0CKE_Pos)
ÀCMU_OPCCR1_UART1CKS_Pos 2
ÅCMU_OPCCR1_UART1CKS_Msk (0x3U << CMU_OPCCR1_UART1CKS_Pos)
ÆCMU_OPCCR1_UART1CKS_APBCLK (0x0U << CMU_OPCCR1_UART1CKS_Pos)
ÇCMU_OPCCR1_UART1CKS_RCHF (0x1U << CMU_OPCCR1_UART1CKS_Pos)
ÈCMU_OPCCR1_UART1CKS_SYSCLK (0x2U << CMU_OPCCR1_UART1CKS_Pos)
ÊCMU_OPCCR1_UART0CKS_Pos 0
ÏCMU_OPCCR1_UART0CKS_Msk (0x3U << CMU_OPCCR1_UART0CKS_Pos)
ÐCMU_OPCCR1_UART0CKS_APBCLK (0x0U << CMU_OPCCR1_UART0CKS_Pos)
ÑCMU_OPCCR1_UART0CKS_RCHF (0x1U << CMU_OPCCR1_UART0CKS_Pos)
ÒCMU_OPCCR1_UART0CKS_SYSCLK (0x2U << CMU_OPCCR1_UART0CKS_Pos)
ÔCMU_OPCCR2_RNGPRSC_Pos 28
ÜCMU_OPCCR2_RNGPRSC_Msk (0x7U << CMU_OPCCR2_RNGPRSC_Pos)
ÝCMU_OPCCR2_RNGPRSC_DIV1 (0x0U << CMU_OPCCR2_RNGPRSC_Pos)
ÞCMU_OPCCR2_RNGPRSC_DIV2 (0x1U << CMU_OPCCR2_RNGPRSC_Pos)
ßCMU_OPCCR2_RNGPRSC_DIV4 (0x2U << CMU_OPCCR2_RNGPRSC_Pos)
àCMU_OPCCR2_RNGPRSC_DIV8 (0x3U << CMU_OPCCR2_RNGPRSC_Pos)
áCMU_OPCCR2_RNGPRSC_DIV16 (0x4U << CMU_OPCCR2_RNGPRSC_Pos)
âCMU_OPCCR2_RNGPRSC_DIV32 (0x5U << CMU_OPCCR2_RNGPRSC_Pos)
äCMU_OPCCR2_NVMCKE_Pos 22
åCMU_OPCCR2_NVMCKE_Msk (0x1U << CMU_OPCCR2_NVMCKE_Pos)
çCMU_OPCCR2_RNGCKE_Pos 21
èCMU_OPCCR2_RNGCKE_Msk (0x1U << CMU_OPCCR2_RNGCKE_Pos)
êCMU_OPCCR2_LPTCKE_Pos 12
ëCMU_OPCCR2_LPTCKE_Msk (0x1U << CMU_OPCCR2_LPTCKE_Pos)
íCMU_OPCCR2_LPTCKS_Pos 8
òCMU_OPCCR2_LPTCKS_Msk (0x3U << CMU_OPCCR2_LPTCKS_Pos)
óCMU_OPCCR2_LPTCKS_APBCLK (0x0U << CMU_OPCCR2_LPTCKS_Pos)
ôCMU_OPCCR2_LPTCKS_LSCLK (0x1U << CMU_OPCCR2_LPTCKS_Pos)
õCMU_OPCCR2_LPTCKS_RCLP (0x2U << CMU_OPCCR2_LPTCKS_Pos)
öCMU_OPCCR2_LPTCKS_PLL_L (0x3U << CMU_OPCCR2_LPTCKS_Pos)
øCMU_OPCCR2_BSTCKE_Pos 4
ùCMU_OPCCR2_BSTCKE_Msk (0x1U << CMU_OPCCR2_BSTCKE_Pos)
ûCMU_OPCCR2_BSTCKS_Pos 0
€CMU_OPCCR2_BSTCKS_Msk (0x3U << CMU_OPCCR2_BSTCKS_Pos)
CMU_OPCCR2_BSTCKS_APBCLK (0x0U << CMU_OPCCR2_BSTCKS_Pos)
‚CMU_OPCCR2_BSTCKS_LSCLK (0x1U << CMU_OPCCR2_BSTCKS_Pos)
ƒCMU_OPCCR2_BSTCKS_RCLP (0x2U << CMU_OPCCR2_BSTCKS_Pos)
„CMU_OPCCR2_BSTCKS_SYSCLK (0x3U << CMU_OPCCR2_BSTCKS_Pos)
£COMPCLK (0x01000000 + CMU_PCLKCR1_COMP_PCE_Pos)
¤SVDCLK (0x01000000 + CMU_PCLKCR1_SVD_PCE_Pos)
¥PADCLK (0x01000000 + CMU_PCLKCR1_PAD_PCE_Pos)
¦ANACCLK (0x01000000 + CMU_PCLKCR1_ANAC_PCE_Pos)
§IWDTCLK (0x01000000 + CMU_PCLKCR1_IWDT_PCE_Pos)
¨SCUCLK (0x01000000 + CMU_PCLKCR1_SCU_PCE_Pos)
©PMUCLK (0x01000000 + CMU_PCLKCR1_PMU_PCE_Pos)
ªRTCCLK (0x01000000 + CMU_PCLKCR1_RTC_PCE_Pos)
«LPTCLK (0x01000000 + CMU_PCLKCR1_LPT_PCE_Pos)
®PAECLK (0x02000000 + CMU_PCLKCR2_PAE_PCE_Pos)
¯SHACLK (0x02000000 + CMU_PCLKCR2_SHA_PCE_Pos)
°CICCLK (0x02000000 + CMU_PCLKCR2_CIC_PCE_Pos)
±WWDTCLK (0x02000000 + CMU_PCLKCR2_WWDT_PCE_Pos)
²RAMBISTCLK (0x02000000 + CMU_PCLKCR2_RAMBIST_PCE_Pos)
³FLASHCLK (0x02000000 + CMU_PCLKCR2_NVM_PCE_Pos)
´DMACLK (0x02000000 + CMU_PCLKCR2_DMA_PCE_Pos)
µLCDCLK (0x02000000 + CMU_PCLKCR2_LCD_PCE_Pos)
¶AESCLK (0x02000000 + CMU_PCLKCR2_AES_PCE_Pos)
·TRNGCLK (0x02000000 + CMU_PCLKCR2_TRNG_PCE_Pos)
¸CRCCLK (0x02000000 + CMU_PCLKCR2_CRC_PCE_Pos)
ºI2C1CLK (0x03000000 + CMU_PCLKCR3_I2C1_PCE_Pos)
»I2C0CLK (0x03000000 + CMU_PCLKCR3_I2C0_PCE_Pos)
¼LPUART1CLK (0x03000000 + CMU_PCLKCR3_LPUART1_PCE_Pos)
½U7816CLK (0x03000000 + CMU_PCLKCR3_U7816_PCE_Pos)
¾LPUART0CLK (0x03000000 + CMU_PCLKCR3_LPUART0_PCE_Pos)
¿UARTIRCLK (0x03000000 + CMU_PCLKCR3_UICR_PCE_Pos)
ÀUART5CLK (0x03000000 + CMU_PCLKCR3_UART5_PCE_Pos)
ÁUART4CLK (0x03000000 + CMU_PCLKCR3_UART4_PCE_Pos)
ÂUART3CLK (0x03000000 + CMU_PCLKCR3_UART3_PCE_Pos)
ÃUART2CLK (0x03000000 + CMU_PCLKCR3_UART2_PCE_Pos)
ÄUART1CLK (0x03000000 + CMU_PCLKCR3_UART1_PCE_Pos)
ÅUART0CLK (0x03000000 + CMU_PCLKCR3_UART0_PCE_Pos)
ÆQSPICLK (0x03000000 + CMU_PCLKCR3_QSPI_PCE_Pos)
ÇSPI4CLK (0x03000000 + CMU_PCLKCR3_SPI4_PCE_Pos)
ÈSPI3CLK (0x03000000 + CMU_PCLKCR3_SPI3_PCE_Pos)
ÉSPI2CLK (0x03000000 + CMU_PCLKCR3_SPI2_PCE_Pos)
ÊSPI1CLK (0x03000000 + CMU_PCLKCR3_SPI1_PCE_Pos)
ËSPI0CLK (0x03000000 + CMU_PCLKCR3_SPI0_PCE_Pos)
ÎET4CLK (0x04000000 + CMU_PCLKCR4_ET4_PCE_Pos)
ÏET3CLK (0x04000000 + CMU_PCLKCR4_ET3_PCE_Pos)
ÐET2CLK (0x04000000 + CMU_PCLKCR4_ET2_PCE_Pos)
ÑET1CLK (0x04000000 + CMU_PCLKCR4_ET1_PCE_Pos)
ÒBT2CLK (0x04000000 + CMU_PCLKCR4_BT2_PCE_Pos)
ÓBT1CLK (0x04000000 + CMU_PCLKCR4_BT1_PCE_Pos)
ÔBSTIMCLK (0x04000000 + CMU_PCLKCR4_BSTIM_PCE_Pos)`T
 




..\Drivers\..\Core\Include\fm33a0xxev_cmu.h
FM33A0XXEV.h


..\Drivers\fm33a0xxev_cmu.hComponent: ARM Compiler 5.06 update 7 for Certification (build 960) Tool: ArmCC [4d365d]E:\GasFlowmeter\Internet_of_things_valve\SZV103\SZV103_FM33A0xxEV_SiZhu_jlcGai\KEIL_MDKARM*‰FSELv
#RCHFEN8
#PCMU_RCHF_InitTypeDefæ
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#PLLL_EN8
#PCMU_PLL_L_InitTypeDef%

/*ÆPLLHDBv
#REFPRSCv
#PLLH_OSELv
#PLLH_INSELv
#PLLH_EN8
#PCMU_PLL_H_InitTypeDefh

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#PCMU_SYSCLK_InitTypeDefã

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SYSTICK_CLOCK_SOURCE_SCLK 0xFFFFFF3F
SYSTICK_CLOCK_SOURCE_LSCLK 0xFFFFFF7F
SYSTICK_CLOCK_SOURCE_RFU 0xFFFFFFBF
    SYSTICK_CLOCK_SOURCE_SYSCLK 0xFFFFFFFF
SYSTICK_CLOCK_SOURCE_U_SCLK 0x00000000
SYSTICK_CLOCK_SOURCE_U_LSCLK 0x00000040
 SYSTICK_CLOCK_SOURCE_U_RFU 0x00000080
SYSTICK_CLOCK_SOURCE_U_SYSCLK 0x000000C0
SYSCLOCK_U 12000000\Q
 




..\Hardware\DELAY\..\Drivers\delay.h
fm33a0xxev_cmu.h



..\Hardware\DELAY\delay.hComponent: ARM Compiler 5.06 update 7 for Certification (build 960) Tool: ArmCC [4d365d]E:\GasFlowmeter\Internet_of_things_valve\SZV103\SZV103_FM33A0xxEV_SiZhu_jlcGai\KEIL_MDKARMintNò
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..\Hardware\DELAY\..\Hardware\DELAY\delay.cdelay.h


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Input Comments:p58c8-3Component: ARM Compiler 5.06 update 7 for Certification (build 960) Tool: armasm [4d35fa]armasm --debug --diag_suppress=9931,9931,1602,1073 --cpu=Cortex-M0 --fpu=SoftVFP --apcs=/interwork/interwork --no_divide delay.oComponent: ARM Compiler 5.06 update 7 for Certification (build 960) Tool: ArmCC [4d365d]ArmCC --c99 --split_sections --debug -c --gnu -o.\objects\delay.o --depend=.\objects\delay.d --cpu=Cortex-M0 --apcs=interwork -O0 --diag_suppress=9931 -I..\Core -I..\Drivers -I..\Core\Include -I..\Hardware -I.\RTE\Device -I..\Hardware\CLOCK -I..\Hardware\DELAY -I..\Hardware\GPIO -I..\Hardware\UART -I..\Hardware\TIM -I..\Function\KEY -I..\Hardware\EXTI -I..\Hardware\RTC -I..\Hardware\ADC -I..\Hardware\I2C -I..\Function\LCD -I..\Function\EXTERN_RTC -I..\Hardware\SPI -I..\Function\GPRS -I..\Function\HARDWARE_WATCHDOG -I..\Function\IR_NEC -I..\Function\MEASURE_INTERACTION -I..\Function\POWER_MANAGE -I..\Function\STORAGE -I..\Function\UPPER_COMPUTER -I..\Function\VALVE -I..\Soft -I..\MultiButton -I..\USMART -I..\Hardware\DMA -I..\Hardware\ON_CHIP_FLASH -I..\Hardware\SVD -I..\Function\OFF_CHIP_FLASH -I..\Hardware\CRC -I..\Function\BOOTLOADER_IAP -I..\Hardware\COMP -I..\CmBackTrace -I..\Function\E2P -I.\RTE\_UFG220_FM33A0_MainSystem -I"D:\Program Files\MDK5\Packs\Keil\FM33A0XXEV_DFP\0.0.4\Device\Include" -D__MICROLIB -D__UVISION_VERSION=538 -D_RTE_ -D_RTE_ -D__VTOR_PRESENT --omf_browse=.\objects\delay.crf ..\Hardware\DELAY\delay.c8
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