#include "ir_nec.h"
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#include "gpio.h"
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#include "uart.h"
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/*ÓÉÓÚFM33A0ûÓд®¿Ú¿ÕÏÐÖжϣ¬ËùÒÔÀûÓÃDMA¼Ä´æÆ÷Ö¸Õë²»ÒÆ¶¯À´Åж¨ÊÇ·ñ½ÓÊÕÍê³É*/
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ErrorStatus_STM32 IR_Uart0_Rx_DMA_CH7_Check(void)
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{
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uint16_t timeout_cnt = 0,dma_recv_cnt;
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uint32_t dma_mar_reg_read = DMA_CHxMAR_Read(DMA_CH7);
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if(dma_mar_reg_read != (uint32)uc_recv_para_g.uc_recv_buf_union.uc_recv_buf)
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{
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delay_ms(2);
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while(dma_mar_reg_read != DMA_CHxMAR_Read(DMA_CH7))
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{
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dma_mar_reg_read = DMA_CHxMAR_Read(DMA_CH7);
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delay_ms(2);
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if(timeout_cnt++ > 100)
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break;
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}
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}
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else
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return ERROR_1;
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dma_recv_cnt = dma_mar_reg_read - (uint32)uc_recv_para_g.uc_recv_buf_union.uc_recv_buf;
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if(dma_recv_cnt)
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{
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uc_recv_para_g.uc_recv_length = dma_recv_cnt;
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//½ÓÊÕRAMµØÖ·ÖØÔØ
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DMA_ISR_DMACHFT_Clr(DMA_CH7);
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DMA_CHxCR_ChxEN_Setable(DMA_CH7, DISABLE); //ͨµÀʧÄÜ
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DMA_CHxMAR_Write(DMA_CH7, (uint32)uc_recv_para_g.uc_recv_buf_union.uc_recv_buf);
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DMA_CHxCR_ChxEN_Setable(DMA_CH7, ENABLE); //ͨµÀʹÄÜ
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uc_recv_para_g.uc_recv_flag = SET;//½ÓÊÕÍê³É
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return SUCCESS_0;
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// DMA_GCR_DMAEN_Setable(DISABLE);//DMA×ÜʹÄÜ
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}
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return ERROR_1;
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}
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