/**
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******************************************************************************
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* @file fm33a0xxev_dma.c
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* @author FM33A0XXEV Application Team
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* @version V1.0.0
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* @date 16-April-2020
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* @brief This file provides firmware functions to manage the following
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* functionalities of....:
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*
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "fm33a0xxev_dma.h"
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#include "fm33a0xxev_rmu.h"
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/** @addtogroup fm33a0xxev_StdPeriph_Driver
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* @{
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*/
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/** @defgroup DMA
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* @brief DMA driver modules
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* @{
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*/
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/* DMA´íÎóµØÖ·ÖжÏʹÄÜ
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1£ºÔÊÐí´íÎóµØÖ·ÖжÏ
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0£º½ûÖ¹´íÎóµØÖ·ÖÐ¶Ï Ïà¹Øº¯Êý */
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void DMA_GCR_DMA_ADDRERR_EN_Setable(FunState NewState)
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{
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if (NewState == ENABLE)
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{
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DMA->GCR |= (DMA_GCR_DMA_ADDRERR_EN_Msk);
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}
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else
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{
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DMA->GCR &= ~(DMA_GCR_DMA_ADDRERR_EN_Msk);
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}
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}
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FunState DMA_GCR_DMA_ADDRERR_EN_Getable(void)
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{
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if (DMA->GCR & (DMA_GCR_DMA_ADDRERR_EN_Msk))
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{
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return ENABLE;
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}
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else
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{
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return DISABLE;
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}
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}
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/* DMAÈ«¾ÖʹÄÜ
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1£ºDMAʹÄÜ
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0£ºDMA¹Ø±Õ Ïà¹Øº¯Êý */
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void DMA_GCR_DMAEN_Setable(FunState NewState)
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{
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if (NewState == ENABLE)
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{
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DMA->GCR |= (DMA_GCR_DMAEN_Msk);
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}
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else
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{
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DMA->GCR &= ~(DMA_GCR_DMAEN_Msk);
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}
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}
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FunState DMA_GCR_DMAEN_Getable(void)
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{
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if (DMA->GCR & (DMA_GCR_DMAEN_Msk))
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{
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return ENABLE;
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}
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else
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{
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return DISABLE;
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}
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}
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/* Channelx´«Ê䳤¶È£¬1-8192´Î´«Êä Ïà¹Øº¯Êý */
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void DMA_CHxCR_CHxTSIZE_Set(DMA_CH_Type CHx, uint32_t SetValue)
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{
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uint32_t *pREG;
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uint32_t tmpreg;
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pREG = (uint32_t *)(DMA_BASE + 0x04 + CHx*8);//DMA->CH0CTRL;
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SetValue <<= DMA_CHxCR_CHxTSIZE_Pos;//ÊÖ¹¤Ìí¼Ó
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tmpreg = *pREG;
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tmpreg &= ~(DMA_CHxCR_CHxTSIZE_Msk);
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tmpreg |= (SetValue&DMA_CHxCR_CHxTSIZE_Msk);
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*pREG = tmpreg;
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}
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uint32_t DMA_CHxCR_CHxTSIZE_Get(DMA_CH_Type CHx)
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{
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uint32_t *pREG;
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pREG = (uint32_t *)(DMA_BASE + 0x04 + CHx*8);
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return (uint32_t)((*pREG & DMA_CHxCR_CHxTSIZE_Msk) >> DMA_CHxCR_CHxTSIZE_Pos);
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}
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/* ChannelxÓÅÏȼ¶
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00£ºLow
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01£ºMedium
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10£ºHigh
|
11£ºVery High Ïà¹Øº¯Êý */
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void DMA_CHxCR_CHxPRI_Set(DMA_CH_Type CHx, uint32_t SetValue)
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{
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uint32_t *pREG;
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uint32_t tmpreg;
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pREG = (uint32_t *)(DMA_BASE + 0x04 + CHx*8);//DMA->CH0CTRL;
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tmpreg = *pREG;
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tmpreg &= ~(DMA_CHxCR_CHxPRI_Msk);
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tmpreg |= (SetValue&DMA_CHxCR_CHxPRI_Msk);
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*pREG = tmpreg;
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}
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uint32_t DMA_CHxCR_CHxPRI_Get(DMA_CH_Type CHx)
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{
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uint32_t *pREG;
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pREG = (uint32_t *)(DMA_BASE + 0x04 + CHx*8);
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return (*pREG & DMA_CHxCR_CHxPRI_Msk);
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}
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/* RAMµØÖ·Ôö¼õÉèÖÃ
|
1£ºRAMµØÖ·µÝÔö
|
0£ºRAMµØÖ·µÝ¼õ Ïà¹Øº¯Êý */
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void DMA_CHxCR_CHxINC_Set(DMA_CH_Type CHx, uint32_t SetValue)
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{
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uint32_t *pREG;
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uint32_t tmpreg;
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pREG = (uint32_t *)(DMA_BASE + 0x04 + CHx*8);//DMA->CH0CTRL;
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tmpreg = *pREG;
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tmpreg &= ~(DMA_CHxCR_CHxINC_Msk);
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tmpreg |= (SetValue&DMA_CHxCR_CHxINC_Msk);
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*pREG = tmpreg;
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}
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uint32_t DMA_CHxCR_CHxINC_Get(DMA_CH_Type CHx)
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{
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uint32_t *pREG;
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pREG = (uint32_t *)(DMA_BASE + 0x04 + CHx*8);
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return (*pREG & DMA_CHxCR_CHxINC_Msk);
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}
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/* ChannelxÍâÉèÇëÇóÓ³Éä
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ÿ¸öͨµÀ¿ÉÒÔ½ÓÊÜ8¸öÍâÉèÇëÇó£¬ÍâÉèÇëÇóµÄÓ³Éä²Î¼û23.6.1DMAÇëÇóÓ³Éä Ïà¹Øº¯Êý */
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void DMA_CHxCR_CHxSSEL_Set(DMA_CH_Type CHx, uint32_t SetValue)
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{
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uint32_t *pREG;
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uint32_t tmpreg;
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pREG = (uint32_t *)(DMA_BASE + 0x04 + CHx*8);//DMA->CH0CTRL;
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tmpreg = *pREG;
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tmpreg &= ~(DMA_CHxCR_CHxSSEL_Msk);
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tmpreg |= (SetValue&DMA_CHxCR_CHxSSEL_Msk);
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*pREG = tmpreg;
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}
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uint32_t DMA_CHxCR_CHxSSEL_Get(DMA_CH_Type CHx)
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{
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uint32_t *pREG;
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pREG = (uint32_t *)(DMA_BASE + 0x04 + CHx*8);
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return (*pREG & DMA_CHxCR_CHxSSEL_Msk);
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}
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/* Ñ»·»º³åģʽÏÂ×Ô¶¯¸üд«Êä²ÎÊý£¬±¾ÂÖ´«ÊäÍê³Éºó½«shadow¼Ä´æÆ÷ÄÚÈݸ´ÖƵ½¿ØÖƼĴæÆ÷
|
0£º½ûÖ¹×Ô¶¯¸üÐÂ
|
1£ºÊ¹ÄÜ×Ô¶¯¸üÐÂ
|
×¢Ò⣺½öͨµÀ0~6Ö§³Ö´Ë¹¦ÄÜ£¬Í¨µÀ7~10Î޴˼ĴæÆ÷ Ïà¹Øº¯Êý */
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void DMA_CHxCR_CIRC_UPD_Setable(DMA_CH_Type CHx, FunState NewState)
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{
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uint32_t *pREG;
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pREG = (uint32_t *)(DMA_BASE + 0x04 + CHx*8);
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if (NewState == ENABLE)
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{
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*pREG |= (DMA_CHxCR_CIRC_UPD_Msk);
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}
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else
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{
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*pREG &= ~(DMA_CHxCR_CIRC_UPD_Msk);
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}
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}
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FunState DMA_CHxCR_CIRC_UPD_Getable(DMA_CH_Type CHx)
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{
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uint32_t *pREG;
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pREG = (uint32_t *)(DMA_BASE + 0x04 + CHx*8);;
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if (*pREG & (DMA_CHxCR_CIRC_UPD_Msk))
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{
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return ENABLE;
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}
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else
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{
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return DISABLE;
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}
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}
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/* ͨµÀ´«Êä·½Ïò
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0£º´ÓÍâÉè¶ÁÈ¡Êý¾ÝдÈëRAM
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1£º´ÓRAM¶ÁÈ¡Êý¾ÝдÈëÍâÉè Ïà¹Øº¯Êý */
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void DMA_CHxCR_DIR_Set(DMA_CH_Type CHx, uint32_t SetValue)
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{
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uint32_t *pREG;
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uint32_t tmpreg;
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pREG = (uint32_t *)(DMA_BASE + 0x04 + CHx*8);//DMA->CH0CTRL;
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tmpreg = *pREG;
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tmpreg &= ~(DMA_CHxCR_DIR_Msk);
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tmpreg |= (SetValue&DMA_CHxCR_DIR_Msk);
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*pREG = tmpreg;
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}
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uint32_t DMA_CHxCR_DIR_Get(DMA_CH_Type CHx)
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{
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uint32_t *pREG;
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pREG = (uint32_t *)(DMA_BASE + 0x04 + CHx*8);
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return (*pREG & DMA_CHxCR_DIR_Msk);
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}
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/* ´«Êä´ø¿íÉèÖÃ
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00£º×Ö½Ú£¬8bit
|
01£º°ë×Ö£¬16bit
|
10£º×Ö£¬32bit
|
11£ºRFU Ïà¹Øº¯Êý */
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void DMA_CHxCR_BDW_Set(DMA_CH_Type CHx, uint32_t SetValue)
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{
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uint32_t *pREG;
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uint32_t tmpreg;
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pREG = (uint32_t *)(DMA_BASE + 0x04 + CHx*8);//DMA->CH0CTRL;
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tmpreg = *pREG;
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tmpreg &= ~(DMA_CHxCR_BDW_Msk);
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tmpreg |= (SetValue&DMA_CHxCR_BDW_Msk);
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*pREG = tmpreg;
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}
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uint32_t DMA_CHxCR_BDW_Get(DMA_CH_Type CHx)
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{
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uint32_t *pREG;
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pREG = (uint32_t *)(DMA_BASE + 0x04 + CHx*8);
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return (*pREG & DMA_CHxCR_BDW_Msk);
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}
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/* Ñ»·»º³åģʽ
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0£º¹Ø±ÕÑ»·Ä£Ê½
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1£ºÊ¹ÄÜÑ»·Ä£Ê½ Ïà¹Øº¯Êý */
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void DMA_CHxCR_CIRC_Setable(DMA_CH_Type CHx, FunState NewState)
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{
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uint32_t *pREG;
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pREG = (uint32_t *)(DMA_BASE + 0x04 + CHx*8);
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if (NewState == ENABLE)
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{
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*pREG |= (DMA_CHxCR_CIRC_Msk);
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}
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else
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{
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*pREG &= ~(DMA_CHxCR_CIRC_Msk);
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}
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}
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FunState DMA_CHxCR_CIRC_Getable(DMA_CH_Type CHx)
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{
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uint32_t *pREG;
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pREG = (uint32_t *)(DMA_BASE + 0x04 + CHx*8);;
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if (*pREG & (DMA_CHxCR_CIRC_Msk))
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{
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return ENABLE;
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}
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else
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{
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return DISABLE;
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}
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}
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/* Channelx´«ÊäÍê³ÉÖжÏʹÄÜ
|
1£ºÊ¹ÄÜ´«ÊäÍê³ÉÖжÏ
|
0£º¹Ø±Õ´«ÊäÍê³ÉÖÐ¶Ï Ïà¹Øº¯Êý */
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void DMA_CHxCR_CHxFTIE_Setable(DMA_CH_Type CHx, FunState NewState)
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{
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uint32_t *pREG;
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pREG = (uint32_t *)(DMA_BASE + 0x04 + CHx*8);
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if (NewState == ENABLE)
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{
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*pREG |= (DMA_CHxCR_CHxFTIE_Msk);
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}
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else
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{
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*pREG &= ~(DMA_CHxCR_CHxFTIE_Msk);
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}
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}
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FunState DMA_CHxCR_CHxFTIE_Getable(DMA_CH_Type CHx)
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{
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uint32_t *pREG;
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pREG = (uint32_t *)(DMA_BASE + 0x04 + CHx*8);;
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if (*pREG & (DMA_CHxCR_CHxFTIE_Msk))
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{
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return ENABLE;
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}
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else
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{
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return DISABLE;
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}
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}
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/* Channelx°ë³Ì´«ÊäÍê³ÉÖжÏʹÄÜ
|
1£ºÊ¹ÄÜ°ë³ÌÖжÏ
|
0£º¹Ø±Õ°ë³ÌÖÐ¶Ï Ïà¹Øº¯Êý */
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void DMA_CHxCR_CHxHTIE_Setable(DMA_CH_Type CHx, FunState NewState)
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{
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uint32_t *pREG;
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pREG = (uint32_t *)(DMA_BASE + 0x04 + CHx*8);
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if (NewState == ENABLE)
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{
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*pREG |= (DMA_CHxCR_CHxHTIE_Msk);
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}
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else
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{
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*pREG &= ~(DMA_CHxCR_CHxHTIE_Msk);
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}
|
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}
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FunState DMA_CHxCR_CHxHTIE_Getable(DMA_CH_Type CHx)
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{
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uint32_t *pREG;
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pREG = (uint32_t *)(DMA_BASE + 0x04 + CHx*8);;
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if (*pREG & (DMA_CHxCR_CHxHTIE_Msk))
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{
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return ENABLE;
|
}
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else
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{
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return DISABLE;
|
}
|
}
|
|
/* ChannelxʹÄÜ
|
1£ºÆô¶¯Í¨µÀ0
|
0£º¹Ø±ÕͨµÀ0 Ïà¹Øº¯Êý */
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void DMA_CHxCR_ChxEN_Setable(DMA_CH_Type CHx, FunState NewState)
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{
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uint32_t *pREG;
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pREG = (uint32_t *)(DMA_BASE + 0x04 + CHx*8);
|
if (NewState == ENABLE)
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{
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*pREG |= (DMA_CHxCR_ChxEN_Msk);
|
|
}
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else
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{
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*pREG &= ~(DMA_CHxCR_ChxEN_Msk);
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}
|
|
}
|
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FunState DMA_CHxCR_ChxEN_Getable(DMA_CH_Type CHx)
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{
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uint32_t *pREG;
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pREG = (uint32_t *)(DMA_BASE + 0x04 + CHx*8);;
|
if (*pREG & (DMA_CHxCR_ChxEN_Msk))
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{
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return ENABLE;
|
}
|
else
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{
|
return DISABLE;
|
}
|
}
|
|
/* Channelx´æ´¢Æ÷Ö¸ÕëµØÖ·£¬DMA´«ÊäÆô¶¯Ç°Èí¼þÏò´Ë¼Ä´æÆ÷дÈë´æ´¢Æ÷Ä¿±êµØÖ·¡£
|
µ±Ö¸ÕëÖ¸Ïò¿ÕµØַʱ£¬DMA·ÃÎʽ«´¥·¢hardfault
|
µ±Ö¸ÕëÖ¸ÏòFlashʱ£¬½ûÖ¹ÏòFlashдÈëÊý¾Ý¡£
|
Èí¼þ¿ÉÒÔ²éѯµ±Ç°DMA´«ÊäµÄÄ¿±ê´æ´¢Æ÷µØÖ·¡£
|
|
×¢Ò⣺´ËÖ¸Õë½ûÖ¹Ö¸Ïò0x00080000~0x1FFFFFFFµØÖ·£¬Õâ¶ÎµØַΪflash±£ÁôÐÅÏ¢Çø£¬Ö¸ÏòÕâ¶ÎµØÖ·¿ÉÄÜÔÚDMA·ÃÎÊÖе¼Ö²»¿ÉÔ¤¼ÆµÄ½á¹û Ïà¹Øº¯Êý */
|
void DMA_CHxMAR_Write(DMA_CH_Type CHx, uint32_t SetValue)
|
{
|
uint32_t *pREG;
|
pREG = (uint32_t *)(DMA_BASE + 8 + CHx*8);
|
*pREG = SetValue;
|
}
|
|
uint32_t DMA_CHxMAR_Read(DMA_CH_Type CHx)
|
{
|
uint32_t *pREG;
|
pREG = (uint32_t *)(DMA_BASE + 8 + CHx*8);
|
return (*pREG);
|
}
|
|
/* Channel11´«Ê䳤¶È£¬1-8192´Î´«Ê䣬½öÔÚFlash->RAM´«ÊäʱÓÐЧ£¬RAM->Flash´«ÊäΪ¹Ì¶¨³¤¶È64´Î´«Êä Ïà¹Øº¯Êý */
|
void DMA_CH11CR_CH11TSIZE_Set(uint32_t SetValue)
|
{
|
uint32_t tmpreg;
|
|
SetValue <<= DMA_CH11CR_CH11TSIZE_Pos;
|
|
tmpreg = DMA->CH11CR;
|
tmpreg &= ~(DMA_CH11CR_CH11TSIZE_Msk);
|
tmpreg |= (SetValue & DMA_CH11CR_CH11TSIZE_Msk);
|
DMA->CH11CR = tmpreg;
|
}
|
|
uint32_t DMA_CH11CR_CH11TSIZE_Get(void)
|
{
|
return (uint32_t)((DMA->CH11CR & DMA_CH11CR_CH11TSIZE_Msk) >> DMA_CH11CR_CH11TSIZE_Pos);
|
}
|
|
/* Channel11ÓÅÏȼ¶
|
00£ºLow
|
01£ºMedium
|
10£ºHigh
|
11£ºVery High Ïà¹Øº¯Êý */
|
void DMA_CH11CR_CH11PRI_Set(uint32_t SetValue)
|
{
|
uint32_t tmpreg;
|
tmpreg = DMA->CH11CR;
|
tmpreg &= ~(DMA_CH11CR_CH11PRI_Msk);
|
tmpreg |= (SetValue & DMA_CH11CR_CH11PRI_Msk);
|
DMA->CH11CR = tmpreg;
|
}
|
|
uint32_t DMA_CH11CR_CH11PRI_Get(void)
|
{
|
return (DMA->CH11CR & DMA_CH11CR_CH11PRI_Msk);
|
}
|
|
/* Channel11´«Êä·½Ïò
|
1£ºFlash->RAM´«Êä
|
0£ºRAM->Flash´«Êä Ïà¹Øº¯Êý */
|
void DMA_CH11CR_CH11DIR_Set(uint32_t SetValue)
|
{
|
uint32_t tmpreg;
|
tmpreg = DMA->CH11CR;
|
tmpreg &= ~(DMA_CH11CR_CH11DIR_Msk);
|
tmpreg |= (SetValue & DMA_CH11CR_CH11DIR_Msk);
|
DMA->CH11CR = tmpreg;
|
}
|
|
uint32_t DMA_CH11CR_CH11DIR_Get(void)
|
{
|
return (DMA->CH11CR & DMA_CH11CR_CH11DIR_Msk);
|
}
|
|
/* Channel11 RAMµØÖ·Ôö¼õÉèÖ㬽öÔÚFlash->RAM´«ÊäÖÐÓÐЧ
|
1£ºRAMµØÖ·µÝÔö
|
0£ºRAMµØÖ·µÝ¼õ Ïà¹Øº¯Êý */
|
void DMA_CH11CR_CH11RI_Set(uint32_t SetValue)
|
{
|
uint32_t tmpreg;
|
tmpreg = DMA->CH11CR;
|
tmpreg &= ~(DMA_CH11CR_CH11RI_Msk);
|
tmpreg |= (SetValue & DMA_CH11CR_CH11RI_Msk);
|
DMA->CH11CR = tmpreg;
|
}
|
|
uint32_t DMA_CH11CR_CH11RI_Get(void)
|
{
|
return (DMA->CH11CR & DMA_CH11CR_CH11RI_Msk);
|
}
|
|
/* Channel11 FlashµØÖ·Ôö¼õÉèÖ㬽öÔÚFlash->RAM´«ÊäÖÐÓÐЧ
|
1£ºFlashµØÖ·µÝÔö
|
0£ºFlashµØÖ·µÝ¼õ Ïà¹Øº¯Êý */
|
void DMA_CH11CR_CH11FI_Set(uint32_t SetValue)
|
{
|
uint32_t tmpreg;
|
tmpreg = DMA->CH11CR;
|
tmpreg &= ~(DMA_CH11CR_CH11FI_Msk);
|
tmpreg |= (SetValue & DMA_CH11CR_CH11FI_Msk);
|
DMA->CH11CR = tmpreg;
|
}
|
|
uint32_t DMA_CH11CR_CH11FI_Get(void)
|
{
|
return (DMA->CH11CR & DMA_CH11CR_CH11FI_Msk);
|
}
|
|
/* Channel11´«ÊäÍê³ÉÖжÏʹÄÜ
|
1£ºÊ¹ÄÜ´«ÊäÍê³ÉÖжÏ
|
0£º¹Ø±Õ´«ÊäÍê³ÉÖÐ¶Ï Ïà¹Øº¯Êý */
|
void DMA_CH11CR_CH11FTIE_Setable(FunState NewState)
|
{
|
if (NewState == ENABLE)
|
{
|
DMA->CH11CR |= (DMA_CH11CR_CH11FTIE_Msk);
|
}
|
else
|
{
|
DMA->CH11CR &= ~(DMA_CH11CR_CH11FTIE_Msk);
|
}
|
}
|
|
FunState DMA_CH11CR_CH11FTIE_Getable(void)
|
{
|
if (DMA->CH11CR & (DMA_CH11CR_CH11FTIE_Msk))
|
{
|
return ENABLE;
|
}
|
else
|
{
|
return DISABLE;
|
}
|
}
|
|
/* Channel11°ë³Ì´«ÊäÍê³ÉÖжÏʹÄÜ
|
1£ºÊ¹ÄÜ°ë³ÌÖжÏ
|
0£º¹Ø±Õ°ë³ÌÖÐ¶Ï Ïà¹Øº¯Êý */
|
void DMA_CH11CR_CH11HTIE_Setable(FunState NewState)
|
{
|
if (NewState == ENABLE)
|
{
|
DMA->CH11CR |= (DMA_CH11CR_CH11HTIE_Msk);
|
}
|
else
|
{
|
DMA->CH11CR &= ~(DMA_CH11CR_CH11HTIE_Msk);
|
}
|
}
|
|
FunState DMA_CH11CR_CH11HTIE_Getable(void)
|
{
|
if (DMA->CH11CR & (DMA_CH11CR_CH11HTIE_Msk))
|
{
|
return ENABLE;
|
}
|
else
|
{
|
return DISABLE;
|
}
|
}
|
|
/* Channel11ʹÄÜ
|
1£ºÆô¶¯Í¨µÀ0
|
0£º¹Ø±ÕͨµÀ0 Ïà¹Øº¯Êý */
|
void DMA_CH11CR_CH11EN_Setable(FunState NewState)
|
{
|
if (NewState == ENABLE)
|
{
|
DMA->CH11CR |= (DMA_CH11CR_CH11EN_Msk);
|
}
|
else
|
{
|
DMA->CH11CR &= ~(DMA_CH11CR_CH11EN_Msk);
|
}
|
}
|
|
FunState DMA_CH11CR_CH11EN_Getable(void)
|
{
|
if (DMA->CH11CR & (DMA_CH11CR_CH11EN_Msk))
|
{
|
return ENABLE;
|
}
|
else
|
{
|
return DISABLE;
|
}
|
}
|
|
/* Channel11 FlashÖ¸ÕëµØÖ·£¬DMA´«ÊäÆô¶¯Ç°Èí¼þÏò´Ë¼Ä´æÆ÷дÈëFlashÄ¿±êµØÖ·£¬DMAÆô¶¯ºó´Ë¼Ä´æÆ÷ËæDMA´«Êä×ÔÔö»ò×Ô¼õ
|
Èí¼þ¿ÉÒÔ²éѯµ±Ç°DMA´«ÊäµÄÄ¿±êFlashµØÖ·
|
´Ë¼Ä´æÆ÷µÍ루bit5-0£©½öÔÚFlash->RAM´«ÊäÖÐÓÐЧ£¬RAM->Flash´«ÊäÖÐĬÈ϶ÔÆëFlashµÄhalf-sectorÆðʼµØÖ· Ïà¹Øº¯Êý */
|
void DMA_CH11FAR_Write(uint32_t SetValue)
|
{
|
DMA->CH11FAR = ((SetValue >> 2) & DMA_CH11FAR_CH11FLSAD_Msk);
|
}
|
|
uint32_t DMA_CH11FAR_Read(void)
|
{
|
return (DMA->CH11FAR & DMA_CH11FAR_CH11FLSAD_Msk);
|
}
|
|
/* Channel7 RAM×ÖÖ¸ÕëµØÖ·£¬DMA´«ÊäÆô¶¯Ç°Èí¼þÏò´Ë¼Ä´æÆ÷дÈëRAMÄ¿±êµØÖ·£¨wordµØÖ·£©£¬DMAÆô¶¯ºó´Ë¼Ä´æÆ÷ËæDMA´«Êä×ÔÔö»ò×Ô¼õ
|
Èí¼þ¿ÉÒÔ²éѯµ±Ç°DMA´«ÊäµÄÄ¿±êRAMµØÖ· Ïà¹Øº¯Êý */
|
void DMA_CH11RAR_Write(uint32_t SetValue)
|
{
|
DMA->CH11RAR = ((SetValue >> 2) & DMA_CH11RAR_CH7RAMAD_Msk);
|
}
|
|
uint32_t DMA_CH11RAR_Read(void)
|
{
|
return (DMA->CH11RAR & DMA_CH11RAR_CH7RAMAD_Msk);
|
}
|
|
/* DMA´«ÊäµØÖ·´íÎó±êÖ¾£¬µ±´æ´¢Æ÷Ö¸Õ볬¹ýRAMºÍFlashºÏ·¨µØÖ··¶Î§Ê±ÖÃλ Ïà¹Øº¯Êý */
|
void DMA_ISR_DMA_ADDRERR_Clr(void)
|
{
|
DMA->ISR = DMA_ISR_DMA_ADDRERR_Msk;
|
}
|
|
FlagStatus DMA_ISR_DMA_ADDRERR_Chk(void)
|
{
|
if (DMA->ISR & DMA_ISR_DMA_ADDRERR_Msk)
|
{
|
return SET;
|
}
|
else
|
{
|
return RESET;
|
}
|
}
|
|
/* DMAͨµÀx´«ÊäÍê³É±êÖ¾£¬Ó²¼þÖÃ룬Èí¼þд1ÇåÁã
|
1£º¶ÔӦͨµÀ´«ÊäÍê³É
|
0£º¶ÔӦͨµÀ´«ÊäδÍê³É Ïà¹Øº¯Êý */
|
void DMA_ISR_DMACHFT_Clr(DMA_CH_Type CHx)
|
{
|
DMA->ISR = ((1 << DMA_ISR_DMACHFT_Pos) << CHx);
|
}
|
|
FlagStatus DMA_ISR_DMACHFT_Chk(DMA_CH_Type CHx)
|
{
|
if (DMA->ISR & ((1 << DMA_ISR_DMACHFT_Pos) << CHx))
|
{
|
return SET;
|
}
|
else
|
{
|
return RESET;
|
}
|
}
|
|
/* DMAͨµÀx´«Êä°ë³Ì±êÖ¾£¬Ó²¼þÖÃ룬Èí¼þд1ÇåÁã Ïà¹Øº¯Êý */
|
void DMA_ISR_DMACHHT_Clr(DMA_CH_Type CHx)
|
{
|
DMA->ISR = (1 << DMA_ISR_DMACHHT_Pos) << CHx;
|
}
|
|
FlagStatus DMA_ISR_DMACHHT_Chk(DMA_CH_Type CHx)
|
{
|
if (DMA->ISR & ((1 << DMA_ISR_DMACHHT_Pos) << CHx))
|
{
|
return SET;
|
}
|
else
|
{
|
return RESET;
|
}
|
}
|
|
/* Channelx´«Ê䳤¶Èshadow¼Ä´æÆ÷£»Ñ»·Ä£Ê½ÏÂÈç¹ûʹÄÜÁËCIRC_UPD¼Ä´æÆ÷£¬ÔòÔÚ±¾ÂÖ´«ÊäÍê³Éºó½«shadow¼Ä´æÆ÷Öµ¸´ÖƵ½CHxTSIZEÖС£ Ïà¹Øº¯Êý */
|
void DMA_CHxCSR_CHxTSIZE_SDW_Set(DMA_CH_Type CHx, uint32_t SetValue)
|
{
|
|
uint32_t *pREG;
|
uint32_t tmpreg;
|
pREG = (uint32_t *)(DMA_BASE + 0x100 + CHx*8);//DMA->CH0CTRL;
|
SetValue <<= DMA_CHxCSR_CHxTSIZE_SDW_Pos;//ÊÖ¹¤Ìí¼Ó
|
|
tmpreg = *pREG;
|
tmpreg &= ~(DMA_CHxCSR_CHxTSIZE_SDW_Msk);
|
tmpreg |= (SetValue&DMA_CHxCSR_CHxTSIZE_SDW_Msk);
|
*pREG = tmpreg;
|
|
}
|
|
uint32_t DMA_CHxCSR_CHxTSIZE_SDW_Get(DMA_CH_Type CHx)
|
{
|
uint32_t *pREG;
|
pREG = (uint32_t *)(DMA_BASE + 0x100 + CHx*8);
|
return (uint32_t)((*pREG & DMA_CHxCSR_CHxTSIZE_SDW_Msk) >> DMA_CHxCSR_CHxTSIZE_SDW_Pos);
|
}
|
|
/* RAMµØÖ·Ôö¼õÉèÖÃshadow¼Ä´æÆ÷£¬Ñ»·Ä£Ê½ÏÂÈç¹ûʹÄÜÁËCIRC_UPD¼Ä´æÆ÷£¬ÔòÔÚ±¾ÂÖ´«ÊäÍê³Éºó½«shadow¼Ä´æÆ÷Öµ¸´ÖƵ½CHxTSIZEÖС£ Ïà¹Øº¯Êý */
|
void DMA_CHxCSR_CHxINC_SDW_Set(DMA_CH_Type CHx, uint32_t SetValue)
|
{
|
uint32_t *pREG;
|
uint32_t tmpreg;
|
pREG = (uint32_t *)(DMA_BASE + 0x100 + CHx*8);//DMA->CH0CTRL;
|
|
tmpreg = *pREG;
|
tmpreg &= ~(DMA_CHxCSR_CHxINC_SDW_Msk);
|
tmpreg |= (SetValue&DMA_CHxCSR_CHxINC_SDW_Msk);
|
*pREG = tmpreg;
|
|
}
|
|
uint32_t DMA_CHxCSR_CHxINC_SDW_Get(DMA_CH_Type CHx)
|
{
|
uint32_t *pREG;
|
pREG = (uint32_t *)(DMA_BASE + 0x100 + CHx*8);
|
return (*pREG & DMA_CHxCSR_CHxINC_SDW_Msk);
|
}
|
|
/* Channelx´æ´¢Æ÷Ö¸ÕëµØÖ·Ó°×ӼĴæÆ÷¡£
|
Ñ»·Ä£Ê½ÏÂÈç¹ûʹÄÜÁËCIRC_UPD¼Ä´æÆ÷£¬ÔòÔÚ±¾ÂÖ´«ÊäÍê³Éºó½«shadow¼Ä´æÆ÷Öµ¸´ÖƵ½CHxMEMADÖС£ Ïà¹Øº¯Êý */
|
void DMA_CHxMASR_Write(DMA_CH_Type CHx, uint32_t SetValue)
|
{
|
uint32_t *pREG;
|
pREG = (uint32_t *)(DMA_BASE + 0x104 + CHx*8);
|
*pREG = SetValue;
|
}
|
|
uint32_t DMA_CHxMASR_Read(DMA_CH_Type CHx)
|
{
|
uint32_t *pREG;
|
pREG = (uint32_t *)(DMA_BASE + 0x104 + CHx*8);
|
return (*pREG);
|
}
|
|
|
void DMA_DeInit(void)
|
{
|
RMU_PRSTEN_Write(0x13579BDF);
|
RMU_AHBRST_DMARST_Setable(ENABLE);
|
RMU_AHBRST_DMARST_Setable(DISABLE);
|
RMU_PRSTEN_Write(0x00000000);
|
}
|
|
void DMA_Init(DMA_InitTypeDef *para)
|
{
|
if (DMA_CH11 == para->CHx)
|
{
|
DMA_CHxCR_ChxEN_Setable(para->CHx, DISABLE); // ͨµÀ¹Ø±ÕʹÄÜ
|
DMA_CH11CR_CH11TSIZE_Set(para->CHxTSIZE); // ͨµÀ´«Ê䳤¶È
|
DMA_CH11CR_CH11PRI_Set(para->CHxPRI); // ͨµÀÓÅÏȼ¶
|
DMA_CH11CR_CH11DIR_Set(para->CHxDIR); // Êý¾Ý´«Êä·½Ïò
|
DMA_CH11CR_CH11RI_Set(para->CH11RI); // RAMÔö³¤·½Ïò
|
DMA_CH11CR_CH11FI_Set(para->CH11FI); // FLSÔö³¤·½Ïò
|
DMA_CH11CR_CH11FTIE_Setable(para->CHxFTIE); // ´«ÊäÍê³ÉÖжÏ
|
DMA_CH11CR_CH11HTIE_Setable(para->CHxHTIE); // ´«Êä°ëÂúÖжÏ
|
|
DMA_CHxMAR_Write(para->CHx, para->CHxRAMAD); // DMA´«ÊäRAMµØÖ·
|
DMA_CH11FAR_Write(para->CH11FLSAD); // DMA´«ÊäFlashµØÖ·
|
|
DMA_CH11CR_CH11EN_Setable(para->CHxEN); // ͨµÀʹÄÜ
|
}
|
else
|
{
|
DMA_CHxCR_ChxEN_Setable(para->CHx, DISABLE); // ͨµÀ¹Ø±ÕʹÄÜ
|
DMA_CHxCR_CHxTSIZE_Set(para->CHx, para->CHxTSIZE); // ͨµÀ´«Ê䳤¶È
|
DMA_CHxCR_CHxPRI_Set(para->CHx, para->CHxPRI); // ͨµÀÓÅÏȼ¶
|
DMA_CHxCR_CHxINC_Set(para->CHx, para->CHxINC); // ͨµÀµØÖ·Ôö³¤·½Ïò
|
DMA_CHxCR_CHxSSEL_Set(para->CHx, para->CHxSSEL); // ͨµÀÍâÉèÑ¡Ôñ
|
DMA_CHxCR_DIR_Set(para->CHx, para->CHxDIR); // ͨµÀ´«Êä·½Ïò
|
DMA_CHxCR_BDW_Set(para->CHx, para->CHxBDW); // ͨµÀ´«Êä´ø¿í
|
DMA_CHxCR_CIRC_Setable(para->CHx, para->CHxCICR); // Ñ»·»º³åģʽ
|
DMA_CHxCR_CHxFTIE_Setable(para->CHx, para->CHxFTIE); // ´«ÊäÍê³ÉÖжÏ
|
DMA_CHxCR_CHxHTIE_Setable(para->CHx, para->CHxHTIE); // ´«Êä°ëÂúÖжÏ
|
|
DMA_CHxMAR_Write(para->CHx, para->CHxRAMAD); // DMA´«ÊäRAMµØÖ·
|
|
DMA_CHxCR_ChxEN_Setable(para->CHx, para->CHxEN); // ͨµÀʹÄÜ
|
}
|
}
|
|
|
/******END OF FILE****/
|
