Ø 1Õ: ÜÙ ..\Soft\check_out.h ®ëʯ ÞÙ! ..\Core\define_all.h ëʯ ¢Ù) ..\Core\Include\FM33A0XXEV.h ëʯ ÀÙ+ ..\Core\Include\core_cm0plus.h ëʯ ¥ÙD 8D:\Program Files\MDK5\ARM\ARMCC\Bin\..\include\stdint.h © 7Ù+ ..\Core\Include\core_cminstr.h ëʯ iÙ* ..\Core\Include\core_cmfunc.h ëʯ ïÙ0 $..\Core\Include\system_FM33A0XXEV.h ëʯ ®ÙC 7D:\Program Files\MDK5\ARM\ARMCC\Bin\..\include\stdio.h Âù¸ô Ù) ..\Core\Include\FM33A0XXEV.h ëʯ ÀÙ- !..\Core\fm33a0xxev_include_all.h ëʯ Ù( ..\Drivers\fm33a0xxev_aes.h ëʯ Ù( ..\Drivers\fm33a0xxev_adc.h ëʯ %Ù* ..\Drivers\fm33a0xxev_bstim.h ëʯ *Ù) ..\Drivers\fm33a0xxev_comp.h ëʯ Ù( ..\Drivers\fm33a0xxev_rmu.h ëʯ ùÙ( ..\Drivers\fm33a0xxev_crc.h ëʯ Ù( ..\Drivers\fm33a0xxev_lcd.h ëʯ Ù( ..\Drivers\fm33a0xxev_dma.h ëʯ Ù) ..\Drivers\fm33a0xxev_gpio.h ëʯ Ù( ..\Drivers\fm33a0xxev_i2c.h ëʯ OÙ) ..\Drivers\fm33a0xxev_iwdt.h ëʯ Ù+ ..\Drivers\fm33a0xxev_lpuart.h ëʯ ¯Ù* ..\Drivers\fm33a0xxev_flash.h ëʯ ;Ù( ..\Drivers\fm33a0xxev_pmu.h ëʯ ûÙ( ..\Drivers\fm33a0xxev_cmu.h ëʯ Ù( ..\Drivers\fm33a0xxev_rtc.h ëʯ Ù( ..\Drivers\fm33a0xxev_dbg.h ëʯ Ù( ..\Drivers\fm33a0xxev_spi.h ëʯ Ù( ..\Drivers\fm33a0xxev_rng.h ëʯ Ù* ..\Drivers\fm33a0xxev_u7816.h ëʯ þÙ) ..\Drivers\fm33a0xxev_uart.h ëʯ Ù* ..\Drivers\fm33a0xxev_lptim.h ëʯ #Ù) ..\Drivers\fm33a0xxev_wwdt.h ëʯ
Ù( ..\Drivers\fm33a0xxev_svd.h ëʯ Ù( ..\Drivers\fm33a0xxev_pae.h ëʯ Ù) ..\Drivers\fm33a0xxev_hash.h ëʯ §Ù) ..\Drivers\fm33a0xxev_qspi.h ëʯ Ù' ..\Drivers\fm33a0xxev_bt.h ëʯ yÙ' ..\Drivers\fm33a0xxev_et.h ëʯ vÙ) ..\Drivers\fm33a0xxev_vrtc.h ëʯ Ù) ..\Drivers\fm33a0xxev_cdif.h ëʯ µÙD 8D:\Program Files\MDK5\ARM\ARMCC\Bin\..\include\string.h Âù¸ô Ù ..\Core\bintohex.h ëʯ HÙ* ..\Hardware\CLOCK\user_init.h ëʯ TÙ! ..\Core\define_all.h ëʯ ¢Ù& ..\Hardware\DELAY\delay.h ëʯ Ù$ ..\Hardware\GPIO\gpio.h ± }Ù ..\Soft\check_out.c ®ëʯ äÚ P _CHECK_OUT_H_ Ú P __DEFINEALL_H__ Ú P RCHFCLKCFG êÚ P clkmode ÞÚ P
|
SYSCLKdef ±Ú 8
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<unnamed> SÚ " B08 Ú 8
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<unnamed> QÚ " bit0 RÚ " bit1 QÚ " bit2 PÚ " bit3 OÚ " bit4 NÚ " bit5 MÚ " bit6 LÚ " bit7 KÚ " Bit Ú B08_Bit ËÚ
|
SUCCESS_0 CÚ ERROR_1 ÕÚ ErrorStatus_STM32 Ú P uint08 Ú P uint16 Ú P uint32 Ú P int08 Ú P int16 Ú P int32 Ú P
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IN_NORMAL úÚ P
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IN_PULLUP áÚ P OUT_PUSHPULL ßÚ P OUT_OPENDRAIN ºÚ P ALTFUN_NORMAL ¿Ú P ALTFUN_OPENDRAIN âÚ P ALTFUN_PULLUP ¦Ú P ALTFUN_OPENDRAIN_PULLUP Ú P FM33A0XXEV_H WÚ P __cplusplus
|
Ú RESET pÚ SET Ú FlagStatus ïÚ ITStatus ÐÚ DISABLE ûÚ ENABLE JÚ FunState ÇÚ FAIL ÙÚ PASS ¾Ú ErrorStatus ]Ú P __RCHF_INITIAL_CLOCK Ú P __RCMF_CLOCK Ú P __RCLP_CLOCK ùÚ P __XTLF_CLOCK ìÚ Reset_IRQn -Ú NMI_IRQn PÚ HardFault_IRQn Ú SVC_IRQn HÚ PendSV_IRQn þÚ SysTick_IRQn bÚ
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WWDT_IRQn ìÚ SVD_IRQn GÚ RTC_IRQn KÚ FLASH_IRQn ÂÚ CMU_IRQn OÚ ADC_IRQn lÚ
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SPI0_IRQn Ú
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SPI1_IRQn Ú
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SPI2_IRQn Ú UART0_IRQn ÄÚ UART1_IRQn ÃÚ UART2_IRQn ÂÚ UART3_IRQn ÁÚ UART4_IRQn ÀÚ UART5_IRQn ¿Ú U7816_IRQn Ú LPUART0_IRQn $Ú
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I2Cx_IRQn üÚ RSV_IRQn 9Ú CRYPTO_IRQn MÚ LPTIM_IRQn ªÚ DMA_IRQn bÚ WKUPx_IRQn qÚ
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COMP_IRQn Ú BTx_IRQn &Ú
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QSPI_IRQn õÚ ETx_IRQn #Ú BSTIM_IRQn ±Ú
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SPI3_IRQn Ú
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SPI4_IRQn Ú
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GPIO_IRQn Ú LPUART1_IRQn #Ú
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IRQn_Type Ú P
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__CM0_REV ïÚ P __MPU_PRESENT Ú P __VTOR_PRESENT &Ú P __NVIC_PRIO_BITS Ú P __Vendor_SysTickConfig ôÚ P __ARMCC_VERSION Ú! P __CORE_CM0PLUS_H_GENERIC NÚ P __stdint_h Ú P __ARMCLIB_VERSION lÚ P __INT64_TYPE__ ;Ú P __INT64 ªÚ P __INT64_C_SUFFIX__ Ú P __PASTE2 NÚ P __PASTE Ú P
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__INT64_C Ú P __UINT64_C Ú P __LONGLONG Ú P __STDINT_DECLS QÚ P __CLIBNS BÚ int8_t Ú int16_t nÚ int32_t pÚ int64_t kÚ uint8_t (Ú uint16_t ÷Ú uint32_t ùÚ uint64_t ôÚ int_least8_t Ú int_least16_t êÚ int_least32_t ìÚ int_least64_t çÚ uint_least8_t ¤Ú uint_least16_t sÚ uint_least32_t uÚ uint_least64_t pÚ int_fast8_t Ú int_fast16_t WÚ int_fast32_t YÚ int_fast64_t TÚ uint_fast8_t Ú uint_fast16_t àÚ uint_fast32_t âÚ uint_fast64_t ÝÚ P __sizeof_ptr ®Ú intptr_t }Ú
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uintptr_t Ú intmax_t Ú
|
uintmax_t Ú P INT8_MIN UÚ P
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INT16_MIN $Ú P
|
INT32_MIN &Ú P
|
INT64_MIN !Ú P INT8_MAX SÚ P
|
INT16_MAX "Ú P
|
INT32_MAX $Ú P
|
INT64_MAX Ú P
|
UINT8_MAX üÚ P UINT16_MAX ËÚ P UINT32_MAX ÍÚ P UINT64_MAX ÈÚ P INT_LEAST8_MIN qÚ P INT_LEAST16_MIN @Ú P INT_LEAST32_MIN BÚ P INT_LEAST64_MIN =Ú P INT_LEAST8_MAX oÚ P INT_LEAST16_MAX >Ú P INT_LEAST32_MAX @Ú P INT_LEAST64_MAX ;Ú P UINT_LEAST8_MAX Ú P UINT_LEAST16_MAX çÚ P UINT_LEAST32_MAX éÚ P UINT_LEAST64_MAX äÚ P INT_FAST8_MIN ¾Ú P INT_FAST16_MIN Ú P INT_FAST32_MIN Ú P INT_FAST64_MIN Ú P INT_FAST8_MAX ¼Ú P INT_FAST16_MAX Ú P INT_FAST32_MAX Ú P INT_FAST64_MAX Ú P UINT_FAST8_MAX eÚ P UINT_FAST16_MAX 4Ú P UINT_FAST32_MAX 6Ú P UINT_FAST64_MAX 1Ú P INTPTR_MIN Ú P INTPTR_MAX Ú P UINTPTR_MAX :Ú P INTMAX_MIN £Ú P INTMAX_MAX ¡Ú P UINTMAX_MAX JÚ P PTRDIFF_MIN cÚ P PTRDIFF_MAX aÚ P SIG_ATOMIC_MIN mÚ P SIG_ATOMIC_MAX kÚ P SIZE_MAX ;Ú P
|
WCHAR_MIN Ú P
|
WCHAR_MAX ÿÚ P WINT_MIN 6Ú P WINT_MAX 4Ú P INT8_C úÚ P INT16_C ÉÚ P INT32_C ËÚ P INT64_C ÆÚ P UINT8_C £Ú P UINT16_C rÚ P UINT32_C tÚ P UINT64_C oÚ P INTMAX_C HÚ P
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UINTMAX_C ñÚ u8 PÚ u16 Ú u32 !Ú uint8 ÿÚ% P __CM0PLUS_CMSIS_VERSION_MAIN êÚ$ P __CM0PLUS_CMSIS_VERSION_SUB 'Ú P __CM0PLUS_CMSIS_VERSION xÚ P __CORTEX_M xÚ P __CC_ARM 6Ú P __ASM "Ú P __INLINE >Ú P __STATIC_INLINE Ú P __NO_RETURN Ú P __USED ÐÚ P __WEAK ÙÚ P __UNALIGNED_UINT32 NÚ P __FPU_USED ~Ú P __CORE_CMINSTR_H Ú P __NOP Ú P __WFI Ú P __WFE !Ú P __SEV Ú P __ISB %Ú P __DSB *Ú P __DMB 0Ú P __REV Ú P __NO_EMBEDDED_ASM Ú __REV16 ÔÚ ,
|
" ãvalue ²Ú __REVSH Ú ," åvalue ²Ú P __ROR Ú P __BKPT ÐÚ __RBIT ùÚ ,
|
" évalue ¬Ú
|
" éresult LÚ " és Ú P __CLZ Ú P __GNUC__ Ú P __CORE_CMFUNC_H Ú __get_CONTROL \Ú
|
" ð __regControl ÷Ú __set_CONTROL PÚ ,
|
" òcontrol »Ú
|
" ò __regControl õÚ __get_IPSR EÚ
|
" õ
|
__regIPSR Ú __get_APSR MÚ
|
" ÷
|
__regAPSR ¡Ú __get_xPSR Ú
|
" ù
|
__regXPSR Ú
|
__get_PSP Ú#
|
" û__regProcessStackPointer ÿÚ
|
__set_PSP Ú ,
|
" ýtopOfProcStack Ú#
|
" ý__regProcessStackPointer ýÚ
|
__get_MSP Ú
|
" __regMainStackPointer ÙÚ
|
__set_MSP Ú ,
|
" topOfMainStack Ú
|
" __regMainStackPointer ×Ú __get_PRIMASK fÚ
|
"
__regPriMask Ú __set_PRIMASK ZÚ ,
|
" priMask OÚ
|
" __regPriMask Ú P __CMSIS_GENERIC Ú# P __CORE_CM0PLUS_H_DEPENDANT ´Ú P __I ¾Ú P __O ¸Ú P __IO mÚ P __IM oÚ P __OM iÚ P __IOM Ú 8
|
<unnamed> SÚ 8
|
<unnamed> QÚ
|
" _reserved0 1Ú
|
" V ÜÚ
|
" C ïÚ
|
" Z ØÚ
|
" N äÚ " b ¿Ú
|
" w ¼Ú
|
APSR_Type ¸Ú P APSR_N_Pos CÚ P APSR_N_Msk JÚ P APSR_Z_Pos 7Ú P APSR_Z_Msk >Ú P APSR_C_Pos NÚ P APSR_C_Msk UÚ P APSR_V_Pos ;Ú P APSR_V_Msk BÚ 8
|
<unnamed> SÚ 8
|
<unnamed> QÚ
|
" ¥ISR .Ú
|
" ¥ _reserved0 Ú " ¤b Ú
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" ¤w ªÚ
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IPSR_Type °Ú P IPSR_ISR_Pos Ú P IPSR_ISR_Msk Ú 8
|
<unnamed> SÚ 8
|
<unnamed> QÚ
|
" ®ISR %Ú
|
" ® _reserved0 Ú
|
" ®T ÃÚ
|
" ® _reserved1 Ú
|
" ®V ÁÚ
|
" ®C ÔÚ
|
" ®Z ½Ú
|
" ®N ÉÚ " b ¤Ú
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" w ¡Ú
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xPSR_Type Ú P xPSR_N_Pos Ú P xPSR_N_Msk Ú P xPSR_Z_Pos Ú P xPSR_Z_Msk Ú P xPSR_C_Pos Ú P xPSR_C_Msk Ú P xPSR_V_Pos Ú P xPSR_V_Msk Ú P xPSR_T_Pos Ú P xPSR_T_Msk Ú P xPSR_ISR_Pos hÚ P xPSR_ISR_Msk oÚ 8
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<unnamed> SÚ 8
|
<unnamed> QÚ
|
" ÇnPRIV GÚ
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" ÇSPSEL oÚ
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" Ç _reserved1 üÚ " Æb Ú
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" Æw Ú CONTROL_Type ÇÚ P CONTROL_SPSEL_Pos Ú P CONTROL_SPSEL_Msk Ú P CONTROL_nPRIV_Pos éÚ P CONTROL_nPRIV_Msk ðÚ 8
|
<unnamed> QÚ <" ÒISER Ú <" |Ò
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RESERVED0 ©Ú <" ÒICER Ú <" |Ò RSERVED1 ïÚ <" ÒISPR }Ú <" |Ò
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RESERVED2 §Ú <" ÒICPR Ú <" |Ò
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RESERVED3 ¦Ú <" Ò
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RESERVED4 Ú <" ÒIP
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Ú
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NVIC_Type ¾Ú 8
|
<unnamed> QÚ
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" ÞCPUID jÚ
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" ÞICSR °Ú
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" ÞVTOR Ú
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" ÞAIRCR nÚ
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" ÞSCR ûÚ
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" ÞCCR Ú
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" Þ
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RESERVED1 FÚ <" ÞSHP ÂÚ
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" ÞSHCSR \Ú SCB_Type Ú" P SCB_CPUID_IMPLEMENTER_Pos »Ú" P SCB_CPUID_IMPLEMENTER_Msk ÂÚ P SCB_CPUID_VARIANT_Pos ðÚ P SCB_CPUID_VARIANT_Msk ÷Ú# P SCB_CPUID_ARCHITECTURE_Pos xÚ# P SCB_CPUID_ARCHITECTURE_Msk Ú P SCB_CPUID_PARTNO_Pos 3Ú P SCB_CPUID_PARTNO_Msk :Ú P SCB_CPUID_REVISION_Pos Ú P SCB_CPUID_REVISION_Msk Ú P SCB_ICSR_NMIPENDSET_Pos NÚ P SCB_ICSR_NMIPENDSET_Msk UÚ P SCB_ICSR_PENDSVSET_Pos Ú P SCB_ICSR_PENDSVSET_Msk Ú P SCB_ICSR_PENDSVCLR_Pos Ú P SCB_ICSR_PENDSVCLR_Msk Ú P SCB_ICSR_PENDSTSET_Pos Ú P SCB_ICSR_PENDSTSET_Msk Ú P SCB_ICSR_PENDSTCLR_Pos Ú P SCB_ICSR_PENDSTCLR_Msk Ú P SCB_ICSR_ISRPREEMPT_Pos :Ú P SCB_ICSR_ISRPREEMPT_Msk AÚ P SCB_ICSR_ISRPENDING_Pos RÚ P SCB_ICSR_ISRPENDING_Msk YÚ! P SCB_ICSR_VECTPENDING_Pos Ú! P SCB_ICSR_VECTPENDING_Msk Ú P SCB_ICSR_VECTACTIVE_Pos WÚ P SCB_ICSR_VECTACTIVE_Msk ^Ú P SCB_VTOR_TBLOFF_Pos vÚ P SCB_VTOR_TBLOFF_Msk }Ú P SCB_AIRCR_VECTKEY_Pos îÚ P SCB_AIRCR_VECTKEY_Msk õÚ" P SCB_AIRCR_VECTKEYSTAT_Pos ªÚ" P SCB_AIRCR_VECTKEYSTAT_Msk ±Ú P SCB_AIRCR_ENDIANESS_Pos kÚ P SCB_AIRCR_ENDIANESS_Msk rÚ" P SCB_AIRCR_SYSRESETREQ_Pos Ú" P SCB_AIRCR_SYSRESETREQ_Msk Ú$ P SCB_AIRCR_VECTCLRACTIVE_Pos .Ú$ P SCB_AIRCR_VECTCLRACTIVE_Msk 5Ú P SCB_SCR_SEVONPEND_Pos àÚ P SCB_SCR_SEVONPEND_Msk çÚ P SCB_SCR_SLEEPDEEP_Pos ûÚ P SCB_SCR_SLEEPDEEP_Msk Ú P SCB_SCR_SLEEPONEXIT_Pos >Ú P SCB_SCR_SLEEPONEXIT_Msk EÚ P SCB_CCR_STKALIGN_Pos GÚ P SCB_CCR_STKALIGN_Msk NÚ P SCB_CCR_UNALIGN_TRP_Pos ;Ú P SCB_CCR_UNALIGN_TRP_Msk BÚ# P SCB_SHCSR_SVCALLPENDED_Pos xÚ# P SCB_SHCSR_SVCALLPENDED_Msk Ú 8
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<unnamed> QÚ
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" CTRL ìÚ
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" LOAD Ú
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" VAL @Ú
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" CALIB ÄÚ SysTick_Type Ú# P SysTick_CTRL_COUNTFLAG_Pos ¦Ú# P SysTick_CTRL_COUNTFLAG_Msk Ú# P SysTick_CTRL_CLKSOURCE_Pos Ú# P SysTick_CTRL_CLKSOURCE_Msk ¥Ú! P SysTick_CTRL_TICKINT_Pos 7Ú! P SysTick_CTRL_TICKINT_Msk >Ú P SysTick_CTRL_ENABLE_Pos ¨Ú P SysTick_CTRL_ENABLE_Msk ¯Ú P SysTick_LOAD_RELOAD_Pos Ú P SysTick_LOAD_RELOAD_Msk ´Ú P SysTick_VAL_CURRENT_Pos ~Ú P SysTick_VAL_CURRENT_Msk
Ú P SysTick_CALIB_NOREF_Pos ¯Ú P SysTick_CALIB_NOREF_Msk ¶Ú P SysTick_CALIB_SKEW_Pos ñÚ P SysTick_CALIB_SKEW_Msk øÚ P SysTick_CALIB_TENMS_Pos ¢Ú P SysTick_CALIB_TENMS_Msk ©Ú 8
|
<unnamed> QÚ
|
" µTYPE ÇÚ
|
" µCTRL ÔÚ
|
" µRNR Ú
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" µRBAR âÚ
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" µRASR ÑÚ MPU_Type þÚ P MPU_TYPE_IREGION_Pos Ú P MPU_TYPE_IREGION_Msk Ú P MPU_TYPE_DREGION_Pos Ú P MPU_TYPE_DREGION_Msk Ú P MPU_TYPE_SEPARATE_Pos ÉÚ P MPU_TYPE_SEPARATE_Msk ÐÚ P MPU_CTRL_PRIVDEFENA_Pos CÚ P MPU_CTRL_PRIVDEFENA_Msk JÚ P MPU_CTRL_HFNMIENA_Pos åÚ P MPU_CTRL_HFNMIENA_Msk ìÚ P MPU_CTRL_ENABLE_Pos Ú P MPU_CTRL_ENABLE_Msk Ú P MPU_RNR_REGION_Pos °Ú P MPU_RNR_REGION_Msk ·Ú P MPU_RBAR_ADDR_Pos &Ú P MPU_RBAR_ADDR_Msk -Ú P MPU_RBAR_VALID_Pos ÏÚ P MPU_RBAR_VALID_Msk ÖÚ P MPU_RBAR_REGION_Pos yÚ P MPU_RBAR_REGION_Msk Ú P MPU_RASR_ATTRS_Pos Ú P MPU_RASR_ATTRS_Msk §Ú P MPU_RASR_XN_Pos Ú P MPU_RASR_XN_Msk Ú P MPU_RASR_AP_Pos £Ú P MPU_RASR_AP_Msk ªÚ P MPU_RASR_TEX_Pos AÚ P MPU_RASR_TEX_Msk HÚ P MPU_RASR_S_Pos ãÚ P MPU_RASR_S_Msk êÚ P MPU_RASR_C_Pos óÚ P MPU_RASR_C_Msk úÚ P MPU_RASR_B_Pos ôÚ P MPU_RASR_B_Msk ûÚ P MPU_RASR_SRD_Pos IÚ P MPU_RASR_SRD_Msk PÚ P MPU_RASR_SIZE_Pos õÚ P MPU_RASR_SIZE_Msk üÚ P MPU_RASR_ENABLE_Pos
Ú P MPU_RASR_ENABLE_Msk Ú P _VAL2FLD qÚ P _FLD2VAL qÚ P SCS_BASE XÚ P SysTick_BASE oÚ P
|
NVIC_BASE Ú P SCB_BASE iÚ P SCB íÚ P SysTick óÚ P NVIC Ú P MPU_BASE OÚ P MPU ÓÚ P _BIT_SHIFT Ú P _SHP_IDX -Ú P _IP_IDX Ú NVIC_EnableIRQ Ú ,"" òIRQn QÚ NVIC_DisableIRQ §Ú ,"" ôIRQn OÚ NVIC_GetPendingIRQ pÚ ,"" öIRQn MÚ NVIC_SetPendingIRQ dÚ ,"" øIRQn KÚ NVIC_ClearPendingIRQ ¥Ú ,"" úIRQn IÚ NVIC_SetPriority ·Ú ,"" üIRQn GÚ ,
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" ü priority ,Ú NVIC_GetPriority ÃÚ ,"" ÿIRQn DÚ NVIC_SystemReset ½Ú __schedule_barrier sÚ __dsb çÚ __nop ÓÚ SCB_GetFPUType ôÚ SysTick_Config YÚ ,
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" ticks Ú P SYSTEM_FM33A0XXEV_H Ú P
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__stdio_h Ú P __int64 HÚ P _ARMABI ²Ú P __STDIO_DECLS ¦Ú size_t gÚ P NULL Ú P
|
__clang__ 6Ú 8
|
__va_list Ú
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__va_list ?Ú 8 __fpos_t_struct ZÚ (" __pos ÷Ú 8
|
<unnamed> QÚ
|
" __state1 Ú
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" __state2 Ú "
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__mbstate ]Ú fpos_t jÚ P
|
_SYS_OPEN ÊÚ 8 __FILE ÛÚ FILE ÙÚ __stdin ÿÚ __stdout |Ú __stderr Ú __aeabi_stdin ¢Ú __aeabi_stdout Ú __aeabi_stderr .Ú P stdin Ú P stdout Ú P stderr +Ú P _IOFBF úÚ P _IOLBF ôÚ P _IONBF òÚ P BUFSIZ ìÚ P
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FOPEN_MAX üÚ P FILENAME_MAX -Ú P L_tmpnam Ú P TMP_MAX Ú P EOF ëÚ P SEEK_SET HÚ P SEEK_CUR JÚ P SEEK_END ]Ú P _IOBIN ïÚ P __STDIN_BUFSIZ =Ú P __STDOUT_BUFSIZ ÚÚ P __STDERR_BUFSIZ éÚ remove NÚ rename dÚ tmpfile éÚ tmpnam OÚ fclose `Ú fflush TÚ fopen ÆÚ freopen ëÚ setbuf SÚ setvbuf ÛÚ fprintf áÚ _fprintf Ú printf IÚ _printf èÚ sprintf ÔÚ _sprintf sÚ __ARM_snprintf [Ú P __STDC_VERSION__ zÚ snprintf dÚ
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_snprintf Ú fscanf kÚ _fscanf
|
Ú scanf ÓÚ _scanf rÚ sscanf ^Ú _sscanf ýÚ vfscanf óÚ vscanf [Ú vsscanf æÚ _vfscanf Ú _vscanf úÚ _vsscanf
Ú __ARM_vsscanf ÝÚ vprintf ÑÚ _vprintf pÚ vfprintf iÚ vsprintf \Ú __ARM_vsnprintf ãÚ
|
vsnprintf ìÚ
|
_vsprintf ûÚ
|
_vfprintf Ú _vsnprintf Ú asprintf qÚ
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vasprintf ùÚ __ARM_asprintf hÚ __ARM_vasprintf ðÚ fgetc ÕÚ fgets ÅÚ fputc ¼Ú fputs ¬Ú getc =Ú P getchar ßÚ getchar üÚ gets -Ú putc $Ú P putchar ÆÚ putchar ãÚ puts Ú ungetc VÚ fread ÜÚ __fread_bytes_avail Ú fwrite KÚ fgetpos âÚ fseek ÐÚ fsetpos ÖÚ ftell ÇÚ rewind SÚ clearerr Ú feof @Ú ferror LÚ perror BÚ _fisatty uÚ! __use_no_semihosting_swi ¶Ú __use_no_semihosting pÚ
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SystemCoreClock ãÚ SystemInit »Ú SystemCoreClockUpdate aÚ P __SYSTEM_CLOCK AÚ P DELAY_US EÚ P DELAY_MS MÚ P Do_DelayStart ¢Ú P While_DelayMsEnd Ú P While_DelayUsEnd
Ú 8
|
<unnamed> QÚ
|
" CR £Ú
|
" WKTR ìÚ
|
" WKFR úÚ
|
" IER VÚ
|
" ISR HÚ PMU_Type þÚ 8
|
<unnamed> QÚ
|
" RSV1 Ú
|
" CR Ú
|
" HDFR Ú DBG_Type #Ú 8
|
<unnamed> QÚ
|
" RDCR ýÚ
|
" PFCR ýÚ
|
" OPTBR Ú <" RSV1 ÆÚ
|
" EPCR þÚ
|
" KEY AÚ
|
" IER JÚ
|
" ISR <Ú <" $RSV2 ©Ú
|
" ACLOCK1 DÚ
|
" ACLOCK2 CÚ
|
" ACLOCK3 BÚ
|
" ACLOCK4 AÚ FLS_Type Ú 8
|
<unnamed> QÚ
|
" £PDRCR Ú
|
" £BORCR Ú
|
" £RSTCFGR øÚ
|
" £SOFTRST ÞÚ
|
" £RSR $Ú
|
" £PRSTEN 9Ú
|
" £AHBRST QÚ
|
" £APBRST1 Ú
|
" £APBRST2 Ú RMU_Type üÚ 8
|
<unnamed> QÚ
|
" ®SERV ÎÚ
|
" ®CFGR ìÚ
|
" ®CNTR ×Ú
|
IWDT_Type ¶Ú 8
|
<unnamed> QÚ
|
" ³CR xÚ
|
" ³CFGR çÚ
|
" ³CNTR ÒÚ
|
" ³IER +Ú
|
" ³ISR Ú
|
" ³PSCR ÑÚ
|
WWDT_Type ¨Ú 8
|
<unnamed> QÚ
|
" » SYSCLKCR Ú
|
" »RCHFCR EÚ
|
" »RCHFTR 4Ú
|
" »PLLLCR 4Ú
|
" »PLLHCR 8Ú
|
" »XTHFCR .Ú
|
" »IER #Ú
|
" »ISR Ú
|
" »PCLKCR1 Ú
|
" »PCLKCR2
|
Ú
|
" »PCLKCR3 Ú
|
" »PCLKCR4 Ú
|
" »OPCCR1 UÚ
|
" »OPCCR2 TÚ CMU_Type Ú 8
|
<unnamed> QÚ
|
" ËCR `Ú
|
" ËPSCR ¹Ú
|
CDIF_Type ØÚ 8
|
<unnamed> QÚ
|
" ÏPDRCR pÚ <" ÏRSV1 Ú
|
" ÏRCMFCR ,Ú
|
" ÏRCLPCR #Ú
|
" ÏRCLPTR Ú
|
" ÏXTLFCR Ú
|
" ÏADCCR Ú
|
" ÏLFDIER 3Ú
|
" ÏLFDISR %Ú
|
VRTC_Type ¯Ú 8
|
<unnamed> QÚ
|
" ÚCFGR ÀÚ
|
" ÚCR QÚ
|
" ÚIER Ú
|
" ÚISR öÚ
|
" ÚVSR éÚ SVD_Type Ú 8
|
<unnamed> QÚ
|
" áCR JÚ
|
" áIER ýÚ
|
" áISR ïÚ
|
" áDIR þÚ
|
" áDOR øÚ
|
" áKEY0 ÂÚ
|
" áKEY1 ÁÚ
|
" áKEY2 ÀÚ
|
" áKEY3 ¿Ú
|
" áKEY4 ¾Ú
|
" áKEY5 ½Ú
|
" áKEY6 ¼Ú
|
" áKEY7 »Ú
|
" áIVR0 ºÚ
|
" áIVR1 ¹Ú
|
" áIVR2 ¸Ú
|
" áIVR3 ·Ú
|
" áH0 gÚ
|
" áH1 fÚ
|
" áH2 eÚ
|
" áH3 dÚ AES_Type Ú 8
|
<unnamed> QÚ
|
" øCSR ÞÚ
|
" øMLR ÛÚ
|
" øMPR ×Ú
|
" øM0CFG uÚ
|
" øM1CFG tÚ
|
" øM2CFG sÚ
|
" øM3CFG rÚ
|
" øWORD Ú PAE_Type Ú 8
|
<unnamed> QÚ
|
" CSR SÚ
|
" DTR QÚ
|
HASH_Type ÊÚ 8
|
<unnamed> QÚ
|
" CR ¤Ú
|
" DOR RÚ <" RSV1 ÓÚ
|
" SR Ú
|
" CRC_CR eÚ
|
" CRC_DIR Ú
|
" CRC_SR UÚ RNG_Type Ú 8
|
<unnamed> QÚ
|
" CR1 hÚ
|
" CR2 gÚ
|
" ICR PÚ
|
" ISR @Ú
|
" PCR IÚ
|
COMP_Type ¿Ú 8
|
<unnamed> QÚ
|
" CFGR Ú
|
" CR Ú
|
" IER GÚ
|
" ISR 9Ú
|
" SR Ú
|
" BRG LÚ
|
" BUF JÚ
|
" TIMING YÚ
|
" TO Ú I2C_Type 2Ú 8
|
<unnamed> QÚ
|
" ¡CR Ú UARTIR_Type Ú 8
|
<unnamed> QÚ
|
" ¤CSR 1Ú
|
" ¤IER 9Ú
|
" ¤ISR +Ú
|
" ¤TODR ÞÚ
|
" ¤RXBUF Ú
|
" ¤TXBUF Ú
|
" ¤BGR >Ú
|
UART_Type ²Ú 8
|
<unnamed> QÚ
|
" CSR (Ú
|
" IER 0Ú
|
" ISR "Ú
|
" BMR /Ú
|
" RXBUF
Ú
|
" TXBUF Ú
|
" DMR -Ú LPUART_Type Ú 8
|
<unnamed> QÚ
|
" ¶CR1 AÚ
|
" ¶CR2 @Ú
|
" ¶CR3 ?Ú
|
" ¶IER 'Ú
|
" ¶ISR Ú
|
" ¶TXBUF zÚ
|
" ¶RXBUF |Ú SPI_Type Ú 8
|
<unnamed> QÚ
|
" ¿CR kÚ
|
" ¿FFR Ú
|
" ¿EGTR ÊÚ
|
" ¿PSC Ú
|
" ¿BGR #Ú
|
" ¿RXBUF sÚ
|
" ¿TXBUF qÚ
|
" ¿IER Ú
|
" ¿ISR Ú U7816_Type ÁÚ 8
|
<unnamed> QÚ
|
" ÊCR `Ú
|
" ÊCFG #Ú
|
" ÊSR PÚ
|
" ÊDATALEN òÚ
|
" ÊCCR Ú
|
" ÊADDR ÖÚ
|
" ÊABR Ú
|
" ÊDR _Ú
|
" ÊSMSK ³Ú
|
" ÊSMAT ¼Ú
|
" ÊPITV ®Ú
|
" ÊTO RÚ
|
QSPI_Type ±Ú 8
|
<unnamed> QÚ
|
" ØGCR Ú
|
" ØCH0CR Ú
|
" ØCH0MAR DÚ
|
" ØCH1CR Ú
|
" ØCH1MAR CÚ
|
" ØCH2CR Ú
|
" ØCH2MAR BÚ
|
" ØCH3CR Ú
|
" ØCH3MAR AÚ
|
" ØCH4CR Ú
|
" ØCH4MAR @Ú
|
" ØCH5CR Ú
|
" ØCH5MAR ?Ú
|
" ØCH6CR Ú
|
" ØCH6MAR >Ú
|
" ØCH7CR Ú
|
" ØCH7MAR =Ú
|
" ØCH8CR Ú
|
" ØCH8MAR <Ú
|
" ØCH9CR Ú
|
" ØCH9MAR ;Ú
|
" ØCH10CR ^Ú
|
" ØCH10MAR Ú
|
" ØCH11CR ]Ú
|
" ØCH11FAR Ú
|
" ØCH11RAR Ú
|
" ØISR ÷Ú <" ØRSV1 óÚ
|
" ØCH0CSR <Ú
|
" ØCH0MASR ïÚ
|
" ØCH1CSR ;Ú
|
" ØCH1MASR îÚ
|
" ØCH2CSR :Ú
|
" ØCH2MASR íÚ
|
" ØCH3CSR 9Ú
|
" ØCH3MASR ìÚ
|
" ØCH4CSR 8Ú
|
" ØCH4MASR ëÚ
|
" ØCH5CSR 7Ú
|
" ØCH5MASR êÚ
|
" ØCH6CSR 6Ú
|
" ØCH6MASR éÚ DMA_Type Ú 8
|
<unnamed> QÚ
|
" DR ¤Ú
|
" CR ¥Ú
|
" LFSR ÿÚ
|
" XOR ?Ú <" RSV1 ÐÚ
|
" POLY òÚ CRC_Type Ú 8
|
<unnamed> QÚ
|
" CR1 jÚ
|
" CR2 iÚ
|
" CFGR1 ÙÚ
|
" CFGR2 ØÚ
|
" PRES ôÚ
|
" LOADCR uÚ
|
" CNTL ýÚ
|
" CNTH Ú
|
" PRESET WÚ
|
" LOADL ÀÚ
|
" LOADH ÄÚ
|
" CMPL Ú
|
" CMPH Ú
|
" OUTCNT MÚ
|
" OCR LÚ
|
" IER PÚ
|
" ISR BÚ BT_Type \Ú 8
|
<unnamed> QÚ
|
" CR Ú
|
" INSR ßÚ
|
" PSCR1 °Ú
|
" PSCR2 ¯Ú
|
" IVR ,Ú
|
" CMPR éÚ
|
" IER =Ú
|
" ISR /Ú ET_Type YÚ 8
|
<unnamed> QÚ
|
" ©CNT1 ûÚ
|
" ©CNT2 úÚ
|
" ©CNT3 ùÚ
|
" ©CNT4 øÚ ETCNT_Type nÚ 8
|
<unnamed> QÚ
|
" ¯CR1 GÚ
|
" ¯CR2 FÚ
|
" ¯RSV1 ßÚ
|
" ¯IER -Ú
|
" ¯ISR Ú
|
" ¯EGR /Ú <" ¯RSV2 ¤Ú
|
" ¯CNTR ÔÚ
|
" ¯PSCR ÓÚ
|
" ¯ARR (Ú BSTIM_Type mÚ 8
|
<unnamed> QÚ
|
" »CFGR ÝÚ
|
" »CNTR ÈÚ
|
" »CCSR ÔÚ
|
" »ARR Ú
|
" »IER !Ú
|
" »ISR Ú
|
" »CR nÚ
|
" »RSV1 ÓÚ
|
" »CCR1 öÚ
|
" »CCR2 õÚ
|
" »CCR3 ôÚ
|
" »CCR4 óÚ LPTIM_Type fÚ 8
|
<unnamed> QÚ
|
" ÉWER Ú
|
" ÉIER Ú
|
" ÉISR Ú
|
" ÉBCDSEC IÚ
|
" ÉBCDMIN @Ú
|
" ÉBCDHOUR äÚ
|
" ÉBCDDATE Ú
|
" ÉBCDWEEK öÚ
|
" É BCDMONTH Ú
|
" ÉBCDYEAR ñÚ
|
" ÉALARM Ú
|
" ÉTMSEL jÚ
|
" ÉADJUST "Ú
|
" ÉADSIGN 7Ú
|
" ÉVCAL ËÚ
|
" ÉMSCNT jÚ
|
" ÉCALSTEP ßÚ
|
" ÉADCNT
Ú
|
" ÉSSR ûÚ
|
" ÉSSA Ú
|
" ÉDTR Ú <" (ÉRSV1 oÚ
|
" ÉCR `Ú RTC_Type Ú 8
|
<unnamed> QÚ
|
" âCR GÚ
|
" âTEST Ú
|
" âFCR ÿÚ
|
" âFLKT §Ú
|
" âRSV1 ¬Ú
|
" âIER úÚ
|
" âISR ìÚ <" âRSV2 uÚ
|
" âDATA0 Ú
|
" âDATA1 Ú
|
" âDATA2 Ú
|
" âDATA3 Ú
|
" âDATA4 Ú
|
" âDATA5 Ú
|
" âDATA6 Ú
|
" âDATA7
Ú
|
" âDATA8 Ú
|
" âDATA9 Ú <" âRSV3 xÚ
|
" âCOMEN dÚ
|
" âSEGEN0 2Ú
|
" âSEGEN1 1Ú
|
" âBSTCR XÚ LCD_Type Ú 8
|
<unnamed> QÚ
|
" ûCR .Ú
|
" ûTRIM Ú
|
" ûDR -Ú
|
" ûISR ÓÚ
|
" ûCFGR Ú ADC_Type (Ú 8
|
<unnamed> QÚ
|
" DR ¥Ú
|
" OS Ú
|
" USDR ùÚ
|
" CR ¦Ú
|
" ISR KÚ CIC_Type !Ú 8
|
<unnamed> QÚ
|
" INEN Ú
|
" PUEN øÚ
|
" ODEN
|
Ú
|
" FCR WÚ
|
" DO ¡Ú
|
" DSET Ú
|
" DRST óÚ
|
" DIN WÚ
|
" DFS UÚ
|
" RSV 7Ú
|
" ANEN Ú
|
GPIO_Type ¿Ú 8
|
<unnamed> QÚ
|
" INEN ùÚ
|
" PUEN ëÚ
|
" FCR JÚ
|
" DO Ú
|
" DIN JÚ GPIOH_Type uÚ 8
|
<unnamed> QÚ
|
" EXTISEL0 ÆÚ
|
" EXTISEL1 ÅÚ
|
" EXTIEDS0 ÎÚ
|
" EXTIEDS1 ÍÚ
|
" EXTIDF TÚ
|
" EXTIISR îÚ
|
" EXTIDI QÚ <" $RSV1 Ú
|
" FOUTSEL ôÚ
|
" IOMCR Ú <" øRSV2 ÇÚ
|
" PINWKEN úÚ GPIO_COMMON_Type Ú P FLASH_BASE ÏÚ P
|
SRAM_BASE Ú P PERIPH_BASE sÚ P PMU_BASE OÚ P DBG_BASE tÚ P FLS_BASE \Ú P RMU_BASE MÚ P
|
IWDT_BASE Ú P
|
WWDT_BASE ùÚ P CMU_BASE \Ú P
|
CDIF_BASE )Ú P
|
VRTC_BASE Ú P SVD_BASE TÚ P AES_BASE hÚ P PAE_BASE kÚ P
|
HASH_BASE Ú P RNG_BASE ZÚ P
|
COMP_BASE Ú P
|
I2C0_BASE QÚ P
|
I2C1_BASE PÚ P UARTIR_BASE dÚ P UART0_BASE ÑÚ P UART1_BASE ÐÚ P UART2_BASE ÏÚ P UART3_BASE ÎÚ P UART4_BASE ÍÚ P UART5_BASE ÌÚ P LPUART0_BASE 1Ú P LPUART1_BASE 0Ú P
|
SPI0_BASE #Ú P
|
SPI1_BASE "Ú P
|
SPI2_BASE !Ú P
|
SPI3_BASE Ú P
|
SPI4_BASE Ú P U7816_BASE Ú P
|
QSPI_BASE Ú P DMA_BASE oÚ P CRC_BASE iÚ P BT1_BASE zÚ P BT2_BASE yÚ P ET1_BASE wÚ P ET2_BASE vÚ P ET3_BASE uÚ P ET4_BASE tÚ P ETCNT_BASE ¿Ú P BSTIM_BASE ¾Ú P LPTIM_BASE ·Ú P RTC_BASE XÚ P LCD_BASE nÚ P ADC_BASE yÚ P CIC_BASE rÚ P GPIOA_BASE ÍÚ P GPIOB_BASE ÌÚ P GPIOC_BASE ËÚ P GPIOD_BASE ÊÚ P GPIOE_BASE ÉÚ P GPIOF_BASE ÈÚ P GPIOG_BASE ÇÚ P GPIOH_BASE ÆÚ P
|
GPIO_BASE Ú P PMU ÓÚ P DBG øÚ P FLS àÚ P RMU ÑÚ P IWDT Ú P WWDT }Ú P CMU àÚ P CDIF Ú P VRTC Ú P SVD ØÚ P AES ìÚ P PAE ïÚ P HASH Ú P RNG ÞÚ P COMP Ú P I2C0 ÕÚ P I2C1 ÔÚ P UARTIR èÚ P UART0 UÚ P UART1 TÚ P UART2 SÚ P UART3 RÚ P UART4 QÚ P UART5 PÚ P LPUART0 µÚ P LPUART1 ´Ú P SPI0 §Ú P SPI1 ¦Ú P SPI2 ¥Ú P SPI3 ¤Ú P SPI4 £Ú P U7816 Ú P QSPI Ú P DMA óÚ P CRC íÚ P BT1 þÚ P BT2 ýÚ P ET1 ûÚ P ET2 úÚ P ET3 ùÚ P ET4 øÚ P ETCNT CÚ P BSTIM BÚ P LPTIM ;Ú P RTC ÜÚ P LCD òÚ P ADC ýÚ P CIC öÚ P GPIOA QÚ P GPIOB PÚ P GPIOC OÚ P GPIOD NÚ P GPIOE MÚ P GPIOF LÚ P GPIOG KÚ P GPIOH JÚ P GPIO Ú P __INCLUDEALL_H__ «Ú P __FM33A0XXEV_AES_H UÚ 8
|
<unnamed> QÚ
|
" ¢ KEYLEN JÚ
|
" ¢ CHMOD ©Ú
|
" ¢ MODE ñÚ
|
" ¢ DATATYP ùÚ "" ¢ DMAOEN IÚ "" ¢ DMAIEN OÚ "" ¢ WERRIE /Ú "" ¢ RERRIE 4Ú "" ¢ CCFIE ¥Ú "" ¢ AESEN Ú AES_InitTypeDef fÚ P AES_CR_KEYLEN_Pos $Ú P AES_CR_KEYLEN_Msk +Ú P AES_CR_KEYLEN_128BIT ÖÚ P AES_CR_KEYLEN_192BIT ÕÚ P AES_CR_KEYLEN_256BIT ÔÚ P AES_CR_KEYLEN_ \Ú P AES_CR_DMAOEN_Pos 8Ú P AES_CR_DMAOEN_Msk ?Ú P AES_CR_DMAIEN_Pos >Ú P AES_CR_DMAIEN_Msk EÚ P AES_CR_CHMOD_Pos Ú P AES_CR_CHMOD_Msk Ú P AES_CR_CHMOD_ECB ëÚ P AES_CR_CHMOD_CBC íÚ P AES_CR_CHMOD_CTR ÌÚ P AES_CR_CHMOD_MULTH 'Ú P AES_CR_MODE_Pos ËÚ P AES_CR_MODE_Msk ÒÚ P AES_CR_MODE_ENCRYPT ÐÚ P AES_CR_MODE_KEYEXP !Ú P AES_CR_MODE_DECRYPT ÚÚ" P AES_CR_MODE_KEYEXPDECRYPT øÚ P AES_CR_DATATYP_Pos ÓÚ P AES_CR_DATATYP_Msk ÚÚ! P AES_CR_DATATYP_32BITNOEX {Ú P AES_CR_DATATYP_16BITEX Ú P AES_CR_DATATYP_8BITEX KÚ P AES_CR_DATATYP_1BITEX RÚ P AES_CR_EN_Pos aÚ P AES_CR_EN_Msk hÚ P AES_IER_WRERR_IE_Pos Ú P AES_IER_WRERR_IE_Msk #Ú P AES_IER_RDERR_IE_Pos /Ú P AES_IER_RDERR_IE_Msk 6Ú P AES_IER_CCF_IE_Pos æÚ P AES_IER_CCF_IE_Msk íÚ P AES_DIR_DIN_Pos ËÚ P AES_DIR_DIN_Msk ÒÚ P AES_DOR_DOUT_Pos bÚ P AES_DOR_DOUT_Msk iÚ P AES_KEY0_KEYx_Pos Ú P AES_KEY0_KEYx_Msk Ú P AES_KEY1_KEYx_Pos Ú P AES_KEY1_KEYx_Msk Ú P AES_KEY2_KEYx_Pos Ú P AES_KEY2_KEYx_Msk Ú P AES_KEY3_KEYx_Pos Ú P AES_KEY3_KEYx_Msk Ú P AES_KEY4_KEYx_Pos Ú P AES_KEY4_KEYx_Msk
|
Ú P AES_KEY5_KEYx_Pos Ú P AES_KEY5_KEYx_Msk Ú P AES_KEY6_KEYx_Pos Ú P AES_KEY6_KEYx_Msk Ú P AES_KEY7_KEYx_Pos Ú P AES_KEY7_KEYx_Msk Ú P AES_IVR0_IVRx_Pos ÷Ú P AES_IVR0_IVRx_Msk þÚ P AES_IVR1_IVRx_Pos öÚ P AES_IVR1_IVRx_Msk ýÚ P AES_IVR2_IVRx_Pos õÚ P AES_IVR2_IVRx_Msk üÚ P AES_IVR3_IVRx_Pos ôÚ P AES_IVR3_IVRx_Msk ûÚ P AES_H0_Hx_Pos QÚ P AES_H0_Hx_Msk XÚ P AES_H1_Hx_Pos PÚ P AES_H1_Hx_Msk WÚ P AES_H2_Hx_Pos OÚ P AES_H2_Hx_Msk VÚ P AES_H3_Hx_Pos NÚ P AES_H3_Hx_Msk UÚ P AES_ISR_WRERR_Pos Ú P AES_ISR_WRERR_Msk Ú P AES_ISR_RDERR_Pos Ú P AES_ISR_RDERR_Msk Ú P AES_ISR_CCF_Pos ËÚ P AES_ISR_CCF_Msk ÒÚ AES_Deinit ?Ú ,
|
SetValue ¦Ú AES_CR_KEYLEN_Set GÚ AES_CR_KEYLEN_Get SÚ ," NewState Ú AES_CR_DMAOEN_Setable ¿Ú AES_CR_DMAOEN_Getable ËÚ ," NewState Ú AES_CR_DMAIEN_Setable ÅÚ& FunStateAES_CR_DMAIEN_Getable Ú ,
|
SetValue ¦Ú AES_CR_CHMOD_Set ¦Ú AES_CR_CHMOD_Get ²Ú ,
|
SetValue ¦Ú AES_CR_MODE_Set îÚ AES_CR_MODE_Get úÚ ,
|
SetValue ¦Ú AES_CR_DATATYP_Set öÚ AES_CR_DATATYP_Get Ú ," NewState Ú AES_CR_EN_Setable èÚ AES_CR_EN_Getable ôÚ ," NewState Ú! AES_IER_WRERR_IE_Setable £Ú! AES_IER_WRERR_IE_Getable ¯Ú ," NewState Ú! AES_IER_RDERR_IE_Setable ¶Ú! AES_IER_RDERR_IE_Getable ÂÚ ," NewState Ú AES_IER_CCF_IE_Setable mÚ AES_IER_CCF_IE_Getable yÚ ,
|
SetValue ¦Ú AES_DIR_Write MÚ AES_DIR_Read ÞÚ AES_DOR_Read ØÚ ,
|
SetValue ¦Ú AES_KEY0_Write Ú ,
|
SetValue ¦Ú AES_KEY1_Write Ú ,
|
SetValue ¦Ú AES_KEY2_Write Ú ,
|
SetValue ¦Ú AES_KEY3_Write Ú ,
|
SetValue ¦Ú AES_KEY4_Write Ú ,
|
SetValue ¦Ú AES_KEY5_Write Ú ,
|
SetValue ¦Ú AES_KEY6_Write Ú ,
|
SetValue ¦Ú AES_KEY7_Write
|
Ú ,
|
SetValue ¦Ú AES_IVR0_Write Ú AES_IVR0_Read Ú ,
|
SetValue ¦Ú AES_IVR1_Write Ú AES_IVR1_Read Ú ,
|
SetValue ¦Ú AES_IVR2_Write Ú AES_IVR2_Read Ú ,
|
SetValue ¦Ú AES_IVR3_Write Ú AES_IVR3_Read Ú ,
|
SetValue ¦Ú AES_H0_Write ¶Ú AES_H0_Read GÚ ,
|
SetValue ¦Ú AES_H1_Write µÚ AES_H1_Read FÚ ,
|
SetValue ¦Ú AES_H2_Write ´Ú AES_H2_Read EÚ ,
|
SetValue ¦Ú AES_H3_Write ³Ú AES_H3_Read DÚ AES_ISR_WRERR_Clr /Ú AES_ISR_WRERR_Chk :Ú AES_ISR_RDERR_Clr BÚ AES_ISR_RDERR_Chk MÚ AES_ISR_CCF_Clr ùÚ AES_ISR_CCF_Chk Ú , KeyIn çÚ , Len ÁÚ AES_KEY_WriteEx Ú , IVRIn Ú AES_IVR_WriteEx zÚ , IVROut Ú AES_IVR_ReadEx Ú , DataIn Ú" AES_DIN_GroupWrite_128BIT SÚ , DataOut Ú" AES_DOUT_GroupRead_128BIT Ú , DataIn Ú , DataOut Ú% AES_GroupWriteAndRead_128BIT øÚ , DataIn Ú , DataOut Ú) !AES_GroupWriteAndRead_128BIT_IVR Ú , para %Ú AES_Init Ú , HxIn RÚ , Len ÁÚ AES_Hx_WriteEx Ú , HxOut ÏÚ , Len ÁÚ AES_Hx_ReadEx >Ú P __FM33A0XXEV_ADC_H fÚ P ADC_CR_ADC_IE_Pos HÚ P ADC_CR_ADC_IE_Msk OÚ P ADC_CR_ACC_IE_Pos IÚ P ADC_CR_ACC_IE_Msk PÚ P ADC_CR_HPEN_Pos ÖÚ P ADC_CR_HPEN_Msk ÝÚ P ADC_CR_HPEN_1MHZ æÚ P ADC_CR_HPEN_2MHZ åÚ P ADC_CR_MODE_Pos ÜÚ P ADC_CR_MODE_Msk ãÚ P ADC_CR_MODE_INNER Ú P ADC_CR_MODE_EXTERNAL ¡Ú P ADC_CR_RSTCTRL_EN_Pos ÕÚ P ADC_CR_RSTCTRL_EN_Msk ÜÚ P ADC_CR_EN_Pos rÚ P ADC_CR_EN_Msk yÚ P ADC_TRIM_ADC_TRIM_Pos ëÚ P ADC_TRIM_ADC_TRIM_Msk òÚ P ADC_DR_ADC_DATA_Pos ·Ú P ADC_DR_ADC_DATA_Msk ¾Ú P ADC_ISR_INIT_RDY_Pos Ú P ADC_ISR_INIT_RDY_Msk #Ú P ADC_ISR_ACC_IF_Pos íÚ P ADC_ISR_ACC_IF_Msk ôÚ P ADC_ISR_ADC_DONE_Pos QÚ P ADC_ISR_ADC_DONE_Msk XÚ P ADC_ISR_ADC_IF_Pos ìÚ P ADC_ISR_ADC_IF_Msk óÚ P ADC_CFGR_ACC_PERIOD_Pos {Ú P ADC_CFGR_ACC_PERIOD_Msk Ú# P ADC_CFGR_ACC_PERIOD_10BITS Ú# P ADC_CFGR_ACC_PERIOD_11BITS Ú# P ADC_CFGR_ACC_PERIOD_12BITS Ú# P ADC_CFGR_ACC_PERIOD_13BITS Ú# P ADC_CFGR_ACC_PERIOD_14BITS Ú$ P ADC_CFGR_RST_CTRL_DELAY_Pos Ú$ P ADC_CFGR_RST_CTRL_DELAY_Msk Ú P ADC_CFGR_BUFEN_Pos þÚ P ADC_CFGR_BUFEN_Msk Ú P ADC_CFGR_BUFSEL_Pos «Ú P ADC_CFGR_BUFSEL_Msk ²Ú P ADC_CFGR_BUFSEL_ADC_IN1 æÚ P ADC_CFGR_BUFSEL_ADC_IN2 åÚ P ADC_CFGR_BUFSEL_ADC_IN3 äÚ P ADC_CFGR_BUFSEL_ADC_IN4 ãÚ P ADC_CFGR_BUFSEL_ADC_IN5 âÚ P ADC_CFGR_BUFSEL_ADC_IN6 áÚ P ADC_CFGR_BUFSEL_ADC_IN7 àÚ P ADC_CFGR_BUFSEL_ADC_IN8 ßÚ P ADC_CFGR_BUFSEL_ADC_IN9 ÞÚ! P ADC_CFGR_BUFSEL_ADC_IN10 ´Ú! P ADC_CFGR_BUFSEL_ADC_IN11 ³Ú! P ADC_CFGR_BUFSEL_ADC_IN12 ²Ú P ADC_CFGR_BUFSEL_VBAT ®Ú P ADC_CFGR_BUFSEL_TS 8Ú P CIC_DR_ADC_CIC_DATA_Pos zÚ P CIC_DR_ADC_CIC_DATA_Msk Ú P CIC_OS_ADC_CIC_OS_Pos êÚ P CIC_OS_ADC_CIC_OS_Msk ñÚ" P CIC_USDR_ADC_CIC_USDR_Pos ªÚ" P CIC_USDR_ADC_CIC_USDR_Msk ±Ú P CIC_CR_CIC_EN_Pos 5Ú P CIC_CR_CIC_EN_Msk <Ú P CIC_CR_NS_DISC_Pos ÑÚ P CIC_CR_NS_DISC_Msk ØÚ P CIC_CR_OVR_IE_Pos Ú P CIC_CR_OVR_IE_Msk Ú P CIC_CR_CIC_IE_Pos :Ú P CIC_CR_CIC_IE_Msk AÚ P CIC_CR_TRUNC_Pos lÚ P CIC_CR_TRUNC_Msk sÚ P CIC_CR_OSR_Pos Ú P CIC_CR_OSR_Msk Ú P CIC_CR_OSR_X8 ¬Ú P CIC_CR_OSR_X16 {Ú P CIC_CR_OSR_X32 }Ú P CIC_CR_OSR_X64 xÚ P CIC_CR_OSR_X128 EÚ P CIC_CR_OSR_X256 CÚ P CIC_CR_OSR_X512 HÚ P CIC_CR_OSR_X1024 Ú P CIC_ISR_CIC_OVR_Pos tÚ P CIC_ISR_CIC_OVR_Msk {Ú P CIC_ISR_CIC_IF_Pos ÞÚ P CIC_ISR_CIC_IF_Msk åÚ ADC_Deinit PÚ ," NewState Ú ADC_CR_ADC_IE_Setable ÏÚ ADC_CR_ADC_IE_Getable ÛÚ ," NewState Ú ADC_CR_ACC_IE_Setable ÐÚ ADC_CR_ACC_IE_Getable ÜÚ ,
|
SetValue ¦Ú ADC_CR_HPEN_Set ùÚ ADC_CR_HPEN_Get Ú ,
|
SetValue ¦Ú ADC_CR_MODE_Set ÿÚ ADC_CR_MODE_Get Ú ," NewState Ú" ADC_CR_RSTCTRL_EN_Setable \Ú" ADC_CR_RSTCTRL_EN_Getable hÚ ," NewState Ú ADC_CR_EN_Setable ùÚ ADC_CR_EN_Getable Ú ,
|
SetValue ¦Ú ADC_TRIM_Write ÿÚ ADC_TRIM_Read Ú ADC_DR_Read :Ú ADC_ISR_INIT_RDY_Chk UÚ ADC_ISR_ACC_IF_Clr Ú ADC_ISR_ACC_IF_Chk &Ú ADC_ISR_ADC_DONE_Chk Ú ADC_ISR_ADC_IF_Clr Ú ADC_ISR_ADC_IF_Chk %Ú ,
|
SetValue ¦Ú ADC_CFGR_ACC_PERIOD_Set Ú ADC_CFGR_ACC_PERIOD_Get ªÚ ,
|
SetValue ¦Ú$ ADC_CFGR_RST_CTRL_DELAY_Set $Ú$ ADC_CFGR_RST_CTRL_DELAY_Get 0Ú ," NewState Ú ADC_CFGR_BUFEN_Setable
Ú ADC_CFGR_BUFEN_Getable Ú ,
|
SetValue ¦Ú ADC_CFGR_BUFSEL_Set ÎÚ ADC_CFGR_BUFSEL_Get ÚÚ CIC_DR_Read 3Ú ,
|
SetValue ¦Ú ACIC_OS_Write SÚ CIC_OS_Read 'Ú CIC_USDR_Read Ú ," NewState Ú CIC_CR_CIC_EN_Setable ¼Ú CIC_CR_CIC_EN_Getable ÈÚ ,
|
SetValue ¦Ú ACIC_CR_NS_DISC_Set ±Ú CIC_CR_NS_DISC_Get Ú ," NewState Ú CIC_CR_OVR_IE_Setable Ú CIC_CR_OVR_IE_Getable ¥Ú ," NewState Ú CIC_CR_CIC_IE_Setable ÁÚ IC_CR_CIC_IE_Getable Ú ,
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SetValue ¦Ú CIC_CR_TRUNC_Set Ú CIC_CR_TRUNC_Get Ú ,
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SetValue ¦Ú CIC_CR_OSR_Set +Ú CIC_CR_OSR_Get 7Ú CIC_ISR_CIC_OVR_Clr ¢Ú CIC_ISR_CIC_OVR_Chk Ú CIC_ISR_CIC_IF_Clr Ú CIC_ISR_CIC_IF_Chk Ú P __FM33A0XXEV_BSTIM_H «Ú P BSTIM_CR1_ARPE_Pos ëÚ P BSTIM_CR1_ARPE_Msk òÚ P BSTIM_CR1_OPM_Pos )Ú P BSTIM_CR1_OPM_Msk 0Ú P BSTIM_CR1_OPM_CONTINUE ìÚ P BSTIM_CR1_OPM_STOP Ú P BSTIM_CR1_URS_Pos Ú P BSTIM_CR1_URS_Msk "Ú P BSTIM_CR1_URS_ALL tÚ P BSTIM_CR1_URS_COUNT ÀÚ P BSTIM_CR1_UDIS_Pos ÞÚ P BSTIM_CR1_UDIS_Msk åÚ P BSTIM_CR1_CEN_Pos ?Ú P BSTIM_CR1_CEN_Msk FÚ P BSTIM_CR2_MMS_Pos 'Ú P BSTIM_CR2_MMS_Msk .Ú P BSTIM_IER_UIE_Pos Ú P BSTIM_IER_UIE_Msk Ú P BSTIM_ISR_UIF_Pos Ú P BSTIM_ISR_UIF_Msk Ú P BSTIM_EGR_UG_Pos cÚ P BSTIM_EGR_UG_Msk jÚ P BSTIM_CNTR_CNT_Pos ½Ú P BSTIM_CNTR_CNT_Msk ÄÚ P BSTIM_PSCR_PSC_Pos »Ú P BSTIM_PSCR_PSC_Msk ÂÚ P BSTIM_ARR_ARR_Pos Ú P BSTIM_ARR_ARR_Msk Ú BSTIM_Deinit Ú ," NewState Ú BSTIM_CR1_ARPE_Setable rÚ BSTIM_CR1_ARPE_Getable ~Ú ,
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SetValue ¦Ú BSTIM_CR1_OPM_Set LÚ BSTIM_CR1_OPM_Get XÚ ,
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SetValue ¦Ú BSTIM_CR1_URS_Set >Ú BSTIM_CR1_URS_Get JÚ ," NewState Ú BSTIM_CR1_UDIS_Setable eÚ BSTIM_CR1_UDIS_Getable qÚ ," NewState Ú BSTIM_CR1_CEN_Setable ÆÚ BSTIM_CR1_CEN_Getable ÒÚ ,
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SetValue ¦Ú BSTIM_CR2_Write »Ú BSTIM_CR2_Read LÚ ," NewState Ú BSTIM_IER_UIE_Setable Ú BSTIM_IER_UIE_Getable «Ú BSTIM_ISR_UIF_Clr 7Ú BSTIM_ISR_UIF_Chk BÚ ," NewState Ú BSTIM_EGR_UG_Setable êÚ ,
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SetValue ¦Ú BSTIM_CNTR_Write IÚ BSTIM_CNTR_Read ÚÚ ,
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SetValue ¦Ú BSTIM_PSCR_Write HÚ BSTIM_PSCR_Read ÙÚ ,
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SetValue ¦Ú BSTIM_ARR_Write Ú BSTIM_ARR_Read .Ú P __FM33A0XXEV_COMP_H ýÚ P COMP_CR1_DFLEN_Pos úÚ P COMP_CR1_DFLEN_Msk Ú P COMP_CR1_DFLEN_X3 £Ú P COMP_CR1_DFLEN_X32 oÚ P COMP_CR1_WINMODE_Pos LÚ P COMP_CR1_WINMODE_Msk SÚ P COMP_CR1_POLAR_Pos åÚ P COMP_CR1_POLAR_Msk ìÚ P COMP_CR1_POLAR_POS %Ú P COMP_CR1_POLAR_NEG =Ú P COMP_CR1_DFEN_Pos HÚ P COMP_CR1_DFEN_Msk OÚ P COMP_CR1_CMP1OR_Pos ¯Ú P COMP_CR1_CMP1OR_Msk ¶Ú P COMP_CR1_CMP1OF_Pos »Ú P COMP_CR1_CMP1OF_Msk ÂÚ P COMP_CR1_V1NSEL_Pos ¨Ú P COMP_CR1_V1NSEL_Msk ¯Ú# P COMP_CR1_V1NSEL_COMP1_INN1 ÷Ú# P COMP_CR1_V1NSEL_COMP1_INN2 öÚ P COMP_CR1_V1NSEL_VREF ¥Ú! P COMP_CR1_V1NSEL_3_4_VREF xÚ! P COMP_CR1_V1NSEL_1_2_VREF |Ú! P COMP_CR1_V1NSEL_1_4_VREF zÚ! P COMP_CR1_V1NSEL_1_8_VREF vÚ P COMP_CR1_V1PSEL_Pos ¦Ú P COMP_CR1_V1PSEL_Msk Ú# P COMP_CR1_V1PSEL_COMP1_INP1 óÚ# P COMP_CR1_V1PSEL_COMP1_INP2 òÚ# P COMP_CR1_V1PSEL_COMP1_INP3 ñÚ# P COMP_CR1_V1PSEL_COMP1_INP4 ðÚ P COMP_CR1_CMP1EN_Pos ½Ú P COMP_CR1_CMP1EN_Msk ÄÚ P COMP_CR2_DFLEN_Pos ùÚ P COMP_CR2_DFLEN_Msk Ú P COMP_CR2_DFLEN_X3 ¢Ú P COMP_CR2_DFLEN_X32 nÚ P COMP_CR2_WINMODE_Pos KÚ P COMP_CR2_WINMODE_Msk RÚ P COMP_CR2_POLAR_Pos äÚ P COMP_CR2_POLAR_Msk ëÚ P COMP_CR2_POLAR_POS $Ú P COMP_CR2_POLAR_NEG <Ú P COMP_CR2_DFEN_Pos GÚ P COMP_CR2_DFEN_Msk NÚ P COMP_CR2_CMP2OR_Pos Ú P COMP_CR2_CMP2OR_Msk ´Ú P COMP_CR2_CMP2OF_Pos ¹Ú P COMP_CR2_CMP2OF_Msk ÀÚ P COMP_CR2_V2NSEL_Pos ¦Ú P COMP_CR2_V2NSEL_Msk Ú# P COMP_CR2_V2NSEL_COMP2_INN1 ôÚ# P COMP_CR2_V2NSEL_COMP2_INN2 óÚ P COMP_CR2_V2NSEL_VREF £Ú! P COMP_CR2_V2NSEL_3_4_VREF vÚ! P COMP_CR2_V2NSEL_1_2_VREF zÚ! P COMP_CR2_V2NSEL_1_4_VREF xÚ! P COMP_CR2_V2NSEL_1_8_VREF tÚ P COMP_CR2_V2NSEL_REFIN `Ú P COMP_CR2_V2PSEL_Pos ¤Ú P COMP_CR2_V2PSEL_Msk «Ú# P COMP_CR2_V2PSEL_COMP2_INP1 ðÚ# P COMP_CR2_V2PSEL_COMP2_INP2 ïÚ# P COMP_CR2_V2PSEL_COMP1_INP1 ñÚ# P COMP_CR2_V2PSEL_COMP1_INP2 ðÚ P COMP_CR2_V2PSEL_AVREF ^Ú P COMP_CR2_V2PSEL_VDD15 Ú P COMP_CR2_CMP2EN_Pos »Ú P COMP_CR2_CMP2EN_Msk ÂÚ P COMP_ICR_OOW_IE_Pos gÚ P COMP_ICR_OOW_IE_Msk nÚ P COMP_ICR_WIN_IE_Pos nÚ P COMP_ICR_WIN_IE_Msk uÚ P COMP_ICR_BUFBYP_Pos Ú P COMP_ICR_BUFBYP_Msk Ú P COMP_ICR_BUF_OFF_Pos 0Ú P COMP_ICR_BUF_OFF_Msk 7Ú P COMP_ICR_CMP2SEL_Pos QÚ P COMP_ICR_CMP2SEL_Msk XÚ P COMP_ICR_CMP2SEL_BOTH TÚ P COMP_ICR_CMP2SEL_RISING ±Ú! P COMP_ICR_CMP2SEL_FALLING ~Ú P COMP_ICR_CMP1SEL_Pos RÚ P COMP_ICR_CMP1SEL_Msk YÚ P COMP_ICR_CMP1SEL_BOTH UÚ P COMP_ICR_CMP1SEL_RISING ²Ú! P COMP_ICR_CMP1SEL_FALLING Ú P COMP_ICR_CMP2IE_Pos ©Ú P COMP_ICR_CMP2IE_Msk °Ú P COMP_ICR_CMP1IE_Pos ªÚ P COMP_ICR_CMP1IE_Msk ±Ú P COMP_ISR_OOW_IF_Pos VÚ P COMP_ISR_OOW_IF_Msk ]Ú P COMP_ISR_WIN_IF_Pos ]Ú P COMP_ISR_WIN_IF_Msk dÚ P COMP_ISR_CMP2IF_Pos Ú P COMP_ISR_CMP2IF_Msk Ú P COMP_ISR_CMP1IF_Pos Ú P COMP_ISR_CMP1IF_Msk Ú! P COMP_PCR_HSCMPBUF_EN_Pos îÚ! P COMP_PCR_HSCMPBUF_EN_Msk õÚ" P COMP_PCR_HSCMPBUF_EN_SLOW ÙÚ" P COMP_PCR_HSCMPBUF_EN_FAST ðÚ P COMP_PCR_HSCMP2_EN_Pos Ú P COMP_PCR_HSCMP2_EN_Msk ¤Ú P COMP_PCR_HSCMP2_EN_SLOW Ú P COMP_PCR_HSCMP2_EN_FAST Ú P COMP_PCR_HSCMP1_EN_Pos Ú P COMP_PCR_HSCMP1_EN_Msk ¥Ú P COMP_PCR_HSCMP1_EN_SLOW Ú P COMP_PCR_HSCMP1_EN_FAST Ú COMP_Deinit çÚ ,
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SetValue ¦Ú COMP_CR1_DFLEN_Set Ú COMP_CR1_DFLEN_Get )Ú ," NewState Ú! COMP_CR1_WINMODE_Setable ÓÚ! COMP_CR1_WINMODE_Getable ßÚ ,
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SetValue ¦Ú COMP_CR1_POLAR_Set Ú COMP_CR1_POLAR_Get Ú ," NewState Ú COMP_CR1_DFEN_Setable ÏÚ COMP_CR1_DFEN_Getable ÛÚ COMP_CR1_CMP1OR_Chk èÚ COMP_CR1_CMP1OF_Chk ôÚ ,
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SetValue ¦Ú COMP_CR1_V1NSEL_Set ËÚ COMP_CR1_V1NSEL_Get ×Ú ,
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SetValue ¦Ú COMP_CR1_V1PSEL_Set ÉÚ COMP_CR1_V1PSEL_Get ÕÚ ," NewState Ú COMP_CR1_CMP1EN_Setable DÚ COMP_CR1_CMP1EN_Getable PÚ ,
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SetValue ¦Ú COMP_CR2_DFLEN_Set Ú COMP_CR2_DFLEN_Get (Ú ," NewState Ú! COMP_CR2_WINMODE_Setable ÒÚ! COMP_CR2_WINMODE_Getable ÞÚ ,
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SetValue ¦Ú COMP_CR2_POLAR_Set Ú COMP_CR2_POLAR_Get Ú ," NewState Ú COMP_CR2_DFEN_Setable ÎÚ COMP_CR2_DFEN_Getable ÚÚ COMP_CR2_CMP2OR_Chk æÚ COMP_CR2_CMP2OF_Chk òÚ ,
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SetValue ¦Ú COMP_CR2_V2NSEL_Set ÉÚ COMP_CR2_V2NSEL_Get ÕÚ ,
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SetValue ¦Ú COMP_CR2_V2PSEL_Set ÇÚ COMP_CR2_V2PSEL_Get ÓÚ ," NewState Ú COMP_CR2_CMP2EN_Setable BÚ COMP_CR2_CMP2EN_Getable NÚ ," NewState Ú COMP_ICR_OOW_IE_Setable îÚ COMP_ICR_OOW_IE_Getable úÚ ," NewState Ú COMP_ICR_WIN_IE_Setable õÚ COMP_ICR_WIN_IE_Getable Ú ," NewState Ú COMP_ICR_BUFBYP_Setable Ú COMP_ICR_BUFBYP_Getable Ú ," NewState Ú! COMP_ICR_BUF_OFF_Setable ·Ú! COMP_ICR_BUF_OFF_Getable ÃÚ ,
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SetValue ¦Ú COMP_ICR_CMP2SEL_Set tÚ COMP_ICR_CMP2SEL_Get Ú ,
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SetValue ¦Ú COMP_ICR_CMP1SEL_Set uÚ COMP_ICR_CMP1SEL_Get Ú ," NewState Ú COMP_ICR_CMP2IE_Setable 0Ú COMP_ICR_CMP2IE_Getable <Ú ," NewState Ú COMP_ICR_CMP1IE_Setable 1Ú COMP_ICR_CMP1IE_Getable =Ú COMP_ISR_OOW_IF_Clr Ú COMP_ISR_OOW_IF_Chk Ú COMP_ISR_WIN_IF_Clr Ú COMP_ISR_WIN_IF_Chk Ú COMP_ISR_CMP2IF_Clr ÆÚ COMP_ISR_CMP2IF_Chk ÑÚ COMP_ISR_CMP1IF_Clr ÇÚ COMP_ISR_CMP1IF_Chk ÒÚ ,
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SetValue ¦Ú! COMP_PCR_HSCMPBUF_EN_Set Ú! COMP_PCR_HSCMPBUF_EN_Get Ú ,
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SetValue ¦Ú COMP_PCR_HSCMP2_EN_Set ÀÚ COMP_PCR_HSCMP2_EN_Get ÌÚ ,
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SetValue ¦Ú COMP_PCR_HSCMP1_EN_Set ÁÚ COMP_PCR_HSCMP1_EN_Get ÍÚ P __FM33A0XXEV_RMU_H :Ú P RMU_PDRCR_PDRCFG_Pos /Ú P RMU_PDRCR_PDRCFG_Msk 6Ú P RMU_PDRCR_PDRCFG_1P5V SÚ P RMU_PDRCR_PDRCFG_1P25V Ú P RMU_PDRCR_PDRCFG_1P35V Ú P RMU_PDRCR_PDRCFG_1P4V TÚ P RMU_PDRCR_PDREN_Pos nÚ P RMU_PDRCR_PDREN_Msk uÚ! P RMU_BORCR_BOR_PDRCFG_Pos èÚ! P RMU_BORCR_BOR_PDRCFG_Msk ïÚ" P RMU_BORCR_BOR_PDRCFG_1P7V
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Ú" P RMU_BORCR_BOR_PDRCFG_1P6V Ú# P RMU_BORCR_BOR_PDRCFG_1P65V ÔÚ# P RMU_BORCR_BOR_PDRCFG_1P75V ÓÚ P RMU_BORCR_OFF_BOR_Pos ÉÚ P RMU_BORCR_OFF_BOR_Msk ÐÚ# P RMU_RSTCFGR_LKUPRST_EN_Pos Ú# P RMU_RSTCFGR_LKUPRST_EN_Msk Ú P RMU_SOFTRST_SOFTRST_Pos ðÚ P RMU_SOFTRST_SOFTRST_Msk ÷Ú P RMU_RSR_NRSTN_FLAG_Pos WÚ P RMU_RSR_NRSTN_FLAG_Msk ^Ú P RMU_RSR_TESTN_FLAG_Pos ^Ú P RMU_RSR_TESTN_FLAG_Msk eÚ P RMU_RSR_PORN_FLAG_Pos ¯Ú P RMU_RSR_PORN_FLAG_Msk ¶Ú P RMU_RSR_PDRN_FLAG_Pos ºÚ P RMU_RSR_PDRN_FLAG_Msk ÁÚ P RMU_RSR_SOFTN_FLAG_Pos bÚ P RMU_RSR_SOFTN_FLAG_Msk iÚ P RMU_RSR_IWDTN_FLAG_Pos fÚ P RMU_RSR_IWDTN_FLAG_Msk mÚ P RMU_RSR_WWDTN_FLAG_Pos XÚ P RMU_RSR_WWDTN_FLAG_Msk _Ú P RMU_RSR_LKUPN_FLAG_Pos bÚ P RMU_RSR_LKUPN_FLAG_Msk iÚ P RMU_RSR_NVICN_FLAG_Pos nÚ P RMU_RSR_NVICN_FLAG_Msk uÚ! P RMU_PRSTEN_PERHRSTEN_Pos ÁÚ! P RMU_PRSTEN_PERHRSTEN_Msk ÈÚ P RMU_AHBRST_HASHRST_Pos {Ú P RMU_AHBRST_HASHRST_Msk Ú P RMU_AHBRST_PAERST_Pos ËÚ P RMU_AHBRST_PAERST_Msk ÒÚ P RMU_AHBRST_DMARST_Pos ÏÚ P RMU_AHBRST_DMARST_Msk ÖÚ! P RMU_APBRST1_UART5RST_Pos ñÚ! P RMU_APBRST1_UART5RST_Msk øÚ! P RMU_APBRST1_UART4RST_Pos òÚ! P RMU_APBRST1_UART4RST_Msk ùÚ! P RMU_APBRST1_UART3RST_Pos óÚ! P RMU_APBRST1_UART3RST_Msk úÚ! P RMU_APBRST1_UART2RST_Pos ôÚ! P RMU_APBRST1_UART2RST_Msk ûÚ P RMU_APBRST1_TIMARST_Pos 9Ú P RMU_APBRST1_TIMARST_Msk @Ú P RMU_APBRST1_LCDRST_Pos Ú P RMU_APBRST1_LCDRST_Msk Ú! P RMU_APBRST1_U7816RST_Pos 7Ú! P RMU_APBRST1_U7816RST_Msk >Ú P RMU_APBRST1_SPI4RST_Pos DÚ P RMU_APBRST1_SPI4RST_Msk KÚ P RMU_APBRST1_SPI3RST_Pos EÚ P RMU_APBRST1_SPI3RST_Msk LÚ P RMU_APBRST1_SPI2RST_Pos FÚ P RMU_APBRST1_SPI2RST_Msk MÚ# P RMU_APBRST1_LPUART0RST_Pos VÚ# P RMU_APBRST1_LPUART0RST_Msk ]Ú P RMU_APBRST1_I2C1RST_Pos uÚ P RMU_APBRST1_I2C1RST_Msk |Ú P RMU_APBRST1_LPTRST_Pos vÚ P RMU_APBRST1_LPTRST_Msk }Ú! P RMU_APBRST2_UART1RST_Pos ôÚ! P RMU_APBRST2_UART1RST_Msk ûÚ! P RMU_APBRST2_UART0RST_Pos õÚ! P RMU_APBRST2_UART0RST_Msk üÚ" P RMU_APBRST2_UARTIRRST_Pos Ú" P RMU_APBRST2_UARTIRRST_Msk Ú P RMU_APBRST2_BSTRST_Pos |Ú P RMU_APBRST2_BSTRST_Msk Ú P RMU_APBRST2_CICRST_Pos Ú P RMU_APBRST2_CICRST_Msk Ú P RMU_APBRST2_ADCRST_Pos Ú P RMU_APBRST2_ADCRST_Msk ¤Ú P RMU_APBRST2_AESRST_Pos Ú P RMU_APBRST2_AESRST_Msk Ú P RMU_APBRST2_CRCRST_Pos Ú P RMU_APBRST2_CRCRST_Msk Ú P RMU_APBRST2_RNGRST_Pos ~Ú P RMU_APBRST2_RNGRST_Msk
Ú P RMU_APBRST2_SPI1RST_Pos FÚ P RMU_APBRST2_SPI1RST_Msk MÚ P RMU_APBRST2_SPI0RST_Pos GÚ P RMU_APBRST2_SPI0RST_Msk NÚ# P RMU_APBRST2_LPUART1RST_Pos TÚ# P RMU_APBRST2_LPUART1RST_Msk [Ú P RMU_APBRST2_I2C0RST_Pos uÚ P RMU_APBRST2_I2C0RST_Msk |Ú P RMU_APBRST2_SVDRST_Pos xÚ P RMU_APBRST2_SVDRST_Msk Ú P RMU_APBRST2_COMPRST_Pos 4Ú P RMU_APBRST2_COMPRST_Msk ;Ú RMU_Deinit $Ú ,
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SetValue ¦Ú RMU_PDRCR_PDRCFG_Set RÚ RMU_PDRCR_PDRCFG_Get ^Ú ," NewState Ú RMU_PDRCR_PDREN_Setable õÚ RMU_PDRCR_PDREN_Getable Ú ,
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SetValue ¦Ú! RMU_BORCR_BOR_PDRCFG_Set Ú! RMU_BORCR_BOR_PDRCFG_Get Ú ," NewState Ú" RMU_BORCR_OFF_BOR_Setable PÚ" RMU_BORCR_OFF_BOR_Getable \Ú ," NewState Ú' RMU_RSTCFGR_LKUPRST_EN_Setable Ú' RMU_RSTCFGR_LKUPRST_EN_Getable ¥Ú ,
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SetValue ¦Ú RMU_SOFTRST_Write ÔÚ RMU_RSR_NRSTN_FLAG_Clr
Ú RMU_RSR_NRSTN_FLAG_Chk Ú RMU_RSR_TESTN_FLAG_Clr Ú RMU_RSR_TESTN_FLAG_Chk Ú RMU_RSR_PORN_FLAG_Clr ÝÚ RMU_RSR_PORN_FLAG_Chk èÚ RMU_RSR_PDRN_FLAG_Clr èÚ RMU_RSR_PDRN_FLAG_Chk óÚ RMU_RSR_SOFTN_FLAG_Clr Ú RMU_RSR_SOFTN_FLAG_Chk Ú RMU_RSR_IWDTN_FLAG_Clr Ú RMU_RSR_IWDTN_FLAG_Chk Ú RMU_RSR_WWDTN_FLAG_Clr Ú RMU_RSR_WWDTN_FLAG_Chk Ú RMU_RSR_LKUPN_FLAG_Clr Ú RMU_RSR_LKUPN_FLAG_Chk Ú RMU_RSR_NVICN_FLAG_Clr Ú RMU_RSR_NVICN_FLAG_Chk §Ú ,
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SetValue ¦Ú RMU_PRSTEN_Write /Ú ," NewState Ú# RMU_AHBRST_HASHRST_Setable Ú# RMU_AHBRST_HASHRST_Getable Ú ," NewState Ú" RMU_AHBRST_PAERST_Setable RÚ" RMU_AHBRST_PAERST_Getable ^Ú ," NewState Ú" RMU_AHBRST_DMARST_Setable VÚ" RMU_AHBRST_DMARST_Getable bÚ ," NewState Ú% RMU_APBRST1_UART5RST_Setable xÚ% RMU_APBRST1_UART5RST_Getable Ú ," NewState Ú% RMU_APBRST1_UART4RST_Setable yÚ% RMU_APBRST1_UART4RST_Getable
Ú ," NewState Ú% RMU_APBRST1_UART3RST_Setable zÚ% RMU_APBRST1_UART3RST_Getable Ú ," NewState Ú% RMU_APBRST1_UART2RST_Setable {Ú% RMU_APBRST1_UART2RST_Getable Ú ," NewState Ú$ RMU_APBRST1_TIMARST_Setable ÀÚ$ RMU_APBRST1_TIMARST_Getable ÌÚ ," NewState Ú# RMU_APBRST1_LCDRST_Setable Ú# RMU_APBRST1_LCDRST_Getable &Ú ," NewState Ú% RMU_APBRST1_U7816RST_Setable ¾Ú% RMU_APBRST1_U7816RST_Getable ÊÚ ," NewState Ú$ RMU_APBRST1_SPI4RST_Setable ËÚ$ RMU_APBRST1_SPI4RST_Getable ×Ú ," NewState Ú$ RMU_APBRST1_SPI3RST_Setable ÌÚ$ RMU_APBRST1_SPI3RST_Getable ØÚ ," NewState Ú$ RMU_APBRST1_SPI2RST_Setable ÍÚ$ RMU_APBRST1_SPI2RST_Getable ÙÚ ," NewState Ú' RMU_APBRST1_LPUART0RST_Setable ÝÚ' RMU_APBRST1_LPUART0RST_Getable éÚ ," NewState Ú$ RMU_APBRST1_I2C1RST_Setable üÚ$ RMU_APBRST1_I2C1RST_Getable Ú ," NewState Ú# RMU_APBRST1_LPTRST_Setable ýÚ# RMU_APBRST1_LPTRST_Getable Ú ," NewState Ú% RMU_APBRST2_UART1RST_Setable {Ú% RMU_APBRST2_UART1RST_Getable Ú ," NewState Ú% RMU_APBRST2_UART0RST_Setable |Ú% RMU_APBRST2_UART0RST_Getable Ú ," NewState Ú& RMU_APBRST2_UARTIRRST_Setable Ú& RMU_APBRST2_UARTIRRST_Getable Ú ," NewState Ú# RMU_APBRST2_BSTRST_Setable Ú# RMU_APBRST2_BSTRST_Getable Ú ," NewState Ú# RMU_APBRST2_CICRST_Setable Ú# RMU_APBRST2_CICRST_Getable )Ú ," NewState Ú# RMU_APBRST2_ADCRST_Setable $Ú# RMU_APBRST2_ADCRST_Getable 0Ú ," NewState Ú# RMU_APBRST2_AESRST_Setable Ú# RMU_APBRST2_AESRST_Getable Ú ," NewState Ú# RMU_APBRST2_CRCRST_Setable Ú# RMU_APBRST2_CRCRST_Getable Ú ," NewState Ú# RMU_APBRST2_RNGRST_Setable Ú# RMU_APBRST2_RNGRST_Getable Ú ," NewState Ú$ RMU_APBRST2_SPI1RST_Setable ÍÚ$ RMU_APBRST2_SPI1RST_Getable ÙÚ ," NewState Ú$ RMU_APBRST2_SPI0RST_Setable ÎÚ$ RMU_APBRST2_SPI0RST_Getable ÚÚ ," NewState Ú' RMU_APBRST2_LPUART1RST_Setable ÛÚ' RMU_APBRST2_LPUART1RST_Getable çÚ ," NewState Ú$ RMU_APBRST2_I2C0RST_Setable üÚ$ RMU_APBRST2_I2C0RST_Getable Ú ," NewState Ú# RMU_APBRST2_SVDRST_Setable ÿÚ# RMU_APBRST2_SVDRST_Getable Ú ," NewState Ú$ RMU_APBRST2_COMPRST_Setable »Ú$ RMU_APBRST2_COMPRST_Getable ÇÚ P __FM33A0XXEV_CRC_H VÚ 8
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<unnamed> QÚ
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" óCRCSEL ÿÚ
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" óOPWD
Ú
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" óPARA Ú
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" óRFLTIN ìÚ
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" óRFLTO 6Ú "" óXOR ³Ú
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" óCRC_XOR Ú
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" óCRCPOLY Ú
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" óLFSR Ú CRC_InitTypeDef gÚ P CRC_DR_DR_Pos ^Ú P CRC_DR_DR_Msk eÚ P CRC_CR_OPWD_Pos ·Ú P CRC_CR_OPWD_Msk ¾Ú P CRC_CR_OPWD_BYTE ³Ú P CRC_CR_OPWD_WORD «Ú P CRC_CR_PARA_Pos ÍÚ P CRC_CR_PARA_Msk ÔÚ P CRC_CR_PARA_SERIAL 9Ú P CRC_CR_PARA_PARALLEL ¨Ú P CRC_CR_RFLTIN_Pos Ú P CRC_CR_RFLTIN_Msk %Ú P CRC_CR_RFLTIN_NONE Ú P CRC_CR_RFLTIN_BYTE Ú P CRC_CR_RFLTIN_HALFWORD ïÚ P CRC_CR_RFLTIN_WORD Ú P CRC_CR_RFLTO_Pos hÚ P CRC_CR_RFLTO_Msk oÚ P CRC_CR_RFLTO_NON ¯Ú P CRC_CR_RFLTO_BYTE dÚ P CRC_CR_RES_Pos Ú P CRC_CR_RES_Msk Ú P CRC_CR_BUSY_Pos ®Ú P CRC_CR_BUSY_Msk µÚ P CRC_CR_XOR_Pos úÚ P CRC_CR_XOR_Msk Ú P CRC_CR_SEL_Pos Ú P CRC_CR_SEL_Msk Ú P CRC_CR_SEL_CRC32 Ú P CRC_CR_SEL_CRC16 þÚ P CRC_CR_SEL_CRC8 /Ú P CRC_CR_SEL_CRC7 0Ú P CRC_LFSR_LFSR_Pos Ú P CRC_LFSR_LFSR_Msk Ú P CRC_XOR_XOR_Pos Ú P CRC_XOR_XOR_Msk Ú P CRC_POLY_POLY_Pos úÚ P CRC_POLY_POLY_Msk Ú CRC_Deinit @Ú ,
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SetValue ¦Ú CRC_DR_Write Ú CRC_DR_Read *Ú ,
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SetValue ¦Ú CRC_CR_OPWD_Set ÚÚ CRC_CR_OPWD_Get æÚ ,
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SetValue ¦Ú CRC_CR_PARA_Set ðÚ CRC_CR_PARA_Get üÚ ,
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SetValue ¦Ú CRC_CR_RFLTIN_Set AÚ CRC_CR_RFLTIN_Get MÚ ,
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SetValue ¦Ú CRC_CR_RFLTO_Set Ú CRC_CR_RFLTO_Get Ú CRC_CR_RES_Chk BÚ CRC_CR_BUSY_Chk çÚ ," NewState Ú CRC_CR_XOR_Setable Ú CRC_CR_XOR_Getable Ú ,
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SetValue ¦Ú CRC_CR_SEL_Set 2Ú CRC_CR_SEL_Get >Ú ,
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SetValue ¦Ú CRC_LFSR_Write ôÚ CRC_LFSR_Read
Ú ,
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SetValue ¦Ú CRC_XOR_Write 4Ú CRC_XOR_Read ÅÚ ,
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SetValue ¦Ú CRC_POLY_Write çÚ CRC_POLY_Read xÚ , para %Ú CRC_Init Ú P __FM33A0XXEV_LCD_H [Ú P LCD_CR_SCSEL_Pos zÚ P LCD_CR_SCSEL_Msk Ú P LCD_CR_SCSEL_LSCLK_COM éÚ P LCD_CR_SCSEL_LSCLK_8 Ú P LCD_CR_SCSEL_LSCLK_16 cÚ P LCD_CR_SCSEL_LSCLK_32 eÚ P LCD_CR_SCSEL_LSCLK_64 `Ú P LCD_CR_SCSEL_LSCLK_128 -Ú P LCD_CR_SCSEL_LSCLK_256 +Ú P LCD_CR_SCSEL_LSCLK_512 0Ú P LCD_CR_SC_CTRL_Pos ÆÚ P LCD_CR_SC_CTRL_Msk ÍÚ P LCD_CR_SC_CTRL_S0 wÚ P LCD_CR_SC_CTRL_S1 vÚ P LCD_CR_SC_CTRL_S2 uÚ P LCD_CR_SC_CTRL_S3 tÚ P LCD_CR_IC_CTRL_Pos ÐÚ P LCD_CR_IC_CTRL_Msk ×Ú P LCD_CR_IC_CTRL_L3
Ú P LCD_CR_IC_CTRL_L2 Ú P LCD_CR_IC_CTRL_L1 Ú P LCD_CR_IC_CTRL_L0 Ú P LCD_CR_ENMODE_Pos :Ú P LCD_CR_ENMODE_Msk AÚ" P LCD_CR_ENMODE_EXTERNALCAP %Ú$ P LCD_CR_ENMODE_INNERRESISTER kÚ P LCD_CR_FLICK_Pos Ú P LCD_CR_FLICK_Msk Ú P LCD_CR_BIAS_Pos ×Ú P LCD_CR_BIAS_Msk ÞÚ P LCD_CR_BIASMD_Pos BÚ P LCD_CR_BIASMD_Msk IÚ P LCD_CR_BIASMD_3BIAS Ú P LCD_CR_BIASMD_4BIAS Ú P LCD_CR_ANTIPOLAR_Pos BÚ P LCD_CR_ANTIPOLAR_Msk IÚ P LCD_CR_ANTIPOLAR_GND Ú P LCD_CR_ANTIPOLAR_FLOAT úÚ P LCD_CR_WFT_Pos Ú P LCD_CR_WFT_Msk Ú P LCD_CR_WFT_BTYPE ±Ú P LCD_CR_WFT_ATYPE ²Ú P LCD_CR_LMUX_Pos °Ú P LCD_CR_LMUX_Msk ·Ú P LCD_CR_LMUX_4COM ÍÚ P LCD_CR_LMUX_6COM ËÚ P LCD_CR_LMUX_8COM ÉÚ P LCD_CR_EN_Pos gÚ P LCD_CR_EN_Msk nÚ P LCD_TEST_LCCTRL_Pos Ú P LCD_TEST_LCCTRL_Msk Ú P LCD_TEST_LCCTRL_LOW ¿Ú P LCD_TEST_LCCTRL_HIGH Ú P LCD_TEST_TESTEN_Pos pÚ P LCD_TEST_TESTEN_Msk wÚ P LCD_FCR_DF_Pos (Ú P LCD_FCR_DF_Msk /Ú P LCD_FLKT_TOFF_Pos 'Ú P LCD_FLKT_TOFF_Msk .Ú P LCD_FLKT_TON_Pos gÚ P LCD_FLKT_TON_Msk nÚ P LCD_IER_DONIE_Pos 8Ú P LCD_IER_DONIE_Msk ?Ú P LCD_IER_DOFFIE_Pos øÚ P LCD_IER_DOFFIE_Msk ÿÚ P LCD_ISR_DONIF_Pos )Ú P LCD_ISR_DONIF_Msk 0Ú P LCD_ISR_DOFFIF_Pos éÚ P LCD_ISR_DOFFIF_Msk ðÚ P LCD_BSTCR_OSC_CFG_Pos íÚ P LCD_BSTCR_OSC_CFG_Msk ôÚ P LCD_BSTCR_BUF_OFF_Pos êÚ P LCD_BSTCR_BUF_OFF_Msk ñÚ P LCD_BSTCR_BUFBYP_Pos ;Ú P LCD_BSTCR_BUFBYP_Msk BÚ P LCD_BSTCR_VLCDPD_Pos FÚ P LCD_BSTCR_VLCDPD_Msk MÚ P LCD_BSTCR_VLCDCFG_Pos Ú P LCD_BSTCR_VLCDCFG_Msk Ú P LCD_BSTCR_VLCDCFG_2_4V Ú P LCD_BSTCR_VLCDCFG_2_6V Ú P LCD_BSTCR_VLCDCFG_2_8V Ú P LCD_BSTCR_VLCDCFG_3_0V Ú P LCD_BSTCR_VLCDCFG_3_2V Ú P LCD_BSTCR_VLCDCFG_3_4V Ú P LCD_BSTCR_VLCDCFG_3_6V Ú P LCD_BSTCR_VLCDCFG_3_8V Ú P LCD_BSTCR_VLCDCFG_4_0V Ú P LCD_BSTCR_VLCDCFG_4_2V Ú P LCD_BSTCR_VLCDCFG_4_4V Ú P LCD_BSTCR_VLCDCFG_4_6V Ú P LCD_BSTCR_VLCDCFG_4_8V Ú P LCD_BSTCR_VLCDCFG_5_0V Ú P LCD_BSTCR_VLCDCFG_5_2V Ú P LCD_BSTCR_VLCDCFG_5_4V Ú P LCD_BSTCR_BOOST_TEN_Pos 0Ú P LCD_BSTCR_BOOST_TEN_Msk 7Ú P LCD_BSTCR_BOOST_EN_Pos Ú P LCD_BSTCR_BOOST_EN_Msk Ú P LCD_COM_EN_COMEN_Pos >Ú P LCD_COM_EN_COMEN_Msk EÚ P LCD_SEG_EN0_SEGENx_Pos Ú P LCD_SEG_EN0_SEGENx_Msk Ú P LCD_SEG_EN1_SEGENx_Pos Ú P LCD_SEG_EN1_SEGENx_Msk Ú P LCD_COM_EN_COMEN3_Pos Ú P LCD_COM_EN_COMEN3_Msk Ú P LCD_COM_EN_COMEN2_Pos
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Ú P LCD_COM_EN_COMEN2_Msk Ú P LCD_COM_EN_COMEN1_Pos Ú P LCD_COM_EN_COMEN1_Msk Ú P LCD_COM_EN_COMEN0_Pos Ú P LCD_COM_EN_COMEN0_Msk Ú P LCD_SEG_EN0_SEGEN31_Pos ¤Ú P LCD_SEG_EN0_SEGEN31_Msk «Ú P LCD_SEG_EN0_SEGEN30_Pos ¥Ú P LCD_SEG_EN0_SEGEN30_Msk ¬Ú P LCD_SEG_EN0_SEGEN29_Pos Ú P LCD_SEG_EN0_SEGEN29_Msk ¤Ú P LCD_SEG_EN0_SEGEN28_Pos Ú P LCD_SEG_EN0_SEGEN28_Msk ¥Ú P LCD_SEG_EN0_SEGEN27_Pos Ú P LCD_SEG_EN0_SEGEN27_Msk ¦Ú P LCD_SEG_EN0_SEGEN26_Pos Ú P LCD_SEG_EN0_SEGEN26_Msk §Ú P LCD_SEG_EN0_SEGEN25_Pos ¡Ú P LCD_SEG_EN0_SEGEN25_Msk ¨Ú P LCD_SEG_EN0_SEGEN24_Pos ¢Ú P LCD_SEG_EN0_SEGEN24_Msk ©Ú P LCD_SEG_EN0_SEGEN23_Pos £Ú P LCD_SEG_EN0_SEGEN23_Msk ªÚ P LCD_SEG_EN0_SEGEN22_Pos ¤Ú P LCD_SEG_EN0_SEGEN22_Msk «Ú P LCD_SEG_EN0_SEGEN21_Pos ¥Ú P LCD_SEG_EN0_SEGEN21_Msk ¬Ú P LCD_SEG_EN0_SEGEN20_Pos ¦Ú P LCD_SEG_EN0_SEGEN20_Msk Ú P LCD_SEG_EN0_SEGEN19_Pos Ú P LCD_SEG_EN0_SEGEN19_Msk ¥Ú P LCD_SEG_EN0_SEGEN18_Pos Ú P LCD_SEG_EN0_SEGEN18_Msk ¦Ú P LCD_SEG_EN0_SEGEN17_Pos Ú P LCD_SEG_EN0_SEGEN17_Msk §Ú P LCD_SEG_EN0_SEGEN16_Pos ¡Ú P LCD_SEG_EN0_SEGEN16_Msk ¨Ú P LCD_SEG_EN0_SEGEN15_Pos ¢Ú P LCD_SEG_EN0_SEGEN15_Msk ©Ú P LCD_SEG_EN0_SEGEN14_Pos £Ú P LCD_SEG_EN0_SEGEN14_Msk ªÚ P LCD_SEG_EN0_SEGEN13_Pos ¤Ú P LCD_SEG_EN0_SEGEN13_Msk «Ú P LCD_SEG_EN0_SEGEN12_Pos ¥Ú P LCD_SEG_EN0_SEGEN12_Msk ¬Ú P LCD_SEG_EN0_SEGEN11_Pos ¦Ú P LCD_SEG_EN0_SEGEN11_Msk Ú P LCD_SEG_EN0_SEGEN10_Pos §Ú P LCD_SEG_EN0_SEGEN10_Msk ®Ú P LCD_SEG_EN0_SEGEN9_Pos ÑÚ P LCD_SEG_EN0_SEGEN9_Msk ØÚ P LCD_SEG_EN0_SEGEN8_Pos ÒÚ P LCD_SEG_EN0_SEGEN8_Msk ÙÚ P LCD_SEG_EN0_SEGEN7_Pos ÓÚ P LCD_SEG_EN0_SEGEN7_Msk ÚÚ P LCD_SEG_EN0_SEGEN6_Pos ÔÚ P LCD_SEG_EN0_SEGEN6_Msk ÛÚ P LCD_SEG_EN0_SEGEN5_Pos ÕÚ P LCD_SEG_EN0_SEGEN5_Msk ÜÚ P LCD_SEG_EN0_SEGEN4_Pos ÖÚ P LCD_SEG_EN0_SEGEN4_Msk ÝÚ P LCD_SEG_EN0_SEGEN3_Pos ×Ú P LCD_SEG_EN0_SEGEN3_Msk ÞÚ P LCD_SEG_EN0_SEGEN2_Pos ØÚ P LCD_SEG_EN0_SEGEN2_Msk ßÚ P LCD_SEG_EN0_SEGEN1_Pos ÙÚ P LCD_SEG_EN0_SEGEN1_Msk àÚ P LCD_SEG_EN0_SEGEN0_Pos ÚÚ P LCD_SEG_EN0_SEGEN0_Msk áÚ P LCD_SEG_EN1_SEGEN43_Pos Ú P LCD_SEG_EN1_SEGEN43_Msk §Ú P LCD_SEG_EN1_SEGEN42_Pos ¡Ú P LCD_SEG_EN1_SEGEN42_Msk ¨Ú P LCD_SEG_EN1_SEGEN41_Pos ¢Ú P LCD_SEG_EN1_SEGEN41_Msk ©Ú P LCD_SEG_EN1_SEGEN40_Pos £Ú P LCD_SEG_EN1_SEGEN40_Msk ªÚ P LCD_SEG_EN1_SEGEN39_Pos Ú P LCD_SEG_EN1_SEGEN39_Msk ¢Ú P LCD_SEG_EN1_SEGEN38_Pos Ú P LCD_SEG_EN1_SEGEN38_Msk £Ú P LCD_SEG_EN1_SEGEN37_Pos Ú P LCD_SEG_EN1_SEGEN37_Msk ¤Ú P LCD_SEG_EN1_SEGEN36_Pos Ú P LCD_SEG_EN1_SEGEN36_Msk ¥Ú P LCD_SEG_EN1_SEGEN35_Pos Ú P LCD_SEG_EN1_SEGEN35_Msk ¦Ú P LCD_SEG_EN1_SEGEN34_Pos Ú P LCD_SEG_EN1_SEGEN34_Msk §Ú P LCD_SEG_EN1_SEGEN33_Pos ¡Ú P LCD_SEG_EN1_SEGEN33_Msk ¨Ú P LCD_SEG_EN1_SEGEN32_Pos ¢Ú P LCD_SEG_EN1_SEGEN32_Msk ©Ú P LCD_SEG_EN1_COMEN7_Pos ÒÚ P LCD_SEG_EN1_COMEN7_Msk ÙÚ P LCD_SEG_EN1_COMEN6_Pos ÓÚ P LCD_SEG_EN1_COMEN6_Msk ÚÚ P LCD_SEG_EN1_COMEN5_Pos ÔÚ P LCD_SEG_EN1_COMEN5_Msk ÛÚ P LCD_SEG_EN1_COMEN4_Pos ÕÚ P LCD_SEG_EN1_COMEN4_Msk ÜÚ LCD_Deinit EÚ ,
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SetValue ¦Ú LCD_CR_SCSEL_Set Ú LCD_CR_SCSEL_Get ©Ú ,
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SetValue ¦Ú LCD_CR_SC_CTRL_Set éÚ LCD_CR_SC_CTRL_Get õÚ ,
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SetValue ¦Ú LCD_CR_IC_CTRL_Set óÚ LCD_CR_IC_CTRL_Get ÿÚ ,
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SetValue ¦Ú LCD_CR_ENMODE_Set ]Ú LCD_CR_ENMODE_Get iÚ ," NewState Ú LCD_CR_FLICK_Setable Ú LCD_CR_FLICK_Getable Ú ,
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SetValue ¦Ú LCD_CR_BIAS_Set úÚ LCD_CR_BIAS_Get Ú ,
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SetValue ¦Ú LCD_CR_BIASMD_Set eÚ LCD_CR_BIASMD_Get qÚ ,
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SetValue ¦Ú LCD_CR_ANTIPOLAR_Set eÚ LCD_CR_ANTIPOLAR_Get qÚ ,
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SetValue ¦Ú LCD_CR_WFT_Set *Ú LCD_CR_WFT_Get 6Ú ,
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SetValue ¦Ú LCD_CR_LMUX_Set ÓÚ LCD_CR_LMUX_Get ßÚ ," NewState Ú LCD_CR_EN_Setable îÚ LCD_CR_EN_Getable úÚ ,
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SetValue ¦Ú LCD_TEST_LCCTRL_Set ¢Ú LCD_TEST_LCCTRL_Get ®Ú ," NewState Ú LCD_TEST_TESTEN_Setable ÷Ú LCD_TEST_TESTEN_Getable Ú ,
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SetValue ¦Ú LCD_FCR_Write WÚ LCD_FCR_Read èÚ ,
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SetValue ¦Ú LCD_FLKT_TOFF_Set JÚ LCD_FLKT_TOFF_Get VÚ ,
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SetValue ¦Ú LCD_FLKT_TON_Set Ú LCD_FLKT_TON_Get Ú ," NewState Ú LCD_IER_DONIE_Setable ¿Ú LCD_IER_DONIE_Getable ËÚ ," NewState Ú LCD_IER_DOFFIE_Setable Ú LCD_IER_DOFFIE_Getable Ú LCD_ISR_DONIF_Clr WÚ LCD_ISR_DONIF_Chk bÚ LCD_ISR_DOFFIF_Clr Ú LCD_ISR_DOFFIF_Chk "Ú ,
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SetValue ¦Ú LCD_BSTCR_OSC_CFG_Set Ú LCD_BSTCR_OSC_CFG_Get Ú ," NewState Ú" LCD_BSTCR_BUF_OFF_Setable qÚ" LCD_BSTCR_BUF_OFF_Getable }Ú ," NewState Ú! LCD_BSTCR_BUFBYP_Setable ÂÚ! LCD_BSTCR_BUFBYP_Getable ÎÚ ," NewState Ú! LCD_BSTCR_VLCDPD_Setable ÍÚ! LCD_BSTCR_VLCDPD_Getable ÙÚ ,
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SetValue ¦Ú LCD_BSTCR_VLCDCFG_Set +Ú LCD_BSTCR_VLCDCFG_Get 7Ú ," NewState Ú$ LCD_BSTCR_BOOST_TEN_Setable ·Ú$ LCD_BSTCR_BOOST_TEN_Getable ÃÚ ," NewState Ú# LCD_BSTCR_BOOST_EN_Setable Ú# LCD_BSTCR_BOOST_EN_Getable Ú ,
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SetValue ¦Ú LCD_COM_EN_Write [Ú LCD_COM_EN_Read ìÚ ,
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SetValue ¦Ú LCD_SEG_EN0_Write )Ú LCD_SEG_EN0_Read ºÚ ,
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SetValue ¦Ú LCD_SEG_EN1_Write (Ú LCD_SEG_EN1_Read ¹Ú , DispBuf Ú LCD_DISPDATAx_Refresh Ú P __FM33A0XXEV_DMA_H \Ú DMA_CH0 Ú DMA_CH1 Ú DMA_CH2 Ú DMA_CH3 Ú DMA_CH4 ÿÚ DMA_CH5 þÚ DMA_CH6 ýÚ DMA_CH7 üÚ DMA_CH8 ûÚ DMA_CH9 úÚ DMA_CH10 ÐÚ DMA_CH11 ÏÚ DMA_CH_Type .Ú 8
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<unnamed> QÚ "" CHx Ú
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" CHxTSIZE Ú
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" CHxPRI :Ú
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" CHxINC KÚ
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" CHxSSEL ìÚ
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" CHxDIR FÚ
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" CHxBDW HÚ "" CHxCICR íÚ "" CHxFTIE æÚ "" CHxHTIE äÚ "" CHxEN Ú
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" CHxRAMAD ¼Ú
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" CH11RI Ú
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" CH11FI ¬Ú
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"
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CH11FLSAD ËÚ DMA_InitTypeDef mÚ# P DMA_GCR_DMA_ADDRERR_EN_Pos sÚ# P DMA_GCR_DMA_ADDRERR_EN_Msk zÚ P DMA_GCR_DMAEN_Pos GÚ P DMA_GCR_DMAEN_Msk NÚ P DMA_CHxCR_CHxTSIZE_Pos TÚ P DMA_CHxCR_CHxTSIZE_Msk [Ú P DMA_CHxCR_CHxPRI_Pos üÚ P DMA_CHxCR_CHxPRI_Msk Ú P DMA_CHxCR_CHxPRI_LOW <Ú P DMA_CHxCR_CHxPRI_MEDIUM gÚ P DMA_CHxCR_CHxPRI_HIGH Ú# P DMA_CHxCR_CHxPRI_VERY_HIGH ]Ú P DMA_CHxCR_CHxINC_Pos Ú P DMA_CHxCR_CHxINC_Msk Ú" P DMA_CHxCR_CHxINC_INCREASE ëÚ" P DMA_CHxCR_CHxINC_DECREASE ùÚ P DMA_CHxCR_CHxSSEL_Pos ®Ú P DMA_CHxCR_CHxSSEL_Msk µÚ P DMA_CHxCR_CH0SSEL_ADC `Ú" P DMA_CHxCR_CH0SSEL_SPI3_RX øÚ% P DMA_CHxCR_CH0SSEL_LPUART0_RX Ú% P DMA_CHxCR_CH0SSEL_LPUART1_RX Ú# P DMA_CHxCR_CH0SSEL_UART2_RX §Ú# P DMA_CHxCR_CH0SSEL_UART4_RX ¥Ú! P DMA_CHxCR_CH0SSEL_AES_IN SÚ P DMA_CHxCR_CH0SSEL_QSPI éÚ P DMA_CHxCR_CH1SSEL_ADC _Ú" P DMA_CHxCR_CH1SSEL_SPI0_RX úÚ" P DMA_CHxCR_CH1SSEL_SPI2_RX øÚ" P DMA_CHxCR_CH1SSEL_SPI3_TX õÚ# P DMA_CHxCR_CH1SSEL_UART0_RX ¨Ú# P DMA_CHxCR_CH1SSEL_UART2_TX ¤Ú# P DMA_CHxCR_CH1SSEL_UART3_RX ¥Ú# P DMA_CHxCR_CH1SSEL_U7816_RX éÚ" P DMA_CHxCR_CH2SSEL_SPI0_TX ÷Ú" P DMA_CHxCR_CH2SSEL_SPI2_TX õÚ" P DMA_CHxCR_CH2SSEL_SPI4_RX õÚ# P DMA_CHxCR_CH2SSEL_UART0_TX ¥Ú# P DMA_CHxCR_CH2SSEL_UART3_TX ¢Ú# P DMA_CHxCR_CH2SSEL_UART5_RX ¢Ú# P DMA_CHxCR_CH2SSEL_U7816_TX æÚ" P DMA_CHxCR_CH2SSEL_AES_OUT îÚ" P DMA_CHxCR_CH3SSEL_SPI1_RX ÷Ú" P DMA_CHxCR_CH3SSEL_SPI4_TX òÚ% P DMA_CHxCR_CH3SSEL_LPUART0_RX Ú# P DMA_CHxCR_CH3SSEL_UART1_RX ¥Ú# P DMA_CHxCR_CH3SSEL_UART4_RX ¢Ú# P DMA_CHxCR_CH3SSEL_UART5_TX Ú" P DMA_CHxCR_CH3SSEL_I2C0_TX $Ú! P DMA_CHxCR_CH3SSEL_AES_IN PÚ" P DMA_CHxCR_CH4SSEL_SPI1_TX ôÚ" P DMA_CHxCR_CH4SSEL_SPI3_RX ôÚ% P DMA_CHxCR_CH4SSEL_LPUART0_TX Ú# P DMA_CHxCR_CH4SSEL_UART1_TX ¢Ú# P DMA_CHxCR_CH4SSEL_UART2_RX £Ú# P DMA_CHxCR_CH4SSEL_UART4_TX Ú" P DMA_CHxCR_CH4SSEL_I2C0_RX %Ú" P DMA_CHxCR_CH4SSEL_AES_OUT ìÚ" P DMA_CHxCR_CH5SSEL_SPI0_RX öÚ" P DMA_CHxCR_CH5SSEL_SPI2_RX ôÚ% P DMA_CHxCR_CH5SSEL_LPUART1_RX Ú# P DMA_CHxCR_CH5SSEL_UART1_RX £Ú# P DMA_CHxCR_CH5SSEL_UART2_TX Ú# P DMA_CHxCR_CH5SSEL_UART3_RX ¡Ú# P DMA_CHxCR_CH5SSEL_UART5_RX Ú" P DMA_CHxCR_CH5SSEL_I2C1_TX !Ú" P DMA_CHxCR_CH6SSEL_SPI0_TX óÚ" P DMA_CHxCR_CH6SSEL_SPI2_TX ñÚ% P DMA_CHxCR_CH6SSEL_LPUART1_TX Ú# P DMA_CHxCR_CH6SSEL_UART1_TX Ú# P DMA_CHxCR_CH6SSEL_UART3_TX Ú# P DMA_CHxCR_CH6SSEL_UART5_TX Ú" P DMA_CHxCR_CH6SSEL_I2C1_RX "Ú P DMA_CHxCR_CH6SSEL_CRC JÚ P DMA_CHxCR_CH7SSEL_ADC YÚ" P DMA_CHxCR_CH7SSEL_SPI1_RX óÚ" P DMA_CHxCR_CH7SSEL_SPI3_RX ñÚ% P DMA_CHxCR_CH7SSEL_LPUART0_RX Ú# P DMA_CHxCR_CH7SSEL_UART0_RX ¢Ú# P DMA_CHxCR_CH7SSEL_UART2_RX Ú# P DMA_CHxCR_CH7SSEL_UART4_RX Ú P DMA_CHxCR_CH7SSEL_QSPI âÚ P DMA_CHxCR_CH8SSEL_ADC XÚ" P DMA_CHxCR_CH8SSEL_SPI1_TX ðÚ" P DMA_CHxCR_CH8SSEL_SPI2_RX ñÚ" P DMA_CHxCR_CH8SSEL_SPI3_TX îÚ% P DMA_CHxCR_CH8SSEL_LPUART0_TX ÿÚ# P DMA_CHxCR_CH8SSEL_UART0_TX Ú# P DMA_CHxCR_CH8SSEL_UART2_TX Ú# P DMA_CHxCR_CH8SSEL_UART4_TX Ú" P DMA_CHxCR_CH9SSEL_SPI0_RX òÚ" P DMA_CHxCR_CH9SSEL_SPI2_TX îÚ" P DMA_CHxCR_CH9SSEL_SPI4_RX îÚ% P DMA_CHxCR_CH9SSEL_LPUART1_RX ÿÚ# P DMA_CHxCR_CH9SSEL_UART1_RX Ú# P DMA_CHxCR_CH9SSEL_UART3_RX Ú# P DMA_CHxCR_CH9SSEL_UART5_RX Ú" P DMA_CHxCR_CH9SSEL_I2C0_TX Ú# P DMA_CHxCR_CH10SSEL_SPI0_TX ÆÚ# P DMA_CHxCR_CH10SSEL_SPI4_TX ÂÚ& P DMA_CHxCR_CH10SSEL_LPUART1_TX ÓÚ$ P DMA_CHxCR_CH10SSEL_UART1_TX sÚ$ P DMA_CHxCR_CH10SSEL_UART3_TX qÚ$ P DMA_CHxCR_CH10SSEL_UART5_TX oÚ# P DMA_CHxCR_CH10SSEL_I2C0_RX öÚ P DMA_CHxCR_CH10SSEL_CRC Ú P DMA_CHxCR_CIRC_UPD_Pos }Ú P DMA_CHxCR_CIRC_UPD_Msk Ú P DMA_CHxCR_DIR_Pos Ú P DMA_CHxCR_DIR_Msk Ú P DMA_CHxCR_DIR_TO_RAM [Ú P DMA_CHxCR_DIR_TO_PER TÚ P DMA_CHxCR_BDW_Pos Ú P DMA_CHxCR_BDW_Msk Ú P DMA_CHxCR_BDW_8BITS ×Ú P DMA_CHxCR_BDW_16BITS ¦Ú P DMA_CHxCR_BDW_32BITS ¨Ú P DMA_CHxCR_CIRC_Pos ÍÚ P DMA_CHxCR_CIRC_Msk ÔÚ P DMA_CHxCR_CHxFTIE_Pos ½Ú P DMA_CHxCR_CHxFTIE_Msk ÄÚ P DMA_CHxCR_CHxHTIE_Pos »Ú P DMA_CHxCR_CHxHTIE_Msk ÂÚ P DMA_CHxCR_ChxEN_Pos 6Ú P DMA_CHxCR_ChxEN_Msk =Ú P DMA_CHxMAR_CHxMEMAD_Pos 2Ú P DMA_CHxMAR_CHxMEMAD_Msk 9Ú! P DMA_CH11CR_CH11TSIZE_Pos |Ú! P DMA_CH11CR_CH11TSIZE_Msk Ú P DMA_CH11CR_CH11PRI_Pos $Ú P DMA_CH11CR_CH11PRI_Msk +Ú P DMA_CH11CR_CH11PRI_LOW dÚ" P DMA_CH11CR_CH11PRI_MEDIUM Ú P DMA_CH11CR_CH11PRI_HIGH 4Ú% P DMA_CH11CR_CH11PRI_VERY_HIGH
Ú P DMA_CH11CR_CH11DIR_Pos 0Ú P DMA_CH11CR_CH11DIR_Msk 7Ú" P DMA_CH11CR_CH11DIR_TO_RAM zÚ$ P DMA_CH11CR_CH11DIR_TO_FLASH èÚ P DMA_CH11CR_CH11RI_Pos vÚ P DMA_CH11CR_CH11RI_Msk }Ú# P DMA_CH11CR_CH11RI_INCREASE TÚ# P DMA_CH11CR_CH11RI_DECREASE bÚ P DMA_CH11CR_CH11FI_Pos Ú P DMA_CH11CR_CH11FI_Msk Ú# P DMA_CH11CR_CH11FI_INCREASE `Ú# P DMA_CH11CR_CH11FI_DECREASE nÚ P DMA_CH11CR_CH11FTIE_Pos åÚ P DMA_CH11CR_CH11FTIE_Msk ìÚ P DMA_CH11CR_CH11HTIE_Pos ãÚ P DMA_CH11CR_CH11HTIE_Msk êÚ P DMA_CH11CR_CH11EN_Pos ~Ú P DMA_CH11CR_CH11EN_Msk
Ú" P DMA_CH11FAR_CH11FLSAD_Pos [Ú" P DMA_CH11FAR_CH11FLSAD_Msk bÚ! P DMA_CH11RAR_CH7RAMAD_Pos Ú! P DMA_CH11RAR_CH7RAMAD_Msk Ú P DMA_ISR_DMA_ADDRERR_Pos YÚ P DMA_ISR_DMA_ADDRERR_Msk `Ú P DMA_ISR_DMACHFT_Pos Ú P DMA_ISR_DMACHFT_Msk ¦Ú P DMA_ISR_DMACHHT_Pos Ú P DMA_ISR_DMACHHT_Msk ¤Ú$ P DMA_CHxCSR_CHxTSIZE_SDW_Pos ªÚ$ P DMA_CHxCSR_CHxTSIZE_SDW_Msk ±Ú" P DMA_CHxCSR_CHxINC_SDW_Pos cÚ" P DMA_CHxCSR_CHxINC_SDW_Msk jÚ# P DMA_CHxMASR_CHxMAD_SDW_Pos Ú# P DMA_CHxMASR_CHxMAD_SDW_Msk %Ú DMA_Deinit FÚ ," NewState Ú' DMA_GCR_DMA_ADDRERR_EN_Setable úÚ' DMA_GCR_DMA_ADDRERR_EN_Getable Ú ," NewState Ú DMA_GCR_DMAEN_Setable ÎÚ DMA_GCR_DMAEN_Getable ÚÚ ," CHx ÁÚ ,
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SetValue ¦Ú DMA_CHxCR_CHxTSIZE_Set wÚ ," CHx ÁÚ DMA_CHxCR_CHxTSIZE_Get Ú ," CHx ÁÚ ,
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SetValue ¦Ú DMA_CHxCR_CHxPRI_Set Ú ," CHx ÁÚ DMA_CHxCR_CHxPRI_Get +Ú ," CHx ÁÚ ,
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SetValue ¦Ú DMA_CHxCR_CHxINC_Set 0Ú ," CHx ÁÚ DMA_CHxCR_CHxINC_Get <Ú ," CHx ÁÚ ,
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SetValue ¦Ú DMA_CHxCR_CHxSSEL_Set ÑÚ ," CHx ÁÚ DMA_CHxCR_CHxSSEL_Get ÝÚ ," CHx ÁÚ ," NewState Ú# DMA_CHxCR_CIRC_UPD_Setable Ú ," CHx ÁÚ# DMA_CHxCR_CIRC_UPD_Getable Ú ," CHx ÁÚ ,
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SetValue ¦Ú DMA_CHxCR_DIR_Set 4Ú ," CHx ÁÚ DMA_CHxCR_DIR_Get @Ú ," CHx ÁÚ ,
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SetValue ¦Ú DMA_CHxCR_BDW_Set 6Ú ," CHx ÁÚ DMA_CHxCR_BDW_Get BÚ ," CHx ÁÚ ," NewState Ú DMA_CHxCR_CIRC_Setable TÚ ," CHx ÁÚ DMA_CHxCR_CIRC_Getable `Ú ," CHx ÁÚ ," NewState Ú" DMA_CHxCR_CHxFTIE_Setable DÚ ," CHx ÁÚ" DMA_CHxCR_CHxFTIE_Getable PÚ ," CHx ÁÚ ," NewState Ú" DMA_CHxCR_CHxHTIE_Setable BÚ ," CHx ÁÚ" DMA_CHxCR_CHxHTIE_Getable NÚ ," CHx ÁÚ ," NewState Ú DMA_CHxCR_ChxEN_Setable ½Ú ," CHx ÁÚ DMA_CHxCR_ChxEN_Getable ÉÚ ," CHx ÁÚ ,
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SetValue ¦Ú DMA_CHxMAR_Write JÚ ," CHx ÁÚ DMA_CHxMAR_Read ÛÚ ,
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SetValue ¦Ú! DMA_CH11CR_CH11TSIZE_Set Ú! DMA_CH11CR_CH11TSIZE_Get «Ú ,
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SetValue ¦Ú DMA_CH11CR_CH11PRI_Set GÚ DMA_CH11CR_CH11PRI_Get SÚ ,
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SetValue ¦Ú DMA_CH11CR_CH11DIR_Set SÚ DMA_CH11CR_CH11DIR_Get _Ú ,
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SetValue ¦Ú DMA_CH11CR_CH11RI_Set Ú DMA_CH11CR_CH11RI_Get ¥Ú ,
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SetValue ¦Ú DMA_CH11CR_CH11FI_Set ¥Ú DMA_CH11CR_CH11FI_Get ±Ú ," NewState Ú$ DMA_CH11CR_CH11FTIE_Setable lÚ$ DMA_CH11CR_CH11FTIE_Getable xÚ ," NewState Ú$ DMA_CH11CR_CH11HTIE_Setable jÚ$ DMA_CH11CR_CH11HTIE_Getable vÚ ," NewState Ú" DMA_CH11CR_CH11EN_Setable Ú" DMA_CH11CR_CH11EN_Getable Ú ,
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SetValue ¦Ú DMA_CH11FAR_Write eÚ DMA_CH11FAR_Read öÚ ,
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SetValue ¦Ú DMA_CH11RAR_Write YÚ DMA_CH11RAR_Read êÚ DMA_ISR_DMA_ADDRERR_Clr Ú DMA_ISR_DMA_ADDRERR_Chk Ú ," CHx ÁÚ DMA_ISR_DMACHFT_Clr ÍÚ ," CHx ÁÚ DMA_ISR_DMACHFT_Chk ØÚ ," CHx ÁÚ DMA_ISR_DMACHHT_Clr ËÚ ," CHx ÁÚ DMA_ISR_DMACHHT_Chk ÖÚ ," CHx ÁÚ ,
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SetValue ¦Ú$ DMA_CHxCSR_CHxTSIZE_SDW_Set ÍÚ ," CHx ÁÚ$ DMA_CHxCSR_CHxTSIZE_SDW_Get ÙÚ ," CHx ÁÚ ,
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SetValue ¦Ú" DMA_CHxCSR_CHxINC_SDW_Set Ú ," CHx ÁÚ" DMA_CHxCSR_CHxINC_SDW_Get Ú ," CHx ÁÚ ,
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SetValue ¦Ú DMA_CHxMASR_Write õÚ ," CHx ÁÚ DMA_CHxMASR_Read Ú DMA_DeInit fÚ , para %Ú DMA_Init Ú P __FM33A0XXEV_GPIO_H ýÚ GPIO_FCR_IN Ú GPIO_FCR_OUT %Ú GPIO_FCR_DIG IÚ GPIO_FCR_ANA MÚ GPIO_FCR_TypeDef hÚ GPIO_OD_Dis GÚ GPIO_OD_En ¶Ú GPIO_ODEN_TypeDef Ú GPIO_PU_Dis 5Ú GPIO_PU_En ¤Ú GPIO_PUEN_TypeDef Ú GPIO_IN_Dis CÚ GPIO_IN_En ²Ú GPIO_INEN_TypeDef Ú GPIO_HD_Dis NÚ GPIO_HD_En ½Ú GPIO_HD_TypeDef ¹Ú GPIO_ANEN_Dis ´Ú GPIO_ANEN_En #Ú GPIO_ANEN_TypeDef Ú 8
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<unnamed> QÚ
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" ÎPin ¹Ú "" ÎPxFCR $Ú "" ÎPxODEN ×Ú "" ÎPxPUEN ÅÚ "" ÎPxINEN ÓÚ GPIO_InitTypeDef Ú
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Bit_RESET êÚ Bit_SET
Ú
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BitAction rÚ P IS_GPIO_BIT_ACTION "Ú EXTI_RISING Ú EXTI_FALLING OÚ
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EXTI_BOTH %Ú EXTIDISABLE ¹Ú GPIOExtiEdge «Ú& P IS_GPIO_INTERRUPT_TRIGER_EDGE Ú P IS_GPIO_ALL_PERIPH Ú P IS_GPIO_HD_PERIPH mÚ P GPIO_Pin_0 sÚ P GPIO_Pin_1 rÚ P GPIO_Pin_2 qÚ P GPIO_Pin_3 pÚ P GPIO_Pin_4 oÚ P GPIO_Pin_5 nÚ P GPIO_Pin_6 mÚ P GPIO_Pin_7 lÚ P GPIO_Pin_8 kÚ P GPIO_Pin_9 jÚ P GPIO_Pin_10 @Ú P GPIO_Pin_11 ?Ú P GPIO_Pin_12 >Ú P GPIO_Pin_13 =Ú P GPIO_Pin_14 <Ú P GPIO_Pin_15 ;Ú P GPIO_Pin_All Ú P IS_GPIO_PIN EÚ P IS_GET_GPIO_PIN þÚ P IS_GET_GPIOH_PIN ´Ú P PINWKEN_PD6 pÚ P PINWKEN_PE9 lÚ P PINWKEN_PE2 sÚ P PINWKEN_PA13 CÚ P PINWKEN_PG7 lÚ P PINWKEN_PC13 AÚ P PINWKEN_PB0 xÚ P PINWKEN_PF5 oÚ P GPIOx_INEN_INEN_Pos [Ú P GPIOx_INEN_INEN_Msk bÚ P GPIOx_PUEN_PUEN_Pos ?Ú P GPIOx_PUEN_PUEN_Msk FÚ P GPIOx_ODEN_ODEN_Pos cÚ P GPIOx_ODEN_ODEN_Msk jÚ P GPIOx_FCR_Px15FCR_Pos ÇÚ P GPIOx_FCR_Px15FCR_Msk ÎÚ P GPIOx_FCR_Px14FCR_Pos ÈÚ P GPIOx_FCR_Px14FCR_Msk ÏÚ P GPIOx_FCR_Px13FCR_Pos ÉÚ P GPIOx_FCR_Px13FCR_Msk ÐÚ P GPIOx_FCR_Px12FCR_Pos ÊÚ P GPIOx_FCR_Px12FCR_Msk ÑÚ P GPIOx_FCR_Px11FCR_Pos ËÚ P GPIOx_FCR_Px11FCR_Msk ÒÚ P GPIOx_FCR_Px10FCR_Pos ÌÚ P GPIOx_FCR_Px10FCR_Msk ÓÚ P GPIOx_FCR_Px9FCR_Pos öÚ P GPIOx_FCR_Px9FCR_Msk ýÚ P GPIOx_FCR_Px8FCR_Pos ÷Ú P GPIOx_FCR_Px8FCR_Msk þÚ P GPIOx_FCR_Px7FCR_Pos øÚ P GPIOx_FCR_Px7FCR_Msk ÿÚ P GPIOx_FCR_Px6FCR_Pos ùÚ P GPIOx_FCR_Px6FCR_Msk Ú P GPIOx_FCR_Px5FCR_Pos úÚ P GPIOx_FCR_Px5FCR_Msk Ú P GPIOx_FCR_Px4FCR_Pos ûÚ P GPIOx_FCR_Px4FCR_Msk Ú P GPIOx_FCR_Px3FCR_Pos üÚ P GPIOx_FCR_Px3FCR_Msk Ú P GPIOx_FCR_Px2FCR_Pos ýÚ P GPIOx_FCR_Px2FCR_Msk Ú P GPIOx_FCR_Px1FCR_Pos þÚ P GPIOx_FCR_Px1FCR_Msk Ú P GPIOx_FCR_Px0FCR_Pos ÿÚ P GPIOx_FCR_Px0FCR_Msk Ú P GPIOx_DO_DO_Pos Ú P GPIOx_DO_DO_Msk Ú P GPIOx_DSET_DSET_Pos OÚ P GPIOx_DSET_DSET_Msk VÚ P GPIOx_DRST_DRESET_Pos §Ú P GPIOx_DRST_DRESET_Msk ®Ú P GPIOx_DIN_DIN_Pos ýÚ P GPIOx_DIN_DIN_Msk Ú P GPIOx_DFS_DFS_Pos ùÚ P GPIOx_DFS_DFS_Msk Ú P GPIOx_ANEN_ANEN_Pos kÚ P GPIOx_ANEN_ANEN_Msk rÚ" P GPIO_FOUTSEL_FOUT1SEL_Pos ¦Ú" P GPIO_FOUTSEL_FOUT1SEL_Msk Ú# P GPIO_FOUTSEL_FOUT1SEL_XTLF Ú# P GPIO_FOUTSEL_FOUT1SEL_RCLP ¥Ú& P GPIO_FOUTSEL_FOUT1SEL_RCHFD64 ÿÚ$ P GPIO_FOUTSEL_FOUT1SEL_LSCLK [Ú( P GPIO_FOUTSEL_FOUT1SEL_AHBCLKD64 yÚ% P GPIO_FOUTSEL_FOUT1SEL_RTC_TM éÚ& P GPIO_FOUTSEL_FOUT1SEL_PLLHD64 òÚ) P !GPIO_FOUTSEL_FOUT1SEL_RTCCLK64Hz ÛÚ( P GPIO_FOUTSEL_FOUT1SEL_APBCLKD64 qÚ$ P GPIO_FOUTSEL_FOUT1SEL_PLL_L AÚ# P GPIO_FOUTSEL_FOUT1SEL_RCMF ®Ú# P GPIO_FOUTSEL_FOUT1SEL_RCHF ³Ú& P GPIO_FOUTSEL_FOUT1SEL_XTHFD64 èÚ% P GPIO_FOUTSEL_FOUT1SEL_ADCCLK 0Ú$ P GPIO_FOUTSEL_FOUT1SEL_PLL_H EÚ) P !GPIO_FOUTSEL_FOUT1SEL_BOOST_FLAG ÊÚ. P &GPIO_FOUTSEL_FOUT1SEL_AUTOTRIM_OUTPUT ûÚ" P GPIO_FOUTSEL_FOUT0SEL_Pos §Ú" P GPIO_FOUTSEL_FOUT0SEL_Msk ®Ú# P GPIO_FOUTSEL_FOUT0SEL_XTLF Ú# P GPIO_FOUTSEL_FOUT0SEL_RCLP ¦Ú& P GPIO_FOUTSEL_FOUT0SEL_RCHFD64 Ú$ P GPIO_FOUTSEL_FOUT0SEL_LSCLK \Ú( P GPIO_FOUTSEL_FOUT0SEL_AHBCLKD64 zÚ% P GPIO_FOUTSEL_FOUT0SEL_RTC_TM êÚ& P GPIO_FOUTSEL_FOUT0SEL_PLLHD64 óÚ) P !GPIO_FOUTSEL_FOUT0SEL_RTCCLK64Hz ÜÚ( P GPIO_FOUTSEL_FOUT0SEL_APBCLKD64 rÚ$ P GPIO_FOUTSEL_FOUT0SEL_PLL_L BÚ# P GPIO_FOUTSEL_FOUT0SEL_RCMF ¯Ú# P GPIO_FOUTSEL_FOUT0SEL_RCHF ´Ú& P GPIO_FOUTSEL_FOUT0SEL_XTHFD64 éÚ% P GPIO_FOUTSEL_FOUT0SEL_ADCCLK 1Ú$ P GPIO_FOUTSEL_FOUT0SEL_PLL_H FÚ) P !GPIO_FOUTSEL_FOUT0SEL_BOOST_FLAG ËÚ P GPIO_IOMCR_IOMUXSEL_Pos /Ú P GPIO_IOMCR_IOMUXSEL_Msk 6Ú P GPIO_IOMCR_IOMUXSEL_PD6 Ú P GPIO_IOMCR_IOMUXSEL_PD7 Ú P GPIO_IOMCR_IOMUXSEL_PG2 Ú P GPIO_IOMCR_IOMUXSEL_PG3 Ú P GPIO_IOMCR_IOMUXEN_Pos Ú P GPIO_IOMCR_IOMCUEN_Msk Ú P GPIO_PINWKEN_WKISEL_Pos 4Ú P GPIO_PINWKEN_WKISEL_Msk ;Ú P GPIO_PINWKEN_WKISEL_NMI Ú P GPIO_PINWKEN_WKISEL_46 þÚ" P GPIO_PINWKEN_PINWKSEL_Pos Ú" P GPIO_PINWKEN_PINWKSEL_Msk Ú& P GPIO_PINWKEN_PINWKSEL_FALLING ¿Ú% P GPIO_PINWKEN_PINWKSEL_RISING òÚ# P GPIO_PINWKEN_PINWKSEL_BOTH Ú! P GPIO_PINWKEN_PINWKEN_Pos åÚ! P GPIO_PINWKEN_PINWKEN_Msk ìÚ P GPIOH_DO_PHDO_Pos %Ú P GPIOH_DO_PHDO_Msk ,Ú P GPIOH_DIN_PHDIN_Pos Ú P GPIOH_DIN_PHDIN_Msk Ú , GPIOx Ú ,
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SetValue ¦Ú GPIOx_DO_Write ÉÚ , GPIOx Ú GPIOx_DO_Read ZÚ , GPIOx Ú ,
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SetValue ¦Ú GPIOx_DSET_Write (Ú , GPIOx Ú ,
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SetValue ¦Ú GPIOx_DRST_Write Ú , GPIOx Ú GPIOx_DIN_Read Ú , GPIOx Ú ,
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GPIO_Pin Ú ," NewState Ú GPIOx_DFS_Setable ÄÚ , GPIOx Ú ,
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GPIO_Pin Ú GPIOx_DFS_Getable ÐÚ , GPIOx Ú ,
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GPIO_Pin Ú ," NewState Ú GPIOx_ANEN_Setable }Ú , GPIOx Ú ,
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GPIO_Pin Ú GPIOx_ANEN_Getable Ú , GPIOx Ú , para %Ú
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GPIO_Init ´Ú , GPIOx Ú ,
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GPIO_Pin Ú , para %Ú GPIO_Get_InitPara ¡Ú , GPIOx Ú GPIO_ReadInputData 0Ú , GPIOx Ú ,
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GPIO_Pin Ú GPIO_ReadInputDataBit Ú , GPIOx Ú ,
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GPIO_Pin Ú GPIO_SetBits Ú , GPIOx Ú ,
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GPIO_Pin Ú GPIO_ResetBits ©Ú , GPIOx Ú ,
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GPIO_Pin Ú GPIO_ToggleBits HÚ ,
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GPIO_Pin Ú GPIOH_SetBits :Ú ,
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GPIO_Pin Ú GPIOH_ResetBits _Ú ,
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GPIO_Pin Ú GPIOH_ToggleBits þÚ , GPIOx Ú GPIO_ReadOutputData Ú , GPIOx Ú ,
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GPIO_Pin Ú GPIO_ReadOutputDataBit Ú , GPIOx Ú ,
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GPIO_Pin Ú GPIO_EXTI_Select_Pin ³Ú , GPIOx Ú ,
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GPIO_Pin Ú ," edge_select @Ú GPIO_EXTI_Select_Edge cÚ , GPIOx Ú ,
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GPIO_Pin Ú ," NewState Ú! GPIO_EXTI_EXTIDF_Setable ®Ú , GPIOx Ú ,
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GPIO_Pin Ú! GPIO_EXTI_EXTIDI_Getable ·Ú , GPIOx Ú ,
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GPIO_Pin Ú GPIO_EXTI_EXTIISR_ClrEx .Ú , GPIOx Ú ,
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GPIO_Pin Ú GPIO_EXTI_EXTIISR_ChkEx 9Ú ,
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SetValue ¦Ú" GPIO_FOUTSEL_FOUT1SEL_Set ÉÚ" GPIO_FOUTSEL_FOUT1SEL_Get ÕÚ ,
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SetValue ¦Ú" GPIO_FOUTSEL_FOUT0SEL_Set ÊÚ" GPIO_FOUTSEL_FOUT0SEL_Get ÖÚ , GPIOx Ú ,
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GPIO_Pin Ú ," edge_select @Ú ," DFState 1Ú GPIO_EXTI_Init Ú , GPIOx Ú ,
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GPIO_Pin Ú GPIO_EXTI_Close Ú , para %Ú GPIOH_Init jÚ ,
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GPIO_Pin Ú , para %Ú GPIOH_Get_InitPara WÚ ,
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SetValue ¦Ú GPIOH_DO_Write ùÚ GPIOH_ReadOutputData cÚ ,
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GPIO_Pin Ú GPIOH_ReadOutputDataBit >Ú GPIOH_ReadInputData æÚ ,
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GPIO_Pin Ú GPIOH_ReadInputDataBit ÁÚ ,
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SetValue ¦Ú GPIO_IOMCR_IOMUXSEL_Set RÚ GPIO_IOMCR_IOMUXSEL_Get ^Ú ," NewState Ú GPIO_IOMCR_Setable Ú GPIO_IOMCR_Getable ©Ú ,
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NWKPinDef §Ú ," NewState Ú GPIO_PINWKEN_SetableEx 6Ú ,
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NWKPinDef §Ú GPIO_PINWKEN_GetableEx BÚ ,
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NWKPinDef §Ú ,
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SetValue ¦Ú GPIO_PINWKSEL_SetEx Ú ,
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NWKPinDef §Ú GPIO_PINWKSEL_GetEx Ú ,
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SetValue ¦Ú GPIO_PINWKEN_WKISEL_Set WÚ GPIO_PINWKEN_WKISEL_Get cÚ P __FM33A0XXEV_I2C_H pÚ P I2C_SEND_STARTBIT Ú P I2C_SEND_RESTARTBIT ûÚ P I2C_SEND_STOPBIT àÚ P I2C_SEND_ACK_0 «Ú P I2C_SEND_ACK_1 ªÚ P I2Cx_CFGR_AUTOEND_Pos êÚ P I2Cx_CFGR_AUTOEND_Msk ñÚ P I2Cx_CFGR_AUTOEND_AUTO áÚ! P I2Cx_CFGR_AUTOEND_MANUAL XÚ P I2Cx_CFGR_MSP_DMAEN_Pos BÚ P I2Cx_CFGR_MSP_DMAEN_Msk IÚ P I2Cx_CFGR_TOEN_Pos ÊÚ P I2Cx_CFGR_TOEN_Msk ÑÚ P I2Cx_CFGR_TOEN_ENABLE OÚ P I2Cx_CFGR_TOEN_DISABLE Ú P I2Cx_CFGR_MSPEN_Pos {Ú P I2Cx_CFGR_MSPEN_Msk Ú P I2Cx_CR_RCEN_Pos iÚ P I2Cx_CR_RCEN_Msk pÚ P I2Cx_CR_PEN_Pos °Ú P I2Cx_CR_PEN_Msk ·Ú P I2Cx_CR_RSEN_Pos YÚ P I2Cx_CR_RSEN_Msk `Ú P I2Cx_CR_SEN_Pos Ú P I2Cx_CR_SEN_Msk ´Ú P I2Cx_IER_WCOLE_Pos ÈÚ P I2Cx_IER_WCOLE_Msk ÏÚ P I2Cx_IER_TOE_Pos ^Ú P I2Cx_IER_TOE_Msk eÚ P I2Cx_IER_SE_Pos °Ú P I2Cx_IER_SE_Msk ·Ú P I2Cx_IER_PE_Pos ³Ú P I2Cx_IER_PE_Msk ºÚ P I2Cx_IER_NACKE_Pos àÚ P I2Cx_IER_NACKE_Msk çÚ P I2Cx_IER_TXIE_Pos
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Ú P I2Cx_IER_TXIE_Msk Ú P I2Cx_IER_RXIE_Pos Ú P I2Cx_IER_RXIE_Msk Ú P I2Cx_ISR_WCOL_Pos Ú P I2Cx_ISR_WCOL_Msk Ú P I2Cx_ISR_TO_Pos Ú P I2Cx_ISR_TO_Msk Ú P I2Cx_ISR_S_Pos éÚ P I2Cx_ISR_S_Msk ðÚ P I2Cx_ISR_P_Pos ìÚ P I2Cx_ISR_P_Msk óÚ P I2Cx_ISR_ACKSTA_Pos {Ú P I2Cx_ISR_ACKSTA_Msk Ú P I2Cx_ISR_TXIF_Pos ûÚ P I2Cx_ISR_TXIF_Msk Ú P I2Cx_ISR_RXIF_Pos ýÚ P I2Cx_ISR_RXIF_Msk Ú P I2Cx_SR_BUSY_Pos >Ú P I2Cx_SR_BUSY_Msk EÚ P I2Cx_SR_RW_Pos ÜÚ P I2Cx_SR_RW_Msk ãÚ P I2Cx_SR_BF_Pos ýÚ P I2Cx_SR_BF_Msk Ú P I2Cx_SR_ACKMO_Pos Ú P I2Cx_SR_ACKMO_Msk Ú P I2Cx_SR_ACKMO_RESET ¿Ú P I2Cx_SR_ACKMO_SET ZÚ P I2Cx_BRG_MSPBRGH_Pos 0Ú P I2Cx_BRG_MSPBRGH_Msk 7Ú P I2Cx_BRG_MSPBRGL_Pos ,Ú P I2Cx_BRG_MSPBRGL_Msk 3Ú P I2Cx_BUF_WR_Pos ¢Ú P I2Cx_BUF_WR_Msk ©Ú P I2Cx_TIMING_SDAHD_Pos ðÚ P I2Cx_TIMING_SDAHD_Msk ÷Ú P I2Cx_TO_TIMEOUT_Pos VÚ P I2Cx_TO_TIMEOUT_Msk ]Ú , I2Cx Ú I2Cx_Deinit àÚ , I2Cx Ú ,
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SetValue ¦Ú I2Cx_CFGR_AUTOEND_Set Ú , I2Cx Ú I2Cx_CFGR_AUTOEND_Get Ú , I2Cx Ú ," NewState Ú$ I2Cx_CFGR_MSP_DMAEN_Setable ÉÚ , I2Cx Ú$ I2Cx_CFGR_MSP_DMAEN_Getable ÕÚ , I2Cx Ú ," NewState Ú I2Cx_CFGR_TOEN_Setable QÚ , I2Cx Ú I2Cx_CFGR_TOEN_Getable ]Ú , I2Cx Ú ," NewState Ú I2Cx_CFGR_MSPEN_Setable Ú , I2Cx Ú I2Cx_CFGR_MSPEN_Getable Ú , I2Cx Ú ," NewState Ú I2Cx_CR_RCEN_Setable ðÚ , I2Cx Ú I2Cx_CR_RCEN_Getable üÚ , I2Cx Ú ," NewState Ú I2Cx_CR_PEN_Setable 7Ú , I2Cx Ú I2Cx_CR_PEN_Getable CÚ , I2Cx Ú ," NewState Ú I2Cx_CR_RSEN_Setable àÚ , I2Cx Ú I2Cx_CR_RSEN_Getable ìÚ , I2Cx Ú ," NewState Ú I2Cx_CR_SEN_Setable 4Ú , I2Cx Ú I2Cx_CR_SEN_Getable @Ú , I2Cx Ú ," NewState Ú I2Cx_IER_WCOLE_Setable OÚ , I2Cx Ú I2Cx_IER_WCOLE_Getable [Ú , I2Cx Ú ," NewState Ú I2Cx_IER_TOE_Setable åÚ , I2Cx Ú I2Cx_IER_TOE_Getable ñÚ , I2Cx Ú ," NewState Ú I2Cx_IER_SE_Setable 7Ú , I2Cx Ú I2Cx_IER_SE_Getable CÚ , I2Cx Ú ," NewState Ú I2Cx_IER_PE_Setable :Ú , I2Cx Ú I2Cx_IER_PE_Getable FÚ , I2Cx Ú ," NewState Ú I2Cx_IER_NACKE_Setable gÚ , I2Cx Ú I2Cx_IER_NACKE_Getable sÚ , I2Cx Ú ," NewState Ú I2Cx_IER_TXIE_Setable Ú , I2Cx Ú I2Cx_IER_TXIE_Getable Ú , I2Cx Ú ," NewState Ú I2Cx_IER_RXIE_Setable Ú , I2Cx Ú I2Cx_IER_RXIE_Getable Ú , I2Cx Ú I2Cx_ISR_WCOL_Clr /Ú , I2Cx Ú I2Cx_ISR_WCOL_Chk :Ú , I2Cx Ú I2Cx_ISR_OVT_Clr mÚ , I2Cx Ú I2Cx_ISR_OVT_Chk xÚ , I2Cx Ú I2Cx_ISR_S_Chk "Ú , I2Cx Ú I2Cx_ISR_P_Chk %Ú , I2Cx Ú I2Cx_ISR_ACKSTA_Clr ©Ú , I2Cx Ú I2Cx_ISR_ACKSTA_Chk ´Ú , I2Cx Ú I2Cx_ISR_TXIF_Clr )Ú , I2Cx Ú I2Cx_ISR_TXIF_Chk 4Ú , I2Cx Ú I2Cx_ISR_RXIF_Clr +Ú , I2Cx Ú I2Cx_ISR_RXIF_Chk 6Ú , I2Cx Ú I2Cx_SR_BUSY_Chk wÚ , I2Cx Ú I2Cx_SR_RW_Chk Ú , I2Cx Ú I2Cx_SR_BF_Chk 6Ú , I2Cx Ú ,
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SetValue ¦Ú I2Cx_SR_ACKMO_Set 7Ú , I2Cx Ú I2Cx_SR_ACKMO_Get CÚ , I2Cx Ú ,
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SetValue ¦Ú I2Cx_BRG_MSPBRGH_Set SÚ , I2Cx Ú I2Cx_BRG_MSPBRGH_Get _Ú , I2Cx Ú ,
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SetValue ¦Ú I2Cx_BRG_MSPBRGL_Set OÚ , I2Cx Ú I2Cx_BRG_MSPBRGL_Get [Ú , I2Cx Ú ,
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SetValue ¦Ú I2Cx_BUF_Write ðÚ , I2Cx Ú I2Cx_BUF_Read Ú , I2Cx Ú ,
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SetValue ¦Ú I2Cx_TIMING_Write ÿÚ , I2Cx Ú I2Cx_TIMING_Read Ú , I2Cx Ú ,
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SetValue ¦Ú I2Cx_TO_Write ,Ú , I2Cx Ú I2Cx_TO_Read ½Ú , I2Cx Ú ,
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I2CClk ûÚ ,
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APBClk æÚ I2C_BaudREG_Calc Ú P __FM33A0XXEV_IWDT_H ôÚ P IWDT_SERV_IWDTSERV_KEY ©Ú P IWDT_SERV_IWDTSERV_Pos `Ú P IWDT_SERV_IWDTSERV_Msk gÚ P IWDT_CFGR_IWDTOVP_Pos ËÚ P IWDT_CFGR_IWDTOVP_Msk ÒÚ P IWDT_IWDTOVP_125MS LÚ P IWDT_IWDTOVP_500MS OÚ P IWDT_IWDTOVP_2S Ú P IWDT_IWDTOVP_8S ÿÚ P IWDT_IWDTOVP_4096S ^Ú P IWDT_CNTR_IWDTCNT_Pos ÆÚ P IWDT_CNTR_IWDTCNT_Msk ÍÚ IWDT_Deinit ÞÚ ,
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SetValue ¦Ú IWDT_SERV_IWDTSERV_Set Ú ,
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SetValue ¦Ú IWDT_CFGR_Write §Ú IWDT_CFGR_Read 8Ú IWDT_CNTR_IWDTCNT_Get õÚ P __FM33A0XXEV_LPUART_H PÚ P LPUARTx_MCTL_FOR9600 ¯Ú P LPUARTx_MCTL_FOR4800 ²Ú P LPUARTx_MCTL_FOR2400 ¸Ú P LPUARTx_MCTL_FOR1200 »Ú P LPUARTx_MCTL_FOR600 êÚ P LPUARTx_MCTL_FOR300 íÚ P LPUARTx_CSR_BUSY_Pos ÙÚ P LPUARTx_CSR_BUSY_Msk àÚ" P LPUARTx_CSR_WKBYTECFG_Pos lÚ" P LPUARTx_CSR_WKBYTECFG_Msk sÚ P LPUARTx_CSR_RXEV_Pos ×Ú P LPUARTx_CSR_RXEV_Msk ÞÚ P LPUARTx_CSR_RXEV_START wÚ P LPUARTx_CSR_RXEV_1BYTE Ú P LPUARTx_CSR_RXEV_MATCH Ú! P LPUARTx_CSR_RXEV_FALLING Ú P LPUARTx_CSR_IOSWAP_Pos EÚ P LPUARTx_CSR_IOSWAP_Msk LÚ# P LPUARTx_CSR_IOSWAP_DEFUALT jÚ P LPUARTx_CSR_IOSWAP_SWAP :Ú# P LPUARTx_CSR_DMATXIFCFG_Pos 3Ú# P LPUARTx_CSR_DMATXIFCFG_Msk :Ú P LPUARTx_CSR_BITORD_Pos TÚ P LPUARTx_CSR_BITORD_Msk [Ú P LPUARTx_CSR_BITORD_LSB ¥Ú P LPUARTx_CSR_BITORD_MSB ¤Ú P LPUARTx_CSR_STOPCFG_Pos Ú P LPUARTx_CSR_STOPCFG_Msk Ú" P LPUARTx_CSR_STOPCFG_1STOP ·Ú" P LPUARTx_CSR_STOPCFG_2STOP ¶Ú P LPUARTx_CSR_PDSEL_Pos ¢Ú P LPUARTx_CSR_PDSEL_Msk ©Ú P LPUARTx_CSR_PDSEL_7BITS gÚ P LPUARTx_CSR_PDSEL_8BITS fÚ P LPUARTx_CSR_PDSEL_9BITS eÚ P LPUARTx_CSR_PDSEL_6BITS hÚ P LPUARTx_CSR_PARITY_Pos ?Ú P LPUARTx_CSR_PARITY_Msk FÚ P LPUARTx_CSR_PARITY_NON Ú P LPUARTx_CSR_PARITY_EVEN AÚ P LPUARTx_CSR_PARITY_ODD Ú P LPUARTx_CSR_RXPOL_Pos
Ú P LPUARTx_CSR_RXPOL_Msk Ú P LPUARTx_CSR_RXPOL_POS ÅÚ P LPUARTx_CSR_RXPOL_NEG ÝÚ P LPUARTx_CSR_TXPOL_Pos Ú P LPUARTx_CSR_TXPOL_Msk Ú P LPUARTx_CSR_TXPOL_POS ÃÚ P LPUARTx_CSR_TXPOL_NEG ÛÚ P LPUARTx_CSR_RXEN_Pos ßÚ P LPUARTx_CSR_RXEN_Msk æÚ P LPUARTx_CSR_TXEN_Pos ÝÚ P LPUARTx_CSR_TXEN_Msk äÚ P LPUARTx_IER_RXEV_IE_Pos ìÚ P LPUARTx_IER_RXEV_IE_Msk óÚ! P LPUARTx_IER_RXERR_IE_Pos Ú! P LPUARTx_IER_RXERR_IE_Msk £Ú P LPUARTx_IER_RXBF_IE_Pos ÿÚ P LPUARTx_IER_RXBF_IE_Msk Ú P LPUARTx_IER_TXBE_IE_Pos þÚ P LPUARTx_IER_TXBE_IE_Msk Ú P LPUARTx_IER_TXSE_IE_Pos íÚ P LPUARTx_IER_TXSE_IE_Msk ôÚ P LPUARTx_ISR_RXEVF_Pos Ú P LPUARTx_ISR_RXEVF_Msk Ú P LPUARTx_ISR_TXOV_Pos ÅÚ P LPUARTx_ISR_TXOV_Msk ÌÚ P LPUARTx_ISR_PERR_Pos ÝÚ P LPUARTx_ISR_PERR_Msk äÚ P LPUARTx_ISR_FERR_Pos çÚ P LPUARTx_ISR_FERR_Msk îÚ P LPUARTx_ISR_OERR_Pos ÞÚ P LPUARTx_ISR_OERR_Msk åÚ P LPUARTx_ISR_RXBF_Pos äÚ P LPUARTx_ISR_RXBF_Msk ëÚ P LPUARTx_ISR_TXBE_Pos ãÚ P LPUARTx_ISR_TXBE_Msk êÚ P LPUARTx_ISR_TXSE_Pos ÒÚ P LPUARTx_ISR_TXSE_Msk ÙÚ P LPUARTx_BMR_MCTL_Pos óÚ P LPUARTx_BMR_MCTL_Msk úÚ P LPUARTx_BMR_BAUD_Pos Ú P LPUARTx_BMR_BAUD_Msk Ú P LPUARTx_BMR_BAUD_9600 hÚ P LPUARTx_BMR_BAUD_4800 kÚ P LPUARTx_BMR_BAUD_2400 qÚ P LPUARTx_BMR_BAUD_1200 tÚ P LPUARTx_BMR_BAUD_600 £Ú P LPUARTx_BMR_BAUD_300 ¦Ú P LPUARTx_RXBUF_RXBUF_Pos ðÚ P LPUARTx_RXBUF_RXBUF_Msk ÷Ú P LPUARTx_TXBUF_TXBUF_Pos ìÚ P LPUARTx_TXBUF_TXBUF_Msk óÚ P LPUARTx_DMR_MATD_Pos ûÚ P LPUARTx_DMR_MATD_Msk Ú , LPUARTx sÚ LPUARTx_Deinit ÀÚ , LPUARTx sÚ LPUARTx_CSR_BUSY_Chk Ú , LPUARTx sÚ ," NewState Ú& LPUARTx_CSR_WKBYTECFG_Setable óÚ , LPUARTx sÚ" LPUARTx_CSR_WKBYTECFG_Chk ¥Ú , LPUARTx sÚ ,
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SetValue ¦Ú LPUARTx_CSR_RXEV_Set úÚ , LPUARTx sÚ LPUARTx_CSR_RXEV_Get Ú , LPUARTx sÚ ,
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SetValue ¦Ú LPUARTx_CSR_IOSWAP_Set hÚ , LPUARTx sÚ LPUARTx_CSR_IOSWAP_Get tÚ , LPUARTx sÚ ," NewState Ú' LPUARTx_CSR_DMATXIFCFG_Setable ºÚ , LPUARTx sÚ' LPUARTx_CSR_DMATXIFCFG_Getable ÆÚ , LPUARTx sÚ ,
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SetValue ¦Ú LPUARTx_CSR_BITORD_Set wÚ , LPUARTx sÚ LPUARTx_CSR_BITORD_Get Ú , LPUARTx sÚ ,
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SetValue ¦Ú LPUARTx_CSR_STOPCFG_Set #Ú , LPUARTx sÚ LPUARTx_CSR_STOPCFG_Get /Ú , LPUARTx sÚ ,
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SetValue ¦Ú LPUARTx_CSR_PDSEL_Set ÅÚ , LPUARTx sÚ LPUARTx_CSR_PDSEL_Get ÑÚ , LPUARTx sÚ ,
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SetValue ¦Ú LPUARTx_CSR_PARITY_Set bÚ , LPUARTx sÚ LPUARTx_CSR_PARITY_Get nÚ , LPUARTx sÚ ,
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SetValue ¦Ú LPUARTx_CSR_RXPOL_Set ¨Ú , LPUARTx sÚ LPUARTx_CSR_RXPOL_Get ´Ú , LPUARTx sÚ ,
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SetValue ¦Ú LPUARTx_CSR_TXPOL_Set ¦Ú , LPUARTx sÚ LPUARTx_CSR_TXPOL_Get ²Ú , LPUARTx sÚ ," NewState Ú! LPUARTx_CSR_RXEN_Setable fÚ , LPUARTx sÚ! LPUARTx_CSR_RXEN_Getable rÚ , LPUARTx sÚ ," NewState Ú! LPUARTx_CSR_TXEN_Setable dÚ , LPUARTx sÚ! LPUARTx_CSR_TXEN_Getable pÚ , LPUARTx sÚ ," NewState Ú$ LPUARTx_IER_RXEV_IE_Setable sÚ , LPUARTx sÚ$ LPUARTx_IER_RXEV_IE_Getable Ú , LPUARTx sÚ ," NewState Ú% LPUARTx_IER_RXERR_IE_Setable #Ú , LPUARTx sÚ% LPUARTx_IER_RXERR_IE_Getable /Ú , LPUARTx sÚ ," NewState Ú$ LPUARTx_IER_RXBF_IE_Setable Ú , LPUARTx sÚ$ LPUARTx_IER_RXBF_IE_Getable Ú , LPUARTx sÚ ," NewState Ú$ LPUARTx_IER_TXBE_IE_Setable
Ú , LPUARTx sÚ$ LPUARTx_IER_TXBE_IE_Getable Ú , LPUARTx sÚ ," NewState Ú$ LPUARTx_IER_TXSE_IE_Setable tÚ , LPUARTx sÚ$ LPUARTx_IER_TXSE_IE_Getable Ú , LPUARTx sÚ LPUARTx_ISR_RXEVF_Clr ·Ú , LPUARTx sÚ LPUARTx_ISR_RXEVF_Chk ÂÚ , LPUARTx sÚ LPUARTx_ISR_TXOV_Clr óÚ , LPUARTx sÚ LPUARTx_ISR_TXOV_Chk þÚ , LPUARTx sÚ LPUARTx_ISR_PERR_Clr Ú , LPUARTx sÚ LPUARTx_ISR_PERR_Chk Ú , LPUARTx sÚ LPUARTx_ISR_FERR_Clr Ú , LPUARTx sÚ LPUARTx_ISR_FERR_Chk Ú , LPUARTx sÚ LPUARTx_ISR_OERR_Clr Ú , LPUARTx sÚ LPUARTx_ISR_OERR_Chk Ú , LPUARTx sÚ LPUARTx_ISR_RXBF_Clr Ú , LPUARTx sÚ LPUARTx_ISR_RXBF_Chk Ú , LPUARTx sÚ LPUARTx_ISR_TXBE_Chk Ú , LPUARTx sÚ LPUARTx_ISR_TXSE_Clr Ú , LPUARTx sÚ LPUARTx_ISR_TXSE_Chk Ú , LPUARTx sÚ ,
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SetValue ¦Ú LPUARTx_BMR_MCTL_Set Ú , LPUARTx sÚ LPUARTx_BMR_MCTL_Get "Ú , LPUARTx sÚ ,
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SetValue ¦Ú LPUARTx_BMR_BAUD_Set *Ú , LPUARTx sÚ LPUARTx_BMR_BAUD_Get 6Ú , LPUARTx sÚ LPUARTx_RXBUF_Read ³Ú , LPUARTx sÚ ,
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SetValue ¦Ú LPUARTx_TXBUF_Write Ú , LPUARTx sÚ ,
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SetValue ¦Ú LPUARTx_DMR_Write ÊÚ , LPUARTx sÚ LPUARTx_DMR_Read [Ú P __FM33A0XXEV_FLASH_H ¼Ú P FLS_RDCR_WAIT_Pos Ú P FLS_RDCR_WAIT_Msk Ú P FLS_RDCR_WAIT_0CYCLE ¡Ú P FLS_RDCR_WAIT_1CYCLE Ú P FLS_RDCR_WAIT_2CYCLE Ú P FLS_PFCR_PRFTEN_Pos wÚ P FLS_PFCR_PRFTEN_Msk ~Ú P FLS_OPTBR_DBGCFGEN_Pos ´Ú P FLS_OPTBR_DBGCFGEN_Msk »Ú P FLS_OPTBR_IF2LOCK_Pos üÚ P FLS_OPTBR_IF2LOCK_Msk Ú P FLS_OPTBR_IF1LOCK_Pos ýÚ P FLS_OPTBR_IF1LOCK_Msk Ú P FLS_OPTBR_DFLSEN_Pos ,Ú P FLS_OPTBR_DFLSEN_Msk 3Ú P FLS_OPTBR_BTSEN_Pos nÚ P FLS_OPTBR_BTSEN_Msk uÚ P FLS_OPTBR_ACLOCKEN_Pos ¤Ú P FLS_OPTBR_ACLOCKEN_Msk «Ú P FLS_OPTBR_DBRDPEN_Pos çÚ P FLS_OPTBR_DBRDPEN_Msk îÚ P FLS_OPTBR_LOCK1_Pos Ú P FLS_OPTBR_LOCK1_Msk Ú P FLS_OPTBR_LOCK2_Pos Ú P FLS_OPTBR_LOCK2_Msk Ú P FLS_OPTBR_LOCK3_Pos Ú P FLS_OPTBR_LOCK3_Msk Ú P FLS_OPTBR_LOCK4_Pos Ú P FLS_OPTBR_LOCK4_Msk Ú P FLS_EPCR_ERTYPE_Pos nÚ P FLS_EPCR_ERTYPE_Msk uÚ P FLS_EPCR_ERTYPE_PAGE Ú P FLS_EPCR_ERTYPE_SECTOR ÊÚ# P FLS_EPCR_ERTYPE_CHIP_ERASE Ú P FLS_EPCR_PREQ_Pos Ú P FLS_EPCR_PREQ_Msk Ú P FLS_EPCR_EREQ_Pos Ú P FLS_EPCR_EREQ_Msk %Ú P FLS_KEY_KEY_Pos §Ú P FLS_KEY_KEY_Msk ®Ú P FLS_IER_OTPIE_Pos Ú P FLS_IER_OTPIE_Msk Ú P FLS_IER_AUTHIE_Pos ÓÚ P FLS_IER_AUTHIE_Msk ÚÚ P FLS_IER_KEYIE_Pos Ú P FLS_IER_KEYIE_Msk %Ú P FLS_IER_CKIE_Pos {Ú P FLS_IER_CKIE_Msk Ú P FLS_IER_PRDIE_Pos !Ú P FLS_IER_PRDIE_Msk (Ú P FLS_IER_ERDIE_Pos ,Ú P FLS_IER_ERDIE_Msk 3Ú P FLS_ISR_KEYSTA_Pos ´Ú P FLS_ISR_KEYSTA_Msk »Ú( P FLS_ISR_KEYSTA_KEY_NONE_PROTECT ÔÚ" P FLS_ISR_KEYSTA_CHIP_ERASE åÚ$ P FLS_ISR_KEYSTA_SECTOR_ERASE 5Ú P FLS_ISR_KEYSTA_PROGRAM ÆÚ' P FLS_ISR_KEYSTA_KEY_ERR_PROTECT Ú P FLS_ISR_BTSF_Pos ZÚ P FLS_ISR_BTSF_Msk aÚ! P FLS_ISR_BTSF_START_0000H Ú! P FLS_ISR_BTSF_START_2000H
Ú P FLS_ISR_OTPERR_Pos ©Ú P FLS_ISR_OTPERR_Msk °Ú P FLS_ISR_AUTHERR_Pos hÚ P FLS_ISR_AUTHERR_Msk oÚ P FLS_ISR_KEYERR_Pos ³Ú P FLS_ISR_KEYERR_Msk ºÚ P FLS_ISR_CKERR_Pos Ú P FLS_ISR_CKERR_Msk Ú P FLS_ISR_PRD_Pos ¥Ú P FLS_ISR_PRD_Msk ¬Ú P FLS_ISR_ERD_Pos °Ú P FLS_ISR_ERD_Msk ·Ú FLS_Deinit 3Ú ,
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SetValue ¦Ú FLS_RDCR_WAIT_Set 8Ú FLS_RDCR_WAIT_Get DÚ ," NewState Ú FLS_PFCR_PRFTEN_Setable þÚ FLS_PFCR_PRFTEN_Getable
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Ú" FLS_OPTBR_IWDTSLP_Getable RÚ FLS_OPTBR_DBGCFGEN_Chk íÚ FLS_OPTBR_IF2LOCK_Chk 5Ú FLS_OPTBR_IF1LOCK_Chk 6Ú! FLS_OPTBR_DFLSEN_Getable ¿Ú FLS_OPTBR_BTSEN_Getable Ú# FLS_OPTBR_ACLOCKEN_Getable 7Ú" FLS_OPTBR_DBRDPEN_Getable zÚ ,
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SetValue ¦Ú FLS_EPCR_ERTYPE_Set Ú FLS_EPCR_ERTYPE_Get Ú ,
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SetValue ¦Ú FLS_EPCR_PREQ_Set 6Ú FLS_EPCR_PREQ_Get BÚ ,
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SetValue ¦Ú FLS_EPCR_EREQ_Set AÚ FLS_EPCR_EREQ_Get MÚ ,
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SetValue ¦Ú FLS_KEY_Write 7Ú ," NewState Ú FLS_IER_OTPIE_Setable Ú FLS_IER_OTPIE_Getable §Ú ," NewState Ú FLS_IER_AUTHIE_Setable ZÚ FLS_IER_AUTHIE_Getable fÚ ," NewState Ú FLS_IER_KEYIE_Setable ¥Ú FLS_IER_KEYIE_Getable ±Ú ," NewState Ú FLS_IER_CKIE_Setable Ú FLS_IER_CKIE_Getable Ú ," NewState Ú FLS_IER_PRDIE_Setable ¨Ú FLS_IER_PRDIE_Getable ´Ú ," NewState Ú FLS_IER_ERDIE_Setable ³Ú FLS_IER_ERDIE_Getable ¿Ú FLS_ISR_KEYSTA_Get ãÚ FLS_ISR_BTSF_Get Ú FLS_ISR_OTPERR_Clr ×Ú FLS_ISR_OTPERR_Chk âÚ FLS_ISR_AUTHERR_Clr Ú FLS_ISR_AUTHERR_Chk ¡Ú FLS_ISR_KEYERR_Clr áÚ FLS_ISR_KEYERR_Chk ìÚ FLS_ISR_CKERR_Clr >Ú FLS_ISR_CKERR_Chk IÚ FLS_ISR_PRD_Clr ÓÚ FLS_ISR_PRD_Chk ÞÚ FLS_ISR_ERD_Clr ÞÚ FLS_ISR_ERD_Chk éÚ P __FM33A0XXEV_PMU_H <Ú 8
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<unnamed> QÚ
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" Å PMOD °Ú
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" Å SLPDP [Ú "" Å CVS áÚ
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" Å SCR úÚ
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" Å TIA Ú! PMU_SleepCfg_InitTypeDef ÓÚ P PMU_CR_LDO15EN_Pos ùÚ P PMU_CR_LDO15EN_Msk Ú P PMU_CR_LDO15EN_B_Pos TÚ P PMU_CR_LDO15EN_B_Msk [Ú P PMU_CR_WKFSEL_Pos Ú P PMU_CR_WKFSEL_Msk Ú P PMU_CR_WKFSEL_RCHF_8M *Ú P PMU_CR_WKFSEL_RCHF_16M ùÚ P PMU_CR_WKFSEL_RCHF_24M úÚ P PMU_CR_WKFSEL_RCHF_32M ûÚ P PMU_CR_SLPDP_Pos RÚ P PMU_CR_SLPDP_Msk YÚ P PMU_CR_SLPDP_DEEPSLEEP áÚ P PMU_CR_SLPDP_SLEEP Ú P PMU_CR_CVS_Pos íÚ P PMU_CR_CVS_Msk ôÚ P PMU_CR_CVS_DISABLE #Ú P PMU_CR_CVS_ENABLE rÚ P PMU_CR_PMOD_Pos §Ú P PMU_CR_PMOD_Msk ®Ú P PMU_CR_PMOD_ACTIVE Ú P PMU_CR_PMOD_LPRUN DÚ P PMU_CR_PMOD_SLEEP \Ú P PMU_WKTR_STPCLR_Pos DÚ P PMU_WKTR_STPCLR_Msk KÚ P PMU_WKTR_STPCLR_SYN |Ú P PMU_WKTR_STPCLR_ASY Ú P PMU_WKTR_T1A_Pos \Ú P PMU_WKTR_T1A_Msk cÚ P PMU_WKTR_T1A_0US ¶Ú P PMU_WKTR_T1A_2US ´Ú P PMU_WKTR_T1A_4US ²Ú P PMU_WKTR_T1A_8US ®Ú P PMU_WKFR_ADCWKF_Pos zÚ P PMU_WKFR_ADCWKF_Msk Ú P PMU_WKFR_RTCWKF_Pos YÚ P PMU_WKFR_RTCWKF_Msk `Ú P PMU_WKFR_SVDWKF_Pos UÚ P PMU_WKFR_SVDWKF_Msk \Ú P PMU_WKFR_LFDETWKF_Pos ÏÚ P PMU_WKFR_LFDETWKF_Msk ÖÚ P PMU_WKFR_IOWKF_Pos ¬Ú P PMU_WKFR_IOWKF_Msk ³Ú P PMU_WKFR_LPU1WKF_Pos Ú P PMU_WKFR_LPU1WKF_Msk %Ú P PMU_WKFR_LPU0WKF_Pos Ú P PMU_WKFR_LPU0WKF_Msk &Ú P PMU_WKFR_COMP_OOWF_Pos [Ú P PMU_WKFR_COMP_OOWF_Msk bÚ P PMU_WKFR_COMP_WINF_Pos bÚ P PMU_WKFR_COMP_WINF_Msk iÚ P PMU_WKFR_COMP2WKF_Pos ÝÚ P PMU_WKFR_COMP2WKF_Msk äÚ P PMU_WKFR_COMP1WKF_Pos ÞÚ P PMU_WKFR_COMP1WKF_Msk åÚ P PMU_WKFR_LPTWKF_Pos RÚ P PMU_WKFR_LPTWKF_Msk YÚ P PMU_WKFR_BSTWKF_Pos YÚ P PMU_WKFR_BSTWKF_Msk `Ú P PMU_WKFR_DBGWKF_Pos uÚ P PMU_WKFR_DBGWKF_Msk |Ú P PMU_IER_SLPEIE_Pos ÄÚ P PMU_IER_SLPEIE_Msk ËÚ P PMU_IER_RTCEIE_Pos ÊÚ P PMU_IER_RTCEIE_Msk ÑÚ P PMU_ISR_SLPEIF_Pos µÚ P PMU_ISR_SLPEIF_Msk ¼Ú P PMU_ISR_RTCEIF_Pos »Ú P PMU_ISR_RTCEIF_Msk ÂÚ PMU_Deinit &Ú PMU_CR_LDO15EN_Chk 2Ú PMU_CR_LDO15EN_B_Chk Ú ,
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SetValue ¦Ú PMU_CR_WKFSEL_Set *Ú PMU_CR_WKFSEL_Get 6Ú ,
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SetValue ¦Ú PMU_CR_SLPDP_Set uÚ PMU_CR_SLPDP_Get Ú ,
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SetValue ¦Ú PMU_CR_CVS_Set Ú PMU_CR_CVS_Get Ú ,
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SetValue ¦Ú PMU_CR_PMOD_Set ÊÚ PMU_CR_PMOD_Get ÖÚ ,
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SetValue ¦Ú PMU_WKTR_STPCLR_Set gÚ PMU_WKTR_STPCLR_Get sÚ ,
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SetValue ¦Ú PMU_WKTR_T1A_Set Ú PMU_WKTR_T1A_Get Ú PMU_WKFR_ADCWKF_Chk ³Ú PMU_WKFR_RTCWKF_Chk Ú PMU_WKFR_SVDWKF_Chk Ú PMU_WKFR_LFDETWKF_Chk Ú PMU_WKFR_IOWKF_Chk åÚ PMU_WKFR_LPU1WKF_Chk WÚ PMU_WKFR_LPU0WKF_Chk XÚ PMU_WKFR_COMP_OOWF_Chk Ú PMU_WKFR_COMP_WINF_Chk Ú PMU_WKFR_COMP2WKF_Chk Ú PMU_WKFR_COMP1WKF_Chk Ú PMU_WKFR_LPTWKF_Chk Ú PMU_WKFR_BSTWKF_Chk Ú PMU_WKFR_DBGWKF_Clr £Ú PMU_WKFR_DBGWKF_Chk ®Ú ," NewState Ú PMU_IER_SLPEIE_Setable KÚ PMU_IER_SLPEIE_Getable WÚ ," NewState Ú PMU_IER_RTCEIE_Setable QÚ PMU_IER_RTCEIE_Getable ]Ú PMU_ISR_SLPEIF_Clr ãÚ PMU_ISR_SLPEIF_Chk îÚ PMU_ISR_RTCEIF_Clr éÚ PMU_ISR_RTCEIF_Chk ôÚ ,
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NWKPinDef §Ú PMU_WKFR_WKPxF_Clr ªÚ ,
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NWKPinDef §Ú PMU_WKFR_WKPxF_Chk µÚ , SleepCfg_InitStruct *Ú PMU_SleepCfg_Init yÚ P __FM33A0XXEV_CMU_H IÚ P HXVAR 8Ú P const_rchf_Trim8 OÚ P const_rchf_Trim16 Ú P const_rchf_Trim24 Ú P const_rchf_Trim32 Ú P __XTHF_CLOCK ðÚ 8
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<unnamed> QÚ
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" Ì FSEL ®Ú "" Ì RCHFEN Ú CMU_RCHF_InitTypeDef ÎÚ 8
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<unnamed> QÚ
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" Ð PLLLDB Ú "" Ð PLLL_EN Ú CMU_PLL_L_InitTypeDef \Ú 8
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<unnamed> QÚ
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" Ô PLLHDB Ú
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" Ô REFPRSC µÚ
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" Ô
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PLLH_OSEL Ú
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" Ô PLLH_INSEL ºÚ "" Ô PLLH_EN Ú CMU_PLL_H_InitTypeDef `Ú 8
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<unnamed> QÚ
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" Û
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SYSCLKSEL Ú
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" Û AHBPRES ¾Ú
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" Û APBPRES ¶Ú "" Û SLP_ENEXTI Ú CMU_SYSCLK_InitTypeDef Ú 8
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<unnamed> QÚ
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" á SYSCLK_Frequency ÁÚ
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" á AHBCLK_Frequency õÚ
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" á APBCLK_Frequency íÚ
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" á RCHF_Frequency {Ú
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" á PLL_H_Frequency Ú
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" á XTHF_Frequency dÚ
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" á LSCLK_Frequency #Ú CMU_ClocksType Ú$ P CMU_SYSCLKCR_SLP_ENEXTI_Pos ØÚ$ P CMU_SYSCLKCR_SLP_ENEXTI_Msk ßÚ! P CMU_SYSCLKCR_APBPRES_Pos ìÚ! P CMU_SYSCLKCR_APBPRES_Msk óÚ" P CMU_SYSCLKCR_APBPRES_DIV1 Ú" P CMU_SYSCLKCR_APBPRES_DIV2 Ú" P CMU_SYSCLKCR_APBPRES_DIV4 Ú" P CMU_SYSCLKCR_APBPRES_DIV8 Ú# P CMU_SYSCLKCR_APBPRES_DIV16 ÐÚ! P CMU_SYSCLKCR_AHBPRES_Pos ôÚ! P CMU_SYSCLKCR_AHBPRES_Msk ûÚ" P CMU_SYSCLKCR_AHBPRES_DIV1 Ú" P CMU_SYSCLKCR_AHBPRES_DIV2 Ú" P CMU_SYSCLKCR_AHBPRES_DIV4 Ú" P CMU_SYSCLKCR_AHBPRES_DIV8 Ú# P CMU_SYSCLKCR_AHBPRES_DIV16 ØÚ" P CMU_SYSCLKCR_STCLKSEL_Pos Ú" P CMU_SYSCLKCR_STCLKSEL_Msk Ú# P CMU_SYSCLKCR_STCLKSEL_SCLK Ú$ P CMU_SYSCLKCR_STCLKSEL_LSCLK GÚ# P CMU_SYSCLKCR_STCLKSEL_RC4M ¬Ú% P CMU_SYSCLKCR_STCLKSEL_SYSCLK åÚ# P CMU_SYSCLKCR_SYSCLKSEL_Pos 8Ú# P CMU_SYSCLKCR_SYSCLKSEL_Msk ?Ú$ P CMU_SYSCLKCR_SYSCLKSEL_RCHF EÚ$ P CMU_SYSCLKCR_SYSCLKSEL_XTHF .Ú% P CMU_SYSCLKCR_SYSCLKSEL_PLL_H ×Ú% P CMU_SYSCLKCR_SYSCLKSEL_LSCLK íÚ P CMU_RCHFCR_FSEL_Pos Ú P CMU_RCHFCR_FSEL_Msk Ú P CMU_RCHFCR_FSEL_8MHZ Ú P CMU_RCHFCR_FSEL_16MHZ gÚ P CMU_RCHFCR_FSEL_24MHZ hÚ P CMU_RCHFCR_FSEL_32MHZ iÚ P CMU_RCHFCR_RCHFEN_Pos ÿÚ P CMU_RCHFCR_RCHFEN_Msk Ú P CMU_RCHFTR_RCHFTRIM_Pos AÚ P CMU_RCHFTR_RCHFTRIM_Msk HÚ P CMU_PLLLCR_PLLDB_Pos 8Ú P CMU_PLLLCR_PLLDB_Msk ?Ú P CMU_PLLLCR_LOCKED_Pos òÚ P CMU_PLLLCR_LOCKED_Msk ùÚ P CMU_PLLLCR_PLLEN_Pos +Ú P CMU_PLLLCR_PLLEN_Msk 2Ú P CMU_PLLHCR_PLLHDB_Pos òÚ P CMU_PLLHCR_PLLHDB_Msk ùÚ P CMU_PLLHCR_PLLHDB_X32 gÚ P CMU_PLLHCR_PLLHDB_X48 `Ú P CMU_PLLHCR_PLLHDB_X64 bÚ P CMU_PLLHCR_LOCKED_Pos öÚ P CMU_PLLHCR_LOCKED_Msk ýÚ P CMU_PLLHCR_REFPRSC_Pos Ú P CMU_PLLHCR_REFPRSC_Msk Ú P CMU_PLLHCR_REFPRSC_DIV1 Ú P CMU_PLLHCR_REFPRSC_DIV2 ¬Ú P CMU_PLLHCR_REFPRSC_DIV4 ªÚ P CMU_PLLHCR_REFPRSC_DIV8 ¦Ú! P CMU_PLLHCR_REFPRSC_DIV12 yÚ! P CMU_PLLHCR_REFPRSC_DIV16 uÚ! P CMU_PLLHCR_REFPRSC_DIV24 vÚ! P CMU_PLLHCR_REFPRSC_DIV32 wÚ P CMU_PLLHCR_OSEL_Pos yÚ P CMU_PLLHCR_OSEL_Msk Ú P CMU_PLLHCR_OSEL_X1 $Ú P CMU_PLLHCR_OSEL_X2 #Ú P CMU_PLLHCR_INSEL_Pos /Ú P CMU_PLLHCR_INSEL_Msk 6Ú P CMU_PLLHCR_INSEL_RCHF <Ú P CMU_PLLHCR_INSEL_XTHF %Ú P CMU_PLLHCR_EN_Pos Ú P CMU_PLLHCR_EN_Msk $Ú P CMU_XTHFCR_XTHF_CFG_Pos 1Ú P CMU_XTHFCR_XTHF_CFG_Msk 8Ú P CMU_XTHFCR_XTHF_CFG_MIN Ú P CMU_XTHFCR_XTHF_CFG_MAX }Ú P CMU_XTHFCR_XTHFEN_Pos ÑÚ P CMU_XTHFCR_XTHFEN_Msk ØÚ P CMU_IER_SYSCSE_IE_Pos ÆÚ P CMU_IER_SYSCSE_IE_Msk ÍÚ P CMU_IER_HFDET_IE_Pos 7Ú P CMU_IER_HFDET_IE_Msk >Ú P CMU_ISR_HFDETO_Pos ËÚ P CMU_ISR_HFDETO_Msk ÒÚ P CMU_ISR_SYSCSE_IF_Pos ·Ú P CMU_ISR_SYSCSE_IF_Msk ¾Ú P CMU_ISR_HFDET_IF_Pos (Ú P CMU_ISR_HFDET_IF_Msk /Ú! P CMU_PCLKCR1_COMP_PCE_Pos Ú! P CMU_PCLKCR1_COMP_PCE_Msk Ú P CMU_PCLKCR1_SVD_PCE_Pos UÚ P CMU_PCLKCR1_SVD_PCE_Msk \Ú P CMU_PCLKCR1_PAD_PCE_Pos mÚ P CMU_PCLKCR1_PAD_PCE_Msk tÚ! P CMU_PCLKCR1_ANAC_PCE_Pos -Ú! P CMU_PCLKCR1_ANAC_PCE_Msk 4Ú! P CMU_PCLKCR1_IWDT_PCE_Pos Ú! P CMU_PCLKCR1_IWDT_PCE_Msk Ú P CMU_PCLKCR1_SCU_PCE_Pos WÚ P CMU_PCLKCR1_SCU_PCE_Msk ^Ú P CMU_PCLKCR1_PMU_PCE_Pos PÚ P CMU_PCLKCR1_PMU_PCE_Msk WÚ P CMU_PCLKCR1_RTC_PCE_Pos YÚ P CMU_PCLKCR1_RTC_PCE_Msk `Ú P CMU_PCLKCR1_LPT_PCE_Pos RÚ P CMU_PCLKCR1_LPT_PCE_Msk YÚ P CMU_PCLKCR2_PAE_PCE_Pos kÚ P CMU_PCLKCR2_PAE_PCE_Msk rÚ P CMU_PCLKCR2_SHA_PCE_Pos eÚ P CMU_PCLKCR2_SHA_PCE_Msk lÚ P CMU_PCLKCR2_CIC_PCE_Pos rÚ P CMU_PCLKCR2_CIC_PCE_Msk yÚ! P CMU_PCLKCR2_WWDT_PCE_Pos ùÚ! P CMU_PCLKCR2_WWDT_PCE_Msk Ú$ P CMU_PCLKCR2_RAMBIST_PCE_Pos 'Ú$ P CMU_PCLKCR2_RAMBIST_PCE_Msk .Ú P CMU_PCLKCR2_NVM_PCE_Pos PÚ P CMU_PCLKCR2_NVM_PCE_Msk WÚ P CMU_PCLKCR2_DMA_PCE_Pos oÚ P CMU_PCLKCR2_DMA_PCE_Msk vÚ P CMU_PCLKCR2_LCD_PCE_Pos nÚ P CMU_PCLKCR2_LCD_PCE_Msk uÚ P CMU_PCLKCR2_AES_PCE_Pos hÚ P CMU_PCLKCR2_AES_PCE_Msk oÚ! P CMU_PCLKCR2_TRNG_PCE_Pos Ú! P CMU_PCLKCR2_TRNG_PCE_Msk Ú P CMU_PCLKCR2_CRC_PCE_Pos iÚ P CMU_PCLKCR2_CRC_PCE_Msk pÚ! P CMU_PCLKCR3_I2C1_PCE_Pos OÚ! P CMU_PCLKCR3_I2C1_PCE_Msk VÚ! P CMU_PCLKCR3_I2C0_PCE_Pos PÚ! P CMU_PCLKCR3_I2C0_PCE_Msk WÚ$ P CMU_PCLKCR3_LPUART1_PCE_Pos /Ú$ P CMU_PCLKCR3_LPUART1_PCE_Msk 6Ú" P CMU_PCLKCR3_U7816_PCE_Pos Ú" P CMU_PCLKCR3_U7816_PCE_Msk Ú$ P CMU_PCLKCR3_LPUART0_PCE_Pos 0Ú$ P CMU_PCLKCR3_LPUART0_PCE_Msk 7Ú! P CMU_PCLKCR3_UICR_PCE_Pos Ú! P CMU_PCLKCR3_UICR_PCE_Msk Ú" P CMU_PCLKCR3_UART5_PCE_Pos ËÚ" P CMU_PCLKCR3_UART5_PCE_Msk ÒÚ" P CMU_PCLKCR3_UART4_PCE_Pos ÌÚ" P CMU_PCLKCR3_UART4_PCE_Msk ÓÚ" P CMU_PCLKCR3_UART3_PCE_Pos ÍÚ" P CMU_PCLKCR3_UART3_PCE_Msk ÔÚ" P CMU_PCLKCR3_UART2_PCE_Pos ÎÚ" P CMU_PCLKCR3_UART2_PCE_Msk ÕÚ" P CMU_PCLKCR3_UART1_PCE_Pos ÏÚ" P CMU_PCLKCR3_UART1_PCE_Msk ÖÚ" P CMU_PCLKCR3_UART0_PCE_Pos ÐÚ" P CMU_PCLKCR3_UART0_PCE_Msk ×Ú! P CMU_PCLKCR3_QSPI_PCE_Pos Ú! P CMU_PCLKCR3_QSPI_PCE_Msk Ú! P CMU_PCLKCR3_SPI4_PCE_Pos Ú! P CMU_PCLKCR3_SPI4_PCE_Msk %Ú! P CMU_PCLKCR3_SPI3_PCE_Pos Ú! P CMU_PCLKCR3_SPI3_PCE_Msk &Ú! P CMU_PCLKCR3_SPI2_PCE_Pos Ú! P CMU_PCLKCR3_SPI2_PCE_Msk 'Ú! P CMU_PCLKCR3_SPI1_PCE_Pos !Ú! P CMU_PCLKCR3_SPI1_PCE_Msk (Ú! P CMU_PCLKCR3_SPI0_PCE_Pos "Ú! P CMU_PCLKCR3_SPI0_PCE_Msk )Ú P CMU_PCLKCR4_ET4_PCE_Pos rÚ P CMU_PCLKCR4_ET4_PCE_Msk yÚ P CMU_PCLKCR4_ET3_PCE_Pos sÚ P CMU_PCLKCR4_ET3_PCE_Msk zÚ P CMU_PCLKCR4_ET2_PCE_Pos tÚ P CMU_PCLKCR4_ET2_PCE_Msk {Ú P CMU_PCLKCR4_ET1_PCE_Pos uÚ P CMU_PCLKCR4_ET1_PCE_Msk |Ú P CMU_PCLKCR4_BT2_PCE_Pos wÚ P CMU_PCLKCR4_BT2_PCE_Msk ~Ú P CMU_PCLKCR4_BT1_PCE_Pos xÚ P CMU_PCLKCR4_BT1_PCE_Msk Ú" P CMU_PCLKCR4_BSTIM_PCE_Pos ¼Ú" P CMU_PCLKCR4_BSTIM_PCE_Msk ÃÚ P CMU_OPCCR1_EXTICKE_Pos ¶Ú P CMU_OPCCR1_EXTICKE_Msk ½Ú! P CMU_OPCCR1_EXTICKSEL_Pos Ú! P CMU_OPCCR1_EXTICKSEL_Msk Ú# P CMU_OPCCR1_EXTICKSEL_LSCLK ÈÚ" P CMU_OPCCR1_EXTICKSEL_HCLK !Ú" P CMU_OPCCR1_LPUART1CKE_Pos áÚ" P CMU_OPCCR1_LPUART1CKE_Msk èÚ" P CMU_OPCCR1_LPUART0CKE_Pos âÚ" P CMU_OPCCR1_LPUART0CKE_Msk éÚ" P CMU_OPCCR1_LPUART1CKS_Pos ÓÚ" P CMU_OPCCR1_LPUART1CKS_Msk ÚÚ$ P CMU_OPCCR1_LPUART1CKS_LSCLK Ú# P CMU_OPCCR1_LPUART1CKS_RCHF àÚ" P CMU_OPCCR1_LPUART0CKS_Pos ÔÚ" P CMU_OPCCR1_LPUART0CKS_Msk ÛÚ$ P CMU_OPCCR1_LPUART0CKS_LSCLK Ú# P CMU_OPCCR1_LPUART0CKS_RCHF áÚ P CMU_OPCCR1_I2C1CKE_Pos Ú P CMU_OPCCR1_I2C1CKE_Msk Ú P CMU_OPCCR1_I2C0CKE_Pos Ú P CMU_OPCCR1_I2C0CKE_Msk Ú P CMU_OPCCR1_I2C1CKS_Pos óÚ P CMU_OPCCR1_I2C1CKS_Msk úÚ" P CMU_OPCCR1_I2C1CKS_APBCLK rÚ P CMU_OPCCR1_I2C1CKS_RCHF Ú" P CMU_OPCCR1_I2C1CKS_SYSCLK FÚ P CMU_OPCCR1_I2C0CKS_Pos ôÚ P CMU_OPCCR1_I2C0CKS_Msk ûÚ" P CMU_OPCCR1_I2C0CKS_APBCLK sÚ P CMU_OPCCR1_I2C0CKS_RCHF Ú" P CMU_OPCCR1_I2C0CKS_SYSCLK GÚ P CMU_OPCCR1_UART1CKE_Pos Ú P CMU_OPCCR1_UART1CKE_Msk Ú P CMU_OPCCR1_UART0CKE_Pos Ú P CMU_OPCCR1_UART0CKE_Msk Ú P CMU_OPCCR1_UART1CKS_Pos sÚ P CMU_OPCCR1_UART1CKS_Msk zÚ# P CMU_OPCCR1_UART1CKS_APBCLK òÚ! P CMU_OPCCR1_UART1CKS_RCHF Ú# P CMU_OPCCR1_UART1CKS_SYSCLK ÆÚ P CMU_OPCCR1_UART0CKS_Pos tÚ P CMU_OPCCR1_UART0CKS_Msk {Ú# P CMU_OPCCR1_UART0CKS_APBCLK óÚ! P CMU_OPCCR1_UART0CKS_RCHF Ú# P CMU_OPCCR1_UART0CKS_SYSCLK ÇÚ P CMU_OPCCR2_RNGPRSC_Pos £Ú P CMU_OPCCR2_RNGPRSC_Msk ªÚ P CMU_OPCCR2_RNGPRSC_DIV1 ¿Ú P CMU_OPCCR2_RNGPRSC_DIV2 ¾Ú P CMU_OPCCR2_RNGPRSC_DIV4 ¼Ú P CMU_OPCCR2_RNGPRSC_DIV8 ¸Ú! P CMU_OPCCR2_RNGPRSC_DIV16 Ú! P CMU_OPCCR2_RNGPRSC_DIV32 Ú P CMU_OPCCR2_NVMCKE_Pos Ú P CMU_OPCCR2_NVMCKE_Msk Ú P CMU_OPCCR2_RNGCKE_Pos
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Ú P CMU_OPCCR2_RNGCKE_Msk Ú P CMU_OPCCR2_LPTCKE_Pos Ú P CMU_OPCCR2_LPTCKE_Msk Ú P CMU_OPCCR2_LPTCKS_Pos óÚ P CMU_OPCCR2_LPTCKS_Msk úÚ! P CMU_OPCCR2_LPTCKS_APBCLK rÚ P CMU_OPCCR2_LPTCKS_LSCLK ¨Ú P CMU_OPCCR2_LPTCKS_RCLP òÚ P CMU_OPCCR2_LPTCKS_PLL_L Ú P CMU_OPCCR2_BSTCKE_Pos Ú P CMU_OPCCR2_BSTCKE_Msk Ú P CMU_OPCCR2_BSTCKS_Pos úÚ P CMU_OPCCR2_BSTCKS_Msk Ú! P CMU_OPCCR2_BSTCKS_APBCLK yÚ P CMU_OPCCR2_BSTCKS_LSCLK ¯Ú P CMU_OPCCR2_BSTCKS_RCLP ùÚ! P CMU_OPCCR2_BSTCKS_SYSCLK MÚ CMU_Deinit 3Ú ," NewState Ú( CMU_SYSCLKCR_SLP_ENEXTI_Setable _Ú( CMU_SYSCLKCR_SLP_ENEXTI_Getable kÚ ,
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SetValue ¦Ú! CMU_SYSCLKCR_APBPRES_Set Ú! CMU_SYSCLKCR_APBPRES_Get Ú ,
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SetValue ¦Ú! CMU_SYSCLKCR_AHBPRES_Set Ú! CMU_SYSCLKCR_AHBPRES_Get #Ú ,
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SetValue ¦Ú" CMU_SYSCLKCR_STCLKSEL_Set µÚ" CMU_SYSCLKCR_STCLKSEL_Get ÁÚ ,
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SetValue ¦Ú# CMU_SYSCLKCR_SYSCLKSEL_Set [Ú# CMU_SYSCLKCR_SYSCLKSEL_Get gÚ ,
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SetValue ¦Ú CMU_RCHFCR_FSEL_Set ²Ú CMU_RCHFCR_FSEL_Get ¾Ú ," NewState Ú" CMU_RCHFCR_RCHFEN_Setable Ú" CMU_RCHFCR_RCHFEN_Getable Ú ,
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SetValue ¦Ú CMU_RCHFTR_RCHFTRIM_Set dÚ CMU_RCHFTR_RCHFTRIM_Get pÚ CMU_PLLLCR_LOCKED_Chk +Ú ,
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SetValue ¦Ú CMU_PLLLCR_PLLDB_Set [Ú CMU_PLLLCR_PLLDB_Get gÚ ," NewState Ú! CMU_PLLLCR_PLLEN_Setable ²Ú! CMU_PLLLCR_PLLEN_Getable ¾Ú ,
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SetValue ¦Ú CMU_PLLHCR_PLLHDB_Set Ú CMU_PLLHCR_PLLHDB_Get !Ú CMU_PLLHCR_LOCKED_Chk /Ú ,
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SetValue ¦Ú CMU_PLLHCR_REFPRSC_Set ´Ú CMU_PLLHCR_REFPRSC_Get ÀÚ ,
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SetValue ¦Ú CMU_PLLHCR_OSEL_Set Ú CMU_PLLHCR_OSEL_Get ¨Ú ,
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SetValue ¦Ú CMU_PLLHCR_INSEL_Set RÚ CMU_PLLHCR_INSEL_Get ^Ú ," NewState Ú CMU_PLLHCR_EN_Setable ¤Ú CMU_PLLHCR_EN_Getable °Ú ,
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SetValue ¦Ú CMU_XTHFCR_XTHF_CFG_Set TÚ CMU_XTHFCR_XTHF_CFG_Get `Ú ," NewState Ú" CMU_XTHFCR_XTHFEN_Setable XÚ" CMU_XTHFCR_XTHFEN_Getable dÚ ," NewState Ú" CMU_IER_SYSCSE_IE_Setable MÚ" CMU_IER_SYSCSE_IE_Getable YÚ ," NewState Ú! CMU_IER_HFDET_IE_Setable ¾Ú! CMU_IER_HFDET_IE_Getable ÊÚ CMU_ISR_HFDETO_Chk Ú CMU_ISR_LFDETO_Chk Ú CMU_ISR_SYSCSE_IF_Clr åÚ CMU_ISR_SYSCSE_IF_Chk ðÚ CMU_ISR_HFDET_IF_Clr VÚ CMU_ISR_HFDET_IF_Chk aÚ ," NewState Ú# CMU_OPCCR1_EXTICKE_Setable =Ú# CMU_OPCCR1_EXTICKE_Getable IÚ ,
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SetValue ¦Ú! CMU_OPCCR1_EXTICKSEL_Set 6Ú! CMU_OPCCR1_EXTICKSEL_Get BÚ ," NewState Ú& CMU_OPCCR1_LPUART1CKE_Setable hÚ& CMU_OPCCR1_LPUART1CKE_Getable tÚ ," NewState Ú& CMU_OPCCR1_LPUART0CKE_Setable iÚ& CMU_OPCCR1_LPUART0CKE_Getable uÚ ,
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SetValue ¦Ú" CMU_OPCCR1_LPUART1CKS_Set öÚ" CMU_OPCCR1_LPUART1CKS_Get Ú ,
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SetValue ¦Ú" CMU_OPCCR1_LPUART0CKS_Set ÷Ú" CMU_OPCCR1_LPUART0CKS_Get Ú ," NewState Ú# CMU_OPCCR1_I2C1CKE_Setable Ú# CMU_OPCCR1_I2C1CKE_Getable Ú ," NewState Ú# CMU_OPCCR1_I2C0CKE_Setable Ú# CMU_OPCCR1_I2C0CKE_Getable Ú ,
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SetValue ¦Ú CMU_OPCCR1_I2C1CKS_Set Ú CMU_OPCCR1_I2C1CKS_Get "Ú ,
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SetValue ¦Ú CMU_OPCCR1_I2C0CKS_Set Ú CMU_OPCCR1_I2C0CKS_Get #Ú ," NewState Ú$ CMU_OPCCR1_UART1CKE_Setable Ú$ CMU_OPCCR1_UART1CKE_Getable Ú ," NewState Ú$ CMU_OPCCR1_UART0CKE_Setable Ú$ CMU_OPCCR1_UART0CKE_Getable Ú ,
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SetValue ¦Ú CMU_OPCCR1_UART1CKS_Set Ú CMU_OPCCR1_UART1CKS_Get ¢Ú ,
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SetValue ¦Ú CMU_OPCCR1_UART0CKS_Set Ú CMU_OPCCR1_UART0CKS_Get £Ú ,
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SetValue ¦Ú CMU_OPCCR2_RNGPRSC_Set ÆÚ CMU_OPCCR2_RNGPRSC_Get ÒÚ ," NewState Ú" CMU_OPCCR2_NVMCKE_Setable Ú" CMU_OPCCR2_NVMCKE_Getable Ú ," NewState Ú" CMU_OPCCR2_RNGCKE_Setable Ú" CMU_OPCCR2_RNGCKE_Getable Ú ," NewState Ú" CMU_OPCCR2_LPTCKE_Setable Ú" CMU_OPCCR2_LPTCKE_Getable Ú ,
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SetValue ¦Ú CMU_OPCCR2_LPTCKS_Set Ú CMU_OPCCR2_LPTCKS_Get "Ú ," NewState Ú" CMU_OPCCR2_BSTCKE_Setable Ú" CMU_OPCCR2_BSTCKE_Getable Ú ,
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SetValue ¦Ú CMU_OPCCR2_BSTCKS_Set Ú CMU_OPCCR2_BSTCKS_Get )Ú , para %Ú CMU_GetClocksFreq uÚ , para %Ú CMU_RCHF_Init tÚ , para %Ú CMU_PLL_H_Init Ú , ClkMode 9Ú CMU_Init_RCHF_Trim oÚ , para %Ú CMU_SysClk_Init :Ú P COMPCLK ´Ú P SVDCLK øÚ P PADCLK Ú P ANACCLK ÐÚ P IWDTCLK «Ú P SCUCLK úÚ P PMUCLK óÚ P RTCCLK üÚ P LPTCLK õÚ P PAECLK Ú P SHACLK Ú P CICCLK Ú P WWDTCLK Ú P RAMBISTCLK ËÚ P FLASHCLK sÚ P DMACLK Ú P LCDCLK Ú P AESCLK Ú P TRNGCLK ¨Ú P CRCCLK Ú P I2C1CLK ôÚ P I2C0CLK õÚ P LPUART1CLK ÔÚ P U7816CLK ¶Ú P LPUART0CLK ÕÚ P
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UARTIRCLK Ú P UART5CLK pÚ P UART4CLK qÚ P UART3CLK rÚ P UART2CLK sÚ P UART1CLK tÚ P UART0CLK uÚ P QSPICLK ¦Ú P SPI4CLK ÃÚ P SPI3CLK ÄÚ P SPI2CLK ÅÚ P SPI1CLK ÆÚ P SPI0CLK ÇÚ P ET4CLK Ú P ET3CLK Ú P ET2CLK Ú P ET1CLK Ú P BT2CLK Ú P BT1CLK Ú P BSTIMCLK bÚ ,
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periph_def µÚ ," NewState Ú CMU_PERCLK_SetableEx ßÚ P __FM33A0XXEV_RTC_H EÚ 8
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<unnamed> QÚ " ¡!Year uÚ " ¡!Month þÚ " ¡!Date Ú " ¡!Hour hÚ " ¡!Minute Ú " ¡!Second ¦Ú " ¡!Week zÚ RTC_TimeDateTypeDef ÕÚ RTC_StampTmieTypeDef LÚ 8
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<unnamed> QÚ " «!Hour ^Ú " «!Minute Ú " «!Second Ú RTC_AlarmTmieTypeDef dÚ P RTC_WRITE_ENABLE ÒÚ P RTC_WRITE_DISABLE Ú P RTC_WER_RTCWE_Pos þÚ P RTC_WER_RTCWE_Msk Ú P RTC_IER_ADJ_IE_Pos ÓÚ P RTC_IER_ADJ_IE_Msk ÚÚ P RTC_IER_ALARM_IE_Pos 1Ú P RTC_IER_ALARM_IE_Msk 8Ú P RTC_IER_1KHZ_IE_Pos Ú P RTC_IER_1KHZ_IE_Msk Ú P RTC_IER_256HZ_IE_Pos _Ú P RTC_IER_256HZ_IE_Msk fÚ P RTC_IER_64HZ_IE_Pos Ú P RTC_IER_64HZ_IE_Msk Ú P RTC_IER_16HZ_IE_Pos Ú P RTC_IER_16HZ_IE_Msk Ú P RTC_IER_8HZ_IE_Pos ÈÚ P RTC_IER_8HZ_IE_Msk ÏÚ P RTC_IER_4HZ_IE_Pos ÌÚ P RTC_IER_4HZ_IE_Msk ÓÚ P RTC_IER_2HZ_IE_Pos ÎÚ P RTC_IER_2HZ_IE_Msk ÕÚ P RTC_IER_SEC_IE_Pos ÇÚ P RTC_IER_SEC_IE_Msk ÎÚ P RTC_IER_MIN_IE_Pos ¾Ú P RTC_IER_MIN_IE_Msk ÅÚ P RTC_IER_HOUR_IE_Pos bÚ P RTC_IER_HOUR_IE_Msk iÚ P RTC_IER_DATE_IE_Pos Ú P RTC_IER_DATE_IE_Msk Ú P RTC_ISR_ADJ_IF_Pos ÄÚ P RTC_ISR_ADJ_IF_Msk ËÚ P RTC_ISR_ALARM_IF_Pos "Ú P RTC_ISR_ALARM_IF_Msk )Ú P RTC_ISR_1KHZ_IF_Pos sÚ P RTC_ISR_1KHZ_IF_Msk zÚ P RTC_ISR_256HZ_IF_Pos PÚ P RTC_ISR_256HZ_IF_Msk WÚ P RTC_ISR_64HZ_IF_Pos
Ú P RTC_ISR_64HZ_IF_Msk Ú P RTC_ISR_16HZ_IF_Pos Ú P RTC_ISR_16HZ_IF_Msk Ú P RTC_ISR_8HZ_IF_Pos ¹Ú P RTC_ISR_8HZ_IF_Msk ÀÚ P RTC_ISR_4HZ_IF_Pos ½Ú P RTC_ISR_4HZ_IF_Msk ÄÚ P RTC_ISR_2HZ_IF_Pos ¿Ú P RTC_ISR_2HZ_IF_Msk ÆÚ P RTC_ISR_SEC_IF_Pos ¸Ú P RTC_ISR_SEC_IF_Msk ¿Ú P RTC_ISR_MIN_IF_Pos ¯Ú P RTC_ISR_MIN_IF_Msk ¶Ú P RTC_ISR_HOUR_IF_Pos SÚ P RTC_ISR_HOUR_IF_Msk ZÚ P RTC_ISR_DATE_IF_Pos sÚ P RTC_ISR_DATE_IF_Msk zÚ P RTC_BCDSEC_BCDSEC_Pos !Ú P RTC_BCDSEC_BCDSEC_Msk (Ú P RTC_BCDMIN_BCDMIN_Pos Ú P RTC_BCDMIN_BCDMIN_Msk Ú P RTC_BCDHOUR_BCDHOUR_Pos WÚ P RTC_BCDHOUR_BCDHOUR_Msk ^Ú P RTC_BCDDATE_BCDDATE_Pos Ú P RTC_BCDDATE_BCDDATE_Msk Ú P RTC_BCDWEEK_BCDWEEK_Pos {Ú P RTC_BCDWEEK_BCDWEEK_Msk Ú" P RTC_BCDMONTH_BCDMONTH_Pos ÃÚ" P RTC_BCDMONTH_BCDMONTH_Msk ÊÚ P RTC_BCDYEAR_BCDYEAR_Pos qÚ P RTC_BCDYEAR_BCDYEAR_Msk xÚ P RTC_ALARM_ALMEN_Pos Ú P RTC_ALARM_ALMEN_Msk Ú P RTC_ALARM_ALARMHOUR_Pos MÚ P RTC_ALARM_ALARMHOUR_Msk TÚ P RTC_ALARM_ALARMMIN_Pos ©Ú P RTC_ALARM_ALARMMIN_Msk °Ú P RTC_ALARM_ALARMSEC_Pos ²Ú P RTC_ALARM_ALARMSEC_Msk ¹Ú P RTC_TMSEL_FSEL_Pos ÀÚ P RTC_TMSEL_FSEL_Msk ÇÚ P RTC_TMSEL_FSEL_PLL1HZ 1Ú P RTC_TMSEL_FSEL_PLLD1HZ ëÚ P RTC_TMSEL_FSEL_SECOND 0Ú P RTC_TMSEL_FSEL_MINUTE Ú P RTC_TMSEL_FSEL_HOUR ²Ú P RTC_TMSEL_FSEL_DAY Ú P RTC_TMSEL_FSEL_ALARM Ú P RTC_TMSEL_FSEL_256S Ú" P RTC_TMSEL_FSEL_PLLD1HZREV øÚ! P RTC_TMSEL_FSEL_SECONDREV =Ú! P RTC_TMSEL_FSEL_MINUTEREV 'Ú P RTC_TMSEL_FSEL_HOURREV ¿Ú P RTC_TMSEL_FSEL_DAYREV !Ú P RTC_TMSEL_FSEL_ALARMREV Ú! P RTC_TMSEL_FSEL_PLL1HZREV >Ú! P RTC_TMSEL_FSEL_SECONDRUN 5Ú P RTC_ADJUST_ADJUST_Pos ÓÚ P RTC_ADJUST_ADJUST_Msk ÚÚ P RTC_ADSIGN_ADSIGN_Pos ýÚ P RTC_ADSIGN_ADSIGN_Msk Ú# P RTC_ADSIGN_ADSIGN_INCREASE ÛÚ# P RTC_ADSIGN_ADSIGN_DECREASE éÚ P RTC_VCAL_PR1SEN_Pos Ú P RTC_VCAL_PR1SEN_Msk Ú P RTC_MSCNT_MSCNT_Pos cÚ P RTC_MSCNT_MSCNT_Msk jÚ P RTC_CALSTEP_CALSTEP_Pos MÚ P RTC_CALSTEP_CALSTEP_Msk TÚ# P RTC_CALSTEP_CALSTEP_006PPM öÚ$ P RTC_CALSTEP_CALSTEP_0119PPM ¿Ú$ P RTC_CALSTEP_CALSTEP_0238PPM ½Ú P RTC_ADCNT_ADJCNT_Pos MÚ P RTC_ADCNT_ADJCNT_Msk TÚ P RTC_SSR_SSR_Pos
Ú P RTC_SSR_SSR_Msk Ú P RTC_SSA_SSAEN_Pos Ú P RTC_SSA_SSAEN_Msk Ú P RTC_SSA_SS_ALARM_Pos Ú P RTC_SSA_SS_ALARM_Msk Ú P RTC_DTR_DUTY_Pos CÚ P RTC_DTR_DUTY_Msk JÚ P RTC_CR_RTC_EN_Pos Ú P RTC_CR_RTC_EN_Msk Ú RTC_Deinit /Ú , para %Ú RTC_TimeDate_SetEx 'Ú , para %Ú RTC_TimeDate_GetEx 3Ú ,
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SetValue ¦Ú RTC_WER_Write .Ú ," NewState Ú RTC_WER_RTCWE_Setable
Ú RTC_WER_RTCWE_Getable Ú ," NewState Ú RTC_IER_ADJ_IE_Setable ZÚ RTC_IER_ADJ_IE_Getable fÚ ," NewState Ú! RTC_IER_ALARM_IE_Setable ¸Ú! RTC_IER_ALARM_IE_Getable ÄÚ ," NewState Ú RTC_IER_1KHZ_IE_Setable Ú RTC_IER_1KHZ_IE_Getable Ú ," NewState Ú! RTC_IER_256HZ_IE_Setable æÚ! RTC_IER_256HZ_IE_Getable òÚ ," NewState Ú RTC_IER_64HZ_IE_Setable Ú RTC_IER_64HZ_IE_Getable 'Ú ," NewState Ú RTC_IER_16HZ_IE_Setable Ú RTC_IER_16HZ_IE_Getable *Ú ," NewState Ú RTC_IER_8HZ_IE_Setable OÚ RTC_IER_8HZ_IE_Getable [Ú ," NewState Ú RTC_IER_4HZ_IE_Setable SÚ RTC_IER_4HZ_IE_Getable _Ú ," NewState Ú RTC_IER_2HZ_IE_Setable UÚ RTC_IER_2HZ_IE_Getable aÚ ," NewState Ú RTC_IER_SEC_IE_Setable NÚ RTC_IER_SEC_IE_Getable ZÚ ," NewState Ú RTC_IER_MIN_IE_Setable EÚ RTC_IER_MIN_IE_Getable QÚ ," NewState Ú RTC_IER_HOUR_IE_Setable éÚ RTC_IER_HOUR_IE_Getable õÚ ," NewState Ú RTC_IER_DATE_IE_Setable Ú RTC_IER_DATE_IE_Getable Ú RTC_ISR_ADJ_IF_Clr òÚ RTC_ISR_ADJ_IF_Chk ýÚ RTC_ISR_ALARM_IF_Clr PÚ RTC_ISR_ALARM_IF_Chk [Ú RTC_ISR_1KHZ_IF_Clr ¡Ú RTC_ISR_1KHZ_IF_Chk ¬Ú RTC_ISR_256HZ_IF_Clr ~Ú RTC_ISR_256HZ_IF_Chk Ú RTC_ISR_64HZ_IF_Clr ³Ú RTC_ISR_64HZ_IF_Chk ¾Ú RTC_ISR_16HZ_IF_Clr ¶Ú RTC_ISR_16HZ_IF_Chk ÁÚ RTC_ISR_8HZ_IF_Clr çÚ RTC_ISR_8HZ_IF_Chk òÚ RTC_ISR_4HZ_IF_Clr ëÚ RTC_ISR_4HZ_IF_Chk öÚ RTC_ISR_2HZ_IF_Clr íÚ RTC_ISR_2HZ_IF_Chk øÚ RTC_ISR_SEC_IF_Clr æÚ RTC_ISR_SEC_IF_Chk ñÚ RTC_ISR_MIN_IF_Clr ÝÚ RTC_ISR_MIN_IF_Chk èÚ RTC_ISR_HOUR_IF_Clr Ú RTC_ISR_HOUR_IF_Chk Ú RTC_ISR_DATE_IF_Clr ¡Ú RTC_ISR_DATE_IF_Chk ¬Ú ,
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SetValue ¦Ú RTC_BCDSEC_Write rÚ RTC_BCDSEC_Read Ú ,
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SetValue ¦Ú RTC_BCDMIN_Write iÚ RTC_BCDMIN_Read úÚ ,
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SetValue ¦Ú RTC_BCDHOUR_Write Ú RTC_BCDHOUR_Read Ú ,
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SetValue ¦Ú RTC_BCDWEEK_Write Ú RTC_BCDWEEK_Read °Ú ,
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SetValue ¦Ú RTC_BCDMONTH_Write ÃÚ RTC_BCDMONTH_Read TÚ ,
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SetValue ¦Ú RTC_BCDYEAR_Write Ú RTC_BCDYEAR_Read «Ú ," NewState Ú RTC_ALARM_ALMEN_Setable Ú RTC_ALARM_ALMEN_Getable &Ú ,
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SetValue ¦Ú RTC_ALARM_ALARMHOUR_Set pÚ RTC_ALARM_ALARMHOUR_Get |Ú ,
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SetValue ¦Ú RTC_ALARM_ALARMMIN_Set ÌÚ RTC_ALARM_ALARMMIN_Get ØÚ ,
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SetValue ¦Ú RTC_ALARM_ALARMSEC_Set ÕÚ RTC_ALARM_ALARMSEC_Get áÚ ,
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SetValue ¦Ú RTC_TMSEL_Write Ú RTC_TMSEL_Read $Ú ,
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SetValue ¦Ú RTC_ADJUST_Write KÚ RTC_ADJUST_Read ÜÚ ,
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SetValue ¦Ú RTC_ADSIGN_ADSIGN_Set Ú RTC_ADSIGN_ADSIGN_Get ,Ú ," NewState Ú RTC_VCAL_PR1SEN_Setable Ú RTC_VCAL_PR1SEN_Getable !Ú ,
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SetValue ¦Ú RTC_MSCNT_Write Ú RTC_MSCNT_Read $Ú ,
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SetValue ¦Ú RTC_CALSTEP_CALSTEP_Set pÚ RTC_CALSTEP_CALSTEP_Get |Ú RTC_ADCNT_Read ?Ú RTC_SSR_Read µÚ ," NewState Ú RTC_SSA_SSAEN_Setable Ú RTC_SSA_SSAEN_Getable £Ú ,
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SetValue ¦Ú RTC_SSA_SS_ALARM_Set 5Ú RTC_SSA_SS_ALARM_Get AÚ ,
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SetValue ¦Ú RTC_DTR_Write 2Ú RTC_DTR_Read ÃÚ ," NewState Ú RTC_CR_RTC_EN_Setable Ú RTC_CR_RTC_EN_Getable Ú , para %Ú RTC_AlarmTime_SetEx ¶Ú P __FM33A0XXEV_DBG_H aÚ P DBG_CR_DBG_LPT_STOP_Pos +Ú P DBG_CR_DBG_LPT_STOP_Msk 2Ú P DBG_CR_DBG_BST_STOP_Pos 2Ú P DBG_CR_DBG_BST_STOP_Msk 9Ú P DBG_CR_DBG_ET4_STOP_Pos NÚ P DBG_CR_DBG_ET4_STOP_Msk UÚ P DBG_CR_DBG_ET3_STOP_Pos OÚ P DBG_CR_DBG_ET3_STOP_Msk VÚ P DBG_CR_DBG_ET2_STOP_Pos PÚ P DBG_CR_DBG_ET2_STOP_Msk WÚ P DBG_CR_DBG_ET1_STOP_Pos QÚ P DBG_CR_DBG_ET1_STOP_Msk XÚ P DBG_CR_DBG_BT2_STOP_Pos SÚ P DBG_CR_DBG_BT2_STOP_Msk ZÚ P DBG_CR_DBG_BT1_STOP_Pos TÚ P DBG_CR_DBG_BT1_STOP_Msk [Ú! P DBG_CR_DBG_WWDT_STOP_Pos ÓÚ! P DBG_CR_DBG_WWDT_STOP_Msk ÚÚ! P DBG_CR_DBG_IWDT_STOP_Pos áÚ! P DBG_CR_DBG_IWDT_STOP_Msk èÚ& P DBG_HDFR_DABORT_ADDR_FLAG_Pos ¢Ú& P DBG_HDFR_DABORT_ADDR_FLAG_Msk ©Ú& P DBG_HDFR_DABORT_RESP_FLAG_Pos Ú& P DBG_HDFR_DABORT_RESP_FLAG_Msk Ú# P DBG_HDFR_SVCUNDEF_FLAG_Pos Ú# P DBG_HDFR_SVCUNDEF_FLAG_Msk Ú P DBG_HDFR_BKPT_FLAG_Pos µÚ P DBG_HDFR_BKPT_FLAG_Msk ¼Ú P DBG_HDFR_TBIT_FLAG_Pos ³Ú P DBG_HDFR_TBIT_FLAG_Msk ºÚ% P DBG_HDFR_SPECIAL_OP_FLAG_Pos ÛÚ% P DBG_HDFR_SPECIAL_OP_FLAG_Msk âÚ& P DBG_HDFR_HDF_REQUEST_FLAG_Pos ~Ú& P DBG_HDFR_HDF_REQUEST_FLAG_Msk
Ú DBG_Deinit KÚ ," NewState Ú$ DBG_CR_DBG_LPT_STOP_Setable ²Ú$ DBG_CR_DBG_LPT_STOP_Getable ¾Ú ," NewState Ú$ DBG_CR_DBG_BST_STOP_Setable ¹Ú$ DBG_CR_DBG_BST_STOP_Getable ÅÚ ," NewState Ú$ DBG_CR_DBG_ET4_STOP_Setable ÕÚ$ DBG_CR_DBG_ET4_STOP_Getable áÚ ," NewState Ú$ DBG_CR_DBG_ET3_STOP_Setable ÖÚ$ DBG_CR_DBG_ET3_STOP_Getable âÚ ," NewState Ú$ DBG_CR_DBG_ET2_STOP_Setable ×Ú$ DBG_CR_DBG_ET2_STOP_Getable ãÚ ," NewState Ú$ DBG_CR_DBG_ET1_STOP_Setable ØÚ$ DBG_CR_DBG_ET1_STOP_Getable äÚ ," NewState Ú$ DBG_CR_DBG_BT2_STOP_Setable ÚÚ$ DBG_CR_DBG_BT2_STOP_Getable æÚ ," NewState Ú$ DBG_CR_DBG_BT1_STOP_Setable ÛÚ$ DBG_CR_DBG_BT1_STOP_Getable çÚ ," NewState Ú% DBG_CR_DBG_WWDT_STOP_Setable ZÚ% DBG_CR_DBG_WWDT_STOP_Getable fÚ ," NewState Ú% DBG_CR_DBG_IWDT_STOP_Setable hÚ% DBG_CR_DBG_IWDT_STOP_Getable tÚ& DBG_HDFR_DABORT_ADDR_FLAG_Clr ÐÚ& DBG_HDFR_DABORT_ADDR_FLAG_Chk ÛÚ& DBG_HDFR_DABORT_RESP_FLAG_Clr ±Ú& DBG_HDFR_DABORT_RESP_FLAG_Chk ¼Ú# DBG_HDFR_SVCUNDEF_FLAG_Clr ®Ú# DBG_HDFR_SVCUNDEF_FLAG_Chk ¹Ú DBG_HDFR_BKPT_FLAG_Clr ãÚ DBG_HDFR_BKPT_FLAG_Chk îÚ DBG_HDFR_TBIT_FLAG_Clr áÚ DBG_HDFR_TBIT_FLAG_Chk ìÚ% DBG_HDFR_SPECIAL_OP_FLAG_Clr Ú% DBG_HDFR_SPECIAL_OP_FLAG_Chk Ú& DBG_HDFR_HDF_REQUEST_FLAG_Clr ¬Ú& DBG_HDFR_HDF_REQUEST_FLAG_Chk ·Ú P __FM33A0XXEV_SPI_H BÚ P SPIx_CR1_IOSWAP_Pos YÚ P SPIx_CR1_IOSWAP_Msk `Ú P SPIx_CR1_IOSWAP_DEFAULT ~Ú! P SPIx_CR1_IOSWAP_EXCHANGE >Ú P SPIx_CR1_MSPA_Pos ÿÚ P SPIx_CR1_MSPA_Msk Ú P SPIx_CR1_MSPA_DELAY ¾Ú P SPIx_CR1_MSPA_NORMAL bÚ P SPIx_CR1_SSPA_Pos ùÚ P SPIx_CR1_SSPA_Msk Ú P SPIx_CR1_SSPA_EARLY ªÚ P SPIx_CR1_SSPA_NORMAL \Ú P SPIx_CR1_MM_Pos Ú P SPIx_CR1_MM_Msk ¡Ú P SPIx_CR1_MM_MASTER úÚ P SPIx_CR1_MM_SLAVE MÚ P SPIx_CR1_WAIT_Pos ûÚ P SPIx_CR1_WAIT_Msk Ú P SPIx_CR1_WAIT_1WAIT ÃÚ P SPIx_CR1_WAIT_2WAIT ÂÚ P SPIx_CR1_WAIT_3WAIT ÁÚ P SPIx_CR1_WAIT_4WAIT ÀÚ P SPIx_CR1_BAUD_Pos Ú P SPIx_CR1_BAUD_Msk Ú P SPIx_CR1_BAUD_DIV2 /Ú P SPIx_CR1_BAUD_DIV4 -Ú P SPIx_CR1_BAUD_DIV8 )Ú P SPIx_CR1_BAUD_DIV16 øÚ P SPIx_CR1_BAUD_DIV32 úÚ P SPIx_CR1_BAUD_DIV64 õÚ P SPIx_CR1_BAUD_DIV128 ÂÚ P SPIx_CR1_BAUD_DIV256 ÀÚ P SPIx_CR1_LSBF_Pos Ú P SPIx_CR1_LSBF_Msk Ú P SPIx_CR1_LSBF_MSB YÚ P SPIx_CR1_LSBF_LSB ZÚ P SPIx_CR1_CPHOL_Pos ¸Ú P SPIx_CR1_CPHOL_Msk ¿Ú P SPIx_CR1_CPHOL_LOW øÚ P SPIx_CR1_CPHOL_HIGH ÈÚ P SPIx_CR1_CPHA_Pos Ú P SPIx_CR1_CPHA_Msk Ú P SPIx_CR1_CPHA_1CLOCK £Ú P SPIx_CR1_CPHA_2CLOCK ¢Ú P SPIx_CR2_DUMMY_EN_Pos ©Ú P SPIx_CR2_DUMMY_EN_Msk °Ú P SPIx_CR2_RXO_Pos 8Ú P SPIx_CR2_RXO_Msk ?Ú P SPIx_CR2_DLEN_Pos Ú P SPIx_CR2_DLEN_Msk Ú P SPIx_CR2_DLEN_8BIT %Ú P SPIx_CR2_DLEN_16BIT ôÚ P SPIx_CR2_DLEN_24BIT õÚ P SPIx_CR2_DLEN_32BIT öÚ P SPIx_CR2_HALFDUPLEX_Pos 6Ú P SPIx_CR2_HALFDUPLEX_Msk =Ú P SPIx_CR2_HALFDUPLEX_SPI |Ú P SPIx_CR2_HALFDUPLEX_DCN Ú P SPIx_CR2_HD_RW_Pos Ú P SPIx_CR2_HD_RW_Msk Ú P SPIx_CR2_HD_RW_WRITE <Ú P SPIx_CR2_HD_RW_READ Ú P SPIx_CR2_CMD8b_Pos ¿Ú P SPIx_CR2_CMD8b_Msk ÆÚ P SPIx_CR2_CMD8b_8BIT ØÚ P SPIx_CR2_CMD8b_DLEN ÌÚ P SPIx_CR2_SSNM_Pos îÚ P SPIx_CR2_SSNM_Msk õÚ P SPIx_CR2_SSNM_HIGH þÚ P SPIx_CR2_SSNM_LOW .Ú P SPIx_CR2_TXO_AC_Pos MÚ P SPIx_CR2_TXO_AC_Msk TÚ P SPIx_CR2_TXO_Pos 6Ú P SPIx_CR2_TXO_Msk =Ú P SPIx_CR2_SSN_Pos =Ú P SPIx_CR2_SSN_Msk DÚ P SPIx_CR2_SSN_LOW }Ú P SPIx_CR2_SSN_HIGH MÚ P SPIx_CR2_SSNSEN_Pos QÚ P SPIx_CR2_SSNSEN_Msk XÚ P SPIx_CR2_SPIEN_Pos ®Ú P SPIx_CR2_SPIEN_Msk µÚ P SPIx_CR3_TXBFC_Pos µÚ P SPIx_CR3_TXBFC_Msk ¼Ú P SPIx_CR3_RXBFC_Pos ·Ú P SPIx_CR3_RXBFC_Msk ¾Ú P SPIx_CR3_MERRC_Pos ³Ú P SPIx_CR3_MERRC_Msk ºÚ P SPIx_CR3_SERRC_Pos Ú P SPIx_CR3_SERRC_Msk ´Ú P SPIx_IER_ERRIE_Pos Ú P SPIx_IER_ERRIE_Msk ¤Ú P SPIx_IER_TXIE_Pos ÜÚ P SPIx_IER_TXIE_Msk ãÚ P SPIx_IER_RXIE_Pos ÞÚ P SPIx_IER_RXIE_Msk åÚ P SPIx_ISR_DCN_TX_Pos $Ú P SPIx_ISR_DCN_TX_Msk +Ú P SPIx_ISR_DCN_TX_COMMAND OÚ P SPIx_ISR_DCN_TX_DATA :Ú P SPIx_ISR_RXCOL_Pos ~Ú P SPIx_ISR_RXCOL_Msk
Ú P SPIx_ISR_TXCOL_Pos |Ú P SPIx_ISR_TXCOL_Msk Ú P SPIx_ISR_BUSY_Pos ÅÚ P SPIx_ISR_BUSY_Msk ÌÚ P SPIx_ISR_MERR_Pos ÒÚ P SPIx_ISR_MERR_Msk ÙÚ P SPIx_ISR_SERR_Pos ÌÚ P SPIx_ISR_SERR_Msk ÓÚ P SPIx_ISR_TXBE_Pos ÕÚ P SPIx_ISR_TXBE_Msk ÜÚ P SPIx_ISR_RXBF_Pos ÖÚ P SPIx_ISR_RXBF_Msk ÝÚ P SPIx_TXBUF_TXBUF_Pos ÞÚ P SPIx_TXBUF_TXBUF_Msk åÚ P SPIx_RXBUF_RXBUF_Pos âÚ P SPIx_RXBUF_RXBUF_Msk éÚ , SPIx eÚ SPIx_Deinit ²Ú , SPIx eÚ ,
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SetValue ¦Ú SPIx_CR1_IOSWAP_Set |Ú , SPIx eÚ SPIx_CR1_IOSWAP_Get Ú , SPIx eÚ ,
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SetValue ¦Ú SPIx_CR1_MSPA_Set "Ú , SPIx eÚ SPIx_CR1_MSPA_Get .Ú , SPIx eÚ ,
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SetValue ¦Ú SPIx_CR1_SSPA_Set Ú , SPIx eÚ SPIx_CR1_SSPA_Get (Ú , SPIx eÚ ,
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SetValue ¦Ú SPIx_CR1_MM_Set ½Ú , SPIx eÚ SPIx_CR1_MM_Get ÉÚ , SPIx eÚ ,
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SetValue ¦Ú SPIx_CR1_WAIT_Set Ú , SPIx eÚ SPIx_CR1_WAIT_Get *Ú , SPIx eÚ ,
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SetValue ¦Ú SPIx_CR1_BAUD_Set 7Ú , SPIx eÚ SPIx_CR1_BAUD_Get CÚ , SPIx eÚ ,
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SetValue ¦Ú SPIx_CR1_LSBF_Set ,Ú , SPIx eÚ SPIx_CR1_LSBF_Get 8Ú , SPIx eÚ ,
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SetValue ¦Ú SPIx_CR1_CPHOL_Set ÛÚ , SPIx eÚ SPIx_CR1_CPHOL_Get çÚ , SPIx eÚ ,
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SetValue ¦Ú SPIx_CR1_CPHA_Set 7Ú , SPIx eÚ SPIx_CR1_CPHA_Get CÚ , SPIx eÚ ," NewState Ú" SPIx_CR2_DUMMY_EN_Setable 0Ú , SPIx eÚ" SPIx_CR2_DUMMY_EN_Getable <Ú , SPIx eÚ ," NewState Ú SPIx_CR2_RXO_Setable ¿Ú , SPIx eÚ SPIx_CR2_RXO_Getable ËÚ , SPIx eÚ ,
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SetValue ¦Ú SPIx_CR2_DLEN_Set /Ú , SPIx eÚ SPIx_CR2_DLEN_Get ;Ú , SPIx eÚ ,
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SetValue ¦Ú SPIx_CR2_HALFDUPLEX_Set YÚ , SPIx eÚ SPIx_CR2_HALFDUPLEX_Get eÚ , SPIx eÚ ,
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SetValue ¦Ú SPIx_CR2_HD_RW_Set ¼Ú , SPIx eÚ SPIx_CR2_HD_RW_Get ÈÚ , SPIx eÚ ,
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SetValue ¦Ú SPIx_CR2_CMD8b_Set âÚ , SPIx eÚ SPIx_CR2_CMD8b_Get îÚ , SPIx eÚ ,
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SetValue ¦Ú SPIx_CR2_SSNM_Set Ú , SPIx eÚ SPIx_CR2_SSNM_Get Ú , SPIx eÚ ," NewState Ú SPIx_CR2_TXO_AC_Setable ÔÚ , SPIx eÚ SPIx_CR2_TXO_AC_Getable àÚ , SPIx eÚ ," NewState Ú SPIx_CR2_TXO_Setable ½Ú , SPIx eÚ SPIx_CR2_TXO_Getable ÉÚ , SPIx eÚ ,
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SetValue ¦Ú SPIx_CR2_SSN_Set `Ú , SPIx eÚ SPIx_CR2_SSN_Get lÚ , SPIx eÚ ," NewState Ú SPIx_CR2_SSNSEN_Setable ØÚ , SPIx eÚ SPIx_CR2_SSNSEN_Getable äÚ , SPIx eÚ ," NewState Ú SPIx_CR2_SPIEN_Setable 5Ú , SPIx eÚ SPIx_CR2_SPIEN_Getable AÚ , SPIx eÚ SPIx_CR3_TXBFC_Clr ãÚ , SPIx eÚ SPIx_CR3_RXBFC_Clr åÚ , SPIx eÚ SPIx_CR3_MERRC_Clr áÚ , SPIx eÚ SPIx_CR3_SERRC_Clr ÛÚ , SPIx eÚ ," NewState Ú SPIx_IER_ERRIE_Setable $Ú , SPIx eÚ SPIx_IER_ERRIE_Getable 0Ú , SPIx eÚ ," NewState Ú SPIx_IER_TXIE_Setable cÚ , SPIx eÚ SPIx_IER_TXIE_Getable oÚ , SPIx eÚ ," NewState Ú SPIx_IER_RXIE_Setable eÚ , SPIx eÚ SPIx_IER_RXIE_Getable qÚ , SPIx eÚ ,
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SetValue ¦Ú SPIx_ISR_DCN_TX_Set GÚ , SPIx eÚ SPIx_ISR_DCN_TX_Get SÚ , SPIx eÚ SPIx_ISR_RXCOL_Clr ¬Ú , SPIx eÚ SPIx_ISR_RXCOL_Chk ·Ú , SPIx eÚ SPIx_ISR_TXCOL_Clr ªÚ , SPIx eÚ SPIx_ISR_TXCOL_Chk µÚ , SPIx eÚ SPIx_ISR_BUSY_Chk þÚ , SPIx eÚ SPIx_ISR_MERR_Chk Ú , SPIx eÚ SPIx_ISR_SERR_Chk Ú , SPIx eÚ SPIx_ISR_TXBE_Chk Ú , SPIx eÚ SPIx_ISR_RXBF_Chk Ú , SPIx eÚ ,
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SetValue ¦Ú SPIx_TXBUF_Write Ú , SPIx eÚ SPIx_RXBUF_Read ¥Ú , SPIx eÚ , SPIx eÚ SPI_SSN_Set_Low oÚ , SPIx eÚ SPI_SSN_Set_High Ú , SPIx eÚ , data DÚ SPI_RW_Byte ëÚ P __FM33A0XXEV_RNG_H GÚ P RNG_CR_EN_Pos SÚ P RNG_CR_EN_Msk ZÚ P RNG_DOR_OUT_Pos Ú P RNG_DOR_OUT_Msk ¡Ú P RNG_SR_LFSREN_Pos Ú P RNG_SR_LFSREN_Msk Ú P RNG_SR_RNF_Pos îÚ P RNG_SR_RNF_Msk õÚ P RNG_CRC_CR_CRCEN_Pos 6Ú P RNG_CRC_CR_CRCEN_Msk =Ú P RNG_CRC_DIR_CRCIN_Pos æÚ P RNG_CRC_DIR_CRCIN_Msk íÚ P RNG_CRC_SR_CRCDONE_Pos Ú P RNG_CRC_SR_CRCDONE_Msk Ú RNG_Deinit 1Ú ," NewState Ú RNG_CR_EN_Setable ÚÚ RNG_CR_EN_Getable æÚ RNG_DOR_Read ÊÚ RNG_SR_LFSREN_Chk =Ú RNG_SR_RNF_Clr Ú RNG_SR_RNF_Chk 'Ú ," NewState Ú! RNG_CRC_CR_CRCEN_Setable ½Ú! RNG_CRC_CR_CRCEN_Getable ÉÚ ,
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SetValue ¦Ú RNG_CRC_DIR_Write Ú RNG_CRC_DIR_Read Ú RNG_CRC_SR_CRCDONE_Clr ½Ú RNG_CRC_SR_CRCDONE_Chk ÈÚ P __FM33A0XXEV_U7816_H ÿÚ 8
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<unnamed> QÚ "" Ã&TXEN Ú "" Ã&RXEN Ú "" Ã&CKOEN QÚ "" Ã&HPUAT ?Ú "" Ã&HPUEN AÚ
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" Ã&ERSW Ú
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" Ã&ERSGD aÚ "" Ã&BGTEN QÚ
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" Ã&REP_T <Ú
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" Ã&PAR ÷Ú
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" Ã&SFREN XÚ
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" Ã&RFREN YÚ "" Ã&TREPEN ñÚ "" Ã&RREPEN óÚ "" Ã&DICONV üÚ
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" Ã&TXEGT JÚ
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" Ã&CLKDIV Ú
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" Ã&PDIV ¥Ú "" Ã&RXIE Ú "" Ã&TXIE Ú "" Ã&LSIE Ú U7816_InitTypeDef Ú P U7816_CR_TXEN_Pos [Ú P U7816_CR_TXEN_Msk bÚ P U7816_CR_RXEN_Pos ]Ú P U7816_CR_RXEN_Msk dÚ P U7816_CR_CKOEN_Pos (Ú P U7816_CR_CKOEN_Msk /Ú P U7816_CR_HPUAT_Pos Ú P U7816_CR_HPUAT_Msk Ú P U7816_CR_HPUEN_Pos Ú P U7816_CR_HPUEN_Msk Ú P U7816_FFR_SFREN_Pos ÏÚ P U7816_FFR_SFREN_Msk ÖÚ P U7816_FFR_SFREN_3ETU ÞÚ P U7816_FFR_SFREN_2ETU ßÚ P U7816_FFR_ERSW_Pos Ú P U7816_FFR_ERSW_Msk Ú P U7816_FFR_ERSW_1ETU Ú P U7816_FFR_ERSW_1P5ETU Ú P U7816_FFR_ERSW_2ETU Ú P U7816_FFR_ERSGD_Pos ØÚ P U7816_FFR_ERSGD_Msk ßÚ P U7816_FFR_ERSGD_1ETU éÚ P U7816_FFR_ERSGD_2ETU èÚ P U7816_FFR_BGTEN_Pos ÝÚ P U7816_FFR_BGTEN_Msk äÚ P U7816_FFR_REP_T_Pos ³Ú P U7816_FFR_REP_T_Msk ºÚ P U7816_FFR_REP_T_1TIMES ,Ú P U7816_FFR_REP_T_3TIMES *Ú P U7816_FFR_PAR_Pos nÚ P U7816_FFR_PAR_Msk uÚ P U7816_FFR_PAR_EVEN pÚ P U7816_FFR_PAR_ODD ÉÚ P U7816_FFR_PAR_1ALAWAYS SÚ P U7816_FFR_PAR_NON µÚ P U7816_FFR_RFREN_Pos ÐÚ P U7816_FFR_RFREN_Msk ×Ú P U7816_FFR_RFREN_1ETU áÚ P U7816_FFR_RFREN_2ETU àÚ P U7816_FFR_TREPEN_Pos }Ú P U7816_FFR_TREPEN_Msk Ú P U7816_FFR_RREPEN_Pos Ú P U7816_FFR_RREPEN_Msk Ú P U7816_FFR_DICONV_Pos Ú P U7816_FFR_DICONV_Msk Ú! P U7816_FFR_DICONV_FORWARD Ú! P U7816_FFR_DICONV_REVERSE Ú P U7816_EGTR_TXEGT_Pos kÚ P U7816_EGTR_TXEGT_Msk rÚ P U7816_PSC_CLKDIV_Pos Ú P U7816_PSC_CLKDIV_Msk Ú P U7816_BGR_PDIV_Pos Ú P U7816_BGR_PDIV_Msk &Ú P U7816_RXBUF_RXBUF_Pos Ú P U7816_RXBUF_RXBUF_Msk Ú P U7816_TXBUF_TXBUF_Pos Ú P U7816_TXBUF_TXBUF_Msk Ú P U7816_IER_RXIE_Pos Ú P U7816_IER_RXIE_Msk Ú P U7816_IER_TXIE_Pos Ú P U7816_IER_TXIE_Msk Ú P U7816_IER_LSIE_Pos Ú P U7816_IER_LSIE_Msk 'Ú P U7816_ISR_WAIT_RPT_Pos Ú P U7816_ISR_WAIT_RPT_Msk ´Ú P U7816_ISR_TXBUSY_Pos LÚ P U7816_ISR_TXBUSY_Msk SÚ P U7816_ISR_RXBUSY_Pos NÚ P U7816_ISR_RXBUSY_Msk UÚ P U7816_ISR_TPARERR_Pos Ú P U7816_ISR_TPARERR_Msk Ú P U7816_ISR_RPARERR_Pos Ú P U7816_ISR_RPARERR_Msk "Ú P U7816_ISR_FRERR_Pos ¼Ú P U7816_ISR_FRERR_Msk ÃÚ P U7816_ISR_OVERR_Pos ¯Ú P U7816_ISR_OVERR_Msk ¶Ú P U7816_ISR_RXIF_Pos Ú P U7816_ISR_RXIF_Msk Ú P U7816_ISR_TXIF_Pos Ú P U7816_ISR_TXIF_Msk Ú P U7816_ISR_ERRIF_Pos ÅÚ P U7816_ISR_ERRIF_Msk ÌÚ U7816_Deinit éÚ ," NewState Ú U7816_CR_TXEN_Setable âÚ U7816_CR_TXEN_Getable îÚ ," NewState Ú U7816_CR_RXEN_Setable äÚ U7816_CR_RXEN_Getable ðÚ ," NewState Ú U7816_CR_CKOEN_Setable ¯Ú U7816_CR_CKOEN_Getable »Ú ," NewState Ú U7816_CR_HPUAT_Setable Ú U7816_CR_HPUAT_Getable ©Ú ," NewState Ú U7816_CR_HPUEN_Setable Ú U7816_CR_HPUEN_Getable «Ú ,
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SetValue ¦Ú U7816_FFR_SFREN_Set òÚ U7816_FFR_SFREN_Get þÚ ,
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SetValue ¦Ú U7816_FFR_ERSW_Set 1Ú U7816_FFR_ERSW_Get =Ú ,
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SetValue ¦Ú U7816_FFR_ERSGD_Set ûÚ U7816_FFR_ERSGD_Get Ú ," NewState Ú U7816_FFR_BGTEN_Setable dÚ U7816_FFR_BGTEN_Getable pÚ ,
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SetValue ¦Ú U7816_FFR_REP_T_Set ÖÚ U7816_FFR_REP_T_Get âÚ ,
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SetValue ¦Ú U7816_FFR_PAR_Set Ú U7816_FFR_PAR_Get Ú ,
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SetValue ¦Ú U7816_FFR_RFREN_Set óÚ U7816_FFR_RFREN_Get ÿÚ ," NewState Ú! U7816_FFR_TREPEN_Setable Ú! U7816_FFR_TREPEN_Getable Ú ," NewState Ú! U7816_FFR_RREPEN_Setable Ú! U7816_FFR_RREPEN_Getable Ú ,
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SetValue ¦Ú U7816_FFR_DICONV_Set «Ú U7816_FFR_DICONV_Get ·Ú ,
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SetValue ¦Ú U7816_EGTR_Write ¢Ú U7816_EGTR_Read 3Ú ,
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SetValue ¦Ú U7816_PSC_Write ðÚ U7816_PSC_Read Ú ,
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SetValue ¦Ú U7816_BGR_Write ûÚ U7816_BGR_Read Ú U7816_RXBUF_Read ÜÚ ,
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SetValue ¦Ú U7816_TXBUF_Write IÚ ," NewState Ú U7816_IER_RXIE_Setable Ú U7816_IER_RXIE_Getable ¨Ú ," NewState Ú U7816_IER_TXIE_Setable Ú U7816_IER_TXIE_Getable ¦Ú ," NewState Ú U7816_IER_LSIE_Setable §Ú U7816_IER_LSIE_Getable ³Ú U7816_ISR_WAIT_RPT_Chk æÚ U7816_ISR_TXBUSY_Chk
Ú U7816_ISR_RXBUSY_Chk Ú U7816_ISR_TPARERR_Clr GÚ U7816_ISR_TPARERR_Chk RÚ U7816_ISR_RPARERR_Clr IÚ U7816_ISR_RPARERR_Chk TÚ U7816_ISR_FRERR_Clr êÚ U7816_ISR_FRERR_Chk õÚ U7816_ISR_OVERR_Clr ÝÚ U7816_ISR_OVERR_Chk èÚ U7816_ISR_RXIF_Chk ?Ú U7816_ISR_TXIF_Chk =Ú U7816_ISR_ERRIF_Chk þÚ , para %Ú U7816_Init ¶Ú P __FM33A0XXEV_UART_H ðÚ RxInt þÚ TxInt üÚ UART_IntTypeDef lÚ
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Seven7Bit Ú
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Eight8Bit £Ú Nine9Bit Ú Six6Bit fÚ UART_DataBitTypeDef öÚ NONE ÅÚ EVEN ÇÚ ODD Ú UART_ParityBitTypeDef óÚ OneBit °Ú TwoBit Ú UART_StopBitTypeDef ÊÚ 8
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<unnamed> QÚ
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" ( BaudRate ùÚ "" (DataBit UÚ "" (
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ParityBit RÚ "" (StopBit )Ú
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" ( ClockSrc íÚ UART_SInitTypeDef ¬Ú 8
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<unnamed> QÚ "" (RXBF_IE ÈÚ "" (TXBE_IE ÇÚ "" (TXSE_IE ¶Ú
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" (SPBRG Ú
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" (PDSEL Ú
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" (PARITY %Ú "" (RXTO_IE Ú "" (ERRIE tÚ "" (RXEN °Ú
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" (STOPSEL ÒÚ "" (TXEN ®Ú "" (IREN ¿Ú "" (RXDFLAG ßÚ "" (TXDFLAG ÝÚ UART_InitTypeDef Ú P UARTIR_CR_IRFLAG_Pos 3Ú P UARTIR_CR_IRFLAG_Msk :Ú" P UARTIR_CR_IRFLAG_POSITIVE èÚ! P UARTIR_CR_IRFLAG_NEGTIVE KÚ P UARTIR_CR_TH_Pos TÚ P UARTIR_CR_TH_Msk [Ú P UARTIR_CR_TZBRG_Pos aÚ P UARTIR_CR_TZBRG_Msk hÚ P UARTx_CSR_BUSY_Pos yÚ P UARTx_CSR_BUSY_Msk Ú P UARTx_CSR_TXIREN_Pos ÞÚ P UARTx_CSR_TXIREN_Msk åÚ P UARTx_CSR_RXTOEN_Pos ØÚ P UARTx_CSR_RXTOEN_Msk ßÚ P UARTx_CSR_IOSWAP_Pos åÚ P UARTx_CSR_IOSWAP_Msk ìÚ! P UARTx_CSR_IOSWAP_DEFAULT
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Ú" P UARTx_CSR_IOSWAP_EXCHANGE ÊÚ! P UARTx_CSR_DMATXIFCFG_Pos ÓÚ! P UARTx_CSR_DMATXIFCFG_Msk ÚÚ P UARTx_CSR_BITORD_Pos ôÚ P UARTx_CSR_BITORD_Msk ûÚ P UARTx_CSR_BITORD_LSB EÚ P UARTx_CSR_BITORD_MSB DÚ P UARTx_CSR_STOPCFG_Pos Ú P UARTx_CSR_STOPCFG_Msk §Ú# P UARTx_CSR_STOPCFG_1STOPBIT rÚ# P UARTx_CSR_STOPCFG_2STOPBIT qÚ P UARTx_CSR_PDSEL_Pos BÚ P UARTx_CSR_PDSEL_Msk IÚ P UARTx_CSR_PDSEL_7BIT \Ú P UARTx_CSR_PDSEL_8BIT [Ú P UARTx_CSR_PDSEL_9BIT ZÚ P UARTx_CSR_PDSEL_6BIT ]Ú P UARTx_CSR_PARITY_Pos ßÚ P UARTx_CSR_PARITY_Msk æÚ P UARTx_CSR_PARITY_NONE ßÚ P UARTx_CSR_PARITY_EVEN áÚ P UARTx_CSR_PARITY_ODD :Ú P UARTx_CSR_RXPOL_Pos %Ú P UARTx_CSR_RXPOL_Msk ,Ú! P UARTx_CSR_RXPOL_POSITIVE ÚÚ P UARTx_CSR_RXPOL_NEGTIVE =Ú P UARTx_CSR_TXPOL_Pos #Ú P UARTx_CSR_TXPOL_Msk *Ú! P UARTx_CSR_TXPOL_POSITIVE ØÚ P UARTx_CSR_TXPOL_NEGTIVE ;Ú P UARTx_CSR_RXEN_Pos Ú P UARTx_CSR_RXEN_Msk Ú P UARTx_CSR_RXEN_DISBALE µÚ P UARTx_CSR_RXEN_ENABLE Ú P UARTx_CSR_TXEN_Pos }Ú P UARTx_CSR_TXEN_Msk Ú P UARTx_CSR_TXEN_DISBALE ³Ú P UARTx_CSR_TXEN_ENABLE Ú P UARTx_IER_RXTO_IE_Pos Ú P UARTx_IER_RXTO_IE_Msk Ú P UARTx_IER_RXERR_IE_Pos <Ú P UARTx_IER_RXERR_IE_Msk CÚ P UARTx_IER_RXBF_IE_Pos Ú P UARTx_IER_RXBF_IE_Msk ¦Ú P UARTx_IER_NEWUP_IE_Pos @Ú P UARTx_IER_NEWUP_IE_Msk GÚ P UARTx_IER_TXBE_IE_Pos Ú P UARTx_IER_TXBE_IE_Msk ¥Ú P UARTx_IER_TXSE_IE_Pos Ú P UARTx_IER_TXSE_IE_Msk Ú P UARTx_ISR_PERR_Pos }Ú P UARTx_ISR_PERR_Msk Ú P UARTx_ISR_FERR_Pos Ú P UARTx_ISR_FERR_Msk Ú P UARTx_ISR_OERR_Pos ~Ú P UARTx_ISR_OERR_Msk
Ú P UARTx_ISR_RXTO_Pos iÚ P UARTx_ISR_RXTO_Msk pÚ P UARTx_ISR_RXBF_Pos Ú P UARTx_ISR_RXBF_Msk Ú P UARTx_ISR_TXBE_Pos Ú P UARTx_ISR_TXBE_Msk Ú P UARTx_ISR_TXSE_Pos rÚ P UARTx_ISR_TXSE_Msk yÚ! P UARTx_TODR_TXDLY_LEN_Pos Ú! P UARTx_TODR_TXDLY_LEN_Msk Ú P UARTx_TODR_RXTO_LEN_Pos ÖÚ P UARTx_TODR_RXTO_LEN_Msk ÝÚ P UARTx_RXBUF_RXBUF_Pos Ú P UARTx_RXBUF_RXBUF_Msk Ú P UARTx_TXBUF_TXBUF_Pos Ú P UARTx_TXBUF_TXBUF_Msk Ú P UARTx_BRG_SPBRG_Pos IÚ P UARTx_BRG_SPBRG_Msk PÚ UART_Deinit ÚÚ ,
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SetValue ¦Ú UARTIR_CR_IRFLAG_Set VÚ UARTIR_CR_IRFLAG_Get bÚ ,
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SetValue ¦Ú UARTIR_CR_TH_Set wÚ UARTIR_CR_TH_Get Ú ,
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SetValue ¦Ú UARTIR_CR_TZBRG_Set Ú UARTIR_CR_TZBRG_Get Ú , UARTx Ú UARTx_Deinit `Ú , UARTx Ú UARTx_CSR_BUSY_Chk ²Ú , UARTx Ú ," NewState Ú! UARTx_CSR_TXIREN_Setable eÚ , UARTx Ú! UARTx_CSR_TXIREN_Getable qÚ , UARTx Ú ," NewState Ú! UARTx_CSR_RXTOEN_Setable _Ú , UARTx Ú! UARTx_CSR_RXTOEN_Getable kÚ , UARTx Ú ,
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SetValue ¦Ú UARTx_CSR_IOSWAP_Set Ú , UARTx Ú UARTx_CSR_IOSWAP_Get Ú , UARTx Ú ," NewState Ú% UARTx_CSR_DMATXIFCFG_Setable ZÚ , UARTx Ú% UARTx_CSR_DMATXIFCFG_Getable fÚ , UARTx Ú ,
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SetValue ¦Ú UARTx_CSR_BITORD_Set Ú , UARTx Ú UARTx_CSR_BITORD_Get #Ú , UARTx Ú ,
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SetValue ¦Ú UARTx_CSR_STOPCFG_Set ÃÚ , UARTx Ú UARTx_CSR_STOPCFG_Get ÏÚ , UARTx Ú ,
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SetValue ¦Ú UARTx_CSR_PDSEL_Set eÚ , UARTx Ú UARTx_CSR_PDSEL_Get qÚ , UARTx Ú ,
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SetValue ¦Ú UARTx_CSR_PARITY_Set Ú , UARTx Ú UARTx_CSR_PARITY_Get Ú , UARTx Ú ," NewState Ú UARTx_CSR_RXPOL_Setable ¬Ú , UARTx Ú UARTx_CSR_RXPOL_Getable ¸Ú , UARTx Ú ," NewState Ú UARTx_CSR_TXPOL_Setable ªÚ , UARTx Ú UARTx_CSR_TXPOL_Getable ¶Ú , UARTx Ú ," NewState Ú UARTx_CSR_RXEN_Setable Ú , UARTx Ú UARTx_CSR_RXEN_Getable Ú , UARTx Ú ," NewState Ú UARTx_CSR_TXEN_Setable Ú , UARTx Ú UARTx_CSR_TXEN_Getable Ú , UARTx Ú ," NewState Ú" UARTx_IER_RXTO_IE_Setable Ú , UARTx Ú" UARTx_IER_RXTO_IE_Getable Ú , UARTx Ú ," NewState Ú# UARTx_IER_RXERR_IE_Setable ÃÚ , UARTx Ú# UARTx_IER_RXERR_IE_Getable ÏÚ , UARTx Ú ," NewState Ú" UARTx_IER_RXBF_IE_Setable &Ú , UARTx Ú" UARTx_IER_RXBF_IE_Getable 2Ú , UARTx Ú ," NewState Ú# UARTx_IER_NEWUP_IE_Setable ÇÚ , UARTx Ú# UARTx_IER_NEWUP_IE_Getable ÓÚ , UARTx Ú ," NewState Ú" UARTx_IER_TXBE_IE_Setable %Ú , UARTx Ú" UARTx_IER_TXBE_IE_Getable 1Ú , UARTx Ú ," NewState Ú" UARTx_IER_TXSE_IE_Setable Ú , UARTx Ú" UARTx_IER_TXSE_IE_Getable Ú , UARTx Ú UARTx_ISR_PERR_Clr «Ú , UARTx Ú UARTx_ISR_PERR_Chk ¶Ú , UARTx Ú UARTx_ISR_FERR_Clr µÚ , UARTx Ú UARTx_ISR_FERR_Chk ÀÚ , UARTx Ú UARTx_ISR_OERR_Clr ¬Ú , UARTx Ú UARTx_ISR_OERR_Chk ·Ú , UARTx Ú UARTx_ISR_RXTO_Clr Ú , UARTx Ú UARTx_ISR_RXTO_Chk ¢Ú , UARTx Ú UARTx_ISR_RXBF_Clr ²Ú , UARTx Ú UARTx_ISR_RXBF_Chk ½Ú , UARTx Ú UARTx_ISR_NEWKF_Clr gÚ , UARTx Ú UARTx_ISR_NEWKF_Chk rÚ , UARTx Ú UARTx_ISR_TXBE_Chk ¼Ú , UARTx Ú UARTx_ISR_TXSE_Clr Ú , UARTx Ú UARTx_ISR_TXSE_Chk «Ú , UARTx Ú ,
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SetValue ¦Ú! UARTx_TODR_TXDLY_LEN_Set ¯Ú , UARTx Ú! UARTx_TODR_TXDLY_LEN_Get »Ú , UARTx Ú ,
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SetValue ¦Ú UARTx_TODR_RXTO_LEN_Set ùÚ , UARTx Ú UARTx_TODR_RXTO_LEN_Get Ú , UARTx Ú UARTx_RXBUF_Read SÚ , UARTx Ú ,
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SetValue ¦Ú UARTx_TXBUF_Write ÀÚ , UARTx Ú UARTx_TXBUF_Read QÚ , UARTx Ú ,
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SetValue ¦Ú UARTx_BGR_Write rÚ , UARTx Ú UARTx_BGR_Read Ú ,
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BaudRate ÇÚ ,
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Clk ¿Ú UART_BaudREGCalc `Ú ,
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ModuFreq ¬Ú , ModuDutyCycle ¡Ú ,
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Clk ¿Ú UART_IRModulation_Init wÚ , UARTx Ú , para %Ú
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UART_Init §Ú , UARTx Ú , para %Ú , CMU_Clocks Ú UART_SInit RÚ P __FM33A0XXEV_LPTIM_H ¤Ú P LPTIM_CFGR_ETR_AFEN_Pos BÚ P LPTIM_CFGR_ETR_AFEN_Msk IÚ P LPTIM_CFGR_PSCSEL_Pos àÚ P LPTIM_CFGR_PSCSEL_Msk çÚ! P LPTIM_CFGR_PSCSEL_CLKSEL NÚ" P LPTIM_CFGR_PSCSEL_LPTETRF éÚ P LPTIM_CFGR_DIVSEL_Pos ãÚ P LPTIM_CFGR_DIVSEL_Msk êÚ P LPTIM_CFGR_DIVSEL_DIV1 ÿÚ P LPTIM_CFGR_DIVSEL_DIV2 þÚ P LPTIM_CFGR_DIVSEL_DIV4 üÚ P LPTIM_CFGR_DIVSEL_DIV8 øÚ P LPTIM_CFGR_DIVSEL_DIV16 ÇÚ P LPTIM_CFGR_DIVSEL_DIV32 ÉÚ P LPTIM_CFGR_DIVSEL_DIV64 ÄÚ! P LPTIM_CFGR_DIVSEL_DIV128 Ú P LPTIM_CFGR_EDGESEL_Pos ¯Ú P LPTIM_CFGR_EDGESEL_Msk ¶Ú" P LPTIM_CFGR_EDGESEL_RISING Ú# P LPTIM_CFGR_EDGESEL_FALLING ÜÚ P LPTIM_CFGR_TRIGCFG_Pos ¢Ú P LPTIM_CFGR_TRIGCFG_Msk ©Ú" P LPTIM_CFGR_TRIGCFG_RISING Ú# P LPTIM_CFGR_TRIGCFG_FALLING ÏÚ$ P LPTIM_CFGR_TRIGCFG_EXTERNAL gÚ P LPTIM_CFGR_ONST_Pos jÚ P LPTIM_CFGR_ONST_Msk qÚ! P LPTIM_CFGR_ONST_CONTINUE -Ú P LPTIM_CFGR_ONST_SINGLE ÔÚ P LPTIM_CFGR_TMODE_Pos 3Ú P LPTIM_CFGR_TMODE_Msk :Ú! P LPTIM_CFGR_TMODE_COUNTER =Ú P LPTIM_CFGR_TMODE_PULSE ØÚ P LPTIM_CFGR_TMODE_ASY xÚ! P LPTIM_CFGR_TMODE_TIMEOUT 6Ú P LPTIM_CNTR_CNT32_Pos MÚ P LPTIM_CNTR_CNT32_Msk TÚ P LPTIM_CCSR_CAP1SSEL_Pos aÚ P LPTIM_CCSR_CAP1SSEL_Msk hÚ$ P LPTIM_CCSR_CAP1SSEL_LPT_CH1 Ú! P LPTIM_CCSR_CAP1SSEL_XTLF SÚ! P LPTIM_CCSR_CAP1SSEL_RCLP `Ú! P LPTIM_CCSR_CAP1SSEL_RCMF iÚ P LPTIM_CCSR_CAP4EDGE_Pos Ú P LPTIM_CCSR_CAP4EDGE_Msk Ú# P LPTIM_CCSR_CAP4EDGE_RISING àÚ$ P LPTIM_CCSR_CAP4EDGE_FALLING Ú P LPTIM_CCSR_CAP3EDGE_Pos Ú P LPTIM_CCSR_CAP3EDGE_Msk Ú# P LPTIM_CCSR_CAP3EDGE_RISING áÚ$ P LPTIM_CCSR_CAP3EDGE_FALLING ®Ú P LPTIM_CCSR_CAP2EDGE_Pos Ú P LPTIM_CCSR_CAP2EDGE_Msk Ú# P LPTIM_CCSR_CAP2EDGE_RISING âÚ$ P LPTIM_CCSR_CAP2EDGE_FALLING ¯Ú P LPTIM_CCSR_CAP1EDGE_Pos Ú P LPTIM_CCSR_CAP1EDGE_Msk Ú# P LPTIM_CCSR_CAP1EDGE_RISING ãÚ$ P LPTIM_CCSR_CAP1EDGE_FALLING °Ú P LPTIM_CCSR_POLAR4_Pos ïÚ P LPTIM_CCSR_POLAR4_Msk öÚ P LPTIM_CCSR_POLAR4_POS /Ú P LPTIM_CCSR_POLAR4_NEG GÚ P LPTIM_CCSR_POLAR3_Pos ðÚ P LPTIM_CCSR_POLAR3_Msk ÷Ú P LPTIM_CCSR_POLAR3_POS 0Ú P LPTIM_CCSR_POLAR3_NEG HÚ P LPTIM_CCSR_POLAR2_Pos ñÚ P LPTIM_CCSR_POLAR2_Msk øÚ P LPTIM_CCSR_POLAR2_POS 1Ú P LPTIM_CCSR_POLAR2_NEG IÚ P LPTIM_CCSR_POLAR1_Pos òÚ P LPTIM_CCSR_POLAR1_Msk ùÚ P LPTIM_CCSR_POLAR1_POS 2Ú P LPTIM_CCSR_POLAR1_NEG JÚ P LPTIM_CCSR_CAPCFG4_Pos ÇÚ P LPTIM_CCSR_CAPCFG4_Msk ÎÚ" P LPTIM_CCSR_CAPCFG4_RISING 'Ú# P LPTIM_CCSR_CAPCFG4_FALLING ôÚ P LPTIM_CCSR_CAPCFG4_BOTH ÊÚ P LPTIM_CCSR_CAPCFG3_Pos ÈÚ P LPTIM_CCSR_CAPCFG3_Msk ÏÚ" P LPTIM_CCSR_CAPCFG3_RISING (Ú# P LPTIM_CCSR_CAPCFG3_FALLING õÚ P LPTIM_CCSR_CAPCFG3_BOTH ËÚ P LPTIM_CCSR_CAPCFG2_Pos ÉÚ P LPTIM_CCSR_CAPCFG2_Msk ÐÚ" P LPTIM_CCSR_CAPCFG2_RISING )Ú# P LPTIM_CCSR_CAPCFG2_FALLING öÚ P LPTIM_CCSR_CAPCFG2_BOTH ÌÚ P LPTIM_CCSR_CAPCFG1_Pos ÊÚ P LPTIM_CCSR_CAPCFG1_Msk ÑÚ" P LPTIM_CCSR_CAPCFG1_RISING *Ú# P LPTIM_CCSR_CAPCFG1_FALLING ÷Ú P LPTIM_CCSR_CAPCFG1_BOTH ÍÚ P LPTIM_CCSR_CC4S_Pos Ú P LPTIM_CCSR_CC4S_Msk Ú P LPTIM_CCSR_CC4S_NON ßÚ# P LPTIM_CCSR_CC4S_LPT_CH4_IN ¸Ú$ P LPTIM_CCSR_CC4S_LPT_CH4_OUT UÚ P LPTIM_CCSR_CC3S_Pos Ú P LPTIM_CCSR_CC3S_Msk Ú P LPTIM_CCSR_CC3S_NON àÚ# P LPTIM_CCSR_CC3S_LPT_CH3_IN ºÚ$ P LPTIM_CCSR_CC3S_LPT_CH3_OUT WÚ P LPTIM_CCSR_CC2S_Pos Ú P LPTIM_CCSR_CC2S_Msk ¡Ú P LPTIM_CCSR_CC2S_NON áÚ# P LPTIM_CCSR_CC2S_LPT_CH2_IN ¼Ú$ P LPTIM_CCSR_CC2S_LPT_CH2_OUT YÚ P LPTIM_CCSR_CC1S_Pos Ú P LPTIM_CCSR_CC1S_Msk ¢Ú P LPTIM_CCSR_CC1S_NON âÚ# P LPTIM_CCSR_CC1S_LPT_CH1_IN ¾Ú$ P LPTIM_CCSR_CC1S_LPT_CH1_OUT [Ú P LPTIM_ARR_ARR_Pos
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Ú P LPTIM_ARR_ARR_Msk Ú P LPTIM_IER_OVR4IE_Pos 5Ú P LPTIM_IER_OVR4IE_Msk <Ú P LPTIM_IER_OVR3IE_Pos 6Ú P LPTIM_IER_OVR3IE_Msk =Ú P LPTIM_IER_OVR2IE_Pos 7Ú P LPTIM_IER_OVR2IE_Msk >Ú P LPTIM_IER_OVR1IE_Pos 8Ú P LPTIM_IER_OVR1IE_Msk ?Ú P LPTIM_IER_TRIGIE_Pos *Ú P LPTIM_IER_TRIGIE_Msk 1Ú P LPTIM_IER_OVIE_Pos ¿Ú P LPTIM_IER_OVIE_Msk ÆÚ P LPTIM_IER_CC4IE_Pos ¨Ú P LPTIM_IER_CC4IE_Msk ¯Ú P LPTIM_IER_CC3IE_Pos ©Ú P LPTIM_IER_CC3IE_Msk °Ú P LPTIM_IER_CC2IE_Pos ªÚ P LPTIM_IER_CC2IE_Msk ±Ú P LPTIM_IER_CC1IE_Pos «Ú P LPTIM_IER_CC1IE_Msk ²Ú P LPTIM_ISR_CAP4OVR_Pos ßÚ P LPTIM_ISR_CAP4OVR_Msk æÚ P LPTIM_ISR_CAP3OVR_Pos àÚ P LPTIM_ISR_CAP3OVR_Msk çÚ P LPTIM_ISR_CAP2OVR_Pos áÚ P LPTIM_ISR_CAP2OVR_Msk èÚ P LPTIM_ISR_CAP1OVR_Pos âÚ P LPTIM_ISR_CAP1OVR_Msk éÚ P LPTIM_ISR_TRIGIF_Pos Ú P LPTIM_ISR_TRIGIF_Msk "Ú P LPTIM_ISR_OVIF_Pos °Ú P LPTIM_ISR_OVIF_Msk ·Ú P LPTIM_ISR_CC4IF_Pos Ú P LPTIM_ISR_CC4IF_Msk Ú P LPTIM_ISR_CC3IF_Pos Ú P LPTIM_ISR_CC3IF_Msk ¡Ú P LPTIM_ISR_CC2IF_Pos Ú P LPTIM_ISR_CC2IF_Msk ¢Ú P LPTIM_ISR_CC1IF_Pos Ú P LPTIM_ISR_CC1IF_Msk £Ú P LPTIM_CR_EN_Pos °Ú P LPTIM_CR_EN_Msk ·Ú P LPTIM_CCR1_CCR1_Pos ¾Ú P LPTIM_CCR1_CCR1_Msk ÅÚ P LPTIM_CCR2_CCR2_Pos ¼Ú P LPTIM_CCR2_CCR2_Msk ÃÚ P LPTIM_CCR3_CCR3_Pos ºÚ P LPTIM_CCR3_CCR3_Msk ÁÚ P LPTIM_CCR4_CCR4_Pos ¸Ú P LPTIM_CCR4_CCR4_Msk ¿Ú LPTIM_Deinit Ú ," NewState Ú$ LPTIM_CFGR_ETR_AFEN_Setable ÉÚ$ LPTIM_CFGR_ETR_AFEN_Getable ÕÚ ,
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SetValue ¦Ú LPTIM_CFGR_PSCSEL_Set Ú LPTIM_CFGR_PSCSEL_Get Ú ,
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SetValue ¦Ú LPTIM_CFGR_DIVSEL_Set Ú LPTIM_CFGR_DIVSEL_Get Ú ,
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SetValue ¦Ú LPTIM_CFGR_EDGESEL_Set ÒÚ LPTIM_CFGR_EDGESEL_Get ÞÚ ,
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SetValue ¦Ú LPTIM_CFGR_TRIGCFG_Set ÅÚ LPTIM_CFGR_TRIGCFG_Get ÑÚ ,
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SetValue ¦Ú LPTIM_CFGR_ONST_Set Ú LPTIM_CFGR_ONST_Get Ú ,
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SetValue ¦Ú LPTIM_CFGR_TMODE_Set VÚ LPTIM_CFGR_TMODE_Get bÚ LPTIM_CNTR_Read ÓÚ ,
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SetValue ¦Ú LPTIM_CCSR_CAP1SSEL_Set Ú LPTIM_CCSR_CAP1SSEL_Get Ú ,
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SetValue ¦Ú LPTIM_CCSR_CAP4EDGE_Set £Ú LPTIM_CCSR_CAP4EDGE_Get ¯Ú ,
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SetValue ¦Ú LPTIM_CCSR_CAP3EDGE_Set ¤Ú LPTIM_CCSR_CAP3EDGE_Get °Ú ,
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SetValue ¦Ú LPTIM_CCSR_CAP2EDGE_Set ¥Ú LPTIM_CCSR_CAP2EDGE_Get ±Ú ,
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SetValue ¦Ú LPTIM_CCSR_CAP1EDGE_Set ¦Ú LPTIM_CCSR_CAP1EDGE_Get ²Ú ,
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SetValue ¦Ú LPTIM_CCSR_POLAR4_Set Ú LPTIM_CCSR_POLAR4_Get Ú ,
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SetValue ¦Ú LPTIM_CCSR_POLAR3_Set Ú LPTIM_CCSR_POLAR3_Get Ú ,
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SetValue ¦Ú LPTIM_CCSR_POLAR2_Set Ú LPTIM_CCSR_POLAR2_Get Ú ,
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SetValue ¦Ú LPTIM_CCSR_POLAR1_Set Ú LPTIM_CCSR_POLAR1_Get !Ú ,
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SetValue ¦Ú LPTIM_CCSR_CAPCFG4_Set êÚ LPTIM_CCSR_CAPCFG4_Get öÚ ,
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SetValue ¦Ú LPTIM_CCSR_CAPCFG3_Set ëÚ LPTIM_CCSR_CAPCFG3_Get ÷Ú ,
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SetValue ¦Ú LPTIM_CCSR_CAPCFG2_Set ìÚ LPTIM_CCSR_CAPCFG2_Get øÚ ,
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SetValue ¦Ú LPTIM_CCSR_CAPCFG1_Set íÚ LPTIM_CCSR_CAPCFG1_Get ùÚ ,
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SetValue ¦Ú LPTIM_CCSR_CC4S_Set »Ú LPTIM_CCSR_CC4S_Get ÇÚ ,
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SetValue ¦Ú LPTIM_CCSR_CC3S_Set ¼Ú LPTIM_CCSR_CC3S_Get ÈÚ ,
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SetValue ¦Ú LPTIM_CCSR_CC2S_Set ½Ú LPTIM_CCSR_CC2S_Get ÉÚ ,
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SetValue ¦Ú LPTIM_CCSR_CC1S_Set ¾Ú LPTIM_CCSR_CC1S_Get ÊÚ ,
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SetValue ¦Ú LPTIM_ARR_Write Ú LPTIM_ARR_Read 'Ú ," NewState Ú! LPTIM_IER_OVR4IE_Setable ¼Ú! LPTIM_IER_OVR4IE_Getable ÈÚ ," NewState Ú! LPTIM_IER_OVR3IE_Setable ½Ú! LPTIM_IER_OVR3IE_Getable ÉÚ ," NewState Ú! LPTIM_IER_OVR2IE_Setable ¾Ú! LPTIM_IER_OVR2IE_Getable ÊÚ ," NewState Ú! LPTIM_IER_OVR1IE_Setable ¿Ú! LPTIM_IER_OVR1IE_Getable ËÚ ," NewState Ú! LPTIM_IER_TRIGIE_Setable ±Ú! LPTIM_IER_TRIGIE_Getable ½Ú ," NewState Ú LPTIM_IER_OVIE_Setable FÚ LPTIM_IER_OVIE_Getable RÚ ," NewState Ú LPTIM_IER_CC4IE_Setable /Ú LPTIM_IER_CC4IE_Getable ;Ú ," NewState Ú LPTIM_IER_CC3IE_Setable 0Ú LPTIM_IER_CC3IE_Getable <Ú ," NewState Ú LPTIM_IER_CC2IE_Setable 1Ú LPTIM_IER_CC2IE_Getable =Ú ," NewState Ú LPTIM_IER_CC1IE_Setable 2Ú LPTIM_IER_CC1IE_Getable >Ú LPTIM_ISR_CAP4OVR_Clr Ú LPTIM_ISR_CAP4OVR_Chk Ú LPTIM_ISR_CAP3OVR_Clr Ú LPTIM_ISR_CAP3OVR_Chk Ú LPTIM_ISR_CAP2OVR_Clr Ú LPTIM_ISR_CAP2OVR_Chk Ú LPTIM_ISR_CAP1OVR_Clr Ú LPTIM_ISR_CAP1OVR_Chk Ú LPTIM_ISR_TRIGIF_Clr IÚ LPTIM_ISR_TRIGIF_Chk TÚ LPTIM_ISR_OVIF_Clr ÞÚ LPTIM_ISR_OVIF_Chk éÚ LPTIM_ISR_CC4IF_Clr ÇÚ LPTIM_ISR_CC4IF_Chk ÒÚ LPTIM_ISR_CC3IF_Clr ÈÚ LPTIM_ISR_CC3IF_Chk ÓÚ LPTIM_ISR_CC2IF_Clr ÉÚ LPTIM_ISR_CC2IF_Chk ÔÚ LPTIM_ISR_CC1IF_Clr ÊÚ LPTIM_ISR_CC1IF_Chk ÕÚ ," NewState Ú LPTIM_CR_EN_Setable 7Ú LPTIM_CR_EN_Getable CÚ ,
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SetValue ¦Ú LPTIM_CCR1_Write pÚ LPTIM_CCR1_Read Ú ,
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SetValue ¦Ú LPTIM_CCR2_Write oÚ LPTIM_CCR2_Read Ú ,
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SetValue ¦Ú LPTIM_CCR3_Write nÚ LPTIM_CCR3_Read ÿÚ ,
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SetValue ¦Ú LPTIM_CCR4_Write mÚ LPTIM_CCR4_Read þÚ P __FM33A0XXEV_WWDT_H æÚ P WWDT_CR_CON_Pos £Ú P WWDT_CR_CON_Msk ªÚ P WWDT_CFGR_CFG_Pos "Ú P WWDT_CFGR_CFG_Msk )Ú P WWDT_CNTR_CNT_Pos øÚ P WWDT_CNTR_CNT_Msk ÿÚ P WWDT_IER_IE_Pos ªÚ P WWDT_IER_IE_Msk ±Ú P WWDT_ISR_NOVF_Pos íÚ P WWDT_ISR_NOVF_Msk ôÚ P WWDT_PSCR_DIV_CNT_Pos Ú P WWDT_PSCR_DIV_CNT_Msk ´Ú WWDT_Deinit ÐÚ ,
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SetValue ¦Ú WWDT_CR_Write *Ú ,
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SetValue ¦Ú WWDT_CFGR_Write Ú WWDT_CFGR_Read *Ú WWDT_CNTR_Read Ú ," NewState Ú WWDT_IER_IE_Setable 1Ú WWDT_IER_IE_Getable =Ú WWDT_ISR_NOVF_Clr Ú WWDT_ISR_NOVF_Chk &Ú WWDT_PSCR_Read Ú P __FM33A0XXEV_SVD_H AÚ 8
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<unnamed> QÚ
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" ý,SVDMOD ÇÚ
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" ý,SVDITVL fÚ
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" ý,SVDLVL ¹Ú "" ý,DFEN fÚ "" ý,PFIE _Ú "" ý,PRIE SÚ "" ý,SVDEN Ú SVD_InitTypeDef RÚ P SVD_CFGR_LVL_Pos _Ú P SVD_CFGR_LVL_Msk fÚ P SVD_CFGR_LVL_1P800V Ú P SVD_CFGR_LVL_2P014V Ú P SVD_CFGR_LVL_2P229V Ú P SVD_CFGR_LVL_2P443V Ú P SVD_CFGR_LVL_2P657V Ú P SVD_CFGR_LVL_2P871V Ú P SVD_CFGR_LVL_3P086V Ú P SVD_CFGR_LVL_3P300V Ú P SVD_CFGR_LVL_3P514V Ú P SVD_CFGR_LVL_3P729V Ú P SVD_CFGR_LVL_3P943V Ú P SVD_CFGR_LVL_4P157V Ú P SVD_CFGR_LVL_4P371V Ú P SVD_CFGR_LVL_4P586V Ú P SVD_CFGR_LVL_4P800V Ú P SVD_CFGR_LVL_SVS Ú P SVD_CFGR_DFEN_Pos .Ú P SVD_CFGR_DFEN_Msk 5Ú P SVD_CFGR_MOD_Pos mÚ P SVD_CFGR_MOD_Msk tÚ P SVD_CFGR_MOD_INTERVAL 0Ú P SVD_CFGR_MOD_ALWAYSON 'Ú P SVD_CFGR_ITVL_Pos Ú P SVD_CFGR_ITVL_Msk Ú P SVD_CFGR_ITVL_62P5MS «Ú P SVD_CFGR_ITVL_256MS ýÚ P SVD_CFGR_ITVL_1S ¼Ú P SVD_CFGR_ITVL_4S ¹Ú P SVD_CR_TE_Pos GÚ P SVD_CR_TE_Msk NÚ P SVD_CR_SVSEN_Pos KÚ P SVD_CR_SVSEN_Msk RÚ P SVD_CR_SVDEN_Pos ZÚ P SVD_CR_SVDEN_Msk aÚ P SVD_IER_PFIE_Pos kÚ P SVD_IER_PFIE_Msk rÚ P SVD_IER_PRIE_Pos _Ú P SVD_IER_PRIE_Msk fÚ P SVD_ISR_SVDO_Pos EÚ P SVD_ISR_SVDO_Msk LÚ P SVD_ISR_SVDR_Pos BÚ P SVD_ISR_SVDR_Msk IÚ P SVD_ISR_PFF_Pos §Ú P SVD_ISR_PFF_Msk ®Ú P SVD_ISR_PRF_Pos Ú P SVD_ISR_PRF_Msk ¢Ú P SVD_VSR_V1P0EN_Pos ÖÚ P SVD_VSR_V1P0EN_Msk ÝÚ P SVD_VSR_V0P95EN_Pos Ú P SVD_VSR_V0P95EN_Msk Ú P SVD_VSR_V0P9EN_Pos ÎÚ P SVD_VSR_V0P9EN_Msk ÕÚ SVD_Deinit +Ú ,
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SetValue ¦Ú SVD_CFGR_LVL_Set Ú SVD_CFGR_LVL_Get Ú ," NewState Ú SVD_CFGR_DFEN_Setable µÚ SVD_CFGR_DFEN_Getable ÁÚ ,
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SetValue ¦Ú SVD_CFGR_MOD_Set Ú SVD_CFGR_MOD_Get Ú ,
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SetValue ¦Ú SVD_CFGR_ITVL_Set /Ú SVD_CFGR_ITVL_Get ;Ú ," NewState Ú SVD_CR_SVSEN_Setable ÒÚ SVD_CR_SVSEN_Getable ÞÚ ," NewState Ú SVD_CR_SVDEN_Setable áÚ SVD_CR_SVDEN_Getable íÚ ," NewState Ú SVD_IER_PFIE_Setable òÚ SVD_IER_PFIE_Getable þÚ ," NewState Ú SVD_IER_PRIE_Setable æÚ SVD_IER_PRIE_Getable òÚ SVD_ISR_SVDO_Chk ~Ú SVD_ISR_SVDR_Chk {Ú SVD_ISR_PFF_Clr ÕÚ SVD_ISR_PFF_Chk àÚ SVD_ISR_PRF_Clr ÉÚ SVD_ISR_PRF_Chk ÔÚ ," NewState Ú SVD_VSR_V1P0EN_Setable ]Ú SVD_VSR_V1P0EN_Getable iÚ ," NewState Ú SVD_VSR_V0P95EN_Setable Ú SVD_VSR_V0P95EN_Getable *Ú ," NewState Ú SVD_VSR_V0P9EN_Setable UÚ SVD_VSR_V0P9EN_Getable aÚ , para %Ú SVD_Init øÚ P __FM33A0XXEV_PAE_H XÚ P ECC_STD_DBL oÚ P ECC_STD_ADD xÚ P ECC_ALG1_DBLADD Ú P ECC_ALG2_ECDBL ÆÚ P ECC_ALG2_ECADDDBL ÷Ú P ECC_ALG2_YRECOVER «Ú P PAE_CSR_DATA_TYPE_Pos ÙÚ P PAE_CSR_DATA_TYPE_Msk àÚ P PAE_CSR_DATA_TYPE_NONE ÙÚ# P PAE_CSR_DATA_TYPE_HALFWORD ªÚ P PAE_CSR_DATA_TYPE_BYTE ÕÚ P PAE_CSR_DATA_TYPE_BIT ,Ú P PAE_CSR_START_Pos Ú P PAE_CSR_START_Msk Ú P PAE_CSR_RUN_MODE_Pos Ú P PAE_CSR_RUN_MODE_Msk $Ú P PAE_CSR_RUN_MODE_MOD oÚ P PAE_CSR_RUN_MODE_DOT hÚ P PAE_CSR_RUN_MODE_RSA iÚ P PAE_CSR_RUN_MODE_ECC Ú P PAE_CSR_SOFT_RST_Pos Ú P PAE_CSR_SOFT_RST_Msk Ú P PAE_CSR_PAEIE_Pos 8Ú P PAE_CSR_PAEIE_Msk ?Ú P PAE_CSR_PAEIE_ENABLE ½Ú P PAE_CSR_PAEIE_DISABLE nÚ P PAE_CSR_PAEIF_Pos 7Ú P PAE_CSR_PAEIF_Msk >Ú P PAE_CSR_BUSY_Pos [Ú P PAE_CSR_BUSY_Msk bÚ P PAE_MLR_PAE_MLR_Pos uÚ P PAE_MLR_PAE_MLR_Msk |Ú P PAE_MPR_PAE_MPR_Pos mÚ P PAE_MPR_PAE_MPR_Msk tÚ P PAE_M0CFG_BLKCFG_Pos Ú P PAE_M0CFG_BLKCFG_Msk Ú! P PAE_M0CFG_BLKCFG_16BLOCK àÚ P PAE_M0CFG_BLKCFG_4BLOCK Ú P PAE_M0CFG_INS_M0_Pos kÚ P PAE_M0CFG_INS_M0_Msk rÚ P PAE_M0CFG_INS_M0_MUL ¯Ú P PAE_M0CFG_INS_M0_ADD ÔÚ P PAE_M0CFG_INS_M0_SUB ³Ú P PAE_M0CFG_RES_BLK_Pos Ú P PAE_M0CFG_RES_BLK_Msk Ú! P PAE_M0CFG_RES_BLK_BLOCK0 Ú! P PAE_M0CFG_RES_BLK_BLOCK1 Ú! P PAE_M0CFG_RES_BLK_BLOCK2 Ú! P PAE_M0CFG_RES_BLK_BLOCK3 Ú! P PAE_M0CFG_RES_BLK_BLOCK4 Ú! P PAE_M0CFG_RES_BLK_BLOCK5 Ú! P PAE_M0CFG_RES_BLK_BLOCK6 Ú! P PAE_M0CFG_RES_BLK_BLOCK7 Ú! P PAE_M0CFG_RES_BLK_BLOCK8 Ú! P PAE_M0CFG_RES_BLK_BLOCK9 Ú" P PAE_M0CFG_RES_BLK_BLOCK10 kÚ" P PAE_M0CFG_RES_BLK_BLOCK11 jÚ" P PAE_M0CFG_RES_BLK_BLOCK12 iÚ" P PAE_M0CFG_RES_BLK_BLOCK13 hÚ" P PAE_M0CFG_RES_BLK_BLOCK14 gÚ" P PAE_M0CFG_RES_BLK_BLOCK15 fÚ P PAE_M0CFG_OP1_BLK_Pos 'Ú P PAE_M0CFG_OP1_BLK_Msk .Ú! P PAE_M0CFG_OP1_BLK_BLOCK0 ¸Ú! P PAE_M0CFG_OP1_BLK_BLOCK1 ·Ú! P PAE_M0CFG_OP1_BLK_BLOCK2 ¶Ú! P PAE_M0CFG_OP1_BLK_BLOCK3 µÚ! P PAE_M0CFG_OP1_BLK_BLOCK4 ´Ú! P PAE_M0CFG_OP1_BLK_BLOCK5 ³Ú! P PAE_M0CFG_OP1_BLK_BLOCK6 ²Ú! P PAE_M0CFG_OP1_BLK_BLOCK7 ±Ú! P PAE_M0CFG_OP1_BLK_BLOCK8 °Ú! P PAE_M0CFG_OP1_BLK_BLOCK9 ¯Ú" P PAE_M0CFG_OP1_BLK_BLOCK10
Ú" P PAE_M0CFG_OP1_BLK_BLOCK11 Ú" P PAE_M0CFG_OP1_BLK_BLOCK12 Ú" P PAE_M0CFG_OP1_BLK_BLOCK13 Ú" P PAE_M0CFG_OP1_BLK_BLOCK14 Ú" P PAE_M0CFG_OP1_BLK_BLOCK15 Ú P PAE_M0CFG_OP2_BLK_Pos &Ú P PAE_M0CFG_OP2_BLK_Msk -Ú! P PAE_M0CFG_OP2_BLK_BLOCK0 ·Ú! P PAE_M0CFG_OP2_BLK_BLOCK1 ¶Ú! P PAE_M0CFG_OP2_BLK_BLOCK2 µÚ! P PAE_M0CFG_OP2_BLK_BLOCK3 ´Ú! P PAE_M0CFG_OP2_BLK_BLOCK4 ³Ú! P PAE_M0CFG_OP2_BLK_BLOCK5 ²Ú! P PAE_M0CFG_OP2_BLK_BLOCK6 ±Ú! P PAE_M0CFG_OP2_BLK_BLOCK7 °Ú! P PAE_M0CFG_OP2_BLK_BLOCK8 ¯Ú! P PAE_M0CFG_OP2_BLK_BLOCK9 ®Ú" P PAE_M0CFG_OP2_BLK_BLOCK10 Ú" P PAE_M0CFG_OP2_BLK_BLOCK11 Ú" P PAE_M0CFG_OP2_BLK_BLOCK12 Ú" P PAE_M0CFG_OP2_BLK_BLOCK13 Ú" P PAE_M0CFG_OP2_BLK_BLOCK14 Ú" P PAE_M0CFG_OP2_BLK_BLOCK15 Ú P PAE_M1CFG_INS_M1_Pos iÚ P PAE_M1CFG_INS_M1_Msk pÚ! P PAE_M1CFG_INS_M1_JACOBIN Ú P PAE_M1CFG_INS_M1_MIXADD ÞÚ P PAE_M1CFG_INS_M1_ECDBL =Ú" P PAE_M1CFG_INS_M1_ECADDDBL nÚ$ P PAE_M1CFG_INS_M1_ECYRECOVER Ú P PAE_M1CFG_AEN3_M1_Pos JÚ P PAE_M1CFG_AEN3_M1_Msk QÚ P PAE_M1CFG_AEN3_M1_NE3 ¶Ú P PAE_M1CFG_AEN3_M1_EQ3 ³Ú# P PAE_M1CFG_BIT_VALUE_M1_Pos Ú# P PAE_M1CFG_BIT_VALUE_M1_Msk Ú& P PAE_M1CFG_BIT_VALUE_M1_VALUE1
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Ú& P PAE_M1CFG_BIT_VALUE_M1_VALUE0 Ú" P PAE_M2CFG_ALWAYS_MULT_Pos ³Ú" P PAE_M2CFG_ALWAYS_MULT_Msk ºÚ% P PAE_M2CFG_ALWAYS_MULT_ALWAYS Ú# P PAE_M2CFG_ALWAYS_MULT_NONE ³Ú P PAE_M2CFG_FBO_M2_Pos zÚ P PAE_M2CFG_FBO_M2_Msk Ú P PAE_M2CFG_FBO_M2_FB1 óÚ P PAE_M2CFG_FBO_M2_NFB1 £Ú P PAE_M3CFG_AEN3_M3_Pos FÚ P PAE_M3CFG_AEN3_M3_Msk MÚ P PAE_M3CFG_AEN3_M3_EQ3 ¯Ú P PAE_M3CFG_AEN3_M3_NE3 ²Ú P PAE_M3CFG_FBO_M3_Pos xÚ P PAE_M3CFG_FBO_M3_Msk Ú P PAE_M3CFG_FBO_M3_FB1 ñÚ P PAE_M3CFG_FBO_M3_NFB1 ¡Ú P PAE_WORD_PAE_WORD_Pos ÏÚ P PAE_WORD_PAE_WORD_Msk ÖÚ PAE_Deinit BÚ ,
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SetValue ¦Ú PAE_CSR_DATA_TYPE_Set üÚ PAE_CSR_DATA_TYPE_Get Ú ," NewState Ú PAE_CSR_START_Setable Ú ,
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SetValue ¦Ú PAE_CSR_RUN_MODE_Set @Ú PAE_CSR_RUN_MODE_Get LÚ ," NewState Ú! PAE_CSR_SOFT_RST_Setable Ú ," NewState Ú PAE_CSR_PAEIE_Setable ¿Ú PAE_CSR_PAEIE_Getable ËÚ PAE_CSR_PAEIF_Clr eÚ PAE_CSR_PAEIF_Chk pÚ PAE_CSR_BUSY_Chk Ú ,
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SetValue ¦Ú PAE_MLR_Write DÚ PAE_MLR_Read ÕÚ ,
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SetValue ¦Ú PAE_MPR_Write @Ú ,
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SetValue ¦Ú PAE_M0CFG_BLKCFG_Set «Ú PAE_M0CFG_BLKCFG_Get ·Ú ,
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SetValue ¦Ú PAE_M0CFG_INS_M0_Set Ú PAE_M0CFG_INS_M0_Get Ú ,
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SetValue ¦Ú PAE_M0CFG_RES_BLK_Set 0Ú PAE_M0CFG_RES_BLK_Get <Ú ,
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SetValue ¦Ú PAE_M0CFG_OP1_BLK_Set JÚ PAE_M0CFG_OP1_BLK_Get VÚ ,
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SetValue ¦Ú PAE_M0CFG_OP2_BLK_Set IÚ PAE_M0CFG_OP2_BLK_Get UÚ ,
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SetValue ¦Ú PAE_M1CFG_INS_M1_Set Ú PAE_M1CFG_INS_M1_Get Ú ,
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SetValue ¦Ú PAE_M1CFG_AEN3_M1_Set mÚ PAE_M1CFG_AEN3_M1_Get yÚ ,
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SetValue ¦Ú# PAE_M1CFG_BIT_VALUE_M1_Set ¯Ú ,
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SetValue ¦Ú# PAE_M1CFG_BIT_VALUE_M1_Get »Ú ,
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SetValue ¦Ú" PAE_M2CFG_ALWAYS_MULT_Set ÖÚ" PAE_M2CFG_ALWAYS_MULT_Get âÚ ,
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SetValue ¦Ú PAE_M2CFG_FBO_M2_Set Ú PAE_M2CFG_FBO_M2_Get ©Ú ,
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SetValue ¦Ú PAE_M3CFG_AEN3_M3_Set iÚ PAE_M3CFG_AEN3_M3_Get uÚ ,
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SetValue ¦Ú PAE_M3CFG_FBO_M3_Set Ú PAE_M3CFG_FBO_M3_Get §Ú ,
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SetValue ¦Ú PAE_WORD_Write ñÚ P __FM33A0XXEV_HASH_H Ú P HASH_CSR_START_Pos ¾Ú P HASH_CSR_START_Msk ÅÚ P HASH_CSR_BUSY_Pos Ú P HASH_CSR_BUSY_Msk Ú P HASH_CSR_HASHSEL_Pos @Ú P HASH_CSR_HASHSEL_Msk GÚ P HASH_CSR_HASHSEL_SHA256 óÚ P HASH_CSR_HASHSEL_SHA1 cÚ P HASH_DTR_DATA_TYPE_Pos Ú P HASH_DTR_DATA_TYPE_Msk Ú P HASH_DTR_DATA_TYPE_NONE Ú$ P HASH_DTR_DATA_TYPE_HALFWORD XÚ P HASH_DTR_DATA_TYPE_BYTE Ú P HASH_DTR_DATA_TYPE_BIT ÚÚ HASH_Deinit òÚ ," NewState Ú HASH_CSR_START_Setable EÚ HASH_CSR_START_Getable QÚ ,
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SetValue ¦Ú HASH_CSR_HASHSEL_Set cÚ HASH_CSR_HASHSEL_Get oÚ ,
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SetValue ¦Ú HASH_DTR_DATA_TYPE_Set ªÚ HASH_DTR_DATA_TYPE_Get ¶Ú P __FM33A0XXEV_QSPI_H ïÚ 8
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<unnamed> QÚ
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" À/ Instruction "Ú
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" À/Address Ú
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" À/AlternateByte Ú
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" À/ AddressSize cÚ
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" À/AlternateByteSize éÚ
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" À/ DummyCycles UÚ
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" À/InstructionMode Ú
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" À/ AddressMode yÚ
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" À/AlternateByteMode ÿÚ
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" À/ DataMode ËÚ QSPI_CmdTypeDef Ú P QSPI_CR_PRESCALER_Pos ßÚ P QSPI_CR_PRESCALER_Msk æÚ P QSPI_CR_PMM_Pos ¢Ú P QSPI_CR_PMM_Msk ©Ú P QSPI_CR_PMM_AND Ú P QSPI_CR_PMM_OR 5Ú P QSPI_CR_TOIE_Pos YÚ P QSPI_CR_TOIE_Msk `Ú P QSPI_CR_SMIE_Pos \Ú P QSPI_CR_SMIE_Msk cÚ P QSPI_CR_FTIE_Pos bÚ P QSPI_CR_FTIE_Msk iÚ P QSPI_CR_TCIE_Pos eÚ P QSPI_CR_TCIE_Msk lÚ P QSPI_CR_TEIE_Pos cÚ P QSPI_CR_TEIE_Msk jÚ P QSPI_CR_FIFOTHR_Pos rÚ P QSPI_CR_FIFOTHR_Msk yÚ P QSPI_CR_FIFOTHR_1 wÚ P QSPI_CR_FIFOTHR_2 vÚ P QSPI_CR_FIFOTHR_3 uÚ P QSPI_CR_FIFOTHR_4 tÚ P QSPI_CR_FIFOTHR_5 sÚ P QSPI_CR_FIFOTHR_6 rÚ P QSPI_CR_FIFOTHR_7 qÚ P QSPI_CR_FIFOTHR_8 pÚ P QSPI_CR_FIFOTHR_9 oÚ P QSPI_CR_FIFOTHR_10 EÚ P QSPI_CR_FIFOTHR_11 DÚ P QSPI_CR_FIFOTHR_12 CÚ P QSPI_CR_FIFOTHR_13 BÚ P QSPI_CR_FIFOTHR_14 AÚ P QSPI_CR_FIFOTHR_15 @Ú P QSPI_CR_FIFOTHR_16 ?Ú P QSPI_CR_SSHFT_Pos Ú P QSPI_CR_SSHFT_Msk Ú P QSPI_CR_TCEN_Pos `Ú P QSPI_CR_TCEN_Msk gÚ P QSPI_CR_DMAEN_Pos #Ú P QSPI_CR_DMAEN_Msk *Ú P QSPI_CR_ABORT_Pos Ú P QSPI_CR_ABORT_Msk Ú P QSPI_CR_EN_Pos ûÚ P QSPI_CR_EN_Msk Ú P QSPI_CFG_CSHT_Pos Ú P QSPI_CFG_CSHT_Msk "Ú P QSPI_CFG_CSHT_1CYCLE ¦Ú P QSPI_CFG_CSHT_2CYCLES PÚ P QSPI_CFG_CSHT_3CYCLES OÚ P QSPI_CFG_CSHT_4CYCLES NÚ P QSPI_CFG_CSHT_5CYCLES MÚ P QSPI_CFG_CSHT_6CYCLES LÚ P QSPI_CFG_CSHT_7CYCLES KÚ P QSPI_CFG_CSHT_8CYCLES JÚ P QSPI_CFG_CKMODE_Pos Ú P QSPI_CFG_CKMODE_Msk Ú P QSPI_CFG_CKMODE_MODE0 oÚ P QSPI_CFG_CKMODE_MODE3 lÚ P QSPI_SR_FIFOLVL_Pos bÚ P QSPI_SR_FIFOLVL_Msk iÚ P QSPI_SR_BUSY_Pos 7Ú P QSPI_SR_BUSY_Msk >Ú P QSPI_SR_TOF_Pos Ú P QSPI_SR_TOF_Msk Ú P QSPI_SR_SMF_Pos Ú P QSPI_SR_SMF_Msk Ú P QSPI_SR_FTF_Pos Ú P QSPI_SR_FTF_Msk £Ú P QSPI_SR_TCF_Pos Ú P QSPI_SR_TCF_Msk ¦Ú& P QSPI_DATALEN_QSPI_DATALEN_Pos wÚ& P QSPI_DATALEN_QSPI_DATALEN_Msk ~Ú P QSPI_CCR_CRM_Pos eÚ P QSPI_CCR_CRM_Msk lÚ P QSPI_CCR_CRM_ALWAYS ÀÚ P QSPI_CCR_CRM_ONLY SÚ P QSPI_CCR_OPMODE_Pos }Ú P QSPI_CCR_OPMODE_Msk Ú P QSPI_CCR_OPMODE_WRITE Ú P QSPI_CCR_OPMODE_READ Ú P QSPI_CCR_OPMODE_QUERY Ú P QSPI_CCR_OPMODE_MAP ÑÚ P QSPI_CCR_DMODE_Pos ÚÚ P QSPI_CCR_DMODE_Msk áÚ P QSPI_CCR_DMODE_NONE ÚÚ P QSPI_CCR_DMODE_SINGLE DÚ P QSPI_CCR_DMODE_DOUBLE KÚ P QSPI_CCR_DMODE_FOUR ÎÚ P QSPI_CCR_DUMCYC_Pos |Ú P QSPI_CCR_DUMCYC_Msk Ú P QSPI_CCR_ABSIZE_Pos Ú P QSPI_CCR_ABSIZE_Msk Ú P QSPI_CCR_ABSIZE_8BITS GÚ P QSPI_CCR_ABSIZE_16BITS Ú P QSPI_CCR_ABSIZE_24BITS Ú P QSPI_CCR_ABSIZE_32BITS Ú P QSPI_CCR_ABMODE_Pos Ú P QSPI_CCR_ABMODE_Msk Ú P QSPI_CCR_ABMODE_NONE Ú P QSPI_CCR_ABMODE_SINGLE Ú P QSPI_CCR_ABMODE_DOUBLE
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Ú P QSPI_CCR_ABMODE_FOUR Ú P QSPI_CCR_ADSIZE_Pos Ú P QSPI_CCR_ADSIZE_Msk Ú P QSPI_CCR_ADSIZE_8BITS EÚ P QSPI_CCR_ADSIZE_16BITS Ú P QSPI_CCR_ADSIZE_24BITS Ú P QSPI_CCR_ADSIZE_32BITS Ú P QSPI_CCR_ADMODE_Pos Ú P QSPI_CCR_ADMODE_Msk Ú P QSPI_CCR_ADMODE_NONE Ú P QSPI_CCR_ADMODE_SINGLE Ú P QSPI_CCR_ADMODE_DOUBLE Ú P QSPI_CCR_ADMODE_FOUR Ú P QSPI_CCR_IMODE_Pos ÕÚ P QSPI_CCR_IMODE_Msk ÜÚ P QSPI_CCR_IMODE_NONE ÕÚ P QSPI_CCR_IMODE_SINGLE ?Ú P QSPI_CCR_IMODE_DOUBLE FÚ P QSPI_CCR_IMODE_FOUR ÉÚ! P QSPI_CCR_INSTRUCTION_Pos ÕÚ! P QSPI_CCR_INSTRUCTION_Msk ÜÚ P QSPI_ADDR_QSPI_ADDR_Pos ?Ú P QSPI_ADDR_QSPI_ADDR_Msk FÚ P QSPI_ABR_QSPI_ABR_Pos ÏÚ P QSPI_ABR_QSPI_ABR_Msk ÖÚ P QSPI_DR_QSPI_DATA_Pos ÉÚ P QSPI_DR_QSPI_DATA_Msk ÐÚ P QSPI_SMSK_QSPI_SMSK_Pos ùÚ P QSPI_SMSK_QSPI_SMSK_Msk Ú P QSPI_SMAT_QSPI_SMAT_Pos Ú P QSPI_SMAT_QSPI_SMAT_Msk Ú P QSPI_PITV_QSPI_PITV_Pos ïÚ P QSPI_PITV_QSPI_PITV_Msk öÚ P QSPI_TO_QSPI_TO_Pos 7Ú P QSPI_TO_QSPI_TO_Msk >Ú QSPI_Deinit ÙÚ ,
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SetValue ¦Ú QSPI_CR_PRESCALER_Set Ú QSPI_CR_PRESCALER_Get Ú ,
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SetValue ¦Ú QSPI_CR_PMM_Set ÅÚ QSPI_CR_PMM_Get ÑÚ ," NewState Ú QSPI_CR_TOIE_Setable àÚ QSPI_CR_TOIE_Getable ìÚ ," NewState Ú QSPI_CR_SMIE_Setable ãÚ QSPI_CR_SMIE_Getable ïÚ ," NewState Ú QSPI_CR_FTIE_Setable éÚ QSPI_CR_FTIE_Getable õÚ ," NewState Ú QSPI_CR_TCIE_Setable ìÚ QSPI_CR_TCIE_Getable øÚ ," NewState Ú QSPI_CR_TEIE_Setable êÚ QSPI_CR_TEIE_Getable öÚ ,
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SetValue ¦Ú QSPI_CR_FIFOTHR_Set Ú QSPI_CR_FIFOTHR_Get ¡Ú ," NewState Ú QSPI_CR_SSHFT_Setable Ú QSPI_CR_SSHFT_Getable Ú ," NewState Ú QSPI_CR_TCEN_Setable çÚ QSPI_CR_TCEN_Getable óÚ ," NewState Ú QSPI_CR_DMAEN_Setable ªÚ QSPI_CR_DMAEN_Getable ¶Ú ," NewState Ú QSPI_CR_ABORT_Setable Ú QSPI_CR_ABORT_Getable £Ú ," NewState Ú QSPI_CR_EN_Setable Ú QSPI_CR_EN_Getable Ú ,
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SetValue ¦Ú QSPI_CFG_CSHT_Set >Ú QSPI_CFG_CSHT_Get JÚ ,
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SetValue ¦Ú QSPI_CFG_CKMODE_Set ¹Ú QSPI_CFG_CKMODE_Get ÅÚ QSPI_SR_FIFOLVL_Get Ú QSPI_SR_BUSY_Chk pÚ QSPI_SR_TOF_Clr ÁÚ QSPI_SR_TOF_Chk ÌÚ QSPI_SR_SMF_Clr ÄÚ QSPI_SR_SMF_Chk ÏÚ QSPI_SR_FTF_Chk ÕÚ QSPI_SR_TCF_Clr ÍÚ QSPI_SR_TCF_Chk ØÚ ,
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SetValue ¦Ú QSPI_DATALEN_Write ÅÚ QSPI_DATALEN_Read VÚ P QSPI_CCR_DUMCYC_SET ÂÚ P QSPI_CCR_DUMCYC_GET ÎÚ! P QSPI_CCR_INSTRUCTION_SET Ú! P QSPI_CCR_INSTRUCTION_GET 'Ú ,
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SetValue ¦Ú QSPI_CCR_Write îÚ QSPI_CCR_Read Ú ,
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SetValue ¦Ú QSPI_ADDR_Write ©Ú QSPI_ADDR_Read :Ú ,
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SetValue ¦Ú QSPI_ABR_Write ñÚ QSPI_ABR_Read Ú , SetValue Ú QSPI_DR_WriteByte Ú QSPI_DR_ReadByte 'Ú , SetValue ¤Ú QSPI_DR_WriteHalfword ëÚ QSPI_DR_ReadHalfword |Ú ,
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SetValue ¦Ú QSPI_DR_WriteWord Ú QSPI_DR_ReadWord Ú ,
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SetValue ¦Ú QSPI_SMSK_Write Ú QSPI_SMSK_Read Ú ,
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SetValue ¦Ú QSPI_SMAT_Write Ú QSPI_SMAT_Read Ú ,
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SetValue ¦Ú QSPI_PITV_Write Ú QSPI_PITV_Read Ú ,
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SetValue ¦Ú QSPI_TO_Write %Ú QSPI_TO_Read ¶Ú
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QSPI_Init ¦Ú P __FM33A0XXEV_BT_H Ú P BTx_CR1_CHEN_Pos jÚ P BTx_CR1_CHEN_Msk qÚ P BTx_CR1_CLEN_Pos fÚ P BTx_CR1_CLEN_Msk mÚ P BTx_CR1_MODE_Pos cÚ P BTx_CR1_MODE_Msk jÚ P BTx_CR1_MODE_CAPTURE yÚ P BTx_CR1_MODE_COUNTER mÚ P BTx_CR1_EDGESEL_Pos Ú P BTx_CR1_EDGESEL_Msk Ú P BTx_CR1_EDGESEL_FALLING ¶Ú P BTx_CR1_EDGESEL_RISING éÚ P BTx_CR1_CAPMOD_Pos ÐÚ P BTx_CR1_CAPMOD_Msk ×Ú P BTx_CR1_CAPMOD_PULSE uÚ P BTx_CR1_CAPMOD_CYCLE Ú P BTx_CR1_CAPCLR_Pos ÏÚ P BTx_CR1_CAPCLR_Msk ÖÚ P BTx_CR1_CAPONCE_Pos Ú P BTx_CR1_CAPONCE_Msk Ú P BTx_CR1_CAPONCE_SINGLE óÚ! P BTx_CR1_CAPONCE_CONTINUE LÚ P BTx_CR1_PWM_Pos Ú P BTx_CR1_PWM_Msk Ú P BTx_CR2_SIG2SEL_Pos Ú P BTx_CR2_SIG2SEL_Msk Ú P BTx_CR2_SIG2SEL_GROUP2 õÚ P BTx_CR2_SIG2SEL_GROUP1 öÚ P BTx_CR2_SIG1SEL_Pos Ú P BTx_CR2_SIG1SEL_Msk Ú P BTx_CR2_SIG1SEL_GROUP1 ÷Ú P BTx_CR2_SIG1SEL_GROUP2 öÚ P BTx_CR2_CNTHSEL_Pos pÚ P BTx_CR2_CNTHSEL_Msk wÚ P BTx_CR2_CNTHSEL_COUNTER zÚ P BTx_CR2_CNTHSEL_CAPTURE Ú P BTx_CR2_CNTHSEL_INNER "Ú P BTx_CR2_DIREN_Pos Ú P BTx_CR2_DIREN_Msk Ú P BTx_CR2_STDIR_Pos ÿÚ P BTx_CR2_STDIR_Msk Ú P BTx_CR2_SRCSEL_Pos ·Ú P BTx_CR2_SRCSEL_Msk ¾Ú P BTx_CR2_DIRPO_Pos Ú P BTx_CR2_DIRPO_Msk Ú P BTx_CR2_DIRPO_REVERSE Ú P BTx_CR2_DIRPO_NON NÚ P BTx_CFGR1_RTCSEL2_Pos òÚ P BTx_CFGR1_RTCSEL2_Msk ùÚ" P BTx_CFGR1_RTCSEL2_32768HZ pÚ" P BTx_CFGR1_RTCSEL2_RTC_SEC ùÚ" P BTx_CFGR1_RTCSEL2_RTC_MIN ðÚ P BTx_CFGR1_RTCSEL1_Pos óÚ P BTx_CFGR1_RTCSEL1_Msk úÚ" P BTx_CFGR1_RTCSEL1_32768HZ qÚ" P BTx_CFGR1_RTCSEL1_RTC_SEC úÚ" P BTx_CFGR1_RTCSEL1_RTC_MIN ñÚ P BTx_CFGR1_GRP2SEL_Pos òÚ P BTx_CFGR1_GRP2SEL_Msk ùÚ! P BTx_CFGR1_GRP2SEL_APBCLK qÚ" P BTx_CFGR1_GRP2SEL_RTCOUT2 Ú" P BTx_CFGR1_GRP2SEL_IN_SIG2 Ú" P BTx_CFGR1_GRP2SEL_EX_SIG2 Ú P BTx_CFGR1_GRP1SEL_Pos óÚ P BTx_CFGR1_GRP1SEL_Msk úÚ! P BTx_CFGR1_GRP1SEL_APBCLK rÚ" P BTx_CFGR1_GRP1SEL_RTCOUT1 Ú" P BTx_CFGR1_GRP1SEL_IN_SIG1 Ú" P BTx_CFGR1_GRP1SEL_EX_SIG1 Ú P BTx_CFGR2_EXSEL2_Pos ?Ú P BTx_CFGR2_EXSEL2_Msk FÚ P BTx_CFGR2_EXSEL2_IN0 ªÚ P BTx_CFGR2_EXSEL2_IN1 ©Ú P BTx_CFGR2_EXSEL2_IN2 ¨Ú P BTx_CFGR2_EXSEL2_IN3 §Ú P BTx_CFGR2_EXSEL1_Pos @Ú P BTx_CFGR2_EXSEL1_Msk GÚ P BTx_CFGR2_EXSEL1_IN0 «Ú P BTx_CFGR2_EXSEL1_IN1 ªÚ P BTx_CFGR2_EXSEL1_IN2 ©Ú P BTx_CFGR2_EXSEL1_IN3 ¨Ú P BTx_CFGR2_INSEL2_Pos EÚ P BTx_CFGR2_INSEL2_Msk LÚ P BTx_CFGR2_INSEL2_RX3 Ú P BTx_CFGR2_INSEL2_RX4 Ú P BTx_CFGR2_INSEL2_RX5 Ú P BTx_CFGR2_INSEL2_RCLP DÚ P BTx_CFGR2_INSEL1_Pos FÚ P BTx_CFGR2_INSEL1_Msk MÚ P BTx_CFGR2_INSEL1_RX0 Ú P BTx_CFGR2_INSEL1_RX1 Ú P BTx_CFGR2_INSEL1_RX2 Ú P BTx_CFGR2_INSEL1_RCLP EÚ P BTx_PRES_PRESCALE_Pos »Ú P BTx_PRES_PRESCALE_Msk ÂÚ P BTx_LOADCR_LHEN_Pos lÚ P BTx_LOADCR_LHEN_Msk sÚ P BTx_LOADCR_LLEN_Pos hÚ P BTx_LOADCR_LLEN_Msk oÚ P BTx_CNTL_CNTL_Pos êÚ P BTx_CNTL_CNTL_Msk ñÚ P BTx_CNTH_CNTH_Pos òÚ P BTx_CNTH_CNTH_Msk ùÚ P BTx_PRESET_PRESETH_Pos TÚ P BTx_PRESET_PRESETH_Msk [Ú P BTx_PRESET_PRESETL_Pos PÚ P BTx_PRESET_PRESETL_Msk WÚ P BTx_LOADL_LOADL_Pos pÚ P BTx_LOADL_LOADL_Msk wÚ P BTx_LOADH_LOADH_Pos xÚ P BTx_LOADH_LOADH_Msk Ú P BTx_CMPL_CMPL_Pos ôÚ P BTx_CMPL_CMPL_Msk ûÚ P BTx_CMPH_CMPH_Pos üÚ P BTx_CMPH_CMPH_Msk Ú P BTx_OUTCNT_OUTCNT_Pos Ú P BTx_OUTCNT_OUTCNT_Msk Ú P BTx_OCR_OUTCLR_Pos Ú P BTx_OCR_OUTCLR_Msk Ú P BTx_OCR_OUTCLR_INVALID °Ú P BTx_OCR_OUTCLR_CLEAR TÚ P BTx_OCR_OUTINV_Pos Ú P BTx_OCR_OUTINV_Msk Ú P BTx_OCR_OUTINV_NORMAL äÚ P BTx_OCR_OUTINV_REVERSE Ú P BTx_OCR_OUTMOD_Pos Ú P BTx_OCR_OUTMOD_Msk Ú# P BTx_OCR_OUTMOD_PULSE_SHIFT JÚ P BTx_OCR_OUTMOD_NEG æÚ P BTx_OCR_OUTSEL_Pos Ú P BTx_OCR_OUTSEL_Msk Ú P BTx_OCR_OUTSEL_HIGH Ú P BTx_OCR_OUTSEL_LOW ÊÚ P BTx_OCR_OUTSEL_GROUP1 øÚ P BTx_OCR_OUTSEL_GROUP2 ÷Ú P BTx_OCR_OUTSEL_PWM ÈÚ P BTx_IER_CMPHIE_Pos ´Ú P BTx_IER_CMPHIE_Msk »Ú P BTx_IER_CMPLIE_Pos °Ú P BTx_IER_CMPLIE_Msk ·Ú P BTx_IER_OVHIE_Pos ñÚ P BTx_IER_OVHIE_Msk øÚ P BTx_IER_OVLIE_Pos íÚ P BTx_IER_OVLIE_Msk ôÚ P BTx_IER_CAPIE_Pos
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Ú P BTx_IER_CAPIE_Msk Ú P BTx_ISR_EDGESTA_Pos ]Ú P BTx_ISR_EDGESTA_Msk dÚ P BTx_ISR_CMPHIF_Pos ¥Ú P BTx_ISR_CMPHIF_Msk ¬Ú P BTx_ISR_CMPLIF_Pos ¡Ú P BTx_ISR_CMPLIF_Msk ¨Ú P BTx_ISR_OVHIF_Pos âÚ P BTx_ISR_OVHIF_Msk éÚ P BTx_ISR_OVLIF_Pos ÞÚ P BTx_ISR_OVLIF_Msk åÚ P BTx_ISR_CAPIF_Pos ûÚ P BTx_ISR_CAPIF_Msk Ú , BTx ½Ú BTx_Deinit
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Ú , BTx ½Ú ," NewState Ú BTx_CR1_CHEN_Setable ñÚ , BTx ½Ú BTx_CR1_CHEN_Getable ýÚ , BTx ½Ú ," NewState Ú BTx_CR1_CLEN_Setable íÚ , BTx ½Ú BTx_CR1_CLEN_Getable ùÚ , BTx ½Ú ,
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SetValue ¦Ú BTx_CR1_MODE_Set Ú , BTx ½Ú BTx_CR1_MODE_Get Ú , BTx ½Ú ,
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SetValue ¦Ú BTx_CR1_EDGESEL_Set ¬Ú , BTx ½Ú BTx_CR1_EDGESEL_Get ¸Ú , BTx ½Ú ,
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SetValue ¦Ú BTx_CR1_CAPMOD_Set óÚ , BTx ½Ú BTx_CR1_CAPMOD_Get ÿÚ , BTx ½Ú ," NewState Ú BTx_CR1_CAPCLR_Setable VÚ , BTx ½Ú BTx_CR1_CAPCLR_Getable bÚ , BTx ½Ú ,
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SetValue ¦Ú BTx_CR1_CAPONCE_Set ¬Ú , BTx ½Ú BTx_CR1_CAPONCE_Get ¸Ú , BTx ½Ú ," NewState Ú BTx_CR1_PWM_Setable Ú , BTx ½Ú BTx_CR1_PWM_Getable )Ú , BTx ½Ú ,
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SetValue ¦Ú BTx_CR2_SIG2SEL_Set «Ú , BTx ½Ú BTx_CR2_SIG2SEL_Get ·Ú , BTx ½Ú ,
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SetValue ¦Ú BTx_CR2_SIG1SEL_Set ¬Ú , BTx ½Ú BTx_CR2_SIG1SEL_Get ¸Ú , BTx ½Ú ,
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SetValue ¦Ú BTx_CR2_CNTHSEL_Set Ú , BTx ½Ú BTx_CR2_CNTHSEL_Get Ú , BTx ½Ú ," NewState Ú BTx_CR2_DIREN_Setable Ú , BTx ½Ú BTx_CR2_DIREN_Getable ¦Ú , BTx ½Ú ," NewState Ú BTx_CR2_STDIR_Setable Ú , BTx ½Ú BTx_CR2_STDIR_Getable Ú , BTx ½Ú ," NewState Ú BTx_CR2_SRCSEL_Setable >Ú , BTx ½Ú BTx_CR2_SRCSEL_Getable JÚ , BTx ½Ú ,
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SetValue ¦Ú BTx_CR2_DIRPO_Set *Ú , BTx ½Ú BTx_CR2_DIRPO_Get 6Ú , BTx ½Ú ,
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SetValue ¦Ú BTx_CFGR1_RTCSEL2_Set Ú , BTx ½Ú BTx_CFGR1_RTCSEL2_Get !Ú , BTx ½Ú ,
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SetValue ¦Ú BTx_CFGR1_RTCSEL1_Set Ú , BTx ½Ú BTx_CFGR1_RTCSEL1_Get "Ú , BTx ½Ú ,
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SetValue ¦Ú BTx_CFGR1_GRP2SEL_Set Ú , BTx ½Ú BTx_CFGR1_GRP2SEL_Get !Ú , BTx ½Ú ,
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SetValue ¦Ú BTx_CFGR1_GRP1SEL_Set Ú , BTx ½Ú BTx_CFGR1_GRP1SEL_Get "Ú , BTx ½Ú ,
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SetValue ¦Ú BTx_CFGR2_EXSEL2_Set bÚ , BTx ½Ú BTx_CFGR2_EXSEL2_Get nÚ , BTx ½Ú ,
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SetValue ¦Ú BTx_CFGR2_EXSEL1_Set cÚ , BTx ½Ú BTx_CFGR2_EXSEL1_Get oÚ , BTx ½Ú ,
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SetValue ¦Ú BTx_CFGR2_INSEL2_Set hÚ , BTx ½Ú BTx_CFGR2_INSEL2_Get tÚ , BTx ½Ú ,
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SetValue ¦Ú BTx_CFGR2_INSEL1_Set iÚ , BTx ½Ú BTx_CFGR2_INSEL1_Get uÚ , BTx ½Ú ,
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SetValue ¦Ú BTx_PRES_Write »Ú , BTx ½Ú BTx_PRES_Read LÚ , BTx ½Ú ," NewState Ú BTx_LOADCR_LHEN_Setable óÚ , BTx ½Ú BTx_LOADCR_LHEN_Getable ÿÚ , BTx ½Ú ," NewState Ú BTx_LOADCR_LLEN_Setable ïÚ , BTx ½Ú BTx_LOADCR_LLEN_Getable ûÚ , BTx ½Ú BTx_CNTL_Read UÚ , BTx ½Ú BTx_CNTH_Read YÚ , BTx ½Ú ,
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SetValue ¦Ú BTx_PRESET_PRESETH_Set wÚ , BTx ½Ú BTx_PRESET_PRESETH_Get Ú , BTx ½Ú ,
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SetValue ¦Ú BTx_PRESET_PRESETL_Set sÚ , BTx ½Ú BTx_PRESET_PRESETL_Get Ú , BTx ½Ú ,
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SetValue ¦Ú BTx_LOADL_Write Ú , BTx ½Ú BTx_LOADL_Read Ú , BTx ½Ú ,
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SetValue ¦Ú BTx_LOADH_Write Ú , BTx ½Ú BTx_LOADH_Read Ú , BTx ½Ú ,
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SetValue ¦Ú BTx_CMPL_Write ÉÚ , BTx ½Ú BTx_CMPL_Read ZÚ , BTx ½Ú ,
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SetValue ¦Ú BTx_CMPH_Write ÍÚ , BTx ½Ú BTx_CMPH_Read ^Ú , BTx ½Ú ,
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SetValue ¦Ú BTx_OUTCNT_Write Ú , BTx ½Ú BTx_OUTCNT_Read ¥Ú , BTx ½Ú ,
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SetValue ¦Ú BTx_OCR_OUTCLR_Set °Ú , BTx ½Ú BTx_OCR_OUTCLR_Get ¼Ú , BTx ½Ú ,
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SetValue ¦Ú BTx_OCR_OUTINV_Set ¤Ú , BTx ½Ú BTx_OCR_OUTINV_Get °Ú , BTx ½Ú ,
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SetValue ¦Ú BTx_OCR_OUTMOD_Set ±Ú , BTx ½Ú BTx_OCR_OUTMOD_Get ½Ú , BTx ½Ú ,
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SetValue ¦Ú BTx_OCR_OUTSEL_Set Ú , BTx ½Ú BTx_OCR_OUTSEL_Get ¹Ú , BTx ½Ú ," NewState Ú BTx_IER_CMPHIE_Setable ;Ú , BTx ½Ú BTx_IER_CMPHIE_Getable GÚ , BTx ½Ú ," NewState Ú BTx_IER_CMPLIE_Setable 7Ú , BTx ½Ú BTx_IER_CMPLIE_Getable CÚ , BTx ½Ú ," NewState Ú BTx_IER_OVHIE_Setable xÚ , BTx ½Ú BTx_IER_OVHIE_Getable Ú , BTx ½Ú ," NewState Ú BTx_IER_OVLIE_Setable tÚ , BTx ½Ú BTx_IER_OVLIE_Getable Ú , BTx ½Ú ," NewState Ú BTx_IER_CAPIE_Setable Ú , BTx ½Ú BTx_IER_CAPIE_Getable Ú , BTx ½Ú BTx_ISR_EDGESTA_Chk Ú , BTx ½Ú BTx_ISR_CMPHIF_Clr ÓÚ , BTx ½Ú BTx_ISR_CMPHIF_Chk ÞÚ , BTx ½Ú BTx_ISR_CMPLIF_Clr ÏÚ , BTx ½Ú BTx_ISR_CMPLIF_Chk ÚÚ , BTx ½Ú BTx_ISR_OVHIF_Clr Ú , BTx ½Ú BTx_ISR_OVHIF_Chk Ú , BTx ½Ú BTx_ISR_OVLIF_Clr Ú , BTx ½Ú BTx_ISR_OVLIF_Chk Ú , BTx ½Ú BTx_ISR_CAPIF_Clr )Ú , BTx ½Ú BTx_ISR_CAPIF_Chk 4Ú P __FM33A0XXEV_ET_H Ú P ETx_CR_OPOL_Pos ~Ú P ETx_CR_OPOL_Msk
Ú P ETx_CR_OPOL_NORMAL áÚ P ETx_CR_OPOL_REVERSE Ú P ETx_CR_EXFLT_Pos 3Ú P ETx_CR_EXFLT_Msk :Ú P ETx_CR_EXFLT_OPEN 1Ú P ETx_CR_EXFLT_CLOSE ëÚ P ETx_CR_PWM_Pos ÆÚ P ETx_CR_PWM_Msk ÍÚ P ETx_CR_CEN_Pos äÚ P ETx_CR_CEN_Msk ëÚ P ETx_CR_MOD_Pos ÚÚ P ETx_CR_MOD_Msk áÚ P ETx_CR_MOD_CAPTURE ðÚ P ETx_CR_MOD_COUNTER äÚ P ETx_CR_CASEN_Pos LÚ P ETx_CR_CASEN_Msk SÚ P ETx_CR_CASEN_32BITS áÚ P ETx_CR_CASEN_16BITS ßÚ P ETx_CR_EDGESEL_Pos ¹Ú P ETx_CR_EDGESEL_Msk ÀÚ P ETx_CR_EDGESEL_FALLING æÚ P ETx_CR_EDGESEL_RISING Ú P ETx_CR_CAPMOD_Pos Ú P ETx_CR_CAPMOD_Msk Ú P ETx_CR_CAPMOD_PULSE ¥Ú P ETx_CR_CAPMOD_CYCLE ¾Ú P ETx_CR_CAPCLR_Pos ÿÚ P ETx_CR_CAPCLR_Msk Ú P ETx_CR_CAPONCE_Pos ¹Ú P ETx_CR_CAPONCE_Msk ÀÚ P ETx_CR_CAPONCE_SINGLE #Ú P ETx_CR_CAPONCE_CONTINUE |Ú P ETx_CR_CAPEDGE_Pos ÉÚ P ETx_CR_CAPEDGE_Msk ÐÚ P ETx_CR_CAPEDGE_FALLING öÚ P ETx_CR_CAPEDGE_RISING )Ú P ETx_INSR_SIG2SEL_Pos Ú P ETx_INSR_SIG2SEL_Msk Ú P ETx_INSR_SIG2SEL_GROUP1 |Ú P ETx_INSR_SIG2SEL_GROUP2 {Ú P ETx_INSR_SIG1SEL_Pos Ú P ETx_INSR_SIG1SEL_Msk Ú P ETx_INSR_SIG1SEL_GROUP2 |Ú P ETx_INSR_SIG1SEL_GROUP1 }Ú P ETx_INSR_GRP2SEL_Pos Ú P ETx_INSR_GRP2SEL_Msk Ú& P ETx_INSR_GRP2SEL_ET1_UART0_RX Ú& P ETx_INSR_GRP2SEL_ET1_UART1_RX Ú" P ETx_INSR_GRP2SEL_ET1_XTLF ÉÚ! P ETx_INSR_GRP2SEL_ET1_IN1 AÚ! P ETx_INSR_GRP2SEL_ET1_IN2 @Ú# P ETx_INSR_GRP2SEL_ET1_CMP1O ¥Ú# P ETx_INSR_GRP2SEL_ET1_CMP2O ¤Ú" P ETx_INSR_GRP2SEL_ET1_RCMF ßÚ& P ETx_INSR_GRP2SEL_ET2_UART2_RX Ú& P ETx_INSR_GRP2SEL_ET2_UART3_RX Ú" P ETx_INSR_GRP2SEL_ET2_XTLF ÈÚ! P ETx_INSR_GRP2SEL_ET2_IN1 @Ú! P ETx_INSR_GRP2SEL_ET2_IN2 ?Ú# P ETx_INSR_GRP2SEL_ET2_CMP1O ¤Ú# P ETx_INSR_GRP2SEL_ET2_CMP2O £Ú" P ETx_INSR_GRP2SEL_ET2_RCMF ÞÚ! P ETx_INSR_GRP2SEL_ET3_IN1 ?Ú" P ETx_INSR_GRP2SEL_ET3_XTLF ÇÚ& P ETx_INSR_GRP2SEL_ET3_UART4_RX Ú& P ETx_INSR_GRP2SEL_ET3_UART5_RX Ú$ P ETx_INSR_GRP2SEL_ET3_RTCSEC =Ú P ETx_INSR_GRP2SEL_ET4_IN qÚ" P ETx_INSR_GRP2SEL_ET4_XTLF ÆÚ& P ETx_INSR_GRP2SEL_ET4_UART_RX2
Ú& P ETx_INSR_GRP2SEL_ET4_UART_RX0 Ú# P ETx_INSR_GRP2SEL_ET4_CMP1O ¢Ú# P ETx_INSR_GRP2SEL_ET4_CMP2O ¡Ú$ P ETx_INSR_GRP2SEL_ET4_RTCSEC <Ú" P ETx_INSR_GRP2SEL_ET4_RCMF ÜÚ P ETx_INSR_GRP1SEL_Pos Ú P ETx_INSR_GRP1SEL_Msk Ú$ P ETx_INSR_GRP1SEL_ET1_APBCLK WÚ" P ETx_INSR_GRP1SEL_ET1_XTLF ÊÚ" P ETx_INSR_GRP1SEL_ET1_RCLP ×Ú! P ETx_INSR_GRP1SEL_ET1_IN0 CÚ$ P ETx_INSR_GRP1SEL_ET2_APBCLK VÚ" P ETx_INSR_GRP1SEL_ET2_XTLF ÉÚ" P ETx_INSR_GRP1SEL_ET2_RCLP ÖÚ! P ETx_INSR_GRP1SEL_ET2_IN0 BÚ$ P ETx_INSR_GRP1SEL_ET3_APBCLK UÚ! P ETx_INSR_GRP1SEL_ET3_IN0 AÚ$ P ETx_INSR_GRP1SEL_ET3_RTCSEC >Ú" P ETx_INSR_GRP1SEL_ET3_RCLP ÕÚ$ P ETx_INSR_GRP1SEL_ET4_APBCLK TÚ! P ETx_INSR_GRP1SEL_ET4_IN0 @Ú% P ETx_INSR_GRP1SEL_ET4_RTC64HZ
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Ú" P ETx_INSR_GRP1SEL_ET4_RCMF ÝÚ P ETx_PSCR1_PRESCALE1_Pos TÚ P ETx_PSCR1_PRESCALE1_Msk [Ú P ETx_PSCR2_PRESCALE2_Pos RÚ P ETx_PSCR2_PRESCALE2_Msk YÚ P ETx_IVR_INITVALUE_Pos Ú P ETx_IVR_INITVALUE_Msk ¦Ú P ETx_CMPR_CMP_Pos 9Ú P ETx_CMPR_CMP_Msk @Ú P ETx_IER_CMPIE_Pos ûÚ P ETx_IER_CMPIE_Msk Ú P ETx_IER_CAPIE_Pos Ú P ETx_IER_CAPIE_Msk Ú P ETx_IER_OVIE_Pos 8Ú P ETx_IER_OVIE_Msk ?Ú P ETx_ISR_CMPIF_Pos ìÚ P ETx_ISR_CMPIF_Msk óÚ P ETx_ISR_EDGESTA_Pos ZÚ P ETx_ISR_EDGESTA_Msk aÚ P ETx_ISR_CAPIF_Pos øÚ P ETx_ISR_CAPIF_Msk ÿÚ P ETx_ISR_OVIF_Pos )Ú P ETx_ISR_OVIF_Msk 0Ú P ETCNTx_CNT_Pos äÚ P ETCNTx_CNT_Msk ëÚ , ETx ºÚ ETx_Deinit Ú , ETx ºÚ ,
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SetValue ¦Ú ETx_CR_OPOL_Set ¡Ú , ETx ºÚ ETx_CR_OPOL_Get Ú , ETx ºÚ ,
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SetValue ¦Ú ETx_CR_EXFLT_Set VÚ , ETx ºÚ ETx_CR_EXFLT_Get bÚ , ETx ºÚ ," NewState Ú ETx_CR_PWM_Setable MÚ , ETx ºÚ ETx_CR_PWM_Getable YÚ , ETx ºÚ ," NewState Ú ETx_CR_CEN_Setable kÚ , ETx ºÚ ETx_CR_CEN_Getable wÚ , ETx ºÚ ,
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SetValue ¦Ú ETx_CR_MOD_Set ýÚ , ETx ºÚ ETx_CR_MOD_Get Ú , ETx ºÚ ,
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SetValue ¦Ú ETx_CR_CASEN_Set oÚ , ETx ºÚ ETx_CR_CASEN_Get {Ú , ETx ºÚ ,
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SetValue ¦Ú ETx_CR_EDGESEL_Set ÜÚ , ETx ºÚ ETx_CR_EDGESEL_Get èÚ , ETx ºÚ ,
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SetValue ¦Ú ETx_CR_CAPMOD_Set #Ú , ETx ºÚ ETx_CR_CAPMOD_Get /Ú , ETx ºÚ ," NewState Ú ETx_CR_CAPCLR_Setable Ú , ETx ºÚ ETx_CR_CAPCLR_Getable Ú , ETx ºÚ ,
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SetValue ¦Ú ETx_CR_CAPONCE_Set ÜÚ , ETx ºÚ ETx_CR_CAPONCE_Get èÚ , ETx ºÚ ,
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SetValue ¦Ú ETx_CR_CAPEDGE_Set ìÚ , ETx ºÚ ETx_CR_CAPEDGE_Get øÚ , ETx ºÚ ,
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SetValue ¦Ú ETx_INSR_SIG2SEL_Set 1Ú , ETx ºÚ ETx_INSR_SIG2SEL_Get =Ú , ETx ºÚ ,
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SetValue ¦Ú ETx_INSR_SIG1SEL_Set 2Ú , ETx ºÚ ETx_INSR_SIG1SEL_Get >Ú , ETx ºÚ ,
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SetValue ¦Ú ETx_INSR_GRP2SEL_Set +Ú , ETx ºÚ ETx_INSR_GRP2SEL_Get 7Ú , ETx ºÚ ,
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SetValue ¦Ú ETx_INSR_GRP1SEL_Set ,Ú , ETx ºÚ ETx_INSR_GRP1SEL_Get 8Ú , ETx ºÚ ,
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SetValue ¦Ú ETx_PSCR1_Write Ú , ETx ºÚ ETx_PSCR1_Read Ú , ETx ºÚ ,
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SetValue ¦Ú ETx_PSCR2_Write Ú , ETx ºÚ ETx_PSCR2_Read Ú , ETx ºÚ ,
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SetValue ¦Ú ETx_IVR_Write Ú , ETx ºÚ ETx_IVR_Read Ú , ETx ºÚ ,
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SetValue ¦Ú ETx_CMPR_Write ÀÚ , ETx ºÚ ETx_CMPR_Read QÚ , ETx ºÚ ," NewState Ú ETx_IER_CMPIE_Setable Ú , ETx ºÚ ETx_IER_CMPIE_Getable Ú , ETx ºÚ ," NewState Ú ETx_IER_CAPIE_Setable Ú , ETx ºÚ ETx_IER_CAPIE_Getable Ú , ETx ºÚ ," NewState Ú ETx_IER_OVIE_Setable ¿Ú , ETx ºÚ ETx_IER_OVIE_Getable ËÚ , ETx ºÚ ETx_ISR_CMPIF_Clr Ú , ETx ºÚ ETx_ISR_CMPIF_Chk %Ú , ETx ºÚ ETx_ISR_EDGESTA_Chk Ú , ETx ºÚ ETx_ISR_CAPIF_Clr &Ú , ETx ºÚ ETx_ISR_CAPIF_Chk 1Ú , ETx ºÚ ETx_ISR_OVIF_Clr WÚ , ETx ºÚ ETx_ISR_OVIF_Chk bÚ , ETIMx Ú ETxCNT_CNTx_Read ;Ú P __FM33A0XXEV_VRTC_H íÚ P const_rcmf_Trim Ú P const_rclp_Trim {Ú P VRTC_PDRCR_CFG_Pos ÎÚ P VRTC_PDRCR_CFG_Msk ÕÚ P VRTC_RCMFCR_EN_Msk ÐÚ P VRTC_RCMFCR_EN_Pos ÉÚ P VRTC_RCMFCR_TRIM_Pos Ú P VRTC_RCMFCR_TRIM_Msk #Ú P VRTC_RCLPCR_CHOPEN_Pos Ú P VRTC_RCLPCR_CHOPEN_Msk Ú! P VRTC_RCLPCR_RCLP_OFF_Pos ÜÚ! P VRTC_RCLPCR_RCLP_OFF_Msk ãÚ" P VRTC_RCLPTR_RCLP_TRIM_Pos hÚ" P VRTC_RCLPTR_RCLP_TRIM_Msk oÚ P VRTC_XTLFCR_XTLFIPW_Pos Ú P VRTC_XTLFCR_XTLFIPW_Msk Ú" P VRTC_XTLFCR_XTLFIPW_850NA Ú" P VRTC_XTLFCR_XTLFIPW_800NA Ú" P VRTC_XTLFCR_XTLFIPW_750NA Ú" P VRTC_XTLFCR_XTLFIPW_700NA Ú" P VRTC_XTLFCR_XTLFIPW_650NA Ú" P VRTC_XTLFCR_XTLFIPW_600NA Ú" P VRTC_XTLFCR_XTLFIPW_550NA Ú" P VRTC_XTLFCR_XTLFIPW_500NA Ú" P VRTC_XTLFCR_XTLFIPW_450NA Ú" P VRTC_XTLFCR_XTLFIPW_400NA Ú" P VRTC_XTLFCR_XTLFIPW_350NA Ú" P VRTC_XTLFCR_XTLFIPW_300NA Ú" P VRTC_XTLFCR_XTLFIPW_250NA Ú" P VRTC_XTLFCR_XTLFIPW_200NA Ú" P VRTC_XTLFCR_XTLFIPW_150NA Ú" P VRTC_XTLFCR_XTLFIPW_100NA Ú P VRTC_ADCCR_CKS_Pos ÛÚ P VRTC_ADCCR_CKS_Msk âÚ P VRTC_ADCCR_CKS_RCMF ãÚ P VRTC_ADCCR_CKS_RCMF_2 NÚ P VRTC_ADCCR_CKS_RCMF_4 LÚ P VRTC_ADCCR_CKS_RCMF_8 HÚ P VRTC_ADCCR_CKS_RCMF_16 Ú P VRTC_ADCCR_CKS_RCMF_32 Ú P VRTC_ADCCR_CKS_RCLP ÚÚ P VRTC_ADCCR_CKS_XTLF ÍÚ P VRTC_ADCCR_CKE_Pos éÚ P VRTC_ADCCR_CKE_Msk ðÚ! P VRTC_LFDIER_LFDET_IE_Pos ûÚ! P VRTC_LFDIER_LFDET_IE_Msk Ú P VRTC_LFDISR_LFDETO_Pos Ú P VRTC_LFDISR_LFDETO_Msk Ú! P VRTC_LFDISR_LFDET_IF_Pos ìÚ! P VRTC_LFDISR_LFDET_IF_Msk óÚ VRTC_Deinit ×Ú ," NewState Ú VRTC_RCMFCR_EN_Setable PÚ VRTC_RCMFCR_EN_Getable \Ú ,
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SetValue ¦Ú VRTC_RCMFCR_TRIM_Set ?Ú VRTC_RCMFCR_TRIM_Get KÚ ," NewState Ú# VRTC_RCLPCR_CHOPEN_Setable Ú# VRTC_RCLPCR_CHOPEN_Getable !Ú ," NewState Ú% VRTC_RCLPCR_RCLP_OFF_Setable cÚ% VRTC_RCLPCR_RCLP_OFF_Getable oÚ ,
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SetValue ¦Ú VRTC_RCLPTR_Write çÚ VRTC_RCLPTR_Read xÚ VRTC_Init_RCLP_Trim Ú ,
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SetValue ¦Ú VRTC_XTLFCR_XTLFIPW_Set 1Ú VRTC_XTLFCR_XTLFIPW_Get =Ú ,
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SetValue ¦Ú VRTC_ADCCR_CKS_Set þÚ VRTC_ADCCR_CKS_Get
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Ú ," NewState Ú VRTC_ADCCR_CKE_Setable pÚ VRTC_ADCCR_CKE_Getable |Ú ," NewState Ú% VRTC_LFDIER_LFDET_IE_Setable Ú% VRTC_LFDIER_LFDET_IE_Getable Ú VRTC_LFDISR_LFDETO_Chk ÈÚ! VRTC_LFDISR_LFDET_IF_Clr Ú! VRTC_LFDISR_LFDET_IF_Chk %Ú VRTC_Init_RCMF_Trim Ú P __FM33A0XXEV_CDIF_H Ú P CDIF_CR_INTF_EN_Pos Ú P CDIF_CR_INTF_EN_Msk Ú P CDIF_CR_INTF_EN_ENABLE Ú P CDIF_CR_INTF_EN_DISABLE ¾Ú P CDIF_PSCR_PRSC_Pos ÒÚ P CDIF_PSCR_PRSC_Msk ÙÚ P CDIF_PSCR_PRSC_DIV1 îÚ P CDIF_PSCR_PRSC_DIV2 íÚ P CDIF_PSCR_PRSC_DIV4 ëÚ P CDIF_PSCR_PRSC_DIV8 çÚ P CDIF_PSCR_PRSC_DIV16 ¶Ú P CDIF_PSCR_PRSC_DIV32 ¸Ú P CDIF_PSCR_PRSC_DIV64 ³Ú P CDIF_PSCR_PRSC_DIV128 Ú CDIF_Deinit Ú ," NewState Ú CDIF_CR_INTF_EN_Setable Ú CDIF_CR_INTF_EN_Getable Ú ,
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SetValue ¦Ú CDIF_PSCR_Write ³Ú CDIF_PSCR_Read DÚ P __string_h Ú P __STRING_DECLS PÚ memcpy QÚ memmove äÚ strcpy 7Ú strncpy ÇÚ strcat KÚ strncat ÛÚ memcmp ]Ú strcmp CÚ strncmp ÓÚ strcasecmp Ú strncasecmp /Ú strcoll ×Ú strxfrm ÄÚ memchr `Ú strchr FÚ strcspn ÍÚ strpbrk ÒÚ strrchr ÒÚ strspn 2Ú strstr *Ú strtok 5Ú
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_strtok_r ÿÚ P __STRICT_ANSI__ ÌÚ strtok_r `Ú memset QÚ strerror UÚ strlen DÚ strlcpy ÉÚ strlcat ÝÚ _membitcpybl ÙÚ _membitcpybb ãÚ _membitcpyhl ÓÚ _membitcpyhb ÝÚ _membitcpywl ÄÚ _membitcpywb ÎÚ _membitmovebl lÚ _membitmovebb vÚ _membitmovehl fÚ _membitmovehb pÚ _membitmovewl WÚ _membitmovewb aÚ P BIT0 ´Ú P BIT1 ³Ú P BIT2 ²Ú P BIT3 ±Ú P BIT4 °Ú P BIT5 ¯Ú P BIT6 ®Ú P BIT7 Ú P BIT8 ¬Ú P BIT9 «Ú P BIT10 Ú P BIT11 Ú P BIT12 Ú P BIT13 ~Ú P BIT14 }Ú P BIT15 |Ú P BIT16 {Ú P BIT17 zÚ P BIT18 yÚ P BIT19 xÚ P BIT20 Ú P BIT21 Ú P BIT22 ~Ú P BIT23 }Ú P BIT24 |Ú P BIT25 {Ú P BIT26 zÚ P BIT27 yÚ P BIT28 xÚ P BIT29 wÚ P BIT30 Ú P BIT31 ~Ú P BITNO EÚ P B0000_0000 Ú P B0000_0001 Ú P B0000_0010 Ú P B0000_0011 Ú P B0000_0100 Ú P B0000_0101 Ú P B0000_0110 Ú P B0000_0111 Ú P B0000_1000 Ú P B0000_1001 Ú P B0000_1010 Ú P B0000_1011 Ú P B0000_1100 Ú P B0000_1101 Ú P B0000_1110 Ú P B0000_1111 Ú P B0001_0000 Ú P B0001_0001 Ú P B0001_0010 Ú P B0001_0011 Ú P B0001_0100 Ú P B0001_0101 Ú P B0001_0110 Ú P B0001_0111 Ú P B0001_1000 Ú P B0001_1001 Ú P B0001_1010 Ú P B0001_1011 Ú P B0001_1100 Ú P B0001_1101 Ú P B0001_1110 Ú P B0001_1111 Ú P B0010_0000 Ú P B0010_0001 Ú P B0010_0010 Ú P B0010_0011 Ú P B0010_0100 Ú P B0010_0101 Ú P B0010_0110 Ú P B0010_0111 Ú P B0010_1000 Ú P B0010_1001 Ú P B0010_1010 Ú P B0010_1011 Ú P B0010_1100 Ú P B0010_1101 Ú P B0010_1110 Ú P B0010_1111 Ú P B0011_0000 Ú P B0011_0001 Ú P B0011_0010 Ú P B0011_0011 Ú P B0011_0100 Ú P B0011_0101 Ú P B0011_0110 Ú P B0011_0111 Ú P B0011_1000 Ú P B0011_1001 Ú P B0011_1010 Ú P B0011_1011 Ú P B0011_1100 Ú P B0011_1101 Ú P B0011_1110 Ú P B0011_1111 Ú P B0100_0000 Ú P B0100_0001 Ú P B0100_0010 Ú P B0100_0011 Ú P B0100_0100 Ú P B0100_0101 Ú P B0100_0110 Ú P B0100_0111 Ú P B0100_1000 Ú P B0100_1001 Ú P B0100_1010 Ú P B0100_1011 Ú P B0100_1100 Ú P B0100_1101 Ú P B0100_1110 Ú P B0100_1111 Ú P B0101_0000 Ú P B0101_0001 Ú P B0101_0010 Ú P B0101_0011 Ú P B0101_0100 Ú P B0101_0101 Ú P B0101_0110 Ú P B0101_0111 Ú P B0101_1000 Ú P B0101_1001 Ú P B0101_1010 Ú P B0101_1011 Ú P B0101_1100 Ú P B0101_1101 Ú P B0101_1110 Ú P B0101_1111 Ú P B0110_0000 Ú P B0110_0001 Ú P B0110_0010 Ú P B0110_0011 Ú P B0110_0100 Ú P B0110_0101 Ú P B0110_0110 Ú P B0110_0111 Ú P B0110_1000 Ú P B0110_1001 Ú P B0110_1010 Ú P B0110_1011 Ú P B0110_1100 Ú P B0110_1101 Ú P B0110_1110 Ú P B0110_1111 Ú P B0111_0000 Ú P B0111_0001 Ú P B0111_0010 Ú P B0111_0011 Ú P B0111_0100 Ú P B0111_0101 Ú P B0111_0110 Ú P B0111_0111 Ú P B0111_1000 Ú P B0111_1001 Ú P B0111_1010 Ú P B0111_1011 Ú P B0111_1100 Ú P B0111_1101 Ú P B0111_1110 Ú P B0111_1111 Ú P B1000_0000 Ú P B1000_0001 Ú P B1000_0010 Ú P B1000_0011 Ú P B1000_0100 Ú P B1000_0101 Ú P B1000_0110 Ú P B1000_0111 Ú P B1000_1000 Ú P B1000_1001 Ú P B1000_1010 Ú P B1000_1011 Ú P B1000_1100 Ú P B1000_1101 Ú P B1000_1110 Ú P B1000_1111 Ú P B1001_0000 Ú P B1001_0001 Ú P B1001_0010 Ú P B1001_0011 Ú P B1001_0100 Ú P B1001_0101 Ú P B1001_0110 Ú P B1001_0111 Ú P B1001_1000 Ú P B1001_1001 Ú P B1001_1010 Ú P B1001_1011 Ú P B1001_1100 Ú P B1001_1101 Ú P B1001_1110 Ú P B1001_1111 Ú P B1010_0000 Ú P B1010_0001 Ú P B1010_0010 Ú P B1010_0011 Ú P B1010_0100 Ú P B1010_0101 Ú P B1010_0110 Ú P B1010_0111 Ú P B1010_1000 Ú P B1010_1001 Ú P B1010_1010 Ú P B1010_1011 Ú P B1010_1100 Ú P B1010_1101 Ú P B1010_1110 Ú P B1010_1111 Ú P B1011_0000 Ú P B1011_0001 Ú P B1011_0010 Ú P B1011_0011 Ú P B1011_0100 Ú P B1011_0101 Ú P B1011_0110 Ú P B1011_0111 Ú P B1011_1000 Ú P B1011_1001 Ú P B1011_1010 Ú P B1011_1011 Ú P B1011_1100 Ú P B1011_1101 Ú P B1011_1110 Ú P B1011_1111 Ú P B1100_0000 Ú P B1100_0001 Ú P B1100_0010 Ú P B1100_0011 Ú P B1100_0100 Ú P B1100_0101 Ú P B1100_0110 Ú P B1100_0111 Ú P B1100_1000 Ú P B1100_1001 Ú P B1100_1010 Ú P B1100_1011 Ú P B1100_1100 Ú P B1100_1101 Ú P B1100_1110 Ú P B1100_1111 Ú P B1101_0000 Ú P B1101_0001 Ú P B1101_0010 Ú P B1101_0011 Ú P B1101_0100 Ú P B1101_0101 Ú P B1101_0110 Ú P B1101_0111 Ú P B1101_1000 Ú P B1101_1001 Ú P B1101_1010 Ú P B1101_1011 Ú P B1101_1100 Ú P B1101_1101 Ú P B1101_1110 Ú P B1101_1111 Ú P B1110_0000 Ú P B1110_0001 Ú P B1110_0010 Ú P B1110_0011 Ú P B1110_0100 Ú P B1110_0101 Ú P B1110_0110 Ú P B1110_0111 Ú P B1110_1000 Ú P B1110_1001 Ú P B1110_1010 Ú P B1110_1011 Ú P B1110_1100 Ú P B1110_1101 Ú P B1110_1110 Ú P B1110_1111 Ú P B1111_0000 Ú P B1111_0001 Ú P B1111_0010 Ú P B1111_0011 Ú P B1111_0100 Ú P B1111_0101 Ú P B1111_0110 Ú P B1111_0111 Ú P B1111_1000 Ú P B1111_1001 Ú P B1111_1010 Ú P B1111_1011 Ú P B1111_1100 Ú P B1111_1101 Ú P B1111_1110 Ú P B1111_1111 Ú P __USER_INIT_H__ ¸Ú , RegAddr *Ú ,
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Value ØÚ CheckSysReg Ú ," IRQn hÚ CheckNvicIrqEn Ú SysWakeUp_ClockCfg ÝÚ Init_SysClk_Gen Ú
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IWDT_Init «Ú Init_System ZÚ IWDT_Clr Ú P
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_DELAY_H_ åÚ" P SYSTICK_CLOCK_SOURCE_SCLK èÚ# P SYSTICK_CLOCK_SOURCE_LSCLK Ú! P SYSTICK_CLOCK_SOURCE_RFU *Ú$ P SYSTICK_CLOCK_SOURCE_SYSCLK 8Ú$ P SYSTICK_CLOCK_SOURCE_U_SCLK 0Ú% P SYSTICK_CLOCK_SOURCE_U_LSCLK âÚ# P SYSTICK_CLOCK_SOURCE_U_RFU rÚ& P SYSTICK_CLOCK_SOURCE_U_SYSCLK Ú P SYSCLOCK_U Ú ConditionHook ¯Ú ,
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sysclkfre ÷Ú delay_init ²Ú ,
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ms ûÚ delay_ms Ú ,
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us óÚ delay_us Ú G6 |Ú G10 OÚ G16 IÚ G25 IÚ CALIBER_TYPE VÚ 8 check_cal_inf Ú " : device_type bÚ " : pluse_flag ÓÚ " :low_pluse_cnt qÚ " : work_period EÚ " :
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check_fre FÚ " :check_fre_low Ú " :check_fre_flow %Ú " :workConInstantFlow rÚ " :stdConInstantFlow ìÚ " :uvol $Ú " :cvol 6Ú " : check_utotal äÚ " : check_ctotal öÚ " :low_pluse_out GÚ CHECK_CAL_INF Ú P PERIOD üÚ P LED_HIGH gÚ P LED_LOW Ú U check_cal_g /Ú led_para_output_init eÚ , flow Ú led_pluse_out ZÚ , flag DÚ! set_led_para_output_flag ÌÚ! get_led_para_output_flag ØÚ P _GPIO_H_ 'Ú P UNCAP_DETECTION_PORT Ú P UNCAP_DETECTION_PIN êÚ P EXT_RTC_INT_PORT Ú P EXT_RTC_INT_PIN äÚ , GPIOx Ú ,
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GPIO_Pin Ú AnalogIO îÚ ,
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GPIO_Pin Ú AnalogIO_H CÚ , GPIOx Ú ,
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GPIO_Pin Ú , Type <Ú InputtIO ¼Ú ,
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GPIO_Pin Ú , Type <Ú InputtIO_H Ú , GPIOx Ú ,
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GPIO_Pin Ú , Type <Ú OutputIO ¯Ú ,
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GPIO_Pin Ú OutputIO_H Ú , GPIOx Ú ,
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GPIO_Pin Ú , Type <Ú AltFunIO öÚ ,
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GPIO_Pin Ú , Type <Ú AltFunIO_H KÚ , GPIOx Ú ,
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GPIO_Pin Ú CloseIO LÚ , GPIOx Ú ,
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GPIO_Pin Ú
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CloseH_IO ¡Ú Pulse_IO_Init ÛÚ allGpioInit vÚ P LOW_FLOW_CNT æÚ P CHECK_PERIOD 3Ú P WORK_FLOW_PARA RÚ ," ¥:flag CÚ ," £:flow Ú " £:
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new_pluse 'Ú " £: data_differ uÚ " £:led_data_delay <Ú " £:time KÛ uÛ .¾Û
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ÏÛ ïÛ íÛ ØÛ ! ÖÛ # ÓÛ $ ÑÛ
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% ÏÛ & ÍÛ ' ËÛ ( ÉÛ ) ÇÛ * ÅÛ + ÃÛ , ÁÛ - ¿Û 1 2Û 2 ¸Û 3 ¶Û 5 ³Û
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6 ºjÛ
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7 »gÛ 8 Û 9 «Û : ©Û A ¡Û B Û G Û H Û O Û !P Û "Q Û #R Û $#$
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