/**
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******************************************************************************
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* @file fm33a0xxev_svd.h
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* @author FM33A0XXEV Application Team
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* @version V1.0.0
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* @date 16-April-2020
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* @brief This file contains all the functions prototypes for the SVD firmware library.
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __FM33A0XXEV_SVD_H
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#define __FM33A0XXEV_SVD_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "FM33A0XXEV.h"
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typedef struct
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{
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uint32_t SVDMOD; /*!<SVD¹¤×÷ģʽѡÔñ */
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uint32_t SVDITVL; /*!<SVD¼äЪʹÄܼä¸ô */
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uint32_t SVDLVL; /*!<SVD±¨¾¯ãÐÖµÉèÖà */
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FunState DFEN; /*!<SVDÊý×ÖÂ˲¨£¨SVDMODE=1ʱ±ØÐëÖÃ1£© */
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FunState PFIE; /*!<SVDµçÔ´µøÂäÖÐ¶Ï */
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FunState PRIE; /*!<SVDµçÔ´»Ö¸´ÖÐ¶Ï */
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FunState SVDEN; /*!<SVDʹÄÜ */
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}SVD_InitTypeDef;
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#define SVD_CFGR_LVL_Pos 4 /* SVD±¨¾¯ãÐÖµµµÎ»ÉèÖ㬲μû11.3.3¼ì²âãÐÖµ
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(SVD threshold level) */
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#define SVD_CFGR_LVL_Msk (0xfU << SVD_CFGR_LVL_Pos)
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#define SVD_CFGR_LVL_1P800V (0x0U << SVD_CFGR_LVL_Pos)
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#define SVD_CFGR_LVL_2P014V (0x1U << SVD_CFGR_LVL_Pos)
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#define SVD_CFGR_LVL_2P229V (0x2U << SVD_CFGR_LVL_Pos)
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#define SVD_CFGR_LVL_2P443V (0x3U << SVD_CFGR_LVL_Pos)
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#define SVD_CFGR_LVL_2P657V (0x4U << SVD_CFGR_LVL_Pos)
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#define SVD_CFGR_LVL_2P871V (0x5U << SVD_CFGR_LVL_Pos)
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#define SVD_CFGR_LVL_3P086V (0x6U << SVD_CFGR_LVL_Pos)
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#define SVD_CFGR_LVL_3P300V (0x7U << SVD_CFGR_LVL_Pos)
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#define SVD_CFGR_LVL_3P514V (0x8U << SVD_CFGR_LVL_Pos)
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#define SVD_CFGR_LVL_3P729V (0x9U << SVD_CFGR_LVL_Pos)
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#define SVD_CFGR_LVL_3P943V (0xaU << SVD_CFGR_LVL_Pos)
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#define SVD_CFGR_LVL_4P157V (0xbU << SVD_CFGR_LVL_Pos)
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#define SVD_CFGR_LVL_4P371V (0xcU << SVD_CFGR_LVL_Pos)
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#define SVD_CFGR_LVL_4P586V (0xdU << SVD_CFGR_LVL_Pos)
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#define SVD_CFGR_LVL_4P800V (0xeU << SVD_CFGR_LVL_Pos)
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#define SVD_CFGR_LVL_SVS (0xfU << SVD_CFGR_LVL_Pos)
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#define SVD_CFGR_DFEN_Pos 3 /* Êý×ÖÂ˲¨Ê¹ÄÜ£¨MOD=1ʱ±ØÐëÖÃ1£©
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(Digital Filter Enable)
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1£ºÆô¶¯SVDÊä³öµÄÊý×ÖÂ˲¨
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0£º¹Ø±ÕSVDÊä³öµÄÊý×ÖÂ˲¨ */
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#define SVD_CFGR_DFEN_Msk (0x1U << SVD_CFGR_DFEN_Pos)
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/* Æô¶¯SVDÊä³öµÄÊý×ÖÂ˲¨ */
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/* ¹Ø±ÕSVDÊä³öµÄÊý×ÖÂ˲¨ */
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#define SVD_CFGR_MOD_Pos 2 /* SVD¹¤×÷ģʽѡÔñ£¬ÅäÖÃģʽºó»¹ÒªÖÃλSVD_CR.EN²Å»áÆô¶¯SVD
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(SVD Mode)
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1£º¼äЪʹÄÜģʽ
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0£º³£Ê¹ÄÜģʽ
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×¢Ò⣺¼äЪʹÄÜģʽϱØÐ뿪ÆôÊý×ÖÂ˲¨ */
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#define SVD_CFGR_MOD_Msk (0x1U << SVD_CFGR_MOD_Pos)
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#define SVD_CFGR_MOD_INTERVAL (0x1U << SVD_CFGR_MOD_Pos) /* ¼äЪʹÄÜģʽ */
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#define SVD_CFGR_MOD_ALWAYSON (0x0U << SVD_CFGR_MOD_Pos) /* ³£Ê¹ÄÜģʽ */
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#define SVD_CFGR_ITVL_Pos 0 /* SVD¼äЪʹÄܼä¸ô (SVD interval enable period)
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00£º62.5ms
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01£º256ms
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10£º1s
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11£º4s */
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#define SVD_CFGR_ITVL_Msk (0x3U << SVD_CFGR_ITVL_Pos)
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#define SVD_CFGR_ITVL_62P5MS (0x0U << SVD_CFGR_ITVL_Pos) /* 62.5ms */
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#define SVD_CFGR_ITVL_256MS (0x1U << SVD_CFGR_ITVL_Pos) /* 256ms */
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#define SVD_CFGR_ITVL_1S (0x2U << SVD_CFGR_ITVL_Pos) /* 1s */
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#define SVD_CFGR_ITVL_4S (0x3U << SVD_CFGR_ITVL_Pos) /* 4s */
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/* 62.5ms */
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/* 256ms */
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/* 1s */
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/* 4s */
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#define SVD_CR_TE_Pos 8 /* SVD²âÊÔʹÄÜ£¬±ÜÃâд1 (SVD test enable) */
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#define SVD_CR_TE_Msk (0x1U << SVD_CR_TE_Pos)
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#define SVD_CR_SVSEN_Pos 1 /* SVSÍⲿµçÔ´¼ì²âͨµÀ¿ØÖÆÐźÅ
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(SVS external monitor channel enable)
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0£ºSVSͨµÀ¹Ø±Õ
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1£ºSVSͨµÀʹÄÜ
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µ±EN=1ʱ£¬¸ù¾ÝSVDLVL¼Ä´æÆ÷¿ÉÒÔÉèÖÃSVSÊäÈëºóÊÇ·ñ¾¹ýÄÚ²¿µç×è·Öѹ£»Èç¹ûLVL=1111£¬ÔòSVSÊäÈë²»×ö·Öѹ£¬Èç¹ûLVL != 1111£¬ÔòSVSÊäÈë¾¹ýÄÚ²¿µç×è·Öѹ¡£ */
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#define SVD_CR_SVSEN_Msk (0x1U << SVD_CR_SVSEN_Pos)
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/* SVSͨµÀ¹Ø±Õ */
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/* SVSͨµÀʹÄÜ */
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#define SVD_CR_SVDEN_Pos 0
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#define SVD_CR_SVDEN_Msk (0x1U << SVD_CR_SVDEN_Pos)
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#define SVD_IER_PFIE_Pos 1 /* µçÔ´µøÂäÖжÏʹÄܼĴæÆ÷£¬1ÓÐЧ (Power Fall interrupt enable) */
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#define SVD_IER_PFIE_Msk (0x1U << SVD_IER_PFIE_Pos)
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#define SVD_IER_PRIE_Pos 0 /* µçÔ´»Ö¸´ÖжÏʹÄܼĴæÆ÷£¬1ÓÐЧ (Power Rise interrupt enable) */
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#define SVD_IER_PRIE_Msk (0x1U << SVD_IER_PRIE_Pos)
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#define SVD_ISR_SVDO_Pos 8 /* SVDµçÔ´¼ì²âÊä³ö (SVD output)
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1£ºµçÔ´µçѹ¸ßÓÚSVDµ±Ç°ãÐÖµ
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0£ºµçÔ´µçѹµÍÓÚSVDµ±Ç°ãÐÖµ */
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#define SVD_ISR_SVDO_Msk (0x1U << SVD_ISR_SVDO_Pos)
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#define SVD_ISR_SVDR_Pos 7 /* SVDÊä³öËø´æÐźţ¬Êý×Öµç·Ëø´æµÄSVD״̬
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(SVD registered output) */
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#define SVD_ISR_SVDR_Msk (0x1U << SVD_ISR_SVDR_Pos)
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#define SVD_ISR_PFF_Pos 1 /* µçÔ´µøÂäÖжϱêÖ¾¼Ä´æÆ÷£¬µçÔ´µçѹµøÂäµ½SVDãÐÖµÖ®ÏÂʱÖÃ룬Èí¼þд1ÇåÁã (Power fall flag) */
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#define SVD_ISR_PFF_Msk (0x1U << SVD_ISR_PFF_Pos)
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#define SVD_ISR_PRF_Pos 0 /* µçÔ´»Ö¸´ÖжϱêÖ¾¼Ä´æÆ÷£¬µçÔ´µçѹÉÏÉýµ½SVDãÐÖµÖ®ÉÏʱÖÃ룬Èí¼þд1ÇåÁã (Power rise flag) */
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#define SVD_ISR_PRF_Msk (0x1U << SVD_ISR_PRF_Pos)
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#define SVD_VSR_V1P0EN_Pos 2 /* 1.0V»ù×¼ÊäÈëʹÄÜÐźŠ(1.0V reference enable)
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1£ºÊ¹ÄÜ1.0V»ù×¼ÊäÈë
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0£º¹Ø±Õ1.0V»ù×¼ÊäÈë */
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#define SVD_VSR_V1P0EN_Msk (0x1U << SVD_VSR_V1P0EN_Pos)
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#define SVD_VSR_V0P95EN_Pos 1 /* 0.95V»ù×¼ÊäÈëʹÄÜÐźŠ(0.95V reference enable)
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1£ºÊ¹ÄÜ0.95V»ù×¼ÊäÈë
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0£º¹Ø±Õ0.95V»ù×¼ÊäÈë */
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#define SVD_VSR_V0P95EN_Msk (0x1U << SVD_VSR_V0P95EN_Pos)
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#define SVD_VSR_V0P9EN_Pos 0 /* 0.9V»ù×¼ÊäÈëʹÄÜÐźŠ(0.9V reference enable)
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1£ºÊ¹ÄÜ0.9V»ù×¼ÊäÈë
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0£º¹Ø±Õ0.9V»ù×¼ÊäÈë */
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#define SVD_VSR_V0P9EN_Msk (0x1U << SVD_VSR_V0P9EN_Pos)
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//Macro_End
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/* Exported functions --------------------------------------------------------*/
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extern void SVD_Deinit(void);
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/* SVD±¨¾¯ãÐÖµµµÎ»ÉèÖ㬲μû11.3.3¼ì²âãÐÖµ
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(SVD threshold level) Ïà¹Øº¯Êý */
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extern void SVD_CFGR_LVL_Set(uint32_t SetValue);
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extern uint32_t SVD_CFGR_LVL_Get(void);
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/* Êý×ÖÂ˲¨Ê¹ÄÜ£¨MOD=1ʱ±ØÐëÖÃ1£©
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(Digital Filter Enable)
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1£ºÆô¶¯SVDÊä³öµÄÊý×ÖÂ˲¨
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0£º¹Ø±ÕSVDÊä³öµÄÊý×ÖÂ˲¨ Ïà¹Øº¯Êý */
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extern void SVD_CFGR_DFEN_Setable(FunState NewState);
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extern FunState SVD_CFGR_DFEN_Getable(void);
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/* SVD¹¤×÷ģʽѡÔñ£¬ÅäÖÃģʽºó»¹ÒªÖÃλSVD_CR.EN²Å»áÆô¶¯SVD
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(SVD Mode)
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1£º¼äЪʹÄÜģʽ
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0£º³£Ê¹ÄÜģʽ
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×¢Ò⣺¼äЪʹÄÜģʽϱØÐ뿪ÆôÊý×ÖÂ˲¨ Ïà¹Øº¯Êý */
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extern void SVD_CFGR_MOD_Set(uint32_t SetValue);
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extern uint32_t SVD_CFGR_MOD_Get(void);
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/* SVD¼äЪʹÄܼä¸ô (SVD interval enable period)
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00£º62.5ms
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01£º256ms
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10£º1s
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11£º4s Ïà¹Øº¯Êý */
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extern void SVD_CFGR_ITVL_Set(uint32_t SetValue);
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extern uint32_t SVD_CFGR_ITVL_Get(void);
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/* SVSÍⲿµçÔ´¼ì²âͨµÀ¿ØÖÆÐźÅ
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(SVS external monitor channel enable)
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0£ºSVSͨµÀ¹Ø±Õ
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1£ºSVSͨµÀʹÄÜ
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µ±EN=1ʱ£¬¸ù¾ÝSVDLVL¼Ä´æÆ÷¿ÉÒÔÉèÖÃSVSÊäÈëºóÊÇ·ñ¾¹ýÄÚ²¿µç×è·Öѹ£»Èç¹ûLVL=1111£¬ÔòSVSÊäÈë²»×ö·Öѹ£¬Èç¹ûLVL != 1111£¬ÔòSVSÊäÈë¾¹ýÄÚ²¿µç×è·Öѹ¡£ Ïà¹Øº¯Êý */
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extern void SVD_CR_SVSEN_Setable(FunState NewState);
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extern FunState SVD_CR_SVSEN_Getable(void);
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extern void SVD_CR_SVDEN_Setable(FunState NewState);
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extern FunState SVD_CR_SVDEN_Getable(void);
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/* µçÔ´µøÂäÖжÏʹÄܼĴæÆ÷£¬1ÓÐЧ (Power Fall interrupt enable) Ïà¹Øº¯Êý */
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extern void SVD_IER_PFIE_Setable(FunState NewState);
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extern FunState SVD_IER_PFIE_Getable(void);
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/* µçÔ´»Ö¸´ÖжÏʹÄܼĴæÆ÷£¬1ÓÐЧ (Power Rise interrupt enable) Ïà¹Øº¯Êý */
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extern void SVD_IER_PRIE_Setable(FunState NewState);
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extern FunState SVD_IER_PRIE_Getable(void);
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/* SVDµçÔ´¼ì²âÊä³ö (SVD output)
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1£ºµçÔ´µçѹ¸ßÓÚSVDµ±Ç°ãÐÖµ
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0£ºµçÔ´µçѹµÍÓÚSVDµ±Ç°ãÐÖµ Ïà¹Øº¯Êý */
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extern FlagStatus SVD_ISR_SVDO_Chk(void);
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/* SVDÊä³öËø´æÐźţ¬Êý×Öµç·Ëø´æµÄSVD״̬
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(SVD registered output) Ïà¹Øº¯Êý */
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extern FlagStatus SVD_ISR_SVDR_Chk(void);
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/* µçÔ´µøÂäÖжϱêÖ¾¼Ä´æÆ÷£¬µçÔ´µçѹµøÂäµ½SVDãÐÖµÖ®ÏÂʱÖÃ룬Èí¼þд1ÇåÁã (Power fall flag) Ïà¹Øº¯Êý */
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extern void SVD_ISR_PFF_Clr(void);
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extern FlagStatus SVD_ISR_PFF_Chk(void);
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/* µçÔ´»Ö¸´ÖжϱêÖ¾¼Ä´æÆ÷£¬µçÔ´µçѹÉÏÉýµ½SVDãÐÖµÖ®ÉÏʱÖÃ룬Èí¼þд1ÇåÁã (Power rise flag) Ïà¹Øº¯Êý */
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extern void SVD_ISR_PRF_Clr(void);
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extern FlagStatus SVD_ISR_PRF_Chk(void);
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/* 1.0V»ù×¼ÊäÈëʹÄÜÐźŠ(1.0V reference enable)
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1£ºÊ¹ÄÜ1.0V»ù×¼ÊäÈë
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0£º¹Ø±Õ1.0V»ù×¼ÊäÈë Ïà¹Øº¯Êý */
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extern void SVD_VSR_V1P0EN_Setable(FunState NewState);
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extern FunState SVD_VSR_V1P0EN_Getable(void);
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/* 0.95V»ù×¼ÊäÈëʹÄÜÐźŠ(0.95V reference enable)
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1£ºÊ¹ÄÜ0.95V»ù×¼ÊäÈë
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0£º¹Ø±Õ0.95V»ù×¼ÊäÈë Ïà¹Øº¯Êý */
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extern void SVD_VSR_V0P95EN_Setable(FunState NewState);
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extern FunState SVD_VSR_V0P95EN_Getable(void);
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/* 0.9V»ù×¼ÊäÈëʹÄÜÐźŠ(0.9V reference enable)
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1£ºÊ¹ÄÜ0.9V»ù×¼ÊäÈë
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0£º¹Ø±Õ0.9V»ù×¼ÊäÈë Ïà¹Øº¯Êý */
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extern void SVD_VSR_V0P9EN_Setable(FunState NewState);
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extern FunState SVD_VSR_V0P9EN_Getable(void);
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extern void SVD_Init(SVD_InitTypeDef* para);
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//Announce_End
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#ifdef __cplusplus
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}
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#endif
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#endif /* __FM33A0XXEV_SVD_H */
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