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FÁhÿ$$ F£CF#F@CÁ`½FHiÀÀ pGÊÒ BapGü ..\\Drivers\\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM __asm___17_fm33a0xxev_uart_c_92591b23____REV16 P 9 ..\\Core\\Include\\ core_cminstr.h ü ..\\Drivers\\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM __asm___17_fm33a0xxev_uart_c_92591b23____REVSH P 9 ..\\Core\\Include\\ core_cminstr.h 0 ÿÿÿÿarmcc+ |
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..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM ..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM ? UARTIR_CR_IRFLAG_Set iSetValue W Xtmpreg W P ..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM >%
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UARTIR_CR_IRFLAG_Get W ^__result W P
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..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM ?+UARTIR_CR_TH_Set iSetValue W Xtmpreg W P ..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM >ÿ4
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UARTIR_CR_TH_Get W ^__result W P
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..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM ?:UARTIR_CR_TZBRG_Set iSetValue W Xtmpreg W P ..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM
|
>C
|
UARTIR_CR_TZBRG_Get W
|
^__result W P ..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM >K UARTx_CSR_BUSY_Chk Ó iUARTx B * ___result Ó ..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM ?ZUARTx_CSR_TXIREN_Setable iUARTx B ) iNewState ..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM >f
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UARTx_CSR_TXIREN_Getable iUARTx B * ___result ..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM ?uUARTx_CSR_RXTOEN_Setable iUARTx B ) iNewState ..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM >
|
UARTx_CSR_RXTOEN_Getable iUARTx B * ___result ..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM ?UARTx_CSR_IOSWAP_Set iUARTx B A iSetValue W # Xtmpreg W Q ..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM >
|
UARTx_CSR_IOSWAP_Get W iUARTx B ^__result W P
|
..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM ?¡UARTx_CSR_DMATXIFCFG_Setable iUARTx B ) iNewState ..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM >
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UARTx_CSR_DMATXIFCFG_Getable iUARTx B * ___result ..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM ?¼UARTx_CSR_BITORD_Set iUARTx B A iSetValue W # Xtmpreg W Q ..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM >Å
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UARTx_CSR_BITORD_Get W iUARTx B ^__result W P
|
..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM ? ÍUARTx_CSR_STOPCFG_Set iUARTx B A iSetValue W # Xtmpreg W Q ..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM >Ö
|
UARTx_CSR_STOPCFG_Get W iUARTx B ^__result W P
|
..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM ?àUARTx_CSR_PDSEL_Set iUARTx B A iSetValue W # Xtmpreg W Q ..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM
|
>é
|
UARTx_CSR_PDSEL_Get W
|
iUARTx B ^__result W P ..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM ?óUARTx_CSR_PARITY_Set iUARTx B A iSetValue W # Xtmpreg W Q ..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM
|
>ü
|
UARTx_CSR_PARITY_Get W
|
iUARTx B ^__result W P ..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM ?UARTx_CSR_RXPOL_Setable iUARTx B ) iNewState ..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM >
|
UARTx_CSR_RXPOL_Getable iUARTx B * ___result ..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM ?UARTx_CSR_TXPOL_Setable iUARTx B ) iNewState ..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM >«
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UARTx_CSR_TXPOL_Getable iUARTx B * ___result ..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM ?¸UARTx_CSR_RXEN_Setable iUARTx B ) iNewState ..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM >Ä
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UARTx_CSR_RXEN_Getable iUARTx B * ___result ..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM ?ÑUARTx_CSR_TXEN_Setable iUARTx B ) iNewState ..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM >Ý
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UARTx_CSR_TXEN_Getable iUARTx B * ___result ..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM ?ëUARTx_IER_RXTO_IE_Setable iUARTx B ) iNewState ..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM >÷
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UARTx_IER_RXTO_IE_Getable iUARTx B * ___result ..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM ?UARTx_IER_RXERR_IE_Setable iUARTx B ) iNewState ..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM >
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UARTx_IER_RXERR_IE_Getable iUARTx B * ___result ..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM ?UARTx_IER_RXBF_IE_Setable iUARTx B ) iNewState ..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM >©
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UARTx_IER_RXBF_IE_Getable iUARTx B * ___result ..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM ?¶UARTx_IER_TXBE_IE_Setable iUARTx B ) iNewState ..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM >Â
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UARTx_IER_TXBE_IE_Getable iUARTx B * ___result ..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM ?ÏUARTx_IER_TXSE_IE_Setable iUARTx B ) iNewState ..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM >Û
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UARTx_IER_TXSE_IE_Getable iUARTx B * ___result ø ..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM ?úèUARTx_ISR_PERR_Clr iUARTx B ..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM >í UARTx_ISR_PERR_Chk Ó iUARTx B * ___result Ó ø ..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM ?úúUARTx_ISR_FERR_Clr iUARTx B ..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM >ÿ UARTx_ISR_FERR_Chk Ó iUARTx B * ___result Ó ø ..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM ?úUARTx_ISR_OERR_Clr iUARTx B ..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM > UARTx_ISR_OERR_Chk Ó iUARTx B * ___result Ó ø ..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM ?ú UARTx_ISR_RXTO_Clr iUARTx B ..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM >¥ UARTx_ISR_RXTO_Chk Ó iUARTx B * ___result Ó ø ..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM ?ú²UARTx_ISR_RXBF_Clr iUARTx B ..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM >· UARTx_ISR_RXBF_Chk Ó iUARTx B * ___result Ó ..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM >Ä UARTx_ISR_TXBE_Chk Ó iUARTx B * ___result Ó ø ..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM ?úÑUARTx_ISR_TXSE_Clr iUARTx B ..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM >Ö UARTx_ISR_TXSE_Chk Ó iUARTx B * ___result Ó $ ..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM ?£ãUARTx_TODR_TXDLY_LEN_Set iUARTx B A iSetValue W # Xtmpreg W Q ..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM >ì
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UARTx_TODR_TXDLY_LEN_Get W iUARTx B ^__result W P
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..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM ?¢òUARTx_TODR_RXTO_LEN_Set iUARTx B 5 iSetValue W Xtmpreg W Q ..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM >û
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UARTx_TODR_RXTO_LEN_Get W iUARTx B ^__result W P ..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM
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UARTx_RXBUF_Read W
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iUARTx B ^__result W P ..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM ?UARTx_TXBUF_Write iUARTx B ) iSetValue W ..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM
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UARTx_TXBUF_Read W
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iUARTx B ^__result W P ..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM ?UARTx_BGR_Write iUARTx B ) iSetValue W ..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM >
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UARTx_BGR_Read W iUARTx B ^__result W P L ..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM ?Ì¡UART_IRModulation_Init iModuFreq W ª iModuDutyCycle 8 iClk W m ZtempTZBRG W Z ZtempTH W < ..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM x ?½UART_Init x iUARTx B > ipara H L ..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM Z float >ÍÔ
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UART_BaudREGCalc W Z iBaudRate W Y iClk W ; ^__result W PVXtmpSPBRG W TVXtmpfloat  ` $ ..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM ô ?¥ìUART_SInit ô iUARTx B v ipara N X iCMU_Clocks T : Ypara2 þ T ä ..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM ?ãUART_Deinit ô ..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM ?ôUARTx_Deinit iUARTx B < 3 ..\Drivers\fm33a0xxev_uart.c d 4 ..\Drivers\ fm33a0xxev_uart.c & T 4 ..\Drivers\ fm33a0xxev_uart.c && d 4 ..\Drivers\ fm33a0xxev_uart.c +& T 4 ..\Drivers\ fm33a0xxev_uart.c 5& d 4 ..\Drivers\ fm33a0xxev_uart.c : T 4 ..\Drivers\ fm33a0xxev_uart.c Ä d 4 ..\Drivers\ fm33a0xxev_uart.c Ë -~ ` 4 ..\Drivers\ fm33a0xxev_uart.c Û )' d 4 ..\Drivers\ fm33a0xxev_uart.c æ -~ ` 4 ..\Drivers\ fm33a0xxev_uart.c ö )' d 4 ..\Drivers\ fm33a0xxev_uart.c -~ ` 4 ..\Drivers\ fm33a0xxev_uart.c & X 4 ..\Drivers\ fm33a0xxev_uart.c ` 4 ..\Drivers\ fm33a0xxev_uart.c ¢)' d 4 ..\Drivers\ fm33a0xxev_uart.c -~ ` 4 ..\Drivers\ fm33a0xxev_uart.c ¼& X 4 ..\Drivers\ fm33a0xxev_uart.c Å ` 4 ..\Drivers\ fm33a0xxev_uart.c Í& X 4 ..\Drivers\ fm33a0xxev_uart.c Ö ` 4 ..\Drivers\ fm33a0xxev_uart.c à X 4 ..\Drivers\ fm33a0xxev_uart.c é ` 4 ..\Drivers\ fm33a0xxev_uart.c ó X 4 ..\Drivers\ fm33a0xxev_uart.c ü ` 4 ..\Drivers\ fm33a0xxev_uart.c
)! d 4 ..\Drivers\ fm33a0xxev_uart.c '~ ` 4 ..\Drivers\ fm33a0xxev_uart.c )! d 4 ..\Drivers\ fm33a0xxev_uart.c «'~ ` 4 ..\Drivers\ fm33a0xxev_uart.c ¹)! d 4 ..\Drivers\ fm33a0xxev_uart.c Ä'~ ` 4 ..\Drivers\ fm33a0xxev_uart.c Ò)! d 4 ..\Drivers\ fm33a0xxev_uart.c Ý'~ ` 4 ..\Drivers\ fm33a0xxev_uart.c ì)' d 4 ..\Drivers\ fm33a0xxev_uart.c ÷-~ ` 4 ..\Drivers\ fm33a0xxev_uart.c
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W P V } x } Q x T P x U } } X }0X Z } Q Z W P Z d } } ò }0ò ô } R ô U Q ô T P ô V } } P __DATE__ "Jun 7 2024" __TIME__ "08:47:44" __STDC__ 1 __STDC_VERSION__ 199901L __STDC_HOSTED__ 1 __STDC_ISO_10646__ 200607 __EDG__ 1 __EDG_VERSION__ 407 __EDG_SIZE_TYPE__ unsigned int __EDG_PTRDIFF_TYPE__ int __GNUC__ 4 __GNUC_STDC_INLINE__ 1 __GNUC_MINOR__ 7 __GNUC_PATCHLEVEL__ 0 __VERSION__ "4.7 (EDG gcc mode)" __CHAR16_TYPE__ unsigned short __CHAR32_TYPE__ unsigned int __USER_LABEL_PREFIX__ __CHAR_UNSIGNED__ 1 __WCHAR_UNSIGNED__ 1 __SIZE_TYPE__ unsigned int __PTRDIFF_TYPE__ int __WCHAR_TYPE__ unsigned short __WINT_TYPE__ unsigned short __INTMAX_TYPE__ long long __UINTMAX_TYPE__ unsigned long long __sizeof_int 4 __sizeof_long 4 __sizeof_ptr 4 __ARMCC_VERSION 5060750 __TARGET_CPU_CORTEX_M0 1 __TARGET_FPU_SOFTVFP 1 __TARGET_FPU_SOFTVFP 1 __MICROLIB 1 __UVISION_VERSION 525 _RTE_ 1 __VTOR_PRESENT 1 __CC_ARM 1 __arm 1 __arm__ 1 __TARGET_ARCH_6S_M 1 __TARGET_ARCH_ARM 0 __TARGET_ARCH_THUMB 3 __TARGET_ARCH_A64 0 __TARGET_ARCH_AARCH32 1 __TARGET_PROFILE_M 1 __TARGET_FEATURE_HALFWORD 1 __TARGET_FEATURE_THUMB 1 __TARGET_FEATURE_DMB 1 __TARGET_FEATURE_EXTENSION_REGISTER_COUNT 0 __APCS_INTERWORK 1 __thumb 1 __thumb__ 1 __t32__ 1 __OPTIMISE_SPACE 1 __OPTIMIZE_SIZE__ 1 __OPTIMISE_LEVEL 0 __SOFTFP__ 1 '  UARTIR_CR_IRFLAG_Set '  UARTIR_CR_IRFLAG_Get #  UARTIR_CR_TH_Set #  UARTIR_CR_TH_Get &  UARTIR_CR_TZBRG_Set &  UARTIR_CR_TZBRG_Get %  UARTx_CSR_BUSY_Chk +  UARTx_CSR_TXIREN_Setable +  UARTx_CSR_TXIREN_Getable +  UARTx_CSR_RXTOEN_Setable +  UARTx_CSR_RXTOEN_Getable ' $  UARTx_CSR_IOSWAP_Set '  UARTx_CSR_IOSWAP_Get /  UARTx_CSR_DMATXIFCFG_Setable /  UARTx_CSR_DMATXIFCFG_Getable ' $  UARTx_CSR_BITORD_Set '  UARTx_CSR_BITORD_Get ( $  UARTx_CSR_STOPCFG_Set (  UARTx_CSR_STOPCFG_Get &  UARTx_CSR_PDSEL_Set &  UARTx_CSR_PDSEL_Get ' $  UARTx_CSR_PARITY_Set '  UARTx_CSR_PARITY_Get *  UARTx_CSR_RXPOL_Setable *  UARTx_CSR_RXPOL_Getable *  UARTx_CSR_TXPOL_Setable *  UARTx_CSR_TXPOL_Getable )  UARTx_CSR_RXEN_Setable )  UARTx_CSR_RXEN_Getable )  UARTx_CSR_TXEN_Setable )  UARTx_CSR_TXEN_Getable ,  UARTx_IER_RXTO_IE_Setable ,  UARTx_IER_RXTO_IE_Getable -  UARTx_IER_RXERR_IE_Setable -  UARTx_IER_RXERR_IE_Getable ,  UARTx_IER_RXBF_IE_Setable ,  UARTx_IER_RXBF_IE_Getable ,  UARTx_IER_TXBE_IE_Setable ,  UARTx_IER_TXBE_IE_Getable ,  UARTx_IER_TXSE_IE_Setable ,  UARTx_IER_TXSE_IE_Getable % ü  UARTx_ISR_PERR_Clr %  UARTx_ISR_PERR_Chk % ü  UARTx_ISR_FERR_Clr %  UARTx_ISR_FERR_Chk % ü  UARTx_ISR_OERR_Clr %  UARTx_ISR_OERR_Chk % ü  UARTx_ISR_RXTO_Clr %  UARTx_ISR_RXTO_Chk % ü  UARTx_ISR_RXBF_Clr %  UARTx_ISR_RXBF_Chk %  UARTx_ISR_TXBE_Chk % ü  UARTx_ISR_TXSE_Clr %  UARTx_ISR_TXSE_Chk + (  UARTx_TODR_TXDLY_LEN_Set +  UARTx_TODR_TXDLY_LEN_Get * $  UARTx_TODR_RXTO_LEN_Set *  UARTx_TODR_RXTO_LEN_Get #  UARTx_RXBUF_Read $  UARTx_TXBUF_Write #  UARTx_TXBUF_Read "  UARTx_BGR_Write !  UARTx_BGR_Read ) P  UART_IRModulation_Init  UART_Init # P Ë UART_BaudREGCalc (  UART_SInit è  UART_Deinit ø  UARTx_Deinit « % . ® ¯ __stdint_h __ARMCLIB_VERSION 5060037 __INT64 __int64 __INT64_C_SUFFIX__ ll __PASTE2(x,y) x ## y __PASTE(x,y) __PASTE2(x, y) __INT64_C(x) __ESCAPE__(__PASTE(x, __INT64_C_SUFFIX__)) __UINT64_C(x) __ESCAPE__(__PASTE(x ## u, __INT64_C_SUFFIX__)) __LONGLONG long long #__STDINT_DECLS %__CLIBNS ,__CLIBNS yINT8_MIN -128 zINT16_MIN -32768 {INT32_MIN (~0x7fffffff) |INT64_MIN __INT64_C(~0x7fffffffffffffff) INT8_MAX 127 INT16_MAX 32767 INT32_MAX 2147483647 INT64_MAX __INT64_C(9223372036854775807)
UINT8_MAX 255 UINT16_MAX 65535 UINT32_MAX 4294967295u UINT64_MAX __UINT64_C(18446744073709551615) INT_LEAST8_MIN -128 INT_LEAST16_MIN -32768 INT_LEAST32_MIN (~0x7fffffff) INT_LEAST64_MIN __INT64_C(~0x7fffffffffffffff) INT_LEAST8_MAX 127 INT_LEAST16_MAX 32767 INT_LEAST32_MAX 2147483647 INT_LEAST64_MAX __INT64_C(9223372036854775807) UINT_LEAST8_MAX 255 UINT_LEAST16_MAX 65535 UINT_LEAST32_MAX 4294967295u UINT_LEAST64_MAX __UINT64_C(18446744073709551615) ¡INT_FAST8_MIN (~0x7fffffff) ¢INT_FAST16_MIN (~0x7fffffff) £INT_FAST32_MIN (~0x7fffffff) ¤INT_FAST64_MIN __INT64_C(~0x7fffffffffffffff) §INT_FAST8_MAX 2147483647 ¨INT_FAST16_MAX 2147483647 ©INT_FAST32_MAX 2147483647 ªINT_FAST64_MAX __INT64_C(9223372036854775807) UINT_FAST8_MAX 4294967295u ®UINT_FAST16_MAX 4294967295u ¯UINT_FAST32_MAX 4294967295u °UINT_FAST64_MAX __UINT64_C(18446744073709551615) ¸INTPTR_MIN INT32_MIN ¿INTPTR_MAX INT32_MAX ÆUINTPTR_MAX UINT32_MAX ÌINTMAX_MIN __ESCAPE__(~0x7fffffffffffffffll) ÏINTMAX_MAX __ESCAPE__(9223372036854775807ll) ÒUINTMAX_MAX __ESCAPE__(18446744073709551615ull) ÛPTRDIFF_MIN INT32_MIN ÜPTRDIFF_MAX INT32_MAX àSIG_ATOMIC_MIN (~0x7fffffff) áSIG_ATOMIC_MAX 2147483647 çSIZE_MAX UINT32_MAX íWCHAR_MIN îWCHAR_MAX ôWCHAR_MIN 0 õWCHAR_MAX 65535 ùWINT_MIN (~0x7fffffff) úWINT_MAX 2147483647 INT8_C(x) (x) INT16_C(x) (x) INT32_C(x) (x) INT64_C(x) __INT64_C(x) UINT8_C(x) (x ## u) UINT16_C(x) (x ## u) UINT32_C(x) (x ## u) UINT64_C(x) __UINT64_C(x) INTMAX_C(x) __ESCAPE__(x ## ll) UINTMAX_C(x) __ESCAPE__(x ## ull) ¸__INT64 ¹__LONGLONG L B D:\Keil5\ARM\ARMCC\Bin\..\include\ stdint.h 0 D:\Keil5\ARM\ARMCC\Bin\..\include\stdint.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] signed char short int long long unsigned char unsigned short unsigned int unsigned long long Pint8_t 8 Pint16_t 9 Pint32_t : Pint64_t § ; Puint8_t ´ > Puint16_t Å ? Puint32_t × @ Puint64_t ç A Pu32 WCPu16 GDPu8 8EPuint8 8GPint_least8_t M Pint_least16_t N Pint_least32_t O Pint_least64_t § P Puint_least8_t ´ S Puint_least16_t Å T Puint_least32_t × U Puint_least64_t ç V Pint_fast8_t [ Pint_fast16_t \ Pint_fast32_t ] Pint_fast64_t § ^ Puint_fast8_t × a Puint_fast16_t × b Puint_fast32_t × c Puint_fast64_t ç d Pintptr_t k Puintptr_t × l Pintmax_t § p!Puintmax_t ç q! ± ² ³ '__CORE_CMINSTR_H <__NOP __nop D__WFI __wfi L__WFE __wfe S__SEV __sev \__ISB() do { __schedule_barrier(); __isb(0xF); __schedule_barrier(); } while (0) g__DSB() do { __schedule_barrier(); __dsb(0xF); __schedule_barrier(); } while (0) r__DMB() do { __schedule_barrier(); __dmb(0xF); __schedule_barrier(); } while (0) __REV __rev ©__ROR __ror ´__BKPT(value) __breakpoint(value) Ú__CLZ __clz @ 6 ..\Core\Include\ core_cminstr.h
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..\Core\Include\core_cminstr.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM ;Á9__RBIT W $W value a__result W \result W \s µ ¶ · '__CORE_CMFUNC_H @ 5 ..\Core\Include\ core_cmfunc.h
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..\Core\Include\core_cmfunc.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM ;ÿ@__get_CONTROL W a__result W Y__regControl W P <¸M__set_CONTROL $W control Y__regControl W P ;òZ__get_IPSR W a__result W Y__regIPSR W P ;¬g__get_APSR W a__result W Y__regAPSR W P ;æt__get_xPSR W a__result W Y__regXPSR W P ;¯__get_PSP W a__result W Y__regProcessStackPointer W P <ø__set_PSP $W topOfProcStack Y__regProcessStackPointer W P ;¾__get_MSP W a__result W Y__regMainStackPointer W P <¨__set_MSP $W topOfMainStack Y__regMainStackPointer W P ;ŵ__get_PRIMASK W a__result W Y__regPriMask W P <ÿÂ__set_PRIMASK $W priMask Y__regPriMask W P ¹ º » __CORE_CM0PLUS_H_GENERIC "@__CM0PLUS_CMSIS_VERSION_MAIN ( 5U) A__CM0PLUS_CMSIS_VERSION_SUB ( 0U) B__CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | __CM0PLUS_CMSIS_VERSION_SUB ) E__CORTEX_M (0U) Q__ASM __asm R__INLINE __inline S__STATIC_INLINE static __inline T__NO_RETURN __declspec(noreturn) U__USED __attribute__((used)) V__WEAK __attribute__((weak)) W__UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) __FPU_USED 0U ÆÇÒ__CORE_CM0PLUS_H_DEPENDANT ÿ__I volatile const __O volatile __IO volatile
__IM volatile const __OM volatile __IOM volatile ³APSR_N_Pos 31U ´APSR_N_Msk (1UL << APSR_N_Pos) ¶APSR_Z_Pos 30U ·APSR_Z_Msk (1UL << APSR_Z_Pos) ¹APSR_C_Pos 29U ºAPSR_C_Msk (1UL << APSR_C_Pos) ¼APSR_V_Pos 28U ½APSR_V_Msk (1UL << APSR_V_Pos) ÎIPSR_ISR_Pos 0U ÏIPSR_ISR_Msk (0x1FFUL ) æxPSR_N_Pos 31U çxPSR_N_Msk (1UL << xPSR_N_Pos) éxPSR_Z_Pos 30U êxPSR_Z_Msk (1UL << xPSR_Z_Pos) ìxPSR_C_Pos 29U íxPSR_C_Msk (1UL << xPSR_C_Pos) ïxPSR_V_Pos 28U ðxPSR_V_Msk (1UL << xPSR_V_Pos) òxPSR_T_Pos 24U óxPSR_T_Msk (1UL << xPSR_T_Pos) õxPSR_ISR_Pos 0U öxPSR_ISR_Msk (0x1FFUL ) CONTROL_SPSEL_Pos 1U CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) CONTROL_nPRIV_Pos 0U CONTROL_nPRIV_Msk (1UL ) ÈSCB_CPUID_IMPLEMENTER_Pos 24U ÉSCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) ËSCB_CPUID_VARIANT_Pos 20U ÌSCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) ÎSCB_CPUID_ARCHITECTURE_Pos 16U ÏSCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) ÑSCB_CPUID_PARTNO_Pos 4U ÒSCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) ÔSCB_CPUID_REVISION_Pos 0U ÕSCB_CPUID_REVISION_Msk (0xFUL ) ØSCB_ICSR_NMIPENDSET_Pos 31U ÙSCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) ÛSCB_ICSR_PENDSVSET_Pos 28U ÜSCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) ÞSCB_ICSR_PENDSVCLR_Pos 27U ßSCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) áSCB_ICSR_PENDSTSET_Pos 26U âSCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) äSCB_ICSR_PENDSTCLR_Pos 25U åSCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) çSCB_ICSR_ISRPREEMPT_Pos 23U èSCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) êSCB_ICSR_ISRPENDING_Pos 22U ëSCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) íSCB_ICSR_VECTPENDING_Pos 12U îSCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) ðSCB_ICSR_VECTACTIVE_Pos 0U ñSCB_ICSR_VECTACTIVE_Msk (0x1FFUL ) õSCB_VTOR_TBLOFF_Pos 8U öSCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) úSCB_AIRCR_VECTKEY_Pos 16U ûSCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) ýSCB_AIRCR_VECTKEYSTAT_Pos 16U þSCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) SCB_AIRCR_ENDIANESS_Pos 15U SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) SCB_AIRCR_SYSRESETREQ_Pos 2U SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) SCB_AIRCR_VECTCLRACTIVE_Pos 1U SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) SCB_SCR_SEVONPEND_Pos 4U SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) SCB_SCR_SLEEPDEEP_Pos 2U SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) SCB_SCR_SLEEPONEXIT_Pos 1U SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) SCB_CCR_STKALIGN_Pos 9U SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) SCB_CCR_UNALIGN_TRP_Pos 3U SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) SCB_SHCSR_SVCALLPENDED_Pos 15U SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) ´SysTick_CTRL_COUNTFLAG_Pos 16U µSysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) ·SysTick_CTRL_CLKSOURCE_Pos 2U ¸SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) ºSysTick_CTRL_TICKINT_Pos 1U »SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) ½SysTick_CTRL_ENABLE_Pos 0U ¾SysTick_CTRL_ENABLE_Msk (1UL ) ÁSysTick_LOAD_RELOAD_Pos 0U ÂSysTick_LOAD_RELOAD_Msk (0xFFFFFFUL ) ÅSysTick_VAL_CURRENT_Pos 0U ÆSysTick_VAL_CURRENT_Msk (0xFFFFFFUL ) ÉSysTick_CALIB_NOREF_Pos 31U ÊSysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) ÌSysTick_CALIB_SKEW_Pos 30U ÍSysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) ÏSysTick_CALIB_TENMS_Pos 0U ÐSysTick_CALIB_TENMS_Msk (0xFFFFFFUL ) éMPU_TYPE_IREGION_Pos 16U êMPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) ìMPU_TYPE_DREGION_Pos 8U íMPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) ïMPU_TYPE_SEPARATE_Pos 0U ðMPU_TYPE_SEPARATE_Msk (1UL ) óMPU_CTRL_PRIVDEFENA_Pos 2U ôMPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) öMPU_CTRL_HFNMIENA_Pos 1U ÷MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) ùMPU_CTRL_ENABLE_Pos 0U úMPU_CTRL_ENABLE_Msk (1UL ) ýMPU_RNR_REGION_Pos 0U þMPU_RNR_REGION_Msk (0xFFUL ) MPU_RBAR_ADDR_Pos 8U MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) MPU_RBAR_VALID_Pos 4U
MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) MPU_RBAR_REGION_Pos 0U MPU_RBAR_REGION_Msk (0xFUL ) MPU_RASR_ATTRS_Pos 16U MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) MPU_RASR_XN_Pos 28U MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) MPU_RASR_AP_Pos 24U MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) MPU_RASR_TEX_Pos 19U MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) MPU_RASR_S_Pos 18U MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) MPU_RASR_C_Pos 17U MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) MPU_RASR_B_Pos 16U MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) MPU_RASR_SRD_Pos 8U ¡MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) £MPU_RASR_SIZE_Pos 1U ¤MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) ¦MPU_RASR_ENABLE_Pos 0U §MPU_RASR_ENABLE_Msk (1UL ) Ä_VAL2FLD(field,value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) Ì_FLD2VAL(field,value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) ÙSCS_BASE (0xE000E000UL) ÚSysTick_BASE (SCS_BASE + 0x0010UL) ÛNVIC_BASE (SCS_BASE + 0x0100UL) ÜSCB_BASE (SCS_BASE + 0x0D00UL) ÞSCB ((SCB_Type *) SCB_BASE ) ßSysTick ((SysTick_Type *) SysTick_BASE ) àNVIC ((NVIC_Type *) NVIC_BASE ) ãMPU_BASE (SCS_BASE + 0x0D90UL) äMPU ((MPU_Type *) MPU_BASE ) _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) ..\Core\Include\ D:\Keil5\ARM\ARMCC\Bin\..\include\ core_cm0plus.h stdint.h core_cminstr.h core_cmfunc.h °
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..\Core\Include\core_cm0plus.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM *!_reserved0 W # !V W # !C W # !Z W # !N W # S§ b À w W PAPSR_Type °*å!ISR W # !_reserved0 W # Sø b 9 w W PIPSR_Type eË*!ISR W # !_reserved0 W # !T W # !_reserved1 W # !V W # !C W # !Z W # !N W # S¦ b w W PxPSR_Type ã*ø!nPRIV W # !SPSEL W # !_reserved1 W # S b 8 w W PCONTROL_Type x
* ® ISER ¥# ÅW RESERVED0 º#ß ICER Ö#÷W RSERVED1 ì# ISPR #©W RESERVED2 #Ä ICPR ;#ÜW RESERVED3 Q#ùW ? RESERVED4 n# IP # tW PNVIC_Type §*¹( CPUID ?# ICSR # VTOR # AIRCR # SCR # CCR # RESERVED1 W # SHP # SHCSR #$ W t9PSCB_Type ¸Å* CTRL # LOAD # VAL # CALIB ?# PSysTick_Type T±*Þ TYPE ?# CTRL # RNR # RBAR # RASR # PMPU_Type æ<
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NVIC_EnableIRQ $( IRQn <¶
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NVIC_DisableIRQ $( IRQn ;ò
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NVIC_GetPendingIRQ W $( IRQn a__result W < ÀNVIC_SetPendingIRQ $( IRQn <Â ÏNVIC_ClearPendingIRQ $( IRQn <ö áNVIC_SetPriority $( IRQn $W priority ;° ùNVIC_GetPriority W $( IRQn a__result W <Ê NVIC_SystemReset ;÷ ¬SCB_GetFPUType W a__result W ;° ËSysTick_Config W $W ticks a__result W ½ ¾ ¿ À __stdio_h __ARMCLIB_VERSION 5060037 "_ARMABI __declspec(__nothrow) %__STDIO_DECLS '__CLIBNS -__CLIBNS <NULL =NULL 0 g_SYS_OPEN 16 ¥stdin (&__CLIBNS __stdin) §stdout (&__CLIBNS __stdout) ©stderr (&__CLIBNS __stderr) ¬_IOFBF 0x100 _IOLBF 0x200 ®_IONBF 0x400 ±BUFSIZ (512) ³FOPEN_MAX _SYS_OPEN ¹FILENAME_MAX 256 ¾L_tmpnam FILENAME_MAX ÄTMP_MAX 256 ÌEOF (-1) ÒSEEK_SET 0 ÓSEEK_CUR 1 ÔSEEK_END 2 Ú_IOBIN 0x04 Ü__STDIN_BUFSIZ (64) Ý__STDOUT_BUFSIZ (64) Þ__STDERR_BUFSIZ (16) ¿getchar() getc(stdin) àputchar(c) putc(c, stdout) L A D:\Keil5\ARM\ARMCC\Bin\..\include\ stdio.h ´ D:\Keil5\ARM\ARMCC\Bin\..\include\stdio.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] unsigned int unsigned long long Psize_t 5P__va_list
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F *ó __state1 # __state2 # )¦__fpos_t_struct __pos # __mbstate Î # Pfpos_t ó a-__FILE PFILE 4lq__stdin <q__stdout <q__stderr <"<q__aeabi_stdin tq__aeabi_stdout tq__aeabi_stderr t l ¸ H __stdin V __stdout e __stderr x __aeabi_stdin __aeabi_stdout ¡ __aeabi_stderr Â Ã Ä $FM33A0XXEV_H .__RCHF_INITIAL_CLOCK (8000000) /__RCMF_CLOCK (2000000) 0__RCLP_CLOCK (32000) 1__XTLF_CLOCK (32768) n__CM0_REV 0x0100 o__MPU_PRESENT 1 p__VTOR_PRESENT 1 q__NVIC_PRIO_BITS 2 r__Vendor_SysTickConfig 0 uv¿FLASH_BASE (( uint32_t)0x00000000) ÀSRAM_BASE (( uint32_t)0x20000000) ÁPERIPH_BASE (( uint32_t)0x40000000) ÊPMU_BASE (PERIPH_BASE +0x00002000) ËDBG_BASE (PERIPH_BASE +0x00000000) ÌFLS_BASE (PERIPH_BASE +0x00001000) ÍRMU_BASE (PERIPH_BASE +0x00002800) ÎIWDT_BASE (PERIPH_BASE +0x00011400) ÏWWDT_BASE (PERIPH_BASE +0x00011800) ÐCMU_BASE (PERIPH_BASE +0x00002400) ÑCDIF_BASE (PERIPH_BASE +0x0001E000) ÒVRTC_BASE (PERIPH_BASE +0x0001F800) ÓSVD_BASE (PERIPH_BASE +0x00012800) ÔAES_BASE (PERIPH_BASE +0x00013800) ÕPAE_BASE (PERIPH_BASE +0x00001400) ÖHASH_BASE (PERIPH_BASE +0x00001800) ×RNG_BASE (PERIPH_BASE +0x00013C00) ØCOMP_BASE (PERIPH_BASE +0x00015400) ÙI2C0_BASE (PERIPH_BASE +0x00012400) ÚI2C1_BASE (PERIPH_BASE +0x00015000) ÛUARTIR_BASE (PERIPH_BASE +0x00017C00) ÜUART0_BASE (PERIPH_BASE +0x00012000) ÝUART1_BASE (PERIPH_BASE +0x00016800) ÞUART2_BASE (PERIPH_BASE +0x00016C00) ßUART3_BASE (PERIPH_BASE +0x00017000) àUART4_BASE (PERIPH_BASE +0x00017400) áUART5_BASE (PERIPH_BASE +0x00017800) âLPUART0_BASE (PERIPH_BASE +0x00014000) ãLPUART1_BASE (PERIPH_BASE +0x00014400) äSPI0_BASE (PERIPH_BASE +0x00010400) åSPI1_BASE (PERIPH_BASE +0x00010800) æSPI2_BASE (PERIPH_BASE +0x00014800) çSPI3_BASE (PERIPH_BASE +0x00014C00) èSPI4_BASE (PERIPH_BASE +0x00016400) éU7816_BASE (PERIPH_BASE +0x00011C00) êQSPI_BASE (PERIPH_BASE +0x00000800) ëDMA_BASE (PERIPH_BASE +0x00000400) ìCRC_BASE (PERIPH_BASE +0x00010000) íBT1_BASE (PERIPH_BASE +0x00013000) îBT2_BASE (PERIPH_BASE +0x00013044) ïET1_BASE (PERIPH_BASE +0x00013090) ðET2_BASE (PERIPH_BASE +0x000130B0) ñET3_BASE (PERIPH_BASE +0x000130D0) òET4_BASE (PERIPH_BASE +0x000130F0) óETCNT_BASE (PERIPH_BASE +0x00013110) ôBSTIM_BASE (PERIPH_BASE +0x00016000) õLPTIM_BASE (PERIPH_BASE +0x00013400) öRTC_BASE (PERIPH_BASE +0x00011000) ÷LCD_BASE (PERIPH_BASE +0x00010C00) øADC_BASE (PERIPH_BASE +0x0001FA00) ùCIC_BASE (PERIPH_BASE +0x00015C00) úGPIOA_BASE (PERIPH_BASE +0x00000C00) ûGPIOB_BASE (PERIPH_BASE +0x00000C40) üGPIOC_BASE (PERIPH_BASE +0x00000C80) ýGPIOD_BASE (PERIPH_BASE +0x00000CC0) þGPIOE_BASE (PERIPH_BASE +0x00000D00) ÿGPIOF_BASE (PERIPH_BASE +0x00000D40) GPIOG_BASE (PERIPH_BASE +0x00000D80) GPIOH_BASE (PERIPH_BASE +0x0001FC00) GPIO_BASE (PERIPH_BASE +0x00000DC0) PMU ((PMU_Type *) PMU_BASE ) DBG ((DBG_Type *) DBG_BASE ) FLS ((FLS_Type *) FLS_BASE ) RMU ((RMU_Type *) RMU_BASE ) IWDT ((IWDT_Type *) IWDT_BASE ) WWDT ((WWDT_Type *) WWDT_BASE ) CMU ((CMU_Type *) CMU_BASE ) CDIF ((CDIF_Type *) CDIF_BASE ) VRTC ((VRTC_Type *) VRTC_BASE ) SVD ((SVD_Type *) SVD_BASE ) AES ((AES_Type *) AES_BASE ) PAE ((PAE_Type *) PAE_BASE ) HASH ((HASH_Type *) HASH_BASE ) RNG ((RNG_Type *) RNG_BASE ) COMP ((COMP_Type *) COMP_BASE ) I2C0 ((I2C_Type *) I2C0_BASE ) I2C1 ((I2C_Type *) I2C1_BASE ) UARTIR ((UARTIR_Type *) UARTIR_BASE ) UART0 ((UART_Type *) UART0_BASE ) UART1 ((UART_Type *) UART1_BASE ) UART2 ((UART_Type *) UART2_BASE ) UART3 ((UART_Type *) UART3_BASE ) UART4 ((UART_Type *) UART4_BASE ) UART5 ((UART_Type *) UART5_BASE ) LPUART0 ((LPUART_Type *) LPUART0_BASE ) ¡LPUART1 ((LPUART_Type *) LPUART1_BASE ) ¢SPI0 ((SPI_Type *) SPI0_BASE ) £SPI1 ((SPI_Type *) SPI1_BASE ) ¤SPI2 ((SPI_Type *) SPI2_BASE ) ¥SPI3 ((SPI_Type *) SPI3_BASE ) ¦SPI4 ((SPI_Type *) SPI4_BASE ) §U7816 ((U7816_Type *) U7816_BASE ) ¨QSPI ((QSPI_Type *) QSPI_BASE ) ©DMA ((DMA_Type *) DMA_BASE ) ªCRC ((CRC_Type *) CRC_BASE ) «BT1 ((BT_Type *) BT1_BASE ) ¬BT2 ((BT_Type *) BT2_BASE ) ET1 ((ET_Type *) ET1_BASE ) ®ET2 ((ET_Type *) ET2_BASE ) ¯ET3 ((ET_Type *) ET3_BASE ) °ET4 ((ET_Type *) ET4_BASE ) ±ETCNT ((ETCNT_Type *) ETCNT_BASE ) ²BSTIM ((BSTIM_Type *) BSTIM_BASE ) ³LPTIM ((LPTIM_Type *) LPTIM_BASE ) ´RTC ((RTC_Type *) RTC_BASE ) µLCD ((LCD_Type *) LCD_BASE ) ¶ADC ((ADC_Type *) ADC_BASE ) ·CIC ((CIC_Type *) CIC_BASE ) ¸GPIOA ((GPIO_Type *) GPIOA_BASE ) ¹GPIOB ((GPIO_Type *) GPIOB_BASE ) ºGPIOC ((GPIO_Type *) GPIOC_BASE ) »GPIOD ((GPIO_Type *) GPIOD_BASE ) ¼GPIOE ((GPIO_Type *) GPIOE_BASE ) ½GPIOF ((GPIO_Type *) GPIOF_BASE ) ¾GPIOG ((GPIO_Type *) GPIOG_BASE ) ¿GPIOH ((GPIOH_Type *) GPIOH_BASE ) ÀGPIO ((GPIO_COMMON_Type *) GPIO_BASE ) h ] ..\Core\Include\ FM33A0XXEV.h core_cm0plus.h system_FM33A0XXEV.h ¬
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..\Core\Include\FM33A0XXEV.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM ÓRESET SET PFlagStatus ¾ *(PITStatus ¾ *4DISABLE ENABLE PFunState õ +/´FAIL PASS PErrorStatus ,'¨Reset_IRQn qNMI_IRQn rHardFault_IRQn sSVC_IRQn {PendSV_IRQn ~SysTick_IRQn WWDT_IRQn SVD_IRQn RTC_IRQn FLASH_IRQn CMU_IRQn ADC_IRQn SPI0_IRQn SPI1_IRQn SPI2_IRQn UART0_IRQn UART1_IRQn
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UART2_IRQn UART3_IRQn UART4_IRQn UART5_IRQn U7816_IRQn LPUART0_IRQn I2Cx_IRQn RSV_IRQn CRYPTO_IRQn LPTIM_IRQn DMA_IRQn WKUPx_IRQn COMP_IRQn BTx_IRQn QSPI_IRQn ETx_IRQn BSTIM_IRQn SPI3_IRQn SPI4_IRQn GPIO_IRQn LPUART1_IRQn PIRQn_Type Gb*ö CR v# WKTR v# WKFR v# IER v# ISR v# tW PPMU_Type 9*´ RSV1 v# CR v# HDFR v# PDBG_Type ¨* X RDCR v# PFCR v# OPTBR #÷v RSV1 î# EPCR v# KEY v# IER v# ISR v# ¹v RSV2 0#$ ACLOCK1 v#H ACLOCK2 v#L ACLOCK3 v#P ACLOCK4 v#T W tPFLS_Type ž*
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$ PDRCR v# BORCR v# RSTCFGR v# SOFTRST v# RSR v# PRSTEN v# AHBRST v# APBRST1 v# APBRST2 v# PRMU_Type Ð*Ù
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SERV v# CFGR v# CNTR # PIWDT_Type 0Ü*´ CR v# CFGR v# CNTR # IER v# ISR v# PSCR # PWWDT_Type kë* 8 SYSCLKCR v# RCHFCR v# RCHFTR v# PLLLCR v# PLLHCR v# XTHFCR v# IER v# ISR v# PCLKCR1 v# PCLKCR2 v#$ PCLKCR3 v#( PCLKCR4 v#, OPCCR1 v#0 OPCCR2 v#4 PCMU_Type Æ*» CR v# PSCR v# PCDIF_Type *Õ0 PDRCR v# ç v RSV1 Þ# RCMFCR v# RCLPCR v# RCLPTR v# XTLFCR v# ADCCR v#$ LFDIER v#( LFDISR v#, PVRTC_Type Í*£ CFGR v# CR v# IER v# ISR v# VSR v# PSVD_Type g¬*§T CR v# IER v# ISR v# DIR v# DOR # KEY0 v# KEY1 v# KEY2 v# KEY3 v# KEY4 v#$ KEY5 v#( KEY6 v#, KEY7 v#0 IVR0 v#4 IVR1 v#8 IVR2 v#< IVR3 v#@ H0 v#D H1 v#H H2 v#L H3 v#P PAES_Type ´Ê* CSR v# MLR v# MPR v# M0CFG v# M1CFG v# M2CFG v# M3CFG v# WORD v# PPAE_Type ¸Û*Ê CSR v# DTR v# PHASH_Type / æ*À CR v# DOR #þv RSV1 u # SR v# CRC_CR v# CRC_DIR v# CRC_SR v# PRNG_Type \ ö* CR1 v# CR2 v# ICR v# ISR v# PCR v# PCOMP_Type Ñ *$ CFGR v# CR v# IER v# ISR v# SR v# BRG v# BUF v# TIMING v# TO v# PI2C_Type
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*¨ CR v# PUARTIR_Type
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* CSR v# IER v# ISR v# TODR v# RXBUF # TXBUF v# BGR v# PUART_Type ¼
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°*û CSR v# IER v# ISR v# BMR v# RXBUF v# TXBUF v# DMR v# PLPUART_Type % À*å CR1 v# CR2 v# CR3 v# IER v# ISR v# TXBUF v# RXBUF # PSPI_Type Ð*â$ CR v# FFR v# EGTR v# PSC v# BGR v# RXBUF # TXBUF v# IER v# ISR v# PU7816_Type ö â*0 CR v# CFG v# SR v# DATALEN v# CCR v# ADDR v# ABR v# DR v# SMSK v# SMAT v#$ PITV v#( TO v#, PQSPI_Type u ÷*õ ¸ GCR v# CH0CR v# CH0MAR v# CH1CR v# CH1MAR v# CH2CR v# CH2MAR v# CH3CR v# CH3MAR v# CH4CR v#$ CH4MAR v#( CH5CR v#, CH5MAR v#0 CH6CR v#4 CH6MAR v#8 CH7CR v#< CH7MAR v#@ CH8CR v#D CH8MAR v#H CH9CR v#L CH9MAR v#P CH10CR v#T CH10MAR v#X CH11CR v#\ CH11FAR v#` CH11RAR v#d ISR v#h v$ RSV1 #l CH0CSR v# CH0MASR v# CH1CSR v# CH1MASR v# CH2CSR v# CH2MASR v# CH3CSR v# CH3MASR v# CH4CSR v# CH4MASR v#¤ CH5CSR v#¨ CH5MASR v#¬ CH6CSR v#° CH6MASR v#´ PDMA_Type ª*× DR v# CR v# LFSR v# XOR v# ¾ v RSV1 µ# POLY v# PCRC_Type ¹*¾!D CR1 v# CR2 v# CFGR1 v# CFGR2 v# PRES v# LOADCR v# CNTL # CNTH # PRESET v# LOADL v#$ LOADH v#( CMPL v#, CMPH v#0 OUTCNT v#4 OCR v#8 IER v#< ISR v#@ PBT_Type èÓ*°" CR v# INSR v# PSCR1 v# PSCR2 v# IVR v# CMPR v# IER v# ISR v# PET_Type Îä*õ" CNT1 v# CNT2 v# CNT3 v# CNT4 v# PETCNT_Type @ï*$0 CR1 v# CR2 v# RSV1 v# IER v# ISR v# EGR v#Ø#v RSV2 Ï# CNTR v#$ PSCR v#( ARR v#, PBSTIM_Type *«%0 CFGR v# CNTR # CCSR v# ARR v# IER v# ISR v# CR v# RSV1 v# CCR1 v# CCR2 v#$ CCR3 v#( CCR4 v#, PLPTIM_Type *ø' WER v# IER v# ISR v# BCDSEC v# BCDMIN v# BCDHOUR v# BCDDATE v# BCDWEEK v# BCDMONTH v# BCDYEAR v#$ ALARM v#( TMSEL v#, ADJUST v#0 ADSIGN v#4 VCAL v#8 MSCNT v#< CALSTEP v#@ ADCNT #D SSR #H SSA v#L DTR v#Pá'v RSV1 Ø#T CR v#| PRTC_Type ¾¶*¿*` CR v# TEST v# FCR v# FLKT v# RSV1 v# IER v# ISR v#å(v RSV2 \# DATA0 v#$ DATA1 v#( DATA2 v#, DATA3 v#0 DATA4 v#4 DATA5 v#8 DATA6 v#< DATA7 v#@ DATA8 v#D DATA9 v#Hü)v RSV3 ó#L COMEN v#P SEGEN0 v#T SEGEN1 v#X BSTCR v#\ PLCD_Type Õ*+ CR v# TRIM v# DR # ISR v# CFGR v# PADC_Type Pã*×+ DR # OS v# USDR # CR v# ISR v# PCIC_Type ñ*ë,, INEN v# PUEN v# ODEN v# FCR v# DO v# DSET v# DRST v# DIN # DFS v# RSV v#$ ANEN v#( PGPIO_Type è
*º- INEN v# PUEN v# FCR v# DO v# DIN v# PGPIOH_Type }*/Ä EXTISEL0 v# EXTISEL1 v# EXTIEDS0 v# EXTIEDS1 v# EXTIDF v# EXTIISR v# EXTIDI #Æ.v RSV1 =# FOUTSEL v#@ IOMCR v#D÷.v= RSV2 n#H PINWKEN v#À PGPIO_COMMON_Type ͦ Æ Ç È É (SYSTEM_FM33A0XXEV_H 234O__SYSTEM_CLOCK (8000000) PDELAY_US (__SYSTEM_CLOCK/1000000) QDELAY_MS (__SYSTEM_CLOCK/1000) TDo_DelayStart() { uint32_t LastTick = SysTick->VAL; do { WWhile_DelayMsEnd(Count) }while(((LastTick - SysTick->VAL)&0xFFFFFF)<DELAY_MS*Count); } ZWhile_DelayUsEnd(Count) }while(((LastTick - SysTick->VAL)&0xFFFFFF)<DELAY_US*Count); }
..\Core\Include\ D:\Keil5\ARM\ARMCC\Bin\..\include\ system_FM33A0XXEV.h stdint.h stdio.h FM33A0XXEV.h Ü
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..\Core\Include\system_FM33A0XXEV.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM qSystemCoreClock W " à Å SystemCoreClock Ë Ì Í __FM33A0XXEV_CMU_H HXVAR(object,addr) (*((object *) (addr))) const_rchf_Trim8 HXVAR( uint32_t, 0x1FFFFB40 ) const_rchf_Trim16 HXVAR( uint32_t, 0x1FFFFB3C ) const_rchf_Trim24 HXVAR( uint32_t, 0x1FFFFB38 ) const_rchf_Trim32 HXVAR( uint32_t, 0x1FFFFB34) !__XTHF_CLOCK (12000000) RCMU_SYSCLKCR_SLP_ENEXTI_Pos 25 SCMU_SYSCLKCR_SLP_ENEXTI_Msk (0x1U << CMU_SYSCLKCR_SLP_ENEXTI_Pos) UCMU_SYSCLKCR_APBPRES_Pos 16 [CMU_SYSCLKCR_APBPRES_Msk (0x7U << CMU_SYSCLKCR_APBPRES_Pos) \CMU_SYSCLKCR_APBPRES_DIV1 (0x0U << CMU_SYSCLKCR_APBPRES_Pos) ]CMU_SYSCLKCR_APBPRES_DIV2 (0x4U << CMU_SYSCLKCR_APBPRES_Pos) ^CMU_SYSCLKCR_APBPRES_DIV4 (0x5U << CMU_SYSCLKCR_APBPRES_Pos) _CMU_SYSCLKCR_APBPRES_DIV8 (0x6U << CMU_SYSCLKCR_APBPRES_Pos) `CMU_SYSCLKCR_APBPRES_DIV16 (0x7U << CMU_SYSCLKCR_APBPRES_Pos) bCMU_SYSCLKCR_AHBPRES_Pos 8 hCMU_SYSCLKCR_AHBPRES_Msk (0x7U << CMU_SYSCLKCR_AHBPRES_Pos) iCMU_SYSCLKCR_AHBPRES_DIV1 (0x0U << CMU_SYSCLKCR_AHBPRES_Pos) jCMU_SYSCLKCR_AHBPRES_DIV2 (0x4U << CMU_SYSCLKCR_AHBPRES_Pos) kCMU_SYSCLKCR_AHBPRES_DIV4 (0x5U << CMU_SYSCLKCR_AHBPRES_Pos) lCMU_SYSCLKCR_AHBPRES_DIV8 (0x6U << CMU_SYSCLKCR_AHBPRES_Pos) mCMU_SYSCLKCR_AHBPRES_DIV16 (0x7U << CMU_SYSCLKCR_AHBPRES_Pos) oCMU_SYSCLKCR_STCLKSEL_Pos 6 tCMU_SYSCLKCR_STCLKSEL_Msk (0x3U << CMU_SYSCLKCR_STCLKSEL_Pos) uCMU_SYSCLKCR_STCLKSEL_SCLK (0x0U << CMU_SYSCLKCR_STCLKSEL_Pos) vCMU_SYSCLKCR_STCLKSEL_LSCLK (0x1U << CMU_SYSCLKCR_STCLKSEL_Pos) wCMU_SYSCLKCR_STCLKSEL_RC4M (0x2U << CMU_SYSCLKCR_STCLKSEL_Pos) xCMU_SYSCLKCR_STCLKSEL_SYSCLK (0x3U << CMU_SYSCLKCR_STCLKSEL_Pos) zCMU_SYSCLKCR_SYSCLKSEL_Pos 0 {CMU_SYSCLKCR_SYSCLKSEL_Msk (0x7U << CMU_SYSCLKCR_SYSCLKSEL_Pos) |CMU_SYSCLKCR_SYSCLKSEL_RCHF (0x0U << CMU_SYSCLKCR_SYSCLKSEL_Pos) }CMU_SYSCLKCR_SYSCLKSEL_XTHF (0x1U << CMU_SYSCLKCR_SYSCLKSEL_Pos) ~CMU_SYSCLKCR_SYSCLKSEL_PLL_H (0x2U << CMU_SYSCLKCR_SYSCLKSEL_Pos) CMU_SYSCLKCR_SYSCLKSEL_LSCLK (0x3U << CMU_SYSCLKCR_SYSCLKSEL_Pos) CMU_RCHFCR_FSEL_Pos 16 CMU_RCHFCR_FSEL_Msk (0xfU << CMU_RCHFCR_FSEL_Pos) CMU_RCHFCR_FSEL_8MHZ (0x0U << CMU_RCHFCR_FSEL_Pos) CMU_RCHFCR_FSEL_16MHZ (0x1U << CMU_RCHFCR_FSEL_Pos) CMU_RCHFCR_FSEL_24MHZ (0x2U << CMU_RCHFCR_FSEL_Pos) CMU_RCHFCR_FSEL_32MHZ (0x3U << CMU_RCHFCR_FSEL_Pos) CMU_RCHFCR_RCHFEN_Pos 0 CMU_RCHFCR_RCHFEN_Msk (0x1U << CMU_RCHFCR_RCHFEN_Pos) CMU_RCHFTR_RCHFTRIM_Pos 0 CMU_RCHFTR_RCHFTRIM_Msk (0xffU << CMU_RCHFTR_RCHFTRIM_Pos) CMU_PLLLCR_PLLDB_Pos 16 CMU_PLLLCR_PLLDB_Msk (0x3ffU << CMU_PLLLCR_PLLDB_Pos) CMU_PLLLCR_LOCKED_Pos 7 CMU_PLLLCR_LOCKED_Msk (0x1U << CMU_PLLLCR_LOCKED_Pos) CMU_PLLLCR_PLLEN_Pos 0 £CMU_PLLLCR_PLLEN_Msk (0x1U << CMU_PLLLCR_PLLEN_Pos) ¥CMU_PLLHCR_PLLHDB_Pos 16 ¨CMU_PLLHCR_PLLHDB_Msk (0x3ffU << CMU_PLLHCR_PLLHDB_Pos) ©CMU_PLLHCR_PLLHDB_X32 (0x1fU << CMU_PLLHCR_PLLHDB_Pos) ªCMU_PLLHCR_PLLHDB_X48 (0x2fU << CMU_PLLHCR_PLLHDB_Pos) «CMU_PLLHCR_PLLHDB_X64 (0x3fU << CMU_PLLHCR_PLLHDB_Pos) CMU_PLLHCR_LOCKED_Pos 7 °CMU_PLLHCR_LOCKED_Msk (0x1U << CMU_PLLHCR_LOCKED_Pos) ²CMU_PLLHCR_REFPRSC_Pos 4 »CMU_PLLHCR_REFPRSC_Msk (0x7U << CMU_PLLHCR_REFPRSC_Pos) ¼CMU_PLLHCR_REFPRSC_DIV1 (0x0U << CMU_PLLHCR_REFPRSC_Pos) ½CMU_PLLHCR_REFPRSC_DIV2 (0x1U << CMU_PLLHCR_REFPRSC_Pos) ¾CMU_PLLHCR_REFPRSC_DIV4 (0x2U << CMU_PLLHCR_REFPRSC_Pos) ¿CMU_PLLHCR_REFPRSC_DIV8 (0x3U << CMU_PLLHCR_REFPRSC_Pos) ÀCMU_PLLHCR_REFPRSC_DIV12 (0x4U << CMU_PLLHCR_REFPRSC_Pos) ÁCMU_PLLHCR_REFPRSC_DIV16 (0x5U << CMU_PLLHCR_REFPRSC_Pos) ÂCMU_PLLHCR_REFPRSC_DIV24 (0x6U << CMU_PLLHCR_REFPRSC_Pos) ÃCMU_PLLHCR_REFPRSC_DIV32 (0x7U << CMU_PLLHCR_REFPRSC_Pos) ÅCMU_PLLHCR_OSEL_Pos 3 ÈCMU_PLLHCR_OSEL_Msk (0x1U << CMU_PLLHCR_OSEL_Pos) ÉCMU_PLLHCR_OSEL_X1 (0x0U << CMU_PLLHCR_OSEL_Pos) ÊCMU_PLLHCR_OSEL_X2 (0x1U << CMU_PLLHCR_OSEL_Pos) ÌCMU_PLLHCR_INSEL_Pos 1 ÏCMU_PLLHCR_INSEL_Msk (0x1U << CMU_PLLHCR_INSEL_Pos) ÐCMU_PLLHCR_INSEL_RCHF (0x0U << CMU_PLLHCR_INSEL_Pos) ÑCMU_PLLHCR_INSEL_XTHF (0x1U << CMU_PLLHCR_INSEL_Pos) ÓCMU_PLLHCR_EN_Pos 0 ÖCMU_PLLHCR_EN_Msk (0x1U << CMU_PLLHCR_EN_Pos) ØCMU_XTHFCR_XTHF_CFG_Pos 8 ÛCMU_XTHFCR_XTHF_CFG_Msk (0x7U << CMU_XTHFCR_XTHF_CFG_Pos) ÜCMU_XTHFCR_XTHF_CFG_MIN (0x0U << CMU_XTHFCR_XTHF_CFG_Pos) ÝCMU_XTHFCR_XTHF_CFG_MAX (0x7U << CMU_XTHFCR_XTHF_CFG_Pos) ßCMU_XTHFCR_XTHFEN_Pos 0 âCMU_XTHFCR_XTHFEN_Msk (0x1U << CMU_XTHFCR_XTHFEN_Pos) æCMU_IER_SYSCSE_IE_Pos 1 çCMU_IER_SYSCSE_IE_Msk (0x1U << CMU_IER_SYSCSE_IE_Pos) éCMU_IER_HFDET_IE_Pos 0 êCMU_IER_HFDET_IE_Msk (0x1U << CMU_IER_HFDET_IE_Pos) íCMU_ISR_HFDETO_Pos 8 ðCMU_ISR_HFDETO_Msk (0x1U << CMU_ISR_HFDETO_Pos) òCMU_ISR_SYSCSE_IF_Pos 1 óCMU_ISR_SYSCSE_IF_Msk (0x1U << CMU_ISR_SYSCSE_IF_Pos) õCMU_ISR_HFDET_IF_Pos 0 öCMU_ISR_HFDET_IF_Msk (0x1U << CMU_ISR_HFDET_IF_Pos) øCMU_PCLKCR1_COMP_PCE_Pos 9 ùCMU_PCLKCR1_COMP_PCE_Msk (0x1U << CMU_PCLKCR1_COMP_PCE_Pos) ûCMU_PCLKCR1_SVD_PCE_Pos 8 üCMU_PCLKCR1_SVD_PCE_Msk (0x1U << CMU_PCLKCR1_SVD_PCE_Pos) þCMU_PCLKCR1_PAD_PCE_Pos 7 ÿCMU_PCLKCR1_PAD_PCE_Msk (0x1U << CMU_PCLKCR1_PAD_PCE_Pos) CMU_PCLKCR1_ANAC_PCE_Pos 6 CMU_PCLKCR1_ANAC_PCE_Msk (0x1U << CMU_PCLKCR1_ANAC_PCE_Pos)
CMU_PCLKCR1_IWDT_PCE_Pos 5 CMU_PCLKCR1_IWDT_PCE_Msk (0x1U << CMU_PCLKCR1_IWDT_PCE_Pos) CMU_PCLKCR1_SCU_PCE_Pos 4 CMU_PCLKCR1_SCU_PCE_Msk (0x1U << CMU_PCLKCR1_SCU_PCE_Pos) CMU_PCLKCR1_PMU_PCE_Pos 3 CMU_PCLKCR1_PMU_PCE_Msk (0x1U << CMU_PCLKCR1_PMU_PCE_Pos) CMU_PCLKCR1_RTC_PCE_Pos 2 CMU_PCLKCR1_RTC_PCE_Msk (0x1U << CMU_PCLKCR1_RTC_PCE_Pos) CMU_PCLKCR1_LPT_PCE_Pos 0 CMU_PCLKCR1_LPT_PCE_Msk (0x1U << CMU_PCLKCR1_LPT_PCE_Pos) CMU_PCLKCR2_PAE_PCE_Pos 17 CMU_PCLKCR2_PAE_PCE_Msk (0x1U << CMU_PCLKCR2_PAE_PCE_Pos) CMU_PCLKCR2_SHA_PCE_Pos 16 CMU_PCLKCR2_SHA_PCE_Msk (0x1U << CMU_PCLKCR2_SHA_PCE_Pos) CMU_PCLKCR2_CIC_PCE_Pos 8 CMU_PCLKCR2_CIC_PCE_Msk (0x1U << CMU_PCLKCR2_CIC_PCE_Pos) CMU_PCLKCR2_WWDT_PCE_Pos 7 CMU_PCLKCR2_WWDT_PCE_Msk (0x1U << CMU_PCLKCR2_WWDT_PCE_Pos) CMU_PCLKCR2_RAMBIST_PCE_Pos 6 ¡CMU_PCLKCR2_RAMBIST_PCE_Msk (0x1U << CMU_PCLKCR2_RAMBIST_PCE_Pos) £CMU_PCLKCR2_NVM_PCE_Pos 5 ¤CMU_PCLKCR2_NVM_PCE_Msk (0x1U << CMU_PCLKCR2_NVM_PCE_Pos) ¦CMU_PCLKCR2_DMA_PCE_Pos 4 §CMU_PCLKCR2_DMA_PCE_Msk (0x1U << CMU_PCLKCR2_DMA_PCE_Pos) ©CMU_PCLKCR2_LCD_PCE_Pos 3 ªCMU_PCLKCR2_LCD_PCE_Msk (0x1U << CMU_PCLKCR2_LCD_PCE_Pos) ¬CMU_PCLKCR2_AES_PCE_Pos 2 CMU_PCLKCR2_AES_PCE_Msk (0x1U << CMU_PCLKCR2_AES_PCE_Pos) ¯CMU_PCLKCR2_TRNG_PCE_Pos 1 °CMU_PCLKCR2_TRNG_PCE_Msk (0x1U << CMU_PCLKCR2_TRNG_PCE_Pos) ²CMU_PCLKCR2_CRC_PCE_Pos 0 ³CMU_PCLKCR2_CRC_PCE_Msk (0x1U << CMU_PCLKCR2_CRC_PCE_Pos) µCMU_PCLKCR3_I2C1_PCE_Pos 25 ¶CMU_PCLKCR3_I2C1_PCE_Msk (0x1U << CMU_PCLKCR3_I2C1_PCE_Pos) ¸CMU_PCLKCR3_I2C0_PCE_Pos 24 ¹CMU_PCLKCR3_I2C0_PCE_Msk (0x1U << CMU_PCLKCR3_I2C0_PCE_Pos) »CMU_PCLKCR3_LPUART1_PCE_Pos 18 ¼CMU_PCLKCR3_LPUART1_PCE_Msk (0x1U << CMU_PCLKCR3_LPUART1_PCE_Pos) ¾CMU_PCLKCR3_U7816_PCE_Pos 16 ¿CMU_PCLKCR3_U7816_PCE_Msk (0x1U << CMU_PCLKCR3_U7816_PCE_Pos) ÁCMU_PCLKCR3_LPUART0_PCE_Pos 15 ÂCMU_PCLKCR3_LPUART0_PCE_Msk (0x1U << CMU_PCLKCR3_LPUART0_PCE_Pos) ÄCMU_PCLKCR3_UICR_PCE_Pos 14 ÅCMU_PCLKCR3_UICR_PCE_Msk (0x1U << CMU_PCLKCR3_UICR_PCE_Pos) ÇCMU_PCLKCR3_UART5_PCE_Pos 13 ÈCMU_PCLKCR3_UART5_PCE_Msk (0x1U << CMU_PCLKCR3_UART5_PCE_Pos) ÊCMU_PCLKCR3_UART4_PCE_Pos 12 ËCMU_PCLKCR3_UART4_PCE_Msk (0x1U << CMU_PCLKCR3_UART4_PCE_Pos) ÍCMU_PCLKCR3_UART3_PCE_Pos 11 ÎCMU_PCLKCR3_UART3_PCE_Msk (0x1U << CMU_PCLKCR3_UART3_PCE_Pos) ÐCMU_PCLKCR3_UART2_PCE_Pos 10 ÑCMU_PCLKCR3_UART2_PCE_Msk (0x1U << CMU_PCLKCR3_UART2_PCE_Pos) ÓCMU_PCLKCR3_UART1_PCE_Pos 9 ÔCMU_PCLKCR3_UART1_PCE_Msk (0x1U << CMU_PCLKCR3_UART1_PCE_Pos) ÖCMU_PCLKCR3_UART0_PCE_Pos 8 ×CMU_PCLKCR3_UART0_PCE_Msk (0x1U << CMU_PCLKCR3_UART0_PCE_Pos) ÙCMU_PCLKCR3_QSPI_PCE_Pos 7 ÚCMU_PCLKCR3_QSPI_PCE_Msk (0x1U << CMU_PCLKCR3_QSPI_PCE_Pos) ÜCMU_PCLKCR3_SPI4_PCE_Pos 4 ÝCMU_PCLKCR3_SPI4_PCE_Msk (0x1U << CMU_PCLKCR3_SPI4_PCE_Pos) ßCMU_PCLKCR3_SPI3_PCE_Pos 3 àCMU_PCLKCR3_SPI3_PCE_Msk (0x1U << CMU_PCLKCR3_SPI3_PCE_Pos) âCMU_PCLKCR3_SPI2_PCE_Pos 2 ãCMU_PCLKCR3_SPI2_PCE_Msk (0x1U << CMU_PCLKCR3_SPI2_PCE_Pos) åCMU_PCLKCR3_SPI1_PCE_Pos 1 æCMU_PCLKCR3_SPI1_PCE_Msk (0x1U << CMU_PCLKCR3_SPI1_PCE_Pos) èCMU_PCLKCR3_SPI0_PCE_Pos 0 éCMU_PCLKCR3_SPI0_PCE_Msk (0x1U << CMU_PCLKCR3_SPI0_PCE_Pos) ëCMU_PCLKCR4_ET4_PCE_Pos 6 ìCMU_PCLKCR4_ET4_PCE_Msk (0x1U << CMU_PCLKCR4_ET4_PCE_Pos) îCMU_PCLKCR4_ET3_PCE_Pos 5 ïCMU_PCLKCR4_ET3_PCE_Msk (0x1U << CMU_PCLKCR4_ET3_PCE_Pos) ñCMU_PCLKCR4_ET2_PCE_Pos 4 òCMU_PCLKCR4_ET2_PCE_Msk (0x1U << CMU_PCLKCR4_ET2_PCE_Pos) ôCMU_PCLKCR4_ET1_PCE_Pos 3 õCMU_PCLKCR4_ET1_PCE_Msk (0x1U << CMU_PCLKCR4_ET1_PCE_Pos) ÷CMU_PCLKCR4_BT2_PCE_Pos 2 øCMU_PCLKCR4_BT2_PCE_Msk (0x1U << CMU_PCLKCR4_BT2_PCE_Pos) úCMU_PCLKCR4_BT1_PCE_Pos 1 ûCMU_PCLKCR4_BT1_PCE_Msk (0x1U << CMU_PCLKCR4_BT1_PCE_Pos) ýCMU_PCLKCR4_BSTIM_PCE_Pos 0 þCMU_PCLKCR4_BSTIM_PCE_Msk (0x1U << CMU_PCLKCR4_BSTIM_PCE_Pos) CMU_OPCCR1_EXTICKE_Pos 31 CMU_OPCCR1_EXTICKE_Msk (0x1U << CMU_OPCCR1_EXTICKE_Pos) CMU_OPCCR1_EXTICKSEL_Pos 30 CMU_OPCCR1_EXTICKSEL_Msk (0x1U << CMU_OPCCR1_EXTICKSEL_Pos)
CMU_OPCCR1_EXTICKSEL_LSCLK (0x1U << CMU_OPCCR1_EXTICKSEL_Pos) CMU_OPCCR1_EXTICKSEL_HCLK (0x0U << CMU_OPCCR1_EXTICKSEL_Pos) CMU_OPCCR1_LPUART1CKE_Pos 29 CMU_OPCCR1_LPUART1CKE_Msk (0x1U << CMU_OPCCR1_LPUART1CKE_Pos) CMU_OPCCR1_LPUART0CKE_Pos 28 CMU_OPCCR1_LPUART0CKE_Msk (0x1U << CMU_OPCCR1_LPUART0CKE_Pos) CMU_OPCCR1_LPUART1CKS_Pos 26 CMU_OPCCR1_LPUART1CKS_Msk (0x3U << CMU_OPCCR1_LPUART1CKS_Pos) CMU_OPCCR1_LPUART1CKS_LSCLK (0x0U << CMU_OPCCR1_LPUART1CKS_Pos) CMU_OPCCR1_LPUART1CKS_RCHF (0x1U << CMU_OPCCR1_LPUART1CKS_Pos) CMU_OPCCR1_LPUART0CKS_Pos 24 CMU_OPCCR1_LPUART0CKS_Msk (0x3U << CMU_OPCCR1_LPUART0CKS_Pos) CMU_OPCCR1_LPUART0CKS_LSCLK (0x0U << CMU_OPCCR1_LPUART0CKS_Pos) CMU_OPCCR1_LPUART0CKS_RCHF (0x1U << CMU_OPCCR1_LPUART0CKS_Pos) CMU_OPCCR1_I2C1CKE_Pos 21 ¡CMU_OPCCR1_I2C1CKE_Msk (0x1U << CMU_OPCCR1_I2C1CKE_Pos) £CMU_OPCCR1_I2C0CKE_Pos 20 ¤CMU_OPCCR1_I2C0CKE_Msk (0x1U << CMU_OPCCR1_I2C0CKE_Pos) ¦CMU_OPCCR1_I2C1CKS_Pos 18 «CMU_OPCCR1_I2C1CKS_Msk (0x3U << CMU_OPCCR1_I2C1CKS_Pos) ¬CMU_OPCCR1_I2C1CKS_APBCLK (0x0U << CMU_OPCCR1_I2C1CKS_Pos) CMU_OPCCR1_I2C1CKS_RCHF (0x1U << CMU_OPCCR1_I2C1CKS_Pos) ®CMU_OPCCR1_I2C1CKS_SYSCLK (0x2U << CMU_OPCCR1_I2C1CKS_Pos) °CMU_OPCCR1_I2C0CKS_Pos 16 µCMU_OPCCR1_I2C0CKS_Msk (0x3U << CMU_OPCCR1_I2C0CKS_Pos) ¶CMU_OPCCR1_I2C0CKS_APBCLK (0x0U << CMU_OPCCR1_I2C0CKS_Pos) ·CMU_OPCCR1_I2C0CKS_RCHF (0x1U << CMU_OPCCR1_I2C0CKS_Pos) ¸CMU_OPCCR1_I2C0CKS_SYSCLK (0x2U << CMU_OPCCR1_I2C0CKS_Pos) ºCMU_OPCCR1_UART1CKE_Pos 9 »CMU_OPCCR1_UART1CKE_Msk (0x1U << CMU_OPCCR1_UART1CKE_Pos) ½CMU_OPCCR1_UART0CKE_Pos 8 ¾CMU_OPCCR1_UART0CKE_Msk (0x1U << CMU_OPCCR1_UART0CKE_Pos) ÀCMU_OPCCR1_UART1CKS_Pos 2 ÅCMU_OPCCR1_UART1CKS_Msk (0x3U << CMU_OPCCR1_UART1CKS_Pos) ÆCMU_OPCCR1_UART1CKS_APBCLK (0x0U << CMU_OPCCR1_UART1CKS_Pos) ÇCMU_OPCCR1_UART1CKS_RCHF (0x1U << CMU_OPCCR1_UART1CKS_Pos) ÈCMU_OPCCR1_UART1CKS_SYSCLK (0x2U << CMU_OPCCR1_UART1CKS_Pos) ÊCMU_OPCCR1_UART0CKS_Pos 0 ÏCMU_OPCCR1_UART0CKS_Msk (0x3U << CMU_OPCCR1_UART0CKS_Pos) ÐCMU_OPCCR1_UART0CKS_APBCLK (0x0U << CMU_OPCCR1_UART0CKS_Pos) ÑCMU_OPCCR1_UART0CKS_RCHF (0x1U << CMU_OPCCR1_UART0CKS_Pos) ÒCMU_OPCCR1_UART0CKS_SYSCLK (0x2U << CMU_OPCCR1_UART0CKS_Pos) ÔCMU_OPCCR2_RNGPRSC_Pos 28 ÜCMU_OPCCR2_RNGPRSC_Msk (0x7U << CMU_OPCCR2_RNGPRSC_Pos) ÝCMU_OPCCR2_RNGPRSC_DIV1 (0x0U << CMU_OPCCR2_RNGPRSC_Pos) ÞCMU_OPCCR2_RNGPRSC_DIV2 (0x1U << CMU_OPCCR2_RNGPRSC_Pos) ßCMU_OPCCR2_RNGPRSC_DIV4 (0x2U << CMU_OPCCR2_RNGPRSC_Pos) àCMU_OPCCR2_RNGPRSC_DIV8 (0x3U << CMU_OPCCR2_RNGPRSC_Pos) áCMU_OPCCR2_RNGPRSC_DIV16 (0x4U << CMU_OPCCR2_RNGPRSC_Pos) âCMU_OPCCR2_RNGPRSC_DIV32 (0x5U << CMU_OPCCR2_RNGPRSC_Pos) äCMU_OPCCR2_NVMCKE_Pos 22 åCMU_OPCCR2_NVMCKE_Msk (0x1U << CMU_OPCCR2_NVMCKE_Pos) çCMU_OPCCR2_RNGCKE_Pos 21 èCMU_OPCCR2_RNGCKE_Msk (0x1U << CMU_OPCCR2_RNGCKE_Pos) êCMU_OPCCR2_LPTCKE_Pos 12 ëCMU_OPCCR2_LPTCKE_Msk (0x1U << CMU_OPCCR2_LPTCKE_Pos) íCMU_OPCCR2_LPTCKS_Pos 8 òCMU_OPCCR2_LPTCKS_Msk (0x3U << CMU_OPCCR2_LPTCKS_Pos) óCMU_OPCCR2_LPTCKS_APBCLK (0x0U << CMU_OPCCR2_LPTCKS_Pos) ôCMU_OPCCR2_LPTCKS_LSCLK (0x1U << CMU_OPCCR2_LPTCKS_Pos) õCMU_OPCCR2_LPTCKS_RCLP (0x2U << CMU_OPCCR2_LPTCKS_Pos) öCMU_OPCCR2_LPTCKS_PLL_L (0x3U << CMU_OPCCR2_LPTCKS_Pos) øCMU_OPCCR2_BSTCKE_Pos 4 ùCMU_OPCCR2_BSTCKE_Msk (0x1U << CMU_OPCCR2_BSTCKE_Pos) ûCMU_OPCCR2_BSTCKS_Pos 0 CMU_OPCCR2_BSTCKS_Msk (0x3U << CMU_OPCCR2_BSTCKS_Pos) CMU_OPCCR2_BSTCKS_APBCLK (0x0U << CMU_OPCCR2_BSTCKS_Pos) CMU_OPCCR2_BSTCKS_LSCLK (0x1U << CMU_OPCCR2_BSTCKS_Pos) CMU_OPCCR2_BSTCKS_RCLP (0x2U << CMU_OPCCR2_BSTCKS_Pos) CMU_OPCCR2_BSTCKS_SYSCLK (0x3U << CMU_OPCCR2_BSTCKS_Pos) £COMPCLK (0x01000000 + CMU_PCLKCR1_COMP_PCE_Pos) ¤SVDCLK (0x01000000 + CMU_PCLKCR1_SVD_PCE_Pos) ¥PADCLK (0x01000000 + CMU_PCLKCR1_PAD_PCE_Pos) ¦ANACCLK (0x01000000 + CMU_PCLKCR1_ANAC_PCE_Pos) §IWDTCLK (0x01000000 + CMU_PCLKCR1_IWDT_PCE_Pos) ¨SCUCLK (0x01000000 + CMU_PCLKCR1_SCU_PCE_Pos) ©PMUCLK (0x01000000 + CMU_PCLKCR1_PMU_PCE_Pos) ªRTCCLK (0x01000000 + CMU_PCLKCR1_RTC_PCE_Pos) «LPTCLK (0x01000000 + CMU_PCLKCR1_LPT_PCE_Pos) ®PAECLK (0x02000000 + CMU_PCLKCR2_PAE_PCE_Pos) ¯SHACLK (0x02000000 + CMU_PCLKCR2_SHA_PCE_Pos) °CICCLK (0x02000000 + CMU_PCLKCR2_CIC_PCE_Pos) ±WWDTCLK (0x02000000 + CMU_PCLKCR2_WWDT_PCE_Pos) ²RAMBISTCLK (0x02000000 + CMU_PCLKCR2_RAMBIST_PCE_Pos) ³FLASHCLK (0x02000000 + CMU_PCLKCR2_NVM_PCE_Pos) ´DMACLK (0x02000000 + CMU_PCLKCR2_DMA_PCE_Pos) µLCDCLK (0x02000000 + CMU_PCLKCR2_LCD_PCE_Pos) ¶AESCLK (0x02000000 + CMU_PCLKCR2_AES_PCE_Pos) ·TRNGCLK (0x02000000 + CMU_PCLKCR2_TRNG_PCE_Pos) ¸CRCCLK (0x02000000 + CMU_PCLKCR2_CRC_PCE_Pos) ºI2C1CLK (0x03000000 + CMU_PCLKCR3_I2C1_PCE_Pos) »I2C0CLK (0x03000000 + CMU_PCLKCR3_I2C0_PCE_Pos) ¼LPUART1CLK (0x03000000 + CMU_PCLKCR3_LPUART1_PCE_Pos) ½U7816CLK (0x03000000 + CMU_PCLKCR3_U7816_PCE_Pos) ¾LPUART0CLK (0x03000000 + CMU_PCLKCR3_LPUART0_PCE_Pos) ¿UARTIRCLK (0x03000000 + CMU_PCLKCR3_UICR_PCE_Pos) ÀUART5CLK (0x03000000 + CMU_PCLKCR3_UART5_PCE_Pos) ÁUART4CLK (0x03000000 + CMU_PCLKCR3_UART4_PCE_Pos) ÂUART3CLK (0x03000000 + CMU_PCLKCR3_UART3_PCE_Pos) ÃUART2CLK (0x03000000 + CMU_PCLKCR3_UART2_PCE_Pos) ÄUART1CLK (0x03000000 + CMU_PCLKCR3_UART1_PCE_Pos) ÅUART0CLK (0x03000000 + CMU_PCLKCR3_UART0_PCE_Pos) ÆQSPICLK (0x03000000 + CMU_PCLKCR3_QSPI_PCE_Pos) ÇSPI4CLK (0x03000000 + CMU_PCLKCR3_SPI4_PCE_Pos) ÈSPI3CLK (0x03000000 + CMU_PCLKCR3_SPI3_PCE_Pos) ÉSPI2CLK (0x03000000 + CMU_PCLKCR3_SPI2_PCE_Pos) ÊSPI1CLK (0x03000000 + CMU_PCLKCR3_SPI1_PCE_Pos) ËSPI0CLK (0x03000000 + CMU_PCLKCR3_SPI0_PCE_Pos) ÎET4CLK (0x04000000 + CMU_PCLKCR4_ET4_PCE_Pos) ÏET3CLK (0x04000000 + CMU_PCLKCR4_ET3_PCE_Pos) ÐET2CLK (0x04000000 + CMU_PCLKCR4_ET2_PCE_Pos) ÑET1CLK (0x04000000 + CMU_PCLKCR4_ET1_PCE_Pos) ÒBT2CLK (0x04000000 + CMU_PCLKCR4_BT2_PCE_Pos) ÓBT1CLK (0x04000000 + CMU_PCLKCR4_BT1_PCE_Pos) ÔBSTIMCLK (0x04000000 + CMU_PCLKCR4_BSTIM_PCE_Pos) ` T ..\Drivers\ ..\Core\Include\ fm33a0xxev_CMU.h FM33A0XXEV.h ð
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..\Drivers\fm33a0xxev_CMU.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM *à FSEL W # RCHFEN # PCMU_RCHF_InitTypeDef ½ )*¢ PLLLDB W # PLLL_EN # PCMU_PLL_L_InitTypeDef ü /* PLLHDB W # REFPRSC W # PLLH_OSEL W # PLLH_INSEL W # PLLH_EN # PCMU_PLL_H_InitTypeDef ?9* SYSCLKSEL W # AHBPRES W # APBPRES W # SLP_ENEXTI # PCMU_SYSCLK_InitTypeDef ºC*Û SYSCLK_Frequency W # AHBCLK_Frequency W # APBCLK_Frequency W # RCHF_Frequency W # PLL_H_Frequency W # XTHF_Frequency W # LSCLK_Frequency W # PCMU_ClocksType &N Ï Ð Ñ __FM33A0XXEV_UART_H OUARTIR_CR_IRFLAG_Pos 15 RUARTIR_CR_IRFLAG_Msk (0x1U << UARTIR_CR_IRFLAG_Pos) SUARTIR_CR_IRFLAG_POSITIVE (0x0U << UARTIR_CR_IRFLAG_Pos) TUARTIR_CR_IRFLAG_NEGTIVE (0x1U << UARTIR_CR_IRFLAG_Pos) VUARTIR_CR_TH_Pos 11 WUARTIR_CR_TH_Msk (0xfU << UARTIR_CR_TH_Pos) YUARTIR_CR_TZBRG_Pos 0 ZUARTIR_CR_TZBRG_Msk (0x7ffU << UARTIR_CR_TZBRG_Pos) \UARTx_CSR_BUSY_Pos 24 _UARTx_CSR_BUSY_Msk (0x1U << UARTx_CSR_BUSY_Pos) aUARTx_CSR_TXIREN_Pos 17 dUARTx_CSR_TXIREN_Msk (0x1U << UARTx_CSR_TXIREN_Pos) hUARTx_CSR_RXTOEN_Pos 16 kUARTx_CSR_RXTOEN_Msk (0x1U << UARTx_CSR_RXTOEN_Pos) oUARTx_CSR_IOSWAP_Pos 12 rUARTx_CSR_IOSWAP_Msk (0x1U << UARTx_CSR_IOSWAP_Pos) sUARTx_CSR_IOSWAP_DEFAULT (0x0U << UARTx_CSR_IOSWAP_Pos) tUARTx_CSR_IOSWAP_EXCHANGE (0x1U << UARTx_CSR_IOSWAP_Pos) vUARTx_CSR_DMATXIFCFG_Pos 10 yUARTx_CSR_DMATXIFCFG_Msk (0x1U << UARTx_CSR_DMATXIFCFG_Pos) }UARTx_CSR_BITORD_Pos 9 UARTx_CSR_BITORD_Msk (0x1U << UARTx_CSR_BITORD_Pos) UARTx_CSR_BITORD_LSB (0x0U << UARTx_CSR_BITORD_Pos) UARTx_CSR_BITORD_MSB (0x1U << UARTx_CSR_BITORD_Pos) UARTx_CSR_STOPCFG_Pos 8 UARTx_CSR_STOPCFG_Msk (0x1U << UARTx_CSR_STOPCFG_Pos) UARTx_CSR_STOPCFG_1STOPBIT (0x0U << UARTx_CSR_STOPCFG_Pos) UARTx_CSR_STOPCFG_2STOPBIT (0x1U << UARTx_CSR_STOPCFG_Pos) UARTx_CSR_PDSEL_Pos 6 UARTx_CSR_PDSEL_Msk (0x3U << UARTx_CSR_PDSEL_Pos) UARTx_CSR_PDSEL_7BIT (0x0U << UARTx_CSR_PDSEL_Pos) UARTx_CSR_PDSEL_8BIT (0x1U << UARTx_CSR_PDSEL_Pos) UARTx_CSR_PDSEL_9BIT (0x2U << UARTx_CSR_PDSEL_Pos) UARTx_CSR_PDSEL_6BIT (0x3U << UARTx_CSR_PDSEL_Pos) UARTx_CSR_PARITY_Pos 4 UARTx_CSR_PARITY_Msk (0x3U << UARTx_CSR_PARITY_Pos) UARTx_CSR_PARITY_NONE (0x0U << UARTx_CSR_PARITY_Pos) UARTx_CSR_PARITY_EVEN (0x1U << UARTx_CSR_PARITY_Pos) UARTx_CSR_PARITY_ODD (0x2U << UARTx_CSR_PARITY_Pos) UARTx_CSR_RXPOL_Pos 3 £UARTx_CSR_RXPOL_Msk (0x1U << UARTx_CSR_RXPOL_Pos) ¤UARTx_CSR_RXPOL_POSITIVE (0x0U << UARTx_CSR_RXPOL_Pos) ¥UARTx_CSR_RXPOL_NEGTIVE (0x1U << UARTx_CSR_RXPOL_Pos) §UARTx_CSR_TXPOL_Pos 2 ªUARTx_CSR_TXPOL_Msk (0x1U << UARTx_CSR_TXPOL_Pos) «UARTx_CSR_TXPOL_POSITIVE (0x0U << UARTx_CSR_TXPOL_Pos) ¬UARTx_CSR_TXPOL_NEGTIVE (0x1U << UARTx_CSR_TXPOL_Pos) ®UARTx_CSR_RXEN_Pos 1 ¯UARTx_CSR_RXEN_Msk (0x1U << UARTx_CSR_RXEN_Pos) °UARTx_CSR_RXEN_DISBALE (0x0U << UARTx_CSR_RXEN_Pos) ±UARTx_CSR_RXEN_ENABLE (0x1U << UARTx_CSR_RXEN_Pos) ³UARTx_CSR_TXEN_Pos 0 ´UARTx_CSR_TXEN_Msk (0x1U << UARTx_CSR_TXEN_Pos) µUARTx_CSR_TXEN_DISBALE (0x0U << UARTx_CSR_TXEN_Pos) ¶UARTx_CSR_TXEN_ENABLE (0x1U << UARTx_CSR_TXEN_Pos) ¸UARTx_IER_RXTO_IE_Pos 11 ºUARTx_IER_RXTO_IE_Msk (0x1U << UARTx_IER_RXTO_IE_Pos) ¼UARTx_IER_RXERR_IE_Pos 10 ½UARTx_IER_RXERR_IE_Msk (0x1U << UARTx_IER_RXERR_IE_Pos) ¿UARTx_IER_RXBF_IE_Pos 8 ÀUARTx_IER_RXBF_IE_Msk (0x1U << UARTx_IER_RXBF_IE_Pos) ÂUARTx_IER_NEWUP_IE_Pos 7 ÃUARTx_IER_NEWUP_IE_Msk (0x1U << UARTx_IER_NEWUP_IE_Pos) ÅUARTx_IER_TXBE_IE_Pos 1 ÆUARTx_IER_TXBE_IE_Msk (0x1U << UARTx_IER_TXBE_IE_Pos) ÈUARTx_IER_TXSE_IE_Pos 0 ÉUARTx_IER_TXSE_IE_Msk (0x1U << UARTx_IER_TXSE_IE_Pos) ËUARTx_ISR_PERR_Pos 18 ÌUARTx_ISR_PERR_Msk (0x1U << UARTx_ISR_PERR_Pos) ÎUARTx_ISR_FERR_Pos 17 ÏUARTx_ISR_FERR_Msk (0x1U << UARTx_ISR_FERR_Pos) ÑUARTx_ISR_OERR_Pos 16 ÓUARTx_ISR_OERR_Msk (0x1U << UARTx_ISR_OERR_Pos) ÕUARTx_ISR_RXTO_Pos 11 ×UARTx_ISR_RXTO_Msk (0x1U << UARTx_ISR_RXTO_Pos) ÙUARTx_ISR_RXBF_Pos 8 ÚUARTx_ISR_RXBF_Msk (0x1U << UARTx_ISR_RXBF_Pos) ÜUARTx_ISR_TXBE_Pos 1 ÝUARTx_ISR_TXBE_Msk (0x1U << UARTx_ISR_TXBE_Pos) ßUARTx_ISR_TXSE_Pos 0 àUARTx_ISR_TXSE_Msk (0x1U << UARTx_ISR_TXSE_Pos) âUARTx_TODR_TXDLY_LEN_Pos 8 ãUARTx_TODR_TXDLY_LEN_Msk (0xffU << UARTx_TODR_TXDLY_LEN_Pos) åUARTx_TODR_RXTO_LEN_Pos 0 æUARTx_TODR_RXTO_LEN_Msk (0xffU << UARTx_TODR_RXTO_LEN_Pos) èUARTx_RXBUF_RXBUF_Pos 0 éUARTx_RXBUF_RXBUF_Msk (0x1ffU << UARTx_RXBUF_RXBUF_Pos) ëUARTx_TXBUF_TXBUF_Pos 0 ìUARTx_TXBUF_TXBUF_Msk (0x1ffU << UARTx_TXBUF_TXBUF_Pos) îUARTx_BRG_SPBRG_Pos 0 ïUARTx_BRG_SPBRG_Msk (0xffffU << UARTx_BRG_SPBRG_Pos) t i ..\Drivers\ ..\Core\Include\ fm33a0xxev_uart.h FM33A0XXEV.h fm33a0xxev_CMU.h
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..\Drivers\fm33a0xxev_uart.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM ÕRxInt TxInt PUART_IntTypeDef ¾ ¢Seven7Bit Eight8Bit Nine9Bit Six6Bit PUART_DataBitTypeDef ì %ÙNONE EVEN ODD PUART_ParityBitTypeDef =,OneBit TwoBit PUART_StopBitTypeDef v2* BaudRate W # DataBit "# ParityBit Y# StopBit # ClockSrc W # PUART_SInitTypeDef ª;*þ RXBF_IE # TXBE_IE # TXSE_IE # SPBRG W # PDSEL W # PARITY W # RXTO_IE # ERRIE # RXEN # STOPSEL W # TXEN # IREN # RXDFLAG # TXDFLAG # PUART_InitTypeDef M Ó Ô Õ t h ..\Drivers\ ..\Drivers\fm33a0xxev_uart.c fm33a0xxev_uart.h fm33a0xxev_cmu.h X
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..\Drivers\fm33a0xxev_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM _Complex long_double _Complex double _Complex float uvoid float )¥__va_list __ap %# "û P__builtin_va_list
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Input Comments: p10b4-3 Component: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec] armasm --debug --diag_suppress=9931,9931,1602,1073 --cpu=Cortex-M0 --fpu=SoftVFP --apcs=/interwork/interwork --no_divide fm33a0xxev_uart.o Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] ArmCC --c99 --split_sections --debug -c --gnu -o.\objects\fm33a0xxev_uart.o --depend=.\objects\fm33a0xxev_uart.d --cpu=Cortex-M0 --apcs=interwork -O0 --diag_suppress=9931 -I..\Core -I..\Drivers -I..\Core\Include -I..\Hardware -I.\RTE\Device -I..\Hardware\CLOCK -I..\Hardware\DELAY -I..\Hardware\GPIO -I..\Hardware\UART -I..\Hardware\TIM -I..\Function\KEY -I..\Hardware\EXTI -I..\Hardware\RTC -I..\Hardware\ADC -I..\Hardware\I2C -I..\Function\LCD -I..\Function\EXTERN_RTC -I..\Hardware\SPI -I..\Function\GPRS -I..\Function\HARDWARE_WATCHDOG -I..\Function\IR_NEC -I..\Function\MEASURE_INTERACTION -I..\Function\POWER_MANAGE -I..\Function\STORAGE -I..\Function\UPPER_COMPUTER -I..\Function\VALVE -I..\Soft -I..\MultiButton -I..\USMART -I..\Hardware\DMA -I..\Hardware\ON_CHIP_FLASH -I..\Hardware\SVD -I..\Function\OFF_CHIP_FLASH -I..\Hardware\CRC -I..\Function\BOOTLOADER_IAP -I..\Hardware\COMP -I..\Function\E2P -I..\CmBackTrace -I..\Pre_Drivers -I..\Pre_Drivers -I..\Function\PROJECT_TETS -I.\RTE\_UFG220_FM33A0_MainSystem -ID:\Keil5\ARM\PACK\ARM\CMSIS\5.3.0\CMSIS\Include -ID:\Keil5\ARM\PACK\Keil\FM33A0XXEV_DFP\0.0.4\Device\Include -D__MICROLIB -D__UVISION_VERSION=525 -D_RTE_ -D__VTOR_PRESENT --omf_browse=.\objects\fm33a0xxev_uart.crf ..\Drivers\fm33a0xxev_uart.c ï7 ï7 ï7 ì7 ï7 ì7 ï7 ì7 ï7 ì7 ï7 ì7
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P P ¥ P ¿ P Î P ß P ù P P ( P C P q P P P · P Ò P ý P P * P > P ] P x P H ¸ h ¼ ^ Ñ P ß P í P û P P " P C P Z P s P P « P ¹ P Ð P Þ P ì P ú P P ! P D P V P m P P ¾ P ð P " P U P r P ¢ P P ; P I , I R P X I l P I ¸ I Ý I è P P I * P b P q P P P ª P H o e Ç N Q H ¶ g º ] x P P H ½ p Á f × P R H µ k ¹ a È P Ø I P I L P ] P p P P I Ê P Û P ì P I = P W P q P P ¢ P º P Ó P H ¶ m º c ¹ P ú P ) I : I K I Z P i P y P I I § I ¸ P Æ I Ô I å I ö I H ¶ l º b D I J O P O V M .ARM.attributes .strtab .shstrtab .rel.debug_pubnames .rel.debug_frame .rel.debug_line .rel.debug_info .reli.UART_SInit .reli.UART_Init .reli.UART_IRModulation_Init .reli.UART_BaudREGCalc .symtab .comment .arm_vfe_header __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000 __ARM_grp.fm33a0xxev_uart.c.2_g$8000_uh8TW6nPxU0_V00000 __ARM_grp.fm33a0xxev_uart.h.2_o_5000_ywUfKpBxMT6_r00000 __ARM_grp.fm33a0xxev_CMU.h.2_Akb000_zIckYzslJqc_v00000 __ARM_grp.system_FM33A0XXEV.h.2_iK2000_$xx4mkEXI33_f00000 __ARM_grp.FM33A0XXEV.h.2_YT4000_XZU28XPoz9f_800000 __ARM_grp.stdio.h.2_UEi000_QiolLKMvkjc_X10000 __ARM_grp.core_cm0plus.h.2_ko7000_oz_SgrIf9Ea_W00000 __ARM_grp.core_cmfunc.h.2_0o1000_LxrOLndRPv6_z00000 __ARM_grp.core_cminstr.h.2_cq1000_pIFywSNOsOf_b00000 __ARM_grp.stdint.h.2_MG1000_W2MyGZvI3s6_300000 .debug_abbrev __ARM_asm.debug_abbrev.1 .debug_macinfo .debug_loc i.UARTx_TXBUF_Write i.UARTx_TXBUF_Read i.UARTx_TODR_TXDLY_LEN_Set i.UARTx_TODR_TXDLY_LEN_Get i.UARTx_TODR_RXTO_LEN_Set i.UARTx_TODR_RXTO_LEN_Get i.UARTx_RXBUF_Read i.UARTx_ISR_TXSE_Clr i.UARTx_ISR_TXSE_Chk i.UARTx_ISR_TXBE_Chk i.UARTx_ISR_RXTO_Clr i.UARTx_ISR_RXTO_Chk i.UARTx_ISR_RXBF_Clr i.UARTx_ISR_RXBF_Chk i.UARTx_ISR_PERR_Clr i.UARTx_ISR_PERR_Chk i.UARTx_ISR_OERR_Clr i.UARTx_ISR_OERR_Chk i.UARTx_ISR_FERR_Clr i.UARTx_ISR_FERR_Chk i.UARTx_IER_TXSE_IE_Setable i.UARTx_IER_TXSE_IE_Getable i.UARTx_IER_TXBE_IE_Setable i.UARTx_IER_TXBE_IE_Getable i.UARTx_IER_RXTO_IE_Setable i.UARTx_IER_RXTO_IE_Getable i.UARTx_IER_RXERR_IE_Setable i.UARTx_IER_RXERR_IE_Getable i.UARTx_IER_RXBF_IE_Setable i.UARTx_IER_RXBF_IE_Getable i.UARTx_Deinit i.UARTx_CSR_TXPOL_Setable i.UARTx_CSR_TXPOL_Getable i.UARTx_CSR_TXIREN_Setable i.UARTx_CSR_TXIREN_Getable i.UARTx_CSR_TXEN_Setable i.UARTx_CSR_TXEN_Getable i.UARTx_CSR_STOPCFG_Set i.UARTx_CSR_STOPCFG_Get i.UARTx_CSR_RXTOEN_Setable i.UARTx_CSR_RXTOEN_Getable i.UARTx_CSR_RXPOL_Setable i.UARTx_CSR_RXPOL_Getable i.UARTx_CSR_RXEN_Setable i.UARTx_CSR_RXEN_Getable i.UARTx_CSR_PDSEL_Set i.UARTx_CSR_PDSEL_Get i.UARTx_CSR_PARITY_Set i.UARTx_CSR_PARITY_Get i.UARTx_CSR_IOSWAP_Set i.UARTx_CSR_IOSWAP_Get i.UARTx_CSR_DMATXIFCFG_Setable i.UARTx_CSR_DMATXIFCFG_Getable i.UARTx_CSR_BUSY_Chk i.UARTx_CSR_BITORD_Set i.UARTx_CSR_BITORD_Get i.UARTx_BGR_Write i.UARTx_BGR_Read i.UART_Deinit i.UARTIR_CR_TZBRG_Set i.UARTIR_CR_TZBRG_Get i.UARTIR_CR_TH_Set i.UARTIR_CR_TH_Get i.UARTIR_CR_IRFLAG_Set i.UARTIR_CR_IRFLAG_Get .revsh_text .rev16_text Lib$$Request$$armlib __aeabi_ui2f __aeabi_fdiv __aeabi_f2d __aeabi_dsub __aeabi_dmul __aeabi_ddiv __aeabi_dadd __aeabi_d2uiz __aeabi_cfrcmple CMU_RCHFCR_RCHFEN_Setable CMU_PERCLK_SetableEx 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__ARM_grp_.debug_frame$97 __ARM_grp_.debug_frame$90 __ARM_grp_.debug_frame$83 __ARM_grp_.debug_frame$76 __ARM_grp_.debug_frame$69 __ARM_grp_.debug_frame$62 __ARM_grp_.debug_frame$55 __ARM_grp_.debug_frame$48 __ARM_grp_.debug_frame$41 __ARM_grp_.debug_frame$34 __ARM_grp_.debug_frame$27 __ARM_grp_.debug_frame$20 __ARM_grp_.debug_frame$13 i.UARTx_TXBUF_Write i.UARTx_TXBUF_Read i.UARTx_TODR_TXDLY_LEN_Set i.UARTx_TODR_TXDLY_LEN_Get i.UARTx_TODR_RXTO_LEN_Set i.UARTx_TODR_RXTO_LEN_Get i.UARTx_RXBUF_Read i.UARTx_ISR_TXSE_Clr i.UARTx_ISR_TXSE_Chk i.UARTx_ISR_TXBE_Chk i.UARTx_ISR_RXTO_Clr i.UARTx_ISR_RXTO_Chk i.UARTx_ISR_RXBF_Clr i.UARTx_ISR_RXBF_Chk i.UARTx_ISR_PERR_Clr i.UARTx_ISR_PERR_Chk i.UARTx_ISR_OERR_Clr i.UARTx_ISR_OERR_Chk i.UARTx_ISR_FERR_Clr i.UARTx_ISR_FERR_Chk i.UARTx_IER_TXSE_IE_Setable i.UARTx_IER_TXSE_IE_Getable i.UARTx_IER_TXBE_IE_Setable i.UARTx_IER_TXBE_IE_Getable i.UARTx_IER_RXTO_IE_Setable i.UARTx_IER_RXTO_IE_Getable i.UARTx_IER_RXERR_IE_Setable i.UARTx_IER_RXERR_IE_Getable i.UARTx_IER_RXBF_IE_Setable i.UARTx_IER_RXBF_IE_Getable i.UARTx_Deinit i.UARTx_CSR_TXPOL_Setable i.UARTx_CSR_TXPOL_Getable i.UARTx_CSR_TXIREN_Setable i.UARTx_CSR_TXIREN_Getable i.UARTx_CSR_TXEN_Setable i.UARTx_CSR_TXEN_Getable i.UARTx_CSR_STOPCFG_Set i.UARTx_CSR_STOPCFG_Get i.UARTx_CSR_RXTOEN_Setable i.UARTx_CSR_RXTOEN_Getable i.UARTx_CSR_RXPOL_Setable i.UARTx_CSR_RXPOL_Getable i.UARTx_CSR_RXEN_Setable i.UARTx_CSR_RXEN_Getable i.UARTx_CSR_PDSEL_Set i.UARTx_CSR_PDSEL_Get i.UARTx_CSR_PARITY_Set i.UARTx_CSR_PARITY_Get i.UARTx_CSR_IOSWAP_Set i.UARTx_CSR_IOSWAP_Get i.UARTx_CSR_DMATXIFCFG_Setable i.UARTx_CSR_DMATXIFCFG_Getable i.UARTx_CSR_BUSY_Chk i.UARTx_CSR_BITORD_Set i.UARTx_CSR_BITORD_Get i.UARTx_BGR_Write i.UARTx_BGR_Read i.UART_SInit i.UART_Init i.UART_IRModulation_Init i.UART_Deinit i.UART_BaudREGCalc i.UARTIR_CR_TZBRG_Set i.UARTIR_CR_TZBRG_Get i.UARTIR_CR_TH_Set i.UARTIR_CR_TH_Get i.UARTIR_CR_IRFLAG_Set BuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$~SHL$OSPACE$EBA8$REQ8$PRES8$EABIv2 i.UARTIR_CR_IRFLAG_Get BuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$~SHL$OSPACE$EBA8$PRES8$EABIv2 ..\Drivers\fm33a0xxev_uart.c .revsh_text .rev16_text ..\\Drivers\\fm33a0xxev_uart.c $d.realdata $d $t A aeabi Cortex-M0 W
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