/**
|
******************************************************************************
|
* @file fm33a0xxev_dma.h
|
* @author FM33A0XXEV Application Team
|
* @version V1.0.0
|
* @date 16-April-2020
|
* @brief This file contains all the functions prototypes for the DMA firmware library.
|
******************************************************************************
|
*/
|
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
|
#ifndef __FM33A0XXEV_DMA_H
|
#define __FM33A0XXEV_DMA_H
|
|
|
#ifdef __cplusplus
|
extern "C" {
|
#endif
|
|
/* Includes ------------------------------------------------------------------*/
|
|
#include "FM33A0XXEV.h"
|
|
typedef enum {
|
DMA_CH0 = 0, DMA_CH1 = 1, DMA_CH2 = 2, DMA_CH3 = 3, DMA_CH4 = 4, DMA_CH5 = 5, DMA_CH6 = 6, DMA_CH7 = 7,
|
DMA_CH8 = 8, DMA_CH9 = 9, DMA_CH10 = 10, DMA_CH11 = 11
|
}DMA_CH_Type;
|
|
typedef struct
|
{
|
DMA_CH_Type CHx; //DMAͨµÀºÅ
|
uint32_t CHxTSIZE; //ͨµÀ´«Ê䳤¶È
|
uint32_t CHxPRI; //ͨµÀÓÅÏȼ¶
|
uint32_t CHxINC; //CH0~CH10ͨµÀµØÖ·Ôö³¤·½Ïò,CH11ÎÞÒâÒå
|
uint32_t CHxSSEL; //CH0~CH10ÍâÉèͨµÀÑ¡Ôñ,CH11´«Ê䷽ʽѡÔñ
|
uint32_t CHxDIR; //CH0~CH10ͨµÀ´«Êä·½Ïò
|
uint32_t CHxBDW; //CH0~CH10ͨµÀ´«Êä´ø¿í
|
FunState CHxCICR; //CH0~CH10Ñ»·»º³åģʽ
|
FunState CHxFTIE; //ͨµÀ´«ÊäÍê³ÉÖжÏʹÄÜ
|
FunState CHxHTIE; //ͨµÀ´«Êä°ë³ÌÖжÏʹÄÜ
|
FunState CHxEN; //ͨµÀʹÄÜ
|
uint32_t CHxRAMAD; //CH0~CH11ͨµÀRAMÖ¸ÕëµØÖ·,×¢ÒâCH11ʹÓõÄÊÇwordµØÖ·£¬Çý¶¯ÀïÒÑ´¦Àí¹ýÁË£¬
|
|
uint32_t CH11RI; // RAMµØÖ·Ôö³¤·½Ïò(½öFlashµ½RAMÓÐЧ)
|
uint32_t CH11FI; // FLSµØÖ·Ôö³¤·½Ïò(½öFlashµ½RAMÓÐЧ)
|
uint32_t CH11FLSAD; //ͨµÀFLASHÖ¸ÕëµØÖ·£¬½öÕë¶ÔͨµÀ11ÓÐÒâÒå
|
}DMA_InitTypeDef;
|
|
#define DMA_GCR_DMA_ADDRERR_EN_Pos 1 /* DMA´íÎóµØÖ·ÖжÏʹÄÜ
|
1£ºÔÊÐí´íÎóµØÖ·ÖжÏ
|
0£º½ûÖ¹´íÎóµØÖ·ÖÐ¶Ï */
|
#define DMA_GCR_DMA_ADDRERR_EN_Msk (0x1U << DMA_GCR_DMA_ADDRERR_EN_Pos)
|
|
#define DMA_GCR_DMAEN_Pos 0 /* DMAÈ«¾ÖʹÄÜ
|
1£ºDMAʹÄÜ
|
0£ºDMA¹Ø±Õ */
|
#define DMA_GCR_DMAEN_Msk (0x1U << DMA_GCR_DMAEN_Pos)
|
|
#define DMA_CHxCR_CHxTSIZE_Pos 16 /* Channelx´«Ê䳤¶È£¬1-8192´Î´«Êä */
|
#define DMA_CHxCR_CHxTSIZE_Msk (0x1fffU << DMA_CHxCR_CHxTSIZE_Pos)
|
|
#define DMA_CHxCR_CHxPRI_Pos 12 /* ChannelxÓÅÏȼ¶
|
00£ºLow
|
01£ºMedium
|
10£ºHigh
|
11£ºVery High */
|
#define DMA_CHxCR_CHxPRI_Msk (0x3U << DMA_CHxCR_CHxPRI_Pos)
|
#define DMA_CHxCR_CHxPRI_LOW (0x0U << DMA_CHxCR_CHxPRI_Pos) /* Low */
|
#define DMA_CHxCR_CHxPRI_MEDIUM (0x1U << DMA_CHxCR_CHxPRI_Pos) /* Medium */
|
#define DMA_CHxCR_CHxPRI_HIGH (0x2U << DMA_CHxCR_CHxPRI_Pos) /* High */
|
#define DMA_CHxCR_CHxPRI_VERY_HIGH (0x3U << DMA_CHxCR_CHxPRI_Pos) /* Very High */
|
|
#define DMA_CHxCR_CHxINC_Pos 11 /* RAMµØÖ·Ôö¼õÉèÖÃ
|
1£ºRAMµØÖ·µÝÔö
|
0£ºRAMµØÖ·µÝ¼õ */
|
#define DMA_CHxCR_CHxINC_Msk (0x1U << DMA_CHxCR_CHxINC_Pos)
|
#define DMA_CHxCR_CHxINC_INCREASE (0x1U << DMA_CHxCR_CHxINC_Pos) /* RAMµØÖ·µÝÔö */
|
#define DMA_CHxCR_CHxINC_DECREASE (0x0U << DMA_CHxCR_CHxINC_Pos) /* RAMµØÖ·µÝ¼õ */
|
|
#define DMA_CHxCR_CHxSSEL_Pos 8 /* ChannelxÍâÉèÇëÇóÓ³Éä
|
ÿ¸öͨµÀ¿ÉÒÔ½ÓÊÜ8¸öÍâÉèÇëÇó£¬ÍâÉèÇëÇóµÄÓ³Éä²Î¼û23.6.1DMAÇëÇóÓ³Éä */
|
#define DMA_CHxCR_CHxSSEL_Msk (0x7U << DMA_CHxCR_CHxSSEL_Pos)
|
|
#define DMA_CHxCR_CH0SSEL_ADC (0x0U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH0SSEL_SPI3_RX (0x1U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH0SSEL_LPUART0_RX (0x2U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH0SSEL_LPUART1_RX (0x3U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH0SSEL_UART2_RX (0x4U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH0SSEL_UART4_RX (0x5U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH0SSEL_AES_IN (0x6U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH0SSEL_QSPI (0x7U << DMA_CHxCR_CHxSSEL_Pos)
|
|
#define DMA_CHxCR_CH1SSEL_ADC (0x0U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH1SSEL_SPI0_RX (0x1U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH1SSEL_SPI2_RX (0x2U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH1SSEL_SPI3_TX (0x3U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH1SSEL_UART0_RX (0x4U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH1SSEL_UART2_TX (0x5U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH1SSEL_UART3_RX (0x6U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH1SSEL_U7816_RX (0x7U << DMA_CHxCR_CHxSSEL_Pos)
|
|
#define DMA_CHxCR_CH2SSEL_SPI0_TX (0x0U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH2SSEL_SPI2_TX (0x1U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH2SSEL_SPI4_RX (0x2U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH2SSEL_UART0_TX (0x3U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH2SSEL_UART3_TX (0x4U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH2SSEL_UART5_RX (0x5U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH2SSEL_U7816_TX (0x6U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH2SSEL_AES_OUT (0x7U << DMA_CHxCR_CHxSSEL_Pos)
|
|
#define DMA_CHxCR_CH3SSEL_SPI1_RX (0x0U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH3SSEL_SPI4_TX (0x1U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH3SSEL_LPUART0_RX (0x2U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH3SSEL_UART1_RX (0x3U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH3SSEL_UART4_RX (0x4U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH3SSEL_UART5_TX (0x5U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH3SSEL_I2C0_TX (0x6U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH3SSEL_AES_IN (0x7U << DMA_CHxCR_CHxSSEL_Pos)
|
|
#define DMA_CHxCR_CH4SSEL_SPI1_TX (0x0U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH4SSEL_SPI3_RX (0x1U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH4SSEL_LPUART0_TX (0x2U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH4SSEL_UART1_TX (0x3U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH4SSEL_UART2_RX (0x4U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH4SSEL_UART4_TX (0x5U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH4SSEL_I2C0_RX (0x6U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH4SSEL_AES_OUT (0x7U << DMA_CHxCR_CHxSSEL_Pos)
|
|
#define DMA_CHxCR_CH5SSEL_SPI0_RX (0x0U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH5SSEL_SPI2_RX (0x1U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH5SSEL_LPUART1_RX (0x2U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH5SSEL_UART1_RX (0x3U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH5SSEL_UART2_TX (0x4U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH5SSEL_UART3_RX (0x5U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH5SSEL_UART5_RX (0x6U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH5SSEL_I2C1_TX (0x7U << DMA_CHxCR_CHxSSEL_Pos)
|
|
#define DMA_CHxCR_CH6SSEL_SPI0_TX (0x0U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH6SSEL_SPI2_TX (0x1U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH6SSEL_LPUART1_TX (0x2U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH6SSEL_UART1_TX (0x3U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH6SSEL_UART3_TX (0x4U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH6SSEL_UART5_TX (0x5U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH6SSEL_I2C1_RX (0x6U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH6SSEL_CRC (0x7U << DMA_CHxCR_CHxSSEL_Pos)
|
|
#define DMA_CHxCR_CH7SSEL_ADC (0x0U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH7SSEL_SPI1_RX (0x1U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH7SSEL_SPI3_RX (0x2U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH7SSEL_LPUART0_RX (0x3U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH7SSEL_UART0_RX (0x4U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH7SSEL_UART2_RX (0x5U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH7SSEL_UART4_RX (0x6U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH7SSEL_QSPI (0x7U << DMA_CHxCR_CHxSSEL_Pos)
|
|
#define DMA_CHxCR_CH8SSEL_ADC (0x0U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH8SSEL_SPI1_TX (0x1U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH8SSEL_SPI2_RX (0x2U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH8SSEL_SPI3_TX (0x3U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH8SSEL_LPUART0_TX (0x4U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH8SSEL_UART0_TX (0x5U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH8SSEL_UART2_TX (0x6U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH8SSEL_UART4_TX (0x7U << DMA_CHxCR_CHxSSEL_Pos)
|
|
#define DMA_CHxCR_CH9SSEL_SPI0_RX (0x0U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH9SSEL_SPI2_TX (0x1U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH9SSEL_SPI4_RX (0x2U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH9SSEL_LPUART1_RX (0x3U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH9SSEL_UART1_RX (0x4U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH9SSEL_UART3_RX (0x5U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH9SSEL_UART5_RX (0x6U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH9SSEL_I2C0_TX (0x7U << DMA_CHxCR_CHxSSEL_Pos)
|
|
#define DMA_CHxCR_CH10SSEL_SPI0_TX (0x0U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH10SSEL_SPI4_TX (0x1U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH10SSEL_LPUART1_TX (0x2U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH10SSEL_UART1_TX (0x3U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH10SSEL_UART3_TX (0x4U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH10SSEL_UART5_TX (0x5U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH10SSEL_I2C0_RX (0x6U << DMA_CHxCR_CHxSSEL_Pos)
|
#define DMA_CHxCR_CH10SSEL_CRC (0x7U << DMA_CHxCR_CHxSSEL_Pos)
|
|
#define DMA_CHxCR_CIRC_UPD_Pos 7 /* Ñ»·»º³åģʽÏÂ×Ô¶¯¸üд«Êä²ÎÊý£¬±¾ÂÖ´«ÊäÍê³Éºó½«shadow¼Ä´æÆ÷ÄÚÈݸ´ÖƵ½¿ØÖƼĴæÆ÷
|
0£º½ûÖ¹×Ô¶¯¸üÐÂ
|
1£ºÊ¹ÄÜ×Ô¶¯¸üÐÂ
|
×¢Ò⣺½öͨµÀ0~6Ö§³Ö´Ë¹¦ÄÜ£¬Í¨µÀ7~10Î޴˼ĴæÆ÷ */
|
#define DMA_CHxCR_CIRC_UPD_Msk (0x1U << DMA_CHxCR_CIRC_UPD_Pos)
|
/* ½ûÖ¹×Ô¶¯¸üР*/
|
/* ʹÄÜ×Ô¶¯¸üР*/
|
/* ½öͨµÀ0~6Ö§³Ö´Ë¹¦ÄÜ£¬Í¨µÀ7~10Î޴˼ĴæÆ÷ */
|
|
#define DMA_CHxCR_DIR_Pos 6 /* ͨµÀ´«Êä·½Ïò
|
0£º´ÓÍâÉè¶ÁÈ¡Êý¾ÝдÈëRAM
|
1£º´ÓRAM¶ÁÈ¡Êý¾ÝдÈëÍâÉè */
|
#define DMA_CHxCR_DIR_Msk (0x1U << DMA_CHxCR_DIR_Pos)
|
#define DMA_CHxCR_DIR_TO_RAM (0x0U << DMA_CHxCR_DIR_Pos) /* ´ÓÍâÉè¶ÁÈ¡Êý¾ÝдÈëRAM */
|
#define DMA_CHxCR_DIR_TO_PER (0x1U << DMA_CHxCR_DIR_Pos) /* ´ÓRAM¶ÁÈ¡Êý¾ÝдÈëÍâÉè */
|
|
#define DMA_CHxCR_BDW_Pos 4 /* ´«Êä´ø¿íÉèÖÃ
|
00£º×Ö½Ú£¬8bit
|
01£º°ë×Ö£¬16bit
|
10£º×Ö£¬32bit
|
11£ºRFU */
|
#define DMA_CHxCR_BDW_Msk (0x3U << DMA_CHxCR_BDW_Pos)
|
#define DMA_CHxCR_BDW_8BITS (0x0U << DMA_CHxCR_BDW_Pos) /* ×Ö½Ú£¬8bit */
|
#define DMA_CHxCR_BDW_16BITS (0x1U << DMA_CHxCR_BDW_Pos) /* °ë×Ö£¬16bit */
|
#define DMA_CHxCR_BDW_32BITS (0x2U << DMA_CHxCR_BDW_Pos) /* ×Ö£¬32bit */
|
|
#define DMA_CHxCR_CIRC_Pos 3 /* Ñ»·»º³åģʽ
|
0£º¹Ø±ÕÑ»·Ä£Ê½
|
1£ºÊ¹ÄÜÑ»·Ä£Ê½ */
|
#define DMA_CHxCR_CIRC_Msk (0x1U << DMA_CHxCR_CIRC_Pos)
|
/* ¹Ø±ÕÑ»·Ä£Ê½ */
|
/* ʹÄÜÑ»·Ä£Ê½ */
|
|
#define DMA_CHxCR_CHxFTIE_Pos 2 /* Channelx´«ÊäÍê³ÉÖжÏʹÄÜ
|
1£ºÊ¹ÄÜ´«ÊäÍê³ÉÖжÏ
|
0£º¹Ø±Õ´«ÊäÍê³ÉÖÐ¶Ï */
|
#define DMA_CHxCR_CHxFTIE_Msk (0x1U << DMA_CHxCR_CHxFTIE_Pos)
|
/* ʹÄÜ´«ÊäÍê³ÉÖÐ¶Ï */
|
/* ¹Ø±Õ´«ÊäÍê³ÉÖÐ¶Ï */
|
|
#define DMA_CHxCR_CHxHTIE_Pos 1 /* Channelx°ë³Ì´«ÊäÍê³ÉÖжÏʹÄÜ
|
1£ºÊ¹ÄÜ°ë³ÌÖжÏ
|
0£º¹Ø±Õ°ë³ÌÖÐ¶Ï */
|
#define DMA_CHxCR_CHxHTIE_Msk (0x1U << DMA_CHxCR_CHxHTIE_Pos)
|
/* ʹÄÜ°ë³ÌÖÐ¶Ï */
|
/* ¹Ø±Õ°ë³ÌÖÐ¶Ï */
|
|
#define DMA_CHxCR_ChxEN_Pos 0 /* ChannelxʹÄÜ
|
1£ºÆô¶¯Í¨µÀ0
|
0£º¹Ø±ÕͨµÀ0 */
|
#define DMA_CHxCR_ChxEN_Msk (0x1U << DMA_CHxCR_ChxEN_Pos)
|
/* Æô¶¯Í¨µÀ0 */
|
/* ¹Ø±ÕͨµÀ0 */
|
|
#define DMA_CHxMAR_CHxMEMAD_Pos 0 /* Channelx´æ´¢Æ÷Ö¸ÕëµØÖ·£¬DMA´«ÊäÆô¶¯Ç°Èí¼þÏò´Ë¼Ä´æÆ÷дÈë´æ´¢Æ÷Ä¿±êµØÖ·¡£
|
µ±Ö¸ÕëÖ¸Ïò¿ÕµØַʱ£¬DMA·ÃÎʽ«´¥·¢hardfault
|
µ±Ö¸ÕëÖ¸ÏòFlashʱ£¬½ûÖ¹ÏòFlashдÈëÊý¾Ý¡£
|
Èí¼þ¿ÉÒÔ²éѯµ±Ç°DMA´«ÊäµÄÄ¿±ê´æ´¢Æ÷µØÖ·¡£
|
|
×¢Ò⣺´ËÖ¸Õë½ûÖ¹Ö¸Ïò0x00080000~0x1FFFFFFFµØÖ·£¬Õâ¶ÎµØַΪflash±£ÁôÐÅÏ¢Çø£¬Ö¸ÏòÕâ¶ÎµØÖ·¿ÉÄÜÔÚDMA·ÃÎÊÖе¼Ö²»¿ÉÔ¤¼ÆµÄ½á¹û */
|
#define DMA_CHxMAR_CHxMEMAD_Msk (0xffffffffU << DMA_CHxMAR_CHxMEMAD_Pos)
|
|
#define DMA_CH11CR_CH11TSIZE_Pos 16 /* Channel11´«Ê䳤¶È£¬1-8192´Î´«Ê䣬½öÔÚFlash->RAM´«ÊäʱÓÐЧ£¬RAM->Flash´«ÊäΪ¹Ì¶¨³¤¶È64´Î´«Êä */
|
#define DMA_CH11CR_CH11TSIZE_Msk (0x1fffU << DMA_CH11CR_CH11TSIZE_Pos)
|
|
#define DMA_CH11CR_CH11PRI_Pos 12 /* Channel11ÓÅÏȼ¶
|
00£ºLow
|
01£ºMedium
|
10£ºHigh
|
11£ºVery High */
|
#define DMA_CH11CR_CH11PRI_Msk (0x3U << DMA_CH11CR_CH11PRI_Pos)
|
#define DMA_CH11CR_CH11PRI_LOW (0x0U << DMA_CH11CR_CH11PRI_Pos) /* Low */
|
#define DMA_CH11CR_CH11PRI_MEDIUM (0x1U << DMA_CH11CR_CH11PRI_Pos) /* Medium */
|
#define DMA_CH11CR_CH11PRI_HIGH (0x2U << DMA_CH11CR_CH11PRI_Pos) /* High */
|
#define DMA_CH11CR_CH11PRI_VERY_HIGH (0x3U << DMA_CH11CR_CH11PRI_Pos) /* Very High */
|
|
#define DMA_CH11CR_CH11DIR_Pos 10 /* Channel11´«Êä·½Ïò
|
1£ºFlash->RAM´«Êä
|
0£ºRAM->Flash´«Êä */
|
#define DMA_CH11CR_CH11DIR_Msk (0x1U << DMA_CH11CR_CH11DIR_Pos)
|
#define DMA_CH11CR_CH11DIR_TO_RAM (0x1U << DMA_CH11CR_CH11DIR_Pos) /* Flash->RAM´«Êä */
|
#define DMA_CH11CR_CH11DIR_TO_FLASH (0x0U << DMA_CH11CR_CH11DIR_Pos) /* RAM->Flash´«Êä */
|
|
#define DMA_CH11CR_CH11RI_Pos 9 /* Channel11 RAMµØÖ·Ôö¼õÉèÖ㬽öÔÚFlash->RAM´«ÊäÖÐÓÐЧ
|
1£ºRAMµØÖ·µÝÔö
|
0£ºRAMµØÖ·µÝ¼õ */
|
#define DMA_CH11CR_CH11RI_Msk (0x1U << DMA_CH11CR_CH11RI_Pos)
|
#define DMA_CH11CR_CH11RI_INCREASE (0x1U << DMA_CH11CR_CH11RI_Pos) /* RAMµØÖ·µÝÔö */
|
#define DMA_CH11CR_CH11RI_DECREASE (0x0U << DMA_CH11CR_CH11RI_Pos) /* RAMµØÖ·µÝ¼õ */
|
|
#define DMA_CH11CR_CH11FI_Pos 8 /* Channel11 FlashµØÖ·Ôö¼õÉèÖ㬽öÔÚFlash->RAM´«ÊäÖÐÓÐЧ
|
1£ºFlashµØÖ·µÝÔö
|
0£ºFlashµØÖ·µÝ¼õ */
|
#define DMA_CH11CR_CH11FI_Msk (0x1U << DMA_CH11CR_CH11FI_Pos)
|
#define DMA_CH11CR_CH11FI_INCREASE (0x1U << DMA_CH11CR_CH11FI_Pos) /* FlashµØÖ·µÝÔö */
|
#define DMA_CH11CR_CH11FI_DECREASE (0x0U << DMA_CH11CR_CH11FI_Pos) /* FlashµØÖ·µÝ¼õ */
|
|
#define DMA_CH11CR_CH11FTIE_Pos 2 /* Channel11´«ÊäÍê³ÉÖжÏʹÄÜ
|
1£ºÊ¹ÄÜ´«ÊäÍê³ÉÖжÏ
|
0£º¹Ø±Õ´«ÊäÍê³ÉÖÐ¶Ï */
|
#define DMA_CH11CR_CH11FTIE_Msk (0x1U << DMA_CH11CR_CH11FTIE_Pos)
|
/* ʹÄÜ´«ÊäÍê³ÉÖÐ¶Ï */
|
/* ¹Ø±Õ´«ÊäÍê³ÉÖÐ¶Ï */
|
|
#define DMA_CH11CR_CH11HTIE_Pos 1 /* Channel11°ë³Ì´«ÊäÍê³ÉÖжÏʹÄÜ
|
1£ºÊ¹ÄÜ°ë³ÌÖжÏ
|
0£º¹Ø±Õ°ë³ÌÖÐ¶Ï */
|
#define DMA_CH11CR_CH11HTIE_Msk (0x1U << DMA_CH11CR_CH11HTIE_Pos)
|
/* ʹÄÜ°ë³ÌÖÐ¶Ï */
|
/* ¹Ø±Õ°ë³ÌÖÐ¶Ï */
|
|
#define DMA_CH11CR_CH11EN_Pos 0 /* Channel11ʹÄÜ
|
1£ºÆô¶¯Í¨µÀ0
|
0£º¹Ø±ÕͨµÀ0 */
|
#define DMA_CH11CR_CH11EN_Msk (0x1U << DMA_CH11CR_CH11EN_Pos)
|
/* Æô¶¯Í¨µÀ0 */
|
/* ¹Ø±ÕͨµÀ0 */
|
|
#define DMA_CH11FAR_CH11FLSAD_Pos 0 /* Channel11 FlashÖ¸ÕëµØÖ·£¬DMA´«ÊäÆô¶¯Ç°Èí¼þÏò´Ë¼Ä´æÆ÷дÈëFlashÄ¿±êµØÖ·£¬DMAÆô¶¯ºó´Ë¼Ä´æÆ÷ËæDMA´«Êä×ÔÔö»ò×Ô¼õ
|
Èí¼þ¿ÉÒÔ²éѯµ±Ç°DMA´«ÊäµÄÄ¿±êFlashµØÖ·
|
´Ë¼Ä´æÆ÷µÍ루bit5-0£©½öÔÚFlash->RAM´«ÊäÖÐÓÐЧ£¬RAM->Flash´«ÊäÖÐĬÈ϶ÔÆëFlashµÄhalf-sectorÆðʼµØÖ· */
|
#define DMA_CH11FAR_CH11FLSAD_Msk (0x7fffU << DMA_CH11FAR_CH11FLSAD_Pos)
|
|
#define DMA_CH11RAR_CH7RAMAD_Pos 0 /* Channel7 RAM×ÖÖ¸ÕëµØÖ·£¬DMA´«ÊäÆô¶¯Ç°Èí¼þÏò´Ë¼Ä´æÆ÷дÈëRAMÄ¿±êµØÖ·£¨wordµØÖ·£©£¬DMAÆô¶¯ºó´Ë¼Ä´æÆ÷ËæDMA´«Êä×ÔÔö»ò×Ô¼õ
|
Èí¼þ¿ÉÒÔ²éѯµ±Ç°DMA´«ÊäµÄÄ¿±êRAMµØÖ· */
|
#define DMA_CH11RAR_CH7RAMAD_Msk (0x7fffU << DMA_CH11RAR_CH7RAMAD_Pos)
|
|
#define DMA_ISR_DMA_ADDRERR_Pos 28 /* DMA´«ÊäµØÖ·´íÎó±êÖ¾£¬µ±´æ´¢Æ÷Ö¸Õ볬¹ýRAMºÍFlashºÏ·¨µØÖ··¶Î§Ê±ÖÃλ */
|
#define DMA_ISR_DMA_ADDRERR_Msk (0x1U << DMA_ISR_DMA_ADDRERR_Pos)
|
|
#define DMA_ISR_DMACHFT_Pos 16 /* DMAͨµÀx´«ÊäÍê³É±êÖ¾£¬Ó²¼þÖÃ룬Èí¼þд1ÇåÁã
|
1£º¶ÔӦͨµÀ´«ÊäÍê³É
|
0£º¶ÔӦͨµÀ´«ÊäδÍê³É */
|
#define DMA_ISR_DMACHFT_Msk (0xfffU << DMA_ISR_DMACHFT_Pos)
|
|
#define DMA_ISR_DMACHHT_Pos 0 /* DMAͨµÀx´«Êä°ë³Ì±êÖ¾£¬Ó²¼þÖÃ룬Èí¼þд1ÇåÁã */
|
#define DMA_ISR_DMACHHT_Msk (0xfffU << DMA_ISR_DMACHHT_Pos)
|
|
#define DMA_CHxCSR_CHxTSIZE_SDW_Pos 16 /* Channelx´«Ê䳤¶Èshadow¼Ä´æÆ÷£»Ñ»·Ä£Ê½ÏÂÈç¹ûʹÄÜÁËCIRC_UPD¼Ä´æÆ÷£¬ÔòÔÚ±¾ÂÖ´«ÊäÍê³Éºó½«shadow¼Ä´æÆ÷Öµ¸´ÖƵ½CHxTSIZEÖС£ */
|
#define DMA_CHxCSR_CHxTSIZE_SDW_Msk (0x1fffU << DMA_CHxCSR_CHxTSIZE_SDW_Pos)
|
|
#define DMA_CHxCSR_CHxINC_SDW_Pos 11 /* RAMµØÖ·Ôö¼õÉèÖÃshadow¼Ä´æÆ÷£¬Ñ»·Ä£Ê½ÏÂÈç¹ûʹÄÜÁËCIRC_UPD¼Ä´æÆ÷£¬ÔòÔÚ±¾ÂÖ´«ÊäÍê³Éºó½«shadow¼Ä´æÆ÷Öµ¸´ÖƵ½CHxTSIZEÖС£ */
|
#define DMA_CHxCSR_CHxINC_SDW_Msk (0x1U << DMA_CHxCSR_CHxINC_SDW_Pos)
|
|
#define DMA_CHxMASR_CHxMAD_SDW_Pos 0 /* Channelx´æ´¢Æ÷Ö¸ÕëµØÖ·Ó°×ӼĴæÆ÷¡£
|
Ñ»·Ä£Ê½ÏÂÈç¹ûʹÄÜÁËCIRC_UPD¼Ä´æÆ÷£¬ÔòÔÚ±¾ÂÖ´«ÊäÍê³Éºó½«shadow¼Ä´æÆ÷Öµ¸´ÖƵ½CHxMEMADÖС£ */
|
#define DMA_CHxMASR_CHxMAD_SDW_Msk (0xffffffffU << DMA_CHxMASR_CHxMAD_SDW_Pos)
|
//Macro_End
|
|
/* Exported functions --------------------------------------------------------*/
|
extern void DMA_Deinit(void);
|
|
/* DMA´íÎóµØÖ·ÖжÏʹÄÜ
|
1£ºÔÊÐí´íÎóµØÖ·ÖжÏ
|
0£º½ûÖ¹´íÎóµØÖ·ÖÐ¶Ï Ïà¹Øº¯Êý */
|
extern void DMA_GCR_DMA_ADDRERR_EN_Setable(FunState NewState);
|
extern FunState DMA_GCR_DMA_ADDRERR_EN_Getable(void);
|
|
/* DMAÈ«¾ÖʹÄÜ
|
1£ºDMAʹÄÜ
|
0£ºDMA¹Ø±Õ Ïà¹Øº¯Êý */
|
extern void DMA_GCR_DMAEN_Setable(FunState NewState);
|
extern FunState DMA_GCR_DMAEN_Getable(void);
|
|
/* Channelx´«Ê䳤¶È£¬1-8192´Î´«Êä Ïà¹Øº¯Êý */
|
extern void DMA_CHxCR_CHxTSIZE_Set(DMA_CH_Type CHx, uint32_t SetValue);
|
extern uint32_t DMA_CHxCR_CHxTSIZE_Get(DMA_CH_Type CHx);
|
|
/* ChannelxÓÅÏȼ¶
|
00£ºLow
|
01£ºMedium
|
10£ºHigh
|
11£ºVery High Ïà¹Øº¯Êý */
|
extern void DMA_CHxCR_CHxPRI_Set(DMA_CH_Type CHx, uint32_t SetValue);
|
extern uint32_t DMA_CHxCR_CHxPRI_Get(DMA_CH_Type CHx);
|
|
/* RAMµØÖ·Ôö¼õÉèÖÃ
|
1£ºRAMµØÖ·µÝÔö
|
0£ºRAMµØÖ·µÝ¼õ Ïà¹Øº¯Êý */
|
extern void DMA_CHxCR_CHxINC_Set(DMA_CH_Type CHx, uint32_t SetValue);
|
extern uint32_t DMA_CHxCR_CHxINC_Get(DMA_CH_Type CHx);
|
|
/* ChannelxÍâÉèÇëÇóÓ³Éä
|
ÿ¸öͨµÀ¿ÉÒÔ½ÓÊÜ8¸öÍâÉèÇëÇó£¬ÍâÉèÇëÇóµÄÓ³Éä²Î¼û23.6.1DMAÇëÇóÓ³Éä Ïà¹Øº¯Êý */
|
extern void DMA_CHxCR_CHxSSEL_Set(DMA_CH_Type CHx, uint32_t SetValue);
|
extern uint32_t DMA_CHxCR_CHxSSEL_Get(DMA_CH_Type CHx);
|
|
/* Ñ»·»º³åģʽÏÂ×Ô¶¯¸üд«Êä²ÎÊý£¬±¾ÂÖ´«ÊäÍê³Éºó½«shadow¼Ä´æÆ÷ÄÚÈݸ´ÖƵ½¿ØÖƼĴæÆ÷
|
0£º½ûÖ¹×Ô¶¯¸üÐÂ
|
1£ºÊ¹ÄÜ×Ô¶¯¸üÐÂ
|
×¢Ò⣺½öͨµÀ0~6Ö§³Ö´Ë¹¦ÄÜ£¬Í¨µÀ7~10Î޴˼ĴæÆ÷ Ïà¹Øº¯Êý */
|
extern void DMA_CHxCR_CIRC_UPD_Setable(DMA_CH_Type CHx, FunState NewState);
|
extern FunState DMA_CHxCR_CIRC_UPD_Getable(DMA_CH_Type CHx);
|
|
/* ͨµÀ´«Êä·½Ïò
|
0£º´ÓÍâÉè¶ÁÈ¡Êý¾ÝдÈëRAM
|
1£º´ÓRAM¶ÁÈ¡Êý¾ÝдÈëÍâÉè Ïà¹Øº¯Êý */
|
extern void DMA_CHxCR_DIR_Set(DMA_CH_Type CHx, uint32_t SetValue);
|
extern uint32_t DMA_CHxCR_DIR_Get(DMA_CH_Type CHx);
|
|
/* ´«Êä´ø¿íÉèÖÃ
|
00£º×Ö½Ú£¬8bit
|
01£º°ë×Ö£¬16bit
|
10£º×Ö£¬32bit
|
11£ºRFU Ïà¹Øº¯Êý */
|
extern void DMA_CHxCR_BDW_Set(DMA_CH_Type CHx, uint32_t SetValue);
|
extern uint32_t DMA_CHxCR_BDW_Get(DMA_CH_Type CHx);
|
|
/* Ñ»·»º³åģʽ
|
0£º¹Ø±ÕÑ»·Ä£Ê½
|
1£ºÊ¹ÄÜÑ»·Ä£Ê½ Ïà¹Øº¯Êý */
|
extern void DMA_CHxCR_CIRC_Setable(DMA_CH_Type CHx, FunState NewState);
|
extern FunState DMA_CHxCR_CIRC_Getable(DMA_CH_Type CHx);
|
|
/* Channelx´«ÊäÍê³ÉÖжÏʹÄÜ
|
1£ºÊ¹ÄÜ´«ÊäÍê³ÉÖжÏ
|
0£º¹Ø±Õ´«ÊäÍê³ÉÖÐ¶Ï Ïà¹Øº¯Êý */
|
extern void DMA_CHxCR_CHxFTIE_Setable(DMA_CH_Type CHx, FunState NewState);
|
extern FunState DMA_CHxCR_CHxFTIE_Getable(DMA_CH_Type CHx);
|
|
/* Channelx°ë³Ì´«ÊäÍê³ÉÖжÏʹÄÜ
|
1£ºÊ¹ÄÜ°ë³ÌÖжÏ
|
0£º¹Ø±Õ°ë³ÌÖÐ¶Ï Ïà¹Øº¯Êý */
|
extern void DMA_CHxCR_CHxHTIE_Setable(DMA_CH_Type CHx, FunState NewState);
|
extern FunState DMA_CHxCR_CHxHTIE_Getable(DMA_CH_Type CHx);
|
|
/* ChannelxʹÄÜ
|
1£ºÆô¶¯Í¨µÀ0
|
0£º¹Ø±ÕͨµÀ0 Ïà¹Øº¯Êý */
|
extern void DMA_CHxCR_ChxEN_Setable(DMA_CH_Type CHx, FunState NewState);
|
extern FunState DMA_CHxCR_ChxEN_Getable(DMA_CH_Type CHx);
|
|
/* Channelx´æ´¢Æ÷Ö¸ÕëµØÖ·£¬DMA´«ÊäÆô¶¯Ç°Èí¼þÏò´Ë¼Ä´æÆ÷дÈë´æ´¢Æ÷Ä¿±êµØÖ·¡£
|
µ±Ö¸ÕëÖ¸Ïò¿ÕµØַʱ£¬DMA·ÃÎʽ«´¥·¢hardfault
|
µ±Ö¸ÕëÖ¸ÏòFlashʱ£¬½ûÖ¹ÏòFlashдÈëÊý¾Ý¡£
|
Èí¼þ¿ÉÒÔ²éѯµ±Ç°DMA´«ÊäµÄÄ¿±ê´æ´¢Æ÷µØÖ·¡£
|
|
×¢Ò⣺´ËÖ¸Õë½ûÖ¹Ö¸Ïò0x00080000~0x1FFFFFFFµØÖ·£¬Õâ¶ÎµØַΪflash±£ÁôÐÅÏ¢Çø£¬Ö¸ÏòÕâ¶ÎµØÖ·¿ÉÄÜÔÚDMA·ÃÎÊÖе¼Ö²»¿ÉÔ¤¼ÆµÄ½á¹û Ïà¹Øº¯Êý */
|
extern void DMA_CHxMAR_Write(DMA_CH_Type CHx, uint32_t SetValue);
|
extern uint32_t DMA_CHxMAR_Read(DMA_CH_Type CHx);
|
|
/* Channel11´«Ê䳤¶È£¬1-8192´Î´«Ê䣬½öÔÚFlash->RAM´«ÊäʱÓÐЧ£¬RAM->Flash´«ÊäΪ¹Ì¶¨³¤¶È64´Î´«Êä Ïà¹Øº¯Êý */
|
extern void DMA_CH11CR_CH11TSIZE_Set(uint32_t SetValue);
|
extern uint32_t DMA_CH11CR_CH11TSIZE_Get(void);
|
|
/* Channel11ÓÅÏȼ¶
|
00£ºLow
|
01£ºMedium
|
10£ºHigh
|
11£ºVery High Ïà¹Øº¯Êý */
|
extern void DMA_CH11CR_CH11PRI_Set(uint32_t SetValue);
|
extern uint32_t DMA_CH11CR_CH11PRI_Get(void);
|
|
/* Channel11´«Êä·½Ïò
|
1£ºFlash->RAM´«Êä
|
0£ºRAM->Flash´«Êä Ïà¹Øº¯Êý */
|
extern void DMA_CH11CR_CH11DIR_Set(uint32_t SetValue);
|
extern uint32_t DMA_CH11CR_CH11DIR_Get(void);
|
|
/* Channel11 RAMµØÖ·Ôö¼õÉèÖ㬽öÔÚFlash->RAM´«ÊäÖÐÓÐЧ
|
1£ºRAMµØÖ·µÝÔö
|
0£ºRAMµØÖ·µÝ¼õ Ïà¹Øº¯Êý */
|
extern void DMA_CH11CR_CH11RI_Set(uint32_t SetValue);
|
extern uint32_t DMA_CH11CR_CH11RI_Get(void);
|
|
/* Channel11 FlashµØÖ·Ôö¼õÉèÖ㬽öÔÚFlash->RAM´«ÊäÖÐÓÐЧ
|
1£ºFlashµØÖ·µÝÔö
|
0£ºFlashµØÖ·µÝ¼õ Ïà¹Øº¯Êý */
|
extern void DMA_CH11CR_CH11FI_Set(uint32_t SetValue);
|
extern uint32_t DMA_CH11CR_CH11FI_Get(void);
|
|
/* Channel11´«ÊäÍê³ÉÖжÏʹÄÜ
|
1£ºÊ¹ÄÜ´«ÊäÍê³ÉÖжÏ
|
0£º¹Ø±Õ´«ÊäÍê³ÉÖÐ¶Ï Ïà¹Øº¯Êý */
|
extern void DMA_CH11CR_CH11FTIE_Setable(FunState NewState);
|
extern FunState DMA_CH11CR_CH11FTIE_Getable(void);
|
|
/* Channel11°ë³Ì´«ÊäÍê³ÉÖжÏʹÄÜ
|
1£ºÊ¹ÄÜ°ë³ÌÖжÏ
|
0£º¹Ø±Õ°ë³ÌÖÐ¶Ï Ïà¹Øº¯Êý */
|
extern void DMA_CH11CR_CH11HTIE_Setable(FunState NewState);
|
extern FunState DMA_CH11CR_CH11HTIE_Getable(void);
|
|
/* Channel11ʹÄÜ
|
1£ºÆô¶¯Í¨µÀ0
|
0£º¹Ø±ÕͨµÀ0 Ïà¹Øº¯Êý */
|
extern void DMA_CH11CR_CH11EN_Setable(FunState NewState);
|
extern FunState DMA_CH11CR_CH11EN_Getable(void);
|
|
/* Channel11 FlashÖ¸ÕëµØÖ·£¬DMA´«ÊäÆô¶¯Ç°Èí¼þÏò´Ë¼Ä´æÆ÷дÈëFlashÄ¿±êµØÖ·£¬DMAÆô¶¯ºó´Ë¼Ä´æÆ÷ËæDMA´«Êä×ÔÔö»ò×Ô¼õ
|
Èí¼þ¿ÉÒÔ²éѯµ±Ç°DMA´«ÊäµÄÄ¿±êFlashµØÖ·
|
´Ë¼Ä´æÆ÷µÍ루bit5-0£©½öÔÚFlash->RAM´«ÊäÖÐÓÐЧ£¬RAM->Flash´«ÊäÖÐĬÈ϶ÔÆëFlashµÄhalf-sectorÆðʼµØÖ· Ïà¹Øº¯Êý */
|
extern void DMA_CH11FAR_Write(uint32_t SetValue);
|
extern uint32_t DMA_CH11FAR_Read(void);
|
|
/* Channel7 RAM×ÖÖ¸ÕëµØÖ·£¬DMA´«ÊäÆô¶¯Ç°Èí¼þÏò´Ë¼Ä´æÆ÷дÈëRAMÄ¿±êµØÖ·£¨wordµØÖ·£©£¬DMAÆô¶¯ºó´Ë¼Ä´æÆ÷ËæDMA´«Êä×ÔÔö»ò×Ô¼õ
|
Èí¼þ¿ÉÒÔ²éѯµ±Ç°DMA´«ÊäµÄÄ¿±êRAMµØÖ· Ïà¹Øº¯Êý */
|
extern void DMA_CH11RAR_Write(uint32_t SetValue);
|
extern uint32_t DMA_CH11RAR_Read(void);
|
|
/* DMA´«ÊäµØÖ·´íÎó±êÖ¾£¬µ±´æ´¢Æ÷Ö¸Õ볬¹ýRAMºÍFlashºÏ·¨µØÖ··¶Î§Ê±ÖÃλ Ïà¹Øº¯Êý */
|
extern void DMA_ISR_DMA_ADDRERR_Clr(void);
|
extern FlagStatus DMA_ISR_DMA_ADDRERR_Chk(void);
|
|
/* DMAͨµÀx´«ÊäÍê³É±êÖ¾£¬Ó²¼þÖÃ룬Èí¼þд1ÇåÁã
|
1£º¶ÔӦͨµÀ´«ÊäÍê³É
|
0£º¶ÔӦͨµÀ´«ÊäδÍê³É Ïà¹Øº¯Êý */
|
extern void DMA_ISR_DMACHFT_Clr(DMA_CH_Type CHx);
|
extern FlagStatus DMA_ISR_DMACHFT_Chk(DMA_CH_Type CHx);
|
|
/* DMAͨµÀx´«Êä°ë³Ì±êÖ¾£¬Ó²¼þÖÃ룬Èí¼þд1ÇåÁã Ïà¹Øº¯Êý */
|
extern void DMA_ISR_DMACHHT_Clr(DMA_CH_Type CHx);
|
extern FlagStatus DMA_ISR_DMACHHT_Chk(DMA_CH_Type CHx);
|
|
/* Channelx´«Ê䳤¶Èshadow¼Ä´æÆ÷£»Ñ»·Ä£Ê½ÏÂÈç¹ûʹÄÜÁËCIRC_UPD¼Ä´æÆ÷£¬ÔòÔÚ±¾ÂÖ´«ÊäÍê³Éºó½«shadow¼Ä´æÆ÷Öµ¸´ÖƵ½CHxTSIZEÖС£ Ïà¹Øº¯Êý */
|
extern void DMA_CHxCSR_CHxTSIZE_SDW_Set(DMA_CH_Type CHx, uint32_t SetValue);
|
extern uint32_t DMA_CHxCSR_CHxTSIZE_SDW_Get(DMA_CH_Type CHx);
|
|
/* RAMµØÖ·Ôö¼õÉèÖÃshadow¼Ä´æÆ÷£¬Ñ»·Ä£Ê½ÏÂÈç¹ûʹÄÜÁËCIRC_UPD¼Ä´æÆ÷£¬ÔòÔÚ±¾ÂÖ´«ÊäÍê³Éºó½«shadow¼Ä´æÆ÷Öµ¸´ÖƵ½CHxTSIZEÖС£ Ïà¹Øº¯Êý */
|
extern void DMA_CHxCSR_CHxINC_SDW_Set(DMA_CH_Type CHx, uint32_t SetValue);
|
extern uint32_t DMA_CHxCSR_CHxINC_SDW_Get(DMA_CH_Type CHx);
|
|
/* Channelx´æ´¢Æ÷Ö¸ÕëµØÖ·Ó°×ӼĴæÆ÷¡£
|
Ñ»·Ä£Ê½ÏÂÈç¹ûʹÄÜÁËCIRC_UPD¼Ä´æÆ÷£¬ÔòÔÚ±¾ÂÖ´«ÊäÍê³Éºó½«shadow¼Ä´æÆ÷Öµ¸´ÖƵ½CHxMEMADÖС£ Ïà¹Øº¯Êý */
|
extern void DMA_CHxMASR_Write(DMA_CH_Type CHx, uint32_t SetValue);
|
extern uint32_t DMA_CHxMASR_Read(DMA_CH_Type CHx);
|
//Announce_End
|
|
void DMA_DeInit(void);
|
void DMA_Init(DMA_InitTypeDef *para);
|
|
//Announce_End
|
#ifdef __cplusplus
|
}
|
#endif
|
|
#endif /* __FM33A0XXEV_DMA_H */
|
