/**
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******************************************************************************
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* @file fm33a0xxev_lptim.h
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* @author FM33A0XXEV Application Team
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* @version V1.0.0
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* @date 16-April-2020
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* @brief This file contains all the functions prototypes for the LPTIM firmware library.
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __FM33A0XXEV_LPTIM_H
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#define __FM33A0XXEV_LPTIM_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "FM33A0XXEV.h"
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#define LPTIM_CFGR_ETR_AFEN_Pos 24 /* LPT_ETRÊäÈëÄ£ÄâÂ˲¨Ê¹ÄÜ(External Trigger input Analog Filter Enable)
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0£º¹Ø±ÕÄ£ÄâÂ˲¨
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1£ºÊ¹ÄÜÄ£ÄâÂ˲¨£¬Â˲¨¿í¶ÈÔ¼100ns */
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#define LPTIM_CFGR_ETR_AFEN_Msk (0x1U << LPTIM_CFGR_ETR_AFEN_Pos)
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/* ¹Ø±ÕÄ£ÄâÂ˲¨ */
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/* ʹÄÜÄ£ÄâÂ˲¨£¬Â˲¨¿í¶ÈÔ¼100ns */
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#define LPTIM_CFGR_PSCSEL_Pos 14 /* ʱÖÓÔ¤·ÖƵÊäÈëÑ¡Ôñ(Prescaler input Select)
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0£ºCLKSELÑ¡ÔñµÄʱÖÓ
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1£ºLPTETRF */
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#define LPTIM_CFGR_PSCSEL_Msk (0x1U << LPTIM_CFGR_PSCSEL_Pos)
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#define LPTIM_CFGR_PSCSEL_CLKSEL (0x0U << LPTIM_CFGR_PSCSEL_Pos) /* CLKSELÑ¡ÔñµÄʱÖÓ */
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#define LPTIM_CFGR_PSCSEL_LPTETRF (0x1U << LPTIM_CFGR_PSCSEL_Pos) /* LPTETRF */
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#define LPTIM_CFGR_DIVSEL_Pos 10 /* ¼ÆÊýʱÖÓ·ÖƵѡÔñ(Counter Clock Divider Select)
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000£º1·ÖƵ
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001£º2·ÖƵ
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010£º4·ÖƵ
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011£º8·ÖƵ
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100£º16·ÖƵ
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101£º32·ÖƵ
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110£º64·ÖƵ
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111£º128·ÖƵ */
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#define LPTIM_CFGR_DIVSEL_Msk (0x7U << LPTIM_CFGR_DIVSEL_Pos)
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#define LPTIM_CFGR_DIVSEL_DIV1 (0x0U << LPTIM_CFGR_DIVSEL_Pos) /* 1·ÖƵ */
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#define LPTIM_CFGR_DIVSEL_DIV2 (0x1U << LPTIM_CFGR_DIVSEL_Pos) /* 2·ÖƵ */
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#define LPTIM_CFGR_DIVSEL_DIV4 (0x2U << LPTIM_CFGR_DIVSEL_Pos) /* 4·ÖƵ */
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#define LPTIM_CFGR_DIVSEL_DIV8 (0x3U << LPTIM_CFGR_DIVSEL_Pos) /* 8·ÖƵ */
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#define LPTIM_CFGR_DIVSEL_DIV16 (0x4U << LPTIM_CFGR_DIVSEL_Pos) /* 16·ÖƵ */
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#define LPTIM_CFGR_DIVSEL_DIV32 (0x5U << LPTIM_CFGR_DIVSEL_Pos) /* 32·ÖƵ */
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#define LPTIM_CFGR_DIVSEL_DIV64 (0x6U << LPTIM_CFGR_DIVSEL_Pos) /* 64·ÖƵ */
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#define LPTIM_CFGR_DIVSEL_DIV128 (0x7U << LPTIM_CFGR_DIVSEL_Pos) /* 128·ÖƵ */
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#define LPTIM_CFGR_EDGESEL_Pos 7 /* ETRÊäÈë±ßÑØÑ¡Ôñ(ETR Clock Edge Select)
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0£ºLPT_ETRµÄÉÏÉýÑؼÆÊý
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1£ºLPT_ETRµÄϽµÑؼÆÊý */
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#define LPTIM_CFGR_EDGESEL_Msk (0x1U << LPTIM_CFGR_EDGESEL_Pos)
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#define LPTIM_CFGR_EDGESEL_RISING (0x0U << LPTIM_CFGR_EDGESEL_Pos) /* LPT_ETRµÄÉÏÉýÑؼÆÊý */
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#define LPTIM_CFGR_EDGESEL_FALLING (0x1U << LPTIM_CFGR_EDGESEL_Pos) /* LPT_ETRµÄϽµÑؼÆÊý */
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#define LPTIM_CFGR_TRIGCFG_Pos 5 /* Íⲿ´¥·¢±ßÑØÑ¡Ôñ£¨ÐèʹÓÃÄÚ²¿Ê±ÖÓͬ²½²ÉÑùLPT_ETR£©(ETR trigger Configuration)
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00: LPT_ETRÊäÈëÐźÅÉÏÉýÑØ´¥·¢
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01: LPT_ETRÊäÈëÐźÅϽµÑØ´¥·¢
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10/11: ÍⲿÊäÈëÐźÅÉÏÉýϽµÑØ´¥·¢ */
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#define LPTIM_CFGR_TRIGCFG_Msk (0x3U << LPTIM_CFGR_TRIGCFG_Pos)
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#define LPTIM_CFGR_TRIGCFG_RISING (0x0U << LPTIM_CFGR_TRIGCFG_Pos)
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#define LPTIM_CFGR_TRIGCFG_FALLING (0x1U << LPTIM_CFGR_TRIGCFG_Pos)
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#define LPTIM_CFGR_TRIGCFG_EXTERNAL (0x2U << LPTIM_CFGR_TRIGCFG_Pos)
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#define LPTIM_CFGR_ONST_Pos 2 /* µ¥´Î¼ÆÊýģʽʹÄÜ(One State Timer)
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0£ºÁ¬Ðø¼ÆÊýģʽ£º¼ÆÊýÆ÷±»´¥·¢ºó±£³ÖÔËÐУ¬Ö±µ½±»¹Ø±ÕΪֹ¡£¼ÆÊýÆ÷´ïµ½Ä¿±êÖµºó»Øµ½0ÖØпªÊ¼¼ÆÊý£¬²¢²úÉúÒç³öÖжϡ£
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1£ºµ¥´Î¼ÆÊýģʽ£º¼ÆÊýÆ÷±»´¥·¢ºó¼ÆÊýµ½Ä¿±êÖµºó»Øµ½0£¬²¢×Ô¶¯Í£Ö¹£¬²úÉúÒç³öÖжϡ£ */
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#define LPTIM_CFGR_ONST_Msk (0x1U << LPTIM_CFGR_ONST_Pos)
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#define LPTIM_CFGR_ONST_CONTINUE (0x0U << LPTIM_CFGR_ONST_Pos) /* Á¬Ðø¼ÆÊýģʽ */
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#define LPTIM_CFGR_ONST_SINGLE (0x1U << LPTIM_CFGR_ONST_Pos) /* µ¥´Î¼ÆÊýģʽ */
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#define LPTIM_CFGR_TMODE_Pos 0 /* ¹¤×÷ģʽѡÔñ(Timer operation Mode)
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00£ºÆÕͨ¶¨Ê±Æ÷ģʽ
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01£ºTriggerÂö³å´¥·¢¼ÆÊýģʽ
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10£ºÍⲿÒì²½Âö³å¼ÆÊýģʽ
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11£ºTimeoutģʽ */
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#define LPTIM_CFGR_TMODE_Msk (0x3U << LPTIM_CFGR_TMODE_Pos)
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#define LPTIM_CFGR_TMODE_COUNTER (0x0U << LPTIM_CFGR_TMODE_Pos)
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#define LPTIM_CFGR_TMODE_PULSE (0x1U << LPTIM_CFGR_TMODE_Pos)
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#define LPTIM_CFGR_TMODE_ASY (0x2U << LPTIM_CFGR_TMODE_Pos)
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#define LPTIM_CFGR_TMODE_TIMEOUT (0x3U << LPTIM_CFGR_TMODE_Pos)
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#define LPTIM_CNTR_CNT32_Pos 0 /* 32bit¼ÆÊýÆ÷µ±Ç°¼ÆÊýÖµ(Counter 32bits-wide) */
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#define LPTIM_CNTR_CNT32_Msk (0xffffffffU << LPTIM_CNTR_CNT32_Pos)
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#define LPTIM_CCSR_CAP1SSEL_Pos 24 /* ͨµÀ1²¶×½Ô´Ñ¡Ôñ(Capture channel 1 source select)£¬½öÔÚCH1ͨµÀÅäÖÃΪÊäÈ벶׽ʱÓÐЧ
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00£ºLPT_CH1ÊäÈë
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01£ºXTLF
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10£ºRCLP
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11£ºRCMF */
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#define LPTIM_CCSR_CAP1SSEL_Msk (0x3U << LPTIM_CCSR_CAP1SSEL_Pos)
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#define LPTIM_CCSR_CAP1SSEL_LPT_CH1 (0x0U << LPTIM_CCSR_CAP1SSEL_Pos)
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#define LPTIM_CCSR_CAP1SSEL_XTLF (0x1U << LPTIM_CCSR_CAP1SSEL_Pos)
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#define LPTIM_CCSR_CAP1SSEL_RCLP (0x2U << LPTIM_CCSR_CAP1SSEL_Pos)
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#define LPTIM_CCSR_CAP1SSEL_RCMF (0x3U << LPTIM_CCSR_CAP1SSEL_Pos)
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#define LPTIM_CCSR_CAP4EDGE_Pos 23 /* ͨµÀ4µ±Ç°±»²¶×½µÄ±ßÑØ£¬ÔÚCC2IFÖÃλʱ¸üÐÂ(Channel 4 Captured Edge)
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0£ºÉÏÉýÑØ
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1£ºÏ½µÑØ */
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#define LPTIM_CCSR_CAP4EDGE_Msk (0x1U << LPTIM_CCSR_CAP4EDGE_Pos)
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#define LPTIM_CCSR_CAP4EDGE_RISING (0x0U << LPTIM_CCSR_CAP4EDGE_Pos)
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#define LPTIM_CCSR_CAP4EDGE_FALLING (0x1U << LPTIM_CCSR_CAP4EDGE_Pos)
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#define LPTIM_CCSR_CAP3EDGE_Pos 22
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#define LPTIM_CCSR_CAP3EDGE_Msk (0x1U << LPTIM_CCSR_CAP3EDGE_Pos)
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#define LPTIM_CCSR_CAP3EDGE_RISING (0x0U << LPTIM_CCSR_CAP3EDGE_Pos)
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#define LPTIM_CCSR_CAP3EDGE_FALLING (0x1U << LPTIM_CCSR_CAP3EDGE_Pos)
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#define LPTIM_CCSR_CAP2EDGE_Pos 21
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#define LPTIM_CCSR_CAP2EDGE_Msk (0x1U << LPTIM_CCSR_CAP2EDGE_Pos)
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#define LPTIM_CCSR_CAP2EDGE_RISING (0x0U << LPTIM_CCSR_CAP2EDGE_Pos)
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#define LPTIM_CCSR_CAP2EDGE_FALLING (0x1U << LPTIM_CCSR_CAP2EDGE_Pos)
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#define LPTIM_CCSR_CAP1EDGE_Pos 20
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#define LPTIM_CCSR_CAP1EDGE_Msk (0x1U << LPTIM_CCSR_CAP1EDGE_Pos)
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#define LPTIM_CCSR_CAP1EDGE_RISING (0x0U << LPTIM_CCSR_CAP1EDGE_Pos)
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#define LPTIM_CCSR_CAP1EDGE_FALLING (0x1U << LPTIM_CCSR_CAP1EDGE_Pos)
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#define LPTIM_CCSR_POLAR4_Pos 19 /* ͨµÀ4±È½ÏÊä³ö²¨Ðμ«ÐÔÑ¡Ôñ (Channel 4 compare output Polarity)
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0£ºÕý¼«ÐÔ²¨ÐΣ¬ÆðʼΪµÍ£¬¼ÆÊýÖµ==±È½ÏֵʱÖøߣ¬¼ÆÊýÖµ==ARRʱ»Ö¸´ÎªµÍ
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1£º¸º¼«ÐÔ²¨ÐΣ¬Õý¼«ÐÔ²¨ÐÎÈ¡·´ */
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#define LPTIM_CCSR_POLAR4_Msk (0x1U << LPTIM_CCSR_POLAR4_Pos)
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#define LPTIM_CCSR_POLAR4_POS (0x0U << LPTIM_CCSR_POLAR4_Pos)
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#define LPTIM_CCSR_POLAR4_NEG (0x1U << LPTIM_CCSR_POLAR4_Pos)
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#define LPTIM_CCSR_POLAR3_Pos 18
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#define LPTIM_CCSR_POLAR3_Msk (0x1U << LPTIM_CCSR_POLAR3_Pos)
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#define LPTIM_CCSR_POLAR3_POS (0x0U << LPTIM_CCSR_POLAR3_Pos)
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#define LPTIM_CCSR_POLAR3_NEG (0x1U << LPTIM_CCSR_POLAR3_Pos)
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#define LPTIM_CCSR_POLAR2_Pos 17
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#define LPTIM_CCSR_POLAR2_Msk (0x1U << LPTIM_CCSR_POLAR2_Pos)
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#define LPTIM_CCSR_POLAR2_POS (0x0U << LPTIM_CCSR_POLAR2_Pos)
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#define LPTIM_CCSR_POLAR2_NEG (0x1U << LPTIM_CCSR_POLAR2_Pos)
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#define LPTIM_CCSR_POLAR1_Pos 16
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#define LPTIM_CCSR_POLAR1_Msk (0x1U << LPTIM_CCSR_POLAR1_Pos)
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#define LPTIM_CCSR_POLAR1_POS (0x0U << LPTIM_CCSR_POLAR1_Pos)
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#define LPTIM_CCSR_POLAR1_NEG (0x1U << LPTIM_CCSR_POLAR1_Pos)
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#define LPTIM_CCSR_CAPCFG4_Pos 14 /* ͨµÀ4²¶×½±ßÑØÑ¡Ôñ(Channel 4 Capture edge Config)
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00£ºÉÏÉýÑز¶×½
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01£ºÏ½µÑز¶×½
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10£ºÉÏÉýϽµÑز¶×½
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11£ºRFU */
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#define LPTIM_CCSR_CAPCFG4_Msk (0x3U << LPTIM_CCSR_CAPCFG4_Pos)
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#define LPTIM_CCSR_CAPCFG4_RISING (0x0U << LPTIM_CCSR_CAPCFG4_Pos)
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#define LPTIM_CCSR_CAPCFG4_FALLING (0x1U << LPTIM_CCSR_CAPCFG4_Pos)
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#define LPTIM_CCSR_CAPCFG4_BOTH (0x2U << LPTIM_CCSR_CAPCFG4_Pos)
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#define LPTIM_CCSR_CAPCFG3_Pos 12
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#define LPTIM_CCSR_CAPCFG3_Msk (0x3U << LPTIM_CCSR_CAPCFG3_Pos)
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#define LPTIM_CCSR_CAPCFG3_RISING (0x0U << LPTIM_CCSR_CAPCFG3_Pos)
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#define LPTIM_CCSR_CAPCFG3_FALLING (0x1U << LPTIM_CCSR_CAPCFG3_Pos)
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#define LPTIM_CCSR_CAPCFG3_BOTH (0x2U << LPTIM_CCSR_CAPCFG3_Pos)
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#define LPTIM_CCSR_CAPCFG2_Pos 10
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#define LPTIM_CCSR_CAPCFG2_Msk (0x3U << LPTIM_CCSR_CAPCFG2_Pos)
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#define LPTIM_CCSR_CAPCFG2_RISING (0x0U << LPTIM_CCSR_CAPCFG2_Pos)
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#define LPTIM_CCSR_CAPCFG2_FALLING (0x1U << LPTIM_CCSR_CAPCFG2_Pos)
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#define LPTIM_CCSR_CAPCFG2_BOTH (0x2U << LPTIM_CCSR_CAPCFG2_Pos)
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#define LPTIM_CCSR_CAPCFG1_Pos 8
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#define LPTIM_CCSR_CAPCFG1_Msk (0x3U << LPTIM_CCSR_CAPCFG1_Pos)
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#define LPTIM_CCSR_CAPCFG1_RISING (0x0U << LPTIM_CCSR_CAPCFG1_Pos)
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#define LPTIM_CCSR_CAPCFG1_FALLING (0x1U << LPTIM_CCSR_CAPCFG1_Pos)
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#define LPTIM_CCSR_CAPCFG1_BOTH (0x2U << LPTIM_CCSR_CAPCFG1_Pos)
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#define LPTIM_CCSR_CC4S_Pos 6 /* ͨµÀ4²¶×½/±È½Ï¹¦ÄÜʹÄÜ(Channel 4 Capture/Compare Select)
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00,11£º½ûֹͨµÀ4²¶×½/±È½Ï¹¦ÄÜ
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01£ºÊ¹ÄÜͨµÀ4²¶×½¹¦ÄÜ£¨LPT_CH4ΪÊäÈ룩
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10£ºÊ¹ÄÜͨµÀ4±È½Ï¹¦ÄÜ£¨LPT_CH4ΪÊä³ö£© */
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#define LPTIM_CCSR_CC4S_Msk (0x3U << LPTIM_CCSR_CC4S_Pos)
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#define LPTIM_CCSR_CC4S_NON (0x0U << LPTIM_CCSR_CC4S_Pos)
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#define LPTIM_CCSR_CC4S_LPT_CH4_IN (0x1U << LPTIM_CCSR_CC4S_Pos)
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#define LPTIM_CCSR_CC4S_LPT_CH4_OUT (0x2U << LPTIM_CCSR_CC4S_Pos)
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#define LPTIM_CCSR_CC3S_Pos 4
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#define LPTIM_CCSR_CC3S_Msk (0x3U << LPTIM_CCSR_CC3S_Pos)
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#define LPTIM_CCSR_CC3S_NON (0x0U << LPTIM_CCSR_CC3S_Pos)
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#define LPTIM_CCSR_CC3S_LPT_CH3_IN (0x1U << LPTIM_CCSR_CC3S_Pos)
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#define LPTIM_CCSR_CC3S_LPT_CH3_OUT (0x2U << LPTIM_CCSR_CC3S_Pos)
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#define LPTIM_CCSR_CC2S_Pos 2
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#define LPTIM_CCSR_CC2S_Msk (0x3U << LPTIM_CCSR_CC2S_Pos)
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#define LPTIM_CCSR_CC2S_NON (0x0U << LPTIM_CCSR_CC2S_Pos)
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#define LPTIM_CCSR_CC2S_LPT_CH2_IN (0x1U << LPTIM_CCSR_CC2S_Pos)
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#define LPTIM_CCSR_CC2S_LPT_CH2_OUT (0x2U << LPTIM_CCSR_CC2S_Pos)
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#define LPTIM_CCSR_CC1S_Pos 0
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#define LPTIM_CCSR_CC1S_Msk (0x3U << LPTIM_CCSR_CC1S_Pos)
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#define LPTIM_CCSR_CC1S_NON (0x0U << LPTIM_CCSR_CC1S_Pos)
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#define LPTIM_CCSR_CC1S_LPT_CH1_IN (0x1U << LPTIM_CCSR_CC1S_Pos)
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#define LPTIM_CCSR_CC1S_LPT_CH1_OUT (0x2U << LPTIM_CCSR_CC1S_Pos)
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#define LPTIM_ARR_ARR_Pos 0 /* ×Ô¶¯ÖØÔØÄ¿±ê¼Ä´æÆ÷(Auto-Reload Register)
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µ±¼ÆÊýÆ÷¼ÆÊýÖµµÈÓÚARRʱ£¬¼ÆÊýÆ÷»Øµ½³õÖµÖØпªÊ¼ÏòÉϼÆÊý */
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#define LPTIM_ARR_ARR_Msk (0xffffffffU << LPTIM_ARR_ARR_Pos)
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#define LPTIM_IER_OVR4IE_Pos 11 /* ͨµÀ4²¶×½Òç³öÖжÏʹÄÜ(Channel 4 Over-Capture Interrupt Enable)
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1£ºÔÊÐíÖжÏ
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0£º½ûÖ¹ÖÐ¶Ï */
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#define LPTIM_IER_OVR4IE_Msk (0x1U << LPTIM_IER_OVR4IE_Pos)
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/* ÔÊÐíÖÐ¶Ï */
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/* ½ûÖ¹ÖÐ¶Ï */
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#define LPTIM_IER_OVR3IE_Pos 10 /* ͨµÀ3²¶×½Òç³öÖжÏʹÄÜ(Channel 3 Over-Capture Interrupt Enable)
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1£ºÔÊÐíÖжÏ
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0£º½ûÖ¹ÖÐ¶Ï */
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#define LPTIM_IER_OVR3IE_Msk (0x1U << LPTIM_IER_OVR3IE_Pos)
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/* ÔÊÐíÖÐ¶Ï */
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/* ½ûÖ¹ÖÐ¶Ï */
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#define LPTIM_IER_OVR2IE_Pos 9 /* ͨµÀ2²¶×½Òç³öÖжÏʹÄÜ(Channel 2 Over-Capture Interrupt Enable)
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1£ºÔÊÐíÖжÏ
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0£º½ûÖ¹ÖÐ¶Ï */
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#define LPTIM_IER_OVR2IE_Msk (0x1U << LPTIM_IER_OVR2IE_Pos)
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/* ÔÊÐíÖÐ¶Ï */
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/* ½ûÖ¹ÖÐ¶Ï */
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#define LPTIM_IER_OVR1IE_Pos 8 /* ͨµÀ1²¶×½Òç³öÖжÏʹÄÜ(Channel 1 Over-Capture Interrupt Enable)
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1£ºÔÊÐíÖжÏ
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0£º½ûÖ¹ÖÐ¶Ï */
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#define LPTIM_IER_OVR1IE_Msk (0x1U << LPTIM_IER_OVR1IE_Pos)
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/* ÔÊÐíÖÐ¶Ï */
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/* ½ûÖ¹ÖÐ¶Ï */
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#define LPTIM_IER_TRIGIE_Pos 7 /* Íⲿ´¥·¢µ½À´ÖжÏʹÄÜλ(External Trigger Interrupt Enable)
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1£ºÍⲿ´¥·¢µ½À´ÖжÏʹÄÜ
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0£ºÍⲿ´¥·¢µ½À´ÖжϽûÖ¹ */
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#define LPTIM_IER_TRIGIE_Msk (0x1U << LPTIM_IER_TRIGIE_Pos)
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/* Íⲿ´¥·¢µ½À´ÖжÏʹÄÜ */
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/* Íⲿ´¥·¢µ½À´ÖжϽûÖ¹ */
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#define LPTIM_IER_OVIE_Pos 6 /* ¼ÆÊýÆ÷Òç³öÖжÏʹÄÜλ(Counter Over-Flow Interrupt Enable)
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1£º¼ÆÊýÆ÷Òç³öÖжÏʹÄÜ
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0£º¼ÆÊýÆ÷Òç³öÖжϽûÖ¹ */
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#define LPTIM_IER_OVIE_Msk (0x1U << LPTIM_IER_OVIE_Pos)
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/* ¼ÆÊýÆ÷Òç³öÖжÏʹÄÜ */
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/* ¼ÆÊýÆ÷Òç³öÖжϽûÖ¹ */
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#define LPTIM_IER_CC4IE_Pos 3 /* ²¶×½/±È½ÏͨµÀ4ÖжÏʹÄÜλ(Capture/Compare channel 4 Interrupt Enable)
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1£º²¶×½/±È½ÏͨµÀ2ÖжÏʹÄÜ
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0£º²¶×½/±È½ÏͨµÀ2ÖжϽûÖ¹ */
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#define LPTIM_IER_CC4IE_Msk (0x1U << LPTIM_IER_CC4IE_Pos)
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/* ²¶×½/±È½ÏͨµÀ2ÖжÏʹÄÜ */
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/* ²¶×½/±È½ÏͨµÀ2ÖжϽûÖ¹ */
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#define LPTIM_IER_CC3IE_Pos 2 /* ²¶×½/±È½ÏͨµÀ3ÖжÏʹÄÜλ(Capture/Compare channel 3 Interrupt Enable)
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1£º²¶×½/±È½ÏͨµÀ1ÖжÏʹÄÜ
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0£º²¶×½/±È½ÏͨµÀ1ÖжϽûÖ¹ */
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#define LPTIM_IER_CC3IE_Msk (0x1U << LPTIM_IER_CC3IE_Pos)
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/* ²¶×½/±È½ÏͨµÀ1ÖжÏʹÄÜ */
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/* ²¶×½/±È½ÏͨµÀ1ÖжϽûÖ¹ */
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#define LPTIM_IER_CC2IE_Pos 1 /* ²¶×½/±È½ÏͨµÀ2ÖжÏʹÄÜλ(Capture/Compare channel 2 Interrupt Enable)
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1£º²¶×½/±È½ÏͨµÀ2ÖжÏʹÄÜ
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0£º²¶×½/±È½ÏͨµÀ2ÖжϽûÖ¹ */
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#define LPTIM_IER_CC2IE_Msk (0x1U << LPTIM_IER_CC2IE_Pos)
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/* ²¶×½/±È½ÏͨµÀ2ÖжÏʹÄÜ */
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/* ²¶×½/±È½ÏͨµÀ2ÖжϽûÖ¹ */
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#define LPTIM_IER_CC1IE_Pos 0 /* ²¶×½/±È½ÏͨµÀ1ÖжÏʹÄÜλ(Capture/Compare channel 1 Interrupt Enable)
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1£º²¶×½/±È½ÏͨµÀ1ÖжÏʹÄÜ
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0£º²¶×½/±È½ÏͨµÀ1ÖжϽûÖ¹ */
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#define LPTIM_IER_CC1IE_Msk (0x1U << LPTIM_IER_CC1IE_Pos)
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/* ²¶×½/±È½ÏͨµÀ1ÖжÏʹÄÜ */
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/* ²¶×½/±È½ÏͨµÀ1ÖжϽûÖ¹ */
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#define LPTIM_ISR_CAP4OVR_Pos 11
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#define LPTIM_ISR_CAP4OVR_Msk (0x1U << LPTIM_ISR_CAP4OVR_Pos)
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#define LPTIM_ISR_CAP3OVR_Pos 10
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#define LPTIM_ISR_CAP3OVR_Msk (0x1U << LPTIM_ISR_CAP3OVR_Pos)
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#define LPTIM_ISR_CAP2OVR_Pos 9
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#define LPTIM_ISR_CAP2OVR_Msk (0x1U << LPTIM_ISR_CAP2OVR_Pos)
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#define LPTIM_ISR_CAP1OVR_Pos 8
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#define LPTIM_ISR_CAP1OVR_Msk (0x1U << LPTIM_ISR_CAP1OVR_Pos)
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#define LPTIM_ISR_TRIGIF_Pos 7
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#define LPTIM_ISR_TRIGIF_Msk (0x1U << LPTIM_ISR_TRIGIF_Pos)
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#define LPTIM_ISR_OVIF_Pos 6
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#define LPTIM_ISR_OVIF_Msk (0x1U << LPTIM_ISR_OVIF_Pos)
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#define LPTIM_ISR_CC4IF_Pos 3
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#define LPTIM_ISR_CC4IF_Msk (0x1U << LPTIM_ISR_CC4IF_Pos)
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#define LPTIM_ISR_CC3IF_Pos 2
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#define LPTIM_ISR_CC3IF_Msk (0x1U << LPTIM_ISR_CC3IF_Pos)
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#define LPTIM_ISR_CC2IF_Pos 1
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#define LPTIM_ISR_CC2IF_Msk (0x1U << LPTIM_ISR_CC2IF_Pos)
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#define LPTIM_ISR_CC1IF_Pos 0
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#define LPTIM_ISR_CC1IF_Msk (0x1U << LPTIM_ISR_CC1IF_Pos)
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#define LPTIM_CR_EN_Pos 0 /* LPTIMʹÄÜλ(LPTIM Enable)
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1£ºÊ¹ÄܼÆÊýÆ÷¼ÆÊý
|
0£º½ûÖ¹¼ÆÊýÆ÷¼ÆÊý */
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#define LPTIM_CR_EN_Msk (0x1U << LPTIM_CR_EN_Pos)
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/* ʹÄܼÆÊýÆ÷¼ÆÊý */
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/* ½ûÖ¹¼ÆÊýÆ÷¼ÆÊý */
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#define LPTIM_CCR1_CCR1_Pos 0 /* ²¶×½/±È½ÏÖµ¼Ä´æÆ÷1 (Channel1 Capture/Compare Register) */
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#define LPTIM_CCR1_CCR1_Msk (0xffffffffU << LPTIM_CCR1_CCR1_Pos)
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#define LPTIM_CCR2_CCR2_Pos 0 /* ²¶×½/±È½ÏÖµ¼Ä´æÆ÷2 (Channel2 Capture/Compare Register) */
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#define LPTIM_CCR2_CCR2_Msk (0xffffffffU << LPTIM_CCR2_CCR2_Pos)
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#define LPTIM_CCR3_CCR3_Pos 0 /* ²¶×½/±È½ÏÖµ¼Ä´æÆ÷3 (Channel3 Capture/Compare Register) */
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#define LPTIM_CCR3_CCR3_Msk (0xffffffffU << LPTIM_CCR3_CCR3_Pos)
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#define LPTIM_CCR4_CCR4_Pos 0 /* ²¶×½/±È½ÏÖµ¼Ä´æÆ÷4 (Channel4 Capture/Compare Register) */
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#define LPTIM_CCR4_CCR4_Msk (0xffffffffU << LPTIM_CCR4_CCR4_Pos)
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//Macro_End
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/* Exported functions --------------------------------------------------------*/
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extern void LPTIM_Deinit(void);
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/* LPT_ETRÊäÈëÄ£ÄâÂ˲¨Ê¹ÄÜ(External Trigger input Analog Filter Enable)
|
0£º¹Ø±ÕÄ£ÄâÂ˲¨
|
1£ºÊ¹ÄÜÄ£ÄâÂ˲¨£¬Â˲¨¿í¶ÈÔ¼100ns Ïà¹Øº¯Êý */
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extern void LPTIM_CFGR_ETR_AFEN_Setable(FunState NewState);
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extern FunState LPTIM_CFGR_ETR_AFEN_Getable(void);
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|
/* ʱÖÓÔ¤·ÖƵÊäÈëÑ¡Ôñ(Prescaler input Select)
|
0£ºCLKSELÑ¡ÔñµÄʱÖÓ
|
1£ºLPTETRF Ïà¹Øº¯Êý */
|
extern void LPTIM_CFGR_PSCSEL_Set(uint32_t SetValue);
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extern uint32_t LPTIM_CFGR_PSCSEL_Get(void);
|
|
/* ¼ÆÊýʱÖÓ·ÖƵѡÔñ(Counter Clock Divider Select)
|
000£º1·ÖƵ
|
001£º2·ÖƵ
|
010£º4·ÖƵ
|
011£º8·ÖƵ
|
100£º16·ÖƵ
|
101£º32·ÖƵ
|
110£º64·ÖƵ
|
111£º128·ÖƵ Ïà¹Øº¯Êý */
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extern void LPTIM_CFGR_DIVSEL_Set(uint32_t SetValue);
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extern uint32_t LPTIM_CFGR_DIVSEL_Get(void);
|
|
/* ETRÊäÈë±ßÑØÑ¡Ôñ(ETR Clock Edge Select)
|
0£ºLPT_ETRµÄÉÏÉýÑؼÆÊý
|
1£ºLPT_ETRµÄϽµÑؼÆÊý Ïà¹Øº¯Êý */
|
extern void LPTIM_CFGR_EDGESEL_Set(uint32_t SetValue);
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extern uint32_t LPTIM_CFGR_EDGESEL_Get(void);
|
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/* Íⲿ´¥·¢±ßÑØÑ¡Ôñ£¨ÐèʹÓÃÄÚ²¿Ê±ÖÓͬ²½²ÉÑùLPT_ETR£©(ETR trigger Configuration)
|
00: LPT_ETRÊäÈëÐźÅÉÏÉýÑØ´¥·¢
|
01: LPT_ETRÊäÈëÐźÅϽµÑØ´¥·¢
|
10/11: ÍⲿÊäÈëÐźÅÉÏÉýϽµÑØ´¥·¢ Ïà¹Øº¯Êý */
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extern void LPTIM_CFGR_TRIGCFG_Set(uint32_t SetValue);
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extern uint32_t LPTIM_CFGR_TRIGCFG_Get(void);
|
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/* µ¥´Î¼ÆÊýģʽʹÄÜ(One State Timer)
|
0£ºÁ¬Ðø¼ÆÊýģʽ£º¼ÆÊýÆ÷±»´¥·¢ºó±£³ÖÔËÐУ¬Ö±µ½±»¹Ø±ÕΪֹ¡£¼ÆÊýÆ÷´ïµ½Ä¿±êÖµºó»Øµ½0ÖØпªÊ¼¼ÆÊý£¬²¢²úÉúÒç³öÖжϡ£
|
1£ºµ¥´Î¼ÆÊýģʽ£º¼ÆÊýÆ÷±»´¥·¢ºó¼ÆÊýµ½Ä¿±êÖµºó»Øµ½0£¬²¢×Ô¶¯Í£Ö¹£¬²úÉúÒç³öÖжϡ£ Ïà¹Øº¯Êý */
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extern void LPTIM_CFGR_ONST_Set(uint32_t SetValue);
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extern uint32_t LPTIM_CFGR_ONST_Get(void);
|
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/* ¹¤×÷ģʽѡÔñ(Timer operation Mode)
|
00£ºÆÕͨ¶¨Ê±Æ÷ģʽ
|
01£ºTriggerÂö³å´¥·¢¼ÆÊýģʽ
|
10£ºÍⲿÒì²½Âö³å¼ÆÊýģʽ
|
11£ºTimeoutģʽ Ïà¹Øº¯Êý */
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extern void LPTIM_CFGR_TMODE_Set(uint32_t SetValue);
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extern uint32_t LPTIM_CFGR_TMODE_Get(void);
|
|
/* 32bit¼ÆÊýÆ÷µ±Ç°¼ÆÊýÖµ(Counter 32bits-wide) Ïà¹Øº¯Êý */
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extern uint32_t LPTIM_CNTR_Read(void);
|
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/* ͨµÀ1²¶×½Ô´Ñ¡Ôñ(Capture channel 1 source select)£¬½öÔÚCH1ͨµÀÅäÖÃΪÊäÈ벶׽ʱÓÐЧ
|
00£ºLPT_CH1ÊäÈë
|
01£ºXTLF
|
10£ºRCLP
|
11£ºRCMF Ïà¹Øº¯Êý */
|
extern void LPTIM_CCSR_CAP1SSEL_Set(uint32_t SetValue);
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extern uint32_t LPTIM_CCSR_CAP1SSEL_Get(void);
|
|
/* ͨµÀ4µ±Ç°±»²¶×½µÄ±ßÑØ£¬ÔÚCC2IFÖÃλʱ¸üÐÂ(Channel 4 Captured Edge)
|
0£ºÉÏÉýÑØ
|
1£ºÏ½µÑØ Ïà¹Øº¯Êý */
|
extern void LPTIM_CCSR_CAP4EDGE_Set(uint32_t SetValue);
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extern uint32_t LPTIM_CCSR_CAP4EDGE_Get(void);
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extern void LPTIM_CCSR_CAP3EDGE_Set(uint32_t SetValue);
|
extern uint32_t LPTIM_CCSR_CAP3EDGE_Get(void);
|
extern void LPTIM_CCSR_CAP2EDGE_Set(uint32_t SetValue);
|
extern uint32_t LPTIM_CCSR_CAP2EDGE_Get(void);
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extern void LPTIM_CCSR_CAP1EDGE_Set(uint32_t SetValue);
|
extern uint32_t LPTIM_CCSR_CAP1EDGE_Get(void);
|
|
/* ͨµÀ4±È½ÏÊä³ö²¨Ðμ«ÐÔÑ¡Ôñ (Channel 4 compare output Polarity)
|
0£ºÕý¼«ÐÔ²¨ÐΣ¬ÆðʼΪµÍ£¬¼ÆÊýÖµ==±È½ÏֵʱÖøߣ¬¼ÆÊýÖµ==ARRʱ»Ö¸´ÎªµÍ
|
1£º¸º¼«ÐÔ²¨ÐΣ¬Õý¼«ÐÔ²¨ÐÎÈ¡·´ Ïà¹Øº¯Êý */
|
extern void LPTIM_CCSR_POLAR4_Set(uint32_t SetValue);
|
extern uint32_t LPTIM_CCSR_POLAR4_Get(void);
|
extern void LPTIM_CCSR_POLAR3_Set(uint32_t SetValue);
|
extern uint32_t LPTIM_CCSR_POLAR3_Get(void);
|
extern void LPTIM_CCSR_POLAR2_Set(uint32_t SetValue);
|
extern uint32_t LPTIM_CCSR_POLAR2_Get(void);
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extern void LPTIM_CCSR_POLAR1_Set(uint32_t SetValue);
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extern uint32_t LPTIM_CCSR_POLAR1_Get(void);
|
|
/* ͨµÀ4²¶×½±ßÑØÑ¡Ôñ(Channel 4 Capture edge Config)
|
00£ºÉÏÉýÑز¶×½
|
01£ºÏ½µÑز¶×½
|
10£ºÉÏÉýϽµÑز¶×½
|
11£ºRFU Ïà¹Øº¯Êý */
|
extern void LPTIM_CCSR_CAPCFG4_Set(uint32_t SetValue);
|
extern uint32_t LPTIM_CCSR_CAPCFG4_Get(void);
|
extern void LPTIM_CCSR_CAPCFG3_Set(uint32_t SetValue);
|
extern uint32_t LPTIM_CCSR_CAPCFG3_Get(void);
|
extern void LPTIM_CCSR_CAPCFG2_Set(uint32_t SetValue);
|
extern uint32_t LPTIM_CCSR_CAPCFG2_Get(void);
|
extern void LPTIM_CCSR_CAPCFG1_Set(uint32_t SetValue);
|
extern uint32_t LPTIM_CCSR_CAPCFG1_Get(void);
|
|
/* ͨµÀ4²¶×½/±È½Ï¹¦ÄÜʹÄÜ(Channel 4 Capture/Compare Select)
|
00,11£º½ûֹͨµÀ4²¶×½/±È½Ï¹¦ÄÜ
|
01£ºÊ¹ÄÜͨµÀ4²¶×½¹¦ÄÜ£¨LPT_CH4ΪÊäÈ룩
|
10£ºÊ¹ÄÜͨµÀ4±È½Ï¹¦ÄÜ£¨LPT_CH4ΪÊä³ö£© Ïà¹Øº¯Êý */
|
extern void LPTIM_CCSR_CC4S_Set(uint32_t SetValue);
|
extern uint32_t LPTIM_CCSR_CC4S_Get(void);
|
extern void LPTIM_CCSR_CC3S_Set(uint32_t SetValue);
|
extern uint32_t LPTIM_CCSR_CC3S_Get(void);
|
extern void LPTIM_CCSR_CC2S_Set(uint32_t SetValue);
|
extern uint32_t LPTIM_CCSR_CC2S_Get(void);
|
extern void LPTIM_CCSR_CC1S_Set(uint32_t SetValue);
|
extern uint32_t LPTIM_CCSR_CC1S_Get(void);
|
|
/* ×Ô¶¯ÖØÔØÄ¿±ê¼Ä´æÆ÷(Auto-Reload Register)
|
µ±¼ÆÊýÆ÷¼ÆÊýÖµµÈÓÚARRʱ£¬¼ÆÊýÆ÷»Øµ½³õÖµÖØпªÊ¼ÏòÉϼÆÊý Ïà¹Øº¯Êý */
|
extern void LPTIM_ARR_Write(uint32_t SetValue);
|
extern uint32_t LPTIM_ARR_Read(void);
|
|
/* ͨµÀ4²¶×½Òç³öÖжÏʹÄÜ(Channel 4 Over-Capture Interrupt Enable)
|
1£ºÔÊÐíÖжÏ
|
0£º½ûÖ¹ÖÐ¶Ï Ïà¹Øº¯Êý */
|
extern void LPTIM_IER_OVR4IE_Setable(FunState NewState);
|
extern FunState LPTIM_IER_OVR4IE_Getable(void);
|
|
/* ͨµÀ3²¶×½Òç³öÖжÏʹÄÜ(Channel 3 Over-Capture Interrupt Enable)
|
1£ºÔÊÐíÖжÏ
|
0£º½ûÖ¹ÖÐ¶Ï Ïà¹Øº¯Êý */
|
extern void LPTIM_IER_OVR3IE_Setable(FunState NewState);
|
extern FunState LPTIM_IER_OVR3IE_Getable(void);
|
|
/* ͨµÀ2²¶×½Òç³öÖжÏʹÄÜ(Channel 2 Over-Capture Interrupt Enable)
|
1£ºÔÊÐíÖжÏ
|
0£º½ûÖ¹ÖÐ¶Ï Ïà¹Øº¯Êý */
|
extern void LPTIM_IER_OVR2IE_Setable(FunState NewState);
|
extern FunState LPTIM_IER_OVR2IE_Getable(void);
|
|
/* ͨµÀ1²¶×½Òç³öÖжÏʹÄÜ(Channel 1 Over-Capture Interrupt Enable)
|
1£ºÔÊÐíÖжÏ
|
0£º½ûÖ¹ÖÐ¶Ï Ïà¹Øº¯Êý */
|
extern void LPTIM_IER_OVR1IE_Setable(FunState NewState);
|
extern FunState LPTIM_IER_OVR1IE_Getable(void);
|
|
/* Íⲿ´¥·¢µ½À´ÖжÏʹÄÜλ(External Trigger Interrupt Enable)
|
1£ºÍⲿ´¥·¢µ½À´ÖжÏʹÄÜ
|
0£ºÍⲿ´¥·¢µ½À´ÖжϽûÖ¹ Ïà¹Øº¯Êý */
|
extern void LPTIM_IER_TRIGIE_Setable(FunState NewState);
|
extern FunState LPTIM_IER_TRIGIE_Getable(void);
|
|
/* ¼ÆÊýÆ÷Òç³öÖжÏʹÄÜλ(Counter Over-Flow Interrupt Enable)
|
1£º¼ÆÊýÆ÷Òç³öÖжÏʹÄÜ
|
0£º¼ÆÊýÆ÷Òç³öÖжϽûÖ¹ Ïà¹Øº¯Êý */
|
extern void LPTIM_IER_OVIE_Setable(FunState NewState);
|
extern FunState LPTIM_IER_OVIE_Getable(void);
|
|
/* ²¶×½/±È½ÏͨµÀ4ÖжÏʹÄÜλ(Capture/Compare channel 4 Interrupt Enable)
|
1£º²¶×½/±È½ÏͨµÀ2ÖжÏʹÄÜ
|
0£º²¶×½/±È½ÏͨµÀ2ÖжϽûÖ¹ Ïà¹Øº¯Êý */
|
extern void LPTIM_IER_CC4IE_Setable(FunState NewState);
|
extern FunState LPTIM_IER_CC4IE_Getable(void);
|
|
/* ²¶×½/±È½ÏͨµÀ3ÖжÏʹÄÜλ(Capture/Compare channel 3 Interrupt Enable)
|
1£º²¶×½/±È½ÏͨµÀ1ÖжÏʹÄÜ
|
0£º²¶×½/±È½ÏͨµÀ1ÖжϽûÖ¹ Ïà¹Øº¯Êý */
|
extern void LPTIM_IER_CC3IE_Setable(FunState NewState);
|
extern FunState LPTIM_IER_CC3IE_Getable(void);
|
|
/* ²¶×½/±È½ÏͨµÀ2ÖжÏʹÄÜλ(Capture/Compare channel 2 Interrupt Enable)
|
1£º²¶×½/±È½ÏͨµÀ2ÖжÏʹÄÜ
|
0£º²¶×½/±È½ÏͨµÀ2ÖжϽûÖ¹ Ïà¹Øº¯Êý */
|
extern void LPTIM_IER_CC2IE_Setable(FunState NewState);
|
extern FunState LPTIM_IER_CC2IE_Getable(void);
|
|
/* ²¶×½/±È½ÏͨµÀ1ÖжÏʹÄÜλ(Capture/Compare channel 1 Interrupt Enable)
|
1£º²¶×½/±È½ÏͨµÀ1ÖжÏʹÄÜ
|
0£º²¶×½/±È½ÏͨµÀ1ÖжϽûÖ¹ Ïà¹Øº¯Êý */
|
extern void LPTIM_IER_CC1IE_Setable(FunState NewState);
|
extern FunState LPTIM_IER_CC1IE_Getable(void);
|
extern void LPTIM_ISR_CAP4OVR_Clr(void);
|
extern FlagStatus LPTIM_ISR_CAP4OVR_Chk(void);
|
extern void LPTIM_ISR_CAP3OVR_Clr(void);
|
extern FlagStatus LPTIM_ISR_CAP3OVR_Chk(void);
|
extern void LPTIM_ISR_CAP2OVR_Clr(void);
|
extern FlagStatus LPTIM_ISR_CAP2OVR_Chk(void);
|
extern void LPTIM_ISR_CAP1OVR_Clr(void);
|
extern FlagStatus LPTIM_ISR_CAP1OVR_Chk(void);
|
extern void LPTIM_ISR_TRIGIF_Clr(void);
|
extern FlagStatus LPTIM_ISR_TRIGIF_Chk(void);
|
extern void LPTIM_ISR_OVIF_Clr(void);
|
extern FlagStatus LPTIM_ISR_OVIF_Chk(void);
|
extern void LPTIM_ISR_CC4IF_Clr(void);
|
extern FlagStatus LPTIM_ISR_CC4IF_Chk(void);
|
extern void LPTIM_ISR_CC3IF_Clr(void);
|
extern FlagStatus LPTIM_ISR_CC3IF_Chk(void);
|
extern void LPTIM_ISR_CC2IF_Clr(void);
|
extern FlagStatus LPTIM_ISR_CC2IF_Chk(void);
|
extern void LPTIM_ISR_CC1IF_Clr(void);
|
extern FlagStatus LPTIM_ISR_CC1IF_Chk(void);
|
|
|
|
|
/* LPTIMʹÄÜλ(LPTIM Enable)
|
1£ºÊ¹ÄܼÆÊýÆ÷¼ÆÊý
|
0£º½ûÖ¹¼ÆÊýÆ÷¼ÆÊý Ïà¹Øº¯Êý */
|
extern void LPTIM_CR_EN_Setable(FunState NewState);
|
extern FunState LPTIM_CR_EN_Getable(void);
|
|
/* ²¶×½/±È½ÏÖµ¼Ä´æÆ÷1 (Channel1 Capture/Compare Register) Ïà¹Øº¯Êý */
|
extern void LPTIM_CCR1_Write(uint32_t SetValue);
|
extern uint32_t LPTIM_CCR1_Read(void);
|
extern void LPTIM_Deinit(void);
|
|
/* ²¶×½/±È½ÏÖµ¼Ä´æÆ÷2 (Channel2 Capture/Compare Register) Ïà¹Øº¯Êý */
|
extern void LPTIM_CCR2_Write(uint32_t SetValue);
|
extern uint32_t LPTIM_CCR2_Read(void);
|
extern void LPTIM_Deinit(void);
|
|
/* ²¶×½/±È½ÏÖµ¼Ä´æÆ÷3 (Channel3 Capture/Compare Register) Ïà¹Øº¯Êý */
|
extern void LPTIM_CCR3_Write(uint32_t SetValue);
|
extern uint32_t LPTIM_CCR3_Read(void);
|
|
/* ²¶×½/±È½ÏÖµ¼Ä´æÆ÷4 (Channel4 Capture/Compare Register) Ïà¹Øº¯Êý */
|
extern void LPTIM_CCR4_Write(uint32_t SetValue);
|
extern uint32_t LPTIM_CCR4_Read(void);
|
//Announce_End
|
#ifdef __cplusplus
|
}
|
#endif
|
|
#endif /*__FM33A0XXEV_LPTIM_H */
|
