继续完善远传

jinlicong

2024-05-21 a05cacad5239ab3f35ffb58f443356b484e6cc1b

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..\\Drivers\\fm33a0xxev_dma.cComponent: ARM Compiler 5.06 update 7 for Certification (build 960) Tool: armasm [4d35fa]E:\GasFlowmeter\Internet_of_things_valve\SZV103\SZV103_FM33A0xxEV_SiZhu\KEIL_MDKARM__asm___16_fm33a0xxev_dma_c_cab1c678____REV16P9

 




..\\Core\\Include\\core_cminstr.h
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..\\Drivers\\fm33a0xxev_dma.cComponent: ARM Compiler 5.06 update 7 for Certification (build 960) Tool: armasm [4d35fa]E:\GasFlowmeter\Internet_of_things_valve\SZV103\SZV103_FM33A0xxEV_SiZhu\KEIL_MDKARM__asm___16_fm33a0xxev_dma_c_cab1c678____REVSHP9

 




..\\Core\\Include\\core_cminstr.h
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1
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v

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..\Drivers\fm33a0xxev_dma.cComponent: ARM Compiler 5.06 update 7 for Certification (build 960) Tool: ArmCC [4d365d]E:\GasFlowmeter\Internet_of_things_valve\SZV103\SZV103_FM33A0xxEV_SiZhu\KEIL_MDKARM>³
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..\Drivers\fm33a0xxev_dma.cComponent: ARM Compiler 5.06 update 7 for Certification (build 960) Tool: ArmCC [4d365d]E:\GasFlowmeter\Internet_of_things_valve\SZV103\SZV103_FM33A0xxEV_SiZhu\KEIL_MDKARM
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4
..\Drivers\fm33a0xxev_dma.cComponent: ARM Compiler 5.06 update 7 for Certification (build 960) Tool: ArmCC [4d365d]E:\GasFlowmeter\Internet_of_things_valve\SZV103\SZV103_FM33A0xxEV_SiZhu\KEIL_MDKARM>³
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..\Drivers\fm33a0xxev_dma.cComponent: ARM Compiler 5.06 update 7 for Certification (build 960) Tool: ArmCC [4d365d]E:\GasFlowmeter\Internet_of_things_valve\SZV103\SZV103_FM33A0xxEV_SiZhu\KEIL_MDKARM?Ó
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iCHxj
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..\Drivers\fm33a0xxev_dma.cComponent: ARM Compiler 5.06 update 7 for Certification (build 960) Tool: ArmCC [4d365d]E:\GasFlowmeter\Internet_of_things_valve\SZV103\SZV103_FM33A0xxEV_SiZhu\KEIL_MDKARM>È
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..\Drivers\fm33a0xxev_dma.cComponent: ARM Compiler 5.06 update 7 for Certification (build 960) Tool: ArmCC [4d365d]E:\GasFlowmeter\Internet_of_things_valve\SZV103\SZV103_FM33A0xxEV_SiZhu\KEIL_MDKARM?Ñ
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__DATE__ "May 20 2024"
__TIME__ "10:52:04"
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__STDC_ISO_10646__ 200607
__EDG__ 1
__EDG_VERSION__ 407
__EDG_SIZE_TYPE__ unsigned int
__EDG_PTRDIFF_TYPE__ int
__GNUC__ 4
__GNUC_STDC_INLINE__ 1
__GNUC_MINOR__ 7
__GNUC_PATCHLEVEL__ 0
__VERSION__ "4.7 (EDG gcc mode)"
__CHAR16_TYPE__ unsigned short
__CHAR32_TYPE__ unsigned int
__USER_LABEL_PREFIX__ 
__CHAR_UNSIGNED__ 1
__WCHAR_UNSIGNED__ 1
__SIZE_TYPE__ unsigned int
__PTRDIFF_TYPE__ int
__WCHAR_TYPE__ unsigned short
__WINT_TYPE__ unsigned short
__INTMAX_TYPE__ long long
__UINTMAX_TYPE__ unsigned long long
__sizeof_int 4
__sizeof_long 4
__sizeof_ptr 4
__ARMCC_VERSION 5060960
__TARGET_CPU_CORTEX_M0 1
__TARGET_FPU_SOFTVFP 1
__TARGET_FPU_SOFTVFP 1
__MICROLIB 1
__UVISION_VERSION 538
_RTE_ 1
_RTE_ 1
__VTOR_PRESENT 1
__CC_ARM 1
__arm 1
__arm__ 1
__TARGET_ARCH_6S_M 1
__TARGET_ARCH_ARM 0
__TARGET_ARCH_THUMB 3
__TARGET_ARCH_A64 0
__TARGET_ARCH_AARCH32 1
__TARGET_PROFILE_M 1
__TARGET_FEATURE_HALFWORD 1
__TARGET_FEATURE_THUMB 1
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__TARGET_FEATURE_EXTENSION_REGISTER_COUNT 0
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1,
ãDMA_GCR_DMA_ADDRERR_EN_Setable14
ãDMA_GCR_DMA_ADDRERR_EN_Getable($
ãDMA_GCR_DMAEN_Setable((
ãDMA_GCR_DMAEN_Getable)P
ãDMA_CHxCR_CHxTSIZE_Set)D
ãDMA_CHxCR_CHxTSIZE_Get'P
ãDMA_CHxCR_CHxPRI_Set'D
ãDMA_CHxCR_CHxPRI_Get'P
ãDMA_CHxCR_CHxINC_Set'D
ãDMA_CHxCR_CHxINC_Get(P
ãDMA_CHxCR_CHxSSEL_Set(D
ãDMA_CHxCR_CHxSSEL_Get-H
ãDMA_CHxCR_CIRC_UPD_Setable-L
ãDMA_CHxCR_CIRC_UPD_Getable$L
ãDMA_CHxCR_DIR_Set$@
ãDMA_CHxCR_DIR_Get$L
ãDMA_CHxCR_BDW_Set$@
ãDMA_CHxCR_BDW_Get)D
ãDMA_CHxCR_CIRC_Setable)H
ãDMA_CHxCR_CIRC_Getable,D
ãDMA_CHxCR_CHxFTIE_Setable,L
ãDMA_CHxCR_CHxFTIE_Getable,D
ãDMA_CHxCR_CHxHTIE_Setable,L
ãDMA_CHxCR_CHxHTIE_Getable*D
ãDMA_CHxCR_ChxEN_Setable*H
ãDMA_CHxCR_ChxEN_Getable#<
ãDMA_CHxMAR_Write"@
ãDMA_CHxMAR_Read+8
ãDMA_CH11CR_CH11TSIZE_Set+,
ãDMA_CH11CR_CH11TSIZE_Get)4
ãDMA_CH11CR_CH11PRI_Set),
ãDMA_CH11CR_CH11PRI_Get)4
ãDMA_CH11CR_CH11DIR_Set),
ãDMA_CH11CR_CH11DIR_Get(4
ãDMA_CH11CR_CH11RI_Set((
ãDMA_CH11CR_CH11RI_Get(4
ãDMA_CH11CR_CH11FI_Set((
ãDMA_CH11CR_CH11FI_Get.,
ãDMA_CH11CR_CH11FTIE_Setable.0
ãDMA_CH11CR_CH11FTIE_Getable.,
ãDMA_CH11CR_CH11HTIE_Setable.0
ãDMA_CH11CR_CH11HTIE_Getable,(
ãDMA_CH11CR_CH11EN_Setable,0
ãDMA_CH11CR_CH11EN_Getable$ 
ãDMA_CH11FAR_Write#$
ãDMA_CH11FAR_Read$ 
ãDMA_CH11RAR_Write#$
ãDMA_CH11RAR_Read*
ãDMA_ISR_DMA_ADDRERR_Clr*,
ãDMA_ISR_DMA_ADDRERR_Chk&
ãDMA_ISR_DMACHFT_Clr&8
ãDMA_ISR_DMACHFT_Chk&
ãDMA_ISR_DMACHHT_Clr&8
ãDMA_ISR_DMACHHT_Chk.X
ãDMA_CHxCSR_CHxTSIZE_SDW_Set.L
ãDMA_CHxCSR_CHxTSIZE_SDW_Get,T
ãDMA_CHxCSR_CHxINC_SDW_Set,H
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__INT64 __int64
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__PASTE(x,y) __PASTE2(x, y)
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__UINT64_C(x) __ESCAPE__(__PASTE(x ## u, __INT64_C_SUFFIX__))
__LONGLONG long long
#__STDINT_DECLS %__CLIBNS
,__CLIBNS 
sINT8_MIN -128
tINT16_MIN -32768
uINT32_MIN (~0x7fffffff)
vINT64_MIN __INT64_C(~0x7fffffffffffffff)
yINT8_MAX 127
zINT16_MAX 32767
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UINT_LEAST8_MAX 255
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UINT_LEAST16_MAX 65535
•
UINT_LEAST32_MAX 4294967295u
–
UINT_LEAST64_MAX __UINT64_C(18446744073709551615)
›
INT_FAST8_MIN (~0x7fffffff)
œ
INT_FAST16_MIN (~0x7fffffff)

INT_FAST32_MIN (~0x7fffffff)
ž
INT_FAST64_MIN __INT64_C(~0x7fffffffffffffff)
¡
INT_FAST8_MAX 2147483647
¢
INT_FAST16_MAX 2147483647
£
INT_FAST32_MAX 2147483647
¤
INT_FAST64_MAX __INT64_C(9223372036854775807)
§
UINT_FAST8_MAX 4294967295u
¨
UINT_FAST16_MAX 4294967295u
©
UINT_FAST32_MAX 4294967295u
ª
UINT_FAST64_MAX __UINT64_C(18446744073709551615)
²
INTPTR_MIN INT32_MIN
¹
INTPTR_MAX INT32_MAX
À
UINTPTR_MAX UINT32_MAX
Æ
INTMAX_MIN __ESCAPE__(~0x7fffffffffffffffll)
É
INTMAX_MAX __ESCAPE__(9223372036854775807ll)
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UINTMAX_MAX __ESCAPE__(18446744073709551615ull)
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PTRDIFF_MIN INT32_MIN
Ö
PTRDIFF_MAX INT32_MAX
Ú
SIG_ATOMIC_MIN (~0x7fffffff)
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SIG_ATOMIC_MAX 2147483647
á
SIZE_MAX UINT32_MAXç
WCHAR_MINè
WCHAR_MAX
î
WCHAR_MIN 0
ï
WCHAR_MAX 65535
ó
WINT_MIN (~0x7fffffff)
ô
WINT_MAX 2147483647
û
INT8_C(x) (x)
ü
INT16_C(x) (x)
ý
INT32_C(x) (x)
þ
INT64_C(x) __INT64_C(x)
€UINT8_C(x) (x ## u)
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‡UINTMAX_C(x) __ESCAPE__(x ## ull)²__INT64³__LONGLONGXO
 




D:\Program Files\MDK5\ARM\ARMCC\Bin\..\include\stdint.h


tD:\Program Files\MDK5\ARM\ARMCC\Bin\..\include\stdint.hComponent: ARM Compiler 5.06 update 7 for Certification (build 960) Tool: ArmCC [4d365d]
signed charshortintlong long
unsigned charunsigned shortunsigned intunsigned long longPint8_t§
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9 Pint32_t¿
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@ Puint64_t

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'__CORE_CMINSTR_H 
<__NOP __nop
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L__WFE __wfe
S__SEV __sev
\__ISB() do { __schedule_barrier(); __isb(0xF); __schedule_barrier(); } while (0)
g__DSB() do { __schedule_barrier(); __dsb(0xF); __schedule_barrier(); } while (0)
r__DMB() do { __schedule_barrier(); __dmb(0xF); __schedule_barrier(); } while (0)
__REV __rev
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__ROR __ror
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__BKPT(value) __breakpoint(value)
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__CLZ __clz@6
 




..\Core\Include\core_cminstr.h


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..\Core\Include\core_cminstr.hComponent: ARM Compiler 5.06 update 7 for Certification (build 960) Tool: ArmCC [4d365d]E:\GasFlowmeter\Internet_of_things_valve\SZV103\SZV103_FM33A0xxEV_SiZhu\KEIL_MDKARM;¨
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'__CORE_CMFUNC_H @5
 




..\Core\Include\core_cmfunc.h


 
..\Core\Include\core_cmfunc.hComponent: ARM Compiler 5.06 update 7 for Certification (build 960) Tool: ArmCC [4d365d]E:\GasFlowmeter\Internet_of_things_valve\SZV103\SZV103_FM33A0xxEV_SiZhu\KEIL_MDKARM;¡
@__get_CONTROLv
a__resultv

Y__regControlv

P<Ú
M__set_CONTROL$v
controlY__regControlv

P;”
Z__get_IPSRv
a__resultv

Y__regIPSRv

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g__get_APSRv
a__resultv

Y__regAPSRv

P;ˆ
t__get_xPSRv
a__resultv

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P;Ñ
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__get_PSPv
a__resultv

Y__regProcessStackPointerv

P<š
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__set_PSP$v
topOfProcStackY__regProcessStackPointerv

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a__resultv

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topOfMainStackY__regMainStackPointerv

P;ç
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 __CORE_CM0PLUS_H_GENERIC "
@__CM0PLUS_CMSIS_VERSION_MAIN ( 5U)
A__CM0PLUS_CMSIS_VERSION_SUB ( 0U)
B__CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | __CM0PLUS_CMSIS_VERSION_SUB )
E__CORTEX_M (0U)
Q__ASM __asm
R__INLINE __inline
S__STATIC_INLINE static __inline
T__NO_RETURN __declspec(noreturn)
U__USED __attribute__((used))
V__WEAK __attribute__((weak))
W__UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
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__FPU_USED 0UÆ
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__CORE_CM0PLUS_H_DEPENDANT 
ÿ
__I volatile const
__O volatile
‚__IO volatile
…__IM volatile const
†__OM volatile
‡__IOM volatile
³APSR_N_Pos 31U
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¶APSR_Z_Pos 30U
·APSR_Z_Msk (1UL << APSR_Z_Pos)
¹APSR_C_Pos 29U
ºAPSR_C_Msk (1UL << APSR_C_Pos)
¼APSR_V_Pos 28U
½APSR_V_Msk (1UL << APSR_V_Pos)
ÎIPSR_ISR_Pos 0U
ÏIPSR_ISR_Msk (0x1FFUL )
æxPSR_N_Pos 31U
çxPSR_N_Msk (1UL << xPSR_N_Pos)
éxPSR_Z_Pos 30U
êxPSR_Z_Msk (1UL << xPSR_Z_Pos)
ìxPSR_C_Pos 29U
íxPSR_C_Msk (1UL << xPSR_C_Pos)
ïxPSR_V_Pos 28U
ðxPSR_V_Msk (1UL << xPSR_V_Pos)
òxPSR_T_Pos 24U
óxPSR_T_Msk (1UL << xPSR_T_Pos)
õxPSR_ISR_Pos 0U
öxPSR_ISR_Msk (0x1FFUL )
ˆCONTROL_SPSEL_Pos 1U
‰CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)
‹CONTROL_nPRIV_Pos 0U
ŒCONTROL_nPRIV_Msk (1UL )
ÈSCB_CPUID_IMPLEMENTER_Pos 24U
ÉSCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
ËSCB_CPUID_VARIANT_Pos 20U
ÌSCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
ÎSCB_CPUID_ARCHITECTURE_Pos 16U
ÏSCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
ÑSCB_CPUID_PARTNO_Pos 4U
ÒSCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
ÔSCB_CPUID_REVISION_Pos 0U
ÕSCB_CPUID_REVISION_Msk (0xFUL )
ØSCB_ICSR_NMIPENDSET_Pos 31U
ÙSCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)
ÛSCB_ICSR_PENDSVSET_Pos 28U
ÜSCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
ÞSCB_ICSR_PENDSVCLR_Pos 27U
ßSCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
áSCB_ICSR_PENDSTSET_Pos 26U
âSCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
äSCB_ICSR_PENDSTCLR_Pos 25U
åSCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
çSCB_ICSR_ISRPREEMPT_Pos 23U
èSCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
êSCB_ICSR_ISRPENDING_Pos 22U
ëSCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
íSCB_ICSR_VECTPENDING_Pos 12U
îSCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
ðSCB_ICSR_VECTACTIVE_Pos 0U
ñSCB_ICSR_VECTACTIVE_Msk (0x1FFUL )
õSCB_VTOR_TBLOFF_Pos 8U
öSCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)
úSCB_AIRCR_VECTKEY_Pos 16U
ûSCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
ýSCB_AIRCR_VECTKEYSTAT_Pos 16U
þSCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
€SCB_AIRCR_ENDIANESS_Pos 15U
SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
ƒSCB_AIRCR_SYSRESETREQ_Pos 2U
„SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
†SCB_AIRCR_VECTCLRACTIVE_Pos 1U
‡SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
ŠSCB_SCR_SEVONPEND_Pos 4U
‹SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
SCB_SCR_SLEEPDEEP_Pos 2U
ŽSCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
SCB_SCR_SLEEPONEXIT_Pos 1U
‘SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
”SCB_CCR_STKALIGN_Pos 9U
•SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)
—SCB_CCR_UNALIGN_TRP_Pos 3U
˜SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
›SCB_SHCSR_SVCALLPENDED_Pos 15U
œSCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
´SysTick_CTRL_COUNTFLAG_Pos 16U
µSysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
·SysTick_CTRL_CLKSOURCE_Pos 2U
¸SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
ºSysTick_CTRL_TICKINT_Pos 1U
»SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
½SysTick_CTRL_ENABLE_Pos 0U
¾SysTick_CTRL_ENABLE_Msk (1UL )
ÁSysTick_LOAD_RELOAD_Pos 0U
ÂSysTick_LOAD_RELOAD_Msk (0xFFFFFFUL )
ÅSysTick_VAL_CURRENT_Pos 0U
ÆSysTick_VAL_CURRENT_Msk (0xFFFFFFUL )
ÉSysTick_CALIB_NOREF_Pos 31U
ÊSysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)
ÌSysTick_CALIB_SKEW_Pos 30U
ÍSysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)
ÏSysTick_CALIB_TENMS_Pos 0U
ÐSysTick_CALIB_TENMS_Msk (0xFFFFFFUL )
éMPU_TYPE_IREGION_Pos 16U
êMPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
ìMPU_TYPE_DREGION_Pos 8U
íMPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
ïMPU_TYPE_SEPARATE_Pos 0U
ðMPU_TYPE_SEPARATE_Msk (1UL )
óMPU_CTRL_PRIVDEFENA_Pos 2U
ôMPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
öMPU_CTRL_HFNMIENA_Pos 1U
÷MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
ùMPU_CTRL_ENABLE_Pos 0U
úMPU_CTRL_ENABLE_Msk (1UL )
ýMPU_RNR_REGION_Pos 0U
þMPU_RNR_REGION_Msk (0xFFUL )
MPU_RBAR_ADDR_Pos 8U
‚MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)
„MPU_RBAR_VALID_Pos 4U
…MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos)
‡MPU_RBAR_REGION_Pos 0U
ˆMPU_RBAR_REGION_Msk (0xFUL )
‹MPU_RASR_ATTRS_Pos 16U
ŒMPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos)
ŽMPU_RASR_XN_Pos 28U
MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos)
‘MPU_RASR_AP_Pos 24U
’MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos)
”MPU_RASR_TEX_Pos 19U
•MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos)
—MPU_RASR_S_Pos 18U
˜MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos)
šMPU_RASR_C_Pos 17U
›MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos)
MPU_RASR_B_Pos 16U
žMPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos)
 MPU_RASR_SRD_Pos 8U
¡MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos)
£MPU_RASR_SIZE_Pos 1U
¤MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos)
¦MPU_RASR_ENABLE_Pos 0U
§MPU_RASR_ENABLE_Msk (1UL )
Ä_VAL2FLD(field,value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
Ì_FLD2VAL(field,value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
ÙSCS_BASE (0xE000E000UL)
ÚSysTick_BASE (SCS_BASE + 0x0010UL)
ÛNVIC_BASE (SCS_BASE + 0x0100UL)
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ßSysTick ((SysTick_Type *) SysTick_BASE )
àNVIC ((NVIC_Type *) NVIC_BASE )
ãMPU_BASE (SCS_BASE + 0x0D90UL)
äMPU ((MPU_Type *) MPU_BASE )
‚_BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
ƒ_SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
„_IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) •
 




..\Core\Include\D:\Program Files\MDK5\ARM\ARMCC\Bin\..\include\core_cm0plus.h
stdint.hcore_cminstr.h
core_cmfunc.h


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..\Core\Include\core_cm0plus.hComponent: ARM Compiler 5.06 update 7 for Certification (build 960) Tool: ArmCC [4d365d]E:\GasFlowmeter\Internet_of_things_valve\SZV103\SZV103_FM33A0xxEV_SiZhu\KEIL_MDKARM*¶!_reserved0v
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__stdio_h 
__ARMCLIB_VERSION 5060044
"_ARMABI __declspec(__nothrow)
%__STDIO_DECLS '__CLIBNS
-__CLIBNS <NULL
=NULL 0
g_SYS_OPEN 16
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stdin (&__CLIBNS __stdin)
§
stdout (&__CLIBNS __stdout)
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¬
_IOFBF 0x100
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_IOLBF 0x200
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±
BUFSIZ (512)
³
FOPEN_MAX _SYS_OPEN
¹
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¾
L_tmpnam FILENAME_MAX
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Ò
SEEK_SET 0
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Ú
_IOBIN 0x04
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__STDIN_BUFSIZ (64)
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¿getchar() getc(stdin)
àputchar(c) putc(c, stdout)XN
 




D:\Program Files\MDK5\ARM\ARMCC\Bin\..\include\stdio.h


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D:\Program Files\MDK5\ARM\ARMCC\Bin\..\include\stdio.hComponent: ARM Compiler 5.06 update 7 for Certification (build 960) Tool: ArmCC [4d365d]unsigned intunsigned long longPsize_t¦
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$FM33A0XXEV_H 
.__RCHF_INITIAL_CLOCK (8000000)
/__RCMF_CLOCK (2000000)
0__RCLP_CLOCK (32000)
1__XTLF_CLOCK (32768)
n__CM0_REV 0x0100
o__MPU_PRESENT 1
p__VTOR_PRESENT 1
q__NVIC_PRIO_BITS 2
r__Vendor_SysTickConfig 0uv
¿FLASH_BASE (( uint32_t)0x00000000)
ÀSRAM_BASE (( uint32_t)0x20000000)
ÁPERIPH_BASE (( uint32_t)0x40000000)
ÊPMU_BASE (PERIPH_BASE +0x00002000)
ËDBG_BASE (PERIPH_BASE +0x00000000)
ÌFLS_BASE (PERIPH_BASE +0x00001000)
ÍRMU_BASE (PERIPH_BASE +0x00002800)
ÎIWDT_BASE (PERIPH_BASE +0x00011400)
ÏWWDT_BASE (PERIPH_BASE +0x00011800)
ÐCMU_BASE (PERIPH_BASE +0x00002400)
ÑCDIF_BASE (PERIPH_BASE +0x0001E000)
ÒVRTC_BASE (PERIPH_BASE +0x0001F800)
ÓSVD_BASE (PERIPH_BASE +0x00012800)
ÔAES_BASE (PERIPH_BASE +0x00013800)
ÕPAE_BASE (PERIPH_BASE +0x00001400)
ÖHASH_BASE (PERIPH_BASE +0x00001800)
×RNG_BASE (PERIPH_BASE +0x00013C00)
ØCOMP_BASE (PERIPH_BASE +0x00015400)
ÙI2C0_BASE (PERIPH_BASE +0x00012400)
ÚI2C1_BASE (PERIPH_BASE +0x00015000)
ÛUARTIR_BASE (PERIPH_BASE +0x00017C00)
ÜUART0_BASE (PERIPH_BASE +0x00012000)
ÝUART1_BASE (PERIPH_BASE +0x00016800)
ÞUART2_BASE (PERIPH_BASE +0x00016C00)
ßUART3_BASE (PERIPH_BASE +0x00017000)
àUART4_BASE (PERIPH_BASE +0x00017400)
áUART5_BASE (PERIPH_BASE +0x00017800)
âLPUART0_BASE (PERIPH_BASE +0x00014000)
ãLPUART1_BASE (PERIPH_BASE +0x00014400)
äSPI0_BASE (PERIPH_BASE +0x00010400)
åSPI1_BASE (PERIPH_BASE +0x00010800)
æSPI2_BASE (PERIPH_BASE +0x00014800)
çSPI3_BASE (PERIPH_BASE +0x00014C00)
èSPI4_BASE (PERIPH_BASE +0x00016400)
éU7816_BASE (PERIPH_BASE +0x00011C00)
êQSPI_BASE (PERIPH_BASE +0x00000800)
ëDMA_BASE (PERIPH_BASE +0x00000400)
ìCRC_BASE (PERIPH_BASE +0x00010000)
íBT1_BASE (PERIPH_BASE +0x00013000)
îBT2_BASE (PERIPH_BASE +0x00013044)
ïET1_BASE (PERIPH_BASE +0x00013090)
ðET2_BASE (PERIPH_BASE +0x000130B0)
ñET3_BASE (PERIPH_BASE +0x000130D0)
òET4_BASE (PERIPH_BASE +0x000130F0)
óETCNT_BASE (PERIPH_BASE +0x00013110)
ôBSTIM_BASE (PERIPH_BASE +0x00016000)
õLPTIM_BASE (PERIPH_BASE +0x00013400)
öRTC_BASE (PERIPH_BASE +0x00011000)
÷LCD_BASE (PERIPH_BASE +0x00010C00)
øADC_BASE (PERIPH_BASE +0x0001FA00)
ùCIC_BASE (PERIPH_BASE +0x00015C00)
úGPIOA_BASE (PERIPH_BASE +0x00000C00)
ûGPIOB_BASE (PERIPH_BASE +0x00000C40)
üGPIOC_BASE (PERIPH_BASE +0x00000C80)
ýGPIOD_BASE (PERIPH_BASE +0x00000CC0)
þGPIOE_BASE (PERIPH_BASE +0x00000D00)
ÿGPIOF_BASE (PERIPH_BASE +0x00000D40)
€GPIOG_BASE (PERIPH_BASE +0x00000D80)
GPIOH_BASE (PERIPH_BASE +0x0001FC00)
‚GPIO_BASE (PERIPH_BASE +0x00000DC0)
ˆPMU ((PMU_Type *) PMU_BASE )
‰DBG ((DBG_Type *) DBG_BASE )
ŠFLS ((FLS_Type *) FLS_BASE )
‹RMU ((RMU_Type *) RMU_BASE )
ŒIWDT ((IWDT_Type *) IWDT_BASE )
WWDT ((WWDT_Type *) WWDT_BASE )
ŽCMU ((CMU_Type *) CMU_BASE )
CDIF ((CDIF_Type *) CDIF_BASE )
VRTC ((VRTC_Type *) VRTC_BASE )
‘SVD ((SVD_Type *) SVD_BASE )
’AES ((AES_Type *) AES_BASE )
“PAE ((PAE_Type *) PAE_BASE )
”HASH ((HASH_Type *) HASH_BASE )
•RNG ((RNG_Type *) RNG_BASE )
–COMP ((COMP_Type *) COMP_BASE )
—I2C0 ((I2C_Type *) I2C0_BASE )
˜I2C1 ((I2C_Type *) I2C1_BASE )
™UARTIR ((UARTIR_Type *) UARTIR_BASE )
šUART0 ((UART_Type *) UART0_BASE )
›UART1 ((UART_Type *) UART1_BASE )
œUART2 ((UART_Type *) UART2_BASE )
UART3 ((UART_Type *) UART3_BASE )
žUART4 ((UART_Type *) UART4_BASE )
ŸUART5 ((UART_Type *) UART5_BASE )
 LPUART0 ((LPUART_Type *) LPUART0_BASE )
¡LPUART1 ((LPUART_Type *) LPUART1_BASE )
¢SPI0 ((SPI_Type *) SPI0_BASE )
£SPI1 ((SPI_Type *) SPI1_BASE )
¤SPI2 ((SPI_Type *) SPI2_BASE )
¥SPI3 ((SPI_Type *) SPI3_BASE )
¦SPI4 ((SPI_Type *) SPI4_BASE )
§U7816 ((U7816_Type *) U7816_BASE )
¨QSPI ((QSPI_Type *) QSPI_BASE )
©DMA ((DMA_Type *) DMA_BASE )
ªCRC ((CRC_Type *) CRC_BASE )
«BT1 ((BT_Type *) BT1_BASE )
¬BT2 ((BT_Type *) BT2_BASE )
­ET1 ((ET_Type *) ET1_BASE )
®ET2 ((ET_Type *) ET2_BASE )
¯ET3 ((ET_Type *) ET3_BASE )
°ET4 ((ET_Type *) ET4_BASE )
±ETCNT ((ETCNT_Type *) ETCNT_BASE )
²BSTIM ((BSTIM_Type *) BSTIM_BASE )
³LPTIM ((LPTIM_Type *) LPTIM_BASE )
´RTC ((RTC_Type *) RTC_BASE )
µLCD ((LCD_Type *) LCD_BASE )
¶ADC ((ADC_Type *) ADC_BASE )
·CIC ((CIC_Type *) CIC_BASE )
¸GPIOA ((GPIO_Type *) GPIOA_BASE )
¹GPIOB ((GPIO_Type *) GPIOB_BASE )
ºGPIOC ((GPIO_Type *) GPIOC_BASE )
»GPIOD ((GPIO_Type *) GPIOD_BASE )
¼GPIOE ((GPIO_Type *) GPIOE_BASE )
½GPIOF ((GPIO_Type *) GPIOF_BASE )
¾GPIOG ((GPIO_Type *) GPIOG_BASE )
¿GPIOH ((GPIOH_Type *) GPIOH_BASE )
ÀGPIO ((GPIO_COMMON_Type *) GPIO_BASE )h]
 




..\Core\Include\FM33A0XXEV.h
core_cm0plus.h
system_FM33A0XXEV.h


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Reset_IRQnqNMI_IRQnrHardFault_IRQnsSVC_IRQn{PendSV_IRQn~SysTick_IRQnWWDT_IRQnSVD_IRQn
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UART2_IRQnUART3_IRQnUART4_IRQn UART5_IRQnU7816_IRQnLPUART0_IRQnI2Cx_IRQnRSV_IRQnCRYPTO_IRQnLPTIM_IRQnDMA_IRQnWKUPx_IRQnCOMP_IRQnBTx_IRQnQSPI_IRQnETx_IRQnBSTIM_IRQnSPI3_IRQnSPI4_IRQnGPIO_IRQnLPUART1_IRQnPIRQn_Typei

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RSV1#RCMFCR˜#RCLPCR˜#RCLPTR˜#XTLFCR˜# ADCCR˜#$LFDIER˜#(LFDISR˜#,PVRTC_Typeï
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Ê*À CSR˜#MLR˜#MPR˜#M0CFG˜#M1CFG˜#M2CFG˜#M3CFG˜#WORD˜#PPAE_TypeÚ
Û*ìCSR˜#DTR˜#PHASH_TypeQ    
æ*â CR˜#DORª# ˜

RSV1—    #SR˜#CRC_CR˜#CRC_DIR˜#CRC_SR˜#PRNG_Type~    
ö*¯CR1˜#CR2˜#ICR˜#ISR˜#PCR˜#PCOMP_Typeó    
„*ª$CFGR˜#CR˜#IER˜#ISR˜#SR˜#BRG˜#BUF˜#TIMING˜#TO˜# PI2C_TypeA

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 *µCSR˜#IER˜#ISR˜#TODR˜#RXBUFª#TXBUF˜#BGR˜#PUART_TypeÞ

°*CSR˜#IER˜#ISR˜#BMR˜#RXBUF˜#TXBUF˜#DMR˜#PLPUART_TypeG
À*‡CR1˜#CR2˜#CR3˜#IER˜#ISR˜#TXBUF˜#RXBUFª#PSPI_Type±
Ð*„$CR˜#FFR˜#EGTR˜#PSC˜#BGR˜#RXBUFª#TXBUF˜#IER˜#ISR˜# PU7816_Type
â*¤0CR˜#CFG˜#SR˜#DATALEN˜#CCR˜#ADDR˜#ABR˜#DR˜#SMSK˜# SMAT˜#$PITV˜#(TO˜#,PQSPI_Type—
÷*—¸GCR˜#CH0CR˜#CH0MAR˜#CH1CR˜#CH1MAR˜#CH2CR˜#CH2MAR˜#CH3CR˜#CH3MAR˜# CH4CR˜#$CH4MAR˜#(CH5CR˜#,CH5MAR˜#0CH6CR˜#4CH6MAR˜#8CH7CR˜#<CH7MAR˜#@CH8CR˜#DCH8MAR˜#HCH9CR˜#LCH9MAR˜#PCH10CR˜#TCH10MAR˜#XCH11CR˜#\CH11FAR˜#`CH11RAR˜#dISR˜#h±˜
$RSV1¨#lCH0CSR˜#€CH0MASR˜#„CH1CSR˜#ˆCH1MASR˜#ŒCH2CSR˜#CH2MASR˜#”CH3CSR˜#˜CH3MASR˜#œCH4CSR˜# CH4MASR˜#¤CH5CSR˜#¨CH5MASR˜#¬CH6CSR˜#°CH6MASR˜#´PDMA_Type6 
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ä*—#CNT1˜#CNT2˜#CNT3˜#CNT4˜#PETCNT_Typeb
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RSV3#LCOMEN˜#PSEGEN0˜#TSEGEN1˜#XBSTCR˜#\PLCD_Type+
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(SYSTEM_FM33A0XXEV_H 234
O__SYSTEM_CLOCK (8000000)
PDELAY_US (__SYSTEM_CLOCK/1000000)
QDELAY_MS (__SYSTEM_CLOCK/1000)
TDo_DelayStart() { uint32_t LastTick = SysTick->VAL; do {
WWhile_DelayMsEnd(Count) }while(((LastTick - SysTick->VAL)&0xFFFFFF)<DELAY_MS*Count); }
ZWhile_DelayUsEnd(Count) }while(((LastTick - SysTick->VAL)&0xFFFFFF)<DELAY_US*Count); }œ’
 




..\Core\Include\D:\Program Files\MDK5\ARM\ARMCC\Bin\..\include\system_FM33A0XXEV.h
stdint.hstdio.hFM33A0XXEV.h




..\Core\Include\system_FM33A0XXEV.hComponent: ARM Compiler 5.06 update 7 for Certification (build 960) Tool: ArmCC [4d365d]E:\GasFlowmeter\Internet_of_things_valve\SZV103\SZV103_FM33A0xxEV_SiZhu\KEIL_MDKARMqSystemCoreClockv


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__FM33A0XXEV_DMA_H 
2DMA_GCR_DMA_ADDRERR_EN_Pos 1
5DMA_GCR_DMA_ADDRERR_EN_Msk (0x1U << DMA_GCR_DMA_ADDRERR_EN_Pos)
7DMA_GCR_DMAEN_Pos 0
:DMA_GCR_DMAEN_Msk (0x1U << DMA_GCR_DMAEN_Pos)
<DMA_CHxCR_CHxTSIZE_Pos 16
=DMA_CHxCR_CHxTSIZE_Msk (0x1fffU << DMA_CHxCR_CHxTSIZE_Pos)
?DMA_CHxCR_CHxPRI_Pos 12
DDMA_CHxCR_CHxPRI_Msk (0x3U << DMA_CHxCR_CHxPRI_Pos)
EDMA_CHxCR_CHxPRI_LOW (0x0U << DMA_CHxCR_CHxPRI_Pos)
FDMA_CHxCR_CHxPRI_MEDIUM (0x1U << DMA_CHxCR_CHxPRI_Pos)
GDMA_CHxCR_CHxPRI_HIGH (0x2U << DMA_CHxCR_CHxPRI_Pos)
HDMA_CHxCR_CHxPRI_VERY_HIGH (0x3U << DMA_CHxCR_CHxPRI_Pos)
JDMA_CHxCR_CHxINC_Pos 11
MDMA_CHxCR_CHxINC_Msk (0x1U << DMA_CHxCR_CHxINC_Pos)
NDMA_CHxCR_CHxINC_INCREASE (0x1U << DMA_CHxCR_CHxINC_Pos)
ODMA_CHxCR_CHxINC_DECREASE (0x0U << DMA_CHxCR_CHxINC_Pos)
QDMA_CHxCR_CHxSSEL_Pos 8
SDMA_CHxCR_CHxSSEL_Msk (0x7U << DMA_CHxCR_CHxSSEL_Pos)
UDMA_CHxCR_CH0SSEL_ADC (0x0U << DMA_CHxCR_CHxSSEL_Pos)
VDMA_CHxCR_CH0SSEL_SPI3_RX (0x1U << DMA_CHxCR_CHxSSEL_Pos)
WDMA_CHxCR_CH0SSEL_LPUART0_RX (0x2U << DMA_CHxCR_CHxSSEL_Pos)
XDMA_CHxCR_CH0SSEL_LPUART1_RX (0x3U << DMA_CHxCR_CHxSSEL_Pos)
YDMA_CHxCR_CH0SSEL_UART2_RX (0x4U << DMA_CHxCR_CHxSSEL_Pos)
ZDMA_CHxCR_CH0SSEL_UART4_RX (0x5U << DMA_CHxCR_CHxSSEL_Pos)
[DMA_CHxCR_CH0SSEL_AES_IN (0x6U << DMA_CHxCR_CHxSSEL_Pos)
\DMA_CHxCR_CH0SSEL_QSPI (0x7U << DMA_CHxCR_CHxSSEL_Pos)
^DMA_CHxCR_CH1SSEL_ADC (0x0U << DMA_CHxCR_CHxSSEL_Pos)
_DMA_CHxCR_CH1SSEL_SPI0_RX (0x1U << DMA_CHxCR_CHxSSEL_Pos)
`DMA_CHxCR_CH1SSEL_SPI2_RX (0x2U << DMA_CHxCR_CHxSSEL_Pos)
aDMA_CHxCR_CH1SSEL_SPI3_TX (0x3U << DMA_CHxCR_CHxSSEL_Pos)
bDMA_CHxCR_CH1SSEL_UART0_RX (0x4U << DMA_CHxCR_CHxSSEL_Pos)
cDMA_CHxCR_CH1SSEL_UART2_TX (0x5U << DMA_CHxCR_CHxSSEL_Pos)
dDMA_CHxCR_CH1SSEL_UART3_RX (0x6U << DMA_CHxCR_CHxSSEL_Pos)
eDMA_CHxCR_CH1SSEL_U7816_RX (0x7U << DMA_CHxCR_CHxSSEL_Pos)
gDMA_CHxCR_CH2SSEL_SPI0_TX (0x0U << DMA_CHxCR_CHxSSEL_Pos)
hDMA_CHxCR_CH2SSEL_SPI2_TX (0x1U << DMA_CHxCR_CHxSSEL_Pos)
iDMA_CHxCR_CH2SSEL_SPI4_RX (0x2U << DMA_CHxCR_CHxSSEL_Pos)
jDMA_CHxCR_CH2SSEL_UART0_TX (0x3U << DMA_CHxCR_CHxSSEL_Pos)
kDMA_CHxCR_CH2SSEL_UART3_TX (0x4U << DMA_CHxCR_CHxSSEL_Pos)
lDMA_CHxCR_CH2SSEL_UART5_RX (0x5U << DMA_CHxCR_CHxSSEL_Pos)
mDMA_CHxCR_CH2SSEL_U7816_TX (0x6U << DMA_CHxCR_CHxSSEL_Pos)
nDMA_CHxCR_CH2SSEL_AES_OUT (0x7U << DMA_CHxCR_CHxSSEL_Pos)
pDMA_CHxCR_CH3SSEL_SPI1_RX (0x0U << DMA_CHxCR_CHxSSEL_Pos)
qDMA_CHxCR_CH3SSEL_SPI4_TX (0x1U << DMA_CHxCR_CHxSSEL_Pos)
rDMA_CHxCR_CH3SSEL_LPUART0_RX (0x2U << DMA_CHxCR_CHxSSEL_Pos)
sDMA_CHxCR_CH3SSEL_UART1_RX (0x3U << DMA_CHxCR_CHxSSEL_Pos)
tDMA_CHxCR_CH3SSEL_UART4_RX (0x4U << DMA_CHxCR_CHxSSEL_Pos)
uDMA_CHxCR_CH3SSEL_UART5_TX (0x5U << DMA_CHxCR_CHxSSEL_Pos)
vDMA_CHxCR_CH3SSEL_I2C0_TX (0x6U << DMA_CHxCR_CHxSSEL_Pos)
wDMA_CHxCR_CH3SSEL_AES_IN (0x7U << DMA_CHxCR_CHxSSEL_Pos)
yDMA_CHxCR_CH4SSEL_SPI1_TX (0x0U << DMA_CHxCR_CHxSSEL_Pos)
zDMA_CHxCR_CH4SSEL_SPI3_RX (0x1U << DMA_CHxCR_CHxSSEL_Pos)
{DMA_CHxCR_CH4SSEL_LPUART0_TX (0x2U << DMA_CHxCR_CHxSSEL_Pos)
|DMA_CHxCR_CH4SSEL_UART1_TX (0x3U << DMA_CHxCR_CHxSSEL_Pos)
}DMA_CHxCR_CH4SSEL_UART2_RX (0x4U << DMA_CHxCR_CHxSSEL_Pos)
~DMA_CHxCR_CH4SSEL_UART4_TX (0x5U << DMA_CHxCR_CHxSSEL_Pos)
DMA_CHxCR_CH4SSEL_I2C0_RX (0x6U << DMA_CHxCR_CHxSSEL_Pos)
€
DMA_CHxCR_CH4SSEL_AES_OUT (0x7U << DMA_CHxCR_CHxSSEL_Pos)
‚
DMA_CHxCR_CH5SSEL_SPI0_RX (0x0U << DMA_CHxCR_CHxSSEL_Pos)
ƒ
DMA_CHxCR_CH5SSEL_SPI2_RX (0x1U << DMA_CHxCR_CHxSSEL_Pos)
„
DMA_CHxCR_CH5SSEL_LPUART1_RX (0x2U << DMA_CHxCR_CHxSSEL_Pos)
…
DMA_CHxCR_CH5SSEL_UART1_RX (0x3U << DMA_CHxCR_CHxSSEL_Pos)
†
DMA_CHxCR_CH5SSEL_UART2_TX (0x4U << DMA_CHxCR_CHxSSEL_Pos)
‡
DMA_CHxCR_CH5SSEL_UART3_RX (0x5U << DMA_CHxCR_CHxSSEL_Pos)
ˆ
DMA_CHxCR_CH5SSEL_UART5_RX (0x6U << DMA_CHxCR_CHxSSEL_Pos)
‰
DMA_CHxCR_CH5SSEL_I2C1_TX (0x7U << DMA_CHxCR_CHxSSEL_Pos)
‹
DMA_CHxCR_CH6SSEL_SPI0_TX (0x0U << DMA_CHxCR_CHxSSEL_Pos)
Œ
DMA_CHxCR_CH6SSEL_SPI2_TX (0x1U << DMA_CHxCR_CHxSSEL_Pos)

DMA_CHxCR_CH6SSEL_LPUART1_TX (0x2U << DMA_CHxCR_CHxSSEL_Pos)
Ž
DMA_CHxCR_CH6SSEL_UART1_TX (0x3U << DMA_CHxCR_CHxSSEL_Pos)

DMA_CHxCR_CH6SSEL_UART3_TX (0x4U << DMA_CHxCR_CHxSSEL_Pos)

DMA_CHxCR_CH6SSEL_UART5_TX (0x5U << DMA_CHxCR_CHxSSEL_Pos)
‘
DMA_CHxCR_CH6SSEL_I2C1_RX (0x6U << DMA_CHxCR_CHxSSEL_Pos)
’
DMA_CHxCR_CH6SSEL_CRC (0x7U << DMA_CHxCR_CHxSSEL_Pos)
”
DMA_CHxCR_CH7SSEL_ADC (0x0U << DMA_CHxCR_CHxSSEL_Pos)
•
DMA_CHxCR_CH7SSEL_SPI1_RX (0x1U << DMA_CHxCR_CHxSSEL_Pos)
–
DMA_CHxCR_CH7SSEL_SPI3_RX (0x2U << DMA_CHxCR_CHxSSEL_Pos)
—
DMA_CHxCR_CH7SSEL_LPUART0_RX (0x3U << DMA_CHxCR_CHxSSEL_Pos)
˜
DMA_CHxCR_CH7SSEL_UART0_RX (0x4U << DMA_CHxCR_CHxSSEL_Pos)
™
DMA_CHxCR_CH7SSEL_UART2_RX (0x5U << DMA_CHxCR_CHxSSEL_Pos)
š
DMA_CHxCR_CH7SSEL_UART4_RX (0x6U << DMA_CHxCR_CHxSSEL_Pos)
›
DMA_CHxCR_CH7SSEL_QSPI (0x7U << DMA_CHxCR_CHxSSEL_Pos)

DMA_CHxCR_CH8SSEL_ADC (0x0U << DMA_CHxCR_CHxSSEL_Pos)
ž
DMA_CHxCR_CH8SSEL_SPI1_TX (0x1U << DMA_CHxCR_CHxSSEL_Pos)
Ÿ
DMA_CHxCR_CH8SSEL_SPI2_RX (0x2U << DMA_CHxCR_CHxSSEL_Pos)
 
DMA_CHxCR_CH8SSEL_SPI3_TX (0x3U << DMA_CHxCR_CHxSSEL_Pos)
¡
DMA_CHxCR_CH8SSEL_LPUART0_TX (0x4U << DMA_CHxCR_CHxSSEL_Pos)
¢
DMA_CHxCR_CH8SSEL_UART0_TX (0x5U << DMA_CHxCR_CHxSSEL_Pos)
£
DMA_CHxCR_CH8SSEL_UART2_TX (0x6U << DMA_CHxCR_CHxSSEL_Pos)
¤
DMA_CHxCR_CH8SSEL_UART4_TX (0x7U << DMA_CHxCR_CHxSSEL_Pos)
¦
DMA_CHxCR_CH9SSEL_SPI0_RX (0x0U << DMA_CHxCR_CHxSSEL_Pos)
§
DMA_CHxCR_CH9SSEL_SPI2_TX (0x1U << DMA_CHxCR_CHxSSEL_Pos)
¨
DMA_CHxCR_CH9SSEL_SPI4_RX (0x2U << DMA_CHxCR_CHxSSEL_Pos)
©
DMA_CHxCR_CH9SSEL_LPUART1_RX (0x3U << DMA_CHxCR_CHxSSEL_Pos)
ª
DMA_CHxCR_CH9SSEL_UART1_RX (0x4U << DMA_CHxCR_CHxSSEL_Pos)
«
DMA_CHxCR_CH9SSEL_UART3_RX (0x5U << DMA_CHxCR_CHxSSEL_Pos)
¬
DMA_CHxCR_CH9SSEL_UART5_RX (0x6U << DMA_CHxCR_CHxSSEL_Pos)
­
DMA_CHxCR_CH9SSEL_I2C0_TX (0x7U << DMA_CHxCR_CHxSSEL_Pos)
¯
DMA_CHxCR_CH10SSEL_SPI0_TX (0x0U << DMA_CHxCR_CHxSSEL_Pos)
°
DMA_CHxCR_CH10SSEL_SPI4_TX (0x1U << DMA_CHxCR_CHxSSEL_Pos)
±
DMA_CHxCR_CH10SSEL_LPUART1_TX (0x2U << DMA_CHxCR_CHxSSEL_Pos)
²
DMA_CHxCR_CH10SSEL_UART1_TX (0x3U << DMA_CHxCR_CHxSSEL_Pos)
³
DMA_CHxCR_CH10SSEL_UART3_TX (0x4U << DMA_CHxCR_CHxSSEL_Pos)
´
DMA_CHxCR_CH10SSEL_UART5_TX (0x5U << DMA_CHxCR_CHxSSEL_Pos)
µ
DMA_CHxCR_CH10SSEL_I2C0_RX (0x6U << DMA_CHxCR_CHxSSEL_Pos)
¶
DMA_CHxCR_CH10SSEL_CRC (0x7U << DMA_CHxCR_CHxSSEL_Pos)
¸
DMA_CHxCR_CIRC_UPD_Pos 7
¼
DMA_CHxCR_CIRC_UPD_Msk (0x1U << DMA_CHxCR_CIRC_UPD_Pos)
Á
DMA_CHxCR_DIR_Pos 6
Ä
DMA_CHxCR_DIR_Msk (0x1U << DMA_CHxCR_DIR_Pos)
Å
DMA_CHxCR_DIR_TO_RAM (0x0U << DMA_CHxCR_DIR_Pos)
Æ
DMA_CHxCR_DIR_TO_PER (0x1U << DMA_CHxCR_DIR_Pos)
È
DMA_CHxCR_BDW_Pos 4
Í
DMA_CHxCR_BDW_Msk (0x3U << DMA_CHxCR_BDW_Pos)
Î
DMA_CHxCR_BDW_8BITS (0x0U << DMA_CHxCR_BDW_Pos)
Ï
DMA_CHxCR_BDW_16BITS (0x1U << DMA_CHxCR_BDW_Pos)
Ð
DMA_CHxCR_BDW_32BITS (0x2U << DMA_CHxCR_BDW_Pos)
Ò
DMA_CHxCR_CIRC_Pos 3
Õ
DMA_CHxCR_CIRC_Msk (0x1U << DMA_CHxCR_CIRC_Pos)
Ù
DMA_CHxCR_CHxFTIE_Pos 2
Ü
DMA_CHxCR_CHxFTIE_Msk (0x1U << DMA_CHxCR_CHxFTIE_Pos)
à
DMA_CHxCR_CHxHTIE_Pos 1
ã
DMA_CHxCR_CHxHTIE_Msk (0x1U << DMA_CHxCR_CHxHTIE_Pos)
ç
DMA_CHxCR_ChxEN_Pos 0
ê
DMA_CHxCR_ChxEN_Msk (0x1U << DMA_CHxCR_ChxEN_Pos)
î
DMA_CHxMAR_CHxMEMAD_Pos 0
ô
DMA_CHxMAR_CHxMEMAD_Msk (0xffffffffU << DMA_CHxMAR_CHxMEMAD_Pos)
ö
DMA_CH11CR_CH11TSIZE_Pos 16
÷
DMA_CH11CR_CH11TSIZE_Msk (0x1fffU << DMA_CH11CR_CH11TSIZE_Pos)
ù
DMA_CH11CR_CH11PRI_Pos 12
þ
DMA_CH11CR_CH11PRI_Msk (0x3U << DMA_CH11CR_CH11PRI_Pos)
ÿ
DMA_CH11CR_CH11PRI_LOW (0x0U << DMA_CH11CR_CH11PRI_Pos)
€DMA_CH11CR_CH11PRI_MEDIUM (0x1U << DMA_CH11CR_CH11PRI_Pos)
DMA_CH11CR_CH11PRI_HIGH (0x2U << DMA_CH11CR_CH11PRI_Pos)
‚DMA_CH11CR_CH11PRI_VERY_HIGH (0x3U << DMA_CH11CR_CH11PRI_Pos)
„DMA_CH11CR_CH11DIR_Pos 10
‡DMA_CH11CR_CH11DIR_Msk (0x1U << DMA_CH11CR_CH11DIR_Pos)
ˆDMA_CH11CR_CH11DIR_TO_RAM (0x1U << DMA_CH11CR_CH11DIR_Pos)
‰DMA_CH11CR_CH11DIR_TO_FLASH (0x0U << DMA_CH11CR_CH11DIR_Pos)
‹DMA_CH11CR_CH11RI_Pos 9
ŽDMA_CH11CR_CH11RI_Msk (0x1U << DMA_CH11CR_CH11RI_Pos)
DMA_CH11CR_CH11RI_INCREASE (0x1U << DMA_CH11CR_CH11RI_Pos)
DMA_CH11CR_CH11RI_DECREASE (0x0U << DMA_CH11CR_CH11RI_Pos)
’DMA_CH11CR_CH11FI_Pos 8
•DMA_CH11CR_CH11FI_Msk (0x1U << DMA_CH11CR_CH11FI_Pos)
–DMA_CH11CR_CH11FI_INCREASE (0x1U << DMA_CH11CR_CH11FI_Pos)
—DMA_CH11CR_CH11FI_DECREASE (0x0U << DMA_CH11CR_CH11FI_Pos)
™DMA_CH11CR_CH11FTIE_Pos 2
œDMA_CH11CR_CH11FTIE_Msk (0x1U << DMA_CH11CR_CH11FTIE_Pos)
 DMA_CH11CR_CH11HTIE_Pos 1
£DMA_CH11CR_CH11HTIE_Msk (0x1U << DMA_CH11CR_CH11HTIE_Pos)
§DMA_CH11CR_CH11EN_Pos 0
ªDMA_CH11CR_CH11EN_Msk (0x1U << DMA_CH11CR_CH11EN_Pos)
®DMA_CH11FAR_CH11FLSAD_Pos 0
±DMA_CH11FAR_CH11FLSAD_Msk (0x7fffU << DMA_CH11FAR_CH11FLSAD_Pos)
³DMA_CH11RAR_CH7RAMAD_Pos 0
µDMA_CH11RAR_CH7RAMAD_Msk (0x7fffU << DMA_CH11RAR_CH7RAMAD_Pos)
·DMA_ISR_DMA_ADDRERR_Pos 28
¸DMA_ISR_DMA_ADDRERR_Msk (0x1U << DMA_ISR_DMA_ADDRERR_Pos)
ºDMA_ISR_DMACHFT_Pos 16
½DMA_ISR_DMACHFT_Msk (0xfffU << DMA_ISR_DMACHFT_Pos)
¿DMA_ISR_DMACHHT_Pos 0
ÀDMA_ISR_DMACHHT_Msk (0xfffU << DMA_ISR_DMACHHT_Pos)
ÂDMA_CHxCSR_CHxTSIZE_SDW_Pos 16
ÃDMA_CHxCSR_CHxTSIZE_SDW_Msk (0x1fffU << DMA_CHxCSR_CHxTSIZE_SDW_Pos)
ÅDMA_CHxCSR_CHxINC_SDW_Pos 11
ÆDMA_CHxCSR_CHxINC_SDW_Msk (0x1U << DMA_CHxCSR_CHxINC_SDW_Pos)
ÈDMA_CHxMASR_CHxMAD_SDW_Pos 0
ÊDMA_CHxMASR_CHxMAD_SDW_Msk (0xffffffffU << DMA_CHxMASR_CHxMAD_SDW_Pos)`T
 




..\Drivers\..\Core\Include\fm33a0xxev_dma.h
FM33A0XXEV.h

Œ
..\Drivers\fm33a0xxev_dma.hComponent: ARM Compiler 5.06 update 7 for Certification (build 960) Tool: ArmCC [4d365d]E:\GasFlowmeter\Internet_of_things_valve\SZV103\SZV103_FM33A0xxEV_SiZhu\KEIL_MDKARMê
DMA_CH0DMA_CH1
DMA_CH2DMA_CH3DMA_CH4DMA_CH5DMA_CH6DMA_CH7DMA_CH8DMA_CH9    DMA_CH10
DMA_CH11PDMA_CH_Typeß
*÷0CHxj
#CHxTSIZEv
#CHxPRIv
#CHxINCv
#CHxSSELv
#CHxDIRv
#CHxBDWv
#CHxCICR1
#CHxFTIE1
#CHxHTIE1
#CHxEN1
#CHxRAMADv
# CH11RIv
#$CH11FIv
#(CH11FLSADv
#,PDMA_InitTypeDef}

0
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§


__FM33A0XXEV_RMU_H 
RMU_PDRCR_PDRCFG_Pos 1
RMU_PDRCR_PDRCFG_Msk (0x3U << RMU_PDRCR_PDRCFG_Pos)
RMU_PDRCR_PDRCFG_1P5V (0x0U << RMU_PDRCR_PDRCFG_Pos)
RMU_PDRCR_PDRCFG_1P25V (0x1U << RMU_PDRCR_PDRCFG_Pos)
RMU_PDRCR_PDRCFG_1P35V (0x2U << RMU_PDRCR_PDRCFG_Pos)
RMU_PDRCR_PDRCFG_1P4V (0x3U << RMU_PDRCR_PDRCFG_Pos)
 RMU_PDRCR_PDREN_Pos 0
!RMU_PDRCR_PDREN_Msk (0x1U << RMU_PDRCR_PDREN_Pos)
%RMU_BORCR_BOR_PDRCFG_Pos 1
&RMU_BORCR_BOR_PDRCFG_Msk (0x3U << RMU_BORCR_BOR_PDRCFG_Pos)
'RMU_BORCR_BOR_PDRCFG_1P7V (0x0U << RMU_BORCR_BOR_PDRCFG_Pos)
(RMU_BORCR_BOR_PDRCFG_1P6V (0x1U << RMU_BORCR_BOR_PDRCFG_Pos)
)RMU_BORCR_BOR_PDRCFG_1P65V (0x2U << RMU_BORCR_BOR_PDRCFG_Pos)
*RMU_BORCR_BOR_PDRCFG_1P75V (0x3U << RMU_BORCR_BOR_PDRCFG_Pos)
,RMU_BORCR_OFF_BOR_Pos 0
-RMU_BORCR_OFF_BOR_Msk (0x1U << RMU_BORCR_OFF_BOR_Pos)
1RMU_RSTCFGR_LKUPRST_EN_Pos 1
2RMU_RSTCFGR_LKUPRST_EN_Msk (0x1U << RMU_RSTCFGR_LKUPRST_EN_Pos)
6RMU_SOFTRST_SOFTRST_Pos 0
7RMU_SOFTRST_SOFTRST_Msk (0xffffffffU << RMU_SOFTRST_SOFTRST_Pos)
9RMU_RSR_NRSTN_FLAG_Pos 11
:RMU_RSR_NRSTN_FLAG_Msk (0x1U << RMU_RSR_NRSTN_FLAG_Pos)
<RMU_RSR_TESTN_FLAG_Pos 10
=RMU_RSR_TESTN_FLAG_Msk (0x1U << RMU_RSR_TESTN_FLAG_Pos)
?RMU_RSR_PORN_FLAG_Pos 9
@RMU_RSR_PORN_FLAG_Msk (0x1U << RMU_RSR_PORN_FLAG_Pos)
BRMU_RSR_PDRN_FLAG_Pos 8
CRMU_RSR_PDRN_FLAG_Msk (0x1U << RMU_RSR_PDRN_FLAG_Pos)
ERMU_RSR_SOFTN_FLAG_Pos 5
FRMU_RSR_SOFTN_FLAG_Msk (0x1U << RMU_RSR_SOFTN_FLAG_Pos)
HRMU_RSR_IWDTN_FLAG_Pos 4
IRMU_RSR_IWDTN_FLAG_Msk (0x1U << RMU_RSR_IWDTN_FLAG_Pos)
KRMU_RSR_WWDTN_FLAG_Pos 2
LRMU_RSR_WWDTN_FLAG_Msk (0x1U << RMU_RSR_WWDTN_FLAG_Pos)
NRMU_RSR_LKUPN_FLAG_Pos 1
ORMU_RSR_LKUPN_FLAG_Msk (0x1U << RMU_RSR_LKUPN_FLAG_Pos)
QRMU_RSR_NVICN_FLAG_Pos 0
RRMU_RSR_NVICN_FLAG_Msk (0x1U << RMU_RSR_NVICN_FLAG_Pos)
TRMU_PRSTEN_PERHRSTEN_Pos 0
URMU_PRSTEN_PERHRSTEN_Msk (0xffffffffU << RMU_PRSTEN_PERHRSTEN_Pos)
WRMU_AHBRST_HASHRST_Pos 2
XRMU_AHBRST_HASHRST_Msk (0x1U << RMU_AHBRST_HASHRST_Pos)
\RMU_AHBRST_PAERST_Pos 1
]RMU_AHBRST_PAERST_Msk (0x1U << RMU_AHBRST_PAERST_Pos)
aRMU_AHBRST_DMARST_Pos 0
bRMU_AHBRST_DMARST_Msk (0x1U << RMU_AHBRST_DMARST_Pos)
fRMU_APBRST1_UART5RST_Pos 31
gRMU_APBRST1_UART5RST_Msk (0x1U << RMU_APBRST1_UART5RST_Pos)
kRMU_APBRST1_UART4RST_Pos 30
lRMU_APBRST1_UART4RST_Msk (0x1U << RMU_APBRST1_UART4RST_Pos)
pRMU_APBRST1_UART3RST_Pos 29
qRMU_APBRST1_UART3RST_Msk (0x1U << RMU_APBRST1_UART3RST_Pos)
uRMU_APBRST1_UART2RST_Pos 28
vRMU_APBRST1_UART2RST_Msk (0x1U << RMU_APBRST1_UART2RST_Pos)
zRMU_APBRST1_TIMARST_Pos 23
{RMU_APBRST1_TIMARST_Msk (0x1U << RMU_APBRST1_TIMARST_Pos)
RMU_APBRST1_LCDRST_Pos 16
€
RMU_APBRST1_LCDRST_Msk (0x1U << RMU_APBRST1_LCDRST_Pos)
„
RMU_APBRST1_U7816RST_Pos 14
…
RMU_APBRST1_U7816RST_Msk (0x1U << RMU_APBRST1_U7816RST_Pos)
‰
RMU_APBRST1_SPI4RST_Pos 12
Š
RMU_APBRST1_SPI4RST_Msk (0x1U << RMU_APBRST1_SPI4RST_Pos)
Ž
RMU_APBRST1_SPI3RST_Pos 11

RMU_APBRST1_SPI3RST_Msk (0x1U << RMU_APBRST1_SPI3RST_Pos)
“
RMU_APBRST1_SPI2RST_Pos 10
”
RMU_APBRST1_SPI2RST_Msk (0x1U << RMU_APBRST1_SPI2RST_Pos)
˜
RMU_APBRST1_LPUART0RST_Pos 6
™
RMU_APBRST1_LPUART0RST_Msk (0x1U << RMU_APBRST1_LPUART0RST_Pos)

RMU_APBRST1_I2C1RST_Pos 3
ž
RMU_APBRST1_I2C1RST_Msk (0x1U << RMU_APBRST1_I2C1RST_Pos)
¢
RMU_APBRST1_LPTRST_Pos 0
£
RMU_APBRST1_LPTRST_Msk (0x1U << RMU_APBRST1_LPTRST_Pos)
§
RMU_APBRST2_UART1RST_Pos 31
¨
RMU_APBRST2_UART1RST_Msk (0x1U << RMU_APBRST2_UART1RST_Pos)
¬
RMU_APBRST2_UART0RST_Pos 30
­
RMU_APBRST2_UART0RST_Msk (0x1U << RMU_APBRST2_UART0RST_Pos)
±
RMU_APBRST2_UARTIRRST_Pos 29
²
RMU_APBRST2_UARTIRRST_Msk (0x1U << RMU_APBRST2_UARTIRRST_Pos)
¶
RMU_APBRST2_BSTRST_Pos 28
·
RMU_APBRST2_BSTRST_Msk (0x1U << RMU_APBRST2_BSTRST_Pos)
»
RMU_APBRST2_CICRST_Pos 24
¼
RMU_APBRST2_CICRST_Msk (0x1U << RMU_APBRST2_CICRST_Pos)
À
RMU_APBRST2_ADCRST_Pos 23
Á
RMU_APBRST2_ADCRST_Msk (0x1U << RMU_APBRST2_ADCRST_Pos)
Å
RMU_APBRST2_AESRST_Pos 18
Æ
RMU_APBRST2_AESRST_Msk (0x1U << RMU_APBRST2_AESRST_Pos)
Ê
RMU_APBRST2_CRCRST_Pos 17
Ë
RMU_APBRST2_CRCRST_Msk (0x1U << RMU_APBRST2_CRCRST_Pos)
Ï
RMU_APBRST2_RNGRST_Pos 16
Ð
RMU_APBRST2_RNGRST_Msk (0x1U << RMU_APBRST2_RNGRST_Pos)
Ô
RMU_APBRST2_SPI1RST_Pos 9
Õ
RMU_APBRST2_SPI1RST_Msk (0x1U << RMU_APBRST2_SPI1RST_Pos)
Ù
RMU_APBRST2_SPI0RST_Pos 8
Ú
RMU_APBRST2_SPI0RST_Msk (0x1U << RMU_APBRST2_SPI0RST_Pos)
Þ
RMU_APBRST2_LPUART1RST_Pos 7
ß
RMU_APBRST2_LPUART1RST_Msk (0x1U << RMU_APBRST2_LPUART1RST_Pos)
ã
RMU_APBRST2_I2C0RST_Pos 4
ä
RMU_APBRST2_I2C0RST_Msk (0x1U << RMU_APBRST2_I2C0RST_Pos)
è
RMU_APBRST2_SVDRST_Pos 1
é
RMU_APBRST2_SVDRST_Msk (0x1U << RMU_APBRST2_SVDRST_Pos)
í
RMU_APBRST2_COMPRST_Pos 0
î
RMU_APBRST2_COMPRST_Msk (0x1U << RMU_APBRST2_COMPRST_Pos)`T
 




..\Drivers\..\Core\Include\fm33a0xxev_rmu.h
FM33A0XXEV.h

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..\Drivers\fm33a0xxev_rmu.hComponent: ARM Compiler 5.06 update 7 for Certification (build 960) Tool: ArmCC [4d365d]E:\GasFlowmeter\Internet_of_things_valve\SZV103\SZV103_FM33A0xxEV_SiZhu\KEIL_MDKARM
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..\Drivers\..\Drivers\fm33a0xxev_dma.cfm33a0xxev_dma.h
fm33a0xxev_rmu.h


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%Component: ARM Compiler 5.06 update 7 for Certification (build 960) Tool: armlink [4d3601]armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=9931,9931,6642 --cpu=Cortex-M0 --fpu=SoftVFP --output=.\objects\fm33a0xxev_dma.o --vfemode=force
Input Comments:p4c30-3Component: ARM Compiler 5.06 update 7 for Certification (build 960) Tool: armasm [4d35fa]armasm --debug --diag_suppress=9931,9931,1602,1073 --cpu=Cortex-M0 --fpu=SoftVFP --apcs=/interwork/interwork --no_divide fm33a0xxev_dma.oComponent: ARM Compiler 5.06 update 7 for Certification (build 960) Tool: ArmCC [4d365d]ArmCC --c99 --split_sections --debug -c --gnu -o.\objects\fm33a0xxev_dma.o --depend=.\objects\fm33a0xxev_dma.d --cpu=Cortex-M0 --apcs=interwork -O0 --diag_suppress=9931 -I..\Core -I..\Drivers -I..\Core\Include -I..\Hardware -I.\RTE\Device -I..\Hardware\CLOCK -I..\Hardware\DELAY -I..\Hardware\GPIO -I..\Hardware\UART -I..\Hardware\TIM -I..\Function\KEY -I..\Hardware\EXTI -I..\Hardware\RTC -I..\Hardware\ADC -I..\Hardware\I2C -I..\Function\LCD -I..\Function\EXTERN_RTC -I..\Hardware\SPI -I..\Function\GPRS -I..\Function\HARDWARE_WATCHDOG -I..\Function\IR_NEC -I..\Function\MEASURE_INTERACTION -I..\Function\POWER_MANAGE -I..\Function\STORAGE -I..\Function\UPPER_COMPUTER -I..\Function\VALVE -I..\Soft -I..\MultiButton -I..\USMART -I..\Hardware\DMA -I..\Hardware\ON_CHIP_FLASH -I..\Hardware\SVD -I..\Function\OFF_CHIP_FLASH -I..\Hardware\CRC -I..\Function\BOOTLOADER_IAP -I..\Hardware\COMP -I..\CmBackTrace -I..\Function\E2P -I..\Function\FLOW_METER_DATA_COLLECT -I..\Function\WirelessRemoteComm -I..\Function\POWER_MANAGE -I..\Function\BILLING -I..\Function\modbus -I..\Function\modbus\functions -I..\Function\modbus\include -I..\Function\modbus\port -I..\Function\modbus\rtu -I.\RTE\_SZV103_FM33A0_MainSystem -I"D:\Program Files\MDK5\Packs\Keil\FM33A0XXEV_DFP\0.0.4\Device\Include" -D__MICROLIB -D__UVISION_VERSION=538 -D_RTE_ -D_RTE_ -D__VTOR_PRESENT --omf_browse=.\objects\fm33a0xxev_dma.crf ..\Drivers\fm33a0xxev_dma.cû2
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