add lower model test

wujiazhi

2024-06-13 72def895431ad7a08e635b11f3da738e2b2c4618

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..\\Drivers\\fm33a0xxev_spi.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM__asm___16_fm33a0xxev_spi_c_d9542dad____REV16P9

 




..\\Core\\Include\\core_cminstr.h
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..\\Drivers\\fm33a0xxev_spi.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM__asm___16_fm33a0xxev_spi_c_d9542dad____REVSHP9

 




..\\Core\\Include\\core_cminstr.h
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..\Drivers\fm33a0xxev_spi.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM
..\Drivers\fm33a0xxev_spi.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM?›
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..\Drivers\fm33a0xxev_spi.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM>
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..\Drivers\fm33a0xxev_spi.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM?™
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..\Drivers\fm33a0xxev_spi.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM>Ž
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..\Drivers\fm33a0xxev_spi.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM?™
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..\Drivers\fm33a0xxev_spi.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM>Ž
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..\Drivers\fm33a0xxev_spi.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM?—
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..\Drivers\fm33a0xxev_spi.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM>Œ
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..\Drivers\fm33a0xxev_spi.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM?™
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..\Drivers\fm33a0xxev_spi.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM
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..\Drivers\fm33a0xxev_spi.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM?™
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..\Drivers\fm33a0xxev_spi.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM
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..\Drivers\fm33a0xxev_spi.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM?™
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..\Drivers\fm33a0xxev_spi.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM
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..\Drivers\fm33a0xxev_spi.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM?›
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..\Drivers\fm33a0xxev_spi.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM
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..\Drivers\fm33a0xxev_spi.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM?š
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..\Drivers\fm33a0xxev_spi.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM>•
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..\Drivers\fm33a0xxev_spi.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM?›
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..\Drivers\fm33a0xxev_spi.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM
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..\Drivers\fm33a0xxev_spi.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM?›
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..\Drivers\fm33a0xxev_spi.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM
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..\Drivers\fm33a0xxev_spi.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM?
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..\Drivers\fm33a0xxev_spi.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM?
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..\Drivers\fm33a0xxev_spi.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM?™
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..\Drivers\fm33a0xxev_spi.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM?
ûSPIx_CR2_SSNSEN_Setable
iSPIxI
)iNewState

..\Drivers\fm33a0xxev_spi.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM>–
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SPIx_CR2_SSNSEN_Getable

iSPIxI
*___result


..\Drivers\fm33a0xxev_spi.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM?
”SPIx_CR2_SPIEN_Setable
iSPIxI
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..\Drivers\fm33a0xxev_spi.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM>•
 
SPIx_CR2_SPIEN_Getable

iSPIxI
*___result

ø..\Drivers\fm33a0xxev_spi.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM?ø

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iSPIxI
ø..\Drivers\fm33a0xxev_spi.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM?ø

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iSPIxI
ø..\Drivers\fm33a0xxev_spi.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM?ø

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iSPIxI
ø..\Drivers\fm33a0xxev_spi.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM?ø

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iSPIxI

..\Drivers\fm33a0xxev_spi.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM?
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SPIx_IER_ERRIE_Getable

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..\Drivers\fm33a0xxev_spi.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM>”
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SPIx_IER_TXIE_Getable

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..\Drivers\fm33a0xxev_spi.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM?Ž
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..\Drivers\fm33a0xxev_spi.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM>”
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SPIx_IER_RXIE_Getable

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..\Drivers\fm33a0xxev_spi.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM?œ
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..\Drivers\fm33a0xxev_spi.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM>‘
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..\Drivers\fm33a0xxev_spi.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM>‘
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__DATE__ "Jun 13 2024"
__TIME__ "10:36:17"
__STDC__ 1
__STDC_VERSION__ 199901L
__STDC_HOSTED__ 1
__STDC_ISO_10646__ 200607
__EDG__ 1
__EDG_VERSION__ 407
__EDG_SIZE_TYPE__ unsigned int
__EDG_PTRDIFF_TYPE__ int
__GNUC__ 4
__GNUC_STDC_INLINE__ 1
__GNUC_MINOR__ 7
__GNUC_PATCHLEVEL__ 0
__VERSION__ "4.7 (EDG gcc mode)"
__CHAR16_TYPE__ unsigned short
__CHAR32_TYPE__ unsigned int
__USER_LABEL_PREFIX__ 
__CHAR_UNSIGNED__ 1
__WCHAR_UNSIGNED__ 1
__SIZE_TYPE__ unsigned int
__PTRDIFF_TYPE__ int
__WCHAR_TYPE__ unsigned short
__WINT_TYPE__ unsigned short
__INTMAX_TYPE__ long long
__UINTMAX_TYPE__ unsigned long long
__sizeof_int 4
__sizeof_long 4
__sizeof_ptr 4
__ARMCC_VERSION 5060750
__TARGET_CPU_CORTEX_M0 1
__TARGET_FPU_SOFTVFP 1
__TARGET_FPU_SOFTVFP 1
__MICROLIB 1
__UVISION_VERSION 525
_RTE_ 1
__VTOR_PRESENT 1
__CC_ARM 1
__arm 1
__arm__ 1
__TARGET_ARCH_6S_M 1
__TARGET_ARCH_ARM 0
__TARGET_ARCH_THUMB 3
__TARGET_ARCH_A64 0
__TARGET_ARCH_AARCH32 1
__TARGET_PROFILE_M 1
__TARGET_FEATURE_HALFWORD 1
__TARGET_FEATURE_THUMB 1
__TARGET_FEATURE_DMB 1
__TARGET_FEATURE_EXTENSION_REGISTER_COUNT 0
__APCS_INTERWORK 1
__thumb 1
__thumb__ 1
__t32__ 1
__OPTIMISE_SPACE 1
__OPTIMIZE_SIZE__ 1
__OPTIMISE_LEVEL 0
__SOFTFP__ 1
& 
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ÁSPIx_CR1_CPHOL_Set%
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ÁSPIx_CR2_DLEN_Set$
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ÁSPIx_CR2_HALFDUPLEX_Set*
ÁSPIx_CR2_HALFDUPLEX_Get% 
ÁSPIx_CR2_HD_RW_Set%
ÁSPIx_CR2_HD_RW_Get% 
ÁSPIx_CR2_CMD8b_Set%
ÁSPIx_CR2_CMD8b_Get$
ÁSPIx_CR2_SSNM_Set$
ÁSPIx_CR2_SSNM_Get*
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ÁSPIx_IER_TXIE_Setable(
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#__STDINT_DECLS %__CLIBNS
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yINT8_MIN -128
zINT16_MIN -32768
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|INT64_MIN __INT64_C(~0x7fffffffffffffff)
INT8_MAX 127
€
INT16_MAX 32767

INT32_MAX 2147483647
‚
INT64_MAX __INT64_C(9223372036854775807)
…
UINT8_MAX 255
†
UINT16_MAX 65535
‡
UINT32_MAX 4294967295u
ˆ
UINT64_MAX __UINT64_C(18446744073709551615)

INT_LEAST8_MIN -128
Ž
INT_LEAST16_MIN -32768

INT_LEAST32_MIN (~0x7fffffff)

INT_LEAST64_MIN __INT64_C(~0x7fffffffffffffff)
“
INT_LEAST8_MAX 127
”
INT_LEAST16_MAX 32767
•
INT_LEAST32_MAX 2147483647
–
INT_LEAST64_MAX __INT64_C(9223372036854775807)
™
UINT_LEAST8_MAX 255
š
UINT_LEAST16_MAX 65535
›
UINT_LEAST32_MAX 4294967295u
œ
UINT_LEAST64_MAX __UINT64_C(18446744073709551615)
¡
INT_FAST8_MIN (~0x7fffffff)
¢
INT_FAST16_MIN (~0x7fffffff)
£
INT_FAST32_MIN (~0x7fffffff)
¤
INT_FAST64_MIN __INT64_C(~0x7fffffffffffffff)
§
INT_FAST8_MAX 2147483647
¨
INT_FAST16_MAX 2147483647
©
INT_FAST32_MAX 2147483647
ª
INT_FAST64_MAX __INT64_C(9223372036854775807)
­
UINT_FAST8_MAX 4294967295u
®
UINT_FAST16_MAX 4294967295u
¯
UINT_FAST32_MAX 4294967295u
°
UINT_FAST64_MAX __UINT64_C(18446744073709551615)
¸
INTPTR_MIN INT32_MIN
¿
INTPTR_MAX INT32_MAX
Æ
UINTPTR_MAX UINT32_MAX
Ì
INTMAX_MIN __ESCAPE__(~0x7fffffffffffffffll)
Ï
INTMAX_MAX __ESCAPE__(9223372036854775807ll)
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UINTMAX_MAX __ESCAPE__(18446744073709551615ull)
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PTRDIFF_MIN INT32_MIN
Ü
PTRDIFF_MAX INT32_MAX
à
SIG_ATOMIC_MIN (~0x7fffffff)
á
SIG_ATOMIC_MAX 2147483647
ç
SIZE_MAX UINT32_MAXí
WCHAR_MINî
WCHAR_MAX
ô
WCHAR_MIN 0
õ
WCHAR_MAX 65535
ù
WINT_MIN (~0x7fffffff)
ú
WINT_MAX 2147483647
INT8_C(x) (x)
‚INT16_C(x) (x)
ƒINT32_C(x) (x)
„INT64_C(x) __INT64_C(x)
†UINT8_C(x) (x ## u)
‡UINT16_C(x) (x ## u)
ˆUINT32_C(x) (x ## u)
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D:\Keil5\ARM\ARMCC\Bin\..\include\stdint.h


0D:\Keil5\ARM\ARMCC\Bin\..\include\stdint.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]
signed charshortintlong long
unsigned charunsigned shortunsigned intunsigned long longPint8_tˆ
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'__CORE_CMINSTR_H 
<__NOP __nop
D__WFI __wfi
L__WFE __wfe
S__SEV __sev
\__ISB() do { __schedule_barrier(); __isb(0xF); __schedule_barrier(); } while (0)
g__DSB() do { __schedule_barrier(); __dsb(0xF); __schedule_barrier(); } while (0)
r__DMB() do { __schedule_barrier(); __dmb(0xF); __schedule_barrier(); } while (0)
__REV __rev
©
__ROR __ror
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__BKPT(value) __breakpoint(value)
Ú
__CLZ __clz@6
 




..\Core\Include\core_cminstr.h




..\Core\Include\core_cminstr.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM;†
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'__CORE_CMFUNC_H @5
 




..\Core\Include\core_cmfunc.h


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..\Core\Include\core_cmfunc.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM;ÿ

@__get_CONTROLW
a__resultW

Y__regControlW

P<¸
M__set_CONTROL$W
controlY__regControlW

P;ò
Z__get_IPSRW
a__resultW

Y__regIPSRW

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g__get_APSRW
a__resultW

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t__get_xPSRW
a__resultW

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__get_PSPW
a__resultW

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a__resultW

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 __CORE_CM0PLUS_H_GENERIC "
@__CM0PLUS_CMSIS_VERSION_MAIN ( 5U)
A__CM0PLUS_CMSIS_VERSION_SUB ( 0U)
B__CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | __CM0PLUS_CMSIS_VERSION_SUB )
E__CORTEX_M (0U)
Q__ASM __asm
R__INLINE __inline
S__STATIC_INLINE static __inline
T__NO_RETURN __declspec(noreturn)
U__USED __attribute__((used))
V__WEAK __attribute__((weak))
W__UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
Ÿ
__FPU_USED 0UÆ
Ç

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__CORE_CM0PLUS_H_DEPENDANT 
ÿ
__I volatile const
__O volatile
‚__IO volatile
…__IM volatile const
†__OM volatile
‡__IOM volatile
³APSR_N_Pos 31U
´APSR_N_Msk (1UL << APSR_N_Pos)
¶APSR_Z_Pos 30U
·APSR_Z_Msk (1UL << APSR_Z_Pos)
¹APSR_C_Pos 29U
ºAPSR_C_Msk (1UL << APSR_C_Pos)
¼APSR_V_Pos 28U
½APSR_V_Msk (1UL << APSR_V_Pos)
ÎIPSR_ISR_Pos 0U
ÏIPSR_ISR_Msk (0x1FFUL )
æxPSR_N_Pos 31U
çxPSR_N_Msk (1UL << xPSR_N_Pos)
éxPSR_Z_Pos 30U
êxPSR_Z_Msk (1UL << xPSR_Z_Pos)
ìxPSR_C_Pos 29U
íxPSR_C_Msk (1UL << xPSR_C_Pos)
ïxPSR_V_Pos 28U
ðxPSR_V_Msk (1UL << xPSR_V_Pos)
òxPSR_T_Pos 24U
óxPSR_T_Msk (1UL << xPSR_T_Pos)
õxPSR_ISR_Pos 0U
öxPSR_ISR_Msk (0x1FFUL )
ˆCONTROL_SPSEL_Pos 1U
‰CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)
‹CONTROL_nPRIV_Pos 0U
ŒCONTROL_nPRIV_Msk (1UL )
ÈSCB_CPUID_IMPLEMENTER_Pos 24U
ÉSCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
ËSCB_CPUID_VARIANT_Pos 20U
ÌSCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
ÎSCB_CPUID_ARCHITECTURE_Pos 16U
ÏSCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
ÑSCB_CPUID_PARTNO_Pos 4U
ÒSCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
ÔSCB_CPUID_REVISION_Pos 0U
ÕSCB_CPUID_REVISION_Msk (0xFUL )
ØSCB_ICSR_NMIPENDSET_Pos 31U
ÙSCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)
ÛSCB_ICSR_PENDSVSET_Pos 28U
ÜSCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
ÞSCB_ICSR_PENDSVCLR_Pos 27U
ßSCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
áSCB_ICSR_PENDSTSET_Pos 26U
âSCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
äSCB_ICSR_PENDSTCLR_Pos 25U
åSCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
çSCB_ICSR_ISRPREEMPT_Pos 23U
èSCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
êSCB_ICSR_ISRPENDING_Pos 22U
ëSCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
íSCB_ICSR_VECTPENDING_Pos 12U
îSCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
ðSCB_ICSR_VECTACTIVE_Pos 0U
ñSCB_ICSR_VECTACTIVE_Msk (0x1FFUL )
õSCB_VTOR_TBLOFF_Pos 8U
öSCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)
úSCB_AIRCR_VECTKEY_Pos 16U
ûSCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
ýSCB_AIRCR_VECTKEYSTAT_Pos 16U
þSCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
€SCB_AIRCR_ENDIANESS_Pos 15U
SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
ƒSCB_AIRCR_SYSRESETREQ_Pos 2U
„SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
†SCB_AIRCR_VECTCLRACTIVE_Pos 1U
‡SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
ŠSCB_SCR_SEVONPEND_Pos 4U
‹SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
SCB_SCR_SLEEPDEEP_Pos 2U
ŽSCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
SCB_SCR_SLEEPONEXIT_Pos 1U
‘SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
”SCB_CCR_STKALIGN_Pos 9U
•SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)
—SCB_CCR_UNALIGN_TRP_Pos 3U
˜SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
›SCB_SHCSR_SVCALLPENDED_Pos 15U
œSCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
´SysTick_CTRL_COUNTFLAG_Pos 16U
µSysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
·SysTick_CTRL_CLKSOURCE_Pos 2U
¸SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
ºSysTick_CTRL_TICKINT_Pos 1U
»SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
½SysTick_CTRL_ENABLE_Pos 0U
¾SysTick_CTRL_ENABLE_Msk (1UL )
ÁSysTick_LOAD_RELOAD_Pos 0U
ÂSysTick_LOAD_RELOAD_Msk (0xFFFFFFUL )
ÅSysTick_VAL_CURRENT_Pos 0U
ÆSysTick_VAL_CURRENT_Msk (0xFFFFFFUL )
ÉSysTick_CALIB_NOREF_Pos 31U
ÊSysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)
ÌSysTick_CALIB_SKEW_Pos 30U
ÍSysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)
ÏSysTick_CALIB_TENMS_Pos 0U
ÐSysTick_CALIB_TENMS_Msk (0xFFFFFFUL )
éMPU_TYPE_IREGION_Pos 16U
êMPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
ìMPU_TYPE_DREGION_Pos 8U
íMPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
ïMPU_TYPE_SEPARATE_Pos 0U
ðMPU_TYPE_SEPARATE_Msk (1UL )
óMPU_CTRL_PRIVDEFENA_Pos 2U
ôMPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
öMPU_CTRL_HFNMIENA_Pos 1U
÷MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
ùMPU_CTRL_ENABLE_Pos 0U
úMPU_CTRL_ENABLE_Msk (1UL )
ýMPU_RNR_REGION_Pos 0U
þMPU_RNR_REGION_Msk (0xFFUL )
MPU_RBAR_ADDR_Pos 8U
‚MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)
„MPU_RBAR_VALID_Pos 4U
…MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos)
‡MPU_RBAR_REGION_Pos 0U
ˆMPU_RBAR_REGION_Msk (0xFUL )
‹MPU_RASR_ATTRS_Pos 16U
ŒMPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos)
ŽMPU_RASR_XN_Pos 28U
MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos)
‘MPU_RASR_AP_Pos 24U
’MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos)
”MPU_RASR_TEX_Pos 19U
•MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos)
—MPU_RASR_S_Pos 18U
˜MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos)
šMPU_RASR_C_Pos 17U
›MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos)
MPU_RASR_B_Pos 16U
žMPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos)
 MPU_RASR_SRD_Pos 8U
¡MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos)
£MPU_RASR_SIZE_Pos 1U
¤MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos)
¦MPU_RASR_ENABLE_Pos 0U
§MPU_RASR_ENABLE_Msk (1UL )
Ä_VAL2FLD(field,value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
Ì_FLD2VAL(field,value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
ÙSCS_BASE (0xE000E000UL)
ÚSysTick_BASE (SCS_BASE + 0x0010UL)
ÛNVIC_BASE (SCS_BASE + 0x0100UL)
ÜSCB_BASE (SCS_BASE + 0x0D00UL)
ÞSCB ((SCB_Type *) SCB_BASE )
ßSysTick ((SysTick_Type *) SysTick_BASE )
àNVIC ((NVIC_Type *) NVIC_BASE )
ãMPU_BASE (SCS_BASE + 0x0D90UL)
äMPU ((MPU_Type *) MPU_BASE )
‚_BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
ƒ_SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
„_IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )”ˆ
 




..\Core\Include\D:\Keil5\ARM\ARMCC\Bin\..\include\core_cm0plus.h
stdint.hcore_cminstr.h
core_cmfunc.h


°
..\Core\Include\core_cm0plus.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM*”!_reserved0W
#!VW
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__stdio_h 
__ARMCLIB_VERSION 5060037
"_ARMABI __declspec(__nothrow)
%__STDIO_DECLS '__CLIBNS
-__CLIBNS <NULL
=NULL 0
g_SYS_OPEN 16
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stdin (&__CLIBNS __stdin)
§
stdout (&__CLIBNS __stdout)
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stderr (&__CLIBNS __stderr)
¬
_IOFBF 0x100
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_IOLBF 0x200
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_IONBF 0x400
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BUFSIZ (512)
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FOPEN_MAX _SYS_OPEN
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FILENAME_MAX 256
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L_tmpnam FILENAME_MAX
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TMP_MAX 256
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EOF (-1)
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SEEK_SET 0
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_IOBIN 0x04
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__STDIN_BUFSIZ (64)
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D:\Keil5\ARM\ARMCC\Bin\..\include\stdio.h


´
D:\Keil5\ARM\ARMCC\Bin\..\include\stdio.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]unsigned intunsigned long longPsize_t‡
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$FM33A0XXEV_H 
.__RCHF_INITIAL_CLOCK (8000000)
/__RCMF_CLOCK (2000000)
0__RCLP_CLOCK (32000)
1__XTLF_CLOCK (32768)
n__CM0_REV 0x0100
o__MPU_PRESENT 1
p__VTOR_PRESENT 1
q__NVIC_PRIO_BITS 2
r__Vendor_SysTickConfig 0uv
¿FLASH_BASE (( uint32_t)0x00000000)
ÀSRAM_BASE (( uint32_t)0x20000000)
ÁPERIPH_BASE (( uint32_t)0x40000000)
ÊPMU_BASE (PERIPH_BASE +0x00002000)
ËDBG_BASE (PERIPH_BASE +0x00000000)
ÌFLS_BASE (PERIPH_BASE +0x00001000)
ÍRMU_BASE (PERIPH_BASE +0x00002800)
ÎIWDT_BASE (PERIPH_BASE +0x00011400)
ÏWWDT_BASE (PERIPH_BASE +0x00011800)
ÐCMU_BASE (PERIPH_BASE +0x00002400)
ÑCDIF_BASE (PERIPH_BASE +0x0001E000)
ÒVRTC_BASE (PERIPH_BASE +0x0001F800)
ÓSVD_BASE (PERIPH_BASE +0x00012800)
ÔAES_BASE (PERIPH_BASE +0x00013800)
ÕPAE_BASE (PERIPH_BASE +0x00001400)
ÖHASH_BASE (PERIPH_BASE +0x00001800)
×RNG_BASE (PERIPH_BASE +0x00013C00)
ØCOMP_BASE (PERIPH_BASE +0x00015400)
ÙI2C0_BASE (PERIPH_BASE +0x00012400)
ÚI2C1_BASE (PERIPH_BASE +0x00015000)
ÛUARTIR_BASE (PERIPH_BASE +0x00017C00)
ÜUART0_BASE (PERIPH_BASE +0x00012000)
ÝUART1_BASE (PERIPH_BASE +0x00016800)
ÞUART2_BASE (PERIPH_BASE +0x00016C00)
ßUART3_BASE (PERIPH_BASE +0x00017000)
àUART4_BASE (PERIPH_BASE +0x00017400)
áUART5_BASE (PERIPH_BASE +0x00017800)
âLPUART0_BASE (PERIPH_BASE +0x00014000)
ãLPUART1_BASE (PERIPH_BASE +0x00014400)
äSPI0_BASE (PERIPH_BASE +0x00010400)
åSPI1_BASE (PERIPH_BASE +0x00010800)
æSPI2_BASE (PERIPH_BASE +0x00014800)
çSPI3_BASE (PERIPH_BASE +0x00014C00)
èSPI4_BASE (PERIPH_BASE +0x00016400)
éU7816_BASE (PERIPH_BASE +0x00011C00)
êQSPI_BASE (PERIPH_BASE +0x00000800)
ëDMA_BASE (PERIPH_BASE +0x00000400)
ìCRC_BASE (PERIPH_BASE +0x00010000)
íBT1_BASE (PERIPH_BASE +0x00013000)
îBT2_BASE (PERIPH_BASE +0x00013044)
ïET1_BASE (PERIPH_BASE +0x00013090)
ðET2_BASE (PERIPH_BASE +0x000130B0)
ñET3_BASE (PERIPH_BASE +0x000130D0)
òET4_BASE (PERIPH_BASE +0x000130F0)
óETCNT_BASE (PERIPH_BASE +0x00013110)
ôBSTIM_BASE (PERIPH_BASE +0x00016000)
õLPTIM_BASE (PERIPH_BASE +0x00013400)
öRTC_BASE (PERIPH_BASE +0x00011000)
÷LCD_BASE (PERIPH_BASE +0x00010C00)
øADC_BASE (PERIPH_BASE +0x0001FA00)
ùCIC_BASE (PERIPH_BASE +0x00015C00)
úGPIOA_BASE (PERIPH_BASE +0x00000C00)
ûGPIOB_BASE (PERIPH_BASE +0x00000C40)
üGPIOC_BASE (PERIPH_BASE +0x00000C80)
ýGPIOD_BASE (PERIPH_BASE +0x00000CC0)
þGPIOE_BASE (PERIPH_BASE +0x00000D00)
ÿGPIOF_BASE (PERIPH_BASE +0x00000D40)
€GPIOG_BASE (PERIPH_BASE +0x00000D80)
GPIOH_BASE (PERIPH_BASE +0x0001FC00)
‚GPIO_BASE (PERIPH_BASE +0x00000DC0)
ˆPMU ((PMU_Type *) PMU_BASE )
‰DBG ((DBG_Type *) DBG_BASE )
ŠFLS ((FLS_Type *) FLS_BASE )
‹RMU ((RMU_Type *) RMU_BASE )
ŒIWDT ((IWDT_Type *) IWDT_BASE )
WWDT ((WWDT_Type *) WWDT_BASE )
ŽCMU ((CMU_Type *) CMU_BASE )
CDIF ((CDIF_Type *) CDIF_BASE )
VRTC ((VRTC_Type *) VRTC_BASE )
‘SVD ((SVD_Type *) SVD_BASE )
’AES ((AES_Type *) AES_BASE )
“PAE ((PAE_Type *) PAE_BASE )
”HASH ((HASH_Type *) HASH_BASE )
•RNG ((RNG_Type *) RNG_BASE )
–COMP ((COMP_Type *) COMP_BASE )
—I2C0 ((I2C_Type *) I2C0_BASE )
˜I2C1 ((I2C_Type *) I2C1_BASE )
™UARTIR ((UARTIR_Type *) UARTIR_BASE )
šUART0 ((UART_Type *) UART0_BASE )
›UART1 ((UART_Type *) UART1_BASE )
œUART2 ((UART_Type *) UART2_BASE )
UART3 ((UART_Type *) UART3_BASE )
žUART4 ((UART_Type *) UART4_BASE )
ŸUART5 ((UART_Type *) UART5_BASE )
 LPUART0 ((LPUART_Type *) LPUART0_BASE )
¡LPUART1 ((LPUART_Type *) LPUART1_BASE )
¢SPI0 ((SPI_Type *) SPI0_BASE )
£SPI1 ((SPI_Type *) SPI1_BASE )
¤SPI2 ((SPI_Type *) SPI2_BASE )
¥SPI3 ((SPI_Type *) SPI3_BASE )
¦SPI4 ((SPI_Type *) SPI4_BASE )
§U7816 ((U7816_Type *) U7816_BASE )
¨QSPI ((QSPI_Type *) QSPI_BASE )
©DMA ((DMA_Type *) DMA_BASE )
ªCRC ((CRC_Type *) CRC_BASE )
«BT1 ((BT_Type *) BT1_BASE )
¬BT2 ((BT_Type *) BT2_BASE )
­ET1 ((ET_Type *) ET1_BASE )
®ET2 ((ET_Type *) ET2_BASE )
¯ET3 ((ET_Type *) ET3_BASE )
°ET4 ((ET_Type *) ET4_BASE )
±ETCNT ((ETCNT_Type *) ETCNT_BASE )
²BSTIM ((BSTIM_Type *) BSTIM_BASE )
³LPTIM ((LPTIM_Type *) LPTIM_BASE )
´RTC ((RTC_Type *) RTC_BASE )
µLCD ((LCD_Type *) LCD_BASE )
¶ADC ((ADC_Type *) ADC_BASE )
·CIC ((CIC_Type *) CIC_BASE )
¸GPIOA ((GPIO_Type *) GPIOA_BASE )
¹GPIOB ((GPIO_Type *) GPIOB_BASE )
ºGPIOC ((GPIO_Type *) GPIOC_BASE )
»GPIOD ((GPIO_Type *) GPIOD_BASE )
¼GPIOE ((GPIO_Type *) GPIOE_BASE )
½GPIOF ((GPIO_Type *) GPIOF_BASE )
¾GPIOG ((GPIO_Type *) GPIOG_BASE )
¿GPIOH ((GPIOH_Type *) GPIOH_BASE )
ÀGPIO ((GPIO_COMMON_Type *) GPIO_BASE )h]
 




..\Core\Include\FM33A0XXEV.h
core_cm0plus.h
system_FM33A0XXEV.h


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..\Core\Include\FM33A0XXEV.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMÓ

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Reset_IRQnqNMI_IRQnrHardFault_IRQnsSVC_IRQn{PendSV_IRQn~SysTick_IRQnWWDT_IRQnSVD_IRQn
RTC_IRQnFLASH_IRQnCMU_IRQnADC_IRQnSPI0_IRQnSPI1_IRQnSPI2_IRQnUART0_IRQn    UART1_IRQn
UART2_IRQnUART3_IRQnUART4_IRQn UART5_IRQnU7816_IRQnLPUART0_IRQnI2Cx_IRQnRSV_IRQnCRYPTO_IRQnLPTIM_IRQnDMA_IRQnWKUPx_IRQnCOMP_IRQnBTx_IRQnQSPI_IRQnETx_IRQnBSTIM_IRQnSPI3_IRQnSPI4_IRQnGPIO_IRQnLPUART1_IRQnPIRQn_TypeG

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RSV1î#EPCRv#KEYv#IERv#ISRv# ¹v
RSV20#$ACLOCK1v#HACLOCK2v#LACLOCK3v#PACLOCK4v#TW
t‚PFLS_TypeÅ
¾
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$PDRCRv#BORCRv#RSTCFGRv#SOFTRSTv#RSRv#PRSTENv#AHBRSTv#APBRST1v#APBRST2v# PRMU_Type
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SERVv#CFGRv#CNTRˆ#PIWDT_Type0
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* 8SYSCLKCRv#RCHFCRv#RCHFTRv#PLLLCRv#PLLHCRv#XTHFCRv#IERv#ISRv#PCLKCR1v# PCLKCR2v#$PCLKCR3v#(PCLKCR4v#,OPCCR1v#0OPCCR2v#4PCMU_TypeÆ
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RSV1Þ#RCMFCRv#RCLPCRv#RCLPTRv#XTLFCRv# ADCCRv#$LFDIERv#(LFDISRv#,PVRTC_TypeÍ
ž*£CFGRv#CRv#IERv#ISRv#VSRv#PSVD_Typeg
¬*§TCRv#IERv#ISRv#DIRv#DORˆ#KEY0v#KEY1v#KEY2v#KEY3v# KEY4v#$KEY5v#(KEY6v#,KEY7v#0IVR0v#4IVR1v#8IVR2v#<IVR3v#@H0v#DH1v#HH2v#LH3v#PPAES_Type´
Ê*ž CSRv#MLRv#MPRv#M0CFGv#M1CFGv#M2CFGv#M3CFGv#WORDv#PPAE_Type¸
Û*ÊCSRv#DTRv#PHASH_Type/    
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RSV1u    #SRv#CRC_CRv#CRC_DIRv#CRC_SRv#PRNG_Type\    
ö*CR1v#CR2v#ICRv#ISRv#PCRv#PCOMP_TypeÑ    
„*ˆ$CFGRv#CRv#IERv#ISRv#SRv#BRGv#BUFv#TIMINGv#TOv# PI2C_Type

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 *“CSRv#IERv#ISRv#TODRv#RXBUFˆ#TXBUFv#BGRv#PUART_Type¼

°*ûCSRv#IERv#ISRv#BMRv#RXBUFv#TXBUFv#DMRv#PLPUART_Type%
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Ð*â$CRv#FFRv#EGTRv#PSCv#BGRv#RXBUFˆ#TXBUFv#IERv#ISRv# PU7816_Typeö
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(SYSTEM_FM33A0XXEV_H 234
O__SYSTEM_CLOCK (8000000)
PDELAY_US (__SYSTEM_CLOCK/1000000)
QDELAY_MS (__SYSTEM_CLOCK/1000)
TDo_DelayStart() { uint32_t LastTick = SysTick->VAL; do {
WWhile_DelayMsEnd(Count) }while(((LastTick - SysTick->VAL)&0xFFFFFF)<DELAY_MS*Count); }
ZWhile_DelayUsEnd(Count) }while(((LastTick - SysTick->VAL)&0xFFFFFF)<DELAY_US*Count); }…
 




..\Core\Include\D:\Keil5\ARM\ARMCC\Bin\..\include\system_FM33A0XXEV.h
stdint.hstdio.hFM33A0XXEV.h


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..\Core\Include\system_FM33A0XXEV.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMqSystemCoreClockW


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__FM33A0XXEV_SPI_H 
SPIx_CR1_IOSWAP_Pos 11
SPIx_CR1_IOSWAP_Msk (0x1U << SPIx_CR1_IOSWAP_Pos)
SPIx_CR1_IOSWAP_DEFAULT (0x0U << SPIx_CR1_IOSWAP_Pos)
 SPIx_CR1_IOSWAP_EXCHANGE (0x1U << SPIx_CR1_IOSWAP_Pos)
"SPIx_CR1_MSPA_Pos 10
%SPIx_CR1_MSPA_Msk (0x1U << SPIx_CR1_MSPA_Pos)
&SPIx_CR1_MSPA_DELAY (0x1U << SPIx_CR1_MSPA_Pos)
'SPIx_CR1_MSPA_NORMAL (0x0U << SPIx_CR1_MSPA_Pos)
)SPIx_CR1_SSPA_Pos 9
,SPIx_CR1_SSPA_Msk (0x1U << SPIx_CR1_SSPA_Pos)
-SPIx_CR1_SSPA_EARLY (0x1U << SPIx_CR1_SSPA_Pos)
.SPIx_CR1_SSPA_NORMAL (0x0U << SPIx_CR1_SSPA_Pos)
0SPIx_CR1_MM_Pos 8
1SPIx_CR1_MM_Msk (0x1U << SPIx_CR1_MM_Pos)
2SPIx_CR1_MM_MASTER (0x1U << SPIx_CR1_MM_Pos)
3SPIx_CR1_MM_SLAVE (0x0U << SPIx_CR1_MM_Pos)
5SPIx_CR1_WAIT_Pos 6
6SPIx_CR1_WAIT_Msk (0x3U << SPIx_CR1_WAIT_Pos)
7SPIx_CR1_WAIT_1WAIT (0x0U << SPIx_CR1_WAIT_Pos)
8SPIx_CR1_WAIT_2WAIT (0x1U << SPIx_CR1_WAIT_Pos)
9SPIx_CR1_WAIT_3WAIT (0x2U << SPIx_CR1_WAIT_Pos)
:SPIx_CR1_WAIT_4WAIT (0x3U << SPIx_CR1_WAIT_Pos)
<SPIx_CR1_BAUD_Pos 3
=SPIx_CR1_BAUD_Msk (0x7U << SPIx_CR1_BAUD_Pos)
>SPIx_CR1_BAUD_DIV2 (0x0U << SPIx_CR1_BAUD_Pos)
?SPIx_CR1_BAUD_DIV4 (0x1U << SPIx_CR1_BAUD_Pos)
@SPIx_CR1_BAUD_DIV8 (0x2U << SPIx_CR1_BAUD_Pos)
ASPIx_CR1_BAUD_DIV16 (0x3U << SPIx_CR1_BAUD_Pos)
BSPIx_CR1_BAUD_DIV32 (0x4U << SPIx_CR1_BAUD_Pos)
CSPIx_CR1_BAUD_DIV64 (0x5U << SPIx_CR1_BAUD_Pos)
DSPIx_CR1_BAUD_DIV128 (0x6U << SPIx_CR1_BAUD_Pos)
ESPIx_CR1_BAUD_DIV256 (0x7U << SPIx_CR1_BAUD_Pos)
GSPIx_CR1_LSBF_Pos 2
HSPIx_CR1_LSBF_Msk (0x1U << SPIx_CR1_LSBF_Pos)
ISPIx_CR1_LSBF_MSB (0x0U << SPIx_CR1_LSBF_Pos)
JSPIx_CR1_LSBF_LSB (0x1U << SPIx_CR1_LSBF_Pos)
LSPIx_CR1_CPHOL_Pos 1
MSPIx_CR1_CPHOL_Msk (0x1U << SPIx_CR1_CPHOL_Pos)
NSPIx_CR1_CPHOL_LOW (0x0U << SPIx_CR1_CPHOL_Pos)
OSPIx_CR1_CPHOL_HIGH (0x1U << SPIx_CR1_CPHOL_Pos)
QSPIx_CR1_CPHA_Pos 0
RSPIx_CR1_CPHA_Msk (0x1U << SPIx_CR1_CPHA_Pos)
SSPIx_CR1_CPHA_1CLOCK (0x0U << SPIx_CR1_CPHA_Pos)
TSPIx_CR1_CPHA_2CLOCK (0x1U << SPIx_CR1_CPHA_Pos)
VSPIx_CR2_DUMMY_EN_Pos 15
ZSPIx_CR2_DUMMY_EN_Msk (0x1U << SPIx_CR2_DUMMY_EN_Pos)
^SPIx_CR2_RXO_Pos 11
aSPIx_CR2_RXO_Msk (0x1U << SPIx_CR2_RXO_Pos)
eSPIx_CR2_DLEN_Pos 9
jSPIx_CR2_DLEN_Msk (0x3U << SPIx_CR2_DLEN_Pos)
kSPIx_CR2_DLEN_8BIT (0x0U << SPIx_CR2_DLEN_Pos)
lSPIx_CR2_DLEN_16BIT (0x1U << SPIx_CR2_DLEN_Pos)
mSPIx_CR2_DLEN_24BIT (0x2U << SPIx_CR2_DLEN_Pos)
nSPIx_CR2_DLEN_32BIT (0x3U << SPIx_CR2_DLEN_Pos)
pSPIx_CR2_HALFDUPLEX_Pos 8
sSPIx_CR2_HALFDUPLEX_Msk (0x1U << SPIx_CR2_HALFDUPLEX_Pos)
tSPIx_CR2_HALFDUPLEX_SPI (0x0U << SPIx_CR2_HALFDUPLEX_Pos)
uSPIx_CR2_HALFDUPLEX_DCN (0x1U << SPIx_CR2_HALFDUPLEX_Pos)
wSPIx_CR2_HD_RW_Pos 7
zSPIx_CR2_HD_RW_Msk (0x1U << SPIx_CR2_HD_RW_Pos)
{SPIx_CR2_HD_RW_WRITE (0x0U << SPIx_CR2_HD_RW_Pos)
|SPIx_CR2_HD_RW_READ (0x1U << SPIx_CR2_HD_RW_Pos)
~SPIx_CR2_CMD8b_Pos 6

SPIx_CR2_CMD8b_Msk (0x1U << SPIx_CR2_CMD8b_Pos)
‚
SPIx_CR2_CMD8b_8BIT (0x1U << SPIx_CR2_CMD8b_Pos)
ƒ
SPIx_CR2_CMD8b_DLEN (0x0U << SPIx_CR2_CMD8b_Pos)
…
SPIx_CR2_SSNM_Pos 5
ˆ
SPIx_CR2_SSNM_Msk (0x1U << SPIx_CR2_SSNM_Pos)
‰
SPIx_CR2_SSNM_HIGH (0x1U << SPIx_CR2_SSNM_Pos)
Š
SPIx_CR2_SSNM_LOW (0x0U << SPIx_CR2_SSNM_Pos)
Œ
SPIx_CR2_TXO_AC_Pos 4

SPIx_CR2_TXO_AC_Msk (0x1U << SPIx_CR2_TXO_AC_Pos)

SPIx_CR2_TXO_Pos 3
’
SPIx_CR2_TXO_Msk (0x1U << SPIx_CR2_TXO_Pos)
–
SPIx_CR2_SSN_Pos 2
˜
SPIx_CR2_SSN_Msk (0x1U << SPIx_CR2_SSN_Pos)
™
SPIx_CR2_SSN_LOW (0x0U << SPIx_CR2_SSN_Pos)
š
SPIx_CR2_SSN_HIGH (0x1U << SPIx_CR2_SSN_Pos)
œ
SPIx_CR2_SSNSEN_Pos 1
Ÿ
SPIx_CR2_SSNSEN_Msk (0x1U << SPIx_CR2_SSNSEN_Pos)
£
SPIx_CR2_SPIEN_Pos 0
¤
SPIx_CR2_SPIEN_Msk (0x1U << SPIx_CR2_SPIEN_Pos)
¦
SPIx_CR3_TXBFC_Pos 3
§
SPIx_CR3_TXBFC_Msk (0x1U << SPIx_CR3_TXBFC_Pos)
©
SPIx_CR3_RXBFC_Pos 2
ª
SPIx_CR3_RXBFC_Msk (0x1U << SPIx_CR3_RXBFC_Pos)
¬
SPIx_CR3_MERRC_Pos 1
­
SPIx_CR3_MERRC_Msk (0x1U << SPIx_CR3_MERRC_Pos)
¯
SPIx_CR3_SERRC_Pos 0
°
SPIx_CR3_SERRC_Msk (0x1U << SPIx_CR3_SERRC_Pos)
²
SPIx_IER_ERRIE_Pos 2
³
SPIx_IER_ERRIE_Msk (0x1U << SPIx_IER_ERRIE_Pos)
µ
SPIx_IER_TXIE_Pos 1
¶
SPIx_IER_TXIE_Msk (0x1U << SPIx_IER_TXIE_Pos)
¸
SPIx_IER_RXIE_Pos 0
¹
SPIx_IER_RXIE_Msk (0x1U << SPIx_IER_RXIE_Pos)
»
SPIx_ISR_DCN_TX_Pos 12
¿
SPIx_ISR_DCN_TX_Msk (0x1U << SPIx_ISR_DCN_TX_Pos)
À
SPIx_ISR_DCN_TX_COMMAND (0x0U << SPIx_ISR_DCN_TX_Pos)
Á
SPIx_ISR_DCN_TX_DATA (0x1U << SPIx_ISR_DCN_TX_Pos)
Ã
SPIx_ISR_RXCOL_Pos 10
Ä
SPIx_ISR_RXCOL_Msk (0x1U << SPIx_ISR_RXCOL_Pos)
Æ
SPIx_ISR_TXCOL_Pos 9
Ç
SPIx_ISR_TXCOL_Msk (0x1U << SPIx_ISR_TXCOL_Pos)
É
SPIx_ISR_BUSY_Pos 8
Ì
SPIx_ISR_BUSY_Msk (0x1U << SPIx_ISR_BUSY_Pos)
Î
SPIx_ISR_MERR_Pos 6
Ð
SPIx_ISR_MERR_Msk (0x1U << SPIx_ISR_MERR_Pos)
Ò
SPIx_ISR_SERR_Pos 5
Ô
SPIx_ISR_SERR_Msk (0x1U << SPIx_ISR_SERR_Pos)
Ö
SPIx_ISR_TXBE_Pos 1
Ù
SPIx_ISR_TXBE_Msk (0x1U << SPIx_ISR_TXBE_Pos)
Û
SPIx_ISR_RXBF_Pos 0
Þ
SPIx_ISR_RXBF_Msk (0x1U << SPIx_ISR_RXBF_Pos)
à
SPIx_TXBUF_TXBUF_Pos 0
á
SPIx_TXBUF_TXBUF_Msk (0xffffffffU << SPIx_TXBUF_TXBUF_Pos)
ã
SPIx_RXBUF_RXBUF_Pos 0
ä
SPIx_RXBUF_RXBUF_Msk (0xffffffffU << SPIx_RXBUF_RXBUF_Pos)`T
 




..\Drivers\..\Core\Include\fm33a0xxev_spi.h
FM33A0XXEV.h

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..\Drivers\fm33a0xxev_spi.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM
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__FM33A0XXEV_RMU_H 
RMU_PDRCR_PDRCFG_Pos 1
RMU_PDRCR_PDRCFG_Msk (0x3U << RMU_PDRCR_PDRCFG_Pos)
RMU_PDRCR_PDRCFG_1P5V (0x0U << RMU_PDRCR_PDRCFG_Pos)
RMU_PDRCR_PDRCFG_1P25V (0x1U << RMU_PDRCR_PDRCFG_Pos)
RMU_PDRCR_PDRCFG_1P35V (0x2U << RMU_PDRCR_PDRCFG_Pos)
RMU_PDRCR_PDRCFG_1P4V (0x3U << RMU_PDRCR_PDRCFG_Pos)
 RMU_PDRCR_PDREN_Pos 0
!RMU_PDRCR_PDREN_Msk (0x1U << RMU_PDRCR_PDREN_Pos)
%RMU_BORCR_BOR_PDRCFG_Pos 1
&RMU_BORCR_BOR_PDRCFG_Msk (0x3U << RMU_BORCR_BOR_PDRCFG_Pos)
'RMU_BORCR_BOR_PDRCFG_1P7V (0x0U << RMU_BORCR_BOR_PDRCFG_Pos)
(RMU_BORCR_BOR_PDRCFG_1P6V (0x1U << RMU_BORCR_BOR_PDRCFG_Pos)
)RMU_BORCR_BOR_PDRCFG_1P65V (0x2U << RMU_BORCR_BOR_PDRCFG_Pos)
*RMU_BORCR_BOR_PDRCFG_1P75V (0x3U << RMU_BORCR_BOR_PDRCFG_Pos)
,RMU_BORCR_OFF_BOR_Pos 0
-RMU_BORCR_OFF_BOR_Msk (0x1U << RMU_BORCR_OFF_BOR_Pos)
1RMU_RSTCFGR_LKUPRST_EN_Pos 1
2RMU_RSTCFGR_LKUPRST_EN_Msk (0x1U << RMU_RSTCFGR_LKUPRST_EN_Pos)
6RMU_SOFTRST_SOFTRST_Pos 0
7RMU_SOFTRST_SOFTRST_Msk (0xffffffffU << RMU_SOFTRST_SOFTRST_Pos)
9RMU_RSR_NRSTN_FLAG_Pos 11
:RMU_RSR_NRSTN_FLAG_Msk (0x1U << RMU_RSR_NRSTN_FLAG_Pos)
<RMU_RSR_TESTN_FLAG_Pos 10
=RMU_RSR_TESTN_FLAG_Msk (0x1U << RMU_RSR_TESTN_FLAG_Pos)
?RMU_RSR_PORN_FLAG_Pos 9
@RMU_RSR_PORN_FLAG_Msk (0x1U << RMU_RSR_PORN_FLAG_Pos)
BRMU_RSR_PDRN_FLAG_Pos 8
CRMU_RSR_PDRN_FLAG_Msk (0x1U << RMU_RSR_PDRN_FLAG_Pos)
ERMU_RSR_SOFTN_FLAG_Pos 5
FRMU_RSR_SOFTN_FLAG_Msk (0x1U << RMU_RSR_SOFTN_FLAG_Pos)
HRMU_RSR_IWDTN_FLAG_Pos 4
IRMU_RSR_IWDTN_FLAG_Msk (0x1U << RMU_RSR_IWDTN_FLAG_Pos)
KRMU_RSR_WWDTN_FLAG_Pos 2
LRMU_RSR_WWDTN_FLAG_Msk (0x1U << RMU_RSR_WWDTN_FLAG_Pos)
NRMU_RSR_LKUPN_FLAG_Pos 1
ORMU_RSR_LKUPN_FLAG_Msk (0x1U << RMU_RSR_LKUPN_FLAG_Pos)
QRMU_RSR_NVICN_FLAG_Pos 0
RRMU_RSR_NVICN_FLAG_Msk (0x1U << RMU_RSR_NVICN_FLAG_Pos)
TRMU_PRSTEN_PERHRSTEN_Pos 0
URMU_PRSTEN_PERHRSTEN_Msk (0xffffffffU << RMU_PRSTEN_PERHRSTEN_Pos)
WRMU_AHBRST_HASHRST_Pos 2
XRMU_AHBRST_HASHRST_Msk (0x1U << RMU_AHBRST_HASHRST_Pos)
\RMU_AHBRST_PAERST_Pos 1
]RMU_AHBRST_PAERST_Msk (0x1U << RMU_AHBRST_PAERST_Pos)
aRMU_AHBRST_DMARST_Pos 0
bRMU_AHBRST_DMARST_Msk (0x1U << RMU_AHBRST_DMARST_Pos)
fRMU_APBRST1_UART5RST_Pos 31
gRMU_APBRST1_UART5RST_Msk (0x1U << RMU_APBRST1_UART5RST_Pos)
kRMU_APBRST1_UART4RST_Pos 30
lRMU_APBRST1_UART4RST_Msk (0x1U << RMU_APBRST1_UART4RST_Pos)
pRMU_APBRST1_UART3RST_Pos 29
qRMU_APBRST1_UART3RST_Msk (0x1U << RMU_APBRST1_UART3RST_Pos)
uRMU_APBRST1_UART2RST_Pos 28
vRMU_APBRST1_UART2RST_Msk (0x1U << RMU_APBRST1_UART2RST_Pos)
zRMU_APBRST1_TIMARST_Pos 23
{RMU_APBRST1_TIMARST_Msk (0x1U << RMU_APBRST1_TIMARST_Pos)
RMU_APBRST1_LCDRST_Pos 16
€
RMU_APBRST1_LCDRST_Msk (0x1U << RMU_APBRST1_LCDRST_Pos)
„
RMU_APBRST1_U7816RST_Pos 14
…
RMU_APBRST1_U7816RST_Msk (0x1U << RMU_APBRST1_U7816RST_Pos)
‰
RMU_APBRST1_SPI4RST_Pos 12
Š
RMU_APBRST1_SPI4RST_Msk (0x1U << RMU_APBRST1_SPI4RST_Pos)
Ž
RMU_APBRST1_SPI3RST_Pos 11

RMU_APBRST1_SPI3RST_Msk (0x1U << RMU_APBRST1_SPI3RST_Pos)
“
RMU_APBRST1_SPI2RST_Pos 10
”
RMU_APBRST1_SPI2RST_Msk (0x1U << RMU_APBRST1_SPI2RST_Pos)
˜
RMU_APBRST1_LPUART0RST_Pos 6
™
RMU_APBRST1_LPUART0RST_Msk (0x1U << RMU_APBRST1_LPUART0RST_Pos)

RMU_APBRST1_I2C1RST_Pos 3
ž
RMU_APBRST1_I2C1RST_Msk (0x1U << RMU_APBRST1_I2C1RST_Pos)
¢
RMU_APBRST1_LPTRST_Pos 0
£
RMU_APBRST1_LPTRST_Msk (0x1U << RMU_APBRST1_LPTRST_Pos)
§
RMU_APBRST2_UART1RST_Pos 31
¨
RMU_APBRST2_UART1RST_Msk (0x1U << RMU_APBRST2_UART1RST_Pos)
¬
RMU_APBRST2_UART0RST_Pos 30
­
RMU_APBRST2_UART0RST_Msk (0x1U << RMU_APBRST2_UART0RST_Pos)
±
RMU_APBRST2_UARTIRRST_Pos 29
²
RMU_APBRST2_UARTIRRST_Msk (0x1U << RMU_APBRST2_UARTIRRST_Pos)
¶
RMU_APBRST2_BSTRST_Pos 28
·
RMU_APBRST2_BSTRST_Msk (0x1U << RMU_APBRST2_BSTRST_Pos)
»
RMU_APBRST2_CICRST_Pos 24
¼
RMU_APBRST2_CICRST_Msk (0x1U << RMU_APBRST2_CICRST_Pos)
À
RMU_APBRST2_ADCRST_Pos 23
Á
RMU_APBRST2_ADCRST_Msk (0x1U << RMU_APBRST2_ADCRST_Pos)
Å
RMU_APBRST2_AESRST_Pos 18
Æ
RMU_APBRST2_AESRST_Msk (0x1U << RMU_APBRST2_AESRST_Pos)
Ê
RMU_APBRST2_CRCRST_Pos 17
Ë
RMU_APBRST2_CRCRST_Msk (0x1U << RMU_APBRST2_CRCRST_Pos)
Ï
RMU_APBRST2_RNGRST_Pos 16
Ð
RMU_APBRST2_RNGRST_Msk (0x1U << RMU_APBRST2_RNGRST_Pos)
Ô
RMU_APBRST2_SPI1RST_Pos 9
Õ
RMU_APBRST2_SPI1RST_Msk (0x1U << RMU_APBRST2_SPI1RST_Pos)
Ù
RMU_APBRST2_SPI0RST_Pos 8
Ú
RMU_APBRST2_SPI0RST_Msk (0x1U << RMU_APBRST2_SPI0RST_Pos)
Þ
RMU_APBRST2_LPUART1RST_Pos 7
ß
RMU_APBRST2_LPUART1RST_Msk (0x1U << RMU_APBRST2_LPUART1RST_Pos)
ã
RMU_APBRST2_I2C0RST_Pos 4
ä
RMU_APBRST2_I2C0RST_Msk (0x1U << RMU_APBRST2_I2C0RST_Pos)
è
RMU_APBRST2_SVDRST_Pos 1
é
RMU_APBRST2_SVDRST_Msk (0x1U << RMU_APBRST2_SVDRST_Pos)
í
RMU_APBRST2_COMPRST_Pos 0
î
RMU_APBRST2_COMPRST_Msk (0x1U << RMU_APBRST2_COMPRST_Pos)`T
 




..\Drivers\..\Core\Include\fm33a0xxev_rmu.h
FM33A0XXEV.h

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..\Drivers\fm33a0xxev_rmu.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM
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..\Drivers\..\Drivers\fm33a0xxev_spi.cfm33a0xxev_spi.h
fm33a0xxev_rmu.h


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%Component: ARM Compiler 5.06 update 6 (build 750) Tool: armlink [4d35ed]armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=9931,9931,6642 --cpu=Cortex-M0 --fpu=SoftVFP --output=.\objects\fm33a0xxev_spi.o --vfemode=force
Input Comments:p10b8-3Component: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]armasm --debug --diag_suppress=9931,9931,1602,1073 --cpu=Cortex-M0 --fpu=SoftVFP --apcs=/interwork/interwork --no_divide fm33a0xxev_spi.oComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]ArmCC --c99 --split_sections --debug -c --gnu -o.\objects\fm33a0xxev_spi.o --depend=.\objects\fm33a0xxev_spi.d --cpu=Cortex-M0 --apcs=interwork -O0 --diag_suppress=9931 -I..\Core -I..\Drivers -I..\Core\Include -I..\Hardware -I.\RTE\Device -I..\Hardware\CLOCK -I..\Hardware\DELAY -I..\Hardware\GPIO -I..\Hardware\UART -I..\Hardware\TIM -I..\Function\KEY -I..\Hardware\EXTI -I..\Hardware\RTC -I..\Hardware\ADC -I..\Hardware\I2C -I..\Function\LCD -I..\Function\EXTERN_RTC -I..\Hardware\SPI -I..\Function\GPRS -I..\Function\HARDWARE_WATCHDOG -I..\Function\IR_NEC -I..\Function\MEASURE_INTERACTION -I..\Function\POWER_MANAGE -I..\Function\STORAGE -I..\Function\UPPER_COMPUTER -I..\Function\VALVE -I..\Soft -I..\MultiButton -I..\USMART -I..\Hardware\DMA -I..\Hardware\ON_CHIP_FLASH -I..\Hardware\SVD -I..\Function\OFF_CHIP_FLASH -I..\Hardware\CRC -I..\Function\BOOTLOADER_IAP -I..\Hardware\COMP -I..\Function\E2P -I..\CmBackTrace -I..\Pre_Drivers -I..\Pre_Drivers -I..\Function\PROJECT_TETS -I.\RTE\_UFG220_FM33A0_MainSystem -ID:\Keil5\ARM\PACK\ARM\CMSIS\5.3.0\CMSIS\Include -ID:\Keil5\ARM\PACK\Keil\FM33A0XXEV_DFP\0.0.4\Device\Include -D__MICROLIB -D__UVISION_VERSION=525 -D_RTE_ -D__VTOR_PRESENT --omf_browse=.\objects\fm33a0xxev_spi.crf ..\Drivers\fm33a0xxev_spi.cñ6
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A.ARM.attributes.strtab.shstrtab.rel.debug_pubnames.rel.debug_frame.rel.debug_line.rel.debug_info.reli.SPIx_Deinit.reli.SPI_SSN_Set_Low.reli.SPI_SSN_Set_High.reli.SPI_RW_Byte.symtab.comment.arm_vfe_header__ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000__ARM_grp.fm33a0xxev_spi.c.2_kU3000_JJRhKC6QzTd_c00000__ARM_grp.fm33a0xxev_rmu.h.2_4L2000_C$q$9vNhOp0_300000__ARM_grp.fm33a0xxev_spi.h.2_AU2000_7eFMvsSXzw0_300000__ARM_grp.system_FM33A0XXEV.h.2_iK2000_$xx4mkEXI33_f00000__ARM_grp.FM33A0XXEV.h.2_YT4000_XZU28XPoz9f_800000__ARM_grp.stdio.h.2_8r8000_YQYCeoSc1N0_x00000__ARM_grp.core_cm0plus.h.2_ko7000_oz_SgrIf9Ea_W00000__ARM_grp.core_cmfunc.h.2_0o1000_LxrOLndRPv6_z00000__ARM_grp.core_cminstr.h.2_cq1000_pIFywSNOsOf_b00000__ARM_grp.stdint.h.2_MG1000_W2MyGZvI3s6_300000.debug_abbrev__ARM_asm.debug_abbrev.1.debug_macinfo.debug_loci.SPIx_TXBUF_Writei.SPIx_RXBUF_Readi.SPIx_ISR_TXCOL_Clri.SPIx_ISR_TXCOL_Chki.SPIx_ISR_TXBE_Chki.SPIx_ISR_SERR_Chki.SPIx_ISR_RXCOL_Clri.SPIx_ISR_RXCOL_Chki.SPIx_ISR_RXBF_Chki.SPIx_ISR_MERR_Chki.SPIx_ISR_DCN_TX_Seti.SPIx_ISR_DCN_TX_Geti.SPIx_ISR_BUSY_Chki.SPIx_IER_TXIE_Setablei.SPIx_IER_TXIE_Getablei.SPIx_IER_RXIE_Setablei.SPIx_IER_RXIE_Getablei.SPIx_IER_ERRIE_Setablei.SPIx_IER_ERRIE_Getablei.SPIx_CR3_TXBFC_Clri.SPIx_CR3_SERRC_Clri.SPIx_CR3_RXBFC_Clri.SPIx_CR3_MERRC_Clri.SPIx_CR2_TXO_Setablei.SPIx_CR2_TXO_Getablei.SPIx_CR2_TXO_AC_Setablei.SPIx_CR2_TXO_AC_Getablei.SPIx_CR2_SSN_Seti.SPIx_CR2_SSN_Geti.SPIx_CR2_SSNSEN_Setablei.SPIx_CR2_SSNSEN_Getablei.SPIx_CR2_SSNM_Seti.SPIx_CR2_SSNM_Geti.SPIx_CR2_SPIEN_Setablei.SPIx_CR2_SPIEN_Getablei.SPIx_CR2_RXO_Setablei.SPIx_CR2_RXO_Getablei.SPIx_CR2_HD_RW_Seti.SPIx_CR2_HD_RW_Geti.SPIx_CR2_HALFDUPLEX_Seti.SPIx_CR2_HALFDUPLEX_Geti.SPIx_CR2_DUMMY_EN_Setablei.SPIx_CR2_DUMMY_EN_Getablei.SPIx_CR2_DLEN_Seti.SPIx_CR2_DLEN_Geti.SPIx_CR2_CMD8b_Seti.SPIx_CR2_CMD8b_Geti.SPIx_CR1_WAIT_Seti.SPIx_CR1_WAIT_Geti.SPIx_CR1_SSPA_Seti.SPIx_CR1_SSPA_Geti.SPIx_CR1_MSPA_Seti.SPIx_CR1_MSPA_Geti.SPIx_CR1_MM_Seti.SPIx_CR1_MM_Geti.SPIx_CR1_LSBF_Seti.SPIx_CR1_LSBF_Geti.SPIx_CR1_IOSWAP_Seti.SPIx_CR1_IOSWAP_Geti.SPIx_CR1_CPHOL_Seti.SPIx_CR1_CPHOL_Geti.SPIx_CR1_CPHA_Seti.SPIx_CR1_CPHA_Geti.SPIx_CR1_BAUD_Seti.SPIx_CR1_BAUD_Get.revsh_text.rev16_textLib$$Request$$armlibRMU_PRSTEN_WriteRMU_APBRST2_SPI1RST_SetableRMU_APBRST2_SPI0RST_SetableRMU_APBRST1_SPI4RST_SetableRMU_APBRST1_SPI3RST_SetableRMU_APBRST1_SPI2RST_Setable__ARM_grp..debug_pubnames$system_FM33A0XXEV.h$.2_iK2000_$xx4mkEXI33_f00000__ARM_grp..debug_pubnames$stdio.h$.2_8r8000_YQYCeoSc1N0_x00000__ARM_grp..debug_macinfo$system_FM33A0XXEV.h$.2_iK2000_$xx4mkEXI33_f00000__ARM_grp..debug_macinfo$stdio.h$.2_8r8000_YQYCeoSc1N0_x00000__ARM_grp..debug_macinfo$stdint.h$.2_MG1000_W2MyGZvI3s6_300000__ARM_grp..debug_macinfo$fm33a0xxev_spi.h$.2_AU2000_7eFMvsSXzw0_300000__ARM_grp..debug_macinfo$fm33a0xxev_spi.c$.2_kU3000_JJRhKC6QzTd_c00000__ARM_grp..debug_macinfo$fm33a0xxev_rmu.h$.2_4L2000_C$q$9vNhOp0_300000__ARM_grp..debug_macinfo$core_cminstr.h$.2_cq1000_pIFywSNOsOf_b00000__ARM_grp..debug_macinfo$core_cmfunc.h$.2_0o1000_LxrOLndRPv6_z00000__ARM_grp..debug_macinfo$core_cm0plus.h$.2_ko7000_oz_SgrIf9Ea_W00000__ARM_grp..debug_macinfo$FM33A0XXEV.h$.2_YT4000_XZU28XPoz9f_800000__ARM_grp..debug_line$system_FM33A0XXEV.h$.2_iK2000_$xx4mkEXI33_f00000__ARM_grp..debug_line$stdio.h$.2_8r8000_YQYCeoSc1N0_x00000__ARM_grp..debug_line$stdint.h$.2_MG1000_W2MyGZvI3s6_300000__ARM_grp..debug_line$fm33a0xxev_spi.h$.2_AU2000_7eFMvsSXzw0_300000__ARM_grp..debug_line$fm33a0xxev_spi.c$.2_kU3000_JJRhKC6QzTd_c00000__ARM_grp..debug_line$fm33a0xxev_rmu.h$.2_4L2000_C$q$9vNhOp0_300000__ARM_grp..debug_line$core_cminstr.h$.2_cq1000_pIFywSNOsOf_b00000__ARM_grp..debug_line$core_cmfunc.h$.2_0o1000_LxrOLndRPv6_z00000__ARM_grp..debug_line$core_cm0plus.h$.2_ko7000_oz_SgrIf9Ea_W00000__ARM_grp..debug_line$FM33A0XXEV.h$.2_YT4000_XZU28XPoz9f_800000__ARM_grp.system_FM33A0XXEV.h.2_iK2000_$xx4mkEXI33_f00000__ARM_grp.stdio.h.2_8r8000_YQYCeoSc1N0_x00000__ARM_grp.stdint.h.2_MG1000_W2MyGZvI3s6_300000__ARM_grp.fm33a0xxev_spi.h.2_AU2000_7eFMvsSXzw0_300000__ARM_grp.fm33a0xxev_spi.c.2_kU3000_JJRhKC6QzTd_c00000__ARM_grp.fm33a0xxev_rmu.h.2_4L2000_C$q$9vNhOp0_300000__ARM_grp.core_cminstr.h.2_cq1000_pIFywSNOsOf_b00000__ARM_grp.core_cmfunc.h.2_0o1000_LxrOLndRPv6_z00000__ARM_grp.core_cm0plus.h.2_ko7000_oz_SgrIf9Ea_W00000__ARM_grp.FM33A0XXEV.h.2_YT4000_XZU28XPoz9f_800000__ARM_grp..debug_info$system_FM33A0XXEV.h$.2_iK2000_$xx4mkEXI33_f00000__ARM_grp..debug_info$stdio.h$.2_8r8000_YQYCeoSc1N0_x00000__ARM_grp..debug_info$stdint.h$.2_MG1000_W2MyGZvI3s6_300000__ARM_grp..debug_info$fm33a0xxev_spi.h$.2_AU2000_7eFMvsSXzw0_300000__ARM_grp..debug_info$fm33a0xxev_spi.c$.2_kU3000_JJRhKC6QzTd_c00000__ARM_grp..debug_info$fm33a0xxev_rmu.h$.2_4L2000_C$q$9vNhOp0_300000__ARM_grp..debug_info$core_cminstr.h$.2_cq1000_pIFywSNOsOf_b00000__ARM_grp..debug_info$core_cmfunc.h$.2_0o1000_LxrOLndRPv6_z00000__ARM_grp..debug_info$core_cm0plus.h$.2_ko7000_oz_SgrIf9Ea_W00000__ARM_grp..debug_info$FM33A0XXEV.h$.2_YT4000_XZU28XPoz9f_800000__ARM_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N_Getablei.SPIx_CR2_DLEN_Seti.SPIx_CR2_DLEN_Geti.SPIx_CR2_CMD8b_Seti.SPIx_CR2_CMD8b_Geti.SPIx_CR1_WAIT_Seti.SPIx_CR1_WAIT_Geti.SPIx_CR1_SSPA_Seti.SPIx_CR1_SSPA_Geti.SPIx_CR1_MSPA_Seti.SPIx_CR1_MSPA_Geti.SPIx_CR1_MM_Seti.SPIx_CR1_MM_Geti.SPIx_CR1_LSBF_Seti.SPIx_CR1_LSBF_Geti.SPIx_CR1_IOSWAP_Seti.SPIx_CR1_IOSWAP_Geti.SPIx_CR1_CPHOL_Seti.SPIx_CR1_CPHOL_Geti.SPIx_CR1_CPHA_Seti.SPIx_CR1_CPHA_Geti.SPIx_CR1_BAUD_Seti.SPIx_CR1_BAUD_Geti.SPI_SSN_Set_Lowi.SPI_SSN_Set_HighBuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$~SHL$OSPACE$EBA8$REQ8$PRES8$EABIv2i.SPI_RW_ByteBuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$~SHL$OSPACE$EBA8$PRES8$EABIv2..\Drivers\fm33a0xxev_spi.c.revsh_text.rev16_text..\\Drivers\\fm33a0xxev_spi.c$d.realdata$d$tA‹aeabi
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