add lower model test

wujiazhi

2024-06-13 72def895431ad7a08e635b11f3da738e2b2c4618

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..\Drivers\fm33a0xxev_lcd.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM ?‚
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..\Drivers\fm33a0xxev_lcd.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM>ˆ
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..\Drivers\fm33a0xxev_lcd.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM>‹
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__DATE__ "Jun 13 2024"
__TIME__ "10:36:15"
__STDC__ 1
__STDC_VERSION__ 199901L
__STDC_HOSTED__ 1
__STDC_ISO_10646__ 200607
__EDG__ 1
__EDG_VERSION__ 407
__EDG_SIZE_TYPE__ unsigned int
__EDG_PTRDIFF_TYPE__ int
__GNUC__ 4
__GNUC_STDC_INLINE__ 1
__GNUC_MINOR__ 7
__GNUC_PATCHLEVEL__ 0
__VERSION__ "4.7 (EDG gcc mode)"
__CHAR16_TYPE__ unsigned short
__CHAR32_TYPE__ unsigned int
__USER_LABEL_PREFIX__ 
__CHAR_UNSIGNED__ 1
__WCHAR_UNSIGNED__ 1
__SIZE_TYPE__ unsigned int
__PTRDIFF_TYPE__ int
__WCHAR_TYPE__ unsigned short
__WINT_TYPE__ unsigned short
__INTMAX_TYPE__ long long
__UINTMAX_TYPE__ unsigned long long
__sizeof_int 4
__sizeof_long 4
__sizeof_ptr 4
__ARMCC_VERSION 5060750
__TARGET_CPU_CORTEX_M0 1
__TARGET_FPU_SOFTVFP 1
__TARGET_FPU_SOFTVFP 1
__MICROLIB 1
__UVISION_VERSION 525
_RTE_ 1
__VTOR_PRESENT 1
__CC_ARM 1
__arm 1
__arm__ 1
__TARGET_ARCH_6S_M 1
__TARGET_ARCH_ARM 0
__TARGET_ARCH_THUMB 3
__TARGET_ARCH_A64 0
__TARGET_ARCH_AARCH32 1
__TARGET_PROFILE_M 1
__TARGET_FEATURE_HALFWORD 1
__TARGET_FEATURE_THUMB 1
__TARGET_FEATURE_DMB 1
__TARGET_FEATURE_EXTENSION_REGISTER_COUNT 0
__APCS_INTERWORK 1
__thumb 1
__thumb__ 1
__t32__ 1
__OPTIMISE_SPACE 1
__OPTIMIZE_SIZE__ 1
__OPTIMISE_LEVEL 0
__SOFTFP__ 1
#
ÁLCD_CR_SCSEL_Set#
ÁLCD_CR_SCSEL_Get%
ÁLCD_CR_SC_CTRL_Set%
ÁLCD_CR_SC_CTRL_Get%
ÁLCD_CR_IC_CTRL_Set%
ÁLCD_CR_IC_CTRL_Get$
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ÁLCD_CR_ANTIPOLAR_Get!
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ÁLCD_TEST_TESTEN_Setable*
ÁLCD_TEST_TESTEN_Getable üÁLCD_FCR_Write
ÁLCD_FCR_Read$
ÁLCD_FLKT_TOFF_Set$
ÁLCD_FLKT_TOFF_Get#
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ÁLCD_IER_DONIE_Setable(
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ÁLCD_BSTCR_BUF_OFF_Setable,
ÁLCD_BSTCR_BUF_OFF_Getable+
ÁLCD_BSTCR_BUFBYP_Setable+
ÁLCD_BSTCR_BUFBYP_Getable+
ÁLCD_BSTCR_VLCDPD_Setable+
ÁLCD_BSTCR_VLCDPD_Getable(
ÁLCD_BSTCR_VLCDCFG_Set(
ÁLCD_BSTCR_VLCDCFG_Get.
ÁLCD_BSTCR_BOOST_TEN_Setable.
ÁLCD_BSTCR_BOOST_TEN_Getable-
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ÁLCD_BSTCR_BOOST_EN_Getable#üÁLCD_COM_EN_Write"
ÁLCD_COM_EN_Read$
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INT_FAST16_MAX 2147483647
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INT_FAST32_MAX 2147483647
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INT_FAST64_MAX __INT64_C(9223372036854775807)
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UINT_FAST8_MAX 4294967295u
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UINT_FAST16_MAX 4294967295u
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PTRDIFF_MAX INT32_MAX
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signed charshortintlong long
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Y__regAPSRW

P;æ
t__get_xPSRW
a__resultW

Y__regXPSRW

P;¯
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__get_PSPW
a__resultW

Y__regProcessStackPointerW

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__set_PSP$W
topOfProcStackY__regProcessStackPointerW

P;¾
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__get_MSPW
a__resultW

Y__regMainStackPointerW

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__set_MSP$W
topOfMainStackY__regMainStackPointerW

P;Å
µ
__get_PRIMASKW
a__resultW

Y__regPriMaskW

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__set_PRIMASK$W
priMaskY__regPriMaskW

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 __CORE_CM0PLUS_H_GENERIC "
@__CM0PLUS_CMSIS_VERSION_MAIN ( 5U)
A__CM0PLUS_CMSIS_VERSION_SUB ( 0U)
B__CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | __CM0PLUS_CMSIS_VERSION_SUB )
E__CORTEX_M (0U)
Q__ASM __asm
R__INLINE __inline
S__STATIC_INLINE static __inline
T__NO_RETURN __declspec(noreturn)
U__USED __attribute__((used))
V__WEAK __attribute__((weak))
W__UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
Ÿ
__FPU_USED 0UÆ
Ç

Ò
__CORE_CM0PLUS_H_DEPENDANT 
ÿ
__I volatile const
__O volatile
‚__IO volatile
…__IM volatile const
†__OM volatile
‡__IOM volatile
³APSR_N_Pos 31U
´APSR_N_Msk (1UL << APSR_N_Pos)
¶APSR_Z_Pos 30U
·APSR_Z_Msk (1UL << APSR_Z_Pos)
¹APSR_C_Pos 29U
ºAPSR_C_Msk (1UL << APSR_C_Pos)
¼APSR_V_Pos 28U
½APSR_V_Msk (1UL << APSR_V_Pos)
ÎIPSR_ISR_Pos 0U
ÏIPSR_ISR_Msk (0x1FFUL )
æxPSR_N_Pos 31U
çxPSR_N_Msk (1UL << xPSR_N_Pos)
éxPSR_Z_Pos 30U
êxPSR_Z_Msk (1UL << xPSR_Z_Pos)
ìxPSR_C_Pos 29U
íxPSR_C_Msk (1UL << xPSR_C_Pos)
ïxPSR_V_Pos 28U
ðxPSR_V_Msk (1UL << xPSR_V_Pos)
òxPSR_T_Pos 24U
óxPSR_T_Msk (1UL << xPSR_T_Pos)
õxPSR_ISR_Pos 0U
öxPSR_ISR_Msk (0x1FFUL )
ˆCONTROL_SPSEL_Pos 1U
‰CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)
‹CONTROL_nPRIV_Pos 0U
ŒCONTROL_nPRIV_Msk (1UL )
ÈSCB_CPUID_IMPLEMENTER_Pos 24U
ÉSCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
ËSCB_CPUID_VARIANT_Pos 20U
ÌSCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
ÎSCB_CPUID_ARCHITECTURE_Pos 16U
ÏSCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
ÑSCB_CPUID_PARTNO_Pos 4U
ÒSCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
ÔSCB_CPUID_REVISION_Pos 0U
ÕSCB_CPUID_REVISION_Msk (0xFUL )
ØSCB_ICSR_NMIPENDSET_Pos 31U
ÙSCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)
ÛSCB_ICSR_PENDSVSET_Pos 28U
ÜSCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
ÞSCB_ICSR_PENDSVCLR_Pos 27U
ßSCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
áSCB_ICSR_PENDSTSET_Pos 26U
âSCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
äSCB_ICSR_PENDSTCLR_Pos 25U
åSCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
çSCB_ICSR_ISRPREEMPT_Pos 23U
èSCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
êSCB_ICSR_ISRPENDING_Pos 22U
ëSCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
íSCB_ICSR_VECTPENDING_Pos 12U
îSCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
ðSCB_ICSR_VECTACTIVE_Pos 0U
ñSCB_ICSR_VECTACTIVE_Msk (0x1FFUL )
õSCB_VTOR_TBLOFF_Pos 8U
öSCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)
úSCB_AIRCR_VECTKEY_Pos 16U
ûSCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
ýSCB_AIRCR_VECTKEYSTAT_Pos 16U
þSCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
€SCB_AIRCR_ENDIANESS_Pos 15U
SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
ƒSCB_AIRCR_SYSRESETREQ_Pos 2U
„SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
†SCB_AIRCR_VECTCLRACTIVE_Pos 1U
‡SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
ŠSCB_SCR_SEVONPEND_Pos 4U
‹SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
SCB_SCR_SLEEPDEEP_Pos 2U
ŽSCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
SCB_SCR_SLEEPONEXIT_Pos 1U
‘SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
”SCB_CCR_STKALIGN_Pos 9U
•SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)
—SCB_CCR_UNALIGN_TRP_Pos 3U
˜SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
›SCB_SHCSR_SVCALLPENDED_Pos 15U
œSCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
´SysTick_CTRL_COUNTFLAG_Pos 16U
µSysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
·SysTick_CTRL_CLKSOURCE_Pos 2U
¸SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
ºSysTick_CTRL_TICKINT_Pos 1U
»SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
½SysTick_CTRL_ENABLE_Pos 0U
¾SysTick_CTRL_ENABLE_Msk (1UL )
ÁSysTick_LOAD_RELOAD_Pos 0U
ÂSysTick_LOAD_RELOAD_Msk (0xFFFFFFUL )
ÅSysTick_VAL_CURRENT_Pos 0U
ÆSysTick_VAL_CURRENT_Msk (0xFFFFFFUL )
ÉSysTick_CALIB_NOREF_Pos 31U
ÊSysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)
ÌSysTick_CALIB_SKEW_Pos 30U
ÍSysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)
ÏSysTick_CALIB_TENMS_Pos 0U
ÐSysTick_CALIB_TENMS_Msk (0xFFFFFFUL )
éMPU_TYPE_IREGION_Pos 16U
êMPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
ìMPU_TYPE_DREGION_Pos 8U
íMPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
ïMPU_TYPE_SEPARATE_Pos 0U
ðMPU_TYPE_SEPARATE_Msk (1UL )
óMPU_CTRL_PRIVDEFENA_Pos 2U
ôMPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
öMPU_CTRL_HFNMIENA_Pos 1U
÷MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
ùMPU_CTRL_ENABLE_Pos 0U
úMPU_CTRL_ENABLE_Msk (1UL )
ýMPU_RNR_REGION_Pos 0U
þMPU_RNR_REGION_Msk (0xFFUL )
MPU_RBAR_ADDR_Pos 8U
‚MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)
„MPU_RBAR_VALID_Pos 4U
…MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos)
‡MPU_RBAR_REGION_Pos 0U
ˆMPU_RBAR_REGION_Msk (0xFUL )
‹MPU_RASR_ATTRS_Pos 16U
ŒMPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos)
ŽMPU_RASR_XN_Pos 28U
MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos)
‘MPU_RASR_AP_Pos 24U
’MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos)
”MPU_RASR_TEX_Pos 19U
•MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos)
—MPU_RASR_S_Pos 18U
˜MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos)
šMPU_RASR_C_Pos 17U
›MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos)
MPU_RASR_B_Pos 16U
žMPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos)
 MPU_RASR_SRD_Pos 8U
¡MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos)
£MPU_RASR_SIZE_Pos 1U
¤MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos)
¦MPU_RASR_ENABLE_Pos 0U
§MPU_RASR_ENABLE_Msk (1UL )
Ä_VAL2FLD(field,value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
Ì_FLD2VAL(field,value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
ÙSCS_BASE (0xE000E000UL)
ÚSysTick_BASE (SCS_BASE + 0x0010UL)
ÛNVIC_BASE (SCS_BASE + 0x0100UL)
ÜSCB_BASE (SCS_BASE + 0x0D00UL)
ÞSCB ((SCB_Type *) SCB_BASE )
ßSysTick ((SysTick_Type *) SysTick_BASE )
àNVIC ((NVIC_Type *) NVIC_BASE )
ãMPU_BASE (SCS_BASE + 0x0D90UL)
äMPU ((MPU_Type *) MPU_BASE )
‚_BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
ƒ_SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
„_IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )”ˆ
 




..\Core\Include\D:\Keil5\ARM\ARMCC\Bin\..\include\core_cm0plus.h
stdint.hcore_cminstr.h
core_cmfunc.h


°
..\Core\Include\core_cm0plus.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM*”!_reserved0W
#!VW
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NVIC_EnableIRQ$(IRQn<¶

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ÏNVIC_ClearPendingIRQ$(IRQn<ö
áNVIC_SetPriority$(IRQn$W
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ùNVIC_GetPriorityW
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__stdio_h 
__ARMCLIB_VERSION 5060037
"_ARMABI __declspec(__nothrow)
%__STDIO_DECLS '__CLIBNS
-__CLIBNS <NULL
=NULL 0
g_SYS_OPEN 16
¥
stdin (&__CLIBNS __stdin)
§
stdout (&__CLIBNS __stdout)
©
stderr (&__CLIBNS __stderr)
¬
_IOFBF 0x100
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_IOLBF 0x200
®
_IONBF 0x400
±
BUFSIZ (512)
³
FOPEN_MAX _SYS_OPEN
¹
FILENAME_MAX 256
¾
L_tmpnam FILENAME_MAX
Ä
TMP_MAX 256
Ì
EOF (-1)
Ò
SEEK_SET 0
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SEEK_CUR 1
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SEEK_END 2
Ú
_IOBIN 0x04
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__STDIN_BUFSIZ (64)
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__STDOUT_BUFSIZ (64)
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__STDERR_BUFSIZ (16)
¿getchar() getc(stdin)
àputchar(c) putc(c, stdout)LA
 




D:\Keil5\ARM\ARMCC\Bin\..\include\stdio.h


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D:\Keil5\ARM\ARMCC\Bin\..\include\stdio.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]unsigned intunsigned long longPsize_t‡
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$FM33A0XXEV_H 
.__RCHF_INITIAL_CLOCK (8000000)
/__RCMF_CLOCK (2000000)
0__RCLP_CLOCK (32000)
1__XTLF_CLOCK (32768)
n__CM0_REV 0x0100
o__MPU_PRESENT 1
p__VTOR_PRESENT 1
q__NVIC_PRIO_BITS 2
r__Vendor_SysTickConfig 0uv
¿FLASH_BASE (( uint32_t)0x00000000)
ÀSRAM_BASE (( uint32_t)0x20000000)
ÁPERIPH_BASE (( uint32_t)0x40000000)
ÊPMU_BASE (PERIPH_BASE +0x00002000)
ËDBG_BASE (PERIPH_BASE +0x00000000)
ÌFLS_BASE (PERIPH_BASE +0x00001000)
ÍRMU_BASE (PERIPH_BASE +0x00002800)
ÎIWDT_BASE (PERIPH_BASE +0x00011400)
ÏWWDT_BASE (PERIPH_BASE +0x00011800)
ÐCMU_BASE (PERIPH_BASE +0x00002400)
ÑCDIF_BASE (PERIPH_BASE +0x0001E000)
ÒVRTC_BASE (PERIPH_BASE +0x0001F800)
ÓSVD_BASE (PERIPH_BASE +0x00012800)
ÔAES_BASE (PERIPH_BASE +0x00013800)
ÕPAE_BASE (PERIPH_BASE +0x00001400)
ÖHASH_BASE (PERIPH_BASE +0x00001800)
×RNG_BASE (PERIPH_BASE +0x00013C00)
ØCOMP_BASE (PERIPH_BASE +0x00015400)
ÙI2C0_BASE (PERIPH_BASE +0x00012400)
ÚI2C1_BASE (PERIPH_BASE +0x00015000)
ÛUARTIR_BASE (PERIPH_BASE +0x00017C00)
ÜUART0_BASE (PERIPH_BASE +0x00012000)
ÝUART1_BASE (PERIPH_BASE +0x00016800)
ÞUART2_BASE (PERIPH_BASE +0x00016C00)
ßUART3_BASE (PERIPH_BASE +0x00017000)
àUART4_BASE (PERIPH_BASE +0x00017400)
áUART5_BASE (PERIPH_BASE +0x00017800)
âLPUART0_BASE (PERIPH_BASE +0x00014000)
ãLPUART1_BASE (PERIPH_BASE +0x00014400)
äSPI0_BASE (PERIPH_BASE +0x00010400)
åSPI1_BASE (PERIPH_BASE +0x00010800)
æSPI2_BASE (PERIPH_BASE +0x00014800)
çSPI3_BASE (PERIPH_BASE +0x00014C00)
èSPI4_BASE (PERIPH_BASE +0x00016400)
éU7816_BASE (PERIPH_BASE +0x00011C00)
êQSPI_BASE (PERIPH_BASE +0x00000800)
ëDMA_BASE (PERIPH_BASE +0x00000400)
ìCRC_BASE (PERIPH_BASE +0x00010000)
íBT1_BASE (PERIPH_BASE +0x00013000)
îBT2_BASE (PERIPH_BASE +0x00013044)
ïET1_BASE (PERIPH_BASE +0x00013090)
ðET2_BASE (PERIPH_BASE +0x000130B0)
ñET3_BASE (PERIPH_BASE +0x000130D0)
òET4_BASE (PERIPH_BASE +0x000130F0)
óETCNT_BASE (PERIPH_BASE +0x00013110)
ôBSTIM_BASE (PERIPH_BASE +0x00016000)
õLPTIM_BASE (PERIPH_BASE +0x00013400)
öRTC_BASE (PERIPH_BASE +0x00011000)
÷LCD_BASE (PERIPH_BASE +0x00010C00)
øADC_BASE (PERIPH_BASE +0x0001FA00)
ùCIC_BASE (PERIPH_BASE +0x00015C00)
úGPIOA_BASE (PERIPH_BASE +0x00000C00)
ûGPIOB_BASE (PERIPH_BASE +0x00000C40)
üGPIOC_BASE (PERIPH_BASE +0x00000C80)
ýGPIOD_BASE (PERIPH_BASE +0x00000CC0)
þGPIOE_BASE (PERIPH_BASE +0x00000D00)
ÿGPIOF_BASE (PERIPH_BASE +0x00000D40)
€GPIOG_BASE (PERIPH_BASE +0x00000D80)
GPIOH_BASE (PERIPH_BASE +0x0001FC00)
‚GPIO_BASE (PERIPH_BASE +0x00000DC0)
ˆPMU ((PMU_Type *) PMU_BASE )
‰DBG ((DBG_Type *) DBG_BASE )
ŠFLS ((FLS_Type *) FLS_BASE )
‹RMU ((RMU_Type *) RMU_BASE )
ŒIWDT ((IWDT_Type *) IWDT_BASE )
WWDT ((WWDT_Type *) WWDT_BASE )
ŽCMU ((CMU_Type *) CMU_BASE )
CDIF ((CDIF_Type *) CDIF_BASE )
VRTC ((VRTC_Type *) VRTC_BASE )
‘SVD ((SVD_Type *) SVD_BASE )
’AES ((AES_Type *) AES_BASE )
“PAE ((PAE_Type *) PAE_BASE )
”HASH ((HASH_Type *) HASH_BASE )
•RNG ((RNG_Type *) RNG_BASE )
–COMP ((COMP_Type *) COMP_BASE )
—I2C0 ((I2C_Type *) I2C0_BASE )
˜I2C1 ((I2C_Type *) I2C1_BASE )
™UARTIR ((UARTIR_Type *) UARTIR_BASE )
šUART0 ((UART_Type *) UART0_BASE )
›UART1 ((UART_Type *) UART1_BASE )
œUART2 ((UART_Type *) UART2_BASE )
UART3 ((UART_Type *) UART3_BASE )
žUART4 ((UART_Type *) UART4_BASE )
ŸUART5 ((UART_Type *) UART5_BASE )
 LPUART0 ((LPUART_Type *) LPUART0_BASE )
¡LPUART1 ((LPUART_Type *) LPUART1_BASE )
¢SPI0 ((SPI_Type *) SPI0_BASE )
£SPI1 ((SPI_Type *) SPI1_BASE )
¤SPI2 ((SPI_Type *) SPI2_BASE )
¥SPI3 ((SPI_Type *) SPI3_BASE )
¦SPI4 ((SPI_Type *) SPI4_BASE )
§U7816 ((U7816_Type *) U7816_BASE )
¨QSPI ((QSPI_Type *) QSPI_BASE )
©DMA ((DMA_Type *) DMA_BASE )
ªCRC ((CRC_Type *) CRC_BASE )
«BT1 ((BT_Type *) BT1_BASE )
¬BT2 ((BT_Type *) BT2_BASE )
­ET1 ((ET_Type *) ET1_BASE )
®ET2 ((ET_Type *) ET2_BASE )
¯ET3 ((ET_Type *) ET3_BASE )
°ET4 ((ET_Type *) ET4_BASE )
±ETCNT ((ETCNT_Type *) ETCNT_BASE )
²BSTIM ((BSTIM_Type *) BSTIM_BASE )
³LPTIM ((LPTIM_Type *) LPTIM_BASE )
´RTC ((RTC_Type *) RTC_BASE )
µLCD ((LCD_Type *) LCD_BASE )
¶ADC ((ADC_Type *) ADC_BASE )
·CIC ((CIC_Type *) CIC_BASE )
¸GPIOA ((GPIO_Type *) GPIOA_BASE )
¹GPIOB ((GPIO_Type *) GPIOB_BASE )
ºGPIOC ((GPIO_Type *) GPIOC_BASE )
»GPIOD ((GPIO_Type *) GPIOD_BASE )
¼GPIOE ((GPIO_Type *) GPIOE_BASE )
½GPIOF ((GPIO_Type *) GPIOF_BASE )
¾GPIOG ((GPIO_Type *) GPIOG_BASE )
¿GPIOH ((GPIOH_Type *) GPIOH_BASE )
ÀGPIO ((GPIO_COMMON_Type *) GPIO_BASE )h]
 




..\Core\Include\FM33A0XXEV.h
core_cm0plus.h
system_FM33A0XXEV.h


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..\Core\Include\FM33A0XXEV.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMÓ

RESETSET
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Reset_IRQnqNMI_IRQnrHardFault_IRQnsSVC_IRQn{PendSV_IRQn~SysTick_IRQnWWDT_IRQnSVD_IRQn
RTC_IRQnFLASH_IRQnCMU_IRQnADC_IRQnSPI0_IRQnSPI1_IRQnSPI2_IRQnUART0_IRQn    UART1_IRQn
UART2_IRQnUART3_IRQnUART4_IRQn UART5_IRQnU7816_IRQnLPUART0_IRQnI2Cx_IRQnRSV_IRQnCRYPTO_IRQnLPTIM_IRQnDMA_IRQnWKUPx_IRQnCOMP_IRQnBTx_IRQnQSPI_IRQnETx_IRQnBSTIM_IRQnSPI3_IRQnSPI4_IRQnGPIO_IRQnLPUART1_IRQnPIRQn_TypeG

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RSV20#$ACLOCK1v#HACLOCK2v#LACLOCK3v#PACLOCK4v#TW
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SERVv#CFGRv#CNTRˆ#PIWDT_Type0
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(SYSTEM_FM33A0XXEV_H 234
O__SYSTEM_CLOCK (8000000)
PDELAY_US (__SYSTEM_CLOCK/1000000)
QDELAY_MS (__SYSTEM_CLOCK/1000)
TDo_DelayStart() { uint32_t LastTick = SysTick->VAL; do {
WWhile_DelayMsEnd(Count) }while(((LastTick - SysTick->VAL)&0xFFFFFF)<DELAY_MS*Count); }
ZWhile_DelayUsEnd(Count) }while(((LastTick - SysTick->VAL)&0xFFFFFF)<DELAY_US*Count); }…
 




..\Core\Include\D:\Keil5\ARM\ARMCC\Bin\..\include\system_FM33A0XXEV.h
stdint.hstdio.hFM33A0XXEV.h


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..\Core\Include\system_FM33A0XXEV.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMqSystemCoreClockW


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__FM33A0XXEV_LCD_H 
LCD_CR_SCSEL_Pos 20
"LCD_CR_SCSEL_Msk (0x7U << LCD_CR_SCSEL_Pos)
#LCD_CR_SCSEL_LSCLK_COM (0x0U << LCD_CR_SCSEL_Pos)
$LCD_CR_SCSEL_LSCLK_8 (0x1U << LCD_CR_SCSEL_Pos)
%LCD_CR_SCSEL_LSCLK_16 (0x2U << LCD_CR_SCSEL_Pos)
&LCD_CR_SCSEL_LSCLK_32 (0x3U << LCD_CR_SCSEL_Pos)
'LCD_CR_SCSEL_LSCLK_64 (0x4U << LCD_CR_SCSEL_Pos)
(LCD_CR_SCSEL_LSCLK_128 (0x5U << LCD_CR_SCSEL_Pos)
)LCD_CR_SCSEL_LSCLK_256 (0x6U << LCD_CR_SCSEL_Pos)
*LCD_CR_SCSEL_LSCLK_512 (0x7U << LCD_CR_SCSEL_Pos)
,LCD_CR_SC_CTRL_Pos 18
1LCD_CR_SC_CTRL_Msk (0x3U << LCD_CR_SC_CTRL_Pos)
2LCD_CR_SC_CTRL_S0 (0x0U << LCD_CR_SC_CTRL_Pos)
3LCD_CR_SC_CTRL_S1 (0x1U << LCD_CR_SC_CTRL_Pos)
4LCD_CR_SC_CTRL_S2 (0x2U << LCD_CR_SC_CTRL_Pos)
5LCD_CR_SC_CTRL_S3 (0x3U << LCD_CR_SC_CTRL_Pos)
8LCD_CR_IC_CTRL_Pos 16
=LCD_CR_IC_CTRL_Msk (0x3U << LCD_CR_IC_CTRL_Pos)
>LCD_CR_IC_CTRL_L3 (0x0U << LCD_CR_IC_CTRL_Pos)
?LCD_CR_IC_CTRL_L2 (0x1U << LCD_CR_IC_CTRL_Pos)
@LCD_CR_IC_CTRL_L1 (0x2U << LCD_CR_IC_CTRL_Pos)
ALCD_CR_IC_CTRL_L0 (0x3U << LCD_CR_IC_CTRL_Pos)
CLCD_CR_ENMODE_Pos 15
FLCD_CR_ENMODE_Msk (0x1U << LCD_CR_ENMODE_Pos)
GLCD_CR_ENMODE_EXTERNALCAP (0x0U << LCD_CR_ENMODE_Pos)
HLCD_CR_ENMODE_INNERRESISTER (0x1U << LCD_CR_ENMODE_Pos)
JLCD_CR_FLICK_Pos 14
MLCD_CR_FLICK_Msk (0x1U << LCD_CR_FLICK_Pos)
QLCD_CR_BIAS_Pos 8
RLCD_CR_BIAS_Msk (0xfU << LCD_CR_BIAS_Pos)
TLCD_CR_BIASMD_Pos 5
WLCD_CR_BIASMD_Msk (0x1U << LCD_CR_BIASMD_Pos)
XLCD_CR_BIASMD_3BIAS (0x1U << LCD_CR_BIASMD_Pos)
YLCD_CR_BIASMD_4BIAS (0x0U << LCD_CR_BIASMD_Pos)
[LCD_CR_ANTIPOLAR_Pos 4
^LCD_CR_ANTIPOLAR_Msk (0x1U << LCD_CR_ANTIPOLAR_Pos)
_LCD_CR_ANTIPOLAR_GND (0x1U << LCD_CR_ANTIPOLAR_Pos)
`LCD_CR_ANTIPOLAR_FLOAT (0x0U << LCD_CR_ANTIPOLAR_Pos)
bLCD_CR_WFT_Pos 3
eLCD_CR_WFT_Msk (0x1U << LCD_CR_WFT_Pos)
fLCD_CR_WFT_BTYPE (0x1U << LCD_CR_WFT_Pos)
gLCD_CR_WFT_ATYPE (0x0U << LCD_CR_WFT_Pos)
iLCD_CR_LMUX_Pos 1
mLCD_CR_LMUX_Msk (0x3U << LCD_CR_LMUX_Pos)
nLCD_CR_LMUX_4COM (0x0U << LCD_CR_LMUX_Pos)
oLCD_CR_LMUX_6COM (0x1U << LCD_CR_LMUX_Pos)
pLCD_CR_LMUX_8COM (0x2U << LCD_CR_LMUX_Pos)
sLCD_CR_EN_Pos 0
vLCD_CR_EN_Msk (0x1U << LCD_CR_EN_Pos)
zLCD_TEST_LCCTRL_Pos 7
|LCD_TEST_LCCTRL_Msk (0x1U << LCD_TEST_LCCTRL_Pos)
}LCD_TEST_LCCTRL_LOW (0x0U << LCD_TEST_LCCTRL_Pos)
~LCD_TEST_LCCTRL_HIGH (0x1U << LCD_TEST_LCCTRL_Pos)
€
LCD_TEST_TESTEN_Pos 0
ƒ
LCD_TEST_TESTEN_Msk (0x1U << LCD_TEST_TESTEN_Pos)
‡
LCD_FCR_DF_Pos 0
ˆ
LCD_FCR_DF_Msk (0xffU << LCD_FCR_DF_Pos)
Š
LCD_FLKT_TOFF_Pos 8
Œ
LCD_FLKT_TOFF_Msk (0xffU << LCD_FLKT_TOFF_Pos)
Ž
LCD_FLKT_TON_Pos 0

LCD_FLKT_TON_Msk (0xffU << LCD_FLKT_TON_Pos)
’
LCD_IER_DONIE_Pos 1
•
LCD_IER_DONIE_Msk (0x1U << LCD_IER_DONIE_Pos)
™
LCD_IER_DOFFIE_Pos 0
œ
LCD_IER_DOFFIE_Msk (0x1U << LCD_IER_DOFFIE_Pos)
 
LCD_ISR_DONIF_Pos 1
¢
LCD_ISR_DONIF_Msk (0x1U << LCD_ISR_DONIF_Pos)
¤
LCD_ISR_DOFFIF_Pos 0
¦
LCD_ISR_DOFFIF_Msk (0x1U << LCD_ISR_DOFFIF_Pos)
¨
LCD_BSTCR_OSC_CFG_Pos 12
©
LCD_BSTCR_OSC_CFG_Msk (0xfU << LCD_BSTCR_OSC_CFG_Pos)
«
LCD_BSTCR_BUF_OFF_Pos 9
¬
LCD_BSTCR_BUF_OFF_Msk (0x1U << LCD_BSTCR_BUF_OFF_Pos)
®
LCD_BSTCR_BUFBYP_Pos 8
¯
LCD_BSTCR_BUFBYP_Msk (0x1U << LCD_BSTCR_BUFBYP_Pos)
±
LCD_BSTCR_VLCDPD_Pos 7
²
LCD_BSTCR_VLCDPD_Msk (0x1U << LCD_BSTCR_VLCDPD_Pos)
´
LCD_BSTCR_VLCDCFG_Pos 2
µ
LCD_BSTCR_VLCDCFG_Msk (0x1fU << LCD_BSTCR_VLCDCFG_Pos)
¶
LCD_BSTCR_VLCDCFG_2_4V (0x0U << LCD_BSTCR_VLCDCFG_Pos)
·
LCD_BSTCR_VLCDCFG_2_6V (0x1U << LCD_BSTCR_VLCDCFG_Pos)
¸
LCD_BSTCR_VLCDCFG_2_8V (0x2U << LCD_BSTCR_VLCDCFG_Pos)
¹
LCD_BSTCR_VLCDCFG_3_0V (0x3U << LCD_BSTCR_VLCDCFG_Pos)
º
LCD_BSTCR_VLCDCFG_3_2V (0x4U << LCD_BSTCR_VLCDCFG_Pos)
»
LCD_BSTCR_VLCDCFG_3_4V (0x5U << LCD_BSTCR_VLCDCFG_Pos)
¼
LCD_BSTCR_VLCDCFG_3_6V (0x6U << LCD_BSTCR_VLCDCFG_Pos)
½
LCD_BSTCR_VLCDCFG_3_8V (0x7U << LCD_BSTCR_VLCDCFG_Pos)
¾
LCD_BSTCR_VLCDCFG_4_0V (0x8U << LCD_BSTCR_VLCDCFG_Pos)
¿
LCD_BSTCR_VLCDCFG_4_2V (0x9U << LCD_BSTCR_VLCDCFG_Pos)
À
LCD_BSTCR_VLCDCFG_4_4V (0xaU << LCD_BSTCR_VLCDCFG_Pos)
Á
LCD_BSTCR_VLCDCFG_4_6V (0xbU << LCD_BSTCR_VLCDCFG_Pos)
Â
LCD_BSTCR_VLCDCFG_4_8V (0xcU << LCD_BSTCR_VLCDCFG_Pos)
Ã
LCD_BSTCR_VLCDCFG_5_0V (0xdU << LCD_BSTCR_VLCDCFG_Pos)
Ä
LCD_BSTCR_VLCDCFG_5_2V (0xeU << LCD_BSTCR_VLCDCFG_Pos)
Å
LCD_BSTCR_VLCDCFG_5_4V (0xfU << LCD_BSTCR_VLCDCFG_Pos)
Ç
LCD_BSTCR_BOOST_TEN_Pos 1
È
LCD_BSTCR_BOOST_TEN_Msk (0x1U << LCD_BSTCR_BOOST_TEN_Pos)
Ê
LCD_BSTCR_BOOST_EN_Pos 0
Ë
LCD_BSTCR_BOOST_EN_Msk (0x1U << LCD_BSTCR_BOOST_EN_Pos)
Í
LCD_COM_EN_COMEN_Pos 0
Î
LCD_COM_EN_COMEN_Msk (0xfU << LCD_COM_EN_COMEN_Pos)
Ð
LCD_SEG_EN0_SEGENx_Pos 0
Ñ
LCD_SEG_EN0_SEGENx_Msk (0xffffffffU << LCD_SEG_EN0_SEGENx_Pos)
Ó
LCD_SEG_EN1_SEGENx_Pos 0
Ô
LCD_SEG_EN1_SEGENx_Msk (0xfffU << LCD_SEG_EN1_SEGENx_Pos)
Ö
LCD_COM_EN_COMEN3_Pos 3
×
LCD_COM_EN_COMEN3_Msk (0x1U << LCD_COM_EN_COMEN3_Pos)
Ù
LCD_COM_EN_COMEN2_Pos 2
Ú
LCD_COM_EN_COMEN2_Msk (0x1U << LCD_COM_EN_COMEN2_Pos)
Ü
LCD_COM_EN_COMEN1_Pos 1
Ý
LCD_COM_EN_COMEN1_Msk (0x1U << LCD_COM_EN_COMEN1_Pos)
ß
LCD_COM_EN_COMEN0_Pos 0
à
LCD_COM_EN_COMEN0_Msk (0x1U << LCD_COM_EN_COMEN0_Pos)
â
LCD_SEG_EN0_SEGEN31_Pos 31
ã
LCD_SEG_EN0_SEGEN31_Msk (0x1U << LCD_SEG_EN0_SEGEN31_Pos)
å
LCD_SEG_EN0_SEGEN30_Pos 30
æ
LCD_SEG_EN0_SEGEN30_Msk (0x1U << LCD_SEG_EN0_SEGEN30_Pos)
è
LCD_SEG_EN0_SEGEN29_Pos 29
é
LCD_SEG_EN0_SEGEN29_Msk (0x1U << LCD_SEG_EN0_SEGEN29_Pos)
ë
LCD_SEG_EN0_SEGEN28_Pos 28
ì
LCD_SEG_EN0_SEGEN28_Msk (0x1U << LCD_SEG_EN0_SEGEN28_Pos)
î
LCD_SEG_EN0_SEGEN27_Pos 27
ï
LCD_SEG_EN0_SEGEN27_Msk (0x1U << LCD_SEG_EN0_SEGEN27_Pos)
ñ
LCD_SEG_EN0_SEGEN26_Pos 26
ò
LCD_SEG_EN0_SEGEN26_Msk (0x1U << LCD_SEG_EN0_SEGEN26_Pos)
ô
LCD_SEG_EN0_SEGEN25_Pos 25
õ
LCD_SEG_EN0_SEGEN25_Msk (0x1U << LCD_SEG_EN0_SEGEN25_Pos)
÷
LCD_SEG_EN0_SEGEN24_Pos 24
ø
LCD_SEG_EN0_SEGEN24_Msk (0x1U << LCD_SEG_EN0_SEGEN24_Pos)
ú
LCD_SEG_EN0_SEGEN23_Pos 23
û
LCD_SEG_EN0_SEGEN23_Msk (0x1U << LCD_SEG_EN0_SEGEN23_Pos)
ý
LCD_SEG_EN0_SEGEN22_Pos 22
þ
LCD_SEG_EN0_SEGEN22_Msk (0x1U << LCD_SEG_EN0_SEGEN22_Pos)
€LCD_SEG_EN0_SEGEN21_Pos 21
LCD_SEG_EN0_SEGEN21_Msk (0x1U << LCD_SEG_EN0_SEGEN21_Pos)
ƒLCD_SEG_EN0_SEGEN20_Pos 20
„LCD_SEG_EN0_SEGEN20_Msk (0x1U << LCD_SEG_EN0_SEGEN20_Pos)
†LCD_SEG_EN0_SEGEN19_Pos 19
‡LCD_SEG_EN0_SEGEN19_Msk (0x1U << LCD_SEG_EN0_SEGEN19_Pos)
‰LCD_SEG_EN0_SEGEN18_Pos 18
ŠLCD_SEG_EN0_SEGEN18_Msk (0x1U << LCD_SEG_EN0_SEGEN18_Pos)
ŒLCD_SEG_EN0_SEGEN17_Pos 17
LCD_SEG_EN0_SEGEN17_Msk (0x1U << LCD_SEG_EN0_SEGEN17_Pos)
LCD_SEG_EN0_SEGEN16_Pos 16
LCD_SEG_EN0_SEGEN16_Msk (0x1U << LCD_SEG_EN0_SEGEN16_Pos)
’LCD_SEG_EN0_SEGEN15_Pos 15
“LCD_SEG_EN0_SEGEN15_Msk (0x1U << LCD_SEG_EN0_SEGEN15_Pos)
•LCD_SEG_EN0_SEGEN14_Pos 14
–LCD_SEG_EN0_SEGEN14_Msk (0x1U << LCD_SEG_EN0_SEGEN14_Pos)
˜LCD_SEG_EN0_SEGEN13_Pos 13
™LCD_SEG_EN0_SEGEN13_Msk (0x1U << LCD_SEG_EN0_SEGEN13_Pos)
›LCD_SEG_EN0_SEGEN12_Pos 12
œLCD_SEG_EN0_SEGEN12_Msk (0x1U << LCD_SEG_EN0_SEGEN12_Pos)
žLCD_SEG_EN0_SEGEN11_Pos 11
ŸLCD_SEG_EN0_SEGEN11_Msk (0x1U << LCD_SEG_EN0_SEGEN11_Pos)
¡LCD_SEG_EN0_SEGEN10_Pos 10
¢LCD_SEG_EN0_SEGEN10_Msk (0x1U << LCD_SEG_EN0_SEGEN10_Pos)
¤LCD_SEG_EN0_SEGEN9_Pos 9
¥LCD_SEG_EN0_SEGEN9_Msk (0x1U << LCD_SEG_EN0_SEGEN9_Pos)
§LCD_SEG_EN0_SEGEN8_Pos 8
¨LCD_SEG_EN0_SEGEN8_Msk (0x1U << LCD_SEG_EN0_SEGEN8_Pos)
ªLCD_SEG_EN0_SEGEN7_Pos 7
«LCD_SEG_EN0_SEGEN7_Msk (0x1U << LCD_SEG_EN0_SEGEN7_Pos)
­LCD_SEG_EN0_SEGEN6_Pos 6
®LCD_SEG_EN0_SEGEN6_Msk (0x1U << LCD_SEG_EN0_SEGEN6_Pos)
°LCD_SEG_EN0_SEGEN5_Pos 5
±LCD_SEG_EN0_SEGEN5_Msk (0x1U << LCD_SEG_EN0_SEGEN5_Pos)
³LCD_SEG_EN0_SEGEN4_Pos 4
´LCD_SEG_EN0_SEGEN4_Msk (0x1U << LCD_SEG_EN0_SEGEN4_Pos)
¶LCD_SEG_EN0_SEGEN3_Pos 3
·LCD_SEG_EN0_SEGEN3_Msk (0x1U << LCD_SEG_EN0_SEGEN3_Pos)
¹LCD_SEG_EN0_SEGEN2_Pos 2
ºLCD_SEG_EN0_SEGEN2_Msk (0x1U << LCD_SEG_EN0_SEGEN2_Pos)
¼LCD_SEG_EN0_SEGEN1_Pos 1
½LCD_SEG_EN0_SEGEN1_Msk (0x1U << LCD_SEG_EN0_SEGEN1_Pos)
¿LCD_SEG_EN0_SEGEN0_Pos 0
ÀLCD_SEG_EN0_SEGEN0_Msk (0x1U << LCD_SEG_EN0_SEGEN0_Pos)
ÂLCD_SEG_EN1_SEGEN43_Pos 11
ÃLCD_SEG_EN1_SEGEN43_Msk (0x1U << LCD_SEG_EN1_SEGEN43_Pos)
ÅLCD_SEG_EN1_SEGEN42_Pos 10
ÆLCD_SEG_EN1_SEGEN42_Msk (0x1U << LCD_SEG_EN1_SEGEN42_Pos)
ÈLCD_SEG_EN1_SEGEN41_Pos 9
ÉLCD_SEG_EN1_SEGEN41_Msk (0x1U << LCD_SEG_EN1_SEGEN41_Pos)
ËLCD_SEG_EN1_SEGEN40_Pos 8
ÌLCD_SEG_EN1_SEGEN40_Msk (0x1U << LCD_SEG_EN1_SEGEN40_Pos)
ÎLCD_SEG_EN1_SEGEN39_Pos 7
ÏLCD_SEG_EN1_SEGEN39_Msk (0x1U << LCD_SEG_EN1_SEGEN39_Pos)
ÑLCD_SEG_EN1_SEGEN38_Pos 6
ÒLCD_SEG_EN1_SEGEN38_Msk (0x1U << LCD_SEG_EN1_SEGEN38_Pos)
ÔLCD_SEG_EN1_SEGEN37_Pos 5
ÕLCD_SEG_EN1_SEGEN37_Msk (0x1U << LCD_SEG_EN1_SEGEN37_Pos)
×LCD_SEG_EN1_SEGEN36_Pos 4
ØLCD_SEG_EN1_SEGEN36_Msk (0x1U << LCD_SEG_EN1_SEGEN36_Pos)
ÚLCD_SEG_EN1_SEGEN35_Pos 3
ÛLCD_SEG_EN1_SEGEN35_Msk (0x1U << LCD_SEG_EN1_SEGEN35_Pos)
ÝLCD_SEG_EN1_SEGEN34_Pos 2
ÞLCD_SEG_EN1_SEGEN34_Msk (0x1U << LCD_SEG_EN1_SEGEN34_Pos)
àLCD_SEG_EN1_SEGEN33_Pos 1
áLCD_SEG_EN1_SEGEN33_Msk (0x1U << LCD_SEG_EN1_SEGEN33_Pos)
ãLCD_SEG_EN1_SEGEN32_Pos 0
äLCD_SEG_EN1_SEGEN32_Msk (0x1U << LCD_SEG_EN1_SEGEN32_Pos)
æLCD_SEG_EN1_COMEN7_Pos 11
çLCD_SEG_EN1_COMEN7_Msk (0x1U << LCD_SEG_EN1_COMEN7_Pos)
éLCD_SEG_EN1_COMEN6_Pos 10
êLCD_SEG_EN1_COMEN6_Msk (0x1U << LCD_SEG_EN1_COMEN6_Pos)
ìLCD_SEG_EN1_COMEN5_Pos 9
íLCD_SEG_EN1_COMEN5_Msk (0x1U << LCD_SEG_EN1_COMEN5_Pos)
ïLCD_SEG_EN1_COMEN4_Pos 8
ðLCD_SEG_EN1_COMEN4_Msk (0x1U << LCD_SEG_EN1_COMEN4_Pos)`T
 




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