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..\USER\stm32f10x.h ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Administrator\Desktop\HCI\USER Xö Ì= ± IRQn NonMaskableInt_IRQn rMemoryManagement_IRQn tBusFault_IRQn uUsageFault_IRQn vSVCall_IRQn {DebugMonitor_IRQn |PendSV_IRQn ~SysTick_IRQn WWDG_IRQn PVD_IRQn TAMPER_IRQn RTC_IRQn FLASH_IRQn RCC_IRQn EXTI0_IRQn EXTI1_IRQn EXTI2_IRQn EXTI3_IRQn EXTI4_IRQn
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DMA1_Channel1_IRQn DMA1_Channel2_IRQn DMA1_Channel3_IRQn DMA1_Channel4_IRQn DMA1_Channel5_IRQn DMA1_Channel6_IRQn DMA1_Channel7_IRQn ADC1_2_IRQn USB_HP_CAN1_TX_IRQn USB_LP_CAN1_RX0_IRQn CAN1_RX1_IRQn CAN1_SCE_IRQn EXTI9_5_IRQn TIM1_BRK_IRQn TIM1_UP_IRQn TIM1_TRG_COM_IRQn TIM1_CC_IRQn TIM2_IRQn TIM3_IRQn TIM4_IRQn I2C1_EV_IRQn I2C1_ER_IRQn I2C2_EV_IRQn !I2C2_ER_IRQn "SPI1_IRQn #SPI2_IRQn $USART1_IRQn %USART2_IRQn &USART3_IRQn 'EXTI15_10_IRQn (RTCAlarm_IRQn )USBWakeUp_IRQn *TIM8_BRK_IRQn +TIM8_UP_IRQn ,TIM8_TRG_COM_IRQn -TIM8_CC_IRQn .ADC3_IRQn /FSMC_IRQn 0SDIO_IRQn 1TIM5_IRQn 2SPI3_IRQn 3UART4_IRQn 4UART5_IRQn 5TIM6_IRQn 6TIM7_IRQn 7DMA2_Channel1_IRQn 8DMA2_Channel2_IRQn 9DMA2_Channel3_IRQn :DMA2_Channel4_5_IRQn ; PIRQn_Type vØPs32 õ çPs16 ç èPs8 Ú éõ Psc32 ëëç Psc16 þìÚ Psc8 ítõ Pvs32 #ïtç Pvs16 6ðtÚ Pvs8 IñtëPvsc32 [ótþPvsc16 môtPvsc8 õPu32 1 ÷Pu16 ! øPu8 ù1 Puc32 ¹û! Puc16 Ìü Puc8 ßýt1 Pvu32 ñÿt! Pvu16 t Pvu8 t¹Pvuc32 )tÌPvuc16 ;tßPvuc8 M
ó RESET SET PFlagStatus ^(PITStatus ^4± DISABLE ENABLE PFunctionalState /â ERROR SUCCESS PErrorStatus É,*éP SR ñ# CR1 ñ# CR2 ñ# SMPR1 ñ# SMPR2 ñ# JOFR1 ñ# JOFR2 ñ# JOFR3 ñ# JOFR4 ñ# HTR ñ#$ LTR ñ#( SQR1 ñ#, SQR2 ñ#0 SQR3 ñ#4 JSQR ñ#8 JDR1 ñ#< JDR2 ñ#@ JDR3 ñ#D JDR4 ñ#H DR ñ#L PADC_TypeDef ö´*ËÀ RESERVED0 1 # DR1 # RESERVED1 ! # DR2 # RESERVED2 ! #
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DR3 # RESERVED3 ! # DR4 # RESERVED4 ! # DR5 # RESERVED5 ! # DR6 # RESERVED6 ! # DR7 # RESERVED7 ! # DR8 # RESERVED8 ! #" DR9 #$ RESERVED9 ! #& DR10 #( RESERVED10 ! #* RTCCR #, RESERVED11 ! #. CR #0 RESERVED12 ! #2 CSR #4! RESERVED13 #6 DR11 #@ RESERVED14 ! #B DR12 #D RESERVED15 ! #F DR13 #H RESERVED16 ! #J DR14 #L RESERVED17 ! #N DR15 #P RESERVED18 ! #R DR16 #T RESERVED19 ! #V DR17 #X RESERVED20 ! #Z DR18 #\ RESERVED21 ! #^ DR19 #` RESERVED22 ! #b DR20 #d RESERVED23 ! #f DR21 #h RESERVED24 ! #j DR22 #l RESERVED25 ! #n DR23 #p RESERVED26 ! #r DR24 #t RESERVED27 ! #v DR25 #x RESERVED28 ! #z DR26 #| RESERVED29 ! #~ DR27 # RESERVED30 ! # DR28 # RESERVED31 ! # DR29 # RESERVED32 ! # DR30 # RESERVED33 ! # DR31 # RESERVED34 ! # DR32 # RESERVED35 ! # DR33 # RESERVED36 ! # DR34 # RESERVED37 ! # DR35 # RESERVED38 ! #¢ DR36 #¤ RESERVED39 ! #¦ DR37 #¨ RESERVED40 ! #ª DR38 #¬ RESERVED41 ! #® DR39 #° RESERVED42 ! #² DR40 #´ RESERVED43 ! #¶ DR41 #¸ RESERVED44 ! #º DR42 #¼ RESERVED45 ! #¾ PBKP_TypeDef ý* TIR ñ# TDTR ñ# TDLR ñ# TDHR ñ# PCAN_TxMailBox_TypeDef ß £*å RIR ñ# RDTR ñ# RDLR ñ# RDHR ñ# PCAN_FIFOMailBox_TypeDef 1¯* FR1 ñ# FR2 ñ# PCAN_FilterRegister_TypeDef
¹*Ñ ° MCR ñ# MSR ñ# TSR ñ# RF0R ñ# RF1R ñ# IER ñ# ESR ñ# BTR ñ# 1 W RESERVED0 "# Ç sTxMailBox >#ã e sFIFOMailBox Z#° 1 RESERVED1 x#Ð FMR ñ# FM1R ñ# RESERVED2 1 # FS1R ñ# RESERVED3 1 # FFA1R ñ# RESERVED4 1 # FA1R ñ# 1 RESERVED5 # ¸ sFilterRegister /#À PCAN_TypeDef ÃÛ*¹! CFGR ñ# OAR ñ# PRES ñ# ESR ñ# CSR ñ# TXD ñ# RXD ñ# PCEC_TypeDef eé*" DR ñ# IDR # RESERVED0 # RESERVED1 ! # CR ñ# PCRC_TypeDef Íö*å#4 CR ñ# SWTRIGR ñ# DHR12R1 ñ# DHR12L1 ñ# DHR8R1 ñ# DHR12R2 ñ# DHR12L2 ñ# DHR8R2 ñ# DHR12RD ñ# DHR12LD ñ#$ DHR8RD ñ#( DOR1 ñ#, DOR2 ñ#0 PDAC_TypeDef +*$ IDCODE ñ# CR ñ# PDBGMCU_TypeDef ù*â$ CCR ñ# CNDTR ñ# CPAR ñ# CMAR ñ# PDMA_Channel_TypeDef -¤*% ISR ñ# IFCR ñ# PDMA_TypeDef ~ª*£.Ø MACCR ñ# MACFFR ñ# MACHTHR ñ# MACHTLR ñ# MACMIIAR ñ# MACMIIDR ñ# MACFCR ñ# MACVLANTR ñ# ¶&1 RESERVED0 +# MACRWUFFR ñ#( MACPMTCSR ñ#,ô&1 RESERVED1 i#0 MACSR ñ#8 MACIMR ñ#< MACA0HR ñ#@ MACA0LR ñ#D MACA1HR ñ#H MACA1LR ñ#L MACA2HR ñ#P MACA2LR ñ#T MACA3HR ñ#X MACA3LR ñ#\£(1 ' RESERVED2 #` MMCCR ñ# MMCRIR ñ# MMCTIR ñ# MMCRIMR ñ# MMCTIMR ñ#)1 RESERVED3 # MMCTGFSCCR ñ#Ì MMCTGFMSCCR ñ#ÐÏ)1 RESERVED4 Ä#Ô MMCTGFCR ñ#èý)1 RESERVED5 ò#ì MMCRFCECR ñ# MMCRFAECR ñ#¾*1 RESERVED6 3# MMCRGUFCR ñ#Äî*1 Í RESERVED7 b#È PTPTSCR ñ# PTPSSIR ñ# PTPTSHR ñ# PTPTSLR ñ# PTPTSHUR ñ# PTPTSLUR ñ# PTPTSAR ñ# PTPTTHR ñ# PTPTTLR ñ# ,1 ¶ RESERVED8 #¤ DMABMR ñ# DMATPDR ñ# DMARPDR ñ# DMARDLAR ñ# DMATDLAR ñ# DMASR ñ# DMAOMR ñ# DMAIER ñ# DMAMFBOCR ñ# Ê-1 RESERVED9 ¿#¤ DMACHTDR ñ#È DMACHRDR ñ#Ì DMACHTBAR ñ#Ð DMACHRBAR ñ#Ô PETH_TypeDef ®ñ*/ IMR ñ# EMR ñ# RTSR ñ# FTSR ñ# SWIER ñ# PR ñ# PEXTI_TypeDef 7ÿ*0$ ACR ñ# KEYR ñ# OPTKEYR ñ# SR ñ# CR ñ# AR ñ# RESERVED ñ# OBR ñ# WRPR ñ# PFLASH_TypeDef *1 RDP # USER # Data0 # Data1 # WRP0 # WRP1 #
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WRP2 # WRP3 # POB_TypeDef ¨*¯1 ¢1ñ BTCR # PFSMC_Bank1_TypeDef ±*ä1 ×1ñ BWTR Î# PFSMC_Bank1E_TypeDef ʺ*Ö2 PCR2 ñ# SR2 ñ# PMEM2 ñ# PATT2 ñ# RESERVED0 1 # ECCR2 ñ# PFSMC_Bank2_TypeDef È*Ç3 PCR3 ñ# SR3 ñ# PMEM3 ñ# PATT3 ñ# RESERVED0 1 # ECCR3 ñ# PFSMC_Bank3_TypeDef qÖ*¤4 PCR4 ñ# SR4 ñ# PMEM4 ñ# PATT4 ñ# PIO4 ñ# PFSMC_Bank4_TypeDef âã*5 CRL ñ# CRH ñ# IDR ñ# ODR ñ# BSRR ñ# BRR ñ# LCKR ñ# PGPIO_TypeDef ?ò*ü5 EVCR ñ# MAPR ñ#Í5ñ EXTICR Ä# RESERVED0 1 # MAPR2 ñ# PAFIO_TypeDef ¨ÿ*§8$ CR1 # RESERVED0 ! # CR2 # RESERVED1 ! # OAR1 # RESERVED2 ! #
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OAR2 # RESERVED3 ! # DR # RESERVED4 ! # SR1 # RESERVED5 ! # SR2 # RESERVED6 ! # CCR # RESERVED7 ! # TRISE # RESERVED8 ! #" PI2C_TypeDef *é8 KR ñ# PR ñ# RLR ñ# SR ñ# PIWDG_TypeDef ; ¤*9 CR ñ# CSR ñ# PPWR_TypeDef ~ ®*µ:( CR ñ# CFGR ñ# CIR ñ# APB2RSTR ñ# APB1RSTR ñ# AHBENR ñ# APB2ENR ñ# APB1ENR ñ# BDCR ñ# CSR ñ#$ PRCC_TypeDef ¬ Ê*=( CRH # RESERVED0 ! # CRL # RESERVED1 ! # PRLH # RESERVED2 ! #
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PRLL # RESERVED3 ! # DIVH # RESERVED4 ! # DIVL # RESERVED5 ! # CNTH # RESERVED6 ! # CNTL # RESERVED7 ! # ALRH # RESERVED8 ! #" ALRL #$ RESERVED9 ! #& PRTC_TypeDef I æ*º? POWER ñ# CLKCR ñ# ARG ñ# CMD ñ# RESPCMD )# RESP1 )# RESP2 )# RESP3 )# RESP4 )# DTIMER ñ#$ DLEN ñ#( DCTRL ñ#, DCOUNT )#0 STA )#4 ICR ñ#8 MASK ñ#<ð>1 RESERVED0 e #@ FIFOCNT )#H?1 RESERVED1 #L FIFO ñ# PSDIO_TypeDef *îA$ CR1 # RESERVED0 ! # CR2 # RESERVED1 ! # SR # RESERVED2 ! #
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DR # RESERVED3 ! # CRCPR # RESERVED4 ! # RXCRCR # RESERVED5 ! # TXCRCR # RESERVED6 ! # I2SCFGR # RESERVED7 ! # I2SPR # RESERVED8 ! #" PSPI_TypeDef Ï *õFP CR1 # RESERVED0 ! # CR2 # RESERVED1 ! # SMCR # RESERVED2 ! #
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DIER # RESERVED3 ! # SR # RESERVED4 ! # EGR # RESERVED5 ! # CCMR1 # RESERVED6 ! # CCMR2 # RESERVED7 ! # CCER # RESERVED8 ! #" CNT #$ RESERVED9 ! #& PSC #( RESERVED10 ! #* ARR #, RESERVED11 ! #. RCR #0 RESERVED12 ! #2 CCR1 #4 RESERVED13 ! #6 CCR2 #8 RESERVED14 ! #: CCR3 #< RESERVED15 ! #> CCR4 #@ RESERVED16 ! #B BDTR #D RESERVED17 ! #F DCR #H RESERVED18 ! #J DMAR #L RESERVED19 ! #N PTIM_TypeDef !Ì *ßH SR # RESERVED0 ! # DR # RESERVED1 ! # BRR # RESERVED2 ! #
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CR1 # RESERVED3 ! # CR2 # RESERVED4 ! # CR3 # RESERVED5 ! # GTPR # RESERVED6 ! # PUSART_TypeDef #â *I CR ñ# CFR ñ# SR ñ# PWWDG_TypeDef u$í @
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..\STM32F10x_FWLib\inc\stm32f10x_adc.h ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Administrator\Desktop\HCI\USER äÔ h= *© ADC_Mode 1 # ADC_ScanConvMode # ADC_ContinuousConvMode # ADC_ExternalTrigConv 1 # ADC_DataAlign 1 # ADC_NbrOfChannel # PADC_InitTypeDef J
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..\STM32F10x_FWLib\inc\stm32f10x_spi.h ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Administrator\Desktop\HCI\USER 4~ << *Ò SPI_Direction ! # SPI_Mode ! # SPI_DataSize ! # SPI_CPOL ! # SPI_CPHA ! # SPI_NSS ! #
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SPI_BaudRatePrescaler ! # SPI_FirstBit ! # SPI_CRCPolynomial ! # PSPI_InitTypeDef Q*ï I2S_Mode ! # I2S_Standard ! # I2S_DataFormat ! # I2S_MCLKOutput ! # I2S_AudioFreq 1 # I2S_CPOL ! # PI2S_InitTypeDef ik ¸
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..\STM32F10x_FWLib\inc\stm32f10x_usart.h ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Administrator\Desktop\HCI\USER t p; *§ USART_BaudRate 1 # USART_WordLength ! # USART_StopBits ! # USART_Parity ! # USART_Mode ! #
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USART_HardwareFlowControl ! # PUSART_InitTypeDef L* USART_Clock ! # USART_CPOL ! # USART_CPHA ! # USART_LastBit ! # PUSART_ClockInitTypeDef @a `
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..\STM32F10x_FWLib\inc\stm32f10x_tim.h ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Administrator\Desktop\HCI\USER ¸2 Ø; *
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TIM_Prescaler ! # TIM_CounterMode ! # TIM_Period ! # TIM_ClockDivision ! # TIM_RepetitionCounter # PTIM_TimeBaseInitTypeDef J*î TIM_OCMode ! # TIM_OutputState ! # TIM_OutputNState ! # TIM_Pulse ! # TIM_OCPolarity ! # TIM_OCNPolarity ! #
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TIM_OCIdleState ! # TIM_OCNIdleState ! # PTIM_OCInitTypeDef +m*
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TIM_Channel ! # TIM_ICPolarity ! # TIM_ICSelection ! # TIM_ICPrescaler ! # TIM_ICFilter ! # PTIM_ICInitTypeDef *Æ TIM_OSSRState ! # TIM_OSSIState ! # TIM_LOCKLevel ! # TIM_DeadTime ! # TIM_Break ! # TIM_BreakPolarity ! #
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TIM_AutomaticOutput ! # PTIM_BDTRInitTypeDef £ $
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..\STM32F10x_FWLib\inc\stm32f10x_rcc.h ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Administrator\Desktop\HCI\USER < * SYSCLK_Frequency 1 # HCLK_Frequency 1 # PCLK1_Frequency 1 # PCLK2_Frequency 1 # ADCCLK_Frequency 1 # PRCC_ClocksTypeDef 5
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..\STM32F10x_FWLib\inc\stm32f10x_gpio.h ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Administrator\Desktop\HCI\USER ô¶ = ÊGPIO_Speed_10MHz GPIO_Speed_2MHz GPIO_Speed_50MHz PGPIOSpeed_TypeDef ?GPIO_Mode_AIN GPIO_Mode_IN_FLOATING GPIO_Mode_IPD (GPIO_Mode_IPU HGPIO_Mode_Out_OD GPIO_Mode_Out_PP GPIO_Mode_AF_OD GPIO_Mode_AF_PP PGPIOMode_TypeDef ã P*Ô GPIO_Pin ! # GPIO_Speed Ê # GPIO_Mode # PGPIO_InitTypeDef eBit_RESET Bit_SET PBitAction ìo
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..\STM32F10x_FWLib\inc\misc.h ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Administrator\Desktop\HCI\USER ; * NVIC_IRQChannel # NVIC_IRQChannelPreemptionPriority # NVIC_IRQChannelSubPriority # NVIC_IRQChannelCmd # PNVIC_InitTypeDef D
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..\STM32F10x_FWLib\src\stm32f10x_adc.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Administrator\Desktop\HCI\USER "Å
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"µ( t1
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..\STM32F10x_FWLib\src\stm32f10x_spi.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Administrator\Desktop\HCI\USER t "Ê# ""* "¿*
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..\STM32F10x_FWLib\src\stm32f10x_usart.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Administrator\Desktop\HCI\USER , Ô ";' "ÿ+ "q, ¨
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..\STM32F10x_FWLib\src\stm32f10x_tim.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Administrator\Desktop\HCI\USER P "Q& " - ". "/ "Ú/ °
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..\STM32F10x_FWLib\src\stm32f10x_rcc.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Administrator\Desktop\HCI\USER è t ¥ t1 "1
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..\STM32F10x_FWLib\src\stm32f10x_gpio.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Administrator\Desktop\HCI\USER "o "ô2
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..\STM32F10x_FWLib\src\misc.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Administrator\Desktop\HCI\USER ì "E4
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..\HARDWARE\RS485\RS485.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Administrator\Desktop\HCI\USER $ ,% ? "
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..\HARDWARE\hcs2022\hcs2022.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Administrator\Desktop\HCI\USER @ , float "
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system_stm32f10x.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Administrator\Desktop\HCI\USER X ø8 tu{ t1 4 ..\STM32F10x_FWLib\src\stm32f10x_adc.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Administrator\Desktop\HCI\USER C îG ?¼³ADC_DeInit C îC * iADCx é4 i ?¤ÚADC_Init îC 4D
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iADCx é4 V iADC_InitStruct ï4 C Xtmpreg1 1 PXtmpreg2 S ?áADC_StructInit 4D FD ö iADC_InitStruct ï4 0 ? «ADC_Cmd FD \D â iADCx é4 iNewState
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?âÄADC_DMACmd \D rD Î iADCx é4 ÷ iNewState ä ?ÈáADC_ITConfig rD D ® iADCx é4 Ñ iADC_IT ! ¾ iNewState « Zitmask ?ûADC_ResetCalibration D D iADCx é4
>î ADC_GetResetCalibrationStatus O D ¨D iADCx é4 r ^__result O PXbitstatus O P ?§¡ADC_StartCalibration ¨D ²D r iADCx é4 _ >® ADC_GetCalibrationStatus O ²D ÆD ^ iADCx é4 L ^__result O PXbitstatus O P ?ßÉADC_SoftwareStartConvCmd ÆD ÜD J iADCx é4 9 iNewState & >Íá ADC_GetSoftwareStartConvStatus O ÜD ðD 6 iADCx é4 ^__result O PXbitstatus O P ?à ýADC_DiscModeChannelCountConfig ðD E iADCx é4 iNumber í Xtmpreg1 1 QXtmpreg2 1 S ?
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ADC_DiscModeCmd E E iADCx é4 Ú iNewState Ç ?© ÎADC_RegularChannelConfig E ÖE â iADCx é4 ´ iADC_Channel ¡ iRank iADC_SampleTime { Ztmpreg1 1 h Ztmpreg2 1 U ?ø ®ADC_ExternalTrigConvCmd ÖE ìE Î iADCx é4 B iNewState / >Ë Ä
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ADC_GetConversionValue ! ìE ôE º iADCx é4 ^__result ! P > Ð
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ADC_GetDualModeConversionValue 1 ôE üE ¦ ^__result 1 P ?æ ÞADC_AutoInjectedConvCmd üE F iADCx é4 iNewState ö ?µøADC_InjectedDiscModeCmd F (F ~ iADCx é4 ã iNewState Ð ?°ADC_ExternalTrigInjectedConvConfig (F 8F j iADCx é4 ½ iADC_ExternalTrigInjecConv 1 ª Xtmpreg 1 Q ?¸ADC_ExternalTrigInjectedConvCmd 8F NF V iADCx é4 iNewState ?ßÑADC_SoftwareStartInjectedConvCmd NF dF B iADCx é4 q iNewState ^ >Øé ADC_GetSoftwareStartInjectedConvCmdStatus O dF xF . iADCx é4 K ^__result O PXbitstatus O P ?¢ADC_InjectedChannelConfig xF úF iADCx é4 8 iADC_Channel % iRank iADC_SampleTime ÿ Xtmpreg1 1 PXtmpreg2 1 R
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Xtmpreg3 1 V ?áADC_InjectedSequencerLengthConfig úF G î iADCx é4 ì iLength Ù Xtmpreg1 1 QXtmpreg2 1 S ?öADC_SetInjectedOffset G &G Î iADCx é4 Æ iADC_InjectedChannel ³ iOffset ! Ytmp õ4 x >ü
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ADC_GetInjectedConversionValue ! &G BG ® iADCx é4 iADC_InjectedChannel z ^__result ! PYtmp õ4 x ?ãºADC_AnalogWatchdogCmd BG RG iADCx é4 g iADC_AnalogWatchdog 1 T Xtmpreg 1 Q ?ÙÓADC_AnalogWatchdogThresholdsConfig RG XG iADCx é4 A iHighThreshold ! . iLowThreshold ! ?ÉùADC_AnalogWatchdogSingleChannelConfig XG hG r iADCx é4 iADC_Channel õ Xtmpreg 1 Q ? ADC_TempSensorVrefintCmd hG ¨G ^ iNewState â >þ« ADC_GetFlagStatus O ¨G ºG J iADCx é4 Ï iADC_FLAG ¼ ^__result O PXbitstatus O P ?ÃÌ ADC_ClearFlag ºG ÀG 6 iADCx é4 © iADC_FLAG >Ùß
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ADC_GetITStatus b ÀG äG iADCx é4 iADC_IT ! p ^__result b P"Xbitstatus b PXitmask 1 SXenablestatus 1 T
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?´
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ADC_ClearITPendingBit äG îG iADCx é4 ] iADC_IT ! J Xitmask R ..\STM32F10x_FWLib\src\stm32f10x_spi.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Administrator\Desktop\HCI\USER @ C ü ?¿wSPI_I2S_DeInit @ à@
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iSPIx 5 ù ?SPI_Init à@ A j
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iSPIx 5 æ iSPI_InitStruct 5 Ó Xtmpreg ! R ?ØÛI2S_Init A þA 2
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iSPIx 5 À iI2S_InitStruct 5 Xtmpreg ! YXi2sdiv ! WXi2sodd ! XXpacketlength ! [Ztmp 1 YRCC_Clocks 1 HXsourceclock 1 Z ?òSPI_StructInit þA B
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iSPI_InitStruct 5 | ?ÒI2S_StructInit B *B
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iI2S_InitStruct 5 i ?«SPI_Cmd *B BB ö iSPIx 5 V iNewState C ?ÐÃI2S_Cmd BB ZB â iSPIx 5 0 iNewState ?ÎâSPI_I2S_ITConfig ZB zB Â iSPIx 5
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iSPI_I2S_IT ÷ iNewState ä Zitpos ! Ñ Zitmask ! ¾ ?SPI_I2S_DMACmd zB B ® iSPIx 5 « iSPI_I2S_DMAReq ! iNewState
?ñ£SPI_I2S_SendData B B iSPIx 5 r iData ! _ >Á³
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SPI_I2S_ReceiveData ! B B iSPIx 5 L ^__result ! P ?¡ ÅSPI_NSSInternalSoftwareConfig B ´B r iSPIx 5 9 iSPI_NSSInternalSoft ! & ?è ÝSPI_SSOutputCmd ´B ÌB ^ iSPIx 5 iNewState ?¶
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÷SPI_DataSizeConfig ÌB ÞB J iSPIx 5 í iSPI_DataSize ! Ú ?ê
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SPI_TransmitCRC ÞB èB 6 iSPIx 5 Ç ?² SPI_CalculateCRC èB C " iSPIx 5 ´ iNewState ¡ > ±
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SPI_GetCRC ! C C iSPIx 5 iSPI_CRC { ^__result ! PXcrcreg ! P >ì Ê
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SPI_GetCRCPolynomial ! C C ú iSPIx 5 h ^__result ! P ?Ä ÜSPI_BiDirectionalLineConfig C 2C æ iSPIx 5 U iSPI_Direction ! B >Àþ SPI_I2S_GetFlagStatus O 2C DC Ò iSPIx 5 / iSPI_I2S_FLAG ! ^__result O PXbitstatus O P ?¤SPI_I2S_ClearFlag DC JC ¾ iSPIx 5 iSPI_I2S_FLAG ! ö
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>º½
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SPI_I2S_GetITStatus b JC ~C iSPIx 5 ã
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iSPI_I2S_IT Ð
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^__result b P2Xbitstatus b PXitpos ! TXitmask ! S
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Xenablestatus ! U ?óSPI_I2S_ClearITPendingBit ~C C | iSPIx 5 ½
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iSPI_I2S_IT ª
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Xitpos ! R Ø
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..\STM32F10x_FWLib\src\stm32f10x_usart.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Administrator\Desktop\HCI\USER < @ ` ?ÂUSART_DeInit < = iUSARTx +6 ?°USART_Init = ä= g iUSARTx +6 ú iUSART_InitStruct 16 ç Xtmpreg 1 T Xapbclock 1 ZXintegerdivider 1 XXfractionaldivider 1 YXusartxbase 1 WYRCC_ClocksStatus 1 L ?ÓUSART_StructInit ä= ü= S iUSART_InitStruct 16 Ô ?¹¯USART_ClockInit ü= > 3 iUSARTx +6 Á iUSART_ClockInitStruct 76 ® Xtmpreg 1 P ?ÎUSART_ClockStructInit > *> iUSART_ClockInitStruct 76 ?ÇàUSART_Cmd *> B> iUSARTx +6 iNewState u ?ë
USART_ITConfig B> > ë iUSARTx +6 b iUSART_IT ! O iNewState < Zusartreg 1 ) Zitpos 1 Zitmask 1 Zusartxbase 1 ð ?ÈÁUSART_DMACmd > > × iUSARTx +6 Ý iUSART_DMAReq ! Ê iNewState · ?ÝUSART_SetAddress > °> Ã iUSARTx +6 ¤ iUSART_Address ?çôUSART_WakeUpConfig °> Â> ¯ iUSARTx +6 ~ iUSART_WakeUp ! k ?¸ USART_ReceiverWakeUpCmd Â> Ú> iUSARTx +6 X iNewState E ?¤
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¤USART_LINBreakDetectLengthConfig Ú> ì> iUSARTx +6 2 iUSART_LINBreakDetectLength ! ?ê
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·USART_LINCmd ì> ? s iUSARTx +6 iNewState ù ?® ÑUSART_SendData ? ? _ iUSARTx +6 æ iData ! Ó >þ â
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USART_ReceiveData ! ? ? K iUSARTx +6 À ^__result ! P ?´ òUSART_SendBreak ? ? 7 iUSARTx +6 ? USART_SetGuardTime ? 0? # iUSARTx +6 iUSART_GuardTime ?Ú USART_SetPrescaler 0? @? iUSARTx +6 t iUSART_Prescaler a ?¦©USART_SmartCardCmd @? X? û iUSARTx +6 N iNewState ; ?öÂUSART_SmartCardNACKCmd X? p? ç iUSARTx +6 ( iNewState ?ÃÜUSART_HalfDuplexCmd p? ? Ó iUSARTx +6 iNewState ï ?ûUSART_OverSampling8Cmd ? ? ¿ iUSARTx +6 Ü iNewState É ?âUSART_OneBitMethodCmd ? ¶? « iUSARTx +6 ¶ iNewState £ ?²³USART_IrDAConfig ¶? È? iUSARTx +6 iUSART_IrDAMode ! } ?ùÆUSART_IrDACmd È? à? iUSARTx +6 j iNewState W >óë USART_GetFlagStatus O à? ú? o iUSARTx +6 D iUSART_FLAG ! 1 ^__result O PXbitstatus O P ?¾ USART_ClearFlag ú? @ [ iUSARTx +6 iUSART_FLAG ! >æÁ
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USART_GetITStatus b @ `@ ; iUSARTx +6 ø iUSART_IT ! å ^__result b PRXbitpos 1 TXitmask 1 SXusartreg 1 U
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Xbitstatus b P ?×USART_ClearITPendingBit `@ @ iUSARTx +6 Ò iUSART_IT ! ¿ Xbitpos ! RXitmask ! S ´" ..\STM32F10x_FWLib\src\stm32f10x_tim.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Administrator\Desktop\HCI\USER p. < ?»zTIM_DeInit p. 0 iTIMx É6 í+ ?¡âTIM_TimeBaseInit 0 0 iTIMx É6 Ú+ iTIM_TimeBaseInitStruct Ï6 Ç+ Xtmpcr1 ! R ?TIM_OC1Init 0 1 ç iTIMx É6 ´+ iTIM_OCInitStruct Õ6 ¡+ Xtmpccmrx ! TXtmpccer ! RXtmpcr2 ! S ?êTIM_OC2Init 1 °1 Ç iTIMx É6 + iTIM_OCInitStruct Õ6 {+ Xtmpccmrx ! TXtmpccer ! RXtmpcr2 ! S ?¼TIM_OC3Init °1 F2 § iTIMx É6 h+ iTIM_OCInitStruct Õ6 U+ Xtmpccmrx ! TXtmpccer ! RXtmpcr2 ! S ?TIM_OC4Init F2 ü2 iTIMx É6 B+ iTIM_OCInitStruct Õ6 /+ Xtmpccmrx ! RXtmpccer ! SXtmpcr2 ! T ?åóTIM_SetIC4Prescaler ü2 3 s iTIMx É6 + iTIM_ICPSC ! + ? TI4_Config 3 3 S iTIMx É6 ö* iTIM_ICPolarity ! ã* iTIM_ICSelection ! Ð* iTIM_ICFilter ! ½* Xtmpccmr2 ! RXtmpccer ! Q
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Xtmp ! V ?ÚÝTIM_SetIC3Prescaler 3 ª3 ? iTIMx É6 ª* iTIM_ICPSC ! * ?
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í TI3_Config ª3 $4 iTIMx É6 * iTIM_ICPolarity ! q* iTIM_ICSelection ! ^* iTIM_ICFilter ! K* Xtmpccmr2 ! RXtmpccer ! Q
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Xtmp ! V ?Ï
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ÇTIM_SetIC2Prescaler $4 >4 iTIMx É6 8* iTIM_ICPSC ! %* ?ø ¼ TI2_Config >4 À4 ë iTIMx É6 * iTIM_ICPolarity ! ÿ) iTIM_ICSelection ! ì) iTIM_ICFilter ! Ù) Xtmpccmr1 ! RXtmpccer ! Q
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Xtmp ! V ?Ä ±TIM_SetIC1Prescaler À4 Ò4 × iTIMx É6 Æ) iTIM_ICPSC ! ³) ?à TI1_Config Ò4 >5 · iTIMx É6 ) iTIM_ICPolarity ! ) iTIM_ICSelection ! z) iTIM_ICFilter ! g) Xtmpccmr1 ! RXtmpccer ! Q
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?ªËTIM_ICInit >5 Ô5 iTIMx É6 T) iTIM_ICInitStruct Û6 A) ?³TIM_PWMIConfig Ô5 P6 w iTIMx É6 .) iTIM_ICInitStruct Û6 ) Zicoppositepolarity ! ) Zicoppositeselection ! õ( ?ÈTIM_BDTRConfig P6 p6 c iTIMx É6 â( iTIM_BDTRInitStruct á6 Ï( ?ÐàTIM_TimeBaseStructInit p6 6 O iTIM_TimeBaseInitStruct Ï6 ¼( ?ðTIM_OCStructInit 6 6 ; iTIM_OCInitStruct Õ6 ©( ?ÒTIM_ICStructInit 6 ¨6 ' iTIM_ICInitStruct Û6 ( ?TIM_BDTRStructInit ¨6 Ð6 iTIM_BDTRInitStruct á6 ( ?Ö¦TIM_Cmd Ð6 è6 ÿ iTIMx É6 p( iNewState ]( ? ¿TIM_CtrlPWMOutputs è6 7 ë iTIMx É6 J( iNewState 7( ?õèTIM_ITConfig 7 7 × iTIMx É6 $( iTIM_IT ! ( iNewState þ' ?ÅTIM_GenerateEvent 7 7 à iTIMx É6 ë' iTIM_EventSource ! Ø' ?ª©TIM_DMAConfig 7 &7 ¯ iTIMx É6 Å' iTIM_DMABase ! ²' iTIM_DMABurstLength ! ' ?ÄTIM_DMACmd &7 87 iTIMx É6 ' iTIM_DMASource ! y' iNewState f' ?ÀÝTIM_InternalClockConfig 87 D7 iTIMx É6 S' ?Í TIM_SelectInputTrigger D7 V7 s iTIMx É6 @' iTIM_InputTriggerSource ! -' Xtmpsmcr ! Q ?ðTIM_ITRxExternalClockConfig V7 n7 S iTIMx É6 ' iTIM_InputTriggerSource ! ' ?TIM_TIxExternalClockConfig n7 ¬7 3 iTIMx É6 ô& iTIM_TIxExternalCLKSource ! á& iTIM_ICPolarity ! Î& iICFilter ! »& ?±üTIM_ETRConfig ¬7 È7 iTIMx É6 ¨& iTIM_ExtTRGPrescaler ! & iTIM_ExtTRGPolarity ! & iExtTRGFilter ! o& Xtmpsmcr ! Q ?гTIM_ETRClockMode1Config È7 þ7 ó iTIMx É6 \& iTIM_ExtTRGPrescaler ! I& iTIM_ExtTRGPolarity ! 6& iExtTRGFilter ! #& Xtmpsmcr ! T ?Þ ÝTIM_ETRClockMode2Config þ7 8 Ó iTIMx É6 & iTIM_ExtTRGPrescaler ! ý% iTIM_ExtTRGPolarity ! ê% iExtTRGFilter ! ×% ?Æ TIM_PrescalerConfig 8 $8 ¿ iTIMx É6 Ä% iPrescaler ! ±% iTIM_PSCReloadMode ! % ?ª ¯ TIM_CounterModeConfig $8 68 « iTIMx É6 % iTIM_CounterMode ! x% Xtmpcr1 ! Q ?ë ð TIM_EncoderInterfaceConfig 68 x8 iTIMx É6 e% iTIM_EncoderMode ! R% iTIM_IC1Polarity ! ?% iTIM_IC2Polarity ! ,% Xtmpsmcr ! Q
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Xtmpccmr1 ! R Xtmpccer ! S ?Ð £
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TIM_ForcedOC1Config x8 8 w iTIMx É6 % iTIM_ForcedAction ! % Xtmpccmr1 ! Q ?µ!»
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TIM_ForcedOC2Config 8 ¤8 c iTIMx É6 ó$ iTIM_ForcedAction ! à$ Xtmpccmr1 ! Q ?"Ó
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TIM_ForcedOC3Config ¤8 ¶8 O iTIMx É6 Í$ iTIM_ForcedAction ! º$ Xtmpccmr2 ! Q ?ÿ"ë
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TIM_ForcedOC4Config ¶8 Ð8 ; iTIMx É6 §$ iTIM_ForcedAction ! $ Xtmpccmr2 ! Q ?Ë# TIM_ARRPreloadConfig Ð8 è8 ' iTIMx É6 $ iNewState n$ ?$ TIM_SelectCOM è8 9 iTIMx É6 [$ iNewState H$ ?×$² TIM_SelectCCDMA 9 9 ÿ iTIMx É6 5$ iNewState "$ ?£%Ë TIM_CCPreloadControl 9 09 ë iTIMx É6 $ iNewState ü# ?&å TIM_OC1PreloadConfig 09 B9 × iTIMx É6 é# iTIM_OCPreload ! Ö# Xtmpccmr1 ! Q ?é&þ TIM_OC2PreloadConfig B9 \9 Ã iTIMx É6 Ã# iTIM_OCPreload ! °# Xtmpccmr1 ! Q ?Ì' TIM_OC3PreloadConfig \9 n9 ¯ iTIMx É6 # iTIM_OCPreload ! # Xtmpccmr2 ! Q ?¯(® TIM_OC4PreloadConfig n9 9 iTIMx É6 w# iTIM_OCPreload ! d# Xtmpccmr2 ! Q ?)Æ TIM_OC1FastConfig 9 9 iTIMx É6 Q# iTIM_OCFast ! ># Xtmpccmr1 ! Q ?é)à TIM_OC2FastConfig 9 ´9 s iTIMx É6 +# iTIM_OCFast ! # Xtmpccmr1 ! Q ?Æ*ù TIM_OC3FastConfig ´9 Æ9 _ iTIMx É6 # iTIM_OCFast ! ò" Xtmpccmr2 ! Q ?£+ TIM_OC4FastConfig Æ9 à9 K iTIMx É6 ß" iTIM_OCFast ! Ì" Xtmpccmr2 ! Q ?ÿ+« TIM_ClearOC1Ref à9 ò9 7 iTIMx É6 ¹" iTIM_OCClear ! ¦" Xtmpccmr1 ! Q ?Û,Å TIM_ClearOC2Ref ò9
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: # iTIMx É6 " iTIM_OCClear ! " Xtmpccmr1 ! Q ?·-Ý TIM_ClearOC3Ref
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: : iTIMx É6 m" iTIM_OCClear ! Z" Xtmpccmr2 ! Q ?.õ TIM_ClearOC4Ref : 4: û iTIMx É6 G" iTIM_OCClear ! 4" Xtmpccmr2 ! Q ?÷.TIM_OC1PolarityConfig 4: F: ç iTIMx É6 !" iTIM_OCPolarity ! " Xtmpccer ! Q ?Ý/¤TIM_OC1NPolarityConfig F: X: Ó iTIMx É6 û! iTIM_OCNPolarity ! è! Xtmpccer ! Q ?Á0¼TIM_OC2PolarityConfig X: r: ¿ iTIMx É6 Õ! iTIM_OCPolarity ! Â! Xtmpccer ! Q ?§1ÓTIM_OC2NPolarityConfig r: : « iTIMx É6 ¯! iTIM_OCNPolarity ! ! Xtmpccer ! Q ?2ëTIM_OC3PolarityConfig : ¦: iTIMx É6 ! iTIM_OCPolarity ! v! Xtmpccer ! Q ?ñ2TIM_OC3NPolarityConfig ¦: À: iTIMx É6 c! iTIM_OCNPolarity ! P! Xtmpccer ! Q ?Õ3TIM_OC4PolarityConfig À: Ú: o iTIMx É6 =! iTIM_OCPolarity ! *! Xtmpccer ! Q ?¹4¶TIM_CCxCmd Ú: ø: O iTIMx É6 ! iTIM_Channel ! ! iTIM_CCx ! ñ Xtmp ! S ?5ÔTIM_CCxNCmd ø: ; / iTIMx É6 Þ iTIM_Channel ! Ë iTIM_CCxN ! ¸ Xtmp ! S ?6ýTIM_SelectOCxM ; h; iTIMx É6 ¥ iTIM_Channel ! iTIM_OCMode ! Ztmp 1 l Ztmp1 ! Y ?é6¬TIM_UpdateDisableConfig h; ; û iTIMx É6 F iNewState 3 ?À7ÈTIM_UpdateRequestConfig ; ; ç iTIMx É6 iTIM_UpdateSource ! ?8àTIM_SelectHallSensor ; °; Ó iTIMx É6 ú iNewState ç ?Ü8úTIM_SelectOnePulseMode °; Â; ¿ iTIMx É6 Ô iTIM_OPMode ! Á ?±9TIM_SelectOutputTrigger Â; Ô; « iTIMx É6 ® iTIM_TRGOSource ! ?:±TIM_SelectSlaveMode Ô; æ; iTIMx É6 iTIM_SlaveMode ! u ?Ý:ÆTIM_SelectMasterSlaveMode æ; ø; iTIMx É6 b iTIM_MasterSlaveMode ! O ?¢;ØTIM_SetCounter ø; ü; o iTIMx É6 < iCounter ! ) ?í;æTIM_SetAutoreload ü; < [ iTIMx É6 iAutoreload ! ?´<ôTIM_SetCompare1 < < G iTIMx É6 ð iCompare1 ! Ý ?û<TIM_SetCompare2 < < 3 iTIMx É6 Ê iCompare2 ! · ?Â=TIM_SetCompare3 < < iTIMx É6 ¤ iCompare3 ! ?>TIM_SetCompare4 < < iTIMx É6 ~ iCompare4 ! k ?Ô>TIM_SetClockDivision < $< ÷ iTIMx É6 X iTIM_CKD ! E > ?
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TIM_GetCapture1 ! $< *< ã iTIMx É6 2 ^__result ! P >ì?¦
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TIM_GetCapture2 ! *< 0< Ï iTIMx É6 ^__result ! P >¸@³
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TIM_GetCapture3 ! 0< 6< » iTIMx É6 ^__result ! P >AÀ
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TIM_GetCapture4 ! 6< >< § iTIMx É6 ù ^__result ! P >ÏAÍ
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TIM_GetCounter ! >< D< iTIMx É6 æ ^__result ! P >BÚ
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TIM_GetPrescaler ! D< J< iTIMx É6 Ó ^__result ! P >Cü TIM_GetFlagStatus O J< \< k iTIMx É6 À iTIM_FLAG ! ^__result O PXbitstatus b P ?ÕC¨TIM_ClearFlag \< b< W iTIMx É6 iTIM_FLAG ! >éDÈ
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TIM_GetITStatus b b< < 7 iTIMx É6 t iTIM_IT ! a ^__result b P Xbitstatus b PXitstatus ! SXitenable ! T
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?´EôTIM_ClearITPendingBit < < iTIMx É6 N iTIM_IT ! ; Ì ..\STM32F10x_FWLib\src\stm32f10x_rcc.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Administrator\Desktop\HCI\USER Ì* D. ?ÙRCC_DeInit Ì* + . ?âRCC_HSEConfig + R+ . iRCC_HSE 1 -1 >ç®
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RCC_GetFlagStatus O R+ + _. iRCC_FLAG 1 ^__result O P6Xtmp 1 RXstatusreg 1 SXbitstatus O P
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>å° RCC_WaitForHSEStartUp ¾ + Â+ ?. ^__result ¾ P6YStartUpCounter 7 pXstatus ¾ TXHSEStatus O U
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?ÆÎRCC_AdjustHSICalibrationValue Â+ Ö+ +. iHSICalibrationValue 1 Xtmpreg 1 P ?ùâRCC_HSICmd Ö+ Ü+ . iNewState ô0 ?ÙúRCC_PLLConfig Ü+ ô+ . iRCC_PLLSource 1 á0 iRCC_PLLMul 1 Î0 Xtmpreg 1 P ?RCC_PLLCmd ô+ ú+ ï- iNewState »0 ?Ý´RCC_SYSCLKConfig ú+ , Û- iRCC_SYSCLKSource 1 ¨0 Xtmpreg 1 P >Ë RCC_GetSYSCLKSource , , Ç- ^__result P ?çàRCC_HCLKConfig , (, ³- iRCC_SYSCLK 1 0 Xtmpreg 1 P ?¯úRCC_PCLK1Config (, :, - iRCC_HCLK 1 0 Xtmpreg 1 P ?÷RCC_PCLK2Config :, N, - iRCC_HCLK 1 o0 Xtmpreg 1 P ?½ ¼RCC_ITConfig N, h, w- iRCC_IT \0 iNewState I0 ?þ ØRCC_USBCLKConfig h, n, c- iRCC_USBCLKSource 1 60 ?È
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þRCC_ADCCLKConfig n, , O- iRCC_PCLK2 1 #0 Xtmpreg 1 P ?ý
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½RCC_LSEConfig , ¬, ;- iRCC_LSE 0 ?° ÞRCC_LSICmd ¬, ², '- iNewState ý/ ?ñ ïRCC_RTCCLKConfig ², ¾, - iRCC_RTCCLKSource 1 ê/ ?§ ýRCC_RTCCLKCmd ¾, Æ, ÿ, iNewState ×/ ?£ RCC_GetClocksFreq Æ, - ß, iRCC_Clocks 7 Ä/ Xtmp 1 QXpllmull 1 RXpllsource 1 TXpresc 1 S
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?ù ¨RCC_AHBPeriphClockCmd - - Ë, iRCC_AHBPeriph 1 ±/ iNewState / ?ÑÇRCC_APB2PeriphClockCmd - º- ·, iRCC_APB2Periph 1 / iNewState x/ ?©æRCC_APB1PeriphClockCmd º- Ô- £, iRCC_APB1Periph 1 e/ iNewState R/ ?¡ RCC_APB2PeriphResetCmd Ô- î- , iRCC_APB2Periph 1 ?/ iNewState ,/ ?ÙÀ RCC_APB1PeriphResetCmd î- . {, iRCC_APB1Periph 1 / iNewState / ?Õ RCC_BackupResetCmd . . g, iNewState ó. ?×â RCC_ClockSecuritySystemCmd . . S, iNewState à. ?
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RCC_MCOConfig . . ?, iRCC_MCO Í. ?¯Û
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RCC_ClearFlag . *. +, >ú
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RCC_GetITStatus b *. >. , iRCC_IT º. ^__result b PXbitstatus b P ?̨ RCC_ClearITPendingBit >. D. , iRCC_IT §. ¸ ..\STM32F10x_FWLib\src\stm32f10x_rcc.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Administrator\Desktop\HCI\USER YAPBAHBPrescTable 7 YADCPrescTable 7 0 ä ..\STM32F10x_FWLib\src\stm32f10x_gpio.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Administrator\Desktop\HCI\USER t' ¤* ?¾lGPIO_DeInit t' ( Ä2 iGPIOx *8 É5 ?ãGPIO_AFIODeInit ( 4( ¤2 ?GPIO_Init 4( F) 2 iGPIOx *8 ¶5 iGPIO_InitStruct 08 £5 Zcurrentmode 1 5 Zcurrentpin 1 }5 Zpinpos 1 j5 Zpos 1 W5 Ztmpreg 1 D5 Zpinmask 1 15 ?ØGPIO_StructInit F) V) p2 iGPIO_InitStruct 08 5 >Ñ GPIO_ReadInputDataBit V) h) \2 iGPIOx *8 5 iGPIO_Pin ! ø4 ^__result PXbitstatus P >¡±
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GPIO_ReadInputData ! h) p) H2 iGPIOx *8 å4 ^__result ! P >À GPIO_ReadOutputDataBit p) ) 42 iGPIOx *8 Ò4 iGPIO_Pin ! ¿4 ^__result PXbitstatus P >ì×
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GPIO_ReadOutputData ! ) ) 2 iGPIOx *8 ¬4 ^__result ! P ?±æGPIO_SetBits ) ) 2 iGPIOx *8 4 iGPIO_Pin ! 4 ?øöGPIO_ResetBits ) ) ø1 iGPIOx *8 s4 iGPIO_Pin ! `4 ?ÏGPIO_WriteBit ) ) ä1 iGPIOx *8 M4 iGPIO_Pin ! :4 iBitVal )3 '4 ? ¡GPIO_Write ) ) Ð1 iGPIOx *8 4 iPortVal ! 4 ?ê °GPIO_PinLockConfig ) ²) ¼1 iGPIOx *8 î3 iGPIO_Pin ! Û3 Ztmp 1 È3 ?Ù
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ÎGPIO_EventOutputConfig ²) Ì) ¨1 iGPIO_PortSource µ3 iGPIO_PinSource ¢3 Xtmpreg 1 P ? ãGPIO_EventOutputCmd Ì) Ò) 1 iNewState 3 ?¦ ¥GPIO_PinRemapConfig Ò) \* t1 iGPIO_Remap 1 |3 iNewState i3 Ztmp 1 V3 Ztmp1 1 C3 Ztmpreg 1 03 Ztmpmask 1 3 ? áGPIO_EXTILineConfig \* * T1 iGPIO_PortSource
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3 iGPIO_PinSource ÷2 Xtmp 1 R ?ä öGPIO_ETH_MediaInterfaceConfig * ¤* @1 iGPIO_ETH_MediaInterface 1 ä2 , ..\STM32F10x_FWLib\src\misc.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Administrator\Desktop\HCI\USER & `' ð ?Î`NVIC_PriorityGroupConfig & ¢& :6 iNVIC_PriorityGroup 1 ù6 ?¾pNVIC_Init ¢& ' 6 iNVIC_InitStruct ¸8 æ6 Ztmppriority 1 Ó6 Ztmppre 1 À6 Ztmpsub 1 6 ?NVIC_SetVectorTable ' ' 6 iNVIC_VectTab 1 6 iOffset 1 6 ?â¯NVIC_SystemLPConfig ' 8' ò5 iLowPowerMode t6 iNewState a6 ?«ÇSysTick_CLKSourceConfig 8' `' Ü5 iSysTick_CLKSource 1 N6 ..\CORE\startup_stm32f10x_hd.s ARM Assembler, 5.03 [Build 24] C:\Users\Administrator\Desktop\HCI\USER X& & ´ Reset_Handler X& `& NMI_Handler `& b& HardFault_Handler b& d& MemManage_Handler d& f& BusFault_Handler f& h& UsageFault_Handler h& j& SVC_Handler j& l& DebugMon_Handler l& n& PendSV_Handler n& p& SysTick_Handler p& r& Default_Handler r& t& ..\SYSTEM\delay\delay.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Administrator\Desktop\HCI\USER % F& ! ?6delay_init % º% 67 ?Ötdelay_us º% & "7 inus l i7 Xtemp l P$ ?delay_ms & F& 7 inms z V7 Xtemp l P$ ..\SYSTEM\delay\delay.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Administrator\Desktop\HCI\USER Yfac_us Yfac_ms z ð ..\HARDWARE\RS232\RS232.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Administrator\Desktop\HCI\USER $ v% à! ?õRS232_init2 $ °$ 8 YGPIO_InitStructure ô2 xYUSART_InitStructure ÿ+ hYNVIC_InitStructure E4 d ?Î-RS232_init3 °$ (% Þ7 YGPIO_InitStructure ô2 xYUSART_InitStructure ÿ+ h ?þXRS232_Send_Data (% D% ¾7 ix a8 >½aR232_Receive_Data D% b% 7 ___result N8 ?ñhUSART2_IRQHandler b% v% |7 Xdata T
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..\HARDWARE\AD421\AD421.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Administrator\Desktop\HCI\USER # ü# <# ?»AD421_init # p# 8 YGPIO_InitStructure ô2 x ?AD421_data p# ü# t8 ima µ8 Xk z W
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Xi z T:Xj z V ..\HARDWARE\ADC\ADC.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Administrator\Desktop\HCI\USER 8" # <$ ?ÐAdc_Init 8" ¼" 9 YADC_InitStructure µ( hYGPIO_InitStructure ô2 d >/Get_Adc z ¼" ê" ë8 ich i9 ^__result z P, >;Get_Adc_Average z ê" # È8 ich V9 itimes C9 ^__result z P*Xtemp_val l U
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Xt V à ..\HARDWARE\RS485\RS485.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Administrator\Desktop\HCI\USER $" & ?´ USART1_IRQHandler : Â; Zres = ?çUART4_IRQHandler : l ¢; Zres
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= ?+UART5_IRQHandler l ; Zres ÷< ?;RS485_Init4 V J; YGPIO_InitStructure ô2 xYUSART_InitStructure ÿ+ hYNVIC_InitStructure E4 d ?iRS485_Init5 V ; YGPIO_InitStructure ô2 xYUSART_InitStructure ÿ+ hYNVIC_InitStructure E4 d ?úRS485_Init1 È Ú: YGPIO_InitStructure ô2 xYUSART_InitStructure ÿ+ hYNVIC_InitStructure E4 d ?ÇÇRS485_Send_Data1 È º: ibuf G9 ä< ilen Ñ< Xt T ?ÖRS485_Send_Data4 \ : ibuf G9 ¾< ilen «< Xt T ?áåRS485_Send_Data5 \ ¦ z: ibuf G9 < ilen
< Xt T ?ÁöRS485_Receive_Data ¦ ! N: ibuf G9 r< ilen G9 _< Zrxlen L< Zi 9< ?rx ! È! : Zcount z < ó Yrs485buf è`
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Ytable T ?ï§read_data È! ú! Ý9 Xcount TXtp Uà > Ytable U´ ? ³tx1 ú! " ½9 ich G9 < ?» ¸tx4 " " 9 ich G9 õ; ?á ½tx5 " $" |9 ich G9 â; ¸ ..\HARDWARE\RS485\RS485.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Administrator\Desktop\HCI\USER pRS485_RX_CNT pkey pRS485_RX_BUF <9 4 ..\HARDWARE\FM25V02\FM25V02.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Administrator\Desktop\HCI\USER ô * ?äFM25V02_write h p= idata É= iaddr16 z ¶= Xhaddr V Xladdr W >ÚFM25V02_read h ¤ P= iaddr16 z £= ^__result P8Xdata U0Xhaddr V
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Xladdr W ?(decode ¤ ô 0= idata =
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Ytable h ä ..\HARDWARE\ERROR\ERROR.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Administrator\Desktop\HCI\USER ¸ ð* ?»Error_init ¸ Þ ý= YGPIO_InitStructure ô2 x ?åError_out Þ Ü= ia > ..\HARDWARE\PWM\PWM.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Administrator\Desktop\HCI\USER ´ ° + ?»TIM8_GPIO_init ´ ä > YGPIO_InitStructure ô2 x ?¬TIM8_CH3 ä J h> ib z ù> ic z æ> YTIM_TimeBaseStructure - hYTIM_OCInitStructure . X ?9TIM8_CH4 J ° 0> ib z Ó> ic z À> YTIM_TimeBaseStructure - hYTIM_OCInitStructure . X x ..\HARDWARE\hcs2022\hcs2022.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Administrator\Desktop\HCI\USER Ø 4- float ? wr_com Ø ( È? idata !@ Xlowbyte VXhighbyte WXtempdata XXstartbyte Y
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Xj U ?¤clear ( 8 ¨? ?£ wr_data2 8 ? idata @ Xlowbyte VXhighbyte WXtempdata XXstartbyte Y
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Xj U ?Ì3wr_data1 h? is Ù9 û? ?í:hcs2022_init H? ?ùlsample ? ich è? Ytable LXtemp Y<Xadcx z TXx [RXy HXm D¾Xn @æ ..\HARDWARE\SPI\spi.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Administrator\Desktop\HCI\USER ä  t/ ?ÑSPI1_Init ä A YGPIO_InitStructure ô2 xYSPI_InitStructure "* d ?¦*SPI2_Init 0 Í@ YGPIO_InitStructure ô2 xYSPI_InitStructure "* d ?ûOSPI3_Init 0 Ø @ YGPIO_InitStructure ô2 xYSPI_InitStructure "* d >ÜxSPI1_ReadWriteByte Ø & u@ iTxData ÕA ___result ¯A Zretry ÂA >¾SPI2_ReadWriteByte & t U@ iTxData A ___result vA Zretry A > SPI3_ReadWriteByte t  4@ iTxData cA ___result =A Zretry PA 8 ..\HARDWARE\KEY\key.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Administrator\Desktop\HCI\USER $ Ø ð1 ?µ KEY_Init $ \ B YGPIO_InitStructure ô2 x >ë.key_scan1 \ `
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B ^__result P >¹6key_scan ` Ø èA ___result QB ¸R Ö Zi >B È ..\HARDWARE\KEY\key.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Administrator\Desktop\HCI\USER pflag1 pflag2 pflag3 px py d system_stm32f10x.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Administrator\Desktop\HCI\USER H
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@9 ?ÉÛ SetSysClockTo72 H
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ÄB YStartUpCounter j: xYHSEStatus j: t ?ê£ SetSysClock $ ¤B ?ÔSystemInit $ r B ?æ²SystemCoreClockUpdate r dB Xtmp 1 QXpllmull 1 PXpllsource 1 R ¤ system_stm32f10x.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Administrator\Desktop\HCI\USER pSystemCoreClock 1 pAHBPrescTable b: ¸ stm32f10x_it.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Administrator\Desktop\HCI\USER ,
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F
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¬: ? NMI_Handler ,
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.
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C ?»!HardFault_Handler .
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2
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pC ?á)MemManage_Handler 2
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6
|
\C ?2BusFault_Handler 6
|
:
|
HC ?:UsageFault_Handler :
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>
|
4C ?ÍBSVC_Handler >
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@
|
C ?òFDebugMon_Handler @
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B
|
C ?JPendSV_Handler B
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D
|
øB ?¹NSysTick_Handler D
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F
|
äB main.c ARM C/C++ Compiler, 5.03 [Build 24] C:\Users\Administrator\Desktop\HCI\USER Ì Ä> int >main mÌ C ]__result mPZstate ÍC Xf z YXdp z ZXb [Zdata ¹C Xct p\receive_usart2 \receive_usart3 { ..\STM32F10x_FWLib\inc\ ..\STM32F10x_FWLib\src\stm32f10x_adc.c stm32f10x_adc.h stm32f10x_rcc.h è = ..\STM32F10x_FWLib\src\stm32f10x_adc.c C ³ !' !) !( '4 *!*!$ " "%!" *!(!3-'!-'-'3-*! *!*!*!%!"(!.3-'!E?
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( B9U %!3 { ..\STM32F10x_FWLib\inc\ ..\STM32F10x_FWLib\src\stm32f10x_spi.c stm32f10x_spi.h stm32f10x_rcc.h Ô = ..\STM32F10x_FWLib\src\stm32f10x_spi.c @ ÷ !' !) !" l)& += & ) "NS "#(N *'*' $$
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} } } } À } T \ t B T 0CR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF) 3CR1_DISCEN_Set ((uint32_t)0x00000800) 4CR1_DISCEN_Reset ((uint32_t)0xFFFFF7FF) 7CR1_JAUTO_Set ((uint32_t)0x00000400) 8CR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF) ;CR1_JDISCEN_Set ((uint32_t)0x00001000) <CR1_JDISCEN_Reset ((uint32_t)0xFFFFEFFF) ?CR1_AWDCH_Reset ((uint32_t)0xFFFFFFE0) BCR1_AWDMode_Reset ((uint32_t)0xFF3FFDFF) ECR1_CLEAR_Mask ((uint32_t)0xFFF0FEFF) HCR2_ADON_Set ((uint32_t)0x00000001) ICR2_ADON_Reset ((uint32_t)0xFFFFFFFE) LCR2_DMA_Set ((uint32_t)0x00000100) MCR2_DMA_Reset ((uint32_t)0xFFFFFEFF) PCR2_RSTCAL_Set ((uint32_t)0x00000008) SCR2_CAL_Set ((uint32_t)0x00000004) VCR2_SWSTART_Set ((uint32_t)0x00400000) YCR2_EXTTRIG_Set ((uint32_t)0x00100000) ZCR2_EXTTRIG_Reset ((uint32_t)0xFFEFFFFF) ]CR2_EXTTRIG_SWSTART_Set ((uint32_t)0x00500000) ^CR2_EXTTRIG_SWSTART_Reset ((uint32_t)0xFFAFFFFF) aCR2_JEXTSEL_Reset ((uint32_t)0xFFFF8FFF) dCR2_JEXTTRIG_Set ((uint32_t)0x00008000) eCR2_JEXTTRIG_Reset ((uint32_t)0xFFFF7FFF) hCR2_JSWSTART_Set ((uint32_t)0x00200000) kCR2_JEXTTRIG_JSWSTART_Set ((uint32_t)0x00208000) lCR2_JEXTTRIG_JSWSTART_Reset ((uint32_t)0xFFDF7FFF) oCR2_TSVREFE_Set ((uint32_t)0x00800000) pCR2_TSVREFE_Reset ((uint32_t)0xFF7FFFFF) sCR2_CLEAR_Mask ((uint32_t)0xFFF1F7FD) vSQR3_SQ_Set ((uint32_t)0x0000001F) wSQR2_SQ_Set ((uint32_t)0x0000001F) xSQR1_SQ_Set ((uint32_t)0x0000001F) {SQR1_CLEAR_Mask ((uint32_t)0xFF0FFFFF) ~JSQR_JSQ_Set ((uint32_t)0x0000001F) JSQR_JL_Set ((uint32_t)0x00300000) JSQR_JL_Reset ((uint32_t)0xFFCFFFFF)
SMPR1_SMP_Set ((uint32_t)0x00000007) SMPR2_SMP_Set ((uint32_t)0x00000007) JDR_Offset ((uint8_t)0x28) DR_ADDRESS ((uint32_t)0x4001244C) 1CR1_SPE_Set ((uint16_t)0x0040) 2CR1_SPE_Reset ((uint16_t)0xFFBF) 5I2SCFGR_I2SE_Set ((uint16_t)0x0400) 6I2SCFGR_I2SE_Reset ((uint16_t)0xFBFF) 9CR1_CRCNext_Set ((uint16_t)0x1000) <CR1_CRCEN_Set ((uint16_t)0x2000) =CR1_CRCEN_Reset ((uint16_t)0xDFFF) @CR2_SSOE_Set ((uint16_t)0x0004) ACR2_SSOE_Reset ((uint16_t)0xFFFB) DCR1_CLEAR_Mask ((uint16_t)0x3040) EI2SCFGR_CLEAR_Mask ((uint16_t)0xF040) HSPI_Mode_Select ((uint16_t)0xF7FF) II2S_Mode_Select ((uint16_t)0x0800) LI2S2_CLOCK_SRC ((uint32_t)(0x00020000)) MI2S3_CLOCK_SRC ((uint32_t)(0x00040000)) NI2S_MUL_MASK ((uint32_t)(0x0000F000)) OI2S_DIV_MASK ((uint32_t)(0x000000F0)) /CR1_UE_Set ((uint16_t)0x2000) 0CR1_UE_Reset ((uint16_t)0xDFFF) 2CR1_WAKE_Mask ((uint16_t)0xF7FF) 4CR1_RWU_Set ((uint16_t)0x0002) 5CR1_RWU_Reset ((uint16_t)0xFFFD) 6CR1_SBK_Set ((uint16_t)0x0001) 7CR1_CLEAR_Mask ((uint16_t)0xE9F3) 8CR2_Address_Mask ((uint16_t)0xFFF0) :CR2_LINEN_Set ((uint16_t)0x4000) ;CR2_LINEN_Reset ((uint16_t)0xBFFF) =CR2_LBDL_Mask ((uint16_t)0xFFDF) >CR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF) ?CR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF) ACR3_SCEN_Set ((uint16_t)0x0020) BCR3_SCEN_Reset ((uint16_t)0xFFDF) DCR3_NACK_Set ((uint16_t)0x0010) ECR3_NACK_Reset ((uint16_t)0xFFEF) GCR3_HDSEL_Set ((uint16_t)0x0008) HCR3_HDSEL_Reset ((uint16_t)0xFFF7) JCR3_IRLP_Mask ((uint16_t)0xFFFB) KCR3_CLEAR_Mask ((uint16_t)0xFCFF) MCR3_IREN_Set ((uint16_t)0x0002) NCR3_IREN_Reset ((uint16_t)0xFFFD) OGTPR_LSB_Mask ((uint16_t)0x00FF) PGTPR_MSB_Mask ((uint16_t)0xFF00) QIT_Mask ((uint16_t)0x001F) TCR1_OVER8_Set ((u16)0x8000) UCR1_OVER8_Reset ((u16)0x7FFF) XCR3_ONEBITE_Set ((u16)0x0800) YCR3_ONEBITE_Reset ((u16)0xF7FF) 0SMCR_ETR_Mask ((uint16_t)0x00FF) 1CCMR_Offset ((uint16_t)0x0018) 2CCER_CCE_Set ((uint16_t)0x0001) 3CCER_CCNE_Set ((uint16_t)0x0004) /RCC_OFFSET (RCC_BASE - PERIPH_BASE) 4CR_OFFSET (RCC_OFFSET + 0x00) 5HSION_BitNumber 0x00 6CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4)) 9PLLON_BitNumber 0x18 :CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4)) GCSSON_BitNumber 0x13 HCR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4)) MCFGR_OFFSET (RCC_OFFSET + 0x04) PUSBPRE_BitNumber 0x16 QCFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4)) ZBDCR_OFFSET (RCC_OFFSET + 0x20) [RTCEN_BitNumber 0x0F \BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4)) _BDRST_BitNumber 0x10 `BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4)) eCSR_OFFSET (RCC_OFFSET + 0x24) fLSION_BitNumber 0x00 gCSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4)) yCR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF) zCR_HSEBYP_Set ((uint32_t)0x00040000) {CR_HSEON_Reset ((uint32_t)0xFFFEFFFF) |CR_HSEON_Set ((uint32_t)0x00010000) }CR_HSITRIM_Mask ((uint32_t)0xFFFFFF07) CFGR_PLL_Mask ((uint32_t)0xFFC0FFFF) CFGR_PLLMull_Mask ((uint32_t)0x003C0000) CFGR_PLLSRC_Mask ((uint32_t)0x00010000) CFGR_PLLXTPRE_Mask ((uint32_t)0x00020000) CFGR_SWS_Mask ((uint32_t)0x0000000C) CFGR_SW_Mask ((uint32_t)0xFFFFFFFC) CFGR_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F) CFGR_HPRE_Set_Mask ((uint32_t)0x000000F0) CFGR_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF) CFGR_PPRE1_Set_Mask ((uint32_t)0x00000700) CFGR_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF) CFGR_PPRE2_Set_Mask ((uint32_t)0x00003800) CFGR_ADCPRE_Reset_Mask ((uint32_t)0xFFFF3FFF) CFGR_ADCPRE_Set_Mask ((uint32_t)0x0000C000) CSR_RMVF_Set ((uint32_t)0x01000000) £FLAG_Mask ((uint8_t)0x1F) ¦CIR_BYTE2_ADDRESS ((uint32_t)0x40021009) ©CIR_BYTE3_ADDRESS ((uint32_t)0x4002100A) ¬CFGR_BYTE4_ADDRESS ((uint32_t)0x40021007) ¯BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET) 0AFIO_OFFSET (AFIO_BASE - PERIPH_BASE) 5EVCR_OFFSET (AFIO_OFFSET + 0x00) 6EVOE_BitNumber ((uint8_t)0x07) 7EVCR_EVOE_BB (PERIPH_BB_BASE + (EVCR_OFFSET * 32) + (EVOE_BitNumber * 4)) <MAPR_OFFSET (AFIO_OFFSET + 0x04) =MII_RMII_SEL_BitNumber ((u8)0x17) >MAPR_MII_RMII_SEL_BB (PERIPH_BB_BASE + (MAPR_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4)) AEVCR_PORTPINCONFIG_MASK ((uint16_t)0xFF80) BLSB_MASK ((uint16_t)0xFFFF) CDBGAFR_POSITION_MASK ((uint32_t)0x000F0000) DDBGAFR_SWJCFG_MASK ((uint32_t)0xF0FFFFFF) EDBGAFR_LOCATION_MASK ((uint32_t)0x00200000) FDBGAFR_NUMBITS_MASK ((uint32_t)0x00100000) /AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) AsSYSCLK_FREQ_72MHz 72000000 VECT_TAB_OFFSET 0x0 __MISC_H sNVIC_VectTab_RAM ((uint32_t)0x20000000) tNVIC_VectTab_FLASH ((uint32_t)0x08000000) uIS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || ((VECTTAB) == NVIC_VectTab_FLASH)) NVIC_LP_SEVONPEND ((uint8_t)0x10) NVIC_LP_SLEEPDEEP ((uint8_t)0x04) NVIC_LP_SLEEPONEXIT ((uint8_t)0x02) IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || ((LP) == NVIC_LP_SLEEPDEEP) || ((LP) == NVIC_LP_SLEEPONEXIT)) NVIC_PriorityGroup_0 ((uint32_t)0x700) NVIC_PriorityGroup_1 ((uint32_t)0x600) NVIC_PriorityGroup_2 ((uint32_t)0x500) NVIC_PriorityGroup_3 ((uint32_t)0x400) NVIC_PriorityGroup_4 ((uint32_t)0x300) IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || ((GROUP) == NVIC_PriorityGroup_1) || ((GROUP) == NVIC_PriorityGroup_2) || ((GROUP) == NVIC_PriorityGroup_3) || ((GROUP) == NVIC_PriorityGroup_4)) IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) ¢IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF) ¬SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) SysTick_CLKSource_HCLK ((uint32_t)0x00000004) ®IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || ((SOURCE) == SysTick_CLKSource_HCLK_Div8)) __STM32F10x_USART_H kIS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || ((PERIPH) == USART2) || ((PERIPH) == USART3) || ((PERIPH) == UART4) || ((PERIPH) == UART5)) qIS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || ((PERIPH) == USART2) || ((PERIPH) == USART3)) uIS_USART_1234_PERIPH(PERIPH) (((PERIPH) == USART1) || ((PERIPH) == USART2) || ((PERIPH) == USART3) || ((PERIPH) == UART4)) }USART_WordLength_8b ((uint16_t)0x0000) ~USART_WordLength_9b ((uint16_t)0x1000) IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || ((LENGTH) == USART_WordLength_9b)) USART_StopBits_1 ((uint16_t)0x0000) USART_StopBits_0_5 ((uint16_t)0x1000) USART_StopBits_2 ((uint16_t)0x2000) USART_StopBits_1_5 ((uint16_t)0x3000) IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || ((STOPBITS) == USART_StopBits_0_5) || ((STOPBITS) == USART_StopBits_2) || ((STOPBITS) == USART_StopBits_1_5)) USART_Parity_No ((uint16_t)0x0000) USART_Parity_Even ((uint16_t)0x0400) USART_Parity_Odd ((uint16_t)0x0600) IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || ((PARITY) == USART_Parity_Even) || ((PARITY) == USART_Parity_Odd)) ¨USART_Mode_Rx ((uint16_t)0x0004) ©USART_Mode_Tx ((uint16_t)0x0008) ªIS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00)) ²USART_HardwareFlowControl_None ((uint16_t)0x0000) ³USART_HardwareFlowControl_RTS ((uint16_t)0x0100) ´USART_HardwareFlowControl_CTS ((uint16_t)0x0200) µUSART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) ¶IS_USART_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == USART_HardwareFlowControl_None) || ((CONTROL) == USART_HardwareFlowControl_RTS) || ((CONTROL) == USART_HardwareFlowControl_CTS) || ((CONTROL) == USART_HardwareFlowControl_RTS_CTS)) ÂUSART_Clock_Disable ((uint16_t)0x0000) ÃUSART_Clock_Enable ((uint16_t)0x0800) ÄIS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || ((CLOCK) == USART_Clock_Enable)) ÎUSART_CPOL_Low ((uint16_t)0x0000) ÏUSART_CPOL_High ((uint16_t)0x0400) ÐIS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High)) ÚUSART_CPHA_1Edge ((uint16_t)0x0000) ÛUSART_CPHA_2Edge ((uint16_t)0x0200) ÜIS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge)) æUSART_LastBit_Disable ((uint16_t)0x0000) çUSART_LastBit_Enable ((uint16_t)0x0100) èIS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || ((LASTBIT) == USART_LastBit_Enable)) òUSART_IT_PE ((uint16_t)0x0028) óUSART_IT_TXE ((uint16_t)0x0727) ôUSART_IT_TC ((uint16_t)0x0626) õUSART_IT_RXNE ((uint16_t)0x0525) öUSART_IT_IDLE ((uint16_t)0x0424) ÷USART_IT_LBD ((uint16_t)0x0846) øUSART_IT_CTS ((uint16_t)0x096A) ùUSART_IT_ERR ((uint16_t)0x0060) úUSART_IT_ORE ((uint16_t)0x0360) ûUSART_IT_NE ((uint16_t)0x0260) üUSART_IT_FE ((uint16_t)0x0160) ýIS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR)) IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE)) IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS)) USART_DMAReq_Tx ((uint16_t)0x0080) USART_DMAReq_Rx ((uint16_t)0x0040) IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00)) USART_WakeUp_IdleLine ((uint16_t)0x0000) USART_WakeUp_AddressMark ((uint16_t)0x0800) IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || ((WAKEUP) == USART_WakeUp_AddressMark)) ¨USART_LINBreakDetectLength_10b ((uint16_t)0x0000) ©USART_LINBreakDetectLength_11b ((uint16_t)0x0020) ªIS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == USART_LINBreakDetectLength_10b) || ((LENGTH) == USART_LINBreakDetectLength_11b)) µUSART_IrDAMode_LowPower ((uint16_t)0x0004) ¶USART_IrDAMode_Normal ((uint16_t)0x0000) ·IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || ((MODE) == USART_IrDAMode_Normal)) ÁUSART_FLAG_CTS ((uint16_t)0x0200) ÂUSART_FLAG_LBD ((uint16_t)0x0100) ÃUSART_FLAG_TXE ((uint16_t)0x0080) ÄUSART_FLAG_TC ((uint16_t)0x0040) ÅUSART_FLAG_RXNE ((uint16_t)0x0020) ÆUSART_FLAG_IDLE ((uint16_t)0x0010) ÇUSART_FLAG_ORE ((uint16_t)0x0008) ÈUSART_FLAG_NE ((uint16_t)0x0004) ÉUSART_FLAG_FE ((uint16_t)0x0002) ÊUSART_FLAG_PE ((uint16_t)0x0001) ËIS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE)) ÑIS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00)) ÒIS_USART_PERIPH_FLAG(PERIPH,USART_FLAG) ((((*(uint32_t*)&(PERIPH)) != UART4_BASE) && ((*(uint32_t*)&(PERIPH)) != UART5_BASE)) || ((USART_FLAG) != USART_FLAG_CTS)) ÕIS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x0044AA21)) ÖIS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF) ×IS_USART_DATA(DATA) ((DATA) <= 0x1FF) __STM32F10x_TIM_H ©IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM6) || ((PERIPH) == TIM7) || ((PERIPH) == TIM8) || ((PERIPH) == TIM9) || ((PERIPH) == TIM10)|| ((PERIPH) == TIM11)|| ((PERIPH) == TIM12)|| ((PERIPH) == TIM13)|| ((PERIPH) == TIM14)|| ((PERIPH) == TIM15)|| ((PERIPH) == TIM16)|| ((PERIPH) == TIM17)) ¼IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) || ((PERIPH) == TIM8)) ÀIS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || ((PERIPH) == TIM8) || ((PERIPH) == TIM15)|| ((PERIPH) == TIM16)|| ((PERIPH) == TIM17)) ÇIS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM8)) ÏIS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM8) || ((PERIPH) == TIM15)|| ((PERIPH) == TIM16)|| ((PERIPH) == TIM17)) ÚIS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM8) || ((PERIPH) == TIM15)) ãIS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM8) || ((PERIPH) == TIM9) || ((PERIPH) == TIM12)|| ((PERIPH) == TIM15)) îIS_TIM_LIST7_PERIPH(PERIPH) (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM6) || ((PERIPH) == TIM7) || ((PERIPH) == TIM8) || ((PERIPH) == TIM9) || ((PERIPH) == TIM12)|| ((PERIPH) == TIM15)) ûIS_TIM_LIST8_PERIPH(PERIPH) (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM8) || ((PERIPH) == TIM9) || ((PERIPH) == TIM10)|| ((PERIPH) == TIM11)|| ((PERIPH) == TIM12)|| ((PERIPH) == TIM13)|| ((PERIPH) == TIM14)|| ((PERIPH) == TIM15)|| ((PERIPH) == TIM16)|| ((PERIPH) == TIM17)) IS_TIM_LIST9_PERIPH(PERIPH) (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM6) || ((PERIPH) == TIM7) || ((PERIPH) == TIM8) || ((PERIPH) == TIM15)|| ((PERIPH) == TIM16)|| ((PERIPH) == TIM17)) TIM_OCMode_Timing ((uint16_t)0x0000) ¡TIM_OCMode_Active ((uint16_t)0x0010) ¢TIM_OCMode_Inactive ((uint16_t)0x0020) £TIM_OCMode_Toggle ((uint16_t)0x0030) ¤TIM_OCMode_PWM1 ((uint16_t)0x0060) ¥TIM_OCMode_PWM2 ((uint16_t)0x0070) ¦IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || ((MODE) == TIM_OCMode_Active) || ((MODE) == TIM_OCMode_Inactive) || ((MODE) == TIM_OCMode_Toggle)|| ((MODE) == TIM_OCMode_PWM1) || ((MODE) == TIM_OCMode_PWM2)) ¬IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || ((MODE) == TIM_OCMode_Active) || ((MODE) == TIM_OCMode_Inactive) || ((MODE) == TIM_OCMode_Toggle)|| ((MODE) == TIM_OCMode_PWM1) || ((MODE) == TIM_OCMode_PWM2) || ((MODE) == TIM_ForcedAction_Active) || ((MODE) == TIM_ForcedAction_InActive)) ¼TIM_OPMode_Single ((uint16_t)0x0008) ½TIM_OPMode_Repetitive ((uint16_t)0x0000) ¾IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || ((MODE) == TIM_OPMode_Repetitive)) ÈTIM_Channel_1 ((uint16_t)0x0000) ÉTIM_Channel_2 ((uint16_t)0x0004) ÊTIM_Channel_3 ((uint16_t)0x0008) ËTIM_Channel_4 ((uint16_t)0x000C) ÌIS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || ((CHANNEL) == TIM_Channel_2) || ((CHANNEL) == TIM_Channel_3) || ((CHANNEL) == TIM_Channel_4)) ÐIS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || ((CHANNEL) == TIM_Channel_2)) ÒIS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || ((CHANNEL) == TIM_Channel_2) || ((CHANNEL) == TIM_Channel_3)) ÝTIM_CKD_DIV1 ((uint16_t)0x0000) ÞTIM_CKD_DIV2 ((uint16_t)0x0100) ßTIM_CKD_DIV4 ((uint16_t)0x0200) àIS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || ((DIV) == TIM_CKD_DIV2) || ((DIV) == TIM_CKD_DIV4)) ëTIM_CounterMode_Up ((uint16_t)0x0000) ìTIM_CounterMode_Down ((uint16_t)0x0010) íTIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) îTIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) ïTIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) ðIS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || ((MODE) == TIM_CounterMode_Down) || ((MODE) == TIM_CounterMode_CenterAligned1) || ((MODE) == TIM_CounterMode_CenterAligned2) || ((MODE) == TIM_CounterMode_CenterAligned3)) ýTIM_OCPolarity_High ((uint16_t)0x0000) þTIM_OCPolarity_Low ((uint16_t)0x0002) ÿIS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || ((POLARITY) == TIM_OCPolarity_Low)) TIM_OCNPolarity_High ((uint16_t)0x0000) TIM_OCNPolarity_Low ((uint16_t)0x0008) IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || ((POLARITY) == TIM_OCNPolarity_Low)) TIM_OutputState_Disable ((uint16_t)0x0000) TIM_OutputState_Enable ((uint16_t)0x0001) IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || ((STATE) == TIM_OutputState_Enable)) ¡TIM_OutputNState_Disable ((uint16_t)0x0000) ¢TIM_OutputNState_Enable ((uint16_t)0x0004) £IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || ((STATE) == TIM_OutputNState_Enable)) TIM_CCx_Enable ((uint16_t)0x0001) ®TIM_CCx_Disable ((uint16_t)0x0000) ¯IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || ((CCX) == TIM_CCx_Disable)) ¹TIM_CCxN_Enable ((uint16_t)0x0004) ºTIM_CCxN_Disable ((uint16_t)0x0000) »IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || ((CCXN) == TIM_CCxN_Disable)) ÅTIM_Break_Enable ((uint16_t)0x1000) ÆTIM_Break_Disable ((uint16_t)0x0000) ÇIS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || ((STATE) == TIM_Break_Disable)) ÑTIM_BreakPolarity_Low ((uint16_t)0x0000) ÒTIM_BreakPolarity_High ((uint16_t)0x2000) ÓIS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || ((POLARITY) == TIM_BreakPolarity_High)) ÝTIM_AutomaticOutput_Enable ((uint16_t)0x4000) ÞTIM_AutomaticOutput_Disable ((uint16_t)0x0000) ßIS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || ((STATE) == TIM_AutomaticOutput_Disable)) éTIM_LOCKLevel_OFF ((uint16_t)0x0000) êTIM_LOCKLevel_1 ((uint16_t)0x0100) ëTIM_LOCKLevel_2 ((uint16_t)0x0200) ìTIM_LOCKLevel_3 ((uint16_t)0x0300) íIS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || ((LEVEL) == TIM_LOCKLevel_1) || ((LEVEL) == TIM_LOCKLevel_2) || ((LEVEL) == TIM_LOCKLevel_3)) ùTIM_OSSIState_Enable ((uint16_t)0x0400) úTIM_OSSIState_Disable ((uint16_t)0x0000) ûIS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || ((STATE) == TIM_OSSIState_Disable))
TIM_OSSRState_Enable ((uint16_t)0x0800) TIM_OSSRState_Disable ((uint16_t)0x0000) IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || ((STATE) == TIM_OSSRState_Disable)) TIM_OCIdleState_Set ((uint16_t)0x0100) TIM_OCIdleState_Reset ((uint16_t)0x0000) IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || ((STATE) == TIM_OCIdleState_Reset)) TIM_OCNIdleState_Set ((uint16_t)0x0200) TIM_OCNIdleState_Reset ((uint16_t)0x0000) IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || ((STATE) == TIM_OCNIdleState_Reset)) ©TIM_ICPolarity_Rising ((uint16_t)0x0000) ªTIM_ICPolarity_Falling ((uint16_t)0x0002) «TIM_ICPolarity_BothEdge ((uint16_t)0x000A) ¬IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || ((POLARITY) == TIM_ICPolarity_Falling)) ®IS_TIM_IC_POLARITY_LITE(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || ((POLARITY) == TIM_ICPolarity_Falling)|| ((POLARITY) == TIM_ICPolarity_BothEdge)) ¹TIM_ICSelection_DirectTI ((uint16_t)0x0001) »TIM_ICSelection_IndirectTI ((uint16_t)0x0002) ½TIM_ICSelection_TRC ((uint16_t)0x0003) ¾IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || ((SELECTION) == TIM_ICSelection_IndirectTI) || ((SELECTION) == TIM_ICSelection_TRC)) ÉTIM_ICPSC_DIV1 ((uint16_t)0x0000) ÊTIM_ICPSC_DIV2 ((uint16_t)0x0004) ËTIM_ICPSC_DIV4 ((uint16_t)0x0008) ÌTIM_ICPSC_DIV8 ((uint16_t)0x000C) ÍIS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || ((PRESCALER) == TIM_ICPSC_DIV2) || ((PRESCALER) == TIM_ICPSC_DIV4) || ((PRESCALER) == TIM_ICPSC_DIV8)) ÙTIM_IT_Update ((uint16_t)0x0001) ÚTIM_IT_CC1 ((uint16_t)0x0002) ÛTIM_IT_CC2 ((uint16_t)0x0004) ÜTIM_IT_CC3 ((uint16_t)0x0008) ÝTIM_IT_CC4 ((uint16_t)0x0010) ÞTIM_IT_COM ((uint16_t)0x0020) ßTIM_IT_Trigger ((uint16_t)0x0040) àTIM_IT_Break ((uint16_t)0x0080) áIS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000)) ãIS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || ((IT) == TIM_IT_CC1) || ((IT) == TIM_IT_CC2) || ((IT) == TIM_IT_CC3) || ((IT) == TIM_IT_CC4) || ((IT) == TIM_IT_COM) || ((IT) == TIM_IT_Trigger) || ((IT) == TIM_IT_Break)) óTIM_DMABase_CR1 ((uint16_t)0x0000) ôTIM_DMABase_CR2 ((uint16_t)0x0001) õTIM_DMABase_SMCR ((uint16_t)0x0002) öTIM_DMABase_DIER ((uint16_t)0x0003) ÷TIM_DMABase_SR ((uint16_t)0x0004) øTIM_DMABase_EGR ((uint16_t)0x0005) ùTIM_DMABase_CCMR1 ((uint16_t)0x0006) úTIM_DMABase_CCMR2 ((uint16_t)0x0007) ûTIM_DMABase_CCER ((uint16_t)0x0008) üTIM_DMABase_CNT ((uint16_t)0x0009) ýTIM_DMABase_PSC ((uint16_t)0x000A) þTIM_DMABase_ARR ((uint16_t)0x000B) ÿTIM_DMABase_RCR ((uint16_t)0x000C) TIM_DMABase_CCR1 ((uint16_t)0x000D) TIM_DMABase_CCR2 ((uint16_t)0x000E) TIM_DMABase_CCR3 ((uint16_t)0x000F) TIM_DMABase_CCR4 ((uint16_t)0x0010) TIM_DMABase_BDTR ((uint16_t)0x0011)
TIM_DMABase_DCR ((uint16_t)0x0012) IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || ((BASE) == TIM_DMABase_CR2) || ((BASE) == TIM_DMABase_SMCR) || ((BASE) == TIM_DMABase_DIER) || ((BASE) == TIM_DMABase_SR) || ((BASE) == TIM_DMABase_EGR) || ((BASE) == TIM_DMABase_CCMR1) || ((BASE) == TIM_DMABase_CCMR2) || ((BASE) == TIM_DMABase_CCER) || ((BASE) == TIM_DMABase_CNT) || ((BASE) == TIM_DMABase_PSC) || ((BASE) == TIM_DMABase_ARR) || ((BASE) == TIM_DMABase_RCR) || ((BASE) == TIM_DMABase_CCR1) || ((BASE) == TIM_DMABase_CCR2) || ((BASE) == TIM_DMABase_CCR3) || ((BASE) == TIM_DMABase_CCR4) || ((BASE) == TIM_DMABase_BDTR) || ((BASE) == TIM_DMABase_DCR)) ¡TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) ¢TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) £TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) ¤TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) ¥TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) ¦TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) §TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) ¨TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) ©TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) ªTIM_DMABurstLength_10Transfers ((uint16_t)0x0900) «TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) ¬TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) ®TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) ¯TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) °TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) ±TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) ²TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) ³IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || ((LENGTH) == TIM_DMABurstLength_2Transfers) || ((LENGTH) == TIM_DMABurstLength_3Transfers) || ((LENGTH) == TIM_DMABurstLength_4Transfers) || ((LENGTH) == TIM_DMABurstLength_5Transfers) || ((LENGTH) == TIM_DMABurstLength_6Transfers) || ((LENGTH) == TIM_DMABurstLength_7Transfers) || ((LENGTH) == TIM_DMABurstLength_8Transfers) || ((LENGTH) == TIM_DMABurstLength_9Transfers) || ((LENGTH) == TIM_DMABurstLength_10Transfers) || ((LENGTH) == TIM_DMABurstLength_11Transfers) || ((LENGTH) == TIM_DMABurstLength_12Transfers) || ((LENGTH) == TIM_DMABurstLength_13Transfers) || ((LENGTH) == TIM_DMABurstLength_14Transfers) || ((LENGTH) == TIM_DMABurstLength_15Transfers) || ((LENGTH) == TIM_DMABurstLength_16Transfers) || ((LENGTH) == TIM_DMABurstLength_17Transfers) || ((LENGTH) == TIM_DMABurstLength_18Transfers)) ÍTIM_DMA_Update ((uint16_t)0x0100) ÎTIM_DMA_CC1 ((uint16_t)0x0200) ÏTIM_DMA_CC2 ((uint16_t)0x0400) ÐTIM_DMA_CC3 ((uint16_t)0x0800) ÑTIM_DMA_CC4 ((uint16_t)0x1000) ÒTIM_DMA_COM ((uint16_t)0x2000) ÓTIM_DMA_Trigger ((uint16_t)0x4000) ÔIS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000)) ÞTIM_ExtTRGPSC_OFF ((uint16_t)0x0000) ßTIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) àTIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) áTIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) âIS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || ((PRESCALER) == TIM_ExtTRGPSC_DIV8)) îTIM_TS_ITR0 ((uint16_t)0x0000) ïTIM_TS_ITR1 ((uint16_t)0x0010) ðTIM_TS_ITR2 ((uint16_t)0x0020) ñTIM_TS_ITR3 ((uint16_t)0x0030) òTIM_TS_TI1F_ED ((uint16_t)0x0040) óTIM_TS_TI1FP1 ((uint16_t)0x0050) ôTIM_TS_TI2FP2 ((uint16_t)0x0060) õTIM_TS_ETRF ((uint16_t)0x0070) öIS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || ((SELECTION) == TIM_TS_ITR1) || ((SELECTION) == TIM_TS_ITR2) || ((SELECTION) == TIM_TS_ITR3) || ((SELECTION) == TIM_TS_TI1F_ED) || ((SELECTION) == TIM_TS_TI1FP1) || ((SELECTION) == TIM_TS_TI2FP2) || ((SELECTION) == TIM_TS_ETRF)) þIS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || ((SELECTION) == TIM_TS_ITR1) || ((SELECTION) == TIM_TS_ITR2) || ((SELECTION) == TIM_TS_ITR3)) TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) IS_TIM_TIXCLK_SOURCE(SOURCE) (((SOURCE) == TIM_TIxExternalCLK1Source_TI1) || ((SOURCE) == TIM_TIxExternalCLK1Source_TI2) || ((SOURCE) == TIM_TIxExternalCLK1Source_TI1ED)) TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || ((POLARITY) == TIM_ExtTRGPolarity_NonInverted)) £TIM_PSCReloadMode_Update ((uint16_t)0x0000) ¤TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) ¥IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || ((RELOAD) == TIM_PSCReloadMode_Immediate)) ¯TIM_ForcedAction_Active ((uint16_t)0x0050) °TIM_ForcedAction_InActive ((uint16_t)0x0040) ±IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || ((ACTION) == TIM_ForcedAction_InActive)) »TIM_EncoderMode_TI1 ((uint16_t)0x0001) ¼TIM_EncoderMode_TI2 ((uint16_t)0x0002) ½TIM_EncoderMode_TI12 ((uint16_t)0x0003) ¾IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || ((MODE) == TIM_EncoderMode_TI2) || ((MODE) == TIM_EncoderMode_TI12)) ÊTIM_EventSource_Update ((uint16_t)0x0001) ËTIM_EventSource_CC1 ((uint16_t)0x0002) ÌTIM_EventSource_CC2 ((uint16_t)0x0004) ÍTIM_EventSource_CC3 ((uint16_t)0x0008) ÎTIM_EventSource_CC4 ((uint16_t)0x0010) ÏTIM_EventSource_COM ((uint16_t)0x0020) ÐTIM_EventSource_Trigger ((uint16_t)0x0040) ÑTIM_EventSource_Break ((uint16_t)0x0080) ÒIS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000)) ÜTIM_UpdateSource_Global ((uint16_t)0x0000) ßTIM_UpdateSource_Regular ((uint16_t)0x0001) àIS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || ((SOURCE) == TIM_UpdateSource_Regular)) êTIM_OCPreload_Enable ((uint16_t)0x0008) ëTIM_OCPreload_Disable ((uint16_t)0x0000) ìIS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || ((STATE) == TIM_OCPreload_Disable)) öTIM_OCFast_Enable ((uint16_t)0x0004) ÷TIM_OCFast_Disable ((uint16_t)0x0000) øIS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || ((STATE) == TIM_OCFast_Disable)) TIM_OCClear_Enable ((uint16_t)0x0080) TIM_OCClear_Disable ((uint16_t)0x0000)
IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || ((STATE) == TIM_OCClear_Disable)) TIM_TRGOSource_Reset ((uint16_t)0x0000) TIM_TRGOSource_Enable ((uint16_t)0x0010) TIM_TRGOSource_Update ((uint16_t)0x0020) TIM_TRGOSource_OC1 ((uint16_t)0x0030) TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || ((SOURCE) == TIM_TRGOSource_Enable) || ((SOURCE) == TIM_TRGOSource_Update) || ((SOURCE) == TIM_TRGOSource_OC1) || ((SOURCE) == TIM_TRGOSource_OC1Ref) || ((SOURCE) == TIM_TRGOSource_OC2Ref) || ((SOURCE) == TIM_TRGOSource_OC3Ref) || ((SOURCE) == TIM_TRGOSource_OC4Ref)) §TIM_SlaveMode_Reset ((uint16_t)0x0004) ¨TIM_SlaveMode_Gated ((uint16_t)0x0005) ©TIM_SlaveMode_Trigger ((uint16_t)0x0006) ªTIM_SlaveMode_External1 ((uint16_t)0x0007) «IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || ((MODE) == TIM_SlaveMode_Gated) || ((MODE) == TIM_SlaveMode_Trigger) || ((MODE) == TIM_SlaveMode_External1)) ·TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) ¸TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) ¹IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || ((STATE) == TIM_MasterSlaveMode_Disable)) ÃTIM_FLAG_Update ((uint16_t)0x0001) ÄTIM_FLAG_CC1 ((uint16_t)0x0002) ÅTIM_FLAG_CC2 ((uint16_t)0x0004) ÆTIM_FLAG_CC3 ((uint16_t)0x0008) ÇTIM_FLAG_CC4 ((uint16_t)0x0010) ÈTIM_FLAG_COM ((uint16_t)0x0020) ÉTIM_FLAG_Trigger ((uint16_t)0x0040) ÊTIM_FLAG_Break ((uint16_t)0x0080) ËTIM_FLAG_CC1OF ((uint16_t)0x0200) ÌTIM_FLAG_CC2OF ((uint16_t)0x0400) ÍTIM_FLAG_CC3OF ((uint16_t)0x0800) ÎTIM_FLAG_CC4OF ((uint16_t)0x1000) ÏIS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || ((FLAG) == TIM_FLAG_CC1) || ((FLAG) == TIM_FLAG_CC2) || ((FLAG) == TIM_FLAG_CC3) || ((FLAG) == TIM_FLAG_CC4) || ((FLAG) == TIM_FLAG_COM) || ((FLAG) == TIM_FLAG_Trigger) || ((FLAG) == TIM_FLAG_Break) || ((FLAG) == TIM_FLAG_CC1OF) || ((FLAG) == TIM_FLAG_CC2OF) || ((FLAG) == TIM_FLAG_CC3OF) || ((FLAG) == TIM_FLAG_CC4OF)) ÝIS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000)) æIS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) ïIS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF) øTIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer ùTIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers úTIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers ûTIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers üTIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers ýTIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers þTIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers ÿTIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers
TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers __STM32F10x_SPI_H uIS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || ((PERIPH) == SPI2) || ((PERIPH) == SPI3)) yIS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || ((PERIPH) == SPI3)) SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) SPI_Direction_1Line_Rx ((uint16_t)0x8000) SPI_Direction_1Line_Tx ((uint16_t)0xC000) IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || ((MODE) == SPI_Direction_2Lines_RxOnly) || ((MODE) == SPI_Direction_1Line_Rx) || ((MODE) == SPI_Direction_1Line_Tx)) SPI_Mode_Master ((uint16_t)0x0104) SPI_Mode_Slave ((uint16_t)0x0000) IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || ((MODE) == SPI_Mode_Slave)) SPI_DataSize_16b ((uint16_t)0x0800) SPI_DataSize_8b ((uint16_t)0x0000) IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || ((DATASIZE) == SPI_DataSize_8b)) ¨SPI_CPOL_Low ((uint16_t)0x0000) ©SPI_CPOL_High ((uint16_t)0x0002) ªIS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || ((CPOL) == SPI_CPOL_High)) ´SPI_CPHA_1Edge ((uint16_t)0x0000) µSPI_CPHA_2Edge ((uint16_t)0x0001) ¶IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || ((CPHA) == SPI_CPHA_2Edge)) ÀSPI_NSS_Soft ((uint16_t)0x0200) ÁSPI_NSS_Hard ((uint16_t)0x0000) ÂIS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || ((NSS) == SPI_NSS_Hard)) ÌSPI_BaudRatePrescaler_2 ((uint16_t)0x0000) ÍSPI_BaudRatePrescaler_4 ((uint16_t)0x0008) ÎSPI_BaudRatePrescaler_8 ((uint16_t)0x0010) ÏSPI_BaudRatePrescaler_16 ((uint16_t)0x0018) ÐSPI_BaudRatePrescaler_32 ((uint16_t)0x0020) ÑSPI_BaudRatePrescaler_64 ((uint16_t)0x0028) ÒSPI_BaudRatePrescaler_128 ((uint16_t)0x0030) ÓSPI_BaudRatePrescaler_256 ((uint16_t)0x0038) ÔIS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || ((PRESCALER) == SPI_BaudRatePrescaler_4) || ((PRESCALER) == SPI_BaudRatePrescaler_8) || ((PRESCALER) == SPI_BaudRatePrescaler_16) || ((PRESCALER) == SPI_BaudRatePrescaler_32) || ((PRESCALER) == SPI_BaudRatePrescaler_64) || ((PRESCALER) == SPI_BaudRatePrescaler_128) || ((PRESCALER) == SPI_BaudRatePrescaler_256)) äSPI_FirstBit_MSB ((uint16_t)0x0000) åSPI_FirstBit_LSB ((uint16_t)0x0080) æIS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || ((BIT) == SPI_FirstBit_LSB)) ðI2S_Mode_SlaveTx ((uint16_t)0x0000) ñI2S_Mode_SlaveRx ((uint16_t)0x0100) òI2S_Mode_MasterTx ((uint16_t)0x0200) óI2S_Mode_MasterRx ((uint16_t)0x0300) ôIS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || ((MODE) == I2S_Mode_SlaveRx) || ((MODE) == I2S_Mode_MasterTx) || ((MODE) == I2S_Mode_MasterRx) ) I2S_Standard_Phillips ((uint16_t)0x0000) I2S_Standard_MSB ((uint16_t)0x0010) I2S_Standard_LSB ((uint16_t)0x0020) I2S_Standard_PCMShort ((uint16_t)0x0030) I2S_Standard_PCMLong ((uint16_t)0x00B0)
IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || ((STANDARD) == I2S_Standard_MSB) || ((STANDARD) == I2S_Standard_LSB) || ((STANDARD) == I2S_Standard_PCMShort) || ((STANDARD) == I2S_Standard_PCMLong)) I2S_DataFormat_16b ((uint16_t)0x0000) I2S_DataFormat_16bextended ((uint16_t)0x0001) I2S_DataFormat_24b ((uint16_t)0x0003) I2S_DataFormat_32b ((uint16_t)0x0005) IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || ((FORMAT) == I2S_DataFormat_16bextended) || ((FORMAT) == I2S_DataFormat_24b) || ((FORMAT) == I2S_DataFormat_32b)) ¢I2S_MCLKOutput_Enable ((uint16_t)0x0200) £I2S_MCLKOutput_Disable ((uint16_t)0x0000) ¤IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || ((OUTPUT) == I2S_MCLKOutput_Disable)) ®I2S_AudioFreq_192k ((uint32_t)192000) ¯I2S_AudioFreq_96k ((uint32_t)96000) °I2S_AudioFreq_48k ((uint32_t)48000) ±I2S_AudioFreq_44k ((uint32_t)44100) ²I2S_AudioFreq_32k ((uint32_t)32000) ³I2S_AudioFreq_22k ((uint32_t)22050) ´I2S_AudioFreq_16k ((uint32_t)16000) µI2S_AudioFreq_11k ((uint32_t)11025) ¶I2S_AudioFreq_8k ((uint32_t)8000) ·I2S_AudioFreq_Default ((uint32_t)2) ¹IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && ((FREQ) <= I2S_AudioFreq_192k)) || ((FREQ) == I2S_AudioFreq_Default)) ÄI2S_CPOL_Low ((uint16_t)0x0000) ÅI2S_CPOL_High ((uint16_t)0x0008) ÆIS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || ((CPOL) == I2S_CPOL_High)) ÐSPI_I2S_DMAReq_Tx ((uint16_t)0x0002) ÑSPI_I2S_DMAReq_Rx ((uint16_t)0x0001) ÒIS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00)) ÛSPI_NSSInternalSoft_Set ((uint16_t)0x0100) ÜSPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) ÝIS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || ((INTERNAL) == SPI_NSSInternalSoft_Reset)) çSPI_CRC_Tx ((uint8_t)0x00) èSPI_CRC_Rx ((uint8_t)0x01) éIS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx)) òSPI_Direction_Rx ((uint16_t)0xBFFF) óSPI_Direction_Tx ((uint16_t)0x4000) ôIS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || ((DIRECTION) == SPI_Direction_Tx)) þSPI_I2S_IT_TXE ((uint8_t)0x71) ÿSPI_I2S_IT_RXNE ((uint8_t)0x60) SPI_I2S_IT_ERR ((uint8_t)0x50) IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || ((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_ERR)) SPI_I2S_IT_OVR ((uint8_t)0x56)
SPI_IT_MODF ((uint8_t)0x55) SPI_IT_CRCERR ((uint8_t)0x54) I2S_IT_UDR ((uint8_t)0x53) IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR)) IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || ((IT) == I2S_IT_UDR) || ((IT) == SPI_IT_CRCERR) || ((IT) == SPI_IT_MODF) || ((IT) == SPI_I2S_IT_OVR)) SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) SPI_I2S_FLAG_TXE ((uint16_t)0x0002) I2S_FLAG_CHSIDE ((uint16_t)0x0004) I2S_FLAG_UDR ((uint16_t)0x0008) SPI_FLAG_CRCERR ((uint16_t)0x0010) SPI_FLAG_MODF ((uint16_t)0x0020) SPI_I2S_FLAG_OVR ((uint16_t)0x0040) SPI_I2S_FLAG_BSY ((uint16_t)0x0080) IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR)) IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)) ©IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1) __STM32F10x_RCC_H CRCC_HSE_OFF ((uint32_t)0x00000000) DRCC_HSE_ON ((uint32_t)0x00010000) ERCC_HSE_Bypass ((uint32_t)0x00040000) FIS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || ((HSE) == RCC_HSE_Bypass)) QRCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000) TRCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000) URCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000) VIS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || ((SOURCE) == RCC_PLLSource_HSE_Div1) || ((SOURCE) == RCC_PLLSource_HSE_Div2)) gRCC_PLLMul_2 ((uint32_t)0x00000000) hRCC_PLLMul_3 ((uint32_t)0x00040000) iRCC_PLLMul_4 ((uint32_t)0x00080000) jRCC_PLLMul_5 ((uint32_t)0x000C0000) kRCC_PLLMul_6 ((uint32_t)0x00100000) lRCC_PLLMul_7 ((uint32_t)0x00140000) mRCC_PLLMul_8 ((uint32_t)0x00180000) nRCC_PLLMul_9 ((uint32_t)0x001C0000) oRCC_PLLMul_10 ((uint32_t)0x00200000) pRCC_PLLMul_11 ((uint32_t)0x00240000) qRCC_PLLMul_12 ((uint32_t)0x00280000) rRCC_PLLMul_13 ((uint32_t)0x002C0000) sRCC_PLLMul_14 ((uint32_t)0x00300000) tRCC_PLLMul_15 ((uint32_t)0x00340000) uRCC_PLLMul_16 ((uint32_t)0x00380000) vIS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || ((MUL) == RCC_PLLMul_16)) ¡RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) ¢RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) £RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) ¤IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || ((SOURCE) == RCC_SYSCLKSource_HSE) || ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) ¯RCC_SYSCLK_Div1 ((uint32_t)0x00000000) °RCC_SYSCLK_Div2 ((uint32_t)0x00000080) ±RCC_SYSCLK_Div4 ((uint32_t)0x00000090) ²RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) ³RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) ´RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) µRCC_SYSCLK_Div128 ((uint32_t)0x000000D0) ¶RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) ·RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) ¸IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || ((HCLK) == RCC_SYSCLK_Div512)) ÅRCC_HCLK_Div1 ((uint32_t)0x00000000) ÆRCC_HCLK_Div2 ((uint32_t)0x00000400) ÇRCC_HCLK_Div4 ((uint32_t)0x00000500) ÈRCC_HCLK_Div8 ((uint32_t)0x00000600) ÉRCC_HCLK_Div16 ((uint32_t)0x00000700) ÊIS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || ((PCLK) == RCC_HCLK_Div16)) ÕRCC_IT_LSIRDY ((uint8_t)0x01) ÖRCC_IT_LSERDY ((uint8_t)0x02) ×RCC_IT_HSIRDY ((uint8_t)0x04) ØRCC_IT_HSERDY ((uint8_t)0x08) ÙRCC_IT_PLLRDY ((uint8_t)0x10) ÚRCC_IT_CSS ((uint8_t)0x80) ÝIS_RCC_IT(IT) ((((IT) & (uint8_t)0xE0) == 0x00) && ((IT) != 0x00)) ÞIS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS)) áIS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x60) == 0x00) && ((IT) != 0x00)) ÷RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00) øRCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01) úIS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1)) RCC_PCLK2_Div2 ((uint32_t)0x00000000) ®RCC_PCLK2_Div4 ((uint32_t)0x00004000) ¯RCC_PCLK2_Div6 ((uint32_t)0x00008000) °RCC_PCLK2_Div8 ((uint32_t)0x0000C000) ±IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || ((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8)) »RCC_LSE_OFF ((uint8_t)0x00) ¼RCC_LSE_ON ((uint8_t)0x01) ½RCC_LSE_Bypass ((uint8_t)0x04) ¾IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || ((LSE) == RCC_LSE_Bypass)) ÈRCC_RTCCLKSource_LSE ((uint32_t)0x00000100) ÉRCC_RTCCLKSource_LSI ((uint32_t)0x00000200) ÊRCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300) ËIS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || ((SOURCE) == RCC_RTCCLKSource_LSI) || ((SOURCE) == RCC_RTCCLKSource_HSE_Div128)) ÖRCC_AHBPeriph_DMA1 ((uint32_t)0x00000001) ×RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002) ØRCC_AHBPeriph_SRAM ((uint32_t)0x00000004) ÙRCC_AHBPeriph_FLITF ((uint32_t)0x00000010) ÚRCC_AHBPeriph_CRC ((uint32_t)0x00000040) ÝRCC_AHBPeriph_FSMC ((uint32_t)0x00000100) ÞRCC_AHBPeriph_SDIO ((uint32_t)0x00000400) ßIS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00)) ñRCC_APB2Periph_AFIO ((uint32_t)0x00000001) òRCC_APB2Periph_GPIOA ((uint32_t)0x00000004) óRCC_APB2Periph_GPIOB ((uint32_t)0x00000008) ôRCC_APB2Periph_GPIOC ((uint32_t)0x00000010) õRCC_APB2Periph_GPIOD ((uint32_t)0x00000020) öRCC_APB2Periph_GPIOE ((uint32_t)0x00000040) ÷RCC_APB2Periph_GPIOF ((uint32_t)0x00000080) øRCC_APB2Periph_GPIOG ((uint32_t)0x00000100) ùRCC_APB2Periph_ADC1 ((uint32_t)0x00000200) úRCC_APB2Periph_ADC2 ((uint32_t)0x00000400) ûRCC_APB2Periph_TIM1 ((uint32_t)0x00000800) üRCC_APB2Periph_SPI1 ((uint32_t)0x00001000) ýRCC_APB2Periph_TIM8 ((uint32_t)0x00002000) þRCC_APB2Periph_USART1 ((uint32_t)0x00004000) ÿRCC_APB2Periph_ADC3 ((uint32_t)0x00008000) RCC_APB2Periph_TIM15 ((uint32_t)0x00010000) RCC_APB2Periph_TIM16 ((uint32_t)0x00020000) RCC_APB2Periph_TIM17 ((uint32_t)0x00040000) RCC_APB2Periph_TIM9 ((uint32_t)0x00080000) RCC_APB2Periph_TIM10 ((uint32_t)0x00100000)
RCC_APB2Periph_TIM11 ((uint32_t)0x00200000) IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFC00002) == 0x00) && ((PERIPH) != 0x00)) RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) RCC_APB1Periph_TIM4 ((uint32_t)0x00000004) RCC_APB1Periph_TIM5 ((uint32_t)0x00000008) RCC_APB1Periph_TIM6 ((uint32_t)0x00000010) RCC_APB1Periph_TIM7 ((uint32_t)0x00000020) RCC_APB1Periph_TIM12 ((uint32_t)0x00000040) RCC_APB1Periph_TIM13 ((uint32_t)0x00000080) RCC_APB1Periph_TIM14 ((uint32_t)0x00000100) RCC_APB1Periph_WWDG ((uint32_t)0x00000800) RCC_APB1Periph_SPI2 ((uint32_t)0x00004000) RCC_APB1Periph_SPI3 ((uint32_t)0x00008000) RCC_APB1Periph_USART2 ((uint32_t)0x00020000) RCC_APB1Periph_USART3 ((uint32_t)0x00040000) RCC_APB1Periph_UART4 ((uint32_t)0x00080000) RCC_APB1Periph_UART5 ((uint32_t)0x00100000) RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) ¡RCC_APB1Periph_I2C2 ((uint32_t)0x00400000) ¢RCC_APB1Periph_USB ((uint32_t)0x00800000) £RCC_APB1Periph_CAN1 ((uint32_t)0x02000000) ¤RCC_APB1Periph_CAN2 ((uint32_t)0x04000000) ¥RCC_APB1Periph_BKP ((uint32_t)0x08000000) ¦RCC_APB1Periph_PWR ((uint32_t)0x10000000) §RCC_APB1Periph_DAC ((uint32_t)0x20000000) ¨RCC_APB1Periph_CEC ((uint32_t)0x40000000) ªIS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x81013600) == 0x00) && ((PERIPH) != 0x00)) ´RCC_MCO_NoClock ((uint8_t)0x00) µRCC_MCO_SYSCLK ((uint8_t)0x04) ¶RCC_MCO_HSI ((uint8_t)0x05) ·RCC_MCO_HSE ((uint8_t)0x06) ¸RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07) »IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || ((MCO) == RCC_MCO_PLLCLK_Div2)) ÓRCC_FLAG_HSIRDY ((uint8_t)0x21) ÔRCC_FLAG_HSERDY ((uint8_t)0x31) ÕRCC_FLAG_PLLRDY ((uint8_t)0x39) ÖRCC_FLAG_LSERDY ((uint8_t)0x41) ×RCC_FLAG_LSIRDY ((uint8_t)0x61) ØRCC_FLAG_PINRST ((uint8_t)0x7A) ÙRCC_FLAG_PORRST ((uint8_t)0x7B) ÚRCC_FLAG_SFTRST ((uint8_t)0x7C) ÛRCC_FLAG_IWDGRST ((uint8_t)0x7D) ÜRCC_FLAG_WWDGRST ((uint8_t)0x7E) ÝRCC_FLAG_LPWRRST ((uint8_t)0x7F) àIS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)) òIS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) __STM32F10x_GPIO_H .IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || ((PERIPH) == GPIOB) || ((PERIPH) == GPIOC) || ((PERIPH) == GPIOD) || ((PERIPH) == GPIOE) || ((PERIPH) == GPIOF) || ((PERIPH) == GPIOG)) @IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_10MHz) || ((SPEED) == GPIO_Speed_2MHz) || ((SPEED) == GPIO_Speed_50MHz)) RIS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_AIN) || ((MODE) == GPIO_Mode_IN_FLOATING) || ((MODE) == GPIO_Mode_IPD) || ((MODE) == GPIO_Mode_IPU) || ((MODE) == GPIO_Mode_Out_OD) || ((MODE) == GPIO_Mode_Out_PP) || ((MODE) == GPIO_Mode_AF_OD) || ((MODE) == GPIO_Mode_AF_PP)) qIS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET)) GPIO_Pin_0 ((uint16_t)0x0001) GPIO_Pin_1 ((uint16_t)0x0002) GPIO_Pin_2 ((uint16_t)0x0004) GPIO_Pin_3 ((uint16_t)0x0008) GPIO_Pin_4 ((uint16_t)0x0010) GPIO_Pin_5 ((uint16_t)0x0020)
GPIO_Pin_6 ((uint16_t)0x0040) GPIO_Pin_7 ((uint16_t)0x0080) GPIO_Pin_8 ((uint16_t)0x0100) GPIO_Pin_9 ((uint16_t)0x0200) GPIO_Pin_10 ((uint16_t)0x0400) GPIO_Pin_11 ((uint16_t)0x0800) GPIO_Pin_12 ((uint16_t)0x1000) GPIO_Pin_13 ((uint16_t)0x2000) GPIO_Pin_14 ((uint16_t)0x4000) GPIO_Pin_15 ((uint16_t)0x8000) GPIO_Pin_All ((uint16_t)0xFFFF) IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00)) IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || ((PIN) == GPIO_Pin_1) || ((PIN) == GPIO_Pin_2) || ((PIN) == GPIO_Pin_3) || ((PIN) == GPIO_Pin_4) || ((PIN) == GPIO_Pin_5) || ((PIN) == GPIO_Pin_6) || ((PIN) == GPIO_Pin_7) || ((PIN) == GPIO_Pin_8) || ((PIN) == GPIO_Pin_9) || ((PIN) == GPIO_Pin_10) || ((PIN) == GPIO_Pin_11) || ((PIN) == GPIO_Pin_12) || ((PIN) == GPIO_Pin_13) || ((PIN) == GPIO_Pin_14) || ((PIN) == GPIO_Pin_15)) ¬GPIO_Remap_SPI1 ((uint32_t)0x00000001) GPIO_Remap_I2C1 ((uint32_t)0x00000002) ®GPIO_Remap_USART1 ((uint32_t)0x00000004) ¯GPIO_Remap_USART2 ((uint32_t)0x00000008) °GPIO_PartialRemap_USART3 ((uint32_t)0x00140010) ±GPIO_FullRemap_USART3 ((uint32_t)0x00140030) ²GPIO_PartialRemap_TIM1 ((uint32_t)0x00160040) ³GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) ´GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) µGPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) ¶GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) ·GPIO_PartialRemap_TIM3 ((uint32_t)0x001A0800) ¸GPIO_FullRemap_TIM3 ((uint32_t)0x001A0C00) ¹GPIO_Remap_TIM4 ((uint32_t)0x00001000) ºGPIO_Remap1_CAN1 ((uint32_t)0x001D4000) »GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) ¼GPIO_Remap_PD01 ((uint32_t)0x00008000) ½GPIO_Remap_TIM5CH4_LSI ((uint32_t)0x00200001) ¾GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) ¿GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) ÀGPIO_Remap_ADC2_ETRGINJ ((uint32_t)0x00200008) ÁGPIO_Remap_ADC2_ETRGREG ((uint32_t)0x00200010) ÂGPIO_Remap_ETH ((uint32_t)0x00200020) ÃGPIO_Remap_CAN2 ((uint32_t)0x00200040) ÄGPIO_Remap_SWJ_NoJTRST ((uint32_t)0x00300100) ÅGPIO_Remap_SWJ_JTAGDisable ((uint32_t)0x00300200) ÆGPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) ÇGPIO_Remap_SPI3 ((uint32_t)0x00201100) ÈGPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000) ËGPIO_Remap_PTP_PPS ((uint32_t)0x00204000) ÍGPIO_Remap_TIM15 ((uint32_t)0x80000001) ÎGPIO_Remap_TIM16 ((uint32_t)0x80000002) ÏGPIO_Remap_TIM17 ((uint32_t)0x80000004) ÐGPIO_Remap_CEC ((uint32_t)0x80000008) ÑGPIO_Remap_TIM1_DMA ((uint32_t)0x80000010) ÓGPIO_Remap_TIM9 ((uint32_t)0x80000020) ÔGPIO_Remap_TIM10 ((uint32_t)0x80000040) ÕGPIO_Remap_TIM11 ((uint32_t)0x80000080) ÖGPIO_Remap_TIM13 ((uint32_t)0x80000100) ×GPIO_Remap_TIM14 ((uint32_t)0x80000200) ØGPIO_Remap_FSMC_NADV ((uint32_t)0x80000400) ÚGPIO_Remap_TIM67_DAC_DMA ((uint32_t)0x80000800) ÛGPIO_Remap_TIM12 ((uint32_t)0x80001000) ÜGPIO_Remap_MISC ((uint32_t)0x80002000) ßIS_GPIO_REMAP(REMAP) (((REMAP) == GPIO_Remap_SPI1) || ((REMAP) == GPIO_Remap_I2C1) || ((REMAP) == GPIO_Remap_USART1) || ((REMAP) == GPIO_Remap_USART2) || ((REMAP) == GPIO_PartialRemap_USART3) || ((REMAP) == GPIO_FullRemap_USART3) || ((REMAP) == GPIO_PartialRemap_TIM1) || ((REMAP) == GPIO_FullRemap_TIM1) || ((REMAP) == GPIO_PartialRemap1_TIM2) || ((REMAP) == GPIO_PartialRemap2_TIM2) || ((REMAP) == GPIO_FullRemap_TIM2) || ((REMAP) == GPIO_PartialRemap_TIM3) || ((REMAP) == GPIO_FullRemap_TIM3) || ((REMAP) == GPIO_Remap_TIM4) || ((REMAP) == GPIO_Remap1_CAN1) || ((REMAP) == GPIO_Remap2_CAN1) || ((REMAP) == GPIO_Remap_PD01) || ((REMAP) == GPIO_Remap_TIM5CH4_LSI) || ((REMAP) == GPIO_Remap_ADC1_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC1_ETRGREG) || ((REMAP) == GPIO_Remap_ADC2_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC2_ETRGREG) || ((REMAP) == GPIO_Remap_ETH) ||((REMAP) == GPIO_Remap_CAN2) || ((REMAP) == GPIO_Remap_SWJ_NoJTRST) || ((REMAP) == GPIO_Remap_SWJ_JTAGDisable) || ((REMAP) == GPIO_Remap_SWJ_Disable)|| ((REMAP) == GPIO_Remap_SPI3) || ((REMAP) == GPIO_Remap_TIM2ITR1_PTP_SOF) || ((REMAP) == GPIO_Remap_PTP_PPS) || ((REMAP) == GPIO_Remap_TIM15) || ((REMAP) == GPIO_Remap_TIM16) || ((REMAP) == GPIO_Remap_TIM17) || ((REMAP) == GPIO_Remap_CEC) || ((REMAP) == GPIO_Remap_TIM1_DMA) || ((REMAP) == GPIO_Remap_TIM9) || ((REMAP) == GPIO_Remap_TIM10) || ((REMAP) == GPIO_Remap_TIM11) || ((REMAP) == GPIO_Remap_TIM13) || ((REMAP) == GPIO_Remap_TIM14) || ((REMAP) == GPIO_Remap_FSMC_NADV) || ((REMAP) == GPIO_Remap_TIM67_DAC_DMA) || ((REMAP) == GPIO_Remap_TIM12) || ((REMAP) == GPIO_Remap_MISC)) þGPIO_PortSourceGPIOA ((uint8_t)0x00) ÿGPIO_PortSourceGPIOB ((uint8_t)0x01) GPIO_PortSourceGPIOC ((uint8_t)0x02) GPIO_PortSourceGPIOD ((uint8_t)0x03) GPIO_PortSourceGPIOE ((uint8_t)0x04) GPIO_PortSourceGPIOF ((uint8_t)0x05) GPIO_PortSourceGPIOG ((uint8_t)0x06)
IS_GPIO_EVENTOUT_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || ((PORTSOURCE) == GPIO_PortSourceGPIOB) || ((PORTSOURCE) == GPIO_PortSourceGPIOC) || ((PORTSOURCE) == GPIO_PortSourceGPIOD) || ((PORTSOURCE) == GPIO_PortSourceGPIOE)) IS_GPIO_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || ((PORTSOURCE) == GPIO_PortSourceGPIOB) || ((PORTSOURCE) == GPIO_PortSourceGPIOC) || ((PORTSOURCE) == GPIO_PortSourceGPIOD) || ((PORTSOURCE) == GPIO_PortSourceGPIOE) || ((PORTSOURCE) == GPIO_PortSourceGPIOF) || ((PORTSOURCE) == GPIO_PortSourceGPIOG)) GPIO_PinSource0 ((uint8_t)0x00) GPIO_PinSource1 ((uint8_t)0x01) GPIO_PinSource2 ((uint8_t)0x02) GPIO_PinSource3 ((uint8_t)0x03) GPIO_PinSource4 ((uint8_t)0x04) GPIO_PinSource5 ((uint8_t)0x05) ¡GPIO_PinSource6 ((uint8_t)0x06) ¢GPIO_PinSource7 ((uint8_t)0x07) £GPIO_PinSource8 ((uint8_t)0x08) ¤GPIO_PinSource9 ((uint8_t)0x09) ¥GPIO_PinSource10 ((uint8_t)0x0A) ¦GPIO_PinSource11 ((uint8_t)0x0B) §GPIO_PinSource12 ((uint8_t)0x0C) ¨GPIO_PinSource13 ((uint8_t)0x0D) ©GPIO_PinSource14 ((uint8_t)0x0E) ªGPIO_PinSource15 ((uint8_t)0x0F) ¬IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || ((PINSOURCE) == GPIO_PinSource1) || ((PINSOURCE) == GPIO_PinSource2) || ((PINSOURCE) == GPIO_PinSource3) || ((PINSOURCE) == GPIO_PinSource4) || ((PINSOURCE) == GPIO_PinSource5) || ((PINSOURCE) == GPIO_PinSource6) || ((PINSOURCE) == GPIO_PinSource7) || ((PINSOURCE) == GPIO_PinSource8) || ((PINSOURCE) == GPIO_PinSource9) || ((PINSOURCE) == GPIO_PinSource10) || ((PINSOURCE) == GPIO_PinSource11) || ((PINSOURCE) == GPIO_PinSource12) || ((PINSOURCE) == GPIO_PinSource13) || ((PINSOURCE) == GPIO_PinSource14) || ((PINSOURCE) == GPIO_PinSource15)) ÄGPIO_ETH_MediaInterface_MII ((u32)0x00000000) ÅGPIO_ETH_MediaInterface_RMII ((u32)0x00000001) ÇIS_GPIO_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == GPIO_ETH_MediaInterface_MII) || ((INTERFACE) == GPIO_ETH_MediaInterface_RMII)) __STM32F10x_ADC_H SIS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || ((PERIPH) == ADC2) || ((PERIPH) == ADC3)) WIS_ADC_DMA_PERIPH(PERIPH) (((PERIPH) == ADC1) || ((PERIPH) == ADC3)) ^ADC_Mode_Independent ((uint32_t)0x00000000) _ADC_Mode_RegInjecSimult ((uint32_t)0x00010000) `ADC_Mode_RegSimult_AlterTrig ((uint32_t)0x00020000) aADC_Mode_InjecSimult_FastInterl ((uint32_t)0x00030000) bADC_Mode_InjecSimult_SlowInterl ((uint32_t)0x00040000) cADC_Mode_InjecSimult ((uint32_t)0x00050000) dADC_Mode_RegSimult ((uint32_t)0x00060000) eADC_Mode_FastInterl ((uint32_t)0x00070000) fADC_Mode_SlowInterl ((uint32_t)0x00080000) gADC_Mode_AlterTrig ((uint32_t)0x00090000) iIS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || ((MODE) == ADC_Mode_RegInjecSimult) || ((MODE) == ADC_Mode_RegSimult_AlterTrig) || ((MODE) == ADC_Mode_InjecSimult_FastInterl) || ((MODE) == ADC_Mode_InjecSimult_SlowInterl) || ((MODE) == ADC_Mode_InjecSimult) || ((MODE) == ADC_Mode_RegSimult) || ((MODE) == ADC_Mode_FastInterl) || ((MODE) == ADC_Mode_SlowInterl) || ((MODE) == ADC_Mode_AlterTrig)) {ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) |ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00020000) }ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00060000) ~ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00080000) ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x000A0000) ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((uint32_t)0x000C0000) ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00040000) ADC_ExternalTrigConv_None ((uint32_t)0x000E0000)
ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x00000000) ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x00020000) ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x00060000) ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x00080000) ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x000A0000) ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x000C0000) IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO) || ((REGTRIG) == ADC_ExternalTrigConv_None) || ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3)) ¢ADC_DataAlign_Right ((uint32_t)0x00000000) £ADC_DataAlign_Left ((uint32_t)0x00000800) ¤IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || ((ALIGN) == ADC_DataAlign_Left)) ®ADC_Channel_0 ((uint8_t)0x00) ¯ADC_Channel_1 ((uint8_t)0x01) °ADC_Channel_2 ((uint8_t)0x02) ±ADC_Channel_3 ((uint8_t)0x03) ²ADC_Channel_4 ((uint8_t)0x04) ³ADC_Channel_5 ((uint8_t)0x05) ´ADC_Channel_6 ((uint8_t)0x06) µADC_Channel_7 ((uint8_t)0x07) ¶ADC_Channel_8 ((uint8_t)0x08) ·ADC_Channel_9 ((uint8_t)0x09) ¸ADC_Channel_10 ((uint8_t)0x0A) ¹ADC_Channel_11 ((uint8_t)0x0B) ºADC_Channel_12 ((uint8_t)0x0C) »ADC_Channel_13 ((uint8_t)0x0D) ¼ADC_Channel_14 ((uint8_t)0x0E) ½ADC_Channel_15 ((uint8_t)0x0F) ¾ADC_Channel_16 ((uint8_t)0x10) ¿ADC_Channel_17 ((uint8_t)0x11) ÁADC_Channel_TempSensor ((uint8_t)ADC_Channel_16) ÂADC_Channel_Vrefint ((uint8_t)ADC_Channel_17) ÄIS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || ((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || ((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || ((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || ((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_9) || ((CHANNEL) == ADC_Channel_10) || ((CHANNEL) == ADC_Channel_11) || ((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || ((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || ((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17)) ÕADC_SampleTime_1Cycles5 ((uint8_t)0x00) ÖADC_SampleTime_7Cycles5 ((uint8_t)0x01) ×ADC_SampleTime_13Cycles5 ((uint8_t)0x02) ØADC_SampleTime_28Cycles5 ((uint8_t)0x03) ÙADC_SampleTime_41Cycles5 ((uint8_t)0x04) ÚADC_SampleTime_55Cycles5 ((uint8_t)0x05) ÛADC_SampleTime_71Cycles5 ((uint8_t)0x06) ÜADC_SampleTime_239Cycles5 ((uint8_t)0x07) ÝIS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1Cycles5) || ((TIME) == ADC_SampleTime_7Cycles5) || ((TIME) == ADC_SampleTime_13Cycles5) || ((TIME) == ADC_SampleTime_28Cycles5) || ((TIME) == ADC_SampleTime_41Cycles5) || ((TIME) == ADC_SampleTime_55Cycles5) || ((TIME) == ADC_SampleTime_71Cycles5) || ((TIME) == ADC_SampleTime_239Cycles5)) íADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00002000) îADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00003000) ïADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00004000) ðADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00005000) ñADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000) óADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00000000) ôADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) õADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) ÷ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00002000) øADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x00003000) ùADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x00004000) úADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x00005000) ûADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x00006000) ýIS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4) || ((INJTRIG) == ADC_ExternalTrigInjecConv_None) || ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4)) ADC_InjectedChannel_1 ((uint8_t)0x14) ADC_InjectedChannel_2 ((uint8_t)0x18) ADC_InjectedChannel_3 ((uint8_t)0x1C) ADC_InjectedChannel_4 ((uint8_t)0x20) IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || ((CHANNEL) == ADC_InjectedChannel_2) || ((CHANNEL) == ADC_InjectedChannel_3) || ((CHANNEL) == ADC_InjectedChannel_4)) ¢ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) £ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) ¤ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) ¥ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) ¦ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) §ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) ¨ADC_AnalogWatchdog_None ((uint32_t)0x00000000) ªIS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || ((WATCHDOG) == ADC_AnalogWatchdog_None)) ¹ADC_IT_EOC ((uint16_t)0x0220) ºADC_IT_AWD ((uint16_t)0x0140) »ADC_IT_JEOC ((uint16_t)0x0480) ½IS_ADC_IT(IT) ((((IT) & (uint16_t)0xF81F) == 0x00) && ((IT) != 0x00)) ¿IS_ADC_GET_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || ((IT) == ADC_IT_JEOC)) ÉADC_FLAG_AWD ((uint8_t)0x01) ÊADC_FLAG_EOC ((uint8_t)0x02) ËADC_FLAG_JEOC ((uint8_t)0x04) ÌADC_FLAG_JSTRT ((uint8_t)0x08) ÍADC_FLAG_STRT ((uint8_t)0x10) ÎIS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xE0) == 0x00) && ((FLAG) != 0x00)) ÏIS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EOC) || ((FLAG) == ADC_FLAG_JEOC) || ((FLAG)== ADC_FLAG_JSTRT) || ((FLAG) == ADC_FLAG_STRT)) ÚIS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF) äIS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF) îIS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4)) øIS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4)) IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10)) IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10)) IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8)) 3__STM32F10x_H wHSE_VALUE ((uint32_t)8000000) HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) HSI_VALUE ((uint32_t)8000000) __STM32F10X_STDPERIPH_VERSION_MAIN (0x03) __STM32F10X_STDPERIPH_VERSION_SUB1 (0x05) __STM32F10X_STDPERIPH_VERSION_SUB2 (0x00) __STM32F10X_STDPERIPH_VERSION_RC (0x00) __STM32F10X_STDPERIPH_VERSION ( (__STM32F10X_STDPERIPH_VERSION_MAIN << 24) |(__STM32F10X_STDPERIPH_VERSION_SUB1 << 16) |(__STM32F10X_STDPERIPH_VERSION_SUB2 << 8) |(__STM32F10X_STDPERIPH_VERSION_RC)) __MPU_PRESENT 0 __NVIC_PRIO_BITS 4 ¡__Vendor_SysTickConfig 0 ÞßàIS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT HSE_Value HSE_VALUE HSI_Value HSI_VALUE ø FLASH_BASE ((uint32_t)0x08000000) ù SRAM_BASE ((uint32_t)0x20000000) ú PERIPH_BASE ((uint32_t)0x40000000) ü SRAM_BB_BASE ((uint32_t)0x22000000) ý PERIPH_BB_BASE ((uint32_t)0x42000000) ÿ FSMC_R_BASE ((uint32_t)0xA0000000)
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APB1PERIPH_BASE PERIPH_BASE
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APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
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AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
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TIM2_BASE (APB1PERIPH_BASE + 0x0000)
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TIM3_BASE (APB1PERIPH_BASE + 0x0400)
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TIM4_BASE (APB1PERIPH_BASE + 0x0800)
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TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
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TIM6_BASE (APB1PERIPH_BASE + 0x1000)
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TIM7_BASE (APB1PERIPH_BASE + 0x1400)
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TIM12_BASE (APB1PERIPH_BASE + 0x1800)
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TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
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TIM14_BASE (APB1PERIPH_BASE + 0x2000)
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RTC_BASE (APB1PERIPH_BASE + 0x2800)
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WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
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IWDG_BASE (APB1PERIPH_BASE + 0x3000)
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SPI2_BASE (APB1PERIPH_BASE + 0x3800)
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SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
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USART2_BASE (APB1PERIPH_BASE + 0x4400)
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USART3_BASE (APB1PERIPH_BASE + 0x4800)
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UART4_BASE (APB1PERIPH_BASE + 0x4C00)
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UART5_BASE (APB1PERIPH_BASE + 0x5000)
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I2C1_BASE (APB1PERIPH_BASE + 0x5400)
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I2C2_BASE (APB1PERIPH_BASE + 0x5800)
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CAN1_BASE (APB1PERIPH_BASE + 0x6400)
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CAN2_BASE (APB1PERIPH_BASE + 0x6800)
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BKP_BASE (APB1PERIPH_BASE + 0x6C00)
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PWR_BASE (APB1PERIPH_BASE + 0x7000)
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DAC_BASE (APB1PERIPH_BASE + 0x7400)
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CEC_BASE (APB1PERIPH_BASE + 0x7800) ¡
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AFIO_BASE (APB2PERIPH_BASE + 0x0000) ¢
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EXTI_BASE (APB2PERIPH_BASE + 0x0400) £
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GPIOA_BASE (APB2PERIPH_BASE + 0x0800) ¤
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GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) ¥
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GPIOC_BASE (APB2PERIPH_BASE + 0x1000) ¦
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GPIOD_BASE (APB2PERIPH_BASE + 0x1400) §
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GPIOE_BASE (APB2PERIPH_BASE + 0x1800) ¨
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GPIOF_BASE (APB2PERIPH_BASE + 0x1C00) ©
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GPIOG_BASE (APB2PERIPH_BASE + 0x2000) ª
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ADC1_BASE (APB2PERIPH_BASE + 0x2400) «
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ADC2_BASE (APB2PERIPH_BASE + 0x2800) ¬
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TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
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SPI1_BASE (APB2PERIPH_BASE + 0x3000) ®
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TIM8_BASE (APB2PERIPH_BASE + 0x3400) ¯
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USART1_BASE (APB2PERIPH_BASE + 0x3800) °
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ADC3_BASE (APB2PERIPH_BASE + 0x3C00) ±
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TIM15_BASE (APB2PERIPH_BASE + 0x4000) ²
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TIM16_BASE (APB2PERIPH_BASE + 0x4400) ³
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TIM17_BASE (APB2PERIPH_BASE + 0x4800) ´
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TIM9_BASE (APB2PERIPH_BASE + 0x4C00) µ
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TIM10_BASE (APB2PERIPH_BASE + 0x5000) ¶
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TIM11_BASE (APB2PERIPH_BASE + 0x5400) ¸
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SDIO_BASE (PERIPH_BASE + 0x18000) º
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DMA1_BASE (AHBPERIPH_BASE + 0x0000) »
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DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) ¼
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DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) ½
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DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) ¾
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DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) ¿
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DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) À
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DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) Á
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DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) Â
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DMA2_BASE (AHBPERIPH_BASE + 0x0400) Ã
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DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408) Ä
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DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C) Å
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DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430) Æ
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DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444) Ç
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DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458) È
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RCC_BASE (AHBPERIPH_BASE + 0x1000) É
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CRC_BASE (AHBPERIPH_BASE + 0x3000) Ë
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FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) Ì
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OB_BASE ((uint32_t)0x1FFFF800) Î
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ETH_BASE (AHBPERIPH_BASE + 0x8000) Ï
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ETH_MAC_BASE (ETH_BASE) Ð
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ETH_MMC_BASE (ETH_BASE + 0x0100) Ñ
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ETH_PTP_BASE (ETH_BASE + 0x0700) Ò
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ETH_DMA_BASE (ETH_BASE + 0x1000) Ô
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FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) Õ
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FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) Ö
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FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) ×
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FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) Ø
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FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) Ú
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DBGMCU_BASE ((uint32_t)0xE0042000) ä
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TIM2 ((TIM_TypeDef *) TIM2_BASE) å
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TIM3 ((TIM_TypeDef *) TIM3_BASE) æ
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TIM4 ((TIM_TypeDef *) TIM4_BASE) ç
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TIM5 ((TIM_TypeDef *) TIM5_BASE) è
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TIM6 ((TIM_TypeDef *) TIM6_BASE) é
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TIM7 ((TIM_TypeDef *) TIM7_BASE) ê
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TIM12 ((TIM_TypeDef *) TIM12_BASE) ë
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TIM13 ((TIM_TypeDef *) TIM13_BASE) ì
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TIM14 ((TIM_TypeDef *) TIM14_BASE) í
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RTC ((RTC_TypeDef *) RTC_BASE) î
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WWDG ((WWDG_TypeDef *) WWDG_BASE) ï
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IWDG ((IWDG_TypeDef *) IWDG_BASE) ð
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SPI2 ((SPI_TypeDef *) SPI2_BASE) ñ
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SPI3 ((SPI_TypeDef *) SPI3_BASE) ò
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USART2 ((USART_TypeDef *) USART2_BASE) ó
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USART3 ((USART_TypeDef *) USART3_BASE) ô
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UART4 ((USART_TypeDef *) UART4_BASE) õ
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UART5 ((USART_TypeDef *) UART5_BASE) ö
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I2C1 ((I2C_TypeDef *) I2C1_BASE) ÷
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I2C2 ((I2C_TypeDef *) I2C2_BASE) ø
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CAN1 ((CAN_TypeDef *) CAN1_BASE) ù
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CAN2 ((CAN_TypeDef *) CAN2_BASE) ú
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BKP ((BKP_TypeDef *) BKP_BASE) û
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PWR ((PWR_TypeDef *) PWR_BASE) ü
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DAC ((DAC_TypeDef *) DAC_BASE) ý
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CEC ((CEC_TypeDef *) CEC_BASE) þ
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AFIO ((AFIO_TypeDef *) AFIO_BASE) ÿ
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EXTI ((EXTI_TypeDef *) EXTI_BASE) GPIOA ((GPIO_TypeDef *) GPIOA_BASE) GPIOB ((GPIO_TypeDef *) GPIOB_BASE) GPIOC ((GPIO_TypeDef *) GPIOC_BASE) GPIOD ((GPIO_TypeDef *) GPIOD_BASE) GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
GPIOF ((GPIO_TypeDef *) GPIOF_BASE) GPIOG ((GPIO_TypeDef *) GPIOG_BASE) ADC1 ((ADC_TypeDef *) ADC1_BASE) ADC2 ((ADC_TypeDef *) ADC2_BASE) TIM1 ((TIM_TypeDef *) TIM1_BASE) SPI1 ((SPI_TypeDef *) SPI1_BASE) TIM8 ((TIM_TypeDef *) TIM8_BASE) USART1 ((USART_TypeDef *) USART1_BASE) ADC3 ((ADC_TypeDef *) ADC3_BASE) TIM15 ((TIM_TypeDef *) TIM15_BASE) TIM16 ((TIM_TypeDef *) TIM16_BASE) TIM17 ((TIM_TypeDef *) TIM17_BASE) TIM9 ((TIM_TypeDef *) TIM9_BASE) TIM10 ((TIM_TypeDef *) TIM10_BASE) TIM11 ((TIM_TypeDef *) TIM11_BASE) SDIO ((SDIO_TypeDef *) SDIO_BASE) DMA1 ((DMA_TypeDef *) DMA1_BASE) DMA2 ((DMA_TypeDef *) DMA2_BASE) DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) ¡ DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) ¢ DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) £ RCC ((RCC_TypeDef *) RCC_BASE) ¤ CRC ((CRC_TypeDef *) CRC_BASE) ¥ FLASH ((FLASH_TypeDef *) FLASH_R_BASE) ¦ OB ((OB_TypeDef *) OB_BASE) § ETH ((ETH_TypeDef *) ETH_BASE) ¨ FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) © FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) ª FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) « FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE) ¬ FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) Æ CRC_DR_DR ((uint32_t)0xFFFFFFFF) Ê CRC_IDR_IDR ((uint8_t)0xFF) Î CRC_CR_RESET ((uint8_t)0x01) × PWR_CR_LPDS ((uint16_t)0x0001) Ø PWR_CR_PDDS ((uint16_t)0x0002) Ù PWR_CR_CWUF ((uint16_t)0x0004) Ú PWR_CR_CSBF ((uint16_t)0x0008) Û PWR_CR_PVDE ((uint16_t)0x0010) Ý PWR_CR_PLS ((uint16_t)0x00E0) Þ PWR_CR_PLS_0 ((uint16_t)0x0020) ß PWR_CR_PLS_1 ((uint16_t)0x0040) à PWR_CR_PLS_2 ((uint16_t)0x0080) ã PWR_CR_PLS_2V2 ((uint16_t)0x0000) ä PWR_CR_PLS_2V3 ((uint16_t)0x0020) å PWR_CR_PLS_2V4 ((uint16_t)0x0040) æ PWR_CR_PLS_2V5 ((uint16_t)0x0060) ç PWR_CR_PLS_2V6 ((uint16_t)0x0080) è PWR_CR_PLS_2V7 ((uint16_t)0x00A0) é PWR_CR_PLS_2V8 ((uint16_t)0x00C0) ê PWR_CR_PLS_2V9 ((uint16_t)0x00E0) ì PWR_CR_DBP ((uint16_t)0x0100) ð PWR_CSR_WUF ((uint16_t)0x0001) ñ PWR_CSR_SBF ((uint16_t)0x0002) ò PWR_CSR_PVDO ((uint16_t)0x0004) ó PWR_CSR_EWUP ((uint16_t)0x0100) ü BKP_DR1_D ((uint16_t)0xFFFF) ÿ BKP_DR2_D ((uint16_t)0xFFFF) BKP_DR3_D ((uint16_t)0xFFFF)
BKP_DR4_D ((uint16_t)0xFFFF) BKP_DR5_D ((uint16_t)0xFFFF) BKP_DR6_D ((uint16_t)0xFFFF) BKP_DR7_D ((uint16_t)0xFFFF) BKP_DR8_D ((uint16_t)0xFFFF) BKP_DR9_D ((uint16_t)0xFFFF) BKP_DR10_D ((uint16_t)0xFFFF) BKP_DR11_D ((uint16_t)0xFFFF) BKP_DR12_D ((uint16_t)0xFFFF) BKP_DR13_D ((uint16_t)0xFFFF) £ BKP_DR14_D ((uint16_t)0xFFFF) ¦ BKP_DR15_D ((uint16_t)0xFFFF) © BKP_DR16_D ((uint16_t)0xFFFF) ¬ BKP_DR17_D ((uint16_t)0xFFFF) ¯ BKP_DR18_D ((uint16_t)0xFFFF) ² BKP_DR19_D ((uint16_t)0xFFFF) µ BKP_DR20_D ((uint16_t)0xFFFF) ¸ BKP_DR21_D ((uint16_t)0xFFFF) » BKP_DR22_D ((uint16_t)0xFFFF) ¾ BKP_DR23_D ((uint16_t)0xFFFF) Á BKP_DR24_D ((uint16_t)0xFFFF) Ä BKP_DR25_D ((uint16_t)0xFFFF) Ç BKP_DR26_D ((uint16_t)0xFFFF) Ê BKP_DR27_D ((uint16_t)0xFFFF) Í BKP_DR28_D ((uint16_t)0xFFFF) Ð BKP_DR29_D ((uint16_t)0xFFFF) Ó BKP_DR30_D ((uint16_t)0xFFFF) Ö BKP_DR31_D ((uint16_t)0xFFFF) Ù BKP_DR32_D ((uint16_t)0xFFFF) Ü BKP_DR33_D ((uint16_t)0xFFFF) ß BKP_DR34_D ((uint16_t)0xFFFF) â BKP_DR35_D ((uint16_t)0xFFFF) å BKP_DR36_D ((uint16_t)0xFFFF) è BKP_DR37_D ((uint16_t)0xFFFF) ë BKP_DR38_D ((uint16_t)0xFFFF) î BKP_DR39_D ((uint16_t)0xFFFF) ñ BKP_DR40_D ((uint16_t)0xFFFF) ô BKP_DR41_D ((uint16_t)0xFFFF) ÷ BKP_DR42_D ((uint16_t)0xFFFF) ú BKP_RTCCR_CAL ((uint16_t)0x007F) û BKP_RTCCR_CCO ((uint16_t)0x0080) ü BKP_RTCCR_ASOE ((uint16_t)0x0100) ý BKP_RTCCR_ASOS ((uint16_t)0x0200) BKP_CR_TPE ((uint8_t)0x01) BKP_CR_TPAL ((uint8_t)0x02) BKP_CSR_CTE ((uint16_t)0x0001)
BKP_CSR_CTI ((uint16_t)0x0002) BKP_CSR_TPIE ((uint16_t)0x0004) BKP_CSR_TEF ((uint16_t)0x0100) BKP_CSR_TIF ((uint16_t)0x0200) RCC_CR_HSION ((uint32_t)0x00000001) RCC_CR_HSIRDY ((uint32_t)0x00000002) RCC_CR_HSITRIM ((uint32_t)0x000000F8) RCC_CR_HSICAL ((uint32_t)0x0000FF00) RCC_CR_HSEON ((uint32_t)0x00010000) RCC_CR_HSERDY ((uint32_t)0x00020000) RCC_CR_HSEBYP ((uint32_t)0x00040000) RCC_CR_CSSON ((uint32_t)0x00080000) RCC_CR_PLLON ((uint32_t)0x01000000) RCC_CR_PLLRDY ((uint32_t)0x02000000) ¥ RCC_CFGR_SW ((uint32_t)0x00000003) ¦ RCC_CFGR_SW_0 ((uint32_t)0x00000001) § RCC_CFGR_SW_1 ((uint32_t)0x00000002) © RCC_CFGR_SW_HSI ((uint32_t)0x00000000) ª RCC_CFGR_SW_HSE ((uint32_t)0x00000001) « RCC_CFGR_SW_PLL ((uint32_t)0x00000002) ® RCC_CFGR_SWS ((uint32_t)0x0000000C) ¯ RCC_CFGR_SWS_0 ((uint32_t)0x00000004) ° RCC_CFGR_SWS_1 ((uint32_t)0x00000008) ² RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) ³ RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) ´ RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) · RCC_CFGR_HPRE ((uint32_t)0x000000F0) ¸ RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) ¹ RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) º RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) » RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) ½ RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) ¾ RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) ¿ RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) À RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) Á RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) Â RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) Ã RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) Ä RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) Å RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) È RCC_CFGR_PPRE1 ((uint32_t)0x00000700) É RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) Ê RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) Ë RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) Í RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) Î RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) Ï RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) Ð RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) Ñ RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) Ô RCC_CFGR_PPRE2 ((uint32_t)0x00003800) Õ RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) Ö RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) × RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) Ù RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) Ú RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) Û RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) Ü RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) Ý RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) à RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) á RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) â RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) ä RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) å RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) æ RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) ç RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) é RCC_CFGR_PLLSRC ((uint32_t)0x00010000) ë RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) î RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) ï RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) ð RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) ñ RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) ò RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) ¸RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) ¹RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) »RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) ¼RCC_CFGR_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) ¾RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) ¿RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) ÀRCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) ÁRCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) ÂRCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) ÃRCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) ÄRCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) ÅRCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) ÆRCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) ÇRCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) ÈRCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) ÉRCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) ÊRCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) ËRCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) ÌRCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) ÍRCC_CFGR_USBPRE ((uint32_t)0x00400000) ÐRCC_CFGR_MCO ((uint32_t)0x07000000) ÑRCC_CFGR_MCO_0 ((uint32_t)0x01000000) ÒRCC_CFGR_MCO_1 ((uint32_t)0x02000000) ÓRCC_CFGR_MCO_2 ((uint32_t)0x04000000) ÕRCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) ÖRCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) ×RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) ØRCC_CFGR_MCO_HSE ((uint32_t)0x06000000) ÙRCC_CFGR_MCO_PLL ((uint32_t)0x07000000) ÝRCC_CIR_LSIRDYF ((uint32_t)0x00000001) ÞRCC_CIR_LSERDYF ((uint32_t)0x00000002) ßRCC_CIR_HSIRDYF ((uint32_t)0x00000004) àRCC_CIR_HSERDYF ((uint32_t)0x00000008) áRCC_CIR_PLLRDYF ((uint32_t)0x00000010) âRCC_CIR_CSSF ((uint32_t)0x00000080) ãRCC_CIR_LSIRDYIE ((uint32_t)0x00000100) äRCC_CIR_LSERDYIE ((uint32_t)0x00000200) åRCC_CIR_HSIRDYIE ((uint32_t)0x00000400) æRCC_CIR_HSERDYIE ((uint32_t)0x00000800) çRCC_CIR_PLLRDYIE ((uint32_t)0x00001000) èRCC_CIR_LSIRDYC ((uint32_t)0x00010000) éRCC_CIR_LSERDYC ((uint32_t)0x00020000) êRCC_CIR_HSIRDYC ((uint32_t)0x00040000) ëRCC_CIR_HSERDYC ((uint32_t)0x00080000) ìRCC_CIR_PLLRDYC ((uint32_t)0x00100000) íRCC_CIR_CSSC ((uint32_t)0x00800000) ùRCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) úRCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) ûRCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) üRCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) ýRCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) þRCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) RCC_APB2RSTR_ADC2RST ((uint32_t)0x00000400) RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800)
RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040) RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) RCC_APB2RSTR_TIM8RST ((uint32_t)0x00002000) RCC_APB2RSTR_ADC3RST ((uint32_t)0x00008000) ¥RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) ¦RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) §RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) ¨RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) ©RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) ¬RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) ¯RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) °RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) ³RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) ´RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) µRCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) ¶RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) ºRCC_APB1RSTR_USBRST ((uint32_t)0x00800000) ¾RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) ¿RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) ÀRCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) ÁRCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) ÂRCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) ÃRCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) ÄRCC_APB1RSTR_DACRST ((uint32_t)0x20000000) ãRCC_AHBENR_DMA1EN ((uint16_t)0x0001) äRCC_AHBENR_SRAMEN ((uint16_t)0x0004) åRCC_AHBENR_FLITFEN ((uint16_t)0x0010) æRCC_AHBENR_CRCEN ((uint16_t)0x0040) éRCC_AHBENR_DMA2EN ((uint16_t)0x0002) íRCC_AHBENR_FSMCEN ((uint16_t)0x0100) îRCC_AHBENR_SDIOEN ((uint16_t)0x0400) ýRCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) þRCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) ÿRCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200)
RCC_APB2ENR_ADC2EN ((uint32_t)0x00000400) RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040) RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) RCC_APB2ENR_TIM8EN ((uint32_t)0x00002000) RCC_APB2ENR_ADC3EN ((uint32_t)0x00008000) ©RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) ªRCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) «RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) ¬RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) °RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) ³RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) ´RCC_APB1ENR_PWREN ((uint32_t)0x10000000) ·RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) ¸RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) ¹RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) ºRCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) ¾RCC_APB1ENR_USBEN ((uint32_t)0x00800000) ÂRCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) ÃRCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) ÄRCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) ÅRCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) ÆRCC_APB1ENR_UART4EN ((uint32_t)0x00080000) ÇRCC_APB1ENR_UART5EN ((uint32_t)0x00100000) ÈRCC_APB1ENR_DACEN ((uint32_t)0x20000000) çRCC_BDCR_LSEON ((uint32_t)0x00000001) èRCC_BDCR_LSERDY ((uint32_t)0x00000002) éRCC_BDCR_LSEBYP ((uint32_t)0x00000004) ëRCC_BDCR_RTCSEL ((uint32_t)0x00000300) ìRCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) íRCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) ðRCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) ñRCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) òRCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) óRCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) õRCC_BDCR_RTCEN ((uint32_t)0x00008000) öRCC_BDCR_BDRST ((uint32_t)0x00010000) ùRCC_CSR_LSION ((uint32_t)0x00000001) úRCC_CSR_LSIRDY ((uint32_t)0x00000002) ûRCC_CSR_RMVF ((uint32_t)0x01000000) üRCC_CSR_PINRSTF ((uint32_t)0x04000000) ýRCC_CSR_PORRSTF ((uint32_t)0x08000000) þRCC_CSR_SFTRSTF ((uint32_t)0x10000000) ÿRCC_CSR_IWDGRSTF ((uint32_t)0x20000000) RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) GPIO_CRL_MODE ((uint32_t)0x33333333) GPIO_CRL_MODE0 ((uint32_t)0x00000003) GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) GPIO_CRL_MODE1 ((uint32_t)0x00000030) GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) GPIO_CRL_MODE2 ((uint32_t)0x00000300) GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) GPIO_CRL_MODE3 ((uint32_t)0x00003000) GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) GPIO_CRL_MODE4 ((uint32_t)0x00030000) GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) GPIO_CRL_MODE5 ((uint32_t)0x00300000) GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) GPIO_CRL_MODE6 ((uint32_t)0x03000000) GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) ¢GPIO_CRL_MODE7 ((uint32_t)0x30000000) £GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) ¤GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) ¦GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) ¨GPIO_CRL_CNF0 ((uint32_t)0x0000000C) ©GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) ªGPIO_CRL_CNF0_1 ((uint32_t)0x00000008) ¬GPIO_CRL_CNF1 ((uint32_t)0x000000C0) GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) ®GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) °GPIO_CRL_CNF2 ((uint32_t)0x00000C00) ±GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) ²GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) ´GPIO_CRL_CNF3 ((uint32_t)0x0000C000) µGPIO_CRL_CNF3_0 ((uint32_t)0x00004000) ¶GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) ¸GPIO_CRL_CNF4 ((uint32_t)0x000C0000) ¹GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) ºGPIO_CRL_CNF4_1 ((uint32_t)0x00080000) ¼GPIO_CRL_CNF5 ((uint32_t)0x00C00000) ½GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) ¾GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) ÀGPIO_CRL_CNF6 ((uint32_t)0x0C000000) ÁGPIO_CRL_CNF6_0 ((uint32_t)0x04000000) ÂGPIO_CRL_CNF6_1 ((uint32_t)0x08000000) ÄGPIO_CRL_CNF7 ((uint32_t)0xC0000000) ÅGPIO_CRL_CNF7_0 ((uint32_t)0x40000000) ÆGPIO_CRL_CNF7_1 ((uint32_t)0x80000000) ÉGPIO_CRH_MODE ((uint32_t)0x33333333) ËGPIO_CRH_MODE8 ((uint32_t)0x00000003) ÌGPIO_CRH_MODE8_0 ((uint32_t)0x00000001) ÍGPIO_CRH_MODE8_1 ((uint32_t)0x00000002) ÏGPIO_CRH_MODE9 ((uint32_t)0x00000030) ÐGPIO_CRH_MODE9_0 ((uint32_t)0x00000010) ÑGPIO_CRH_MODE9_1 ((uint32_t)0x00000020) ÓGPIO_CRH_MODE10 ((uint32_t)0x00000300) ÔGPIO_CRH_MODE10_0 ((uint32_t)0x00000100) ÕGPIO_CRH_MODE10_1 ((uint32_t)0x00000200) ×GPIO_CRH_MODE11 ((uint32_t)0x00003000) ØGPIO_CRH_MODE11_0 ((uint32_t)0x00001000) ÙGPIO_CRH_MODE11_1 ((uint32_t)0x00002000) ÛGPIO_CRH_MODE12 ((uint32_t)0x00030000) ÜGPIO_CRH_MODE12_0 ((uint32_t)0x00010000) ÝGPIO_CRH_MODE12_1 ((uint32_t)0x00020000) ßGPIO_CRH_MODE13 ((uint32_t)0x00300000) àGPIO_CRH_MODE13_0 ((uint32_t)0x00100000) áGPIO_CRH_MODE13_1 ((uint32_t)0x00200000) ãGPIO_CRH_MODE14 ((uint32_t)0x03000000) äGPIO_CRH_MODE14_0 ((uint32_t)0x01000000) åGPIO_CRH_MODE14_1 ((uint32_t)0x02000000) çGPIO_CRH_MODE15 ((uint32_t)0x30000000) èGPIO_CRH_MODE15_0 ((uint32_t)0x10000000) éGPIO_CRH_MODE15_1 ((uint32_t)0x20000000) ëGPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) íGPIO_CRH_CNF8 ((uint32_t)0x0000000C) îGPIO_CRH_CNF8_0 ((uint32_t)0x00000004) ïGPIO_CRH_CNF8_1 ((uint32_t)0x00000008) ñGPIO_CRH_CNF9 ((uint32_t)0x000000C0) òGPIO_CRH_CNF9_0 ((uint32_t)0x00000040) óGPIO_CRH_CNF9_1 ((uint32_t)0x00000080) õGPIO_CRH_CNF10 ((uint32_t)0x00000C00) öGPIO_CRH_CNF10_0 ((uint32_t)0x00000400) ÷GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) ùGPIO_CRH_CNF11 ((uint32_t)0x0000C000) úGPIO_CRH_CNF11_0 ((uint32_t)0x00004000) ûGPIO_CRH_CNF11_1 ((uint32_t)0x00008000) ýGPIO_CRH_CNF12 ((uint32_t)0x000C0000) þGPIO_CRH_CNF12_0 ((uint32_t)0x00040000) ÿGPIO_CRH_CNF12_1 ((uint32_t)0x00080000) GPIO_CRH_CNF13 ((uint32_t)0x00C00000) GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) GPIO_CRH_CNF13_1 ((uint32_t)0x00800000)
GPIO_CRH_CNF14 ((uint32_t)0x0C000000) GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) GPIO_CRH_CNF15 ((uint32_t)0xC0000000) GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) GPIO_IDR_IDR0 ((uint16_t)0x0001) GPIO_IDR_IDR1 ((uint16_t)0x0002) GPIO_IDR_IDR2 ((uint16_t)0x0004) GPIO_IDR_IDR3 ((uint16_t)0x0008) GPIO_IDR_IDR4 ((uint16_t)0x0010) GPIO_IDR_IDR5 ((uint16_t)0x0020) GPIO_IDR_IDR6 ((uint16_t)0x0040) GPIO_IDR_IDR7 ((uint16_t)0x0080) GPIO_IDR_IDR8 ((uint16_t)0x0100) GPIO_IDR_IDR9 ((uint16_t)0x0200) GPIO_IDR_IDR10 ((uint16_t)0x0400) GPIO_IDR_IDR11 ((uint16_t)0x0800) GPIO_IDR_IDR12 ((uint16_t)0x1000) GPIO_IDR_IDR13 ((uint16_t)0x2000) GPIO_IDR_IDR14 ((uint16_t)0x4000) GPIO_IDR_IDR15 ((uint16_t)0x8000) GPIO_ODR_ODR0 ((uint16_t)0x0001) ¡GPIO_ODR_ODR1 ((uint16_t)0x0002) ¢GPIO_ODR_ODR2 ((uint16_t)0x0004) £GPIO_ODR_ODR3 ((uint16_t)0x0008) ¤GPIO_ODR_ODR4 ((uint16_t)0x0010) ¥GPIO_ODR_ODR5 ((uint16_t)0x0020) ¦GPIO_ODR_ODR6 ((uint16_t)0x0040) §GPIO_ODR_ODR7 ((uint16_t)0x0080) ¨GPIO_ODR_ODR8 ((uint16_t)0x0100) ©GPIO_ODR_ODR9 ((uint16_t)0x0200) ªGPIO_ODR_ODR10 ((uint16_t)0x0400) «GPIO_ODR_ODR11 ((uint16_t)0x0800) ¬GPIO_ODR_ODR12 ((uint16_t)0x1000) GPIO_ODR_ODR13 ((uint16_t)0x2000) ®GPIO_ODR_ODR14 ((uint16_t)0x4000) ¯GPIO_ODR_ODR15 ((uint16_t)0x8000) ²GPIO_BSRR_BS0 ((uint32_t)0x00000001) ³GPIO_BSRR_BS1 ((uint32_t)0x00000002) ´GPIO_BSRR_BS2 ((uint32_t)0x00000004) µGPIO_BSRR_BS3 ((uint32_t)0x00000008) ¶GPIO_BSRR_BS4 ((uint32_t)0x00000010) ·GPIO_BSRR_BS5 ((uint32_t)0x00000020) ¸GPIO_BSRR_BS6 ((uint32_t)0x00000040) ¹GPIO_BSRR_BS7 ((uint32_t)0x00000080) ºGPIO_BSRR_BS8 ((uint32_t)0x00000100) »GPIO_BSRR_BS9 ((uint32_t)0x00000200) ¼GPIO_BSRR_BS10 ((uint32_t)0x00000400) ½GPIO_BSRR_BS11 ((uint32_t)0x00000800) ¾GPIO_BSRR_BS12 ((uint32_t)0x00001000) ¿GPIO_BSRR_BS13 ((uint32_t)0x00002000) ÀGPIO_BSRR_BS14 ((uint32_t)0x00004000) ÁGPIO_BSRR_BS15 ((uint32_t)0x00008000) ÃGPIO_BSRR_BR0 ((uint32_t)0x00010000) ÄGPIO_BSRR_BR1 ((uint32_t)0x00020000) ÅGPIO_BSRR_BR2 ((uint32_t)0x00040000) ÆGPIO_BSRR_BR3 ((uint32_t)0x00080000) ÇGPIO_BSRR_BR4 ((uint32_t)0x00100000) ÈGPIO_BSRR_BR5 ((uint32_t)0x00200000) ÉGPIO_BSRR_BR6 ((uint32_t)0x00400000) ÊGPIO_BSRR_BR7 ((uint32_t)0x00800000) ËGPIO_BSRR_BR8 ((uint32_t)0x01000000) ÌGPIO_BSRR_BR9 ((uint32_t)0x02000000) ÍGPIO_BSRR_BR10 ((uint32_t)0x04000000) ÎGPIO_BSRR_BR11 ((uint32_t)0x08000000) ÏGPIO_BSRR_BR12 ((uint32_t)0x10000000) ÐGPIO_BSRR_BR13 ((uint32_t)0x20000000) ÑGPIO_BSRR_BR14 ((uint32_t)0x40000000) ÒGPIO_BSRR_BR15 ((uint32_t)0x80000000) ÕGPIO_BRR_BR0 ((uint16_t)0x0001) ÖGPIO_BRR_BR1 ((uint16_t)0x0002) ×GPIO_BRR_BR2 ((uint16_t)0x0004) ØGPIO_BRR_BR3 ((uint16_t)0x0008) ÙGPIO_BRR_BR4 ((uint16_t)0x0010) ÚGPIO_BRR_BR5 ((uint16_t)0x0020) ÛGPIO_BRR_BR6 ((uint16_t)0x0040) ÜGPIO_BRR_BR7 ((uint16_t)0x0080) ÝGPIO_BRR_BR8 ((uint16_t)0x0100) ÞGPIO_BRR_BR9 ((uint16_t)0x0200) ßGPIO_BRR_BR10 ((uint16_t)0x0400) àGPIO_BRR_BR11 ((uint16_t)0x0800) áGPIO_BRR_BR12 ((uint16_t)0x1000) âGPIO_BRR_BR13 ((uint16_t)0x2000) ãGPIO_BRR_BR14 ((uint16_t)0x4000) äGPIO_BRR_BR15 ((uint16_t)0x8000) çGPIO_LCKR_LCK0 ((uint32_t)0x00000001) èGPIO_LCKR_LCK1 ((uint32_t)0x00000002) éGPIO_LCKR_LCK2 ((uint32_t)0x00000004) êGPIO_LCKR_LCK3 ((uint32_t)0x00000008) ëGPIO_LCKR_LCK4 ((uint32_t)0x00000010) ìGPIO_LCKR_LCK5 ((uint32_t)0x00000020) íGPIO_LCKR_LCK6 ((uint32_t)0x00000040) îGPIO_LCKR_LCK7 ((uint32_t)0x00000080) ïGPIO_LCKR_LCK8 ((uint32_t)0x00000100) ðGPIO_LCKR_LCK9 ((uint32_t)0x00000200) ñGPIO_LCKR_LCK10 ((uint32_t)0x00000400) òGPIO_LCKR_LCK11 ((uint32_t)0x00000800) óGPIO_LCKR_LCK12 ((uint32_t)0x00001000) ôGPIO_LCKR_LCK13 ((uint32_t)0x00002000) õGPIO_LCKR_LCK14 ((uint32_t)0x00004000) öGPIO_LCKR_LCK15 ((uint32_t)0x00008000) ÷GPIO_LCKR_LCKK ((uint32_t)0x00010000) üAFIO_EVCR_PIN ((uint8_t)0x0F) ýAFIO_EVCR_PIN_0 ((uint8_t)0x01) þAFIO_EVCR_PIN_1 ((uint8_t)0x02) ÿAFIO_EVCR_PIN_2 ((uint8_t)0x04) AFIO_EVCR_PIN_3 ((uint8_t)0x08) AFIO_EVCR_PIN_PX0 ((uint8_t)0x00) AFIO_EVCR_PIN_PX1 ((uint8_t)0x01)
AFIO_EVCR_PIN_PX2 ((uint8_t)0x02) AFIO_EVCR_PIN_PX3 ((uint8_t)0x03) AFIO_EVCR_PIN_PX4 ((uint8_t)0x04) AFIO_EVCR_PIN_PX5 ((uint8_t)0x05) AFIO_EVCR_PIN_PX6 ((uint8_t)0x06) AFIO_EVCR_PIN_PX7 ((uint8_t)0x07) AFIO_EVCR_PIN_PX8 ((uint8_t)0x08) AFIO_EVCR_PIN_PX9 ((uint8_t)0x09) AFIO_EVCR_PIN_PX10 ((uint8_t)0x0A) AFIO_EVCR_PIN_PX11 ((uint8_t)0x0B) AFIO_EVCR_PIN_PX12 ((uint8_t)0x0C) AFIO_EVCR_PIN_PX13 ((uint8_t)0x0D) AFIO_EVCR_PIN_PX14 ((uint8_t)0x0E) AFIO_EVCR_PIN_PX15 ((uint8_t)0x0F) AFIO_EVCR_PORT ((uint8_t)0x70) AFIO_EVCR_PORT_0 ((uint8_t)0x10) AFIO_EVCR_PORT_1 ((uint8_t)0x20) AFIO_EVCR_PORT_2 ((uint8_t)0x40) AFIO_EVCR_PORT_PA ((uint8_t)0x00) AFIO_EVCR_PORT_PB ((uint8_t)0x10) AFIO_EVCR_PORT_PC ((uint8_t)0x20) AFIO_EVCR_PORT_PD ((uint8_t)0x30) AFIO_EVCR_PORT_PE ((uint8_t)0x40) AFIO_EVCR_EVOE ((uint8_t)0x80) £AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) ¤AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) ¥AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) ¦AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) ¨AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) ©AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) ªAFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) ®AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) ¯AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) ±AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) ²AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) ³AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) ¶AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) ·AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) ¸AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) ºAFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) »AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) ¼AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) ¿AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) ÀAFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) ÁAFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) ÂAFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) ÄAFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) ÅAFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) ÆAFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) ÉAFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) ÊAFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) ËAFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) ÍAFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) ÏAFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000) ÐAFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000) ÑAFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000) ÔAFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) ÕAFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) ÖAFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) ØAFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) ÙAFIO_MAPR_TIM5CH4_IREMAP ((uint32_t)0x00010000) ÚAFIO_MAPR_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) ÛAFIO_MAPR_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) ÜAFIO_MAPR_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) ÝAFIO_MAPR_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) àAFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) áAFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) âAFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) ãAFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) åAFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) æAFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) çAFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) èAFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) ÿAFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000)
AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004) AFIO_EXTICR1_EXTI0_PF ((uint16_t)0x0005) AFIO_EXTICR1_EXTI0_PG ((uint16_t)0x0006) AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040) AFIO_EXTICR1_EXTI1_PF ((uint16_t)0x0050) AFIO_EXTICR1_EXTI1_PG ((uint16_t)0x0060) AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400) AFIO_EXTICR1_EXTI2_PF ((uint16_t)0x0500) AFIO_EXTICR1_EXTI2_PG ((uint16_t)0x0600) AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) ¡AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) ¢AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) £AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) ¤AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000) ¥AFIO_EXTICR1_EXTI3_PF ((uint16_t)0x5000) ¦AFIO_EXTICR1_EXTI3_PG ((uint16_t)0x6000) ©AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) ªAFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) «AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00) ¬AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000) ¯AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000) °AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001) ±AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002) ²AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003) ³AFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004) ´AFIO_EXTICR2_EXTI4_PF ((uint16_t)0x0005) µAFIO_EXTICR2_EXTI4_PG ((uint16_t)0x0006) ¸AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000) ¹AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010) ºAFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020) »AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030) ¼AFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040) ½AFIO_EXTICR2_EXTI5_PF ((uint16_t)0x0050) ¾AFIO_EXTICR2_EXTI5_PG ((uint16_t)0x0060) ÁAFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000) ÂAFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100) ÃAFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200) ÄAFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300) ÅAFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400) ÆAFIO_EXTICR2_EXTI6_PF ((uint16_t)0x0500) ÇAFIO_EXTICR2_EXTI6_PG ((uint16_t)0x0600) ÊAFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000) ËAFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000) ÌAFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000) ÍAFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000) ÎAFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000) ÏAFIO_EXTICR2_EXTI7_PF ((uint16_t)0x5000) ÐAFIO_EXTICR2_EXTI7_PG ((uint16_t)0x6000) ÓAFIO_EXTICR3_EXTI8 ((uint16_t)0x000F) ÔAFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0) ÕAFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00) ÖAFIO_EXTICR3_EXTI11 ((uint16_t)0xF000) ÙAFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000) ÚAFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001) ÛAFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002) ÜAFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003) ÝAFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004) ÞAFIO_EXTICR3_EXTI8_PF ((uint16_t)0x0005) ßAFIO_EXTICR3_EXTI8_PG ((uint16_t)0x0006) âAFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000) ãAFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010) äAFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020) åAFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030) æAFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040) çAFIO_EXTICR3_EXTI9_PF ((uint16_t)0x0050) èAFIO_EXTICR3_EXTI9_PG ((uint16_t)0x0060) ëAFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000) ìAFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100) íAFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200) îAFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300) ïAFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400) ðAFIO_EXTICR3_EXTI10_PF ((uint16_t)0x0500) ñAFIO_EXTICR3_EXTI10_PG ((uint16_t)0x0600) ôAFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000) õAFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000) öAFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000) ÷AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000) øAFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000) ùAFIO_EXTICR3_EXTI11_PF ((uint16_t)0x5000) úAFIO_EXTICR3_EXTI11_PG ((uint16_t)0x6000) ýAFIO_EXTICR4_EXTI12 ((uint16_t)0x000F) þAFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0) ÿAFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00) AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000) AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000) AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001)
AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002) AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003) AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004) AFIO_EXTICR4_EXTI12_PF ((uint16_t)0x0005) AFIO_EXTICR4_EXTI12_PG ((uint16_t)0x0006) AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000) AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010) AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020) AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030) AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040) AFIO_EXTICR4_EXTI13_PF ((uint16_t)0x0050) AFIO_EXTICR4_EXTI13_PG ((uint16_t)0x0060) AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000) AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100) AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200) AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300) AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400) AFIO_EXTICR4_EXTI14_PF ((uint16_t)0x0500) AFIO_EXTICR4_EXTI14_PG ((uint16_t)0x0600) AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000) AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000) AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000) ¡AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000) ¢AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000) £AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000) ¤AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000) ÉSysTick_CTRL_ENABLE ((uint32_t)0x00000001) ÊSysTick_CTRL_TICKINT ((uint32_t)0x00000002) ËSysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) ÌSysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) ÏSysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) ÒSysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) ÕSysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) ÖSysTick_CALIB_SKEW ((uint32_t)0x40000000) ×SysTick_CALIB_NOREF ((uint32_t)0x80000000) àNVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) áNVIC_ISER_SETENA_0 ((uint32_t)0x00000001) âNVIC_ISER_SETENA_1 ((uint32_t)0x00000002) ãNVIC_ISER_SETENA_2 ((uint32_t)0x00000004) äNVIC_ISER_SETENA_3 ((uint32_t)0x00000008) åNVIC_ISER_SETENA_4 ((uint32_t)0x00000010) æNVIC_ISER_SETENA_5 ((uint32_t)0x00000020) çNVIC_ISER_SETENA_6 ((uint32_t)0x00000040) èNVIC_ISER_SETENA_7 ((uint32_t)0x00000080) éNVIC_ISER_SETENA_8 ((uint32_t)0x00000100) êNVIC_ISER_SETENA_9 ((uint32_t)0x00000200) ëNVIC_ISER_SETENA_10 ((uint32_t)0x00000400) ìNVIC_ISER_SETENA_11 ((uint32_t)0x00000800) íNVIC_ISER_SETENA_12 ((uint32_t)0x00001000) îNVIC_ISER_SETENA_13 ((uint32_t)0x00002000) ïNVIC_ISER_SETENA_14 ((uint32_t)0x00004000) ðNVIC_ISER_SETENA_15 ((uint32_t)0x00008000) ñNVIC_ISER_SETENA_16 ((uint32_t)0x00010000) òNVIC_ISER_SETENA_17 ((uint32_t)0x00020000) óNVIC_ISER_SETENA_18 ((uint32_t)0x00040000) ôNVIC_ISER_SETENA_19 ((uint32_t)0x00080000) õNVIC_ISER_SETENA_20 ((uint32_t)0x00100000) öNVIC_ISER_SETENA_21 ((uint32_t)0x00200000) ÷NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) øNVIC_ISER_SETENA_23 ((uint32_t)0x00800000) ùNVIC_ISER_SETENA_24 ((uint32_t)0x01000000) úNVIC_ISER_SETENA_25 ((uint32_t)0x02000000) ûNVIC_ISER_SETENA_26 ((uint32_t)0x04000000) üNVIC_ISER_SETENA_27 ((uint32_t)0x08000000) ýNVIC_ISER_SETENA_28 ((uint32_t)0x10000000) þNVIC_ISER_SETENA_29 ((uint32_t)0x20000000) ÿNVIC_ISER_SETENA_30 ((uint32_t)0x40000000) NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001)
NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) ¡NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) ¢NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) £NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) ¦NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) §NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) ¨NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) ©NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) ªNVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) «NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) ¬NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) ®NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) ¯NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) °NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) ±NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) ²NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) ³NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) ´NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) µNVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) ¶NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) ·NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) ¸NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) ¹NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) ºNVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) »NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) ¼NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) ½NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) ¾NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) ¿NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) ÀNVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) ÁNVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) ÂNVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) ÃNVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) ÄNVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) ÅNVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) ÆNVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) ÉNVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) ÊNVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) ËNVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) ÌNVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) ÍNVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) ÎNVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) ÏNVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) ÐNVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) ÑNVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) ÒNVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) ÓNVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) ÔNVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) ÕNVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) ÖNVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) ×NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) ØNVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) ÙNVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) ÚNVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) ÛNVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) ÜNVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) ÝNVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) ÞNVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) ßNVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) àNVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) áNVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) âNVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) ãNVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) äNVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) åNVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) æNVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) çNVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) èNVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) éNVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) ìNVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) íNVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) îNVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) ïNVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) ðNVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) ñNVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) òNVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) óNVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) ôNVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) õNVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) öNVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) ÷NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) øNVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) ùNVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) úNVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) ûNVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) üNVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) ýNVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) þNVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) ÿNVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000)
NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) ¡NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) ¢NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) £NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) ¤NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) §NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) ¨NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) ©NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) ªNVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) ®NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) ¯NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) °NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) ³NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) ´NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) µNVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) ¶NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) ¹NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) ºNVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) »NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) ¼NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) ¿SCB_CPUID_REVISION ((uint32_t)0x0000000F) ÀSCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) ÁSCB_CPUID_Constant ((uint32_t)0x000F0000) ÂSCB_CPUID_VARIANT ((uint32_t)0x00F00000) ÃSCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) ÆSCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) ÇSCB_ICSR_RETTOBASE ((uint32_t)0x00000800) ÈSCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) ÉSCB_ICSR_ISRPENDING ((uint32_t)0x00400000) ÊSCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) ËSCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) ÌSCB_ICSR_PENDSTSET ((uint32_t)0x04000000) ÍSCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) ÎSCB_ICSR_PENDSVSET ((uint32_t)0x10000000) ÏSCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) ÒSCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) ÓSCB_VTOR_TBLBASE ((uint32_t)0x20000000) ÖSCB_AIRCR_VECTRESET ((uint32_t)0x00000001) ×SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) ØSCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) ÚSCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) ÛSCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) ÜSCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) ÝSCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) àSCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) áSCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) âSCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) ãSCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) äSCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) åSCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) æSCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) çSCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) éSCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) êSCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) íSCB_SCR_SLEEPONEXIT ((uint8_t)0x02) îSCB_SCR_SLEEPDEEP ((uint8_t)0x04) ïSCB_SCR_SEVONPEND ((uint8_t)0x10) òSCB_CCR_NONBASETHRDENA ((uint16_t)0x0001) óSCB_CCR_USERSETMPEND ((uint16_t)0x0002) ôSCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) õSCB_CCR_DIV_0_TRP ((uint16_t)0x0010) öSCB_CCR_BFHFNMIGN ((uint16_t)0x0100) ÷SCB_CCR_STKALIGN ((uint16_t)0x0200) úSCB_SHPR_PRI_N ((uint32_t)0x000000FF) ûSCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) üSCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) ýSCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) SCB_SHCSR_MONITORACT ((uint32_t)0x00000100)
SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) SCB_CFSR_MSTKERR ((uint32_t)0x00000010) SCB_CFSR_MMARVALID ((uint32_t)0x00000080) SCB_CFSR_IBUSERR ((uint32_t)0x00000100) SCB_CFSR_PRECISERR ((uint32_t)0x00000200) SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) SCB_CFSR_STKERR ((uint32_t)0x00001000) SCB_CFSR_BFARVALID ((uint32_t)0x00008000) SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) SCB_CFSR_INVSTATE ((uint32_t)0x00020000) SCB_CFSR_INVPC ((uint32_t)0x00040000) ¡SCB_CFSR_NOCP ((uint32_t)0x00080000) ¢SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) £SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) ¦SCB_HFSR_VECTTBL ((uint32_t)0x00000002) §SCB_HFSR_FORCED ((uint32_t)0x40000000) ¨SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) «SCB_DFSR_HALTED ((uint8_t)0x01) ¬SCB_DFSR_BKPT ((uint8_t)0x02) SCB_DFSR_DWTTRAP ((uint8_t)0x04) ®SCB_DFSR_VCATCH ((uint8_t)0x08) ¯SCB_DFSR_EXTERNAL ((uint8_t)0x10) ²SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) µSCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) ¸SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) ÁEXTI_IMR_MR0 ((uint32_t)0x00000001) ÂEXTI_IMR_MR1 ((uint32_t)0x00000002) ÃEXTI_IMR_MR2 ((uint32_t)0x00000004) ÄEXTI_IMR_MR3 ((uint32_t)0x00000008) ÅEXTI_IMR_MR4 ((uint32_t)0x00000010) ÆEXTI_IMR_MR5 ((uint32_t)0x00000020) ÇEXTI_IMR_MR6 ((uint32_t)0x00000040) ÈEXTI_IMR_MR7 ((uint32_t)0x00000080) ÉEXTI_IMR_MR8 ((uint32_t)0x00000100) ÊEXTI_IMR_MR9 ((uint32_t)0x00000200) ËEXTI_IMR_MR10 ((uint32_t)0x00000400) ÌEXTI_IMR_MR11 ((uint32_t)0x00000800) ÍEXTI_IMR_MR12 ((uint32_t)0x00001000) ÎEXTI_IMR_MR13 ((uint32_t)0x00002000) ÏEXTI_IMR_MR14 ((uint32_t)0x00004000) ÐEXTI_IMR_MR15 ((uint32_t)0x00008000) ÑEXTI_IMR_MR16 ((uint32_t)0x00010000) ÒEXTI_IMR_MR17 ((uint32_t)0x00020000) ÓEXTI_IMR_MR18 ((uint32_t)0x00040000) ÔEXTI_IMR_MR19 ((uint32_t)0x00080000) ×EXTI_EMR_MR0 ((uint32_t)0x00000001) ØEXTI_EMR_MR1 ((uint32_t)0x00000002) ÙEXTI_EMR_MR2 ((uint32_t)0x00000004) ÚEXTI_EMR_MR3 ((uint32_t)0x00000008) ÛEXTI_EMR_MR4 ((uint32_t)0x00000010) ÜEXTI_EMR_MR5 ((uint32_t)0x00000020) ÝEXTI_EMR_MR6 ((uint32_t)0x00000040) ÞEXTI_EMR_MR7 ((uint32_t)0x00000080) ßEXTI_EMR_MR8 ((uint32_t)0x00000100) àEXTI_EMR_MR9 ((uint32_t)0x00000200) áEXTI_EMR_MR10 ((uint32_t)0x00000400) âEXTI_EMR_MR11 ((uint32_t)0x00000800) ãEXTI_EMR_MR12 ((uint32_t)0x00001000) äEXTI_EMR_MR13 ((uint32_t)0x00002000) åEXTI_EMR_MR14 ((uint32_t)0x00004000) æEXTI_EMR_MR15 ((uint32_t)0x00008000) çEXTI_EMR_MR16 ((uint32_t)0x00010000) èEXTI_EMR_MR17 ((uint32_t)0x00020000) éEXTI_EMR_MR18 ((uint32_t)0x00040000) êEXTI_EMR_MR19 ((uint32_t)0x00080000) íEXTI_RTSR_TR0 ((uint32_t)0x00000001) îEXTI_RTSR_TR1 ((uint32_t)0x00000002) ïEXTI_RTSR_TR2 ((uint32_t)0x00000004) ðEXTI_RTSR_TR3 ((uint32_t)0x00000008) ñEXTI_RTSR_TR4 ((uint32_t)0x00000010) òEXTI_RTSR_TR5 ((uint32_t)0x00000020) óEXTI_RTSR_TR6 ((uint32_t)0x00000040) ôEXTI_RTSR_TR7 ((uint32_t)0x00000080) õEXTI_RTSR_TR8 ((uint32_t)0x00000100) öEXTI_RTSR_TR9 ((uint32_t)0x00000200) ÷EXTI_RTSR_TR10 ((uint32_t)0x00000400) øEXTI_RTSR_TR11 ((uint32_t)0x00000800) ùEXTI_RTSR_TR12 ((uint32_t)0x00001000) úEXTI_RTSR_TR13 ((uint32_t)0x00002000) ûEXTI_RTSR_TR14 ((uint32_t)0x00004000) üEXTI_RTSR_TR15 ((uint32_t)0x00008000) ýEXTI_RTSR_TR16 ((uint32_t)0x00010000) þEXTI_RTSR_TR17 ((uint32_t)0x00020000) ÿEXTI_RTSR_TR18 ((uint32_t)0x00040000) EXTI_RTSR_TR19 ((uint32_t)0x00080000) EXTI_FTSR_TR0 ((uint32_t)0x00000001) EXTI_FTSR_TR1 ((uint32_t)0x00000002)
EXTI_FTSR_TR2 ((uint32_t)0x00000004) EXTI_FTSR_TR3 ((uint32_t)0x00000008) EXTI_FTSR_TR4 ((uint32_t)0x00000010) EXTI_FTSR_TR5 ((uint32_t)0x00000020) EXTI_FTSR_TR6 ((uint32_t)0x00000040) EXTI_FTSR_TR7 ((uint32_t)0x00000080) EXTI_FTSR_TR8 ((uint32_t)0x00000100) EXTI_FTSR_TR9 ((uint32_t)0x00000200) EXTI_FTSR_TR10 ((uint32_t)0x00000400) EXTI_FTSR_TR11 ((uint32_t)0x00000800) EXTI_FTSR_TR12 ((uint32_t)0x00001000) EXTI_FTSR_TR13 ((uint32_t)0x00002000) EXTI_FTSR_TR14 ((uint32_t)0x00004000) EXTI_FTSR_TR15 ((uint32_t)0x00008000) EXTI_FTSR_TR16 ((uint32_t)0x00010000) EXTI_FTSR_TR17 ((uint32_t)0x00020000) EXTI_FTSR_TR18 ((uint32_t)0x00040000) EXTI_FTSR_TR19 ((uint32_t)0x00080000) EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) ¡EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) ¢EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) £EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) ¤EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) ¥EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) ¦EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) §EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) ¨EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) ©EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) ªEXTI_SWIER_SWIER17 ((uint32_t)0x00020000) «EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) ¬EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) ¯EXTI_PR_PR0 ((uint32_t)0x00000001) °EXTI_PR_PR1 ((uint32_t)0x00000002) ±EXTI_PR_PR2 ((uint32_t)0x00000004) ²EXTI_PR_PR3 ((uint32_t)0x00000008) ³EXTI_PR_PR4 ((uint32_t)0x00000010) ´EXTI_PR_PR5 ((uint32_t)0x00000020) µEXTI_PR_PR6 ((uint32_t)0x00000040) ¶EXTI_PR_PR7 ((uint32_t)0x00000080) ·EXTI_PR_PR8 ((uint32_t)0x00000100) ¸EXTI_PR_PR9 ((uint32_t)0x00000200) ¹EXTI_PR_PR10 ((uint32_t)0x00000400) ºEXTI_PR_PR11 ((uint32_t)0x00000800) »EXTI_PR_PR12 ((uint32_t)0x00001000) ¼EXTI_PR_PR13 ((uint32_t)0x00002000) ½EXTI_PR_PR14 ((uint32_t)0x00004000) ¾EXTI_PR_PR15 ((uint32_t)0x00008000) ¿EXTI_PR_PR16 ((uint32_t)0x00010000) ÀEXTI_PR_PR17 ((uint32_t)0x00020000) ÁEXTI_PR_PR18 ((uint32_t)0x00040000) ÂEXTI_PR_PR19 ((uint32_t)0x00080000) ËDMA_ISR_GIF1 ((uint32_t)0x00000001) ÌDMA_ISR_TCIF1 ((uint32_t)0x00000002) ÍDMA_ISR_HTIF1 ((uint32_t)0x00000004) ÎDMA_ISR_TEIF1 ((uint32_t)0x00000008) ÏDMA_ISR_GIF2 ((uint32_t)0x00000010) ÐDMA_ISR_TCIF2 ((uint32_t)0x00000020) ÑDMA_ISR_HTIF2 ((uint32_t)0x00000040) ÒDMA_ISR_TEIF2 ((uint32_t)0x00000080) ÓDMA_ISR_GIF3 ((uint32_t)0x00000100) ÔDMA_ISR_TCIF3 ((uint32_t)0x00000200) ÕDMA_ISR_HTIF3 ((uint32_t)0x00000400) ÖDMA_ISR_TEIF3 ((uint32_t)0x00000800) ×DMA_ISR_GIF4 ((uint32_t)0x00001000) ØDMA_ISR_TCIF4 ((uint32_t)0x00002000) ÙDMA_ISR_HTIF4 ((uint32_t)0x00004000) ÚDMA_ISR_TEIF4 ((uint32_t)0x00008000) ÛDMA_ISR_GIF5 ((uint32_t)0x00010000) ÜDMA_ISR_TCIF5 ((uint32_t)0x00020000) ÝDMA_ISR_HTIF5 ((uint32_t)0x00040000) ÞDMA_ISR_TEIF5 ((uint32_t)0x00080000) ßDMA_ISR_GIF6 ((uint32_t)0x00100000) àDMA_ISR_TCIF6 ((uint32_t)0x00200000) áDMA_ISR_HTIF6 ((uint32_t)0x00400000) âDMA_ISR_TEIF6 ((uint32_t)0x00800000) ãDMA_ISR_GIF7 ((uint32_t)0x01000000) äDMA_ISR_TCIF7 ((uint32_t)0x02000000) åDMA_ISR_HTIF7 ((uint32_t)0x04000000) æDMA_ISR_TEIF7 ((uint32_t)0x08000000) éDMA_IFCR_CGIF1 ((uint32_t)0x00000001) êDMA_IFCR_CTCIF1 ((uint32_t)0x00000002) ëDMA_IFCR_CHTIF1 ((uint32_t)0x00000004) ìDMA_IFCR_CTEIF1 ((uint32_t)0x00000008) íDMA_IFCR_CGIF2 ((uint32_t)0x00000010) îDMA_IFCR_CTCIF2 ((uint32_t)0x00000020) ïDMA_IFCR_CHTIF2 ((uint32_t)0x00000040) ðDMA_IFCR_CTEIF2 ((uint32_t)0x00000080) ñDMA_IFCR_CGIF3 ((uint32_t)0x00000100) òDMA_IFCR_CTCIF3 ((uint32_t)0x00000200) óDMA_IFCR_CHTIF3 ((uint32_t)0x00000400) ôDMA_IFCR_CTEIF3 ((uint32_t)0x00000800) õDMA_IFCR_CGIF4 ((uint32_t)0x00001000) öDMA_IFCR_CTCIF4 ((uint32_t)0x00002000) ÷DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) øDMA_IFCR_CTEIF4 ((uint32_t)0x00008000) ùDMA_IFCR_CGIF5 ((uint32_t)0x00010000) úDMA_IFCR_CTCIF5 ((uint32_t)0x00020000) ûDMA_IFCR_CHTIF5 ((uint32_t)0x00040000) üDMA_IFCR_CTEIF5 ((uint32_t)0x00080000) ýDMA_IFCR_CGIF6 ((uint32_t)0x00100000) þDMA_IFCR_CTCIF6 ((uint32_t)0x00200000) ÿDMA_IFCR_CHTIF6 ((uint32_t)0x00400000) DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) DMA_IFCR_CGIF7 ((uint32_t)0x01000000) DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) DMA_CCR1_EN ((uint16_t)0x0001) DMA_CCR1_TCIE ((uint16_t)0x0002) DMA_CCR1_HTIE ((uint16_t)0x0004) DMA_CCR1_TEIE ((uint16_t)0x0008) DMA_CCR1_DIR ((uint16_t)0x0010) DMA_CCR1_CIRC ((uint16_t)0x0020) DMA_CCR1_PINC ((uint16_t)0x0040) DMA_CCR1_MINC ((uint16_t)0x0080) DMA_CCR1_PSIZE ((uint16_t)0x0300) DMA_CCR1_PSIZE_0 ((uint16_t)0x0100) DMA_CCR1_PSIZE_1 ((uint16_t)0x0200) DMA_CCR1_MSIZE ((uint16_t)0x0C00) DMA_CCR1_MSIZE_0 ((uint16_t)0x0400) DMA_CCR1_MSIZE_1 ((uint16_t)0x0800) DMA_CCR1_PL ((uint16_t)0x3000) DMA_CCR1_PL_0 ((uint16_t)0x1000) DMA_CCR1_PL_1 ((uint16_t)0x2000) DMA_CCR1_MEM2MEM ((uint16_t)0x4000) DMA_CCR2_EN ((uint16_t)0x0001) DMA_CCR2_TCIE ((uint16_t)0x0002) ¡DMA_CCR2_HTIE ((uint16_t)0x0004) ¢DMA_CCR2_TEIE ((uint16_t)0x0008) £DMA_CCR2_DIR ((uint16_t)0x0010) ¤DMA_CCR2_CIRC ((uint16_t)0x0020) ¥DMA_CCR2_PINC ((uint16_t)0x0040) ¦DMA_CCR2_MINC ((uint16_t)0x0080) ¨DMA_CCR2_PSIZE ((uint16_t)0x0300) ©DMA_CCR2_PSIZE_0 ((uint16_t)0x0100) ªDMA_CCR2_PSIZE_1 ((uint16_t)0x0200) ¬DMA_CCR2_MSIZE ((uint16_t)0x0C00) DMA_CCR2_MSIZE_0 ((uint16_t)0x0400) ®DMA_CCR2_MSIZE_1 ((uint16_t)0x0800) °DMA_CCR2_PL ((uint16_t)0x3000) ±DMA_CCR2_PL_0 ((uint16_t)0x1000) ²DMA_CCR2_PL_1 ((uint16_t)0x2000) ´DMA_CCR2_MEM2MEM ((uint16_t)0x4000) ·DMA_CCR3_EN ((uint16_t)0x0001) ¸DMA_CCR3_TCIE ((uint16_t)0x0002) ¹DMA_CCR3_HTIE ((uint16_t)0x0004) ºDMA_CCR3_TEIE ((uint16_t)0x0008) »DMA_CCR3_DIR ((uint16_t)0x0010) ¼DMA_CCR3_CIRC ((uint16_t)0x0020) ½DMA_CCR3_PINC ((uint16_t)0x0040) ¾DMA_CCR3_MINC ((uint16_t)0x0080) ÀDMA_CCR3_PSIZE ((uint16_t)0x0300) ÁDMA_CCR3_PSIZE_0 ((uint16_t)0x0100) ÂDMA_CCR3_PSIZE_1 ((uint16_t)0x0200) ÄDMA_CCR3_MSIZE ((uint16_t)0x0C00) ÅDMA_CCR3_MSIZE_0 ((uint16_t)0x0400) ÆDMA_CCR3_MSIZE_1 ((uint16_t)0x0800) ÈDMA_CCR3_PL ((uint16_t)0x3000) ÉDMA_CCR3_PL_0 ((uint16_t)0x1000) ÊDMA_CCR3_PL_1 ((uint16_t)0x2000) ÌDMA_CCR3_MEM2MEM ((uint16_t)0x4000) ÏDMA_CCR4_EN ((uint16_t)0x0001) ÐDMA_CCR4_TCIE ((uint16_t)0x0002) ÑDMA_CCR4_HTIE ((uint16_t)0x0004) ÒDMA_CCR4_TEIE ((uint16_t)0x0008) ÓDMA_CCR4_DIR ((uint16_t)0x0010) ÔDMA_CCR4_CIRC ((uint16_t)0x0020) ÕDMA_CCR4_PINC ((uint16_t)0x0040) ÖDMA_CCR4_MINC ((uint16_t)0x0080) ØDMA_CCR4_PSIZE ((uint16_t)0x0300) ÙDMA_CCR4_PSIZE_0 ((uint16_t)0x0100) ÚDMA_CCR4_PSIZE_1 ((uint16_t)0x0200) ÜDMA_CCR4_MSIZE ((uint16_t)0x0C00) ÝDMA_CCR4_MSIZE_0 ((uint16_t)0x0400) ÞDMA_CCR4_MSIZE_1 ((uint16_t)0x0800) àDMA_CCR4_PL ((uint16_t)0x3000) áDMA_CCR4_PL_0 ((uint16_t)0x1000) âDMA_CCR4_PL_1 ((uint16_t)0x2000) äDMA_CCR4_MEM2MEM ((uint16_t)0x4000) çDMA_CCR5_EN ((uint16_t)0x0001) èDMA_CCR5_TCIE ((uint16_t)0x0002) éDMA_CCR5_HTIE ((uint16_t)0x0004) êDMA_CCR5_TEIE ((uint16_t)0x0008) ëDMA_CCR5_DIR ((uint16_t)0x0010) ìDMA_CCR5_CIRC ((uint16_t)0x0020) íDMA_CCR5_PINC ((uint16_t)0x0040) îDMA_CCR5_MINC ((uint16_t)0x0080) ðDMA_CCR5_PSIZE ((uint16_t)0x0300) ñDMA_CCR5_PSIZE_0 ((uint16_t)0x0100) òDMA_CCR5_PSIZE_1 ((uint16_t)0x0200) ôDMA_CCR5_MSIZE ((uint16_t)0x0C00) õDMA_CCR5_MSIZE_0 ((uint16_t)0x0400) öDMA_CCR5_MSIZE_1 ((uint16_t)0x0800) øDMA_CCR5_PL ((uint16_t)0x3000) ùDMA_CCR5_PL_0 ((uint16_t)0x1000) úDMA_CCR5_PL_1 ((uint16_t)0x2000) üDMA_CCR5_MEM2MEM ((uint16_t)0x4000) ÿDMA_CCR6_EN ((uint16_t)0x0001) DMA_CCR6_TCIE ((uint16_t)0x0002) DMA_CCR6_HTIE ((uint16_t)0x0004) DMA_CCR6_TEIE ((uint16_t)0x0008) DMA_CCR6_DIR ((uint16_t)0x0010) DMA_CCR6_CIRC ((uint16_t)0x0020)
DMA_CCR6_PINC ((uint16_t)0x0040) DMA_CCR6_MINC ((uint16_t)0x0080) DMA_CCR6_PSIZE ((uint16_t)0x0300) DMA_CCR6_PSIZE_0 ((uint16_t)0x0100) DMA_CCR6_PSIZE_1 ((uint16_t)0x0200) DMA_CCR6_MSIZE ((uint16_t)0x0C00) DMA_CCR6_MSIZE_0 ((uint16_t)0x0400) DMA_CCR6_MSIZE_1 ((uint16_t)0x0800) DMA_CCR6_PL ((uint16_t)0x3000) DMA_CCR6_PL_0 ((uint16_t)0x1000) DMA_CCR6_PL_1 ((uint16_t)0x2000) DMA_CCR6_MEM2MEM ((uint16_t)0x4000) DMA_CCR7_EN ((uint16_t)0x0001) DMA_CCR7_TCIE ((uint16_t)0x0002) DMA_CCR7_HTIE ((uint16_t)0x0004) DMA_CCR7_TEIE ((uint16_t)0x0008) DMA_CCR7_DIR ((uint16_t)0x0010) DMA_CCR7_CIRC ((uint16_t)0x0020) DMA_CCR7_PINC ((uint16_t)0x0040) DMA_CCR7_MINC ((uint16_t)0x0080) DMA_CCR7_PSIZE , ((uint16_t)0x0300) ¡ DMA_CCR7_PSIZE_0 ((uint16_t)0x0100) ¢ DMA_CCR7_PSIZE_1 ((uint16_t)0x0200) ¤ DMA_CCR7_MSIZE ((uint16_t)0x0C00) ¥ DMA_CCR7_MSIZE_0 ((uint16_t)0x0400) ¦ DMA_CCR7_MSIZE_1 ((uint16_t)0x0800) ¨ DMA_CCR7_PL ((uint16_t)0x3000) © DMA_CCR7_PL_0 ((uint16_t)0x1000) ª DMA_CCR7_PL_1 ((uint16_t)0x2000) ¬ DMA_CCR7_MEM2MEM ((uint16_t)0x4000) ¯ DMA_CNDTR1_NDT ((uint16_t)0xFFFF) ² DMA_CNDTR2_NDT ((uint16_t)0xFFFF) µ DMA_CNDTR3_NDT ((uint16_t)0xFFFF) ¸ DMA_CNDTR4_NDT ((uint16_t)0xFFFF) » DMA_CNDTR5_NDT ((uint16_t)0xFFFF) ¾ DMA_CNDTR6_NDT ((uint16_t)0xFFFF) Á DMA_CNDTR7_NDT ((uint16_t)0xFFFF) Ä DMA_CPAR1_PA ((uint32_t)0xFFFFFFFF) Ç DMA_CPAR2_PA ((uint32_t)0xFFFFFFFF) Ê DMA_CPAR3_PA ((uint32_t)0xFFFFFFFF) Î DMA_CPAR4_PA ((uint32_t)0xFFFFFFFF) Ñ DMA_CPAR5_PA ((uint32_t)0xFFFFFFFF) Ô DMA_CPAR6_PA ((uint32_t)0xFFFFFFFF) Ø DMA_CPAR7_PA ((uint32_t)0xFFFFFFFF) Û DMA_CMAR1_MA ((uint32_t)0xFFFFFFFF) Þ DMA_CMAR2_MA ((uint32_t)0xFFFFFFFF) á DMA_CMAR3_MA ((uint32_t)0xFFFFFFFF) å DMA_CMAR4_MA ((uint32_t)0xFFFFFFFF) è DMA_CMAR5_MA ((uint32_t)0xFFFFFFFF) ë DMA_CMAR6_MA ((uint32_t)0xFFFFFFFF) î DMA_CMAR7_MA ((uint32_t)0xFFFFFFFF) ÷ ADC_SR_AWD ((uint8_t)0x01) ø ADC_SR_EOC ((uint8_t)0x02) ù ADC_SR_JEOC ((uint8_t)0x04) ú ADC_SR_JSTRT ((uint8_t)0x08) û ADC_SR_STRT ((uint8_t)0x10) þ ADC_CR1_AWDCH ((uint32_t)0x0000001F) ÿ ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) ADC_CR1_AWDCH_4 ((uint32_t)0x00000010)
ADC_CR1_EOCIE ((uint32_t)0x00000020) ADC_CR1_AWDIE ((uint32_t)0x00000040) ADC_CR1_JEOCIE ((uint32_t)0x00000080) ADC_CR1_SCAN ((uint32_t)0x00000100) ADC_CR1_AWDSGL ((uint32_t)0x00000200) ADC_CR1_JAUTO ((uint32_t)0x00000400) ADC_CR1_DISCEN ((uint32_t)0x00000800) ADC_CR1_JDISCEN ((uint32_t)0x00001000) ADC_CR1_DISCNUM ((uint32_t)0x0000E000) ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) ADC_CR1_DUALMOD ((uint32_t)0x000F0000) ADC_CR1_DUALMOD_0 ((uint32_t)0x00010000) ADC_CR1_DUALMOD_1 ((uint32_t)0x00020000) ADC_CR1_DUALMOD_2 ((uint32_t)0x00040000) ADC_CR1_DUALMOD_3 ((uint32_t)0x00080000) ADC_CR1_JAWDEN ((uint32_t)0x00400000) ADC_CR1_AWDEN ((uint32_t)0x00800000) ADC_CR2_ADON ((uint32_t)0x00000001) ADC_CR2_CONT ((uint32_t)0x00000002) ADC_CR2_CAL ((uint32_t)0x00000004) ¡ ADC_CR2_RSTCAL ((uint32_t)0x00000008) ¢ ADC_CR2_DMA ((uint32_t)0x00000100) £ ADC_CR2_ALIGN ((uint32_t)0x00000800) ¥ ADC_CR2_JEXTSEL ((uint32_t)0x00007000) ¦ ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) § ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) ¨ ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) ª ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) ¬ ADC_CR2_EXTSEL ((uint32_t)0x000E0000) ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) ® ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) ¯ ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) ± ADC_CR2_EXTTRIG ((uint32_t)0x00100000) ² ADC_CR2_JSWSTART ((uint32_t)0x00200000) ³ ADC_CR2_SWSTART ((uint32_t)0x00400000) ´ ADC_CR2_TSVREFE ((uint32_t)0x00800000) · ADC_SMPR1_SMP10 ((uint32_t)0x00000007) ¸ ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) ¹ ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) º ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) ¼ ADC_SMPR1_SMP11 ((uint32_t)0x00000038) ½ ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) ¾ ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) ¿ ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) Á ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) Â ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) Ã ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) Ä ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) Æ ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) Ç ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) È ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) É ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) Ë ADC_SMPR1_SMP14 ((uint32_t)0x00007000) Ì ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) Í ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) Î ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) Ð ADC_SMPR1_SMP15 ((uint32_t)0x00038000) Ñ ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) Ò ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) Ó ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) Õ ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) Ö ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) × ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) Ø ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) Ú ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) Û ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) Ü ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) Ý ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) à ADC_SMPR2_SMP0 ((uint32_t)0x00000007) á ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) â ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) ã ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) å ADC_SMPR2_SMP1 ((uint32_t)0x00000038) æ ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) ç ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) è ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) ê ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) ë ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) ì ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) í ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) ï ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) ð ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) ñ ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) ò ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) ô ADC_SMPR2_SMP4 ((uint32_t)0x00007000) õ ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) ö ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) ÷ ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) ù ADC_SMPR2_SMP5 ((uint32_t)0x00038000) ú ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) û ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) ü ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) þ ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) ÿ ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000)
ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) ADC_SMPR2_SMP8 ((uint32_t)0x07000000) ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) ADC_SMPR2_SMP9 ((uint32_t)0x38000000) ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF) ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF) ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF) ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF) ADC_HTR_HT ((uint16_t)0x0FFF) ¢ ADC_LTR_LT ((uint16_t)0x0FFF) ¥ ADC_SQR1_SQ13 ((uint32_t)0x0000001F) ¦ ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) § ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) ¨ ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) © ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) ª ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) ¬ ADC_SQR1_SQ14 ((uint32_t)0x000003E0) ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) ® ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) ¯ ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) ° ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) ± ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) ³ ADC_SQR1_SQ15 ((uint32_t)0x00007C00) ´ ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) µ ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) ¶ ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) · ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) ¸ ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) º ADC_SQR1_SQ16 ((uint32_t)0x000F8000) » ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) ¼ ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) ½ ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) ¾ ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) ¿ ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) Á ADC_SQR1_L ((uint32_t)0x00F00000) Â ADC_SQR1_L_0 ((uint32_t)0x00100000) Ã ADC_SQR1_L_1 ((uint32_t)0x00200000) Ä ADC_SQR1_L_2 ((uint32_t)0x00400000) Å ADC_SQR1_L_3 ((uint32_t)0x00800000) È ADC_SQR2_SQ7 ((uint32_t)0x0000001F) É ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) Ê ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) Ë ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) Ì ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) Í ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) Ï ADC_SQR2_SQ8 ((uint32_t)0x000003E0) Ð ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) Ñ ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) Ò ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) Ó ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) Ô ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) Ö ADC_SQR2_SQ9 ((uint32_t)0x00007C00) × ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) Ø ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) Ù ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) Ú ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) Û ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) Ý ADC_SQR2_SQ10 ((uint32_t)0x000F8000) Þ ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) ß ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) à ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) á ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) â ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) ä ADC_SQR2_SQ11 ((uint32_t)0x01F00000) å ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) æ ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) ç ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) è ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) é ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) ë ADC_SQR2_SQ12 ((uint32_t)0x3E000000) ì ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) í ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) î ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) ï ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) ð ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) ó ADC_SQR3_SQ1 ((uint32_t)0x0000001F) ô ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) õ ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) ö ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) ÷ ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) ø ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) ú ADC_SQR3_SQ2 ((uint32_t)0x000003E0) û ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) ü ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) ý ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) þ ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) ÿ ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) ADC_SQR3_SQ3 ((uint32_t)0x00007C00) ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) ADC_SQR3_SQ3_2 ((uint32_t)0x00001000)
ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) ADC_SQR3_SQ4 ((uint32_t)0x000F8000) ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) ADC_SQR3_SQ5 ((uint32_t)0x01F00000) ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) ADC_SQR3_SQ6 ((uint32_t)0x3E000000) ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) ¡ ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) ¢ ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) £ ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) ¥ ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) ¦ ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) § ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) ¨ ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) © ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) ª ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) ¬ ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) ® ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) ¯ ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) ° ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) ± ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) ³ ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) ´ ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) µ ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) ¶ ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) · ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) ¸ ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) º ADC_JSQR_JL ((uint32_t)0x00300000) » ADC_JSQR_JL_0 ((uint32_t)0x00100000) ¼ ADC_JSQR_JL_1 ((uint32_t)0x00200000) ¿ ADC_JDR1_JDATA ((uint16_t)0xFFFF) Â ADC_JDR2_JDATA ((uint16_t)0xFFFF) Å ADC_JDR3_JDATA ((uint16_t)0xFFFF) È ADC_JDR4_JDATA ((uint16_t)0xFFFF) Ë ADC_DR_DATA ((uint32_t)0x0000FFFF) Ì ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) Õ DAC_CR_EN1 ((uint32_t)0x00000001) Ö DAC_CR_BOFF1 ((uint32_t)0x00000002) × DAC_CR_TEN1 ((uint32_t)0x00000004) Ù DAC_CR_TSEL1 ((uint32_t)0x00000038) Ú DAC_CR_TSEL1_0 ((uint32_t)0x00000008) Û DAC_CR_TSEL1_1 ((uint32_t)0x00000010) Ü DAC_CR_TSEL1_2 ((uint32_t)0x00000020) Þ DAC_CR_WAVE1 ((uint32_t)0x000000C0) ß DAC_CR_WAVE1_0 ((uint32_t)0x00000040) à DAC_CR_WAVE1_1 ((uint32_t)0x00000080) â DAC_CR_MAMP1 ((uint32_t)0x00000F00) ã DAC_CR_MAMP1_0 ((uint32_t)0x00000100) ä DAC_CR_MAMP1_1 ((uint32_t)0x00000200) å DAC_CR_MAMP1_2 ((uint32_t)0x00000400) æ DAC_CR_MAMP1_3 ((uint32_t)0x00000800) è DAC_CR_DMAEN1 ((uint32_t)0x00001000) é DAC_CR_EN2 ((uint32_t)0x00010000) ê DAC_CR_BOFF2 ((uint32_t)0x00020000) ë DAC_CR_TEN2 ((uint32_t)0x00040000) í DAC_CR_TSEL2 ((uint32_t)0x00380000) î DAC_CR_TSEL2_0 ((uint32_t)0x00080000) ï DAC_CR_TSEL2_1 ((uint32_t)0x00100000) ð DAC_CR_TSEL2_2 ((uint32_t)0x00200000) ò DAC_CR_WAVE2 ((uint32_t)0x00C00000) ó DAC_CR_WAVE2_0 ((uint32_t)0x00400000) ô DAC_CR_WAVE2_1 ((uint32_t)0x00800000) ö DAC_CR_MAMP2 ((uint32_t)0x0F000000) ÷ DAC_CR_MAMP2_0 ((uint32_t)0x01000000) ø DAC_CR_MAMP2_1 ((uint32_t)0x02000000) ù DAC_CR_MAMP2_2 ((uint32_t)0x04000000) ú DAC_CR_MAMP2_3 ((uint32_t)0x08000000) ü DAC_CR_DMAEN2 ((uint32_t)0x10000000) ÿ DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) ¡ DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) ¤ DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) § DAC_SR_DMAUDR1 ((uint32_t)0x00002000) ¨ DAC_SR_DMAUDR2 ((uint32_t)0x20000000) ° CEC_CFGR_PE ((uint16_t)0x0001) ± CEC_CFGR_IE ((uint16_t)0x0002) ² CEC_CFGR_BTEM ((uint16_t)0x0004) ³ CEC_CFGR_BPEM ((uint16_t)0x0008) ¶ CEC_OAR_OA ((uint16_t)0x000F) · CEC_OAR_OA_0 ((uint16_t)0x0001) ¸ CEC_OAR_OA_1 ((uint16_t)0x0002) ¹ CEC_OAR_OA_2 ((uint16_t)0x0004) º CEC_OAR_OA_3 ((uint16_t)0x0008) ½ CEC_PRES_PRES ((uint16_t)0x3FFF) À CEC_ESR_BTE ((uint16_t)0x0001) Á CEC_ESR_BPE ((uint16_t)0x0002) Â CEC_ESR_RBTFE ((uint16_t)0x0004) Ã CEC_ESR_SBE ((uint16_t)0x0008) Ä CEC_ESR_ACKE ((uint16_t)0x0010) Å CEC_ESR_LINE ((uint16_t)0x0020) Æ CEC_ESR_TBTFE ((uint16_t)0x0040) É CEC_CSR_TSOM ((uint16_t)0x0001) Ê CEC_CSR_TEOM ((uint16_t)0x0002) Ë CEC_CSR_TERR ((uint16_t)0x0004) Ì CEC_CSR_TBTRF ((uint16_t)0x0008) Í CEC_CSR_RSOM ((uint16_t)0x0010) Î CEC_CSR_REOM ((uint16_t)0x0020) Ï CEC_CSR_RERR ((uint16_t)0x0040) Ð CEC_CSR_RBTF ((uint16_t)0x0080) Ó CEC_TXD_TXD ((uint16_t)0x00FF) Ö CEC_RXD_RXD ((uint16_t)0x00FF) ß TIM_CR1_CEN ((uint16_t)0x0001) à TIM_CR1_UDIS ((uint16_t)0x0002) á TIM_CR1_URS ((uint16_t)0x0004) â TIM_CR1_OPM ((uint16_t)0x0008) ã TIM_CR1_DIR ((uint16_t)0x0010) å TIM_CR1_CMS ((uint16_t)0x0060) æ TIM_CR1_CMS_0 ((uint16_t)0x0020) ç TIM_CR1_CMS_1 ((uint16_t)0x0040) é TIM_CR1_ARPE ((uint16_t)0x0080) ë TIM_CR1_CKD ((uint16_t)0x0300) ì TIM_CR1_CKD_0 ((uint16_t)0x0100) í TIM_CR1_CKD_1 ((uint16_t)0x0200) ð TIM_CR2_CCPC ((uint16_t)0x0001) ñ TIM_CR2_CCUS ((uint16_t)0x0004) ò TIM_CR2_CCDS ((uint16_t)0x0008) ô TIM_CR2_MMS ((uint16_t)0x0070) õ TIM_CR2_MMS_0 ((uint16_t)0x0010) ö TIM_CR2_MMS_1 ((uint16_t)0x0020) ÷ TIM_CR2_MMS_2 ((uint16_t)0x0040) ù TIM_CR2_TI1S ((uint16_t)0x0080) ú TIM_CR2_OIS1 ((uint16_t)0x0100) û TIM_CR2_OIS1N ((uint16_t)0x0200) ü TIM_CR2_OIS2 ((uint16_t)0x0400) ý TIM_CR2_OIS2N ((uint16_t)0x0800) þ TIM_CR2_OIS3 ((uint16_t)0x1000) ÿ TIM_CR2_OIS3N ((uint16_t)0x2000) !TIM_CR2_OIS4 ((uint16_t)0x4000) !TIM_SMCR_SMS ((uint16_t)0x0007) !TIM_SMCR_SMS_0 ((uint16_t)0x0001)
!TIM_SMCR_SMS_1 ((uint16_t)0x0002) !TIM_SMCR_SMS_2 ((uint16_t)0x0004) !TIM_SMCR_TS ((uint16_t)0x0070) !TIM_SMCR_TS_0 ((uint16_t)0x0010) !TIM_SMCR_TS_1 ((uint16_t)0x0020) !TIM_SMCR_TS_2 ((uint16_t)0x0040) !TIM_SMCR_MSM ((uint16_t)0x0080) !TIM_SMCR_ETF ((uint16_t)0x0F00) !TIM_SMCR_ETF_0 ((uint16_t)0x0100) !TIM_SMCR_ETF_1 ((uint16_t)0x0200) !TIM_SMCR_ETF_2 ((uint16_t)0x0400) !TIM_SMCR_ETF_3 ((uint16_t)0x0800) !TIM_SMCR_ETPS ((uint16_t)0x3000) !TIM_SMCR_ETPS_0 ((uint16_t)0x1000) !TIM_SMCR_ETPS_1 ((uint16_t)0x2000) !TIM_SMCR_ECE ((uint16_t)0x4000) !TIM_SMCR_ETP ((uint16_t)0x8000) !TIM_DIER_UIE ((uint16_t)0x0001) !TIM_DIER_CC1IE ((uint16_t)0x0002) !TIM_DIER_CC2IE ((uint16_t)0x0004) !TIM_DIER_CC3IE ((uint16_t)0x0008) ¡!TIM_DIER_CC4IE ((uint16_t)0x0010) ¢!TIM_DIER_COMIE ((uint16_t)0x0020) £!TIM_DIER_TIE ((uint16_t)0x0040) ¤!TIM_DIER_BIE ((uint16_t)0x0080) ¥!TIM_DIER_UDE ((uint16_t)0x0100) ¦!TIM_DIER_CC1DE ((uint16_t)0x0200) §!TIM_DIER_CC2DE ((uint16_t)0x0400) ¨!TIM_DIER_CC3DE ((uint16_t)0x0800) ©!TIM_DIER_CC4DE ((uint16_t)0x1000) ª!TIM_DIER_COMDE ((uint16_t)0x2000) «!TIM_DIER_TDE ((uint16_t)0x4000) ®!TIM_SR_UIF ((uint16_t)0x0001) ¯!TIM_SR_CC1IF ((uint16_t)0x0002) °!TIM_SR_CC2IF ((uint16_t)0x0004) ±!TIM_SR_CC3IF ((uint16_t)0x0008) ²!TIM_SR_CC4IF ((uint16_t)0x0010) ³!TIM_SR_COMIF ((uint16_t)0x0020) ´!TIM_SR_TIF ((uint16_t)0x0040) µ!TIM_SR_BIF ((uint16_t)0x0080) ¶!TIM_SR_CC1OF ((uint16_t)0x0200) ·!TIM_SR_CC2OF ((uint16_t)0x0400) ¸!TIM_SR_CC3OF ((uint16_t)0x0800) ¹!TIM_SR_CC4OF ((uint16_t)0x1000) ¼!TIM_EGR_UG ((uint8_t)0x01) ½!TIM_EGR_CC1G ((uint8_t)0x02) ¾!TIM_EGR_CC2G ((uint8_t)0x04) ¿!TIM_EGR_CC3G ((uint8_t)0x08) À!TIM_EGR_CC4G ((uint8_t)0x10) Á!TIM_EGR_COMG ((uint8_t)0x20) Â!TIM_EGR_TG ((uint8_t)0x40) Ã!TIM_EGR_BG ((uint8_t)0x80) Æ!TIM_CCMR1_CC1S ((uint16_t)0x0003) Ç!TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) È!TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) Ê!TIM_CCMR1_OC1FE ((uint16_t)0x0004) Ë!TIM_CCMR1_OC1PE ((uint16_t)0x0008) Í!TIM_CCMR1_OC1M ((uint16_t)0x0070) Î!TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) Ï!TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) Ð!TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) Ò!TIM_CCMR1_OC1CE ((uint16_t)0x0080) Ô!TIM_CCMR1_CC2S ((uint16_t)0x0300) Õ!TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) Ö!TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) Ø!TIM_CCMR1_OC2FE ((uint16_t)0x0400) Ù!TIM_CCMR1_OC2PE ((uint16_t)0x0800) Û!TIM_CCMR1_OC2M ((uint16_t)0x7000) Ü!TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) Ý!TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) Þ!TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) à!TIM_CCMR1_OC2CE ((uint16_t)0x8000) ä!TIM_CCMR1_IC1PSC ((uint16_t)0x000C) å!TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) æ!TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) è!TIM_CCMR1_IC1F ((uint16_t)0x00F0) é!TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) ê!TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) ë!TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) ì!TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) î!TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) ï!TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) ð!TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) ò!TIM_CCMR1_IC2F ((uint16_t)0xF000) ó!TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) ô!TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) õ!TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) ö!TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) ù!TIM_CCMR2_CC3S ((uint16_t)0x0003) ú!TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) û!TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) ý!TIM_CCMR2_OC3FE ((uint16_t)0x0004) þ!TIM_CCMR2_OC3PE ((uint16_t)0x0008) "TIM_CCMR2_OC3M ((uint16_t)0x0070) "TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) "TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) "TIM_CCMR2_OC3M_2 ((uint16_t)0x0040)
"TIM_CCMR2_OC3CE ((uint16_t)0x0080) "TIM_CCMR2_CC4S ((uint16_t)0x0300) "TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) "TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) "TIM_CCMR2_OC4FE ((uint16_t)0x0400) "TIM_CCMR2_OC4PE ((uint16_t)0x0800) "TIM_CCMR2_OC4M ((uint16_t)0x7000) "TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) "TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) "TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) "TIM_CCMR2_OC4CE ((uint16_t)0x8000) "TIM_CCMR2_IC3PSC ((uint16_t)0x000C) "TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) "TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) "TIM_CCMR2_IC3F ((uint16_t)0x00F0) "TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) "TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) "TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) "TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) ¡"TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) ¢"TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) £"TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) ¥"TIM_CCMR2_IC4F ((uint16_t)0xF000) ¦"TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) §"TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) ¨"TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) ©"TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) ¬"TIM_CCER_CC1E ((uint16_t)0x0001) "TIM_CCER_CC1P ((uint16_t)0x0002) ®"TIM_CCER_CC1NE ((uint16_t)0x0004) ¯"TIM_CCER_CC1NP ((uint16_t)0x0008) °"TIM_CCER_CC2E ((uint16_t)0x0010) ±"TIM_CCER_CC2P ((uint16_t)0x0020) ²"TIM_CCER_CC2NE ((uint16_t)0x0040) ³"TIM_CCER_CC2NP ((uint16_t)0x0080) ´"TIM_CCER_CC3E ((uint16_t)0x0100) µ"TIM_CCER_CC3P ((uint16_t)0x0200) ¶"TIM_CCER_CC3NE ((uint16_t)0x0400) ·"TIM_CCER_CC3NP ((uint16_t)0x0800) ¸"TIM_CCER_CC4E ((uint16_t)0x1000) ¹"TIM_CCER_CC4P ((uint16_t)0x2000) º"TIM_CCER_CC4NP ((uint16_t)0x8000) ½"TIM_CNT_CNT ((uint16_t)0xFFFF) À"TIM_PSC_PSC ((uint16_t)0xFFFF) Ã"TIM_ARR_ARR ((uint16_t)0xFFFF) Æ"TIM_RCR_REP ((uint8_t)0xFF) É"TIM_CCR1_CCR1 ((uint16_t)0xFFFF) Ì"TIM_CCR2_CCR2 ((uint16_t)0xFFFF) Ï"TIM_CCR3_CCR3 ((uint16_t)0xFFFF) Ò"TIM_CCR4_CCR4 ((uint16_t)0xFFFF) Õ"TIM_BDTR_DTG ((uint16_t)0x00FF) Ö"TIM_BDTR_DTG_0 ((uint16_t)0x0001) ×"TIM_BDTR_DTG_1 ((uint16_t)0x0002) Ø"TIM_BDTR_DTG_2 ((uint16_t)0x0004) Ù"TIM_BDTR_DTG_3 ((uint16_t)0x0008) Ú"TIM_BDTR_DTG_4 ((uint16_t)0x0010) Û"TIM_BDTR_DTG_5 ((uint16_t)0x0020) Ü"TIM_BDTR_DTG_6 ((uint16_t)0x0040) Ý"TIM_BDTR_DTG_7 ((uint16_t)0x0080) ß"TIM_BDTR_LOCK ((uint16_t)0x0300) à"TIM_BDTR_LOCK_0 ((uint16_t)0x0100) á"TIM_BDTR_LOCK_1 ((uint16_t)0x0200) ã"TIM_BDTR_OSSI ((uint16_t)0x0400) ä"TIM_BDTR_OSSR ((uint16_t)0x0800) å"TIM_BDTR_BKE ((uint16_t)0x1000) æ"TIM_BDTR_BKP ((uint16_t)0x2000) ç"TIM_BDTR_AOE ((uint16_t)0x4000) è"TIM_BDTR_MOE ((uint16_t)0x8000) ë"TIM_DCR_DBA ((uint16_t)0x001F) ì"TIM_DCR_DBA_0 ((uint16_t)0x0001) í"TIM_DCR_DBA_1 ((uint16_t)0x0002) î"TIM_DCR_DBA_2 ((uint16_t)0x0004) ï"TIM_DCR_DBA_3 ((uint16_t)0x0008) ð"TIM_DCR_DBA_4 ((uint16_t)0x0010) ò"TIM_DCR_DBL ((uint16_t)0x1F00) ó"TIM_DCR_DBL_0 ((uint16_t)0x0100) ô"TIM_DCR_DBL_1 ((uint16_t)0x0200) õ"TIM_DCR_DBL_2 ((uint16_t)0x0400) ö"TIM_DCR_DBL_3 ((uint16_t)0x0800) ÷"TIM_DCR_DBL_4 ((uint16_t)0x1000) ú"TIM_DMAR_DMAB ((uint16_t)0xFFFF) #RTC_CRH_SECIE ((uint8_t)0x01) #RTC_CRH_ALRIE ((uint8_t)0x02)
#RTC_CRH_OWIE ((uint8_t)0x04) #RTC_CRL_SECF ((uint8_t)0x01) #RTC_CRL_ALRF ((uint8_t)0x02) #RTC_CRL_OWF ((uint8_t)0x04) #RTC_CRL_RSF ((uint8_t)0x08) #RTC_CRL_CNF ((uint8_t)0x10) #RTC_CRL_RTOFF ((uint8_t)0x20) #RTC_PRLH_PRL ((uint16_t)0x000F) #RTC_PRLL_PRL ((uint16_t)0xFFFF) #RTC_DIVH_RTC_DIV ((uint16_t)0x000F) #RTC_DIVL_RTC_DIV ((uint16_t)0xFFFF) #RTC_CNTH_RTC_CNT ((uint16_t)0xFFFF) #RTC_CNTL_RTC_CNT ((uint16_t)0xFFFF) ¢#RTC_ALRH_RTC_ALR ((uint16_t)0xFFFF) ¥#RTC_ALRL_RTC_ALR ((uint16_t)0xFFFF) ®#IWDG_KR_KEY ((uint16_t)0xFFFF) ±#IWDG_PR_PR ((uint8_t)0x07) ²#IWDG_PR_PR_0 ((uint8_t)0x01) ³#IWDG_PR_PR_1 ((uint8_t)0x02) ´#IWDG_PR_PR_2 ((uint8_t)0x04) ·#IWDG_RLR_RL ((uint16_t)0x0FFF) º#IWDG_SR_PVU ((uint8_t)0x01) »#IWDG_SR_RVU ((uint8_t)0x02) Ä#WWDG_CR_T ((uint8_t)0x7F) Å#WWDG_CR_T0 ((uint8_t)0x01) Æ#WWDG_CR_T1 ((uint8_t)0x02) Ç#WWDG_CR_T2 ((uint8_t)0x04) È#WWDG_CR_T3 ((uint8_t)0x08) É#WWDG_CR_T4 ((uint8_t)0x10) Ê#WWDG_CR_T5 ((uint8_t)0x20) Ë#WWDG_CR_T6 ((uint8_t)0x40) Í#WWDG_CR_WDGA ((uint8_t)0x80) Ð#WWDG_CFR_W ((uint16_t)0x007F) Ñ#WWDG_CFR_W0 ((uint16_t)0x0001) Ò#WWDG_CFR_W1 ((uint16_t)0x0002) Ó#WWDG_CFR_W2 ((uint16_t)0x0004) Ô#WWDG_CFR_W3 ((uint16_t)0x0008) Õ#WWDG_CFR_W4 ((uint16_t)0x0010) Ö#WWDG_CFR_W5 ((uint16_t)0x0020) ×#WWDG_CFR_W6 ((uint16_t)0x0040) Ù#WWDG_CFR_WDGTB ((uint16_t)0x0180) Ú#WWDG_CFR_WDGTB0 ((uint16_t)0x0080) Û#WWDG_CFR_WDGTB1 ((uint16_t)0x0100) Ý#WWDG_CFR_EWI ((uint16_t)0x0200) à#WWDG_SR_EWIF ((uint8_t)0x01) é#FSMC_BCR1_MBKEN ((uint32_t)0x00000001) ê#FSMC_BCR1_MUXEN ((uint32_t)0x00000002) ì#FSMC_BCR1_MTYP ((uint32_t)0x0000000C) í#FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) î#FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) ð#FSMC_BCR1_MWID ((uint32_t)0x00000030) ñ#FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) ò#FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) ô#FSMC_BCR1_FACCEN ((uint32_t)0x00000040) õ#FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) ö#FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) ÷#FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) ø#FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) ù#FSMC_BCR1_WREN ((uint32_t)0x00001000) ú#FSMC_BCR1_WAITEN ((uint32_t)0x00002000) û#FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) ü#FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) ý#FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) $FSMC_BCR2_MBKEN ((uint32_t)0x00000001) $FSMC_BCR2_MUXEN ((uint32_t)0x00000002) $FSMC_BCR2_MTYP ((uint32_t)0x0000000C) $FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004)
$FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) $FSMC_BCR2_MWID ((uint32_t)0x00000030) $FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) $FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) $FSMC_BCR2_FACCEN ((uint32_t)0x00000040) $FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) $FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) $FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) $FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) $FSMC_BCR2_WREN ((uint32_t)0x00001000) $FSMC_BCR2_WAITEN ((uint32_t)0x00002000) $FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) $FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) $FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) $FSMC_BCR3_MBKEN ((uint32_t)0x00000001) $FSMC_BCR3_MUXEN ((uint32_t)0x00000002) $FSMC_BCR3_MTYP ((uint32_t)0x0000000C) $FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) $FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) $FSMC_BCR3_MWID ((uint32_t)0x00000030) $FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) $FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) ¢$FSMC_BCR3_FACCEN ((uint32_t)0x00000040) £$FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) ¤$FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) ¥$FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) ¦$FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) §$FSMC_BCR3_WREN ((uint32_t)0x00001000) ¨$FSMC_BCR3_WAITEN ((uint32_t)0x00002000) ©$FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) ª$FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) «$FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) ®$FSMC_BCR4_MBKEN ((uint32_t)0x00000001) ¯$FSMC_BCR4_MUXEN ((uint32_t)0x00000002) ±$FSMC_BCR4_MTYP ((uint32_t)0x0000000C) ²$FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) ³$FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) µ$FSMC_BCR4_MWID ((uint32_t)0x00000030) ¶$FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) ·$FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) ¹$FSMC_BCR4_FACCEN ((uint32_t)0x00000040) º$FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) »$FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) ¼$FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) ½$FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) ¾$FSMC_BCR4_WREN ((uint32_t)0x00001000) ¿$FSMC_BCR4_WAITEN ((uint32_t)0x00002000) À$FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) Á$FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) Â$FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) Å$FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) Æ$FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) Ç$FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) È$FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) É$FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) Ë$FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) Ì$FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) Í$FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) Î$FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) Ï$FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) Ñ$FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) Ò$FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) Ó$FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) Ô$FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) Õ$FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) ×$FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) Ø$FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) Ù$FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) Ú$FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) Û$FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) Ý$FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) Þ$FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) ß$FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) à$FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) á$FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) ã$FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) ä$FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) å$FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) æ$FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) ç$FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) é$FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) ê$FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) ë$FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) î$FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) ï$FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) ð$FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) ñ$FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) ò$FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) ô$FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) õ$FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) ö$FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) ÷$FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) ø$FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) ú$FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) û$FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) ü$FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) ý$FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) þ$FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) %FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) %FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) %FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) %FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) %FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) %FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) %FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) %FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) %FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) %FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) %FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) %FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) %FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) %FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) %FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) %FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) %FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) %FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) %FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) %FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) %FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) %FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) %FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) %FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) %FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) %FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) %FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) ¡%FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) £%FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) ¤%FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) ¥%FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) ¦%FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) §%FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) ©%FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) ª%FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) «%FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) ¬%FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) %FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) ¯%FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) °%FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) ±%FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) ²%FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) ³%FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) µ%FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) ¶%FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) ·%FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) ¸%FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) ¹%FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) »%FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) ¼%FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) ½%FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) À%FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) Á%FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) Â%FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) Ã%FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) Ä%FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) Æ%FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) Ç%FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) È%FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) É%FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) Ê%FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) Ì%FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) Í%FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) Î%FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) Ï%FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) Ð%FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) Ò%FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) Ó%FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) Ô%FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) Õ%FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) Ö%FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) Ø%FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) Ù%FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) Ú%FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) Û%FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) Ü%FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) Þ%FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) ß%FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) à%FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) á%FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) â%FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) ä%FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) å%FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) æ%FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) é%FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) ê%FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) ë%FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) ì%FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) í%FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) ï%FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) ð%FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) ñ%FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) ò%FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) ó%FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) õ%FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) ö%FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) ÷%FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) ø%FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) ù%FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) û%FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) ü%FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) ý%FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) þ%FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) ÿ%FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) &FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) &FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) &FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) &FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000)
&FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) &FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) &FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) &FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) &FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) &FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) &FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) &FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) &FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) &FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) &FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) &FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) &FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) &FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) &FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) &FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) &FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) &FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) &FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) &FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) &FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) &FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) ¡&FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) ¢&FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) ¤&FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) ¥&FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) ¦&FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) §&FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) ¨&FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) ª&FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) «&FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) ¬&FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) ¯&FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) °&FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) ±&FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) ²&FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) ³&FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) µ&FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) ¶&FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) ·&FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) ¸&FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) ¹&FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) »&FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) ¼&FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) ½&FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) ¾&FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) ¿&FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) Á&FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) Â&FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) Ã&FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) Ä&FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) Å&FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) Ç&FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) È&FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) É&FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) Ê&FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) Ë&FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) Í&FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) Î&FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) Ï&FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) Ò&FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) Ó&FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) Ô&FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) Õ&FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) Ö&FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) Ø&FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) Ù&FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) Ú&FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) Û&FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) Ü&FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) Þ&FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) ß&FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) à&FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) á&FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) â&FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) ä&FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) å&FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) æ&FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) ç&FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) è&FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) ê&FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) ë&FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) ì&FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) í&FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) î&FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) ð&FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) ñ&FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) ò&FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) õ&FSMC_PCR2_PWAITEN ((uint32_t)0x00000002) ö&FSMC_PCR2_PBKEN ((uint32_t)0x00000004) ÷&FSMC_PCR2_PTYP ((uint32_t)0x00000008) ù&FSMC_PCR2_PWID ((uint32_t)0x00000030) ú&FSMC_PCR2_PWID_0 ((uint32_t)0x00000010) û&FSMC_PCR2_PWID_1 ((uint32_t)0x00000020) ý&FSMC_PCR2_ECCEN ((uint32_t)0x00000040) ÿ&FSMC_PCR2_TCLR ((uint32_t)0x00001E00) 'FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200) 'FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400) 'FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800) 'FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000)
'FSMC_PCR2_TAR ((uint32_t)0x0001E000) 'FSMC_PCR2_TAR_0 ((uint32_t)0x00002000) 'FSMC_PCR2_TAR_1 ((uint32_t)0x00004000) 'FSMC_PCR2_TAR_2 ((uint32_t)0x00008000) 'FSMC_PCR2_TAR_3 ((uint32_t)0x00010000) 'FSMC_PCR2_ECCPS ((uint32_t)0x000E0000) 'FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) 'FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) 'FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) 'FSMC_PCR3_PWAITEN ((uint32_t)0x00000002) 'FSMC_PCR3_PBKEN ((uint32_t)0x00000004) 'FSMC_PCR3_PTYP ((uint32_t)0x00000008) 'FSMC_PCR3_PWID ((uint32_t)0x00000030) 'FSMC_PCR3_PWID_0 ((uint32_t)0x00000010) 'FSMC_PCR3_PWID_1 ((uint32_t)0x00000020) 'FSMC_PCR3_ECCEN ((uint32_t)0x00000040) 'FSMC_PCR3_TCLR ((uint32_t)0x00001E00) 'FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200) 'FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400) 'FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800) 'FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000) ¡'FSMC_PCR3_TAR ((uint32_t)0x0001E000) ¢'FSMC_PCR3_TAR_0 ((uint32_t)0x00002000) £'FSMC_PCR3_TAR_1 ((uint32_t)0x00004000) ¤'FSMC_PCR3_TAR_2 ((uint32_t)0x00008000) ¥'FSMC_PCR3_TAR_3 ((uint32_t)0x00010000) §'FSMC_PCR3_ECCPS ((uint32_t)0x000E0000) ¨'FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) ©'FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) ª'FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) 'FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) ®'FSMC_PCR4_PBKEN ((uint32_t)0x00000004) ¯'FSMC_PCR4_PTYP ((uint32_t)0x00000008) ±'FSMC_PCR4_PWID ((uint32_t)0x00000030) ²'FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) ³'FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) µ'FSMC_PCR4_ECCEN ((uint32_t)0x00000040) ·'FSMC_PCR4_TCLR ((uint32_t)0x00001E00) ¸'FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) ¹'FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) º'FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) »'FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) ½'FSMC_PCR4_TAR ((uint32_t)0x0001E000) ¾'FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) ¿'FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) À'FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) Á'FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) Ã'FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) Ä'FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) Å'FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) Æ'FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) É'FSMC_SR2_IRS ((uint8_t)0x01) Ê'FSMC_SR2_ILS ((uint8_t)0x02) Ë'FSMC_SR2_IFS ((uint8_t)0x04) Ì'FSMC_SR2_IREN ((uint8_t)0x08) Í'FSMC_SR2_ILEN ((uint8_t)0x10) Î'FSMC_SR2_IFEN ((uint8_t)0x20) Ï'FSMC_SR2_FEMPT ((uint8_t)0x40) Ò'FSMC_SR3_IRS ((uint8_t)0x01) Ó'FSMC_SR3_ILS ((uint8_t)0x02) Ô'FSMC_SR3_IFS ((uint8_t)0x04) Õ'FSMC_SR3_IREN ((uint8_t)0x08) Ö'FSMC_SR3_ILEN ((uint8_t)0x10) ×'FSMC_SR3_IFEN ((uint8_t)0x20) Ø'FSMC_SR3_FEMPT ((uint8_t)0x40) Û'FSMC_SR4_IRS ((uint8_t)0x01) Ü'FSMC_SR4_ILS ((uint8_t)0x02) Ý'FSMC_SR4_IFS ((uint8_t)0x04) Þ'FSMC_SR4_IREN ((uint8_t)0x08) ß'FSMC_SR4_ILEN ((uint8_t)0x10) à'FSMC_SR4_IFEN ((uint8_t)0x20) á'FSMC_SR4_FEMPT ((uint8_t)0x40) ä'FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) å'FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) æ'FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) ç'FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) è'FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) é'FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) ê'FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) ë'FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) ì'FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) î'FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) ï'FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) ð'FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) ñ'FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) ò'FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) ó'FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) ô'FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) õ'FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) ö'FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) ø'FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) ù'FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) ú'FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) û'FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) ü'FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) ý'FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) þ'FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) ÿ'FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) (FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) (FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) (FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) (FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000)
(FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) (FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) (FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) (FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) (FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) (FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) (FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) (FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) (FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) (FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) (FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) (FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) (FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) (FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) (FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) (FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) (FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) (FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) (FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) (FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) (FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) (FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) (FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) (FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) ¡(FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) ¢(FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) £(FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) ¤(FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) ¥(FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) ¦(FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) §(FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) ¨(FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) ©(FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) «(FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) ¬(FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) (FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) ®(FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) ¯(FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) °(FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) ±(FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) ²(FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) ³(FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) ¶(FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) ·(FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) ¸(FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) ¹(FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) º(FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) »(FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) ¼(FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) ½(FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) ¾(FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) À(FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) Á(FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) Â(FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) Ã(FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) Ä(FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) Å(FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) Æ(FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) Ç(FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) È(FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) Ê(FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) Ë(FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) Ì(FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) Í(FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) Î(FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) Ï(FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) Ð(FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) Ñ(FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) Ò(FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) Ô(FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) Õ(FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) Ö(FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) ×(FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) Ø(FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) Ù(FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) Ú(FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) Û(FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) Ü(FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) ß(FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) à(FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) á(FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) â(FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) ã(FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) ä(FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) å(FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) æ(FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) ç(FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) é(FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) ê(FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) ë(FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) ì(FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) í(FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) î(FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) ï(FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) ð(FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) ñ(FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) ó(FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) ô(FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) õ(FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) ö(FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) ÷(FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) ø(FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) ù(FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) ú(FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) û(FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) ý(FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) þ(FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) ÿ(FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) )FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) )FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) )FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) )FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) )FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000)
)FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) )FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) )FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) )FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) )FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) )FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) )FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) )FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) )FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) )FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) )FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) )FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) )FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) )FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) )FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) )FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) )FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) )FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) )FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) )FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) )FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) )FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) )FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) )FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) ¡)FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) ¢)FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) £)FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) ¤)FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) ¦)FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) §)FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) ¨)FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) ©)FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) ª)FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) «)FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) ¬)FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) )FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) ®)FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) ±)FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) ²)FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) ³)FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) ´)FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) µ)FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) ¶)FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) ·)FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) ¸)FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) ¹)FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) »)FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) ¼)FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) ½)FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) ¾)FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) ¿)FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) À)FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) Á)FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) Â)FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) Ã)FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) Å)FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) Æ)FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) Ç)FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) È)FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) É)FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) Ê)FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) Ë)FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) Ì)FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) Í)FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) Ï)FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) Ð)FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) Ñ)FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) Ò)FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) Ó)FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) Ô)FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) Õ)FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) Ö)FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) ×)FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) Ú)FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) Û)FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) Ü)FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) Ý)FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) Þ)FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) ß)FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) à)FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) á)FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) â)FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) ä)FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) å)FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) æ)FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) ç)FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) è)FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) é)FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) ê)FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) ë)FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) ì)FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) î)FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) ï)FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) ð)FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) ñ)FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) ò)FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) ó)FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) ô)FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) õ)FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) ö)FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) ø)FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) ù)FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) ú)FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) û)FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) ü)FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) ý)FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) þ)FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) ÿ)FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) *FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) *FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) *FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) *SDIO_POWER_PWRCTRL ((uint8_t)0x03) *SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01) *SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02) *SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF) *SDIO_CLKCR_CLKEN ((uint16_t)0x0100) *SDIO_CLKCR_PWRSAV ((uint16_t)0x0200) *SDIO_CLKCR_BYPASS ((uint16_t)0x0400) *SDIO_CLKCR_WIDBUS ((uint16_t)0x1800) *SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800) *SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000) *SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000) *SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000) ¡*SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) ¤*SDIO_CMD_CMDINDEX ((uint16_t)0x003F) ¦*SDIO_CMD_WAITRESP ((uint16_t)0x00C0) §*SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) ¨*SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) ª*SDIO_CMD_WAITINT ((uint16_t)0x0100) «*SDIO_CMD_WAITPEND ((uint16_t)0x0200) ¬*SDIO_CMD_CPSMEN ((uint16_t)0x0400) *SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800) ®*SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000) ¯*SDIO_CMD_NIEN ((uint16_t)0x2000) °*SDIO_CMD_CEATACMD ((uint16_t)0x4000) ³*SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) ¶*SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) ¹*SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) ¼*SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) ¿*SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) Â*SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) Å*SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) È*SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) Ë*SDIO_DCTRL_DTEN ((uint16_t)0x0001) Ì*SDIO_DCTRL_DTDIR ((uint16_t)0x0002) Í*SDIO_DCTRL_DTMODE ((uint16_t)0x0004) Î*SDIO_DCTRL_DMAEN ((uint16_t)0x0008) Ð*SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) Ñ*SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) Ò*SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) Ó*SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) Ô*SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) Ö*SDIO_DCTRL_RWSTART ((uint16_t)0x0100) ×*SDIO_DCTRL_RWSTOP ((uint16_t)0x0200) Ø*SDIO_DCTRL_RWMOD ((uint16_t)0x0400) Ù*SDIO_DCTRL_SDIOEN ((uint16_t)0x0800) Ü*SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) ß*SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) à*SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) á*SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) â*SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) ã*SDIO_STA_TXUNDERR ((uint32_t)0x00000010) ä*SDIO_STA_RXOVERR ((uint32_t)0x00000020) å*SDIO_STA_CMDREND ((uint32_t)0x00000040) æ*SDIO_STA_CMDSENT ((uint32_t)0x00000080) ç*SDIO_STA_DATAEND ((uint32_t)0x00000100) è*SDIO_STA_STBITERR ((uint32_t)0x00000200) é*SDIO_STA_DBCKEND ((uint32_t)0x00000400) ê*SDIO_STA_CMDACT ((uint32_t)0x00000800) ë*SDIO_STA_TXACT ((uint32_t)0x00001000) ì*SDIO_STA_RXACT ((uint32_t)0x00002000) í*SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) î*SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) ï*SDIO_STA_TXFIFOF ((uint32_t)0x00010000) ð*SDIO_STA_RXFIFOF ((uint32_t)0x00020000) ñ*SDIO_STA_TXFIFOE ((uint32_t)0x00040000) ò*SDIO_STA_RXFIFOE ((uint32_t)0x00080000) ó*SDIO_STA_TXDAVL ((uint32_t)0x00100000) ô*SDIO_STA_RXDAVL ((uint32_t)0x00200000) õ*SDIO_STA_SDIOIT ((uint32_t)0x00400000) ö*SDIO_STA_CEATAEND ((uint32_t)0x00800000) ù*SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) ú*SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) û*SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) ü*SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) ý*SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) þ*SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) ÿ*SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) +SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) +SDIO_ICR_DATAENDC ((uint32_t)0x00000100) +SDIO_ICR_STBITERRC ((uint32_t)0x00000200) +SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) +SDIO_ICR_SDIOITC ((uint32_t)0x00400000)
+SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) +SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) +SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) +SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) +SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) +SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) +SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) +SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) +SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) +SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) +SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) +SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) +SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) +SDIO_MASK_TXACTIE ((uint32_t)0x00001000) +SDIO_MASK_RXACTIE ((uint32_t)0x00002000) +SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) +SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) +SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) +SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) +SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) +SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) +SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) +SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) +SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) +SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) ¢+SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) ¥+SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) ¯+USB_EP0R_EA ((uint16_t)0x000F) ±+USB_EP0R_STAT_TX ((uint16_t)0x0030) ²+USB_EP0R_STAT_TX_0 ((uint16_t)0x0010) ³+USB_EP0R_STAT_TX_1 ((uint16_t)0x0020) µ+USB_EP0R_DTOG_TX ((uint16_t)0x0040) ¶+USB_EP0R_CTR_TX ((uint16_t)0x0080) ·+USB_EP0R_EP_KIND ((uint16_t)0x0100) ¹+USB_EP0R_EP_TYPE ((uint16_t)0x0600) º+USB_EP0R_EP_TYPE_0 ((uint16_t)0x0200) »+USB_EP0R_EP_TYPE_1 ((uint16_t)0x0400) ½+USB_EP0R_SETUP ((uint16_t)0x0800) ¿+USB_EP0R_STAT_RX ((uint16_t)0x3000) À+USB_EP0R_STAT_RX_0 ((uint16_t)0x1000) Á+USB_EP0R_STAT_RX_1 ((uint16_t)0x2000) Ã+USB_EP0R_DTOG_RX ((uint16_t)0x4000) Ä+USB_EP0R_CTR_RX ((uint16_t)0x8000) Ç+USB_EP1R_EA ((uint16_t)0x000F) É+USB_EP1R_STAT_TX ((uint16_t)0x0030) Ê+USB_EP1R_STAT_TX_0 ((uint16_t)0x0010) Ë+USB_EP1R_STAT_TX_1 ((uint16_t)0x0020) Í+USB_EP1R_DTOG_TX ((uint16_t)0x0040) Î+USB_EP1R_CTR_TX ((uint16_t)0x0080) Ï+USB_EP1R_EP_KIND ((uint16_t)0x0100) Ñ+USB_EP1R_EP_TYPE ((uint16_t)0x0600) Ò+USB_EP1R_EP_TYPE_0 ((uint16_t)0x0200) Ó+USB_EP1R_EP_TYPE_1 ((uint16_t)0x0400) Õ+USB_EP1R_SETUP ((uint16_t)0x0800) ×+USB_EP1R_STAT_RX ((uint16_t)0x3000) Ø+USB_EP1R_STAT_RX_0 ((uint16_t)0x1000) Ù+USB_EP1R_STAT_RX_1 ((uint16_t)0x2000) Û+USB_EP1R_DTOG_RX ((uint16_t)0x4000) Ü+USB_EP1R_CTR_RX ((uint16_t)0x8000) ß+USB_EP2R_EA ((uint16_t)0x000F) á+USB_EP2R_STAT_TX ((uint16_t)0x0030) â+USB_EP2R_STAT_TX_0 ((uint16_t)0x0010) ã+USB_EP2R_STAT_TX_1 ((uint16_t)0x0020) å+USB_EP2R_DTOG_TX ((uint16_t)0x0040) æ+USB_EP2R_CTR_TX ((uint16_t)0x0080) ç+USB_EP2R_EP_KIND ((uint16_t)0x0100) é+USB_EP2R_EP_TYPE ((uint16_t)0x0600) ê+USB_EP2R_EP_TYPE_0 ((uint16_t)0x0200) ë+USB_EP2R_EP_TYPE_1 ((uint16_t)0x0400) í+USB_EP2R_SETUP ((uint16_t)0x0800) ï+USB_EP2R_STAT_RX ((uint16_t)0x3000) ð+USB_EP2R_STAT_RX_0 ((uint16_t)0x1000) ñ+USB_EP2R_STAT_RX_1 ((uint16_t)0x2000) ó+USB_EP2R_DTOG_RX ((uint16_t)0x4000) ô+USB_EP2R_CTR_RX ((uint16_t)0x8000) ÷+USB_EP3R_EA ((uint16_t)0x000F) ù+USB_EP3R_STAT_TX ((uint16_t)0x0030) ú+USB_EP3R_STAT_TX_0 ((uint16_t)0x0010) û+USB_EP3R_STAT_TX_1 ((uint16_t)0x0020) ý+USB_EP3R_DTOG_TX ((uint16_t)0x0040) þ+USB_EP3R_CTR_TX ((uint16_t)0x0080) ÿ+USB_EP3R_EP_KIND ((uint16_t)0x0100) ,USB_EP3R_EP_TYPE ((uint16_t)0x0600) ,USB_EP3R_EP_TYPE_0 ((uint16_t)0x0200) ,USB_EP3R_EP_TYPE_1 ((uint16_t)0x0400)
,USB_EP3R_SETUP ((uint16_t)0x0800) ,USB_EP3R_STAT_RX ((uint16_t)0x3000) ,USB_EP3R_STAT_RX_0 ((uint16_t)0x1000) ,USB_EP3R_STAT_RX_1 ((uint16_t)0x2000) ,USB_EP3R_DTOG_RX ((uint16_t)0x4000) ,USB_EP3R_CTR_RX ((uint16_t)0x8000) ,USB_EP4R_EA ((uint16_t)0x000F) ,USB_EP4R_STAT_TX ((uint16_t)0x0030) ,USB_EP4R_STAT_TX_0 ((uint16_t)0x0010) ,USB_EP4R_STAT_TX_1 ((uint16_t)0x0020) ,USB_EP4R_DTOG_TX ((uint16_t)0x0040) ,USB_EP4R_CTR_TX ((uint16_t)0x0080) ,USB_EP4R_EP_KIND ((uint16_t)0x0100) ,USB_EP4R_EP_TYPE ((uint16_t)0x0600) ,USB_EP4R_EP_TYPE_0 ((uint16_t)0x0200) ,USB_EP4R_EP_TYPE_1 ((uint16_t)0x0400) ,USB_EP4R_SETUP ((uint16_t)0x0800) ,USB_EP4R_STAT_RX ((uint16_t)0x3000) ,USB_EP4R_STAT_RX_0 ((uint16_t)0x1000) ¡,USB_EP4R_STAT_RX_1 ((uint16_t)0x2000) £,USB_EP4R_DTOG_RX ((uint16_t)0x4000) ¤,USB_EP4R_CTR_RX ((uint16_t)0x8000) §,USB_EP5R_EA ((uint16_t)0x000F) ©,USB_EP5R_STAT_TX ((uint16_t)0x0030) ª,USB_EP5R_STAT_TX_0 ((uint16_t)0x0010) «,USB_EP5R_STAT_TX_1 ((uint16_t)0x0020) ,USB_EP5R_DTOG_TX ((uint16_t)0x0040) ®,USB_EP5R_CTR_TX ((uint16_t)0x0080) ¯,USB_EP5R_EP_KIND ((uint16_t)0x0100) ±,USB_EP5R_EP_TYPE ((uint16_t)0x0600) ²,USB_EP5R_EP_TYPE_0 ((uint16_t)0x0200) ³,USB_EP5R_EP_TYPE_1 ((uint16_t)0x0400) µ,USB_EP5R_SETUP ((uint16_t)0x0800) ·,USB_EP5R_STAT_RX ((uint16_t)0x3000) ¸,USB_EP5R_STAT_RX_0 ((uint16_t)0x1000) ¹,USB_EP5R_STAT_RX_1 ((uint16_t)0x2000) »,USB_EP5R_DTOG_RX ((uint16_t)0x4000) ¼,USB_EP5R_CTR_RX ((uint16_t)0x8000) ¿,USB_EP6R_EA ((uint16_t)0x000F) Á,USB_EP6R_STAT_TX ((uint16_t)0x0030) Â,USB_EP6R_STAT_TX_0 ((uint16_t)0x0010) Ã,USB_EP6R_STAT_TX_1 ((uint16_t)0x0020) Å,USB_EP6R_DTOG_TX ((uint16_t)0x0040) Æ,USB_EP6R_CTR_TX ((uint16_t)0x0080) Ç,USB_EP6R_EP_KIND ((uint16_t)0x0100) É,USB_EP6R_EP_TYPE ((uint16_t)0x0600) Ê,USB_EP6R_EP_TYPE_0 ((uint16_t)0x0200) Ë,USB_EP6R_EP_TYPE_1 ((uint16_t)0x0400) Í,USB_EP6R_SETUP ((uint16_t)0x0800) Ï,USB_EP6R_STAT_RX ((uint16_t)0x3000) Ð,USB_EP6R_STAT_RX_0 ((uint16_t)0x1000) Ñ,USB_EP6R_STAT_RX_1 ((uint16_t)0x2000) Ó,USB_EP6R_DTOG_RX ((uint16_t)0x4000) Ô,USB_EP6R_CTR_RX ((uint16_t)0x8000) ×,USB_EP7R_EA ((uint16_t)0x000F) Ù,USB_EP7R_STAT_TX ((uint16_t)0x0030) Ú,USB_EP7R_STAT_TX_0 ((uint16_t)0x0010) Û,USB_EP7R_STAT_TX_1 ((uint16_t)0x0020) Ý,USB_EP7R_DTOG_TX ((uint16_t)0x0040) Þ,USB_EP7R_CTR_TX ((uint16_t)0x0080) ß,USB_EP7R_EP_KIND ((uint16_t)0x0100) á,USB_EP7R_EP_TYPE ((uint16_t)0x0600) â,USB_EP7R_EP_TYPE_0 ((uint16_t)0x0200) ã,USB_EP7R_EP_TYPE_1 ((uint16_t)0x0400) å,USB_EP7R_SETUP ((uint16_t)0x0800) ç,USB_EP7R_STAT_RX ((uint16_t)0x3000) è,USB_EP7R_STAT_RX_0 ((uint16_t)0x1000) é,USB_EP7R_STAT_RX_1 ((uint16_t)0x2000) ë,USB_EP7R_DTOG_RX ((uint16_t)0x4000) ì,USB_EP7R_CTR_RX ((uint16_t)0x8000) ð,USB_CNTR_FRES ((uint16_t)0x0001) ñ,USB_CNTR_PDWN ((uint16_t)0x0002) ò,USB_CNTR_LP_MODE ((uint16_t)0x0004) ó,USB_CNTR_FSUSP ((uint16_t)0x0008) ô,USB_CNTR_RESUME ((uint16_t)0x0010) õ,USB_CNTR_ESOFM ((uint16_t)0x0100) ö,USB_CNTR_SOFM ((uint16_t)0x0200) ÷,USB_CNTR_RESETM ((uint16_t)0x0400) ø,USB_CNTR_SUSPM ((uint16_t)0x0800) ù,USB_CNTR_WKUPM ((uint16_t)0x1000) ú,USB_CNTR_ERRM ((uint16_t)0x2000) û,USB_CNTR_PMAOVRM ((uint16_t)0x4000) ü,USB_CNTR_CTRM ((uint16_t)0x8000) ÿ,USB_ISTR_EP_ID ((uint16_t)0x000F) -USB_ISTR_DIR ((uint16_t)0x0010) -USB_ISTR_ESOF ((uint16_t)0x0100) -USB_ISTR_SOF ((uint16_t)0x0200) -USB_ISTR_RESET ((uint16_t)0x0400) -USB_ISTR_SUSP ((uint16_t)0x0800)
-USB_ISTR_WKUP ((uint16_t)0x1000) -USB_ISTR_ERR ((uint16_t)0x2000) -USB_ISTR_PMAOVR ((uint16_t)0x4000) -USB_ISTR_CTR ((uint16_t)0x8000) -USB_FNR_FN ((uint16_t)0x07FF) -USB_FNR_LSOF ((uint16_t)0x1800) -USB_FNR_LCK ((uint16_t)0x2000) -USB_FNR_RXDM ((uint16_t)0x4000) -USB_FNR_RXDP ((uint16_t)0x8000) -USB_DADDR_ADD ((uint8_t)0x7F) -USB_DADDR_ADD0 ((uint8_t)0x01) -USB_DADDR_ADD1 ((uint8_t)0x02) -USB_DADDR_ADD2 ((uint8_t)0x04) -USB_DADDR_ADD3 ((uint8_t)0x08) -USB_DADDR_ADD4 ((uint8_t)0x10) -USB_DADDR_ADD5 ((uint8_t)0x20) -USB_DADDR_ADD6 ((uint8_t)0x40) -USB_DADDR_EF ((uint8_t)0x80) -USB_BTABLE_BTABLE ((uint16_t)0xFFF8) ¢-USB_ADDR0_TX_ADDR0_TX ((uint16_t)0xFFFE) ¥-USB_ADDR1_TX_ADDR1_TX ((uint16_t)0xFFFE) ¨-USB_ADDR2_TX_ADDR2_TX ((uint16_t)0xFFFE) «-USB_ADDR3_TX_ADDR3_TX ((uint16_t)0xFFFE) ®-USB_ADDR4_TX_ADDR4_TX ((uint16_t)0xFFFE) ±-USB_ADDR5_TX_ADDR5_TX ((uint16_t)0xFFFE) ´-USB_ADDR6_TX_ADDR6_TX ((uint16_t)0xFFFE) ·-USB_ADDR7_TX_ADDR7_TX ((uint16_t)0xFFFE) ¼-USB_COUNT0_TX_COUNT0_TX ((uint16_t)0x03FF) ¿-USB_COUNT1_TX_COUNT1_TX ((uint16_t)0x03FF) Â-USB_COUNT2_TX_COUNT2_TX ((uint16_t)0x03FF) Å-USB_COUNT3_TX_COUNT3_TX ((uint16_t)0x03FF) È-USB_COUNT4_TX_COUNT4_TX ((uint16_t)0x03FF) Ë-USB_COUNT5_TX_COUNT5_TX ((uint16_t)0x03FF) Î-USB_COUNT6_TX_COUNT6_TX ((uint16_t)0x03FF) Ñ-USB_COUNT7_TX_COUNT7_TX ((uint16_t)0x03FF) Ö-USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) Ù-USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) Ü-USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) ß-USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) â-USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) å-USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) è-USB_COUNT3_TX_0_COUNT3_TX_0 ((uint16_t)0x000003FF) ë-USB_COUNT3_TX_1_COUNT3_TX_1 ((uint16_t)0x03FF0000) î-USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) ñ-USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) ô-USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) ÷-USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) ú-USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) ý-USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) .USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) .USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) .USB_ADDR0_RX_ADDR0_RX ((uint16_t)0xFFFE) .USB_ADDR1_RX_ADDR1_RX ((uint16_t)0xFFFE) .USB_ADDR2_RX_ADDR2_RX ((uint16_t)0xFFFE) .USB_ADDR3_RX_ADDR3_RX ((uint16_t)0xFFFE) .USB_ADDR4_RX_ADDR4_RX ((uint16_t)0xFFFE) .USB_ADDR5_RX_ADDR5_RX ((uint16_t)0xFFFE) .USB_ADDR6_RX_ADDR6_RX ((uint16_t)0xFFFE) .USB_ADDR7_RX_ADDR7_RX ((uint16_t)0xFFFE) ¢.USB_COUNT0_RX_COUNT0_RX ((uint16_t)0x03FF) ¤.USB_COUNT0_RX_NUM_BLOCK ((uint16_t)0x7C00) ¥.USB_COUNT0_RX_NUM_BLOCK_0 ((uint16_t)0x0400) ¦.USB_COUNT0_RX_NUM_BLOCK_1 ((uint16_t)0x0800) §.USB_COUNT0_RX_NUM_BLOCK_2 ((uint16_t)0x1000) ¨.USB_COUNT0_RX_NUM_BLOCK_3 ((uint16_t)0x2000) ©.USB_COUNT0_RX_NUM_BLOCK_4 ((uint16_t)0x4000) «.USB_COUNT0_RX_BLSIZE ((uint16_t)0x8000) ®.USB_COUNT1_RX_COUNT1_RX ((uint16_t)0x03FF) °.USB_COUNT1_RX_NUM_BLOCK ((uint16_t)0x7C00) ±.USB_COUNT1_RX_NUM_BLOCK_0 ((uint16_t)0x0400) ².USB_COUNT1_RX_NUM_BLOCK_1 ((uint16_t)0x0800) ³.USB_COUNT1_RX_NUM_BLOCK_2 ((uint16_t)0x1000) ´.USB_COUNT1_RX_NUM_BLOCK_3 ((uint16_t)0x2000) µ.USB_COUNT1_RX_NUM_BLOCK_4 ((uint16_t)0x4000) ·.USB_COUNT1_RX_BLSIZE ((uint16_t)0x8000) º.USB_COUNT2_RX_COUNT2_RX ((uint16_t)0x03FF) ¼.USB_COUNT2_RX_NUM_BLOCK ((uint16_t)0x7C00) ½.USB_COUNT2_RX_NUM_BLOCK_0 ((uint16_t)0x0400) ¾.USB_COUNT2_RX_NUM_BLOCK_1 ((uint16_t)0x0800) ¿.USB_COUNT2_RX_NUM_BLOCK_2 ((uint16_t)0x1000) À.USB_COUNT2_RX_NUM_BLOCK_3 ((uint16_t)0x2000) Á.USB_COUNT2_RX_NUM_BLOCK_4 ((uint16_t)0x4000) Ã.USB_COUNT2_RX_BLSIZE ((uint16_t)0x8000) Æ.USB_COUNT3_RX_COUNT3_RX ((uint16_t)0x03FF) È.USB_COUNT3_RX_NUM_BLOCK ((uint16_t)0x7C00) É.USB_COUNT3_RX_NUM_BLOCK_0 ((uint16_t)0x0400) Ê.USB_COUNT3_RX_NUM_BLOCK_1 ((uint16_t)0x0800) Ë.USB_COUNT3_RX_NUM_BLOCK_2 ((uint16_t)0x1000) Ì.USB_COUNT3_RX_NUM_BLOCK_3 ((uint16_t)0x2000) Í.USB_COUNT3_RX_NUM_BLOCK_4 ((uint16_t)0x4000) Ï.USB_COUNT3_RX_BLSIZE ((uint16_t)0x8000) Ò.USB_COUNT4_RX_COUNT4_RX ((uint16_t)0x03FF) Ô.USB_COUNT4_RX_NUM_BLOCK ((uint16_t)0x7C00) Õ.USB_COUNT4_RX_NUM_BLOCK_0 ((uint16_t)0x0400) Ö.USB_COUNT4_RX_NUM_BLOCK_1 ((uint16_t)0x0800) ×.USB_COUNT4_RX_NUM_BLOCK_2 ((uint16_t)0x1000) Ø.USB_COUNT4_RX_NUM_BLOCK_3 ((uint16_t)0x2000) Ù.USB_COUNT4_RX_NUM_BLOCK_4 ((uint16_t)0x4000) Û.USB_COUNT4_RX_BLSIZE ((uint16_t)0x8000) Þ.USB_COUNT5_RX_COUNT5_RX ((uint16_t)0x03FF) à.USB_COUNT5_RX_NUM_BLOCK ((uint16_t)0x7C00) á.USB_COUNT5_RX_NUM_BLOCK_0 ((uint16_t)0x0400) â.USB_COUNT5_RX_NUM_BLOCK_1 ((uint16_t)0x0800) ã.USB_COUNT5_RX_NUM_BLOCK_2 ((uint16_t)0x1000) ä.USB_COUNT5_RX_NUM_BLOCK_3 ((uint16_t)0x2000) å.USB_COUNT5_RX_NUM_BLOCK_4 ((uint16_t)0x4000) ç.USB_COUNT5_RX_BLSIZE ((uint16_t)0x8000) ê.USB_COUNT6_RX_COUNT6_RX ((uint16_t)0x03FF) ì.USB_COUNT6_RX_NUM_BLOCK ((uint16_t)0x7C00) í.USB_COUNT6_RX_NUM_BLOCK_0 ((uint16_t)0x0400) î.USB_COUNT6_RX_NUM_BLOCK_1 ((uint16_t)0x0800) ï.USB_COUNT6_RX_NUM_BLOCK_2 ((uint16_t)0x1000) ð.USB_COUNT6_RX_NUM_BLOCK_3 ((uint16_t)0x2000) ñ.USB_COUNT6_RX_NUM_BLOCK_4 ((uint16_t)0x4000) ó.USB_COUNT6_RX_BLSIZE ((uint16_t)0x8000) ö.USB_COUNT7_RX_COUNT7_RX ((uint16_t)0x03FF) ø.USB_COUNT7_RX_NUM_BLOCK ((uint16_t)0x7C00) ù.USB_COUNT7_RX_NUM_BLOCK_0 ((uint16_t)0x0400) ú.USB_COUNT7_RX_NUM_BLOCK_1 ((uint16_t)0x0800) û.USB_COUNT7_RX_NUM_BLOCK_2 ((uint16_t)0x1000) ü.USB_COUNT7_RX_NUM_BLOCK_3 ((uint16_t)0x2000) ý.USB_COUNT7_RX_NUM_BLOCK_4 ((uint16_t)0x4000) ÿ.USB_COUNT7_RX_BLSIZE ((uint16_t)0x8000) /USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) ¡/USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) ¢/USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) £/USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) ¥/USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) ¨/USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) ª/USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) «/USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) ¬/USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) ®/USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) ¯/USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) ±/USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) ´/USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) ¶/USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) ·/USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) ¸/USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) ¹/USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) º/USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) »/USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) ½/USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) À/USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) Â/USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) Ã/USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) Ä/USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) Å/USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) Æ/USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) Ç/USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) É/USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) Ì/USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) Î/USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) Ï/USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) Ð/USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) Ñ/USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) Ò/USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) Ó/USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) Õ/USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) Ø/USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) Ú/USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) Û/USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) Ü/USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) Ý/USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) Þ/USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) ß/USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) á/USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) ä/USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) æ/USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) ç/USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) è/USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) é/USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) ê/USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) ë/USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) í/USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) ð/USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) ò/USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) ó/USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) ô/USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) õ/USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) ö/USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) ÷/USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) ù/USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) ü/USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) þ/USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) ÿ/USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) 0USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) 0USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) 0USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) 0USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000)
0USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) 0USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) 0USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) 0USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) 0USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) 0USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) 0USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) 0USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) 0USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) 0USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) 0USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) 0USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) 0USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) 0USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) 0USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) 0USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) 0USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) 0USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) ¢0USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) £0USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) ¤0USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) ¥0USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) ¦0USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) §0USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) ©0USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) ¬0USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) ®0USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) ¯0USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) °0USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) ±0USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) ²0USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) ³0USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) µ0USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) ¸0USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) º0USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) »0USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) ¼0USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) ½0USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) ¾0USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) ¿0USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) Á0USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) Ë0CAN_MCR_INRQ ((uint16_t)0x0001) Ì0CAN_MCR_SLEEP ((uint16_t)0x0002) Í0CAN_MCR_TXFP ((uint16_t)0x0004) Î0CAN_MCR_RFLM ((uint16_t)0x0008) Ï0CAN_MCR_NART ((uint16_t)0x0010) Ð0CAN_MCR_AWUM ((uint16_t)0x0020) Ñ0CAN_MCR_ABOM ((uint16_t)0x0040) Ò0CAN_MCR_TTCM ((uint16_t)0x0080) Ó0CAN_MCR_RESET ((uint16_t)0x8000) Ö0CAN_MSR_INAK ((uint16_t)0x0001) ×0CAN_MSR_SLAK ((uint16_t)0x0002) Ø0CAN_MSR_ERRI ((uint16_t)0x0004) Ù0CAN_MSR_WKUI ((uint16_t)0x0008) Ú0CAN_MSR_SLAKI ((uint16_t)0x0010) Û0CAN_MSR_TXM ((uint16_t)0x0100) Ü0CAN_MSR_RXM ((uint16_t)0x0200) Ý0CAN_MSR_SAMP ((uint16_t)0x0400) Þ0CAN_MSR_RX ((uint16_t)0x0800) á0CAN_TSR_RQCP0 ((uint32_t)0x00000001) â0CAN_TSR_TXOK0 ((uint32_t)0x00000002) ã0CAN_TSR_ALST0 ((uint32_t)0x00000004) ä0CAN_TSR_TERR0 ((uint32_t)0x00000008) å0CAN_TSR_ABRQ0 ((uint32_t)0x00000080) æ0CAN_TSR_RQCP1 ((uint32_t)0x00000100) ç0CAN_TSR_TXOK1 ((uint32_t)0x00000200) è0CAN_TSR_ALST1 ((uint32_t)0x00000400) é0CAN_TSR_TERR1 ((uint32_t)0x00000800) ê0CAN_TSR_ABRQ1 ((uint32_t)0x00008000) ë0CAN_TSR_RQCP2 ((uint32_t)0x00010000) ì0CAN_TSR_TXOK2 ((uint32_t)0x00020000) í0CAN_TSR_ALST2 ((uint32_t)0x00040000) î0CAN_TSR_TERR2 ((uint32_t)0x00080000) ï0CAN_TSR_ABRQ2 ((uint32_t)0x00800000) ð0CAN_TSR_CODE ((uint32_t)0x03000000) ò0CAN_TSR_TME ((uint32_t)0x1C000000) ó0CAN_TSR_TME0 ((uint32_t)0x04000000) ô0CAN_TSR_TME1 ((uint32_t)0x08000000) õ0CAN_TSR_TME2 ((uint32_t)0x10000000) ÷0CAN_TSR_LOW ((uint32_t)0xE0000000) ø0CAN_TSR_LOW0 ((uint32_t)0x20000000) ù0CAN_TSR_LOW1 ((uint32_t)0x40000000) ú0CAN_TSR_LOW2 ((uint32_t)0x80000000) ý0CAN_RF0R_FMP0 ((uint8_t)0x03) þ0CAN_RF0R_FULL0 ((uint8_t)0x08) ÿ0CAN_RF0R_FOVR0 ((uint8_t)0x10) 1CAN_RF0R_RFOM0 ((uint8_t)0x20) 1CAN_RF1R_FMP1 ((uint8_t)0x03) 1CAN_RF1R_FULL1 ((uint8_t)0x08)
1CAN_RF1R_FOVR1 ((uint8_t)0x10) 1CAN_RF1R_RFOM1 ((uint8_t)0x20) 1CAN_IER_TMEIE ((uint32_t)0x00000001) 1CAN_IER_FMPIE0 ((uint32_t)0x00000002) 1CAN_IER_FFIE0 ((uint32_t)0x00000004) 1CAN_IER_FOVIE0 ((uint32_t)0x00000008) 1CAN_IER_FMPIE1 ((uint32_t)0x00000010) 1CAN_IER_FFIE1 ((uint32_t)0x00000020) 1CAN_IER_FOVIE1 ((uint32_t)0x00000040) 1CAN_IER_EWGIE ((uint32_t)0x00000100) 1CAN_IER_EPVIE ((uint32_t)0x00000200) 1CAN_IER_BOFIE ((uint32_t)0x00000400) 1CAN_IER_LECIE ((uint32_t)0x00000800) 1CAN_IER_ERRIE ((uint32_t)0x00008000) 1CAN_IER_WKUIE ((uint32_t)0x00010000) 1CAN_IER_SLKIE ((uint32_t)0x00020000) 1CAN_ESR_EWGF ((uint32_t)0x00000001) 1CAN_ESR_EPVF ((uint32_t)0x00000002) 1CAN_ESR_BOFF ((uint32_t)0x00000004) 1CAN_ESR_LEC ((uint32_t)0x00000070) 1CAN_ESR_LEC_0 ((uint32_t)0x00000010) 1CAN_ESR_LEC_1 ((uint32_t)0x00000020) 1CAN_ESR_LEC_2 ((uint32_t)0x00000040) ¢1CAN_ESR_TEC ((uint32_t)0x00FF0000) £1CAN_ESR_REC ((uint32_t)0xFF000000) ¦1CAN_BTR_BRP ((uint32_t)0x000003FF) §1CAN_BTR_TS1 ((uint32_t)0x000F0000) ¨1CAN_BTR_TS2 ((uint32_t)0x00700000) ©1CAN_BTR_SJW ((uint32_t)0x03000000) ª1CAN_BTR_LBKM ((uint32_t)0x40000000) «1CAN_BTR_SILM ((uint32_t)0x80000000) ¯1CAN_TI0R_TXRQ ((uint32_t)0x00000001) °1CAN_TI0R_RTR ((uint32_t)0x00000002) ±1CAN_TI0R_IDE ((uint32_t)0x00000004) ²1CAN_TI0R_EXID ((uint32_t)0x001FFFF8) ³1CAN_TI0R_STID ((uint32_t)0xFFE00000) ¶1CAN_TDT0R_DLC ((uint32_t)0x0000000F) ·1CAN_TDT0R_TGT ((uint32_t)0x00000100) ¸1CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) »1CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) ¼1CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) ½1CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) ¾1CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) Á1CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) Â1CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) Ã1CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) Ä1CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) Ç1CAN_TI1R_TXRQ ((uint32_t)0x00000001) È1CAN_TI1R_RTR ((uint32_t)0x00000002) É1CAN_TI1R_IDE ((uint32_t)0x00000004) Ê1CAN_TI1R_EXID ((uint32_t)0x001FFFF8) Ë1CAN_TI1R_STID ((uint32_t)0xFFE00000) Î1CAN_TDT1R_DLC ((uint32_t)0x0000000F) Ï1CAN_TDT1R_TGT ((uint32_t)0x00000100) Ð1CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) Ó1CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) Ô1CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) Õ1CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) Ö1CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) Ù1CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) Ú1CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) Û1CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) Ü1CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) ß1CAN_TI2R_TXRQ ((uint32_t)0x00000001) à1CAN_TI2R_RTR ((uint32_t)0x00000002) á1CAN_TI2R_IDE ((uint32_t)0x00000004) â1CAN_TI2R_EXID ((uint32_t)0x001FFFF8) ã1CAN_TI2R_STID ((uint32_t)0xFFE00000) æ1CAN_TDT2R_DLC ((uint32_t)0x0000000F) ç1CAN_TDT2R_TGT ((uint32_t)0x00000100) è1CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) ë1CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) ì1CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) í1CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) î1CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) ñ1CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) ò1CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) ó1CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) ô1CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) ÷1CAN_RI0R_RTR ((uint32_t)0x00000002) ø1CAN_RI0R_IDE ((uint32_t)0x00000004) ù1CAN_RI0R_EXID ((uint32_t)0x001FFFF8) ú1CAN_RI0R_STID ((uint32_t)0xFFE00000) ý1CAN_RDT0R_DLC ((uint32_t)0x0000000F) þ1CAN_RDT0R_FMI ((uint32_t)0x0000FF00) ÿ1CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) 2CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) 2CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) 2CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000)
2CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) 2CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) 2CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) 2CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) 2CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) 2CAN_RI1R_RTR ((uint32_t)0x00000002) 2CAN_RI1R_IDE ((uint32_t)0x00000004) 2CAN_RI1R_EXID ((uint32_t)0x001FFFF8) 2CAN_RI1R_STID ((uint32_t)0xFFE00000) 2CAN_RDT1R_DLC ((uint32_t)0x0000000F) 2CAN_RDT1R_FMI ((uint32_t)0x0000FF00) 2CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) 2CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) 2CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) 2CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) 2CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) 2CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) 2CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) ¡2CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) ¢2CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) ¦2CAN_FMR_FINIT ((uint8_t)0x01) ©2CAN_FM1R_FBM ((uint16_t)0x3FFF) ª2CAN_FM1R_FBM0 ((uint16_t)0x0001) «2CAN_FM1R_FBM1 ((uint16_t)0x0002) ¬2CAN_FM1R_FBM2 ((uint16_t)0x0004) 2CAN_FM1R_FBM3 ((uint16_t)0x0008) ®2CAN_FM1R_FBM4 ((uint16_t)0x0010) ¯2CAN_FM1R_FBM5 ((uint16_t)0x0020) °2CAN_FM1R_FBM6 ((uint16_t)0x0040) ±2CAN_FM1R_FBM7 ((uint16_t)0x0080) ²2CAN_FM1R_FBM8 ((uint16_t)0x0100) ³2CAN_FM1R_FBM9 ((uint16_t)0x0200) ´2CAN_FM1R_FBM10 ((uint16_t)0x0400) µ2CAN_FM1R_FBM11 ((uint16_t)0x0800) ¶2CAN_FM1R_FBM12 ((uint16_t)0x1000) ·2CAN_FM1R_FBM13 ((uint16_t)0x2000) º2CAN_FS1R_FSC ((uint16_t)0x3FFF) »2CAN_FS1R_FSC0 ((uint16_t)0x0001) ¼2CAN_FS1R_FSC1 ((uint16_t)0x0002) ½2CAN_FS1R_FSC2 ((uint16_t)0x0004) ¾2CAN_FS1R_FSC3 ((uint16_t)0x0008) ¿2CAN_FS1R_FSC4 ((uint16_t)0x0010) À2CAN_FS1R_FSC5 ((uint16_t)0x0020) Á2CAN_FS1R_FSC6 ((uint16_t)0x0040) Â2CAN_FS1R_FSC7 ((uint16_t)0x0080) Ã2CAN_FS1R_FSC8 ((uint16_t)0x0100) Ä2CAN_FS1R_FSC9 ((uint16_t)0x0200) Å2CAN_FS1R_FSC10 ((uint16_t)0x0400) Æ2CAN_FS1R_FSC11 ((uint16_t)0x0800) Ç2CAN_FS1R_FSC12 ((uint16_t)0x1000) È2CAN_FS1R_FSC13 ((uint16_t)0x2000) Ë2CAN_FFA1R_FFA ((uint16_t)0x3FFF) Ì2CAN_FFA1R_FFA0 ((uint16_t)0x0001) Í2CAN_FFA1R_FFA1 ((uint16_t)0x0002) Î2CAN_FFA1R_FFA2 ((uint16_t)0x0004) Ï2CAN_FFA1R_FFA3 ((uint16_t)0x0008) Ð2CAN_FFA1R_FFA4 ((uint16_t)0x0010) Ñ2CAN_FFA1R_FFA5 ((uint16_t)0x0020) Ò2CAN_FFA1R_FFA6 ((uint16_t)0x0040) Ó2CAN_FFA1R_FFA7 ((uint16_t)0x0080) Ô2CAN_FFA1R_FFA8 ((uint16_t)0x0100) Õ2CAN_FFA1R_FFA9 ((uint16_t)0x0200) Ö2CAN_FFA1R_FFA10 ((uint16_t)0x0400) ×2CAN_FFA1R_FFA11 ((uint16_t)0x0800) Ø2CAN_FFA1R_FFA12 ((uint16_t)0x1000) Ù2CAN_FFA1R_FFA13 ((uint16_t)0x2000) Ü2CAN_FA1R_FACT ((uint16_t)0x3FFF) Ý2CAN_FA1R_FACT0 ((uint16_t)0x0001) Þ2CAN_FA1R_FACT1 ((uint16_t)0x0002) ß2CAN_FA1R_FACT2 ((uint16_t)0x0004) à2CAN_FA1R_FACT3 ((uint16_t)0x0008) á2CAN_FA1R_FACT4 ((uint16_t)0x0010) â2CAN_FA1R_FACT5 ((uint16_t)0x0020) ã2CAN_FA1R_FACT6 ((uint16_t)0x0040) ä2CAN_FA1R_FACT7 ((uint16_t)0x0080) å2CAN_FA1R_FACT8 ((uint16_t)0x0100) æ2CAN_FA1R_FACT9 ((uint16_t)0x0200) ç2CAN_FA1R_FACT10 ((uint16_t)0x0400) è2CAN_FA1R_FACT11 ((uint16_t)0x0800) é2CAN_FA1R_FACT12 ((uint16_t)0x1000) ê2CAN_FA1R_FACT13 ((uint16_t)0x2000) í2CAN_F0R1_FB0 ((uint32_t)0x00000001) î2CAN_F0R1_FB1 ((uint32_t)0x00000002) ï2CAN_F0R1_FB2 ((uint32_t)0x00000004) ð2CAN_F0R1_FB3 ((uint32_t)0x00000008) ñ2CAN_F0R1_FB4 ((uint32_t)0x00000010) ò2CAN_F0R1_FB5 ((uint32_t)0x00000020) ó2CAN_F0R1_FB6 ((uint32_t)0x00000040) ô2CAN_F0R1_FB7 ((uint32_t)0x00000080) õ2CAN_F0R1_FB8 ((uint32_t)0x00000100) ö2CAN_F0R1_FB9 ((uint32_t)0x00000200) ÷2CAN_F0R1_FB10 ((uint32_t)0x00000400) ø2CAN_F0R1_FB11 ((uint32_t)0x00000800) ù2CAN_F0R1_FB12 ((uint32_t)0x00001000) ú2CAN_F0R1_FB13 ((uint32_t)0x00002000) û2CAN_F0R1_FB14 ((uint32_t)0x00004000) ü2CAN_F0R1_FB15 ((uint32_t)0x00008000) ý2CAN_F0R1_FB16 ((uint32_t)0x00010000) þ2CAN_F0R1_FB17 ((uint32_t)0x00020000) ÿ2CAN_F0R1_FB18 ((uint32_t)0x00040000) 3CAN_F0R1_FB19 ((uint32_t)0x00080000) 3CAN_F0R1_FB20 ((uint32_t)0x00100000) 3CAN_F0R1_FB21 ((uint32_t)0x00200000) 3CAN_F0R1_FB22 ((uint32_t)0x00400000) 3CAN_F0R1_FB23 ((uint32_t)0x00800000)
3CAN_F0R1_FB24 ((uint32_t)0x01000000) 3CAN_F0R1_FB25 ((uint32_t)0x02000000) 3CAN_F0R1_FB26 ((uint32_t)0x04000000) 3CAN_F0R1_FB27 ((uint32_t)0x08000000) 3CAN_F0R1_FB28 ((uint32_t)0x10000000) 3CAN_F0R1_FB29 ((uint32_t)0x20000000) 3CAN_F0R1_FB30 ((uint32_t)0x40000000) 3CAN_F0R1_FB31 ((uint32_t)0x80000000) 3CAN_F1R1_FB0 ((uint32_t)0x00000001) 3CAN_F1R1_FB1 ((uint32_t)0x00000002) 3CAN_F1R1_FB2 ((uint32_t)0x00000004) 3CAN_F1R1_FB3 ((uint32_t)0x00000008) 3CAN_F1R1_FB4 ((uint32_t)0x00000010) 3CAN_F1R1_FB5 ((uint32_t)0x00000020) 3CAN_F1R1_FB6 ((uint32_t)0x00000040) 3CAN_F1R1_FB7 ((uint32_t)0x00000080) 3CAN_F1R1_FB8 ((uint32_t)0x00000100) 3CAN_F1R1_FB9 ((uint32_t)0x00000200) 3CAN_F1R1_FB10 ((uint32_t)0x00000400) 3CAN_F1R1_FB11 ((uint32_t)0x00000800) 3CAN_F1R1_FB12 ((uint32_t)0x00001000) 3CAN_F1R1_FB13 ((uint32_t)0x00002000) 3CAN_F1R1_FB14 ((uint32_t)0x00004000) 3CAN_F1R1_FB15 ((uint32_t)0x00008000) 3CAN_F1R1_FB16 ((uint32_t)0x00010000) 3CAN_F1R1_FB17 ((uint32_t)0x00020000) ¡3CAN_F1R1_FB18 ((uint32_t)0x00040000) ¢3CAN_F1R1_FB19 ((uint32_t)0x00080000) £3CAN_F1R1_FB20 ((uint32_t)0x00100000) ¤3CAN_F1R1_FB21 ((uint32_t)0x00200000) ¥3CAN_F1R1_FB22 ((uint32_t)0x00400000) ¦3CAN_F1R1_FB23 ((uint32_t)0x00800000) §3CAN_F1R1_FB24 ((uint32_t)0x01000000) ¨3CAN_F1R1_FB25 ((uint32_t)0x02000000) ©3CAN_F1R1_FB26 ((uint32_t)0x04000000) ª3CAN_F1R1_FB27 ((uint32_t)0x08000000) «3CAN_F1R1_FB28 ((uint32_t)0x10000000) ¬3CAN_F1R1_FB29 ((uint32_t)0x20000000) 3CAN_F1R1_FB30 ((uint32_t)0x40000000) ®3CAN_F1R1_FB31 ((uint32_t)0x80000000) ±3CAN_F2R1_FB0 ((uint32_t)0x00000001) ²3CAN_F2R1_FB1 ((uint32_t)0x00000002) ³3CAN_F2R1_FB2 ((uint32_t)0x00000004) ´3CAN_F2R1_FB3 ((uint32_t)0x00000008) µ3CAN_F2R1_FB4 ((uint32_t)0x00000010) ¶3CAN_F2R1_FB5 ((uint32_t)0x00000020) ·3CAN_F2R1_FB6 ((uint32_t)0x00000040) ¸3CAN_F2R1_FB7 ((uint32_t)0x00000080) ¹3CAN_F2R1_FB8 ((uint32_t)0x00000100) º3CAN_F2R1_FB9 ((uint32_t)0x00000200) »3CAN_F2R1_FB10 ((uint32_t)0x00000400) ¼3CAN_F2R1_FB11 ((uint32_t)0x00000800) ½3CAN_F2R1_FB12 ((uint32_t)0x00001000) ¾3CAN_F2R1_FB13 ((uint32_t)0x00002000) ¿3CAN_F2R1_FB14 ((uint32_t)0x00004000) À3CAN_F2R1_FB15 ((uint32_t)0x00008000) Á3CAN_F2R1_FB16 ((uint32_t)0x00010000) Â3CAN_F2R1_FB17 ((uint32_t)0x00020000) Ã3CAN_F2R1_FB18 ((uint32_t)0x00040000) Ä3CAN_F2R1_FB19 ((uint32_t)0x00080000) Å3CAN_F2R1_FB20 ((uint32_t)0x00100000) Æ3CAN_F2R1_FB21 ((uint32_t)0x00200000) Ç3CAN_F2R1_FB22 ((uint32_t)0x00400000) È3CAN_F2R1_FB23 ((uint32_t)0x00800000) É3CAN_F2R1_FB24 ((uint32_t)0x01000000) Ê3CAN_F2R1_FB25 ((uint32_t)0x02000000) Ë3CAN_F2R1_FB26 ((uint32_t)0x04000000) Ì3CAN_F2R1_FB27 ((uint32_t)0x08000000) Í3CAN_F2R1_FB28 ((uint32_t)0x10000000) Î3CAN_F2R1_FB29 ((uint32_t)0x20000000) Ï3CAN_F2R1_FB30 ((uint32_t)0x40000000) Ð3CAN_F2R1_FB31 ((uint32_t)0x80000000) Ó3CAN_F3R1_FB0 ((uint32_t)0x00000001) Ô3CAN_F3R1_FB1 ((uint32_t)0x00000002) Õ3CAN_F3R1_FB2 ((uint32_t)0x00000004) Ö3CAN_F3R1_FB3 ((uint32_t)0x00000008) ×3CAN_F3R1_FB4 ((uint32_t)0x00000010) Ø3CAN_F3R1_FB5 ((uint32_t)0x00000020) Ù3CAN_F3R1_FB6 ((uint32_t)0x00000040) Ú3CAN_F3R1_FB7 ((uint32_t)0x00000080) Û3CAN_F3R1_FB8 ((uint32_t)0x00000100) Ü3CAN_F3R1_FB9 ((uint32_t)0x00000200) Ý3CAN_F3R1_FB10 ((uint32_t)0x00000400) Þ3CAN_F3R1_FB11 ((uint32_t)0x00000800) ß3CAN_F3R1_FB12 ((uint32_t)0x00001000) à3CAN_F3R1_FB13 ((uint32_t)0x00002000) á3CAN_F3R1_FB14 ((uint32_t)0x00004000) â3CAN_F3R1_FB15 ((uint32_t)0x00008000) ã3CAN_F3R1_FB16 ((uint32_t)0x00010000) ä3CAN_F3R1_FB17 ((uint32_t)0x00020000) å3CAN_F3R1_FB18 ((uint32_t)0x00040000) æ3CAN_F3R1_FB19 ((uint32_t)0x00080000) ç3CAN_F3R1_FB20 ((uint32_t)0x00100000) è3CAN_F3R1_FB21 ((uint32_t)0x00200000) é3CAN_F3R1_FB22 ((uint32_t)0x00400000) ê3CAN_F3R1_FB23 ((uint32_t)0x00800000) ë3CAN_F3R1_FB24 ((uint32_t)0x01000000) ì3CAN_F3R1_FB25 ((uint32_t)0x02000000) í3CAN_F3R1_FB26 ((uint32_t)0x04000000) î3CAN_F3R1_FB27 ((uint32_t)0x08000000) ï3CAN_F3R1_FB28 ((uint32_t)0x10000000) ð3CAN_F3R1_FB29 ((uint32_t)0x20000000) ñ3CAN_F3R1_FB30 ((uint32_t)0x40000000) ò3CAN_F3R1_FB31 ((uint32_t)0x80000000) õ3CAN_F4R1_FB0 ((uint32_t)0x00000001) ö3CAN_F4R1_FB1 ((uint32_t)0x00000002) ÷3CAN_F4R1_FB2 ((uint32_t)0x00000004) ø3CAN_F4R1_FB3 ((uint32_t)0x00000008) ù3CAN_F4R1_FB4 ((uint32_t)0x00000010) ú3CAN_F4R1_FB5 ((uint32_t)0x00000020) û3CAN_F4R1_FB6 ((uint32_t)0x00000040) ü3CAN_F4R1_FB7 ((uint32_t)0x00000080) ý3CAN_F4R1_FB8 ((uint32_t)0x00000100) þ3CAN_F4R1_FB9 ((uint32_t)0x00000200) ÿ3CAN_F4R1_FB10 ((uint32_t)0x00000400) 4CAN_F4R1_FB11 ((uint32_t)0x00000800) 4CAN_F4R1_FB12 ((uint32_t)0x00001000) 4CAN_F4R1_FB13 ((uint32_t)0x00002000) 4CAN_F4R1_FB14 ((uint32_t)0x00004000) 4CAN_F4R1_FB15 ((uint32_t)0x00008000)
4CAN_F4R1_FB16 ((uint32_t)0x00010000) 4CAN_F4R1_FB17 ((uint32_t)0x00020000) 4CAN_F4R1_FB18 ((uint32_t)0x00040000) 4CAN_F4R1_FB19 ((uint32_t)0x00080000) 4CAN_F4R1_FB20 ((uint32_t)0x00100000) 4CAN_F4R1_FB21 ((uint32_t)0x00200000) 4CAN_F4R1_FB22 ((uint32_t)0x00400000) 4CAN_F4R1_FB23 ((uint32_t)0x00800000) 4CAN_F4R1_FB24 ((uint32_t)0x01000000) 4CAN_F4R1_FB25 ((uint32_t)0x02000000) 4CAN_F4R1_FB26 ((uint32_t)0x04000000) 4CAN_F4R1_FB27 ((uint32_t)0x08000000) 4CAN_F4R1_FB28 ((uint32_t)0x10000000) 4CAN_F4R1_FB29 ((uint32_t)0x20000000) 4CAN_F4R1_FB30 ((uint32_t)0x40000000) 4CAN_F4R1_FB31 ((uint32_t)0x80000000) 4CAN_F5R1_FB0 ((uint32_t)0x00000001) 4CAN_F5R1_FB1 ((uint32_t)0x00000002) 4CAN_F5R1_FB2 ((uint32_t)0x00000004) 4CAN_F5R1_FB3 ((uint32_t)0x00000008) 4CAN_F5R1_FB4 ((uint32_t)0x00000010) 4CAN_F5R1_FB5 ((uint32_t)0x00000020) 4CAN_F5R1_FB6 ((uint32_t)0x00000040) 4CAN_F5R1_FB7 ((uint32_t)0x00000080) 4CAN_F5R1_FB8 ((uint32_t)0x00000100) 4CAN_F5R1_FB9 ((uint32_t)0x00000200) ¡4CAN_F5R1_FB10 ((uint32_t)0x00000400) ¢4CAN_F5R1_FB11 ((uint32_t)0x00000800) £4CAN_F5R1_FB12 ((uint32_t)0x00001000) ¤4CAN_F5R1_FB13 ((uint32_t)0x00002000) ¥4CAN_F5R1_FB14 ((uint32_t)0x00004000) ¦4CAN_F5R1_FB15 ((uint32_t)0x00008000) §4CAN_F5R1_FB16 ((uint32_t)0x00010000) ¨4CAN_F5R1_FB17 ((uint32_t)0x00020000) ©4CAN_F5R1_FB18 ((uint32_t)0x00040000) ª4CAN_F5R1_FB19 ((uint32_t)0x00080000) «4CAN_F5R1_FB20 ((uint32_t)0x00100000) ¬4CAN_F5R1_FB21 ((uint32_t)0x00200000) 4CAN_F5R1_FB22 ((uint32_t)0x00400000) ®4CAN_F5R1_FB23 ((uint32_t)0x00800000) ¯4CAN_F5R1_FB24 ((uint32_t)0x01000000) °4CAN_F5R1_FB25 ((uint32_t)0x02000000) ±4CAN_F5R1_FB26 ((uint32_t)0x04000000) ²4CAN_F5R1_FB27 ((uint32_t)0x08000000) ³4CAN_F5R1_FB28 ((uint32_t)0x10000000) ´4CAN_F5R1_FB29 ((uint32_t)0x20000000) µ4CAN_F5R1_FB30 ((uint32_t)0x40000000) ¶4CAN_F5R1_FB31 ((uint32_t)0x80000000) ¹4CAN_F6R1_FB0 ((uint32_t)0x00000001) º4CAN_F6R1_FB1 ((uint32_t)0x00000002) »4CAN_F6R1_FB2 ((uint32_t)0x00000004) ¼4CAN_F6R1_FB3 ((uint32_t)0x00000008) ½4CAN_F6R1_FB4 ((uint32_t)0x00000010) ¾4CAN_F6R1_FB5 ((uint32_t)0x00000020) ¿4CAN_F6R1_FB6 ((uint32_t)0x00000040) À4CAN_F6R1_FB7 ((uint32_t)0x00000080) Á4CAN_F6R1_FB8 ((uint32_t)0x00000100) Â4CAN_F6R1_FB9 ((uint32_t)0x00000200) Ã4CAN_F6R1_FB10 ((uint32_t)0x00000400) Ä4CAN_F6R1_FB11 ((uint32_t)0x00000800) Å4CAN_F6R1_FB12 ((uint32_t)0x00001000) Æ4CAN_F6R1_FB13 ((uint32_t)0x00002000) Ç4CAN_F6R1_FB14 ((uint32_t)0x00004000) È4CAN_F6R1_FB15 ((uint32_t)0x00008000) É4CAN_F6R1_FB16 ((uint32_t)0x00010000) Ê4CAN_F6R1_FB17 ((uint32_t)0x00020000) Ë4CAN_F6R1_FB18 ((uint32_t)0x00040000) Ì4CAN_F6R1_FB19 ((uint32_t)0x00080000) Í4CAN_F6R1_FB20 ((uint32_t)0x00100000) Î4CAN_F6R1_FB21 ((uint32_t)0x00200000) Ï4CAN_F6R1_FB22 ((uint32_t)0x00400000) Ð4CAN_F6R1_FB23 ((uint32_t)0x00800000) Ñ4CAN_F6R1_FB24 ((uint32_t)0x01000000) Ò4CAN_F6R1_FB25 ((uint32_t)0x02000000) Ó4CAN_F6R1_FB26 ((uint32_t)0x04000000) Ô4CAN_F6R1_FB27 ((uint32_t)0x08000000) Õ4CAN_F6R1_FB28 ((uint32_t)0x10000000) Ö4CAN_F6R1_FB29 ((uint32_t)0x20000000) ×4CAN_F6R1_FB30 ((uint32_t)0x40000000) Ø4CAN_F6R1_FB31 ((uint32_t)0x80000000) Û4CAN_F7R1_FB0 ((uint32_t)0x00000001) Ü4CAN_F7R1_FB1 ((uint32_t)0x00000002) Ý4CAN_F7R1_FB2 ((uint32_t)0x00000004) Þ4CAN_F7R1_FB3 ((uint32_t)0x00000008) ß4CAN_F7R1_FB4 ((uint32_t)0x00000010) à4CAN_F7R1_FB5 ((uint32_t)0x00000020) á4CAN_F7R1_FB6 ((uint32_t)0x00000040) â4CAN_F7R1_FB7 ((uint32_t)0x00000080) ã4CAN_F7R1_FB8 ((uint32_t)0x00000100) ä4CAN_F7R1_FB9 ((uint32_t)0x00000200) å4CAN_F7R1_FB10 ((uint32_t)0x00000400) æ4CAN_F7R1_FB11 ((uint32_t)0x00000800) ç4CAN_F7R1_FB12 ((uint32_t)0x00001000) è4CAN_F7R1_FB13 ((uint32_t)0x00002000) é4CAN_F7R1_FB14 ((uint32_t)0x00004000) ê4CAN_F7R1_FB15 ((uint32_t)0x00008000) ë4CAN_F7R1_FB16 ((uint32_t)0x00010000) ì4CAN_F7R1_FB17 ((uint32_t)0x00020000) í4CAN_F7R1_FB18 ((uint32_t)0x00040000) î4CAN_F7R1_FB19 ((uint32_t)0x00080000) ï4CAN_F7R1_FB20 ((uint32_t)0x00100000) ð4CAN_F7R1_FB21 ((uint32_t)0x00200000) ñ4CAN_F7R1_FB22 ((uint32_t)0x00400000) ò4CAN_F7R1_FB23 ((uint32_t)0x00800000) ó4CAN_F7R1_FB24 ((uint32_t)0x01000000) ô4CAN_F7R1_FB25 ((uint32_t)0x02000000) õ4CAN_F7R1_FB26 ((uint32_t)0x04000000) ö4CAN_F7R1_FB27 ((uint32_t)0x08000000) ÷4CAN_F7R1_FB28 ((uint32_t)0x10000000) ø4CAN_F7R1_FB29 ((uint32_t)0x20000000) ù4CAN_F7R1_FB30 ((uint32_t)0x40000000) ú4CAN_F7R1_FB31 ((uint32_t)0x80000000) ý4CAN_F8R1_FB0 ((uint32_t)0x00000001) þ4CAN_F8R1_FB1 ((uint32_t)0x00000002) ÿ4CAN_F8R1_FB2 ((uint32_t)0x00000004) 5CAN_F8R1_FB3 ((uint32_t)0x00000008) 5CAN_F8R1_FB4 ((uint32_t)0x00000010) 5CAN_F8R1_FB5 ((uint32_t)0x00000020) 5CAN_F8R1_FB6 ((uint32_t)0x00000040) 5CAN_F8R1_FB7 ((uint32_t)0x00000080)
5CAN_F8R1_FB8 ((uint32_t)0x00000100) 5CAN_F8R1_FB9 ((uint32_t)0x00000200) 5CAN_F8R1_FB10 ((uint32_t)0x00000400) 5CAN_F8R1_FB11 ((uint32_t)0x00000800) 5CAN_F8R1_FB12 ((uint32_t)0x00001000) 5CAN_F8R1_FB13 ((uint32_t)0x00002000) 5CAN_F8R1_FB14 ((uint32_t)0x00004000) 5CAN_F8R1_FB15 ((uint32_t)0x00008000) 5CAN_F8R1_FB16 ((uint32_t)0x00010000) 5CAN_F8R1_FB17 ((uint32_t)0x00020000) 5CAN_F8R1_FB18 ((uint32_t)0x00040000) 5CAN_F8R1_FB19 ((uint32_t)0x00080000) 5CAN_F8R1_FB20 ((uint32_t)0x00100000) 5CAN_F8R1_FB21 ((uint32_t)0x00200000) 5CAN_F8R1_FB22 ((uint32_t)0x00400000) 5CAN_F8R1_FB23 ((uint32_t)0x00800000) 5CAN_F8R1_FB24 ((uint32_t)0x01000000) 5CAN_F8R1_FB25 ((uint32_t)0x02000000) 5CAN_F8R1_FB26 ((uint32_t)0x04000000) 5CAN_F8R1_FB27 ((uint32_t)0x08000000) 5CAN_F8R1_FB28 ((uint32_t)0x10000000) 5CAN_F8R1_FB29 ((uint32_t)0x20000000) 5CAN_F8R1_FB30 ((uint32_t)0x40000000) 5CAN_F8R1_FB31 ((uint32_t)0x80000000) 5CAN_F9R1_FB0 ((uint32_t)0x00000001) 5CAN_F9R1_FB1 ((uint32_t)0x00000002) ¡5CAN_F9R1_FB2 ((uint32_t)0x00000004) ¢5CAN_F9R1_FB3 ((uint32_t)0x00000008) £5CAN_F9R1_FB4 ((uint32_t)0x00000010) ¤5CAN_F9R1_FB5 ((uint32_t)0x00000020) ¥5CAN_F9R1_FB6 ((uint32_t)0x00000040) ¦5CAN_F9R1_FB7 ((uint32_t)0x00000080) §5CAN_F9R1_FB8 ((uint32_t)0x00000100) ¨5CAN_F9R1_FB9 ((uint32_t)0x00000200) ©5CAN_F9R1_FB10 ((uint32_t)0x00000400) ª5CAN_F9R1_FB11 ((uint32_t)0x00000800) «5CAN_F9R1_FB12 ((uint32_t)0x00001000) ¬5CAN_F9R1_FB13 ((uint32_t)0x00002000) 5CAN_F9R1_FB14 ((uint32_t)0x00004000) ®5CAN_F9R1_FB15 ((uint32_t)0x00008000) ¯5CAN_F9R1_FB16 ((uint32_t)0x00010000) °5CAN_F9R1_FB17 ((uint32_t)0x00020000) ±5CAN_F9R1_FB18 ((uint32_t)0x00040000) ²5CAN_F9R1_FB19 ((uint32_t)0x00080000) ³5CAN_F9R1_FB20 ((uint32_t)0x00100000) ´5CAN_F9R1_FB21 ((uint32_t)0x00200000) µ5CAN_F9R1_FB22 ((uint32_t)0x00400000) ¶5CAN_F9R1_FB23 ((uint32_t)0x00800000) ·5CAN_F9R1_FB24 ((uint32_t)0x01000000) ¸5CAN_F9R1_FB25 ((uint32_t)0x02000000) ¹5CAN_F9R1_FB26 ((uint32_t)0x04000000) º5CAN_F9R1_FB27 ((uint32_t)0x08000000) »5CAN_F9R1_FB28 ((uint32_t)0x10000000) ¼5CAN_F9R1_FB29 ((uint32_t)0x20000000) ½5CAN_F9R1_FB30 ((uint32_t)0x40000000) ¾5CAN_F9R1_FB31 ((uint32_t)0x80000000) Á5CAN_F10R1_FB0 ((uint32_t)0x00000001) Â5CAN_F10R1_FB1 ((uint32_t)0x00000002) Ã5CAN_F10R1_FB2 ((uint32_t)0x00000004) Ä5CAN_F10R1_FB3 ((uint32_t)0x00000008) Å5CAN_F10R1_FB4 ((uint32_t)0x00000010) Æ5CAN_F10R1_FB5 ((uint32_t)0x00000020) Ç5CAN_F10R1_FB6 ((uint32_t)0x00000040) È5CAN_F10R1_FB7 ((uint32_t)0x00000080) É5CAN_F10R1_FB8 ((uint32_t)0x00000100) Ê5CAN_F10R1_FB9 ((uint32_t)0x00000200) Ë5CAN_F10R1_FB10 ((uint32_t)0x00000400) Ì5CAN_F10R1_FB11 ((uint32_t)0x00000800) Í5CAN_F10R1_FB12 ((uint32_t)0x00001000) Î5CAN_F10R1_FB13 ((uint32_t)0x00002000) Ï5CAN_F10R1_FB14 ((uint32_t)0x00004000) Ð5CAN_F10R1_FB15 ((uint32_t)0x00008000) Ñ5CAN_F10R1_FB16 ((uint32_t)0x00010000) Ò5CAN_F10R1_FB17 ((uint32_t)0x00020000) Ó5CAN_F10R1_FB18 ((uint32_t)0x00040000) Ô5CAN_F10R1_FB19 ((uint32_t)0x00080000) Õ5CAN_F10R1_FB20 ((uint32_t)0x00100000) Ö5CAN_F10R1_FB21 ((uint32_t)0x00200000) ×5CAN_F10R1_FB22 ((uint32_t)0x00400000) Ø5CAN_F10R1_FB23 ((uint32_t)0x00800000) Ù5CAN_F10R1_FB24 ((uint32_t)0x01000000) Ú5CAN_F10R1_FB25 ((uint32_t)0x02000000) Û5CAN_F10R1_FB26 ((uint32_t)0x04000000) Ü5CAN_F10R1_FB27 ((uint32_t)0x08000000) Ý5CAN_F10R1_FB28 ((uint32_t)0x10000000) Þ5CAN_F10R1_FB29 ((uint32_t)0x20000000) ß5CAN_F10R1_FB30 ((uint32_t)0x40000000) à5CAN_F10R1_FB31 ((uint32_t)0x80000000) ã5CAN_F11R1_FB0 ((uint32_t)0x00000001) ä5CAN_F11R1_FB1 ((uint32_t)0x00000002) å5CAN_F11R1_FB2 ((uint32_t)0x00000004) æ5CAN_F11R1_FB3 ((uint32_t)0x00000008) ç5CAN_F11R1_FB4 ((uint32_t)0x00000010) è5CAN_F11R1_FB5 ((uint32_t)0x00000020) é5CAN_F11R1_FB6 ((uint32_t)0x00000040) ê5CAN_F11R1_FB7 ((uint32_t)0x00000080) ë5CAN_F11R1_FB8 ((uint32_t)0x00000100) ì5CAN_F11R1_FB9 ((uint32_t)0x00000200) í5CAN_F11R1_FB10 ((uint32_t)0x00000400) î5CAN_F11R1_FB11 ((uint32_t)0x00000800) ï5CAN_F11R1_FB12 ((uint32_t)0x00001000) ð5CAN_F11R1_FB13 ((uint32_t)0x00002000) ñ5CAN_F11R1_FB14 ((uint32_t)0x00004000) ò5CAN_F11R1_FB15 ((uint32_t)0x00008000) ó5CAN_F11R1_FB16 ((uint32_t)0x00010000) ô5CAN_F11R1_FB17 ((uint32_t)0x00020000) õ5CAN_F11R1_FB18 ((uint32_t)0x00040000) ö5CAN_F11R1_FB19 ((uint32_t)0x00080000) ÷5CAN_F11R1_FB20 ((uint32_t)0x00100000) ø5CAN_F11R1_FB21 ((uint32_t)0x00200000) ù5CAN_F11R1_FB22 ((uint32_t)0x00400000) ú5CAN_F11R1_FB23 ((uint32_t)0x00800000) û5CAN_F11R1_FB24 ((uint32_t)0x01000000) ü5CAN_F11R1_FB25 ((uint32_t)0x02000000) ý5CAN_F11R1_FB26 ((uint32_t)0x04000000) þ5CAN_F11R1_FB27 ((uint32_t)0x08000000) ÿ5CAN_F11R1_FB28 ((uint32_t)0x10000000) 6CAN_F11R1_FB29 ((uint32_t)0x20000000) 6CAN_F11R1_FB30 ((uint32_t)0x40000000) 6CAN_F11R1_FB31 ((uint32_t)0x80000000)
6CAN_F12R1_FB0 ((uint32_t)0x00000001) 6CAN_F12R1_FB1 ((uint32_t)0x00000002) 6CAN_F12R1_FB2 ((uint32_t)0x00000004) 6CAN_F12R1_FB3 ((uint32_t)0x00000008) 6CAN_F12R1_FB4 ((uint32_t)0x00000010) 6CAN_F12R1_FB5 ((uint32_t)0x00000020) 6CAN_F12R1_FB6 ((uint32_t)0x00000040) 6CAN_F12R1_FB7 ((uint32_t)0x00000080) 6CAN_F12R1_FB8 ((uint32_t)0x00000100) 6CAN_F12R1_FB9 ((uint32_t)0x00000200) 6CAN_F12R1_FB10 ((uint32_t)0x00000400) 6CAN_F12R1_FB11 ((uint32_t)0x00000800) 6CAN_F12R1_FB12 ((uint32_t)0x00001000) 6CAN_F12R1_FB13 ((uint32_t)0x00002000) 6CAN_F12R1_FB14 ((uint32_t)0x00004000) 6CAN_F12R1_FB15 ((uint32_t)0x00008000) 6CAN_F12R1_FB16 ((uint32_t)0x00010000) 6CAN_F12R1_FB17 ((uint32_t)0x00020000) 6CAN_F12R1_FB18 ((uint32_t)0x00040000) 6CAN_F12R1_FB19 ((uint32_t)0x00080000) 6CAN_F12R1_FB20 ((uint32_t)0x00100000) 6CAN_F12R1_FB21 ((uint32_t)0x00200000) 6CAN_F12R1_FB22 ((uint32_t)0x00400000) 6CAN_F12R1_FB23 ((uint32_t)0x00800000) 6CAN_F12R1_FB24 ((uint32_t)0x01000000) 6CAN_F12R1_FB25 ((uint32_t)0x02000000) 6CAN_F12R1_FB26 ((uint32_t)0x04000000) 6CAN_F12R1_FB27 ((uint32_t)0x08000000) ¡6CAN_F12R1_FB28 ((uint32_t)0x10000000) ¢6CAN_F12R1_FB29 ((uint32_t)0x20000000) £6CAN_F12R1_FB30 ((uint32_t)0x40000000) ¤6CAN_F12R1_FB31 ((uint32_t)0x80000000) §6CAN_F13R1_FB0 ((uint32_t)0x00000001) ¨6CAN_F13R1_FB1 ((uint32_t)0x00000002) ©6CAN_F13R1_FB2 ((uint32_t)0x00000004) ª6CAN_F13R1_FB3 ((uint32_t)0x00000008) «6CAN_F13R1_FB4 ((uint32_t)0x00000010) ¬6CAN_F13R1_FB5 ((uint32_t)0x00000020) 6CAN_F13R1_FB6 ((uint32_t)0x00000040) ®6CAN_F13R1_FB7 ((uint32_t)0x00000080) ¯6CAN_F13R1_FB8 ((uint32_t)0x00000100) °6CAN_F13R1_FB9 ((uint32_t)0x00000200) ±6CAN_F13R1_FB10 ((uint32_t)0x00000400) ²6CAN_F13R1_FB11 ((uint32_t)0x00000800) ³6CAN_F13R1_FB12 ((uint32_t)0x00001000) ´6CAN_F13R1_FB13 ((uint32_t)0x00002000) µ6CAN_F13R1_FB14 ((uint32_t)0x00004000) ¶6CAN_F13R1_FB15 ((uint32_t)0x00008000) ·6CAN_F13R1_FB16 ((uint32_t)0x00010000) ¸6CAN_F13R1_FB17 ((uint32_t)0x00020000) ¹6CAN_F13R1_FB18 ((uint32_t)0x00040000) º6CAN_F13R1_FB19 ((uint32_t)0x00080000) »6CAN_F13R1_FB20 ((uint32_t)0x00100000) ¼6CAN_F13R1_FB21 ((uint32_t)0x00200000) ½6CAN_F13R1_FB22 ((uint32_t)0x00400000) ¾6CAN_F13R1_FB23 ((uint32_t)0x00800000) ¿6CAN_F13R1_FB24 ((uint32_t)0x01000000) À6CAN_F13R1_FB25 ((uint32_t)0x02000000) Á6CAN_F13R1_FB26 ((uint32_t)0x04000000) Â6CAN_F13R1_FB27 ((uint32_t)0x08000000) Ã6CAN_F13R1_FB28 ((uint32_t)0x10000000) Ä6CAN_F13R1_FB29 ((uint32_t)0x20000000) Å6CAN_F13R1_FB30 ((uint32_t)0x40000000) Æ6CAN_F13R1_FB31 ((uint32_t)0x80000000) É6CAN_F0R2_FB0 ((uint32_t)0x00000001) Ê6CAN_F0R2_FB1 ((uint32_t)0x00000002) Ë6CAN_F0R2_FB2 ((uint32_t)0x00000004) Ì6CAN_F0R2_FB3 ((uint32_t)0x00000008) Í6CAN_F0R2_FB4 ((uint32_t)0x00000010) Î6CAN_F0R2_FB5 ((uint32_t)0x00000020) Ï6CAN_F0R2_FB6 ((uint32_t)0x00000040) Ð6CAN_F0R2_FB7 ((uint32_t)0x00000080) Ñ6CAN_F0R2_FB8 ((uint32_t)0x00000100) Ò6CAN_F0R2_FB9 ((uint32_t)0x00000200) Ó6CAN_F0R2_FB10 ((uint32_t)0x00000400) Ô6CAN_F0R2_FB11 ((uint32_t)0x00000800) Õ6CAN_F0R2_FB12 ((uint32_t)0x00001000) Ö6CAN_F0R2_FB13 ((uint32_t)0x00002000) ×6CAN_F0R2_FB14 ((uint32_t)0x00004000) Ø6CAN_F0R2_FB15 ((uint32_t)0x00008000) Ù6CAN_F0R2_FB16 ((uint32_t)0x00010000) Ú6CAN_F0R2_FB17 ((uint32_t)0x00020000) Û6CAN_F0R2_FB18 ((uint32_t)0x00040000) Ü6CAN_F0R2_FB19 ((uint32_t)0x00080000) Ý6CAN_F0R2_FB20 ((uint32_t)0x00100000) Þ6CAN_F0R2_FB21 ((uint32_t)0x00200000) ß6CAN_F0R2_FB22 ((uint32_t)0x00400000) à6CAN_F0R2_FB23 ((uint32_t)0x00800000) á6CAN_F0R2_FB24 ((uint32_t)0x01000000) â6CAN_F0R2_FB25 ((uint32_t)0x02000000) ã6CAN_F0R2_FB26 ((uint32_t)0x04000000) ä6CAN_F0R2_FB27 ((uint32_t)0x08000000) å6CAN_F0R2_FB28 ((uint32_t)0x10000000) æ6CAN_F0R2_FB29 ((uint32_t)0x20000000) ç6CAN_F0R2_FB30 ((uint32_t)0x40000000) è6CAN_F0R2_FB31 ((uint32_t)0x80000000) ë6CAN_F1R2_FB0 ((uint32_t)0x00000001) ì6CAN_F1R2_FB1 ((uint32_t)0x00000002) í6CAN_F1R2_FB2 ((uint32_t)0x00000004) î6CAN_F1R2_FB3 ((uint32_t)0x00000008) ï6CAN_F1R2_FB4 ((uint32_t)0x00000010) ð6CAN_F1R2_FB5 ((uint32_t)0x00000020) ñ6CAN_F1R2_FB6 ((uint32_t)0x00000040) ò6CAN_F1R2_FB7 ((uint32_t)0x00000080) ó6CAN_F1R2_FB8 ((uint32_t)0x00000100) ô6CAN_F1R2_FB9 ((uint32_t)0x00000200) õ6CAN_F1R2_FB10 ((uint32_t)0x00000400) ö6CAN_F1R2_FB11 ((uint32_t)0x00000800) ÷6CAN_F1R2_FB12 ((uint32_t)0x00001000) ø6CAN_F1R2_FB13 ((uint32_t)0x00002000) ù6CAN_F1R2_FB14 ((uint32_t)0x00004000) ú6CAN_F1R2_FB15 ((uint32_t)0x00008000) û6CAN_F1R2_FB16 ((uint32_t)0x00010000) ü6CAN_F1R2_FB17 ((uint32_t)0x00020000) ý6CAN_F1R2_FB18 ((uint32_t)0x00040000) þ6CAN_F1R2_FB19 ((uint32_t)0x00080000) ÿ6CAN_F1R2_FB20 ((uint32_t)0x00100000) 7CAN_F1R2_FB21 ((uint32_t)0x00200000) 7CAN_F1R2_FB22 ((uint32_t)0x00400000) 7CAN_F1R2_FB23 ((uint32_t)0x00800000) 7CAN_F1R2_FB24 ((uint32_t)0x01000000) 7CAN_F1R2_FB25 ((uint32_t)0x02000000)
7CAN_F1R2_FB26 ((uint32_t)0x04000000) 7CAN_F1R2_FB27 ((uint32_t)0x08000000) 7CAN_F1R2_FB28 ((uint32_t)0x10000000) 7CAN_F1R2_FB29 ((uint32_t)0x20000000) 7CAN_F1R2_FB30 ((uint32_t)0x40000000) 7CAN_F1R2_FB31 ((uint32_t)0x80000000) 7CAN_F2R2_FB0 ((uint32_t)0x00000001) 7CAN_F2R2_FB1 ((uint32_t)0x00000002) 7CAN_F2R2_FB2 ((uint32_t)0x00000004) 7CAN_F2R2_FB3 ((uint32_t)0x00000008) 7CAN_F2R2_FB4 ((uint32_t)0x00000010) 7CAN_F2R2_FB5 ((uint32_t)0x00000020) 7CAN_F2R2_FB6 ((uint32_t)0x00000040) 7CAN_F2R2_FB7 ((uint32_t)0x00000080) 7CAN_F2R2_FB8 ((uint32_t)0x00000100) 7CAN_F2R2_FB9 ((uint32_t)0x00000200) 7CAN_F2R2_FB10 ((uint32_t)0x00000400) 7CAN_F2R2_FB11 ((uint32_t)0x00000800) 7CAN_F2R2_FB12 ((uint32_t)0x00001000) 7CAN_F2R2_FB13 ((uint32_t)0x00002000) 7CAN_F2R2_FB14 ((uint32_t)0x00004000) 7CAN_F2R2_FB15 ((uint32_t)0x00008000) 7CAN_F2R2_FB16 ((uint32_t)0x00010000) 7CAN_F2R2_FB17 ((uint32_t)0x00020000) 7CAN_F2R2_FB18 ((uint32_t)0x00040000) 7CAN_F2R2_FB19 ((uint32_t)0x00080000) ¡7CAN_F2R2_FB20 ((uint32_t)0x00100000) ¢7CAN_F2R2_FB21 ((uint32_t)0x00200000) £7CAN_F2R2_FB22 ((uint32_t)0x00400000) ¤7CAN_F2R2_FB23 ((uint32_t)0x00800000) ¥7CAN_F2R2_FB24 ((uint32_t)0x01000000) ¦7CAN_F2R2_FB25 ((uint32_t)0x02000000) §7CAN_F2R2_FB26 ((uint32_t)0x04000000) ¨7CAN_F2R2_FB27 ((uint32_t)0x08000000) ©7CAN_F2R2_FB28 ((uint32_t)0x10000000) ª7CAN_F2R2_FB29 ((uint32_t)0x20000000) «7CAN_F2R2_FB30 ((uint32_t)0x40000000) ¬7CAN_F2R2_FB31 ((uint32_t)0x80000000) ¯7CAN_F3R2_FB0 ((uint32_t)0x00000001) °7CAN_F3R2_FB1 ((uint32_t)0x00000002) ±7CAN_F3R2_FB2 ((uint32_t)0x00000004) ²7CAN_F3R2_FB3 ((uint32_t)0x00000008) ³7CAN_F3R2_FB4 ((uint32_t)0x00000010) ´7CAN_F3R2_FB5 ((uint32_t)0x00000020) µ7CAN_F3R2_FB6 ((uint32_t)0x00000040) ¶7CAN_F3R2_FB7 ((uint32_t)0x00000080) ·7CAN_F3R2_FB8 ((uint32_t)0x00000100) ¸7CAN_F3R2_FB9 ((uint32_t)0x00000200) ¹7CAN_F3R2_FB10 ((uint32_t)0x00000400) º7CAN_F3R2_FB11 ((uint32_t)0x00000800) »7CAN_F3R2_FB12 ((uint32_t)0x00001000) ¼7CAN_F3R2_FB13 ((uint32_t)0x00002000) ½7CAN_F3R2_FB14 ((uint32_t)0x00004000) ¾7CAN_F3R2_FB15 ((uint32_t)0x00008000) ¿7CAN_F3R2_FB16 ((uint32_t)0x00010000) À7CAN_F3R2_FB17 ((uint32_t)0x00020000) Á7CAN_F3R2_FB18 ((uint32_t)0x00040000) Â7CAN_F3R2_FB19 ((uint32_t)0x00080000) Ã7CAN_F3R2_FB20 ((uint32_t)0x00100000) Ä7CAN_F3R2_FB21 ((uint32_t)0x00200000) Å7CAN_F3R2_FB22 ((uint32_t)0x00400000) Æ7CAN_F3R2_FB23 ((uint32_t)0x00800000) Ç7CAN_F3R2_FB24 ((uint32_t)0x01000000) È7CAN_F3R2_FB25 ((uint32_t)0x02000000) É7CAN_F3R2_FB26 ((uint32_t)0x04000000) Ê7CAN_F3R2_FB27 ((uint32_t)0x08000000) Ë7CAN_F3R2_FB28 ((uint32_t)0x10000000) Ì7CAN_F3R2_FB29 ((uint32_t)0x20000000) Í7CAN_F3R2_FB30 ((uint32_t)0x40000000) Î7CAN_F3R2_FB31 ((uint32_t)0x80000000) Ñ7CAN_F4R2_FB0 ((uint32_t)0x00000001) Ò7CAN_F4R2_FB1 ((uint32_t)0x00000002) Ó7CAN_F4R2_FB2 ((uint32_t)0x00000004) Ô7CAN_F4R2_FB3 ((uint32_t)0x00000008) Õ7CAN_F4R2_FB4 ((uint32_t)0x00000010) Ö7CAN_F4R2_FB5 ((uint32_t)0x00000020) ×7CAN_F4R2_FB6 ((uint32_t)0x00000040) Ø7CAN_F4R2_FB7 ((uint32_t)0x00000080) Ù7CAN_F4R2_FB8 ((uint32_t)0x00000100) Ú7CAN_F4R2_FB9 ((uint32_t)0x00000200) Û7CAN_F4R2_FB10 ((uint32_t)0x00000400) Ü7CAN_F4R2_FB11 ((uint32_t)0x00000800) Ý7CAN_F4R2_FB12 ((uint32_t)0x00001000) Þ7CAN_F4R2_FB13 ((uint32_t)0x00002000) ß7CAN_F4R2_FB14 ((uint32_t)0x00004000) à7CAN_F4R2_FB15 ((uint32_t)0x00008000) á7CAN_F4R2_FB16 ((uint32_t)0x00010000) â7CAN_F4R2_FB17 ((uint32_t)0x00020000) ã7CAN_F4R2_FB18 ((uint32_t)0x00040000) ä7CAN_F4R2_FB19 ((uint32_t)0x00080000) å7CAN_F4R2_FB20 ((uint32_t)0x00100000) æ7CAN_F4R2_FB21 ((uint32_t)0x00200000) ç7CAN_F4R2_FB22 ((uint32_t)0x00400000) è7CAN_F4R2_FB23 ((uint32_t)0x00800000) é7CAN_F4R2_FB24 ((uint32_t)0x01000000) ê7CAN_F4R2_FB25 ((uint32_t)0x02000000) ë7CAN_F4R2_FB26 ((uint32_t)0x04000000) ì7CAN_F4R2_FB27 ((uint32_t)0x08000000) í7CAN_F4R2_FB28 ((uint32_t)0x10000000) î7CAN_F4R2_FB29 ((uint32_t)0x20000000) ï7CAN_F4R2_FB30 ((uint32_t)0x40000000) ð7CAN_F4R2_FB31 ((uint32_t)0x80000000) ó7CAN_F5R2_FB0 ((uint32_t)0x00000001) ô7CAN_F5R2_FB1 ((uint32_t)0x00000002) õ7CAN_F5R2_FB2 ((uint32_t)0x00000004) ö7CAN_F5R2_FB3 ((uint32_t)0x00000008) ÷7CAN_F5R2_FB4 ((uint32_t)0x00000010) ø7CAN_F5R2_FB5 ((uint32_t)0x00000020) ù7CAN_F5R2_FB6 ((uint32_t)0x00000040) ú7CAN_F5R2_FB7 ((uint32_t)0x00000080) û7CAN_F5R2_FB8 ((uint32_t)0x00000100) ü7CAN_F5R2_FB9 ((uint32_t)0x00000200) ý7CAN_F5R2_FB10 ((uint32_t)0x00000400) þ7CAN_F5R2_FB11 ((uint32_t)0x00000800) ÿ7CAN_F5R2_FB12 ((uint32_t)0x00001000) 8CAN_F5R2_FB13 ((uint32_t)0x00002000) 8CAN_F5R2_FB14 ((uint32_t)0x00004000) 8CAN_F5R2_FB15 ((uint32_t)0x00008000) 8CAN_F5R2_FB16 ((uint32_t)0x00010000) 8CAN_F5R2_FB17 ((uint32_t)0x00020000)
8CAN_F5R2_FB18 ((uint32_t)0x00040000) 8CAN_F5R2_FB19 ((uint32_t)0x00080000) 8CAN_F5R2_FB20 ((uint32_t)0x00100000) 8CAN_F5R2_FB21 ((uint32_t)0x00200000) 8CAN_F5R2_FB22 ((uint32_t)0x00400000) 8CAN_F5R2_FB23 ((uint32_t)0x00800000) 8CAN_F5R2_FB24 ((uint32_t)0x01000000) 8CAN_F5R2_FB25 ((uint32_t)0x02000000) 8CAN_F5R2_FB26 ((uint32_t)0x04000000) 8CAN_F5R2_FB27 ((uint32_t)0x08000000) 8CAN_F5R2_FB28 ((uint32_t)0x10000000) 8CAN_F5R2_FB29 ((uint32_t)0x20000000) 8CAN_F5R2_FB30 ((uint32_t)0x40000000) 8CAN_F5R2_FB31 ((uint32_t)0x80000000) 8CAN_F6R2_FB0 ((uint32_t)0x00000001) 8CAN_F6R2_FB1 ((uint32_t)0x00000002) 8CAN_F6R2_FB2 ((uint32_t)0x00000004) 8CAN_F6R2_FB3 ((uint32_t)0x00000008) 8CAN_F6R2_FB4 ((uint32_t)0x00000010) 8CAN_F6R2_FB5 ((uint32_t)0x00000020) 8CAN_F6R2_FB6 ((uint32_t)0x00000040) 8CAN_F6R2_FB7 ((uint32_t)0x00000080) 8CAN_F6R2_FB8 ((uint32_t)0x00000100) 8CAN_F6R2_FB9 ((uint32_t)0x00000200) 8CAN_F6R2_FB10 ((uint32_t)0x00000400) 8CAN_F6R2_FB11 ((uint32_t)0x00000800) ¡8CAN_F6R2_FB12 ((uint32_t)0x00001000) ¢8CAN_F6R2_FB13 ((uint32_t)0x00002000) £8CAN_F6R2_FB14 ((uint32_t)0x00004000) ¤8CAN_F6R2_FB15 ((uint32_t)0x00008000) ¥8CAN_F6R2_FB16 ((uint32_t)0x00010000) ¦8CAN_F6R2_FB17 ((uint32_t)0x00020000) §8CAN_F6R2_FB18 ((uint32_t)0x00040000) ¨8CAN_F6R2_FB19 ((uint32_t)0x00080000) ©8CAN_F6R2_FB20 ((uint32_t)0x00100000) ª8CAN_F6R2_FB21 ((uint32_t)0x00200000) «8CAN_F6R2_FB22 ((uint32_t)0x00400000) ¬8CAN_F6R2_FB23 ((uint32_t)0x00800000) 8CAN_F6R2_FB24 ((uint32_t)0x01000000) ®8CAN_F6R2_FB25 ((uint32_t)0x02000000) ¯8CAN_F6R2_FB26 ((uint32_t)0x04000000) °8CAN_F6R2_FB27 ((uint32_t)0x08000000) ±8CAN_F6R2_FB28 ((uint32_t)0x10000000) ²8CAN_F6R2_FB29 ((uint32_t)0x20000000) ³8CAN_F6R2_FB30 ((uint32_t)0x40000000) ´8CAN_F6R2_FB31 ((uint32_t)0x80000000) ·8CAN_F7R2_FB0 ((uint32_t)0x00000001) ¸8CAN_F7R2_FB1 ((uint32_t)0x00000002) ¹8CAN_F7R2_FB2 ((uint32_t)0x00000004) º8CAN_F7R2_FB3 ((uint32_t)0x00000008) »8CAN_F7R2_FB4 ((uint32_t)0x00000010) ¼8CAN_F7R2_FB5 ((uint32_t)0x00000020) ½8CAN_F7R2_FB6 ((uint32_t)0x00000040) ¾8CAN_F7R2_FB7 ((uint32_t)0x00000080) ¿8CAN_F7R2_FB8 ((uint32_t)0x00000100) À8CAN_F7R2_FB9 ((uint32_t)0x00000200) Á8CAN_F7R2_FB10 ((uint32_t)0x00000400) Â8CAN_F7R2_FB11 ((uint32_t)0x00000800) Ã8CAN_F7R2_FB12 ((uint32_t)0x00001000) Ä8CAN_F7R2_FB13 ((uint32_t)0x00002000) Å8CAN_F7R2_FB14 ((uint32_t)0x00004000) Æ8CAN_F7R2_FB15 ((uint32_t)0x00008000) Ç8CAN_F7R2_FB16 ((uint32_t)0x00010000) È8CAN_F7R2_FB17 ((uint32_t)0x00020000) É8CAN_F7R2_FB18 ((uint32_t)0x00040000) Ê8CAN_F7R2_FB19 ((uint32_t)0x00080000) Ë8CAN_F7R2_FB20 ((uint32_t)0x00100000) Ì8CAN_F7R2_FB21 ((uint32_t)0x00200000) Í8CAN_F7R2_FB22 ((uint32_t)0x00400000) Î8CAN_F7R2_FB23 ((uint32_t)0x00800000) Ï8CAN_F7R2_FB24 ((uint32_t)0x01000000) Ð8CAN_F7R2_FB25 ((uint32_t)0x02000000) Ñ8CAN_F7R2_FB26 ((uint32_t)0x04000000) Ò8CAN_F7R2_FB27 ((uint32_t)0x08000000) Ó8CAN_F7R2_FB28 ((uint32_t)0x10000000) Ô8CAN_F7R2_FB29 ((uint32_t)0x20000000) Õ8CAN_F7R2_FB30 ((uint32_t)0x40000000) Ö8CAN_F7R2_FB31 ((uint32_t)0x80000000) Ù8CAN_F8R2_FB0 ((uint32_t)0x00000001) Ú8CAN_F8R2_FB1 ((uint32_t)0x00000002) Û8CAN_F8R2_FB2 ((uint32_t)0x00000004) Ü8CAN_F8R2_FB3 ((uint32_t)0x00000008) Ý8CAN_F8R2_FB4 ((uint32_t)0x00000010) Þ8CAN_F8R2_FB5 ((uint32_t)0x00000020) ß8CAN_F8R2_FB6 ((uint32_t)0x00000040) à8CAN_F8R2_FB7 ((uint32_t)0x00000080) á8CAN_F8R2_FB8 ((uint32_t)0x00000100) â8CAN_F8R2_FB9 ((uint32_t)0x00000200) ã8CAN_F8R2_FB10 ((uint32_t)0x00000400) ä8CAN_F8R2_FB11 ((uint32_t)0x00000800) å8CAN_F8R2_FB12 ((uint32_t)0x00001000) æ8CAN_F8R2_FB13 ((uint32_t)0x00002000) ç8CAN_F8R2_FB14 ((uint32_t)0x00004000) è8CAN_F8R2_FB15 ((uint32_t)0x00008000) é8CAN_F8R2_FB16 ((uint32_t)0x00010000) ê8CAN_F8R2_FB17 ((uint32_t)0x00020000) ë8CAN_F8R2_FB18 ((uint32_t)0x00040000) ì8CAN_F8R2_FB19 ((uint32_t)0x00080000) í8CAN_F8R2_FB20 ((uint32_t)0x00100000) î8CAN_F8R2_FB21 ((uint32_t)0x00200000) ï8CAN_F8R2_FB22 ((uint32_t)0x00400000) ð8CAN_F8R2_FB23 ((uint32_t)0x00800000) ñ8CAN_F8R2_FB24 ((uint32_t)0x01000000) ò8CAN_F8R2_FB25 ((uint32_t)0x02000000) ó8CAN_F8R2_FB26 ((uint32_t)0x04000000) ô8CAN_F8R2_FB27 ((uint32_t)0x08000000) õ8CAN_F8R2_FB28 ((uint32_t)0x10000000) ö8CAN_F8R2_FB29 ((uint32_t)0x20000000) ÷8CAN_F8R2_FB30 ((uint32_t)0x40000000) ø8CAN_F8R2_FB31 ((uint32_t)0x80000000) û8CAN_F9R2_FB0 ((uint32_t)0x00000001) ü8CAN_F9R2_FB1 ((uint32_t)0x00000002) ý8CAN_F9R2_FB2 ((uint32_t)0x00000004) þ8CAN_F9R2_FB3 ((uint32_t)0x00000008) ÿ8CAN_F9R2_FB4 ((uint32_t)0x00000010) 9CAN_F9R2_FB5 ((uint32_t)0x00000020) 9CAN_F9R2_FB6 ((uint32_t)0x00000040) 9CAN_F9R2_FB7 ((uint32_t)0x00000080) 9CAN_F9R2_FB8 ((uint32_t)0x00000100) 9CAN_F9R2_FB9 ((uint32_t)0x00000200)
9CAN_F9R2_FB10 ((uint32_t)0x00000400) 9CAN_F9R2_FB11 ((uint32_t)0x00000800) 9CAN_F9R2_FB12 ((uint32_t)0x00001000) 9CAN_F9R2_FB13 ((uint32_t)0x00002000) 9CAN_F9R2_FB14 ((uint32_t)0x00004000) 9CAN_F9R2_FB15 ((uint32_t)0x00008000) 9CAN_F9R2_FB16 ((uint32_t)0x00010000) 9CAN_F9R2_FB17 ((uint32_t)0x00020000) 9CAN_F9R2_FB18 ((uint32_t)0x00040000) 9CAN_F9R2_FB19 ((uint32_t)0x00080000) 9CAN_F9R2_FB20 ((uint32_t)0x00100000) 9CAN_F9R2_FB21 ((uint32_t)0x00200000) 9CAN_F9R2_FB22 ((uint32_t)0x00400000) 9CAN_F9R2_FB23 ((uint32_t)0x00800000) 9CAN_F9R2_FB24 ((uint32_t)0x01000000) 9CAN_F9R2_FB25 ((uint32_t)0x02000000) 9CAN_F9R2_FB26 ((uint32_t)0x04000000) 9CAN_F9R2_FB27 ((uint32_t)0x08000000) 9CAN_F9R2_FB28 ((uint32_t)0x10000000) 9CAN_F9R2_FB29 ((uint32_t)0x20000000) 9CAN_F9R2_FB30 ((uint32_t)0x40000000) 9CAN_F9R2_FB31 ((uint32_t)0x80000000) 9CAN_F10R2_FB0 ((uint32_t)0x00000001) 9CAN_F10R2_FB1 ((uint32_t)0x00000002) 9CAN_F10R2_FB2 ((uint32_t)0x00000004) 9CAN_F10R2_FB3 ((uint32_t)0x00000008) ¡9CAN_F10R2_FB4 ((uint32_t)0x00000010) ¢9CAN_F10R2_FB5 ((uint32_t)0x00000020) £9CAN_F10R2_FB6 ((uint32_t)0x00000040) ¤9CAN_F10R2_FB7 ((uint32_t)0x00000080) ¥9CAN_F10R2_FB8 ((uint32_t)0x00000100) ¦9CAN_F10R2_FB9 ((uint32_t)0x00000200) §9CAN_F10R2_FB10 ((uint32_t)0x00000400) ¨9CAN_F10R2_FB11 ((uint32_t)0x00000800) ©9CAN_F10R2_FB12 ((uint32_t)0x00001000) ª9CAN_F10R2_FB13 ((uint32_t)0x00002000) «9CAN_F10R2_FB14 ((uint32_t)0x00004000) ¬9CAN_F10R2_FB15 ((uint32_t)0x00008000) 9CAN_F10R2_FB16 ((uint32_t)0x00010000) ®9CAN_F10R2_FB17 ((uint32_t)0x00020000) ¯9CAN_F10R2_FB18 ((uint32_t)0x00040000) °9CAN_F10R2_FB19 ((uint32_t)0x00080000) ±9CAN_F10R2_FB20 ((uint32_t)0x00100000) ²9CAN_F10R2_FB21 ((uint32_t)0x00200000) ³9CAN_F10R2_FB22 ((uint32_t)0x00400000) ´9CAN_F10R2_FB23 ((uint32_t)0x00800000) µ9CAN_F10R2_FB24 ((uint32_t)0x01000000) ¶9CAN_F10R2_FB25 ((uint32_t)0x02000000) ·9CAN_F10R2_FB26 ((uint32_t)0x04000000) ¸9CAN_F10R2_FB27 ((uint32_t)0x08000000) ¹9CAN_F10R2_FB28 ((uint32_t)0x10000000) º9CAN_F10R2_FB29 ((uint32_t)0x20000000) »9CAN_F10R2_FB30 ((uint32_t)0x40000000) ¼9CAN_F10R2_FB31 ((uint32_t)0x80000000) ¿9CAN_F11R2_FB0 ((uint32_t)0x00000001) À9CAN_F11R2_FB1 ((uint32_t)0x00000002) Á9CAN_F11R2_FB2 ((uint32_t)0x00000004) Â9CAN_F11R2_FB3 ((uint32_t)0x00000008) Ã9CAN_F11R2_FB4 ((uint32_t)0x00000010) Ä9CAN_F11R2_FB5 ((uint32_t)0x00000020) Å9CAN_F11R2_FB6 ((uint32_t)0x00000040) Æ9CAN_F11R2_FB7 ((uint32_t)0x00000080) Ç9CAN_F11R2_FB8 ((uint32_t)0x00000100) È9CAN_F11R2_FB9 ((uint32_t)0x00000200) É9CAN_F11R2_FB10 ((uint32_t)0x00000400) Ê9CAN_F11R2_FB11 ((uint32_t)0x00000800) Ë9CAN_F11R2_FB12 ((uint32_t)0x00001000) Ì9CAN_F11R2_FB13 ((uint32_t)0x00002000) Í9CAN_F11R2_FB14 ((uint32_t)0x00004000) Î9CAN_F11R2_FB15 ((uint32_t)0x00008000) Ï9CAN_F11R2_FB16 ((uint32_t)0x00010000) Ð9CAN_F11R2_FB17 ((uint32_t)0x00020000) Ñ9CAN_F11R2_FB18 ((uint32_t)0x00040000) Ò9CAN_F11R2_FB19 ((uint32_t)0x00080000) Ó9CAN_F11R2_FB20 ((uint32_t)0x00100000) Ô9CAN_F11R2_FB21 ((uint32_t)0x00200000) Õ9CAN_F11R2_FB22 ((uint32_t)0x00400000) Ö9CAN_F11R2_FB23 ((uint32_t)0x00800000) ×9CAN_F11R2_FB24 ((uint32_t)0x01000000) Ø9CAN_F11R2_FB25 ((uint32_t)0x02000000) Ù9CAN_F11R2_FB26 ((uint32_t)0x04000000) Ú9CAN_F11R2_FB27 ((uint32_t)0x08000000) Û9CAN_F11R2_FB28 ((uint32_t)0x10000000) Ü9CAN_F11R2_FB29 ((uint32_t)0x20000000) Ý9CAN_F11R2_FB30 ((uint32_t)0x40000000) Þ9CAN_F11R2_FB31 ((uint32_t)0x80000000) á9CAN_F12R2_FB0 ((uint32_t)0x00000001) â9CAN_F12R2_FB1 ((uint32_t)0x00000002) ã9CAN_F12R2_FB2 ((uint32_t)0x00000004) ä9CAN_F12R2_FB3 ((uint32_t)0x00000008) å9CAN_F12R2_FB4 ((uint32_t)0x00000010) æ9CAN_F12R2_FB5 ((uint32_t)0x00000020) ç9CAN_F12R2_FB6 ((uint32_t)0x00000040) è9CAN_F12R2_FB7 ((uint32_t)0x00000080) é9CAN_F12R2_FB8 ((uint32_t)0x00000100) ê9CAN_F12R2_FB9 ((uint32_t)0x00000200) ë9CAN_F12R2_FB10 ((uint32_t)0x00000400) ì9CAN_F12R2_FB11 ((uint32_t)0x00000800) í9CAN_F12R2_FB12 ((uint32_t)0x00001000) î9CAN_F12R2_FB13 ((uint32_t)0x00002000) ï9CAN_F12R2_FB14 ((uint32_t)0x00004000) ð9CAN_F12R2_FB15 ((uint32_t)0x00008000) ñ9CAN_F12R2_FB16 ((uint32_t)0x00010000) ò9CAN_F12R2_FB17 ((uint32_t)0x00020000) ó9CAN_F12R2_FB18 ((uint32_t)0x00040000) ô9CAN_F12R2_FB19 ((uint32_t)0x00080000) õ9CAN_F12R2_FB20 ((uint32_t)0x00100000) ö9CAN_F12R2_FB21 ((uint32_t)0x00200000) ÷9CAN_F12R2_FB22 ((uint32_t)0x00400000) ø9CAN_F12R2_FB23 ((uint32_t)0x00800000) ù9CAN_F12R2_FB24 ((uint32_t)0x01000000) ú9CAN_F12R2_FB25 ((uint32_t)0x02000000) û9CAN_F12R2_FB26 ((uint32_t)0x04000000) ü9CAN_F12R2_FB27 ((uint32_t)0x08000000) ý9CAN_F12R2_FB28 ((uint32_t)0x10000000) þ9CAN_F12R2_FB29 ((uint32_t)0x20000000) ÿ9CAN_F12R2_FB30 ((uint32_t)0x40000000) :CAN_F12R2_FB31 ((uint32_t)0x80000000) :CAN_F13R2_FB0 ((uint32_t)0x00000001) :CAN_F13R2_FB1 ((uint32_t)0x00000002)
:CAN_F13R2_FB2 ((uint32_t)0x00000004) :CAN_F13R2_FB3 ((uint32_t)0x00000008) :CAN_F13R2_FB4 ((uint32_t)0x00000010) :CAN_F13R2_FB5 ((uint32_t)0x00000020) :CAN_F13R2_FB6 ((uint32_t)0x00000040) :CAN_F13R2_FB7 ((uint32_t)0x00000080) :CAN_F13R2_FB8 ((uint32_t)0x00000100) :CAN_F13R2_FB9 ((uint32_t)0x00000200) :CAN_F13R2_FB10 ((uint32_t)0x00000400) :CAN_F13R2_FB11 ((uint32_t)0x00000800) :CAN_F13R2_FB12 ((uint32_t)0x00001000) :CAN_F13R2_FB13 ((uint32_t)0x00002000) :CAN_F13R2_FB14 ((uint32_t)0x00004000) :CAN_F13R2_FB15 ((uint32_t)0x00008000) :CAN_F13R2_FB16 ((uint32_t)0x00010000) :CAN_F13R2_FB17 ((uint32_t)0x00020000) :CAN_F13R2_FB18 ((uint32_t)0x00040000) :CAN_F13R2_FB19 ((uint32_t)0x00080000) :CAN_F13R2_FB20 ((uint32_t)0x00100000) :CAN_F13R2_FB21 ((uint32_t)0x00200000) :CAN_F13R2_FB22 ((uint32_t)0x00400000) :CAN_F13R2_FB23 ((uint32_t)0x00800000) :CAN_F13R2_FB24 ((uint32_t)0x01000000) :CAN_F13R2_FB25 ((uint32_t)0x02000000) :CAN_F13R2_FB26 ((uint32_t)0x04000000) :CAN_F13R2_FB27 ((uint32_t)0x08000000) :CAN_F13R2_FB28 ((uint32_t)0x10000000) :CAN_F13R2_FB29 ((uint32_t)0x20000000) ¡:CAN_F13R2_FB30 ((uint32_t)0x40000000) ¢:CAN_F13R2_FB31 ((uint32_t)0x80000000) «:SPI_CR1_CPHA ((uint16_t)0x0001) ¬:SPI_CR1_CPOL ((uint16_t)0x0002) :SPI_CR1_MSTR ((uint16_t)0x0004) ¯:SPI_CR1_BR ((uint16_t)0x0038) °:SPI_CR1_BR_0 ((uint16_t)0x0008) ±:SPI_CR1_BR_1 ((uint16_t)0x0010) ²:SPI_CR1_BR_2 ((uint16_t)0x0020) ´:SPI_CR1_SPE ((uint16_t)0x0040) µ:SPI_CR1_LSBFIRST ((uint16_t)0x0080) ¶:SPI_CR1_SSI ((uint16_t)0x0100) ·:SPI_CR1_SSM ((uint16_t)0x0200) ¸:SPI_CR1_RXONLY ((uint16_t)0x0400) ¹:SPI_CR1_DFF ((uint16_t)0x0800) º:SPI_CR1_CRCNEXT ((uint16_t)0x1000) »:SPI_CR1_CRCEN ((uint16_t)0x2000) ¼:SPI_CR1_BIDIOE ((uint16_t)0x4000) ½:SPI_CR1_BIDIMODE ((uint16_t)0x8000) À:SPI_CR2_RXDMAEN ((uint8_t)0x01) Á:SPI_CR2_TXDMAEN ((uint8_t)0x02) Â:SPI_CR2_SSOE ((uint8_t)0x04) Ã:SPI_CR2_ERRIE ((uint8_t)0x20) Ä:SPI_CR2_RXNEIE ((uint8_t)0x40) Å:SPI_CR2_TXEIE ((uint8_t)0x80) È:SPI_SR_RXNE ((uint8_t)0x01) É:SPI_SR_TXE ((uint8_t)0x02) Ê:SPI_SR_CHSIDE ((uint8_t)0x04) Ë:SPI_SR_UDR ((uint8_t)0x08) Ì:SPI_SR_CRCERR ((uint8_t)0x10) Í:SPI_SR_MODF ((uint8_t)0x20) Î:SPI_SR_OVR ((uint8_t)0x40) Ï:SPI_SR_BSY ((uint8_t)0x80) Ò:SPI_DR_DR ((uint16_t)0xFFFF) Õ:SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) Ø:SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) Û:SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) Þ:SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) à:SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) á:SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) â:SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) ä:SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) æ:SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) ç:SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) è:SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) ê:SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) ì:SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) í:SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) î:SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) ð:SPI_I2SCFGR_I2SE ((uint16_t)0x0400) ñ:SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) ô:SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) õ:SPI_I2SPR_ODD ((uint16_t)0x0100) ö:SPI_I2SPR_MCKOE ((uint16_t)0x0200) ÿ:I2C_CR1_PE ((uint16_t)0x0001) ;I2C_CR1_SMBUS ((uint16_t)0x0002) ;I2C_CR1_SMBTYPE ((uint16_t)0x0008) ;I2C_CR1_ENARP ((uint16_t)0x0010) ;I2C_CR1_ENPEC ((uint16_t)0x0020) ;I2C_CR1_ENGC ((uint16_t)0x0040)
;I2C_CR1_NOSTRETCH ((uint16_t)0x0080) ;I2C_CR1_START ((uint16_t)0x0100) ;I2C_CR1_STOP ((uint16_t)0x0200) ;I2C_CR1_ACK ((uint16_t)0x0400) ;I2C_CR1_POS ((uint16_t)0x0800) ;I2C_CR1_PEC ((uint16_t)0x1000) ;I2C_CR1_ALERT ((uint16_t)0x2000) ;I2C_CR1_SWRST ((uint16_t)0x8000) ;I2C_CR2_FREQ ((uint16_t)0x003F) ;I2C_CR2_FREQ_0 ((uint16_t)0x0001) ;I2C_CR2_FREQ_1 ((uint16_t)0x0002) ;I2C_CR2_FREQ_2 ((uint16_t)0x0004) ;I2C_CR2_FREQ_3 ((uint16_t)0x0008) ;I2C_CR2_FREQ_4 ((uint16_t)0x0010) ;I2C_CR2_FREQ_5 ((uint16_t)0x0020) ;I2C_CR2_ITERREN ((uint16_t)0x0100) ;I2C_CR2_ITEVTEN ((uint16_t)0x0200) ;I2C_CR2_ITBUFEN ((uint16_t)0x0400) ;I2C_CR2_DMAEN ((uint16_t)0x0800) ;I2C_CR2_LAST ((uint16_t)0x1000) ;I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) ;I2C_OAR1_ADD8_9 ((uint16_t)0x0300) ¡;I2C_OAR1_ADD0 ((uint16_t)0x0001) ¢;I2C_OAR1_ADD1 ((uint16_t)0x0002) £;I2C_OAR1_ADD2 ((uint16_t)0x0004) ¤;I2C_OAR1_ADD3 ((uint16_t)0x0008) ¥;I2C_OAR1_ADD4 ((uint16_t)0x0010) ¦;I2C_OAR1_ADD5 ((uint16_t)0x0020) §;I2C_OAR1_ADD6 ((uint16_t)0x0040) ¨;I2C_OAR1_ADD7 ((uint16_t)0x0080) ©;I2C_OAR1_ADD8 ((uint16_t)0x0100) ª;I2C_OAR1_ADD9 ((uint16_t)0x0200) ¬;I2C_OAR1_ADDMODE ((uint16_t)0x8000) ¯;I2C_OAR2_ENDUAL ((uint8_t)0x01) °;I2C_OAR2_ADD2 ((uint8_t)0xFE) ³;I2C_DR_DR ((uint8_t)0xFF) ¶;I2C_SR1_SB ((uint16_t)0x0001) ·;I2C_SR1_ADDR ((uint16_t)0x0002) ¸;I2C_SR1_BTF ((uint16_t)0x0004) ¹;I2C_SR1_ADD10 ((uint16_t)0x0008) º;I2C_SR1_STOPF ((uint16_t)0x0010) »;I2C_SR1_RXNE ((uint16_t)0x0040) ¼;I2C_SR1_TXE ((uint16_t)0x0080) ½;I2C_SR1_BERR ((uint16_t)0x0100) ¾;I2C_SR1_ARLO ((uint16_t)0x0200) ¿;I2C_SR1_AF ((uint16_t)0x0400) À;I2C_SR1_OVR ((uint16_t)0x0800) Á;I2C_SR1_PECERR ((uint16_t)0x1000) Â;I2C_SR1_TIMEOUT ((uint16_t)0x4000) Ã;I2C_SR1_SMBALERT ((uint16_t)0x8000) Æ;I2C_SR2_MSL ((uint16_t)0x0001) Ç;I2C_SR2_BUSY ((uint16_t)0x0002) È;I2C_SR2_TRA ((uint16_t)0x0004) É;I2C_SR2_GENCALL ((uint16_t)0x0010) Ê;I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) Ë;I2C_SR2_SMBHOST ((uint16_t)0x0040) Ì;I2C_SR2_DUALF ((uint16_t)0x0080) Í;I2C_SR2_PEC ((uint16_t)0xFF00) Ð;I2C_CCR_CCR ((uint16_t)0x0FFF) Ñ;I2C_CCR_DUTY ((uint16_t)0x4000) Ò;I2C_CCR_FS ((uint16_t)0x8000) Õ;I2C_TRISE_TRISE ((uint8_t)0x3F) Þ;USART_SR_PE ((uint16_t)0x0001) ß;USART_SR_FE ((uint16_t)0x0002) à;USART_SR_NE ((uint16_t)0x0004) á;USART_SR_ORE ((uint16_t)0x0008) â;USART_SR_IDLE ((uint16_t)0x0010) ã;USART_SR_RXNE ((uint16_t)0x0020) ä;USART_SR_TC ((uint16_t)0x0040) å;USART_SR_TXE ((uint16_t)0x0080) æ;USART_SR_LBD ((uint16_t)0x0100) ç;USART_SR_CTS ((uint16_t)0x0200) ê;USART_DR_DR ((uint16_t)0x01FF) í;USART_BRR_DIV_Fraction ((uint16_t)0x000F) î;USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) ñ;USART_CR1_SBK ((uint16_t)0x0001) ò;USART_CR1_RWU ((uint16_t)0x0002) ó;USART_CR1_RE ((uint16_t)0x0004) ô;USART_CR1_TE ((uint16_t)0x0008) õ;USART_CR1_IDLEIE ((uint16_t)0x0010) ö;USART_CR1_RXNEIE ((uint16_t)0x0020) ÷;USART_CR1_TCIE ((uint16_t)0x0040) ø;USART_CR1_TXEIE ((uint16_t)0x0080) ù;USART_CR1_PEIE ((uint16_t)0x0100) ú;USART_CR1_PS ((uint16_t)0x0200) û;USART_CR1_PCE ((uint16_t)0x0400) ü;USART_CR1_WAKE ((uint16_t)0x0800) ý;USART_CR1_M ((uint16_t)0x1000) þ;USART_CR1_UE ((uint16_t)0x2000) ÿ;USART_CR1_OVER8 ((uint16_t)0x8000) <USART_CR2_ADD ((uint16_t)0x000F) <USART_CR2_LBDL ((uint16_t)0x0020) <USART_CR2_LBDIE ((uint16_t)0x0040)
<USART_CR2_LBCL ((uint16_t)0x0100) <USART_CR2_CPHA ((uint16_t)0x0200) <USART_CR2_CPOL ((uint16_t)0x0400) <USART_CR2_CLKEN ((uint16_t)0x0800) <USART_CR2_STOP ((uint16_t)0x3000) <USART_CR2_STOP_0 ((uint16_t)0x1000) <USART_CR2_STOP_1 ((uint16_t)0x2000) <USART_CR2_LINEN ((uint16_t)0x4000) <USART_CR3_EIE ((uint16_t)0x0001) <USART_CR3_IREN ((uint16_t)0x0002) <USART_CR3_IRLP ((uint16_t)0x0004) <USART_CR3_HDSEL ((uint16_t)0x0008) <USART_CR3_NACK ((uint16_t)0x0010) <USART_CR3_SCEN ((uint16_t)0x0020) <USART_CR3_DMAR ((uint16_t)0x0040) <USART_CR3_DMAT ((uint16_t)0x0080) <USART_CR3_RTSE ((uint16_t)0x0100) <USART_CR3_CTSE ((uint16_t)0x0200) <USART_CR3_CTSIE ((uint16_t)0x0400) <USART_CR3_ONEBIT ((uint16_t)0x0800) <USART_GTPR_PSC ((uint16_t)0x00FF) <USART_GTPR_PSC_0 ((uint16_t)0x0001) ¡<USART_GTPR_PSC_1 ((uint16_t)0x0002) ¢<USART_GTPR_PSC_2 ((uint16_t)0x0004) £<USART_GTPR_PSC_3 ((uint16_t)0x0008) ¤<USART_GTPR_PSC_4 ((uint16_t)0x0010) ¥<USART_GTPR_PSC_5 ((uint16_t)0x0020) ¦<USART_GTPR_PSC_6 ((uint16_t)0x0040) §<USART_GTPR_PSC_7 ((uint16_t)0x0080) ©<USART_GTPR_GT ((uint16_t)0xFF00) ²<DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) ´<DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) µ<DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) ¶<DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) ·<DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) ¸<DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) ¹<DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) º<DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) »<DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) ¼<DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) ½<DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) ¾<DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) ¿<DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) À<DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) Á<DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) Â<DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) Ã<DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) Ä<DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) Ç<DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) È<DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) É<DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) Ê<DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) Ì<DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) Í<DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) Î<DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) Ð<DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100) Ñ<DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200) Ò<DBGMCU_CR_DBG_TIM1_STOP ((uint32_t)0x00000400) Ó<DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800) Ô<DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000) Õ<DBGMCU_CR_DBG_TIM4_STOP ((uint32_t)0x00002000) Ö<DBGMCU_CR_DBG_CAN1_STOP ((uint32_t)0x00004000) ×<DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) Ø<DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) Ù<DBGMCU_CR_DBG_TIM8_STOP ((uint32_t)0x00020000) Ú<DBGMCU_CR_DBG_TIM5_STOP ((uint32_t)0x00040000) Û<DBGMCU_CR_DBG_TIM6_STOP ((uint32_t)0x00080000) Ü<DBGMCU_CR_DBG_TIM7_STOP ((uint32_t)0x00100000) Ý<DBGMCU_CR_DBG_CAN2_STOP ((uint32_t)0x00200000) Þ<DBGMCU_CR_DBG_TIM15_STOP ((uint32_t)0x00400000) ß<DBGMCU_CR_DBG_TIM16_STOP ((uint32_t)0x00800000) à<DBGMCU_CR_DBG_TIM17_STOP ((uint32_t)0x01000000) á<DBGMCU_CR_DBG_TIM12_STOP ((uint32_t)0x02000000) â<DBGMCU_CR_DBG_TIM13_STOP ((uint32_t)0x04000000) ã<DBGMCU_CR_DBG_TIM14_STOP ((uint32_t)0x08000000) ä<DBGMCU_CR_DBG_TIM9_STOP ((uint32_t)0x10000000) å<DBGMCU_CR_DBG_TIM10_STOP ((uint32_t)0x20000000) æ<DBGMCU_CR_DBG_TIM11_STOP ((uint32_t)0x40000000) ï<FLASH_ACR_LATENCY ((uint8_t)0x03) ð<FLASH_ACR_LATENCY_0 ((uint8_t)0x00) ñ<FLASH_ACR_LATENCY_1 ((uint8_t)0x01) ò<FLASH_ACR_LATENCY_2 ((uint8_t)0x02) ô<FLASH_ACR_HLFCYA ((uint8_t)0x08) õ<FLASH_ACR_PRFTBE ((uint8_t)0x10) ö<FLASH_ACR_PRFTBS ((uint8_t)0x20) ù<FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) ü<FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) ÿ<FLASH_SR_BSY ((uint8_t)0x01) =FLASH_SR_PGERR ((uint8_t)0x04) =FLASH_SR_WRPRTERR ((uint8_t)0x10) =FLASH_SR_EOP ((uint8_t)0x20)
=FLASH_CR_PG ((uint16_t)0x0001) =FLASH_CR_PER ((uint16_t)0x0002) =FLASH_CR_MER ((uint16_t)0x0004) =FLASH_CR_OPTPG ((uint16_t)0x0010) =FLASH_CR_OPTER ((uint16_t)0x0020) =FLASH_CR_STRT ((uint16_t)0x0040) =FLASH_CR_LOCK ((uint16_t)0x0080) =FLASH_CR_OPTWRE ((uint16_t)0x0200) =FLASH_CR_ERRIE ((uint16_t)0x0400) =FLASH_CR_EOPIE ((uint16_t)0x1000) =FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) =FLASH_OBR_OPTERR ((uint16_t)0x0001) =FLASH_OBR_RDPRT ((uint16_t)0x0002) =FLASH_OBR_USER ((uint16_t)0x03FC) =FLASH_OBR_WDG_SW ((uint16_t)0x0004) =FLASH_OBR_nRST_STOP ((uint16_t)0x0008) =FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) =FLASH_OBR_BFB2 ((uint16_t)0x0020) =FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) £=FLASH_RDP_RDP ((uint32_t)0x000000FF) ¤=FLASH_RDP_nRDP ((uint32_t)0x0000FF00) §=FLASH_USER_USER ((uint32_t)0x00FF0000) ¨=FLASH_USER_nUSER ((uint32_t)0xFF000000) «=FLASH_Data0_Data0 ((uint32_t)0x000000FF) ¬=FLASH_Data0_nData0 ((uint32_t)0x0000FF00) ¯=FLASH_Data1_Data1 ((uint32_t)0x00FF0000) °=FLASH_Data1_nData1 ((uint32_t)0xFF000000) ³=FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) ´=FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00) ·=FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) ¸=FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000) »=FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) ¼=FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00) ¿=FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) À=FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000) é@ð@SET_BIT(REG,BIT) ((REG) |= (BIT)) ò@CLEAR_BIT(REG,BIT) ((REG) &= ~(BIT)) ô@READ_BIT(REG,BIT) ((REG) & (BIT)) ö@CLEAR_REG(REG) ((REG) = (0x0)) ø@WRITE_REG(REG,VAL) ((REG) = (VAL)) ú@READ_REG(REG) ((REG)) ü@MODIFY_REG(REG,CLEARMASK,SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) __stdint_h __ARMCLIB_VERSION 5030024 __STDINT_DECLS __CLIBNS __CLIBNS \INT8_MIN -128 ]INT16_MIN -32768 ^INT32_MIN (~0x7fffffff) _INT64_MIN __ESCAPE__(~0x7fffffffffffffffll) bINT8_MAX 127 cINT16_MAX 32767 dINT32_MAX 2147483647 eINT64_MAX __ESCAPE__(9223372036854775807ll) hUINT8_MAX 255 iUINT16_MAX 65535 jUINT32_MAX 4294967295u kUINT64_MAX __ESCAPE__(18446744073709551615ull) pINT_LEAST8_MIN -128 qINT_LEAST16_MIN -32768 rINT_LEAST32_MIN (~0x7fffffff) sINT_LEAST64_MIN __ESCAPE__(~0x7fffffffffffffffll) vINT_LEAST8_MAX 127 wINT_LEAST16_MAX 32767 xINT_LEAST32_MAX 2147483647 yINT_LEAST64_MAX __ESCAPE__(9223372036854775807ll) |UINT_LEAST8_MAX 255 }UINT_LEAST16_MAX 65535 ~UINT_LEAST32_MAX 4294967295u UINT_LEAST64_MAX __ESCAPE__(18446744073709551615ull) INT_FAST8_MIN (~0x7fffffff)
INT_FAST16_MIN (~0x7fffffff) INT_FAST32_MIN (~0x7fffffff) INT_FAST64_MIN __ESCAPE__(~0x7fffffffffffffffll) INT_FAST8_MAX 2147483647 INT_FAST16_MAX 2147483647 INT_FAST32_MAX 2147483647 INT_FAST64_MAX __ESCAPE__(9223372036854775807ll) UINT_FAST8_MAX 4294967295u UINT_FAST16_MAX 4294967295u UINT_FAST32_MAX 4294967295u UINT_FAST64_MAX __ESCAPE__(18446744073709551615ull) INTPTR_MIN (~0x7fffffff) INTPTR_MAX 2147483647 UINTPTR_MAX 4294967295u £INTMAX_MIN __ESCAPE__(~0x7fffffffffffffffll) ¦INTMAX_MAX __ESCAPE__(9223372036854775807ll) ©UINTMAX_MAX __ESCAPE__(18446744073709551615ull) ®PTRDIFF_MIN (~0x7fffffff) ¯PTRDIFF_MAX 2147483647 ²SIG_ATOMIC_MIN (~0x7fffffff) ³SIG_ATOMIC_MAX 2147483647 ¶SIZE_MAX 4294967295u »WCHAR_MIN ¼WCHAR_MAX ÂWCHAR_MIN 0 ÃWCHAR_MAX 65535 ÇWINT_MIN (~0x7fffffff) ÈWINT_MAX 2147483647 ÏINT8_C(x) (x) ÐINT16_C(x) (x) ÑINT32_C(x) (x) ÒINT64_C(x) __ESCAPE__(x##ll) ÔUINT8_C(x) (x##u) ÕUINT16_C(x) (x##u) ÖUINT32_C(x) (x##u) ×UINT64_C(x) __ESCAPE__(x##ull) ÚINTMAX_C(x) __ESCAPE__(x##ll) ÛUINTMAX_C(x) __ESCAPE__(x##ull) ý t: 8 ADC_DeInit ¼ ADC_Init $ ADC_StructInit a ADC_Cmd ADC_DMACmd â ADC_ITConfig H ADC_ResetCalibration ADC_GetResetCalibrationStatus î ADC_StartCalibration ' ADC_GetCalibrationStatus ADC_SoftwareStartConvCmd ß ADC_GetSoftwareStartConvStatus M ADC_DiscModeChannelCountConfig à ADC_DiscModeCmd
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ADC_RegularChannelConfig © ADC_ExternalTrigConvCmd ø ADC_GetConversionValue K ADC_GetDualModeConversionValue ADC_AutoInjectedConvCmd æ ADC_InjectedDiscModeCmd 5 ADC_ExternalTrigInjectedConvConfig ° ADC_ExternalTrigInjectedConvCmd ADC_SoftwareStartInjectedConvCmd _ ADC_GetSoftwareStartInjectedConvCmdStatus Ø ADC_InjectedChannelConfig ADC_InjectedSequencerLengthConfig
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ADC_SetInjectedOffset v
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ADC_GetInjectedConversionValue ü
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ADC_AnalogWatchdogCmd c ADC_AnalogWatchdogThresholdsConfig Ù ADC_AnalogWatchdogSingleChannelConfig I ADC_TempSensorVrefintCmd ADC_GetFlagStatus þ ADC_ClearFlag C ADC_GetITStatus Ù ADC_ClearITPendingBit ò ¬H SPI_I2S_DeInit ¿ SPI_Init I2S_Init Ø SPI_StructInit I2S_StructInit R SPI_Cmd I2S_Cmd Ð SPI_I2S_ITConfig N SPI_I2S_DMACmd SPI_I2S_SendData ñ SPI_I2S_ReceiveData A SPI_NSSInternalSoftwareConfig ¡ SPI_SSOutputCmd è SPI_DataSizeConfig 6 SPI_TransmitCRC j SPI_CalculateCRC ² SPI_GetCRC SPI_GetCRCPolynomial l SPI_BiDirectionalLineConfig Ä SPI_I2S_GetFlagStatus @ SPI_I2S_ClearFlag SPI_I2S_GetITStatus : SPI_I2S_ClearITPendingBit LQ Ü
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USART_DeInit  USART_Init USART_StructInit Ó USART_ClockInit 9 USART_ClockStructInit USART_Cmd Ç USART_ITConfig k USART_DMACmd È USART_SetAddress USART_WakeUpConfig g USART_ReceiverWakeUpCmd ¸ USART_LINBreakDetectLengthConfig $ USART_LINCmd j USART_SendData ® USART_ReceiveData þ USART_SendBreak 4 USART_SetGuardTime USART_SetPrescaler Ú USART_SmartCardCmd & USART_SmartCardNACKCmd v USART_HalfDuplexCmd à USART_OverSampling8Cmd USART_OneBitMethodCmd b USART_IrDAConfig ² USART_IrDACmd ù USART_GetFlagStatus s USART_ClearFlag ¾ USART_GetITStatus f
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USART_ClearITPendingBit ¬ (\ ¸" TIM_DeInit » TIM_TimeBaseInit ! TIM_OC1Init TIM_OC2Init TIM_OC3Init TIM_OC4Init TIM_SetIC4Prescaler TIM_SetIC3Prescaler TIM_SetIC2Prescaler ø TIM_SetIC1Prescaler à TIM_ICInit * TIM_PWMIConfig ³ TIM_BDTRConfig TIM_TimeBaseStructInit P TIM_OCStructInit TIM_ICStructInit Ò TIM_BDTRStructInit TIM_Cmd V TIM_CtrlPWMOutputs TIM_ITConfig õ TIM_GenerateEvent E
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TIM_DMAConfig ª
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TIM_DMACmd TIM_InternalClockConfig @ TIM_SelectInputTrigger TIM_ITRxExternalClockConfig TIM_TIxExternalClockConfig TIM_ETRConfig 1 TIM_ETRClockMode1Config Ð TIM_ETRClockMode2Config ^ TIM_PrescalerConfig Æ TIM_CounterModeConfig * TIM_EncoderInterfaceConfig ë TIM_ForcedOC1Config P TIM_ForcedOC2Config µ TIM_ForcedOC3Config TIM_ForcedOC4Config TIM_ARRPreloadConfig Ë TIM_SelectCOM TIM_SelectCCDMA W TIM_CCPreloadControl £ TIM_OC1PreloadConfig TIM_OC2PreloadConfig i TIM_OC3PreloadConfig Ì TIM_OC4PreloadConfig / TIM_OC1FastConfig TIM_OC2FastConfig é TIM_OC3FastConfig F TIM_OC4FastConfig £ TIM_ClearOC1Ref ÿ TIM_ClearOC2Ref [ TIM_ClearOC3Ref · TIM_ClearOC4Ref TIM_OC1PolarityConfig w TIM_OC1NPolarityConfig Ý TIM_OC2PolarityConfig A TIM_OC2NPolarityConfig § TIM_OC3PolarityConfig TIM_OC3NPolarityConfig q TIM_OC4PolarityConfig Õ TIM_CCxCmd 9 TIM_CCxNCmd TIM_SelectOCxM TIM_UpdateDisableConfig i TIM_UpdateRequestConfig À TIM_SelectHallSensor TIM_SelectOnePulseMode \ TIM_SelectOutputTrigger ± TIM_SelectSlaveMode TIM_SelectMasterSlaveMode ] TIM_SetCounter ¢ TIM_SetAutoreload í TIM_SetCompare1 4 TIM_SetCompare2 { TIM_SetCompare3 Â TIM_SetCompare4 TIM_SetClockDivision T TIM_GetCapture1 TIM_GetCapture2 ì TIM_GetCapture3 8 TIM_GetCapture4 TIM_GetCounter Ï TIM_GetPrescaler ! TIM_GetFlagStatus ! TIM_ClearFlag Õ! TIM_GetITStatus i" TIM_ClearITPendingBit À à~ Ð RCC_DeInit RCC_HSEConfig â RCC_GetFlagStatus g RCC_WaitForHSEStartUp å RCC_AdjustHSICalibrationValue F RCC_HSICmd y RCC_PLLConfig Ù RCC_PLLCmd RCC_SYSCLKConfig ] RCC_GetSYSCLKSource RCC_HCLKConfig ç RCC_PCLK1Config / RCC_PCLK2Config w RCC_ITConfig ½ RCC_USBCLKConfig þ RCC_ADCCLKConfig H RCC_LSEConfig } RCC_LSICmd ° RCC_RTCCLKConfig ñ RCC_RTCCLKCmd ' RCC_GetClocksFreq £ RCC_AHBPeriphClockCmd ù RCC_APB2PeriphClockCmd Q RCC_APB1PeriphClockCmd © RCC_APB2PeriphResetCmd RCC_APB1PeriphResetCmd Y RCC_BackupResetCmd RCC_ClockSecuritySystemCmd × RCC_MCOConfig RCC_ClearFlag / RCC_GetITStatus RCC_ClearITPendingBit l è GPIO_DeInit ¾ GPIO_AFIODeInit ã GPIO_Init GPIO_StructInit Ø GPIO_ReadInputDataBit Q GPIO_ReadInputData ¡ GPIO_ReadOutputDataBit GPIO_ReadOutputData l GPIO_SetBits ± GPIO_ResetBits ø GPIO_WriteBit O GPIO_Write GPIO_PinLockConfig ê GPIO_EventOutputConfig Y GPIO_EventOutputCmd GPIO_PinRemapConfig & GPIO_EXTILineConfig GPIO_ETH_MediaInterfaceConfig
T 0 NVIC_PriorityGroupConfig Î NVIC_Init > NVIC_SetVectorTable NVIC_SystemLPConfig â SysTick_CLKSourceConfig 7 ~ delay_init delay_us Ö delay_ms n È ô RS232_init2 õ RS232_init3 N RS232_Send_Data ~ R232_Receive_Data ½ USART2_IRQHandler , ¼ AD421_init » AD421_data ; È | Adc_Init Ð Get_Adc Get_Adc_Average T ä USART1_IRQHandler ´ UART4_IRQHandler ç UART5_IRQHandler RS485_Init4 RS485_Init5 RS485_Init1 z RS485_Send_Data1 Ç RS485_Send_Data4 RS485_Send_Data5 a RS485_Receive_Data Á rx read_data o tx1 tx4 » tx5 8 8 ¼ t RS485_RX_CNT key RS485_RX_BUF < ô FM25V02_write ä FM25V02_read Z decode + ¡ è Error_init » Error_out ; |¢ | TIM8_GPIO_init » TIM8_CH3 , TIM8_CH4 Y ¤ | wr_com
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clear $ wr_data2 £ wr_data1 Ì hcs2022_init í sample } ¦ ¤ | SPI1_Init Ñ SPI2_Init & SPI3_Init { SPI1_ReadWriteByte Ü SPI2_ReadWriteByte > SPI3_ReadWriteByte 6 <© < | KEY_Init µ key_scan1 ë key_scan 8 xª Ì p flag1 flag2 flag3 © x ¸ y 7 D« h ê SystemInit
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Ì* iN Ú* iN à* }N í* }N ê ó* fO þ* hO + O '+ 7+ E+ K+ Q+ W+ Y+ [+ h+ l+ 4 @ y+ t ` + Ô $d.realdata $t $d main.c .text stm32f10x_it.c system_stm32f10x.c SetSysClockTo72 SetSysClock .data ..\HARDWARE\KEY\key.c ..\HARDWARE\SPI\spi.c ..\HARDWARE\hcs2022\hcs2022.c ..\HARDWARE\PWM\PWM.c ..\HARDWARE\ERROR\ERROR.c ..\HARDWARE\FM25V02\FM25V02.c ..\HARDWARE\RS485\RS485.c .bss ..\HARDWARE\ADC\ADC.c ..\HARDWARE\AD421\AD421.c ..\HARDWARE\RS232\RS232.c ..\SYSTEM\delay\delay.c fac_us fac_ms ..\SYSTEM\sys\sys.c ..\\CORE\\core_cm3.c ..\CORE\core_cm3.c ..\CORE\startup_stm32f10x_hd.s STACK Stack_Mem __initial_sp HEAP Heap_Mem RESET ..\STM32F10x_FWLib\src\misc.c ..\STM32F10x_FWLib\src\stm32f10x_fsmc.c ..\STM32F10x_FWLib\src\stm32f10x_gpio.c ..\STM32F10x_FWLib\src\stm32f10x_rcc.c APBAHBPrescTable ADCPrescTable ..\STM32F10x_FWLib\src\stm32f10x_tim.c TI4_Config TI3_Config TI2_Config TI1_Config ..\STM32F10x_FWLib\src\stm32f10x_usart.c ..\STM32F10x_FWLib\src\stm32f10x_spi.c ..\STM32F10x_FWLib\src\stm32f10x_adc.c dc.s ../clib/heapaux.c ../clib/angel/startup.s !!!main ../fplib/d2f.s x$fpl$d2f ../fplib/dfixu.s x$fpl$dfixu ../fplib/dflt.s x$fpl$dflt ../fplib/dmul.s x$fpl$dmul ../fplib/f2d.s x$fpl$f2d ../fplib/faddsub.s x$fpl$fadd _fadd1 x$fpl$frsb x$fpl$fsub _fsub1 ../fplib/ffixu.s x$fpl$ffixu ../fplib/fflt.s x$fpl$ffltu ../fplib/fmul.s x$fpl$fmul ../clib/angel/kernel.s .ARM.Collect$$rtentry$$00000000 ../fplib/dnaninf.s x$fpl$dnaninf ../fplib/dretinf.s x$fpl$dretinf ../fplib/fnaninf.s x$fpl$fnaninf ../fplib/fretinf.s x$fpl$fretinf ../fplib/usenofp.s x$fpl$usenofp .ARM.Collect$$rtentry$$00000002 .ARM.Collect$$rtentry$$00000009 .ARM.Collect$$rtentry$$0000000A .ARM.Collect$$rtentry$$0000000C .ARM.Collect$$rtentry$$0000000D .ARM.Collect$$rtentry$$00000004 ../clib/angel/sys.s ../clib/stdlib.c ../clib/angel/boardlib.s ../clib/libinit.s .ARM.Collect$$libinit$$00000000 .ARM.Collect$$rtexit$$00000000 .ARM.Collect$$libinit$$00000002 .ARM.Collect$$libinit$$00000008 .ARM.Collect$$libinit$$0000000A .ARM.Collect$$libinit$$0000000C .ARM.Collect$$libinit$$0000000F .ARM.Collect$$libinit$$00000011 .ARM.Collect$$libinit$$00000013 .ARM.Collect$$libinit$$00000015 .ARM.Collect$$libinit$$00000017 .ARM.Collect$$libinit$$00000019 .ARM.Collect$$libinit$$0000001B .ARM.Collect$$libinit$$0000001D .ARM.Collect$$libinit$$0000001F .ARM.Collect$$libinit$$00000021 .ARM.Collect$$libinit$$00000023 .ARM.Collect$$libinit$$0000002A .ARM.Collect$$libinit$$0000002C .ARM.Collect$$libinit$$0000002E .ARM.Collect$$libinit$$00000030 .ARM.Collect$$libinit$$00000031 .ARM.Collect$$rtexit$$00000002 .ARM.Collect$$rtexit$$00000003 .ARM.Collect$$rtexit$$00000004 ../clib/armsys.c ../fplib/fpinit.s ../clib/angel/sysapp.c .ARM.Collect$$libshutdown$$00000000 ../clib/heapalloc.c ../clib/signal.c .ARM.Collect$$libshutdown$$00000003 .ARM.Collect$$libshutdown$$00000006 .ARM.Collect$$libshutdown$$00000009 .ARM.Collect$$libshutdown$$0000000B .ARM.Collect$$libshutdown$$0000000E .ARM.Collect$$libshutdown$$0000000F ../clib/angel/rt.s ../clib/signal.s ../clib/angel/scatter.s !!!scatter ../clib/angel/handlers.s !!handler_copy !!handler_zi BuildAttributes$$THM_ISAv4$P$D$K$B$S$PE$A:L22UL41UL21$X:L11$S22US41US21$IEEE1$IW$USESV6$~STKCKD$USESV7$~SHL$OSPACE$ROPI$EBA8$UX$STANDARDLIB$REQ8$PRES8$EABIv2 __ARM_use_no_argv __Vectors_Size __Vectors __Vectors_End __main __scatterload __scatterload_rt2 __scatterload_rt2_thumb_only __scatterload_null __scatterload_copy __scatterload_zeroinit __rt_lib_init __rt_lib_init_alloca_1 __rt_lib_init_argv_1 __rt_lib_init_atexit_1 __rt_lib_init_clock_1 __rt_lib_init_cpp_1 __rt_lib_init_exceptions_1 __rt_lib_init_fp_1 __rt_lib_init_fp_trap_1 __rt_lib_init_getenv_1 __rt_lib_init_heap_1 __rt_lib_init_lc_collate_1 __rt_lib_init_lc_ctype_1 __rt_lib_init_lc_monetary_1 __rt_lib_init_lc_numeric_1 __rt_lib_init_lc_time_1 __rt_lib_init_rand_1 __rt_lib_init_return __rt_lib_init_signal_1 __rt_lib_init_stdio_1 __rt_lib_init_user_alloc_1 __rt_lib_shutdown __rt_lib_shutdown_fp_trap_1 __rt_lib_shutdown_heap_1 __rt_lib_shutdown_return __rt_lib_shutdown_signal_1 __rt_lib_shutdown_stdio_1 __rt_lib_shutdown_user_alloc_1 __rt_entry __rt_entry_presh_1 __rt_entry_sh __rt_entry_li __rt_entry_postsh_1 __rt_entry_main __rt_entry_postli_1 __rt_exit __rt_exit_ls __rt_exit_prels_1 __rt_exit_exit main NMI_Handler HardFault_Handler MemManage_Handler BusFault_Handler UsageFault_Handler SVC_Handler DebugMon_Handler PendSV_Handler SysTick_Handler SystemInit SystemCoreClockUpdate KEY_Init key_scan1 key_scan SPI1_Init SPI2_Init SPI3_Init SPI1_ReadWriteByte SPI2_ReadWriteByte SPI3_ReadWriteByte wr_com clear wr_data2 wr_data1 hcs2022_init sample TIM8_GPIO_init TIM8_CH3 TIM8_CH4 Error_init Error_out FM25V02_write FM25V02_read decode USART1_IRQHandler UART4_IRQHandler UART5_IRQHandler RS485_Init4 RS485_Init5 RS485_Init1 RS485_Send_Data1 RS485_Send_Data4 RS485_Send_Data5 RS485_Receive_Data rx read_data tx1 tx4 tx5 Adc_Init Get_Adc Get_Adc_Average AD421_init AD421_data RS232_init2 RS232_init3 RS232_Send_Data R232_Receive_Data USART2_IRQHandler delay_init delay_us delay_ms Reset_Handler ADC1_2_IRQHandler ADC3_IRQHandler CAN1_RX1_IRQHandler CAN1_SCE_IRQHandler DMA1_Channel1_IRQHandler DMA1_Channel2_IRQHandler DMA1_Channel3_IRQHandler DMA1_Channel4_IRQHandler DMA1_Channel5_IRQHandler DMA1_Channel6_IRQHandler DMA1_Channel7_IRQHandler DMA2_Channel1_IRQHandler DMA2_Channel2_IRQHandler DMA2_Channel3_IRQHandler DMA2_Channel4_5_IRQHandler EXTI0_IRQHandler EXTI15_10_IRQHandler EXTI1_IRQHandler EXTI2_IRQHandler EXTI3_IRQHandler EXTI4_IRQHandler EXTI9_5_IRQHandler FLASH_IRQHandler FSMC_IRQHandler I2C1_ER_IRQHandler I2C1_EV_IRQHandler I2C2_ER_IRQHandler I2C2_EV_IRQHandler PVD_IRQHandler RCC_IRQHandler RTCAlarm_IRQHandler RTC_IRQHandler SDIO_IRQHandler SPI1_IRQHandler SPI2_IRQHandler SPI3_IRQHandler TAMPER_IRQHandler TIM1_BRK_IRQHandler TIM1_CC_IRQHandler TIM1_TRG_COM_IRQHandler TIM1_UP_IRQHandler TIM2_IRQHandler TIM3_IRQHandler TIM4_IRQHandler TIM5_IRQHandler TIM6_IRQHandler TIM7_IRQHandler TIM8_BRK_IRQHandler TIM8_CC_IRQHandler TIM8_TRG_COM_IRQHandler TIM8_UP_IRQHandler USART3_IRQHandler USBWakeUp_IRQHandler USB_HP_CAN1_TX_IRQHandler USB_LP_CAN1_RX0_IRQHandler WWDG_IRQHandler __user_initial_stackheap NVIC_PriorityGroupConfig NVIC_Init NVIC_SetVectorTable NVIC_SystemLPConfig SysTick_CLKSourceConfig GPIO_DeInit GPIO_AFIODeInit GPIO_Init GPIO_StructInit GPIO_ReadInputDataBit GPIO_ReadInputData GPIO_ReadOutputDataBit GPIO_ReadOutputData GPIO_SetBits GPIO_ResetBits GPIO_WriteBit GPIO_Write GPIO_PinLockConfig GPIO_EventOutputConfig GPIO_EventOutputCmd GPIO_PinRemapConfig GPIO_EXTILineConfig GPIO_ETH_MediaInterfaceConfig RCC_DeInit RCC_HSEConfig RCC_GetFlagStatus RCC_WaitForHSEStartUp RCC_AdjustHSICalibrationValue RCC_HSICmd RCC_PLLConfig RCC_PLLCmd RCC_SYSCLKConfig RCC_GetSYSCLKSource RCC_HCLKConfig RCC_PCLK1Config RCC_PCLK2Config RCC_ITConfig RCC_USBCLKConfig RCC_ADCCLKConfig RCC_LSEConfig RCC_LSICmd RCC_RTCCLKConfig RCC_RTCCLKCmd RCC_GetClocksFreq RCC_AHBPeriphClockCmd RCC_APB2PeriphClockCmd RCC_APB1PeriphClockCmd RCC_APB2PeriphResetCmd RCC_APB1PeriphResetCmd RCC_BackupResetCmd RCC_ClockSecuritySystemCmd RCC_MCOConfig RCC_ClearFlag RCC_GetITStatus RCC_ClearITPendingBit TIM_DeInit TIM_TimeBaseInit TIM_OC1Init TIM_OC2Init TIM_OC3Init TIM_OC4Init TIM_SetIC4Prescaler TIM_SetIC3Prescaler TIM_SetIC2Prescaler TIM_SetIC1Prescaler TIM_ICInit TIM_PWMIConfig TIM_BDTRConfig TIM_TimeBaseStructInit TIM_OCStructInit TIM_ICStructInit TIM_BDTRStructInit TIM_Cmd TIM_CtrlPWMOutputs TIM_ITConfig TIM_GenerateEvent TIM_DMAConfig TIM_DMACmd TIM_InternalClockConfig TIM_SelectInputTrigger TIM_ITRxExternalClockConfig TIM_TIxExternalClockConfig TIM_ETRConfig TIM_ETRClockMode1Config TIM_ETRClockMode2Config TIM_PrescalerConfig TIM_CounterModeConfig TIM_EncoderInterfaceConfig TIM_ForcedOC1Config TIM_ForcedOC2Config TIM_ForcedOC3Config TIM_ForcedOC4Config TIM_ARRPreloadConfig TIM_SelectCOM TIM_SelectCCDMA TIM_CCPreloadControl TIM_OC1PreloadConfig TIM_OC2PreloadConfig TIM_OC3PreloadConfig TIM_OC4PreloadConfig TIM_OC1FastConfig TIM_OC2FastConfig TIM_OC3FastConfig TIM_OC4FastConfig TIM_ClearOC1Ref TIM_ClearOC2Ref TIM_ClearOC3Ref TIM_ClearOC4Ref TIM_OC1PolarityConfig TIM_OC1NPolarityConfig TIM_OC2PolarityConfig TIM_OC2NPolarityConfig TIM_OC3PolarityConfig TIM_OC3NPolarityConfig TIM_OC4PolarityConfig TIM_CCxCmd TIM_CCxNCmd TIM_SelectOCxM TIM_UpdateDisableConfig TIM_UpdateRequestConfig TIM_SelectHallSensor TIM_SelectOnePulseMode TIM_SelectOutputTrigger TIM_SelectSlaveMode TIM_SelectMasterSlaveMode TIM_SetCounter TIM_SetAutoreload TIM_SetCompare1 TIM_SetCompare2 TIM_SetCompare3 TIM_SetCompare4 TIM_SetClockDivision TIM_GetCapture1 TIM_GetCapture2 TIM_GetCapture3 TIM_GetCapture4 TIM_GetCounter TIM_GetPrescaler TIM_GetFlagStatus TIM_ClearFlag TIM_GetITStatus TIM_ClearITPendingBit USART_DeInit USART_Init USART_StructInit USART_ClockInit USART_ClockStructInit USART_Cmd USART_ITConfig USART_DMACmd USART_SetAddress USART_WakeUpConfig USART_ReceiverWakeUpCmd USART_LINBreakDetectLengthConfig USART_LINCmd USART_SendData USART_ReceiveData USART_SendBreak USART_SetGuardTime USART_SetPrescaler USART_SmartCardCmd USART_SmartCardNACKCmd USART_HalfDuplexCmd USART_OverSampling8Cmd USART_OneBitMethodCmd USART_IrDAConfig USART_IrDACmd USART_GetFlagStatus USART_ClearFlag USART_GetITStatus USART_ClearITPendingBit SPI_I2S_DeInit SPI_Init I2S_Init SPI_StructInit I2S_StructInit SPI_Cmd I2S_Cmd SPI_I2S_ITConfig SPI_I2S_DMACmd SPI_I2S_SendData SPI_I2S_ReceiveData SPI_NSSInternalSoftwareConfig SPI_SSOutputCmd SPI_DataSizeConfig SPI_TransmitCRC SPI_CalculateCRC SPI_GetCRC SPI_GetCRCPolynomial SPI_BiDirectionalLineConfig SPI_I2S_GetFlagStatus SPI_I2S_ClearFlag SPI_I2S_GetITStatus SPI_I2S_ClearITPendingBit ADC_DeInit ADC_Init ADC_StructInit ADC_Cmd ADC_DMACmd ADC_ITConfig ADC_ResetCalibration ADC_GetResetCalibrationStatus ADC_StartCalibration ADC_GetCalibrationStatus ADC_SoftwareStartConvCmd ADC_GetSoftwareStartConvStatus ADC_DiscModeChannelCountConfig ADC_DiscModeCmd ADC_RegularChannelConfig ADC_ExternalTrigConvCmd ADC_GetConversionValue ADC_GetDualModeConversionValue ADC_AutoInjectedConvCmd ADC_InjectedDiscModeCmd ADC_ExternalTrigInjectedConvConfig ADC_ExternalTrigInjectedConvCmd ADC_SoftwareStartInjectedConvCmd ADC_GetSoftwareStartInjectedConvCmdStatus ADC_InjectedChannelConfig ADC_InjectedSequencerLengthConfig ADC_SetInjectedOffset ADC_GetInjectedConversionValue ADC_AnalogWatchdogCmd ADC_AnalogWatchdogThresholdsConfig ADC_AnalogWatchdogSingleChannelConfig ADC_TempSensorVrefintCmd ADC_GetFlagStatus ADC_ClearFlag ADC_GetITStatus ADC_ClearITPendingBit __use_two_region_memory __rt_heap_escrow$2region __rt_heap_expand$2region __user_setup_stackheap exit __user_libspace __user_perproc_libspace __user_perthread_libspace _sys_exit __I$use$semihosting __use_no_semihosting_swi __semihosting_library_function __aeabi_d2f _d2f __aeabi_d2uiz _dfixu __aeabi_i2d _dflt __aeabi_dmul _dmul __fpl_dnaninf __fpl_dretinf __aeabi_f2d _f2d __aeabi_fadd _fadd __aeabi_f2uiz _ffixu __aeabi_ui2f _ffltu __aeabi_fmul _fmul __fpl_fnaninf __fpl_fretinf __aeabi_frsub _frsb __aeabi_fsub _fsub __I$use$fp Region$$Table$$Base Region$$Table$$Limit SystemCoreClock AHBPrescTable flag1 flag2 flag3 x y RS485_RX_CNT key RS485_RX_BUF __libspace_start __temporary_stack_top$libspace @ARM ARM Linker, 5.03 [Build 24]
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ArmLink --strict --callgraph --map --symbols --xref --cpu=Cortex-M3 --fpu=SoftVFP --list=.\SPI.map --output=..\OBJ\SPI.axf --scatter=..\OBJ\SPI.sct --info=summarysizes,sizes,totals,unused,veneers
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F:\stm32\ARM\ARMCC\bin\..\lib\armlib\c_w.l F:\stm32\ARM\ARMCC\bin\..\lib\armlib\fz_ws.l F:\stm32\ARM\ARMCC\bin\..\lib\armlib\h_w.l F:\stm32\ARM\ARMCC\bin\..\lib\armlib\m_ws.l F:\stm32\ARM\ARMCC\bin\..\lib\armlib\vfpsupport.l Input Comments: main.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=..\OBJ\main.d --cpu=Cortex-M3 --apcs=interwork -O0 -I..\HARDWARE\LED -I..\SYSTEM\delay -I..\SYSTEM\sys -I..\SYSTEM\usart -I..\USER -I..\STM32F10x_FWLib\inc -I..\CORE -I..\HARDWARE\KEY -I..\HARDWARE\LCD -I..\HARDWARE\RTC -I..\HARDWARE\RTC -I..\HARDWARE\WKUP -I..\HARDWARE\ADC -I..\HARDWARE\DAC -I..\HARDWARE\DMA -I..\HARDWARE\IIC -I..\HARDWARE\24CXX -I..\HARDWARE\SPI -I..\HARDWARE\FLASH -I..\HARDWARE\hcs2022 -I..\HARDWARE\SPI_CS -I..\HARDWARE\PWM -I..\HARDWARE\ERROR -I..\HARDWARE\FM25V02 -I..\HARDWARE\RS485 -I..\HARDWARE\AD421 -I..\HARDWARE\RS232 -IF:\stm32\ARM\RV31\INC -IF:\stm32\ARM\CMSIS\Include -IF:\stm32\ARM\Inc\ST\STM32F10x -DSTM32F10X_HD -DUSE_STDPERIPH_DRIVER --omf_browse=..\OBJ\main.crf stm32f10x_it.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=..\OBJ\stm32f10x_it.d --cpu=Cortex-M3 --apcs=interwork -O0 -I..\HARDWARE\LED -I..\SYSTEM\delay -I..\SYSTEM\sys -I..\SYSTEM\usart -I..\USER -I..\STM32F10x_FWLib\inc -I..\CORE -I..\HARDWARE\KEY -I..\HARDWARE\LCD -I..\HARDWARE\RTC -I..\HARDWARE\RTC -I..\HARDWARE\WKUP -I..\HARDWARE\ADC -I..\HARDWARE\DAC -I..\HARDWARE\DMA -I..\HARDWARE\IIC -I..\HARDWARE\24CXX -I..\HARDWARE\SPI -I..\HARDWARE\FLASH -I..\HARDWARE\hcs2022 -I..\HARDWARE\SPI_CS -I..\HARDWARE\PWM -I..\HARDWARE\ERROR -I..\HARDWARE\FM25V02 -I..\HARDWARE\RS485 -I..\HARDWARE\AD421 -I..\HARDWARE\RS232 -IF:\stm32\ARM\RV31\INC -IF:\stm32\ARM\CMSIS\Include -IF:\stm32\ARM\Inc\ST\STM32F10x -DSTM32F10X_HD -DUSE_STDPERIPH_DRIVER --omf_browse=..\OBJ\stm32f10x_it.crf system_stm32f10x.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=..\OBJ\system_stm32f10x.d --cpu=Cortex-M3 --apcs=interwork -O0 -I..\HARDWARE\LED -I..\SYSTEM\delay -I..\SYSTEM\sys -I..\SYSTEM\usart -I..\USER -I..\STM32F10x_FWLib\inc -I..\CORE -I..\HARDWARE\KEY -I..\HARDWARE\LCD -I..\HARDWARE\RTC -I..\HARDWARE\RTC -I..\HARDWARE\WKUP -I..\HARDWARE\ADC -I..\HARDWARE\DAC -I..\HARDWARE\DMA -I..\HARDWARE\IIC -I..\HARDWARE\24CXX -I..\HARDWARE\SPI -I..\HARDWARE\FLASH -I..\HARDWARE\hcs2022 -I..\HARDWARE\SPI_CS -I..\HARDWARE\PWM -I..\HARDWARE\ERROR -I..\HARDWARE\FM25V02 -I..\HARDWARE\RS485 -I..\HARDWARE\AD421 -I..\HARDWARE\RS232 -IF:\stm32\ARM\RV31\INC -IF:\stm32\ARM\CMSIS\Include -IF:\stm32\ARM\Inc\ST\STM32F10x -DSTM32F10X_HD -DUSE_STDPERIPH_DRIVER --omf_browse=..\OBJ\system_stm32f10x.crf key.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=..\OBJ\key.d --cpu=Cortex-M3 --apcs=interwork -O0 -I..\HARDWARE\LED -I..\SYSTEM\delay -I..\SYSTEM\sys -I..\SYSTEM\usart -I..\USER -I..\STM32F10x_FWLib\inc -I..\CORE -I..\HARDWARE\KEY -I..\HARDWARE\LCD -I..\HARDWARE\RTC -I..\HARDWARE\RTC -I..\HARDWARE\WKUP -I..\HARDWARE\ADC -I..\HARDWARE\DAC -I..\HARDWARE\DMA -I..\HARDWARE\IIC -I..\HARDWARE\24CXX -I..\HARDWARE\SPI -I..\HARDWARE\FLASH -I..\HARDWARE\hcs2022 -I..\HARDWARE\SPI_CS -I..\HARDWARE\PWM -I..\HARDWARE\ERROR -I..\HARDWARE\FM25V02 -I..\HARDWARE\RS485 -I..\HARDWARE\AD421 -I..\HARDWARE\RS232 -IF:\stm32\ARM\RV31\INC -IF:\stm32\ARM\CMSIS\Include -IF:\stm32\ARM\Inc\ST\STM32F10x -DSTM32F10X_HD -DUSE_STDPERIPH_DRIVER --omf_browse=..\OBJ\key.crf spi.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=..\OBJ\spi.d --cpu=Cortex-M3 --apcs=interwork -O0 -I..\HARDWARE\LED -I..\SYSTEM\delay -I..\SYSTEM\sys -I..\SYSTEM\usart -I..\USER -I..\STM32F10x_FWLib\inc -I..\CORE -I..\HARDWARE\KEY -I..\HARDWARE\LCD -I..\HARDWARE\RTC -I..\HARDWARE\RTC -I..\HARDWARE\WKUP -I..\HARDWARE\ADC -I..\HARDWARE\DAC -I..\HARDWARE\DMA -I..\HARDWARE\IIC -I..\HARDWARE\24CXX -I..\HARDWARE\SPI -I..\HARDWARE\FLASH -I..\HARDWARE\hcs2022 -I..\HARDWARE\SPI_CS -I..\HARDWARE\PWM -I..\HARDWARE\ERROR -I..\HARDWARE\FM25V02 -I..\HARDWARE\RS485 -I..\HARDWARE\AD421 -I..\HARDWARE\RS232 -IF:\stm32\ARM\RV31\INC -IF:\stm32\ARM\CMSIS\Include -IF:\stm32\ARM\Inc\ST\STM32F10x -DSTM32F10X_HD -DUSE_STDPERIPH_DRIVER --omf_browse=..\OBJ\spi.crf hcs2022.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=..\OBJ\hcs2022.d --cpu=Cortex-M3 --apcs=interwork -O0 -I..\HARDWARE\LED -I..\SYSTEM\delay -I..\SYSTEM\sys -I..\SYSTEM\usart -I..\USER -I..\STM32F10x_FWLib\inc -I..\CORE -I..\HARDWARE\KEY -I..\HARDWARE\LCD -I..\HARDWARE\RTC -I..\HARDWARE\RTC -I..\HARDWARE\WKUP -I..\HARDWARE\ADC -I..\HARDWARE\DAC -I..\HARDWARE\DMA -I..\HARDWARE\IIC -I..\HARDWARE\24CXX -I..\HARDWARE\SPI -I..\HARDWARE\FLASH -I..\HARDWARE\hcs2022 -I..\HARDWARE\SPI_CS -I..\HARDWARE\PWM -I..\HARDWARE\ERROR -I..\HARDWARE\FM25V02 -I..\HARDWARE\RS485 -I..\HARDWARE\AD421 -I..\HARDWARE\RS232 -IF:\stm32\ARM\RV31\INC -IF:\stm32\ARM\CMSIS\Include -IF:\stm32\ARM\Inc\ST\STM32F10x -DSTM32F10X_HD -DUSE_STDPERIPH_DRIVER --omf_browse=..\OBJ\hcs2022.crf pwm.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=..\OBJ\pwm.d --cpu=Cortex-M3 --apcs=interwork -O0 -I..\HARDWARE\LED -I..\SYSTEM\delay -I..\SYSTEM\sys -I..\SYSTEM\usart -I..\USER -I..\STM32F10x_FWLib\inc -I..\CORE -I..\HARDWARE\KEY -I..\HARDWARE\LCD -I..\HARDWARE\RTC -I..\HARDWARE\RTC -I..\HARDWARE\WKUP -I..\HARDWARE\ADC -I..\HARDWARE\DAC -I..\HARDWARE\DMA -I..\HARDWARE\IIC -I..\HARDWARE\24CXX -I..\HARDWARE\SPI -I..\HARDWARE\FLASH -I..\HARDWARE\hcs2022 -I..\HARDWARE\SPI_CS -I..\HARDWARE\PWM -I..\HARDWARE\ERROR -I..\HARDWARE\FM25V02 -I..\HARDWARE\RS485 -I..\HARDWARE\AD421 -I..\HARDWARE\RS232 -IF:\stm32\ARM\RV31\INC -IF:\stm32\ARM\CMSIS\Include -IF:\stm32\ARM\Inc\ST\STM32F10x -DSTM32F10X_HD -DUSE_STDPERIPH_DRIVER --omf_browse=..\OBJ\pwm.crf error.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=..\OBJ\error.d --cpu=Cortex-M3 --apcs=interwork -O0 -I..\HARDWARE\LED -I..\SYSTEM\delay -I..\SYSTEM\sys -I..\SYSTEM\usart -I..\USER -I..\STM32F10x_FWLib\inc -I..\CORE -I..\HARDWARE\KEY -I..\HARDWARE\LCD -I..\HARDWARE\RTC -I..\HARDWARE\RTC -I..\HARDWARE\WKUP -I..\HARDWARE\ADC -I..\HARDWARE\DAC -I..\HARDWARE\DMA -I..\HARDWARE\IIC -I..\HARDWARE\24CXX -I..\HARDWARE\SPI -I..\HARDWARE\FLASH -I..\HARDWARE\hcs2022 -I..\HARDWARE\SPI_CS -I..\HARDWARE\PWM -I..\HARDWARE\ERROR -I..\HARDWARE\FM25V02 -I..\HARDWARE\RS485 -I..\HARDWARE\AD421 -I..\HARDWARE\RS232 -IF:\stm32\ARM\RV31\INC -IF:\stm32\ARM\CMSIS\Include -IF:\stm32\ARM\Inc\ST\STM32F10x -DSTM32F10X_HD -DUSE_STDPERIPH_DRIVER --omf_browse=..\OBJ\error.crf fm25v02.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=..\OBJ\fm25v02.d --cpu=Cortex-M3 --apcs=interwork -O0 -I..\HARDWARE\LED -I..\SYSTEM\delay -I..\SYSTEM\sys -I..\SYSTEM\usart -I..\USER -I..\STM32F10x_FWLib\inc -I..\CORE -I..\HARDWARE\KEY -I..\HARDWARE\LCD -I..\HARDWARE\RTC -I..\HARDWARE\RTC -I..\HARDWARE\WKUP -I..\HARDWARE\ADC -I..\HARDWARE\DAC -I..\HARDWARE\DMA -I..\HARDWARE\IIC -I..\HARDWARE\24CXX -I..\HARDWARE\SPI -I..\HARDWARE\FLASH -I..\HARDWARE\hcs2022 -I..\HARDWARE\SPI_CS -I..\HARDWARE\PWM -I..\HARDWARE\ERROR -I..\HARDWARE\FM25V02 -I..\HARDWARE\RS485 -I..\HARDWARE\AD421 -I..\HARDWARE\RS232 -IF:\stm32\ARM\RV31\INC -IF:\stm32\ARM\CMSIS\Include -IF:\stm32\ARM\Inc\ST\STM32F10x -DSTM32F10X_HD -DUSE_STDPERIPH_DRIVER --omf_browse=..\OBJ\fm25v02.crf rs485.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=..\OBJ\rs485.d --cpu=Cortex-M3 --apcs=interwork -O0 -I..\HARDWARE\LED -I..\SYSTEM\delay -I..\SYSTEM\sys -I..\SYSTEM\usart -I..\USER -I..\STM32F10x_FWLib\inc -I..\CORE -I..\HARDWARE\KEY -I..\HARDWARE\LCD -I..\HARDWARE\RTC -I..\HARDWARE\RTC -I..\HARDWARE\WKUP -I..\HARDWARE\ADC -I..\HARDWARE\DAC -I..\HARDWARE\DMA -I..\HARDWARE\IIC -I..\HARDWARE\24CXX -I..\HARDWARE\SPI -I..\HARDWARE\FLASH -I..\HARDWARE\hcs2022 -I..\HARDWARE\SPI_CS -I..\HARDWARE\PWM -I..\HARDWARE\ERROR -I..\HARDWARE\FM25V02 -I..\HARDWARE\RS485 -I..\HARDWARE\AD421 -I..\HARDWARE\RS232 -IF:\stm32\ARM\RV31\INC -IF:\stm32\ARM\CMSIS\Include -IF:\stm32\ARM\Inc\ST\STM32F10x -DSTM32F10X_HD -DUSE_STDPERIPH_DRIVER --omf_browse=..\OBJ\rs485.crf adc.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=..\OBJ\adc.d --cpu=Cortex-M3 --apcs=interwork -O0 -I..\HARDWARE\LED -I..\SYSTEM\delay -I..\SYSTEM\sys -I..\SYSTEM\usart -I..\USER -I..\STM32F10x_FWLib\inc -I..\CORE -I..\HARDWARE\KEY -I..\HARDWARE\LCD -I..\HARDWARE\RTC -I..\HARDWARE\RTC -I..\HARDWARE\WKUP -I..\HARDWARE\ADC -I..\HARDWARE\DAC -I..\HARDWARE\DMA -I..\HARDWARE\IIC -I..\HARDWARE\24CXX -I..\HARDWARE\SPI -I..\HARDWARE\FLASH -I..\HARDWARE\hcs2022 -I..\HARDWARE\SPI_CS -I..\HARDWARE\PWM -I..\HARDWARE\ERROR -I..\HARDWARE\FM25V02 -I..\HARDWARE\RS485 -I..\HARDWARE\AD421 -I..\HARDWARE\RS232 -IF:\stm32\ARM\RV31\INC -IF:\stm32\ARM\CMSIS\Include -IF:\stm32\ARM\Inc\ST\STM32F10x -DSTM32F10X_HD -DUSE_STDPERIPH_DRIVER --omf_browse=..\OBJ\adc.crf ad421.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=..\OBJ\ad421.d --cpu=Cortex-M3 --apcs=interwork -O0 -I..\HARDWARE\LED -I..\SYSTEM\delay -I..\SYSTEM\sys -I..\SYSTEM\usart -I..\USER -I..\STM32F10x_FWLib\inc -I..\CORE -I..\HARDWARE\KEY -I..\HARDWARE\LCD -I..\HARDWARE\RTC -I..\HARDWARE\RTC -I..\HARDWARE\WKUP -I..\HARDWARE\ADC -I..\HARDWARE\DAC -I..\HARDWARE\DMA -I..\HARDWARE\IIC -I..\HARDWARE\24CXX -I..\HARDWARE\SPI -I..\HARDWARE\FLASH -I..\HARDWARE\hcs2022 -I..\HARDWARE\SPI_CS -I..\HARDWARE\PWM -I..\HARDWARE\ERROR -I..\HARDWARE\FM25V02 -I..\HARDWARE\RS485 -I..\HARDWARE\AD421 -I..\HARDWARE\RS232 -IF:\stm32\ARM\RV31\INC -IF:\stm32\ARM\CMSIS\Include -IF:\stm32\ARM\Inc\ST\STM32F10x -DSTM32F10X_HD -DUSE_STDPERIPH_DRIVER --omf_browse=..\OBJ\ad421.crf rs232.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=..\OBJ\rs232.d --cpu=Cortex-M3 --apcs=interwork -O0 -I..\HARDWARE\LED -I..\SYSTEM\delay -I..\SYSTEM\sys -I..\SYSTEM\usart -I..\USER -I..\STM32F10x_FWLib\inc -I..\CORE -I..\HARDWARE\KEY -I..\HARDWARE\LCD -I..\HARDWARE\RTC -I..\HARDWARE\RTC -I..\HARDWARE\WKUP -I..\HARDWARE\ADC -I..\HARDWARE\DAC -I..\HARDWARE\DMA -I..\HARDWARE\IIC -I..\HARDWARE\24CXX -I..\HARDWARE\SPI -I..\HARDWARE\FLASH -I..\HARDWARE\hcs2022 -I..\HARDWARE\SPI_CS -I..\HARDWARE\PWM -I..\HARDWARE\ERROR -I..\HARDWARE\FM25V02 -I..\HARDWARE\RS485 -I..\HARDWARE\AD421 -I..\HARDWARE\RS232 -IF:\stm32\ARM\RV31\INC -IF:\stm32\ARM\CMSIS\Include -IF:\stm32\ARM\Inc\ST\STM32F10x -DSTM32F10X_HD -DUSE_STDPERIPH_DRIVER --omf_browse=..\OBJ\rs232.crf delay.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=..\OBJ\delay.d --cpu=Cortex-M3 --apcs=interwork -O0 -I..\HARDWARE\LED -I..\SYSTEM\delay -I..\SYSTEM\sys -I..\SYSTEM\usart -I..\USER -I..\STM32F10x_FWLib\inc -I..\CORE -I..\HARDWARE\KEY -I..\HARDWARE\LCD -I..\HARDWARE\RTC -I..\HARDWARE\RTC -I..\HARDWARE\WKUP -I..\HARDWARE\ADC -I..\HARDWARE\DAC -I..\HARDWARE\DMA -I..\HARDWARE\IIC -I..\HARDWARE\24CXX -I..\HARDWARE\SPI -I..\HARDWARE\FLASH -I..\HARDWARE\hcs2022 -I..\HARDWARE\SPI_CS -I..\HARDWARE\PWM -I..\HARDWARE\ERROR -I..\HARDWARE\FM25V02 -I..\HARDWARE\RS485 -I..\HARDWARE\AD421 -I..\HARDWARE\RS232 -IF:\stm32\ARM\RV31\INC -IF:\stm32\ARM\CMSIS\Include -IF:\stm32\ARM\Inc\ST\STM32F10x -DSTM32F10X_HD -DUSE_STDPERIPH_DRIVER --omf_browse=..\OBJ\delay.crf sys.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=..\OBJ\sys.d --cpu=Cortex-M3 --apcs=interwork -O0 -I..\HARDWARE\LED -I..\SYSTEM\delay -I..\SYSTEM\sys -I..\SYSTEM\usart -I..\USER -I..\STM32F10x_FWLib\inc -I..\CORE -I..\HARDWARE\KEY -I..\HARDWARE\LCD -I..\HARDWARE\RTC -I..\HARDWARE\RTC -I..\HARDWARE\WKUP -I..\HARDWARE\ADC -I..\HARDWARE\DAC -I..\HARDWARE\DMA -I..\HARDWARE\IIC -I..\HARDWARE\24CXX -I..\HARDWARE\SPI -I..\HARDWARE\FLASH -I..\HARDWARE\hcs2022 -I..\HARDWARE\SPI_CS -I..\HARDWARE\PWM -I..\HARDWARE\ERROR -I..\HARDWARE\FM25V02 -I..\HARDWARE\RS485 -I..\HARDWARE\AD421 -I..\HARDWARE\RS232 -IF:\stm32\ARM\RV31\INC -IF:\stm32\ARM\CMSIS\Include -IF:\stm32\ARM\Inc\ST\STM32F10x -DSTM32F10X_HD -DUSE_STDPERIPH_DRIVER --omf_browse=..\OBJ\sys.crf core_cm3.o ARM Linker, 5.03 [Build 24]
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armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=6642 --cpu=Cortex-M3 --fpu=SoftVFP --output=..\OBJ\core_cm3.o --vfemode=force
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Input Comments: p1278-3 ARM Assembler, 5.03 [Build 24] armasm --debug --diag_suppress=1602,1073 --cpu=Cortex-M3 --fpu=SoftVFP --apcs=/interwork/interwork --divide C:\Users\ADMINI~1\AppData\Local\Temp\p1278-2 core_cm3.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=..\OBJ\core_cm3.d --cpu=Cortex-M3 --apcs=interwork -O0 -I..\HARDWARE\LED -I..\SYSTEM\delay -I..\SYSTEM\sys -I..\SYSTEM\usart -I..\USER -I..\STM32F10x_FWLib\inc -I..\CORE -I..\HARDWARE\KEY -I..\HARDWARE\LCD -I..\HARDWARE\RTC -I..\HARDWARE\RTC -I..\HARDWARE\WKUP -I..\HARDWARE\ADC -I..\HARDWARE\DAC -I..\HARDWARE\DMA -I..\HARDWARE\IIC -I..\HARDWARE\24CXX -I..\HARDWARE\SPI -I..\HARDWARE\FLASH -I..\HARDWARE\hcs2022 -I..\HARDWARE\SPI_CS -I..\HARDWARE\PWM -I..\HARDWARE\ERROR -I..\HARDWARE\FM25V02 -I..\HARDWARE\RS485 -I..\HARDWARE\AD421 -I..\HARDWARE\RS232 -IF:\stm32\ARM\RV31\INC -IF:\stm32\ARM\CMSIS\Include -IF:\stm32\ARM\Inc\ST\STM32F10x -DSTM32F10X_HD -DUSE_STDPERIPH_DRIVER --omf_browse=..\OBJ\core_cm3.crf startup_stm32f10x_hd.o ARM Assembler, 5.03 [Build 24] ArmAsm --debug --xref --cpu=Cortex-M3 --apcs=interwork --depend=..\OBJ\startup_stm32f10x_hd.d -IF:\stm32\ARM\RV31\INC -IF:\stm32\ARM\CMSIS\Include -IF:\stm32\ARM\Inc\ST\STM32F10x --list=.\startup_stm32f10x_hd.lst misc.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=..\OBJ\misc.d --cpu=Cortex-M3 --apcs=interwork -O0 -I..\HARDWARE\LED -I..\SYSTEM\delay -I..\SYSTEM\sys -I..\SYSTEM\usart -I..\USER -I..\STM32F10x_FWLib\inc -I..\CORE -I..\HARDWARE\KEY -I..\HARDWARE\LCD -I..\HARDWARE\RTC -I..\HARDWARE\RTC -I..\HARDWARE\WKUP -I..\HARDWARE\ADC -I..\HARDWARE\DAC -I..\HARDWARE\DMA -I..\HARDWARE\IIC -I..\HARDWARE\24CXX -I..\HARDWARE\SPI -I..\HARDWARE\FLASH -I..\HARDWARE\hcs2022 -I..\HARDWARE\SPI_CS -I..\HARDWARE\PWM -I..\HARDWARE\ERROR -I..\HARDWARE\FM25V02 -I..\HARDWARE\RS485 -I..\HARDWARE\AD421 -I..\HARDWARE\RS232 -IF:\stm32\ARM\RV31\INC -IF:\stm32\ARM\CMSIS\Include -IF:\stm32\ARM\Inc\ST\STM32F10x -DSTM32F10X_HD -DUSE_STDPERIPH_DRIVER --omf_browse=..\OBJ\misc.crf stm32f10x_fsmc.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=..\OBJ\stm32f10x_fsmc.d --cpu=Cortex-M3 --apcs=interwork -O0 -I..\HARDWARE\LED -I..\SYSTEM\delay -I..\SYSTEM\sys -I..\SYSTEM\usart -I..\USER -I..\STM32F10x_FWLib\inc -I..\CORE -I..\HARDWARE\KEY -I..\HARDWARE\LCD -I..\HARDWARE\RTC -I..\HARDWARE\RTC -I..\HARDWARE\WKUP -I..\HARDWARE\ADC -I..\HARDWARE\DAC -I..\HARDWARE\DMA -I..\HARDWARE\IIC -I..\HARDWARE\24CXX -I..\HARDWARE\SPI -I..\HARDWARE\FLASH -I..\HARDWARE\hcs2022 -I..\HARDWARE\SPI_CS -I..\HARDWARE\PWM -I..\HARDWARE\ERROR -I..\HARDWARE\FM25V02 -I..\HARDWARE\RS485 -I..\HARDWARE\AD421 -I..\HARDWARE\RS232 -IF:\stm32\ARM\RV31\INC -IF:\stm32\ARM\CMSIS\Include -IF:\stm32\ARM\Inc\ST\STM32F10x -DSTM32F10X_HD -DUSE_STDPERIPH_DRIVER --omf_browse=..\OBJ\stm32f10x_fsmc.crf stm32f10x_gpio.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=..\OBJ\stm32f10x_gpio.d --cpu=Cortex-M3 --apcs=interwork -O0 -I..\HARDWARE\LED -I..\SYSTEM\delay -I..\SYSTEM\sys -I..\SYSTEM\usart -I..\USER -I..\STM32F10x_FWLib\inc -I..\CORE -I..\HARDWARE\KEY -I..\HARDWARE\LCD -I..\HARDWARE\RTC -I..\HARDWARE\RTC -I..\HARDWARE\WKUP -I..\HARDWARE\ADC -I..\HARDWARE\DAC -I..\HARDWARE\DMA -I..\HARDWARE\IIC -I..\HARDWARE\24CXX -I..\HARDWARE\SPI -I..\HARDWARE\FLASH -I..\HARDWARE\hcs2022 -I..\HARDWARE\SPI_CS -I..\HARDWARE\PWM -I..\HARDWARE\ERROR -I..\HARDWARE\FM25V02 -I..\HARDWARE\RS485 -I..\HARDWARE\AD421 -I..\HARDWARE\RS232 -IF:\stm32\ARM\RV31\INC -IF:\stm32\ARM\CMSIS\Include -IF:\stm32\ARM\Inc\ST\STM32F10x -DSTM32F10X_HD -DUSE_STDPERIPH_DRIVER --omf_browse=..\OBJ\stm32f10x_gpio.crf stm32f10x_rcc.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=..\OBJ\stm32f10x_rcc.d --cpu=Cortex-M3 --apcs=interwork -O0 -I..\HARDWARE\LED -I..\SYSTEM\delay -I..\SYSTEM\sys -I..\SYSTEM\usart -I..\USER -I..\STM32F10x_FWLib\inc -I..\CORE -I..\HARDWARE\KEY -I..\HARDWARE\LCD -I..\HARDWARE\RTC -I..\HARDWARE\RTC -I..\HARDWARE\WKUP -I..\HARDWARE\ADC -I..\HARDWARE\DAC -I..\HARDWARE\DMA -I..\HARDWARE\IIC -I..\HARDWARE\24CXX -I..\HARDWARE\SPI -I..\HARDWARE\FLASH -I..\HARDWARE\hcs2022 -I..\HARDWARE\SPI_CS -I..\HARDWARE\PWM -I..\HARDWARE\ERROR -I..\HARDWARE\FM25V02 -I..\HARDWARE\RS485 -I..\HARDWARE\AD421 -I..\HARDWARE\RS232 -IF:\stm32\ARM\RV31\INC -IF:\stm32\ARM\CMSIS\Include -IF:\stm32\ARM\Inc\ST\STM32F10x -DSTM32F10X_HD -DUSE_STDPERIPH_DRIVER --omf_browse=..\OBJ\stm32f10x_rcc.crf stm32f10x_tim.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=..\OBJ\stm32f10x_tim.d --cpu=Cortex-M3 --apcs=interwork -O0 -I..\HARDWARE\LED -I..\SYSTEM\delay -I..\SYSTEM\sys -I..\SYSTEM\usart -I..\USER -I..\STM32F10x_FWLib\inc -I..\CORE -I..\HARDWARE\KEY -I..\HARDWARE\LCD -I..\HARDWARE\RTC -I..\HARDWARE\RTC -I..\HARDWARE\WKUP -I..\HARDWARE\ADC -I..\HARDWARE\DAC -I..\HARDWARE\DMA -I..\HARDWARE\IIC -I..\HARDWARE\24CXX -I..\HARDWARE\SPI -I..\HARDWARE\FLASH -I..\HARDWARE\hcs2022 -I..\HARDWARE\SPI_CS -I..\HARDWARE\PWM -I..\HARDWARE\ERROR -I..\HARDWARE\FM25V02 -I..\HARDWARE\RS485 -I..\HARDWARE\AD421 -I..\HARDWARE\RS232 -IF:\stm32\ARM\RV31\INC -IF:\stm32\ARM\CMSIS\Include -IF:\stm32\ARM\Inc\ST\STM32F10x -DSTM32F10X_HD -DUSE_STDPERIPH_DRIVER --omf_browse=..\OBJ\stm32f10x_tim.crf stm32f10x_usart.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=..\OBJ\stm32f10x_usart.d --cpu=Cortex-M3 --apcs=interwork -O0 -I..\HARDWARE\LED -I..\SYSTEM\delay -I..\SYSTEM\sys -I..\SYSTEM\usart -I..\USER -I..\STM32F10x_FWLib\inc -I..\CORE -I..\HARDWARE\KEY -I..\HARDWARE\LCD -I..\HARDWARE\RTC -I..\HARDWARE\RTC -I..\HARDWARE\WKUP -I..\HARDWARE\ADC -I..\HARDWARE\DAC -I..\HARDWARE\DMA -I..\HARDWARE\IIC -I..\HARDWARE\24CXX -I..\HARDWARE\SPI -I..\HARDWARE\FLASH -I..\HARDWARE\hcs2022 -I..\HARDWARE\SPI_CS -I..\HARDWARE\PWM -I..\HARDWARE\ERROR -I..\HARDWARE\FM25V02 -I..\HARDWARE\RS485 -I..\HARDWARE\AD421 -I..\HARDWARE\RS232 -IF:\stm32\ARM\RV31\INC -IF:\stm32\ARM\CMSIS\Include -IF:\stm32\ARM\Inc\ST\STM32F10x -DSTM32F10X_HD -DUSE_STDPERIPH_DRIVER --omf_browse=..\OBJ\stm32f10x_usart.crf stm32f10x_spi.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=..\OBJ\stm32f10x_spi.d --cpu=Cortex-M3 --apcs=interwork -O0 -I..\HARDWARE\LED -I..\SYSTEM\delay -I..\SYSTEM\sys -I..\SYSTEM\usart -I..\USER -I..\STM32F10x_FWLib\inc -I..\CORE -I..\HARDWARE\KEY -I..\HARDWARE\LCD -I..\HARDWARE\RTC -I..\HARDWARE\RTC -I..\HARDWARE\WKUP -I..\HARDWARE\ADC -I..\HARDWARE\DAC -I..\HARDWARE\DMA -I..\HARDWARE\IIC -I..\HARDWARE\24CXX -I..\HARDWARE\SPI -I..\HARDWARE\FLASH -I..\HARDWARE\hcs2022 -I..\HARDWARE\SPI_CS -I..\HARDWARE\PWM -I..\HARDWARE\ERROR -I..\HARDWARE\FM25V02 -I..\HARDWARE\RS485 -I..\HARDWARE\AD421 -I..\HARDWARE\RS232 -IF:\stm32\ARM\RV31\INC -IF:\stm32\ARM\CMSIS\Include -IF:\stm32\ARM\Inc\ST\STM32F10x -DSTM32F10X_HD -DUSE_STDPERIPH_DRIVER --omf_browse=..\OBJ\stm32f10x_spi.crf stm32f10x_adc.o ARM C/C++ Compiler, 5.03 [Build 24] ArmCC --debug -c --depend=..\OBJ\stm32f10x_adc.d --cpu=Cortex-M3 --apcs=interwork -O0 -I..\HARDWARE\LED -I..\SYSTEM\delay -I..\SYSTEM\sys -I..\SYSTEM\usart -I..\USER -I..\STM32F10x_FWLib\inc -I..\CORE -I..\HARDWARE\KEY -I..\HARDWARE\LCD -I..\HARDWARE\RTC -I..\HARDWARE\RTC -I..\HARDWARE\WKUP -I..\HARDWARE\ADC -I..\HARDWARE\DAC -I..\HARDWARE\DMA -I..\HARDWARE\IIC -I..\HARDWARE\24CXX -I..\HARDWARE\SPI -I..\HARDWARE\FLASH -I..\HARDWARE\hcs2022 -I..\HARDWARE\SPI_CS -I..\HARDWARE\PWM -I..\HARDWARE\ERROR -I..\HARDWARE\FM25V02 -I..\HARDWARE\RS485 -I..\HARDWARE\AD421 -I..\HARDWARE\RS232 -IF:\stm32\ARM\RV31\INC -IF:\stm32\ARM\CMSIS\Include -IF:\stm32\ARM\Inc\ST\STM32F10x -DSTM32F10X_HD -DUSE_STDPERIPH_DRIVER --omf_browse=..\OBJ\stm32f10x_adc.crf argv_veneer.o ARM Linker, 5.03 [Build 24]
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armlink --partial --no_add_relocs_to_undefined --no_execstack --no_generate_mapping_symbols --diag_suppress=6642 --cpu=7-M --fpu=None --no_unaligned_access --output=argv_veneer.o --vfemode=force --branchpatch=m3-ldrd
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Input Comments: ER_IROM1 RW_IRAM1 .debug_abbrev .debug_frame .debug_info .debug_line .debug_loc .debug_macinfo .debug_pubnames .symtab .strtab .note .comment .shstrtab 4 ¼O `V 4 O
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