/**
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******************************************************************************
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* @file fm33a0xxev_pmu.h
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* @author FM33A0XXEV Application Team
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* @version V1.0.0
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* @date 16-April-2020
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* @brief This file contains all the functions prototypes for the PMU firmware library.
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __FM33A0XXEV_PMU_H
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#define __FM33A0XXEV_PMU_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "FM33A0XXEV.h"
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typedef struct
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{
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uint32_t PMOD; /*!<µÍ¹¦ºÄģʽÅäÖà */
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uint32_t SLPDP; /*!<DeepSleep¿ØÖƼĴæÆ÷ */
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FunState CVS; /*!<Äں˵çѹ½µµÍʹÄÜ¿ØÖÆ */
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uint32_t SCR; /*!<M0ϵͳ¿ØÖƼĴæÆ÷£¬Ò»°ãÅäÖÃΪ0¼´¿É */
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uint32_t TIA; /*!¿É±à³Ì¶îÍ⻽ÐÑÑÓ³Ù */
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}PMU_SleepCfg_InitTypeDef;
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#define PMU_CR_LDO15EN_Pos 17 /* LDO15ʹÄܱê־λ
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1£ºLDO15´¦ÓÚ¹¤×÷״̬
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0£ºLDO15±»¹Ø±Õ */
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#define PMU_CR_LDO15EN_Msk (0x1U << PMU_CR_LDO15EN_Pos)
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#define PMU_CR_LDO15EN_B_Pos 16 /* LDO15ʹÄܱêÖ¾·´ÂëУÑéλ */
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#define PMU_CR_LDO15EN_B_Msk (0x1U << PMU_CR_LDO15EN_B_Pos)
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#define PMU_CR_WKFSEL_Pos 10 /* Sleep/DeepSleep»½ÐѺóµÄϵͳƵÂÊ
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00£ºRCHF-8MHz
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01£ºRCHF-16MHz
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10£ºRCHF-24MHz
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11£ºRCHF-32MHz */
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#define PMU_CR_WKFSEL_Msk (0x3U << PMU_CR_WKFSEL_Pos)
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#define PMU_CR_WKFSEL_RCHF_8M (0x0U << PMU_CR_WKFSEL_Pos) /* RCHF-8MHz */
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#define PMU_CR_WKFSEL_RCHF_16M (0x1U << PMU_CR_WKFSEL_Pos) /* RCHF-16MHz */
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#define PMU_CR_WKFSEL_RCHF_24M (0x2U << PMU_CR_WKFSEL_Pos) /* RCHF-24MHz */
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#define PMU_CR_WKFSEL_RCHF_32M (0x3U << PMU_CR_WKFSEL_Pos) /* RCHF-32MHz */
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#define PMU_CR_SLPDP_Pos 9 /* DeepSleep¿ØÖƼĴæÆ÷
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1£ºDeepSleepģʽʹÄÜ£¬Ï¹رջù×¼µçѹԴ
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0£º³£¹æSleepģʽ
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ÔÚSleepÏ£¬Èç¹ûÖÃλÁËSLPDPλ¼´ÎªDeepSleepģʽ£»
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¸Ãλ½öÔÚSleepÏÂÓÐЧ */
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#define PMU_CR_SLPDP_Msk (0x1U << PMU_CR_SLPDP_Pos)
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#define PMU_CR_SLPDP_DEEPSLEEP (0x1U << PMU_CR_SLPDP_Pos) /* DeepSleepģʽʹÄÜ£¬Ï¹رջù×¼µçѹԴ */
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#define PMU_CR_SLPDP_SLEEP (0x0U << PMU_CR_SLPDP_Pos) /* ³£¹æSleepģʽ */
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#define PMU_CR_CVS_Pos 8 /* CoreVoltageScalingÅäÖÃ
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0£ºµÍ¹¦ºÄģʽϲ»Ê¹ÄÜÄں˵çѹµ÷Õû
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1£ºµÍ¹¦ºÄģʽϽµµÍÄں˵çѹ
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¸Ãλ½öÔÚSleep/DeepSleep/RTCBKPģʽÏÂÆð×÷Óà */
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#define PMU_CR_CVS_Msk (0x1U << PMU_CR_CVS_Pos)
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#define PMU_CR_CVS_DISABLE (0x0U << PMU_CR_CVS_Pos) /* µÍ¹¦ºÄģʽϲ»Ê¹ÄÜÄں˵çѹµ÷Õû */
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#define PMU_CR_CVS_ENABLE (0x1U << PMU_CR_CVS_Pos) /* µÍ¹¦ºÄģʽϽµµÍÄں˵çѹ */
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#define PMU_CR_PMOD_Pos 0 /* µÍ¹¦ºÄģʽÅäÖüĴæÆ÷
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00£ºActive mode / LP Active mode
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01£ºLPRUN mode
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10£ºSleep mode / DeepSleep mode
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11£ºRTCBKP mode */
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#define PMU_CR_PMOD_Msk (0x3U << PMU_CR_PMOD_Pos)
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#define PMU_CR_PMOD_ACTIVE (0x0U << PMU_CR_PMOD_Pos) /* Active mode / LP Active mode */
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#define PMU_CR_PMOD_LPRUN (0x1U << PMU_CR_PMOD_Pos) /* LPRUN mode */
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#define PMU_CR_PMOD_SLEEP (0x2U << PMU_CR_PMOD_Pos) /* Sleep mode / DeepSleep mode */
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#define PMU_WKTR_STPCLR_Pos 2 /* Flash Stop»½ÐÑ¿ØÖÆ
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0£ºStopÐźŵȴýʱÖÓ½¨Á¢ºóͬ²½ÇåÁã
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1£ºStopÐźÅÒì²½ÇåÁã */
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#define PMU_WKTR_STPCLR_Msk (0x1U << PMU_WKTR_STPCLR_Pos)
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#define PMU_WKTR_STPCLR_SYN (0x0U << PMU_WKTR_STPCLR_Pos) /* StopÐźŵȴýʱÖÓ½¨Á¢ºóͬ²½ÇåÁã */
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#define PMU_WKTR_STPCLR_ASY (0x1U << PMU_WKTR_STPCLR_Pos) /* StopÐźÅÒì²½ÇåÁã */
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#define PMU_WKTR_T1A_Pos 0 /* ¿É±à³Ì¶îÍ⻽ÐÑÑÓ³Ù
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ÔÚDeepSleepģʽÏ£¬RCHFʱÖÓµ½À´ºó£¬¸ù¾Ý´Ë¼Ä´æÆ÷ÅäÖõȴý¶îÍâÑÓ³Ùʱ¼äºó£¬ÔÙ¶ÁÈ¡FlashУÑé×Ö
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00£º0us
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01£º2us
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10£º4us
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11£º8us */
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#define PMU_WKTR_T1A_Msk (0x3U << PMU_WKTR_T1A_Pos)
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#define PMU_WKTR_T1A_0US (0x0U << PMU_WKTR_T1A_Pos) /* 0us */
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#define PMU_WKTR_T1A_2US (0x1U << PMU_WKTR_T1A_Pos) /* 2us */
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#define PMU_WKTR_T1A_4US (0x2U << PMU_WKTR_T1A_Pos) /* 4us */
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#define PMU_WKTR_T1A_8US (0x3U << PMU_WKTR_T1A_Pos) /* 8us */
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#define PMU_WKFR_ADCWKF_Pos 31 /* ADCÖжϻ½ÐѱêÖ¾£¬Öжϳ·ÏúʱӲ¼þ×Ô¶¯ÇåÁã */
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#define PMU_WKFR_ADCWKF_Msk (0x1U << PMU_WKFR_ADCWKF_Pos)
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#define PMU_WKFR_RTCWKF_Pos 28 /* RTCÖжϻ½ÐѱêÖ¾£¬Öжϳ·ÏúʱӲ¼þ×Ô¶¯ÇåÁã */
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#define PMU_WKFR_RTCWKF_Msk (0x1U << PMU_WKFR_RTCWKF_Pos)
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#define PMU_WKFR_SVDWKF_Pos 27 /* SVDÖжϻ½ÐѱêÖ¾£¬Öжϳ·ÏúʱӲ¼þ×Ô¶¯ÇåÁã */
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#define PMU_WKFR_SVDWKF_Msk (0x1U << PMU_WKFR_SVDWKF_Pos)
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#define PMU_WKFR_LFDETWKF_Pos 26 /* 32768Hz¾§ÌåÍ£ÕñÖжϻ½ÐѱêÖ¾£¬Öжϳ·ÏúʱӲ¼þ×Ô¶¯ÇåÁã */
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#define PMU_WKFR_LFDETWKF_Msk (0x1U << PMU_WKFR_LFDETWKF_Pos)
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#define PMU_WKFR_IOWKF_Pos 24 /* IOÖжϻ½ÐѱêÖ¾£¬Öжϳ·ÏúʱӲ¼þ×Ô¶¯ÇåÁã */
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#define PMU_WKFR_IOWKF_Msk (0x1U << PMU_WKFR_IOWKF_Pos)
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#define PMU_WKFR_LPU1WKF_Pos 21 /* LPUART1Öжϻ½ÐѱêÖ¾£¬Öжϳ·ÏúʱӲ¼þ×Ô¶¯ÇåÁã */
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#define PMU_WKFR_LPU1WKF_Msk (0x1U << PMU_WKFR_LPU1WKF_Pos)
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#define PMU_WKFR_LPU0WKF_Pos 20 /* LPUART0Öжϻ½ÐѱêÖ¾£¬Öжϳ·ÏúʱӲ¼þ×Ô¶¯ÇåÁã */
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#define PMU_WKFR_LPU0WKF_Msk (0x1U << PMU_WKFR_LPU0WKF_Pos)
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#define PMU_WKFR_COMP_OOWF_Pos 19 /* ±È½ÏÆ÷out-of-window»½ÐѱêÖ¾£¬Öжϳ·ÏúʱӲ¼þ×Ô¶¯ÇåÁã */
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#define PMU_WKFR_COMP_OOWF_Msk (0x1U << PMU_WKFR_COMP_OOWF_Pos)
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#define PMU_WKFR_COMP_WINF_Pos 18 /* ±È½ÏÆ÷window»½ÐѱêÖ¾£¬Öжϳ·ÏúʱӲ¼þ×Ô¶¯ÇåÁã */
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#define PMU_WKFR_COMP_WINF_Msk (0x1U << PMU_WKFR_COMP_WINF_Pos)
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#define PMU_WKFR_COMP2WKF_Pos 17 /* ±È½ÏÆ÷2Öжϻ½ÐѱêÖ¾£¬Öжϳ·ÏúʱӲ¼þ×Ô¶¯ÇåÁã */
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#define PMU_WKFR_COMP2WKF_Msk (0x1U << PMU_WKFR_COMP2WKF_Pos)
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#define PMU_WKFR_COMP1WKF_Pos 16 /* ±È½ÏÆ÷1Öжϻ½ÐѱêÖ¾£¬Öжϳ·ÏúʱӲ¼þ×Ô¶¯ÇåÁã */
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#define PMU_WKFR_COMP1WKF_Msk (0x1U << PMU_WKFR_COMP1WKF_Pos)
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#define PMU_WKFR_LPTWKF_Pos 10 /* _32Öжϻ½ÐѱêÖ¾£¬Öжϳ·ÏúʱӲ¼þ×Ô¶¯ÇåÁã */
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#define PMU_WKFR_LPTWKF_Msk (0x1U << PMU_WKFR_LPTWKF_Pos)
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#define PMU_WKFR_BSTWKF_Pos 9 /* BSTIM32Öжϻ½ÐѱêÖ¾£¬Öжϳ·ÏúʱӲ¼þ×Ô¶¯ÇåÁã */
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#define PMU_WKFR_BSTWKF_Msk (0x1U << PMU_WKFR_BSTWKF_Pos)
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#define PMU_WKFR_DBGWKF_Pos 8 /* CPU Debugger»½ÐѱêÖ¾£¬Èí¼þд1ÇåÁã */
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#define PMU_WKFR_DBGWKF_Msk (0x1U << PMU_WKFR_DBGWKF_Pos)
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#define PMU_IER_SLPEIE_Pos 1 /* SLEEP´íÎóÖжÏʹÄÜ (Sleep mode Error Interrupt Enable)
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1£ºÊ¹ÄÜSLEEP´íÎóÖжÏ
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0£º½ûÖ¹SLEEP´íÎóÖÐ¶Ï */
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#define PMU_IER_SLPEIE_Msk (0x1U << PMU_IER_SLPEIE_Pos)
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/* ʹÄÜSLEEP´íÎóÖÐ¶Ï */
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/* ½ûÖ¹SLEEP´íÎóÖÐ¶Ï */
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#define PMU_IER_RTCEIE_Pos 0 /* RTCBKP´íÎóÖжÏʹÄÜ(RTCBKP mode Error Interrupt Enable)
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1£ºÊ¹ÄÜRTCBKP´íÎóÖжÏ
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0£º½ûÖ¹RTCBKP´íÎóÖÐ¶Ï */
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#define PMU_IER_RTCEIE_Msk (0x1U << PMU_IER_RTCEIE_Pos)
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/* ʹÄÜRTCBKP´íÎóÖÐ¶Ï */
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/* ½ûÖ¹RTCBKP´íÎóÖÐ¶Ï */
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#define PMU_ISR_SLPEIF_Pos 1 /* SLEEP´íÎóÖжϱêÖ¾£¬Ó²¼þÖÃ룬Èí¼þд1ÇåÁã (Sleep Error Interrupt Flag, write 1 to clear)
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1£ºÔÚPMOD=2¡¯h2ºó£¬CPUÖ´ÐÐWFI/WFEÖ¸ÁîÇ°ÖÃλÁËSLEEPDEEP¼Ä´æÆ÷ʱÖÃλ
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0£ºÔÚPMOD=2¡¯h2ºó£¬CPUÕýÈ·½øÈëSLEEP */
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#define PMU_ISR_SLPEIF_Msk (0x1U << PMU_ISR_SLPEIF_Pos)
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#define PMU_ISR_RTCEIF_Pos 0 /* RTCBKP´íÎóÖжϱêÖ¾£¬Ó²¼þÖÃ룬Èí¼þд1ÇåÁã(RTC Error Interrupt Flag, write 1 to clear)
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1£ºÔÚPMOD=2¡¯h3ºó£¬Î´¸ÄдCPUÄÚ²¿¼Ä´æÆ÷SLEEPDEEP=1£¬È»ºóÖ´ÐÐWFI/WFEÖ¸Á»òÕßϵͳʱÖÓÀ´×ÔUSB PHY£¬ÊÔͼ½øÈëRTCBKPģʽ
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0£ºÔÚPMOD=2¡¯h3ºó£¬CPU×ÔÉíÕýÈ·½øÈëDEEP SLEEP */
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#define PMU_ISR_RTCEIF_Msk (0x1U << PMU_ISR_RTCEIF_Pos)
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//Macro_End
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/* Exported functions --------------------------------------------------------*/
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extern void PMU_Deinit(void);
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/* LDO15ʹÄܱê־λ
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1£ºLDO15´¦ÓÚ¹¤×÷״̬
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0£ºLDO15±»¹Ø±Õ Ïà¹Øº¯Êý */
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extern FlagStatus PMU_CR_LDO15EN_Chk(void);
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/* LDO15ʹÄܱêÖ¾·´ÂëУÑéλ Ïà¹Øº¯Êý */
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extern FlagStatus PMU_CR_LDO15EN_B_Chk(void);
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/* Sleep/DeepSleep»½ÐѺóµÄϵͳƵÂÊ
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00£ºRCHF-8MHz
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01£ºRCHF-16MHz
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10£ºRCHF-24MHz
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11£ºRCHF-32MHz Ïà¹Øº¯Êý */
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extern void PMU_CR_WKFSEL_Set(uint32_t SetValue);
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extern uint32_t PMU_CR_WKFSEL_Get(void);
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/* DeepSleep¿ØÖƼĴæÆ÷
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1£ºDeepSleepģʽʹÄÜ£¬Ï¹رջù×¼µçѹԴ
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0£º³£¹æSleepģʽ
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ÔÚSleepÏ£¬Èç¹ûÖÃλÁËSLPDPλ¼´ÎªDeepSleepģʽ£»
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¸Ãλ½öÔÚSleepÏÂÓÐЧ Ïà¹Øº¯Êý */
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extern void PMU_CR_SLPDP_Set(uint32_t SetValue);
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extern uint32_t PMU_CR_SLPDP_Get(void);
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/* CoreVoltageScalingÅäÖÃ
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0£ºµÍ¹¦ºÄģʽϲ»Ê¹ÄÜÄں˵çѹµ÷Õû
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1£ºµÍ¹¦ºÄģʽϽµµÍÄں˵çѹ
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¸Ãλ½öÔÚSleep/DeepSleep/RTCBKPģʽÏÂÆð×÷Óà Ïà¹Øº¯Êý */
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extern void PMU_CR_CVS_Set(uint32_t SetValue);
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extern uint32_t PMU_CR_CVS_Get(void);
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/* µÍ¹¦ºÄģʽÅäÖüĴæÆ÷
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00£ºActive mode / LP Active mode
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01£ºLPRUN mode
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10£ºSleep mode / DeepSleep mode
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11£ºRTCBKP mode Ïà¹Øº¯Êý */
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extern void PMU_CR_PMOD_Set(uint32_t SetValue);
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extern uint32_t PMU_CR_PMOD_Get(void);
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/* Flash Stop»½ÐÑ¿ØÖÆ
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0£ºStopÐźŵȴýʱÖÓ½¨Á¢ºóͬ²½ÇåÁã
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1£ºStopÐźÅÒì²½ÇåÁã Ïà¹Øº¯Êý */
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extern void PMU_WKTR_STPCLR_Set(uint32_t SetValue);
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extern uint32_t PMU_WKTR_STPCLR_Get(void);
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/* ¿É±à³Ì¶îÍ⻽ÐÑÑÓ³Ù
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ÔÚDeepSleepģʽÏ£¬RCHFʱÖÓµ½À´ºó£¬¸ù¾Ý´Ë¼Ä´æÆ÷ÅäÖõȴý¶îÍâÑÓ³Ùʱ¼äºó£¬ÔÙ¶ÁÈ¡FlashУÑé×Ö
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00£º0us
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01£º2us
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10£º4us
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11£º8us Ïà¹Øº¯Êý */
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extern void PMU_WKTR_T1A_Set(uint32_t SetValue);
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extern uint32_t PMU_WKTR_T1A_Get(void);
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/* ADCÖжϻ½ÐѱêÖ¾£¬Öжϳ·ÏúʱӲ¼þ×Ô¶¯ÇåÁã Ïà¹Øº¯Êý */
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extern FlagStatus PMU_WKFR_ADCWKF_Chk(void);
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/* RTCÖжϻ½ÐѱêÖ¾£¬Öжϳ·ÏúʱӲ¼þ×Ô¶¯ÇåÁã Ïà¹Øº¯Êý */
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extern FlagStatus PMU_WKFR_RTCWKF_Chk(void);
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/* SVDÖжϻ½ÐѱêÖ¾£¬Öжϳ·ÏúʱӲ¼þ×Ô¶¯ÇåÁã Ïà¹Øº¯Êý */
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extern FlagStatus PMU_WKFR_SVDWKF_Chk(void);
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/* 32768Hz¾§ÌåÍ£ÕñÖжϻ½ÐѱêÖ¾£¬Öжϳ·ÏúʱӲ¼þ×Ô¶¯ÇåÁã Ïà¹Øº¯Êý */
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extern FlagStatus PMU_WKFR_LFDETWKF_Chk(void);
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/* IOÖжϻ½ÐѱêÖ¾£¬Öжϳ·ÏúʱӲ¼þ×Ô¶¯ÇåÁã Ïà¹Øº¯Êý */
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extern FlagStatus PMU_WKFR_IOWKF_Chk(void);
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/* LPUART1Öжϻ½ÐѱêÖ¾£¬Öжϳ·ÏúʱӲ¼þ×Ô¶¯ÇåÁã Ïà¹Øº¯Êý */
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extern FlagStatus PMU_WKFR_LPU1WKF_Chk(void);
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/* LPUART0Öжϻ½ÐѱêÖ¾£¬Öжϳ·ÏúʱӲ¼þ×Ô¶¯ÇåÁã Ïà¹Øº¯Êý */
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extern FlagStatus PMU_WKFR_LPU0WKF_Chk(void);
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/* ±È½ÏÆ÷out-of-window»½ÐѱêÖ¾£¬Öжϳ·ÏúʱӲ¼þ×Ô¶¯ÇåÁã Ïà¹Øº¯Êý */
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extern FlagStatus PMU_WKFR_COMP_OOWF_Chk(void);
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/* ±È½ÏÆ÷window»½ÐѱêÖ¾£¬Öжϳ·ÏúʱӲ¼þ×Ô¶¯ÇåÁã Ïà¹Øº¯Êý */
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extern FlagStatus PMU_WKFR_COMP_WINF_Chk(void);
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/* ±È½ÏÆ÷2Öжϻ½ÐѱêÖ¾£¬Öжϳ·ÏúʱӲ¼þ×Ô¶¯ÇåÁã Ïà¹Øº¯Êý */
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extern FlagStatus PMU_WKFR_COMP2WKF_Chk(void);
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/* ±È½ÏÆ÷1Öжϻ½ÐѱêÖ¾£¬Öжϳ·ÏúʱӲ¼þ×Ô¶¯ÇåÁã Ïà¹Øº¯Êý */
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extern FlagStatus PMU_WKFR_COMP1WKF_Chk(void);
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/* _32Öжϻ½ÐѱêÖ¾£¬Öжϳ·ÏúʱӲ¼þ×Ô¶¯ÇåÁã Ïà¹Øº¯Êý */
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extern FlagStatus PMU_WKFR_LPTWKF_Chk(void);
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/* BSTIM32Öжϻ½ÐѱêÖ¾£¬Öжϳ·ÏúʱӲ¼þ×Ô¶¯ÇåÁã Ïà¹Øº¯Êý */
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extern FlagStatus PMU_WKFR_BSTWKF_Chk(void);
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/* CPU Debugger»½ÐѱêÖ¾£¬Èí¼þд1ÇåÁã Ïà¹Øº¯Êý */
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extern void PMU_WKFR_DBGWKF_Clr(void);
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extern FlagStatus PMU_WKFR_DBGWKF_Chk(void);
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/* SLEEP´íÎóÖжÏʹÄÜ (Sleep mode Error Interrupt Enable)
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1£ºÊ¹ÄÜSLEEP´íÎóÖжÏ
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0£º½ûÖ¹SLEEP´íÎóÖÐ¶Ï Ïà¹Øº¯Êý */
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extern void PMU_IER_SLPEIE_Setable(FunState NewState);
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extern FunState PMU_IER_SLPEIE_Getable(void);
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/* RTCBKP´íÎóÖжÏʹÄÜ(RTCBKP mode Error Interrupt Enable)
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1£ºÊ¹ÄÜRTCBKP´íÎóÖжÏ
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0£º½ûÖ¹RTCBKP´íÎóÖÐ¶Ï Ïà¹Øº¯Êý */
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extern void PMU_IER_RTCEIE_Setable(FunState NewState);
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extern FunState PMU_IER_RTCEIE_Getable(void);
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/* SLEEP´íÎóÖжϱêÖ¾£¬Ó²¼þÖÃ룬Èí¼þд1ÇåÁã (Sleep Error Interrupt Flag, write 1 to clear)
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1£ºÔÚPMOD=2¡¯h2ºó£¬CPUÖ´ÐÐWFI/WFEÖ¸ÁîÇ°ÖÃλÁËSLEEPDEEP¼Ä´æÆ÷ʱÖÃλ
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0£ºÔÚPMOD=2¡¯h2ºó£¬CPUÕýÈ·½øÈëSLEEP Ïà¹Øº¯Êý */
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extern void PMU_ISR_SLPEIF_Clr(void);
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extern FlagStatus PMU_ISR_SLPEIF_Chk(void);
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/* RTCBKP´íÎóÖжϱêÖ¾£¬Ó²¼þÖÃ룬Èí¼þд1ÇåÁã(RTC Error Interrupt Flag, write 1 to clear)
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1£ºÔÚPMOD=2¡¯h3ºó£¬Î´¸ÄдCPUÄÚ²¿¼Ä´æÆ÷SLEEPDEEP=1£¬È»ºóÖ´ÐÐWFI/WFEÖ¸Á»òÕßϵͳʱÖÓÀ´×ÔUSB PHY£¬ÊÔͼ½øÈëRTCBKPģʽ
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0£ºÔÚPMOD=2¡¯h3ºó£¬CPU×ÔÉíÕýÈ·½øÈëDEEP SLEEP Ïà¹Øº¯Êý */
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extern void PMU_ISR_RTCEIF_Clr(void);
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extern FlagStatus PMU_ISR_RTCEIF_Chk(void);
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extern void PMU_WKFR_WKPxF_Clr(uint32_t NWKPinDef);
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extern FlagStatus PMU_WKFR_WKPxF_Chk(uint32_t NWKPinDef);
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extern void PMU_SleepCfg_Init(PMU_SleepCfg_InitTypeDef* SleepCfg_InitStruct);
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//Announce_End
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#ifdef __cplusplus
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}
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#endif
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#endif /* __FM33A0XXEV_PMU_H */
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