/**
|
******************************************************************************
|
* @file fm33a0xxev_cmu.c
|
* @author FM33A0XXEV Application Team
|
* @version V1.0.0
|
* @date 16-April-2020
|
* @brief This file provides firmware functions to manage the following
|
* functionalities of....:
|
*
|
*/
|
|
/* Includes ------------------------------------------------------------------*/
|
|
#include "fm33a0xxev_cmu.h"
|
|
/** @addtogroup fm33a0xxev_StdPeriph_Driver
|
* @{
|
*/
|
|
/** @defgroup CMU
|
* @brief CMU driver modules
|
* @{
|
*/
|
|
void CMU_SYSCLKCR_SLP_ENEXTI_Setable(FunState NewState)
|
{
|
if (NewState == ENABLE)
|
{
|
CMU->SYSCLKCR |= (CMU_SYSCLKCR_SLP_ENEXTI_Msk);
|
}
|
else
|
{
|
CMU->SYSCLKCR &= ~(CMU_SYSCLKCR_SLP_ENEXTI_Msk);
|
}
|
}
|
|
FunState CMU_SYSCLKCR_SLP_ENEXTI_Getable(void)
|
{
|
if (CMU->SYSCLKCR & (CMU_SYSCLKCR_SLP_ENEXTI_Msk))
|
{
|
return ENABLE;
|
}
|
else
|
{
|
return DISABLE;
|
}
|
}
|
|
/* APBʱÖÓ·ÖƵѡÔñ (APBbus clock Prescaler)
|
000/001/010/011£º²»·ÖƵ
|
100£º2·ÖƵ
|
101£º4·ÖƵ
|
110£º8·ÖƵ
|
111£º16·ÖƵ Ïà¹Øº¯Êý */
|
void CMU_SYSCLKCR_APBPRES_Set(uint32_t SetValue)
|
{
|
uint32_t tmpreg;
|
tmpreg = CMU->SYSCLKCR;
|
tmpreg &= ~(CMU_SYSCLKCR_APBPRES_Msk);
|
tmpreg |= (SetValue & CMU_SYSCLKCR_APBPRES_Msk);
|
CMU->SYSCLKCR = tmpreg;
|
}
|
|
uint32_t CMU_SYSCLKCR_APBPRES_Get(void)
|
{
|
return (CMU->SYSCLKCR & CMU_SYSCLKCR_APBPRES_Msk);
|
}
|
|
/* AHBʱÖÓ·ÖƵѡÔñ (AHB bus clock Prescaler)
|
000/001/010/011£º²»·ÖƵ
|
100£º2·ÖƵ
|
101£º4·ÖƵ
|
110£º8·ÖƵ
|
111£º16·ÖƵ Ïà¹Øº¯Êý */
|
void CMU_SYSCLKCR_AHBPRES_Set(uint32_t SetValue)
|
{
|
uint32_t tmpreg;
|
tmpreg = CMU->SYSCLKCR;
|
tmpreg &= ~(CMU_SYSCLKCR_AHBPRES_Msk);
|
tmpreg |= (SetValue & CMU_SYSCLKCR_AHBPRES_Msk);
|
CMU->SYSCLKCR = tmpreg;
|
}
|
|
uint32_t CMU_SYSCLKCR_AHBPRES_Get(void)
|
{
|
return (CMU->SYSCLKCR & CMU_SYSCLKCR_AHBPRES_Msk);
|
}
|
|
/* CPUÄÚºËsystick¹¤×÷ʱÖÓÑ¡Ôñ (Systick clock select)
|
00£ºSCLK
|
01£ºLSCLK
|
10£ºRC4M
|
11£ºSYSCLK Ïà¹Øº¯Êý */
|
void CMU_SYSCLKCR_STCLKSEL_Set(uint32_t SetValue)
|
{
|
uint32_t tmpreg;
|
tmpreg = CMU->SYSCLKCR;
|
tmpreg &= ~(CMU_SYSCLKCR_STCLKSEL_Msk);
|
tmpreg |= (SetValue & CMU_SYSCLKCR_STCLKSEL_Msk);
|
CMU->SYSCLKCR = tmpreg;
|
}
|
|
uint32_t CMU_SYSCLKCR_STCLKSEL_Get(void)
|
{
|
return (CMU->SYSCLKCR & CMU_SYSCLKCR_STCLKSEL_Msk);
|
}
|
|
/* ϵͳʱÖÓÔ´Ñ¡Ôñ Ïà¹Øº¯Êý */
|
void CMU_SYSCLKCR_SYSCLKSEL_Set(uint32_t SetValue)
|
{
|
uint32_t tmpreg;
|
tmpreg = CMU->SYSCLKCR;
|
tmpreg &= ~(CMU_SYSCLKCR_SYSCLKSEL_Msk);
|
tmpreg |= (SetValue & CMU_SYSCLKCR_SYSCLKSEL_Msk);
|
CMU->SYSCLKCR = tmpreg;
|
}
|
|
uint32_t CMU_SYSCLKCR_SYSCLKSEL_Get(void)
|
{
|
return (CMU->SYSCLKCR & CMU_SYSCLKCR_SYSCLKSEL_Msk);
|
}
|
|
/* RCHFƵÂÊÑ¡Ôñ¼Ä´æÆ÷0000£º8MHz
|
0001£º16MHz
|
0010£º24MHz
|
0011£º32MHz
|
0111£º40MHz
|
1111£º48MHz
|
ÆäËû£ºRFU Ïà¹Øº¯Êý */
|
void CMU_RCHFCR_FSEL_Set(uint32_t SetValue)
|
{
|
uint32_t tmpreg;
|
tmpreg = CMU->RCHFCR;
|
tmpreg &= ~(CMU_RCHFCR_FSEL_Msk);
|
tmpreg |= (SetValue & CMU_RCHFCR_FSEL_Msk);
|
CMU->RCHFCR = tmpreg;
|
}
|
|
uint32_t CMU_RCHFCR_FSEL_Get(void)
|
{
|
return (CMU->RCHFCR & CMU_RCHFCR_FSEL_Msk);
|
}
|
|
/* RCHFʹÄܼĴæÆ÷ (RCHF Enable)
|
1£ºÊ¹ÄÜRCHF
|
0£º¹Ø±ÕRCHF Ïà¹Øº¯Êý */
|
void CMU_RCHFCR_RCHFEN_Setable(FunState NewState)
|
{
|
if (NewState == ENABLE)
|
{
|
CMU->RCHFCR |= (CMU_RCHFCR_RCHFEN_Msk);
|
}
|
else
|
{
|
CMU->RCHFCR &= ~(CMU_RCHFCR_RCHFEN_Msk);
|
}
|
}
|
|
FunState CMU_RCHFCR_RCHFEN_Getable(void)
|
{
|
if (CMU->RCHFCR & (CMU_RCHFCR_RCHFEN_Msk))
|
{
|
return ENABLE;
|
}
|
else
|
{
|
return DISABLE;
|
}
|
}
|
|
/* RCHFƵÂʵ÷У¼Ä´æÆ÷£¬8¡¯h00±íʾƵÂÊ×îµÍ£¬8¡¯hFF±íʾƵÂÊ×î¸ß£¬µ÷У·¶Î§ÎªÖÐÐÄƵÂÊ+/-30%£¬µ÷У²½³¤ÎªÖÐÐÄƵÂÊ0.25%
|
ÉϵçºóоƬ×Ô¶¯´ÓLDT0¶ÁÈ¡8MHzµ÷Уֵ²¢Ð´Èë´Ë¼Ä´æÆ÷
|
Èí¼þʹÓÃÆäËûƵÂÊʱ£¬¿ÉÒÔ×ÔÐдÓLDT0Ö¸¶¨µØÖ·¶ÁÈ¡µ÷УÐÅÏ¢²¢Ð´Èë´Ë¼Ä´æÆ÷£¬´Ó¶øÈ·±£Êä³öƵÂÊ׼ȷ¡£ Ïà¹Øº¯Êý */
|
void CMU_RCHFTR_RCHFTRIM_Set(uint32_t SetValue)
|
{
|
uint32_t tmpreg;
|
tmpreg = CMU->RCHFTR;
|
tmpreg &= ~(CMU_RCHFTR_RCHFTRIM_Msk);
|
tmpreg |= (SetValue & CMU_RCHFTR_RCHFTRIM_Msk);
|
CMU->RCHFTR = tmpreg;
|
}
|
|
uint32_t CMU_RCHFTR_RCHFTRIM_Get(void)
|
{
|
return (CMU->RCHFTR & CMU_RCHFTR_RCHFTRIM_Msk);
|
}
|
|
void CMU_PLLLCR_PLLDB_Set(uint32_t SetValue)
|
{
|
uint32_t tmpreg;
|
tmpreg = CMU->PLLLCR;
|
tmpreg &= ~(CMU_PLLLCR_PLLDB_Msk);
|
tmpreg |= (SetValue & CMU_PLLLCR_PLLDB_Msk);
|
CMU->PLLLCR = tmpreg;
|
}
|
|
uint32_t CMU_PLLLCR_PLLDB_Get(void)
|
{
|
return (CMU->PLLLCR & CMU_PLLLCR_PLLDB_Msk);
|
}
|
|
/* PLL_LËø¶¨±êÖ¾
|
1£ºPLL_LÒÑËø¶¨
|
0£ºPLL_LδËø¶¨ Ïà¹Øº¯Êý */
|
FlagStatus CMU_PLLLCR_LOCKED_Chk(void)
|
{
|
if (CMU->PLLLCR & CMU_PLLLCR_LOCKED_Msk)
|
{
|
return SET;
|
}
|
else
|
{
|
return RESET;
|
}
|
}
|
|
/* PLLʹÄܼĴæÆ÷
|
1£ºÊ¹ÄÜPLL
|
0£º¹Ø±ÕPLL Ïà¹Øº¯Êý */
|
void CMU_PLLLCR_PLLEN_Setable(FunState NewState)
|
{
|
if (NewState == ENABLE)
|
{
|
CMU->PLLLCR |= (CMU_PLLLCR_PLLEN_Msk);
|
}
|
else
|
{
|
CMU->PLLLCR &= ~(CMU_PLLLCR_PLLEN_Msk);
|
}
|
}
|
|
FunState CMU_PLLLCR_PLLEN_Getable(void)
|
{
|
if (CMU->PLLLCR & (CMU_PLLLCR_PLLEN_Msk))
|
{
|
return ENABLE;
|
}
|
else
|
{
|
return DISABLE;
|
}
|
}
|
|
/* PLLH±¶Æµ±È£¬²Î¿¼Ê±ÖÓ1Mhz
|
0000011111£ºÊä³ö32±¶Æµ
|
0101111£ºÊä³ö48±¶Æµ Ïà¹Øº¯Êý */
|
void CMU_PLLHCR_PLLHDB_Set(uint32_t SetValue)
|
{
|
uint32_t tmpreg;
|
tmpreg = CMU->PLLHCR;
|
tmpreg &= ~(CMU_PLLHCR_PLLHDB_Msk);
|
tmpreg |= (SetValue & CMU_PLLHCR_PLLHDB_Msk);
|
CMU->PLLHCR = tmpreg;
|
}
|
|
uint32_t CMU_PLLHCR_PLLHDB_Get(void)
|
{
|
return (CMU->PLLHCR & CMU_PLLHCR_PLLHDB_Msk);
|
}
|
|
/* PLLHËø¶¨±êÖ¾£¬Èí¼þͨ¹ý²éѯ´Ë¼Ä´æÆ÷È·ÈÏPLLÒѾ´¦ÓÚËø¶¨×´Ì¬
|
1£ºPLLÒÑËø¶¨
|
0£ºPLLδËø¶¨ Ïà¹Øº¯Êý */
|
FlagStatus CMU_PLLHCR_LOCKED_Chk(void)
|
{
|
if (CMU->PLLHCR & CMU_PLLHCR_LOCKED_Msk)
|
{
|
return SET;
|
}
|
else
|
{
|
return RESET;
|
}
|
}
|
|
/* PLLH²Î¿¼Ê±ÖÓÔ¤·ÖƵ£¨Ä¿±êÊDzúÉú1MHz²Î¿¼Ê±ÖÓ¸øPLL£©
|
000£º²»·ÖƵ
|
001£º2·ÖƵ
|
010£º4·ÖƵ
|
011£º8·ÖƵ
|
100£º12·ÖƵ
|
101£º16·ÖƵ
|
110£º24·ÖƵ
|
111£º32·ÖƵ Ïà¹Øº¯Êý */
|
void CMU_PLLHCR_REFPRSC_Set(uint32_t SetValue)
|
{
|
uint32_t tmpreg;
|
tmpreg = CMU->PLLHCR;
|
tmpreg &= ~(CMU_PLLHCR_REFPRSC_Msk);
|
tmpreg |= (SetValue & CMU_PLLHCR_REFPRSC_Msk);
|
CMU->PLLHCR = tmpreg;
|
}
|
|
uint32_t CMU_PLLHCR_REFPRSC_Get(void)
|
{
|
return (CMU->PLLHCR & CMU_PLLHCR_REFPRSC_Msk);
|
}
|
|
/* PLLHÊä³öÑ¡Ôñ¼Ä´æÆ÷
|
0£ºÑ¡ÔñPLLHÒ»±¶Êä³ö×÷ΪÊý×Öµç·ÄÚµÄPLLʱÖÓ
|
1£ºÑ¡ÔñPLLHÁ½±¶Êä³ö×÷ΪÊý×Öµç·ÄÚµÄPLLʱÖÓ Ïà¹Øº¯Êý */
|
void CMU_PLLHCR_OSEL_Set(uint32_t SetValue)
|
{
|
uint32_t tmpreg;
|
tmpreg = CMU->PLLHCR;
|
tmpreg &= ~(CMU_PLLHCR_OSEL_Msk);
|
tmpreg |= (SetValue & CMU_PLLHCR_OSEL_Msk);
|
CMU->PLLHCR = tmpreg;
|
}
|
|
uint32_t CMU_PLLHCR_OSEL_Get(void)
|
{
|
return (CMU->PLLHCR & CMU_PLLHCR_OSEL_Msk);
|
}
|
|
/* PLLHÊäÈëÑ¡Ôñ¼Ä´æÆ÷
|
0£ºRCHF
|
1£ºXTHF */
|
void CMU_PLLHCR_INSEL_Set(uint32_t SetValue)
|
{
|
uint32_t tmpreg;
|
tmpreg = CMU->PLLHCR;
|
tmpreg &= ~(CMU_PLLHCR_INSEL_Msk);
|
tmpreg |= (SetValue & CMU_PLLHCR_INSEL_Msk);
|
CMU->PLLHCR = tmpreg;
|
}
|
|
uint32_t CMU_PLLHCR_INSEL_Get(void)
|
{
|
return (CMU->PLLHCR & CMU_PLLHCR_INSEL_Msk);
|
}
|
|
/* PLLHʹÄܼĴæÆ÷
|
1£ºÊ¹ÄÜPLLH
|
0£º¹Ø±ÕPLLH Ïà¹Øº¯Êý */
|
void CMU_PLLHCR_EN_Setable(FunState NewState)
|
{
|
if (NewState == ENABLE)
|
{
|
CMU->PLLHCR |= (CMU_PLLHCR_EN_Msk);
|
}
|
else
|
{
|
CMU->PLLHCR &= ~(CMU_PLLHCR_EN_Msk);
|
}
|
}
|
|
FunState CMU_PLLHCR_EN_Getable(void)
|
{
|
if (CMU->PLLHCR & (CMU_PLLHCR_EN_Msk))
|
{
|
return ENABLE;
|
}
|
else
|
{
|
return DISABLE;
|
}
|
}
|
|
/* XTHFÕñµ´Ç¿¶ÈÅäÖÃ
|
000£º×îÈõ
|
111£º×îÇ¿ Ïà¹Øº¯Êý */
|
void CMU_XTHFCR_XTHF_CFG_Set(uint32_t SetValue)
|
{
|
uint32_t tmpreg;
|
tmpreg = CMU->XTHFCR;
|
tmpreg &= ~(CMU_XTHFCR_XTHF_CFG_Msk);
|
tmpreg |= (SetValue & CMU_XTHFCR_XTHF_CFG_Msk);
|
CMU->XTHFCR = tmpreg;
|
}
|
|
uint32_t CMU_XTHFCR_XTHF_CFG_Get(void)
|
{
|
return (CMU->XTHFCR & CMU_XTHFCR_XTHF_CFG_Msk);
|
}
|
|
/* XTHFʹÄܼĴæÆ÷
|
0£º¹Ø±ÕXTHF
|
1£ºÊ¹ÄÜXTHF Ïà¹Øº¯Êý */
|
void CMU_XTHFCR_XTHFEN_Setable(FunState NewState)
|
{
|
if (NewState == ENABLE)
|
{
|
CMU->XTHFCR |= (CMU_XTHFCR_XTHFEN_Msk);
|
}
|
else
|
{
|
CMU->XTHFCR &= ~(CMU_XTHFCR_XTHFEN_Msk);
|
}
|
}
|
|
FunState CMU_XTHFCR_XTHFEN_Getable(void)
|
{
|
if (CMU->XTHFCR & (CMU_XTHFCR_XTHFEN_Msk))
|
{
|
return ENABLE;
|
}
|
else
|
{
|
return DISABLE;
|
}
|
}
|
|
void CMU_IER_SYSCSE_IE_Setable(FunState NewState)
|
{
|
if (NewState == ENABLE)
|
{
|
CMU->IER |= (CMU_IER_SYSCSE_IE_Msk);
|
}
|
else
|
{
|
CMU->IER &= ~(CMU_IER_SYSCSE_IE_Msk);
|
}
|
}
|
|
FunState CMU_IER_SYSCSE_IE_Getable(void)
|
{
|
if (CMU->IER & (CMU_IER_SYSCSE_IE_Msk))
|
{
|
return ENABLE;
|
}
|
else
|
{
|
return DISABLE;
|
}
|
}
|
|
void CMU_IER_HFDET_IE_Setable(FunState NewState)
|
{
|
if (NewState == ENABLE)
|
{
|
CMU->IER |= (CMU_IER_HFDET_IE_Msk);
|
}
|
else
|
{
|
CMU->IER &= ~(CMU_IER_HFDET_IE_Msk);
|
}
|
}
|
|
FunState CMU_IER_HFDET_IE_Getable(void)
|
{
|
if (CMU->IER & (CMU_IER_HFDET_IE_Msk))
|
{
|
return ENABLE;
|
}
|
else
|
{
|
return DISABLE;
|
}
|
}
|
|
|
/* ¸ßƵ¾§ÌåÍ£Õñ¼ì²âÄ£¿éÊä³ö
|
1£ºXTHFδͣÕñ
|
0£ºXTHFÍ£Õñ Ïà¹Øº¯Êý */
|
FlagStatus CMU_ISR_HFDETO_Chk(void)
|
{
|
if (CMU->ISR & CMU_ISR_HFDETO_Msk)
|
{
|
return SET;
|
}
|
else
|
{
|
return RESET;
|
}
|
}
|
|
|
/* SYSCLKʱÖÓÑ¡Ôñ´íÎóÖжϱêÖ¾¼Ä´æÆ÷£»µ±±»Ñ¡ÖеÄʱÖÓԴûÓÐʹÄÜʱ£¬´ËÖжϱêÖ¾ÖÃ룬Èí¼þд1ÇåÁã¡£ Ïà¹Øº¯Êý */
|
void CMU_ISR_SYSCSE_IF_Clr(void)
|
{
|
CMU->ISR = CMU_ISR_SYSCSE_IF_Msk;
|
}
|
|
FlagStatus CMU_ISR_SYSCSE_IF_Chk(void)
|
{
|
if (CMU->ISR & CMU_ISR_SYSCSE_IF_Msk)
|
{
|
return SET;
|
}
|
else
|
{
|
return RESET;
|
}
|
}
|
|
/* ¸ßƵͣÕñ¼ì²âÖжϱêÖ¾¼Ä´æÆ÷£¬XTHFÍ£ÕñʱӲ¼þÒì²½ÖÃ룬Èí¼þд1ÇåÁ㣻ֻÓÐÔÚFFDETO²»Îª0µÄÇé¿öϲÅÄܹ»Çå³ý´Ë¼Ä´æÆ÷ Ïà¹Øº¯Êý */
|
void CMU_ISR_HFDET_IF_Clr(void)
|
{
|
CMU->ISR = CMU_ISR_HFDET_IF_Msk;
|
}
|
|
FlagStatus CMU_ISR_HFDET_IF_Chk(void)
|
{
|
if (CMU->ISR & CMU_ISR_HFDET_IF_Msk)
|
{
|
return SET;
|
}
|
else
|
{
|
return RESET;
|
}
|
}
|
|
/* EXTI¹¤×÷ʱÖÓʹÄÜ£¬¸ßÓÐЧ Ïà¹Øº¯Êý */
|
void CMU_OPCCR1_EXTICKE_Setable(FunState NewState)
|
{
|
if (NewState == ENABLE)
|
{
|
CMU->OPCCR1 |= (CMU_OPCCR1_EXTICKE_Msk);
|
}
|
else
|
{
|
CMU->OPCCR1 &= ~(CMU_OPCCR1_EXTICKE_Msk);
|
}
|
}
|
|
FunState CMU_OPCCR1_EXTICKE_Getable(void)
|
{
|
if (CMU->OPCCR1 & (CMU_OPCCR1_EXTICKE_Msk))
|
{
|
return ENABLE;
|
}
|
else
|
{
|
return DISABLE;
|
}
|
}
|
|
/* EXTIÖжϲÉÑùʱÖÓÑ¡Ôñ */
|
void CMU_OPCCR1_EXTICKSEL_Set(uint32_t SetValue)
|
{
|
uint32_t tmpreg;
|
tmpreg = CMU->OPCCR1;
|
tmpreg &= ~(CMU_OPCCR1_EXTICKSEL_Msk);
|
tmpreg |= (SetValue & CMU_OPCCR1_EXTICKSEL_Msk);
|
CMU->OPCCR1 = tmpreg;
|
}
|
|
uint32_t CMU_OPCCR1_EXTICKSEL_Get(void)
|
{
|
return (CMU->OPCCR1 & CMU_OPCCR1_EXTICKSEL_Msk);
|
}
|
|
/* LPUART1¹¤×÷ʱÖÓʹÄÜ£¬¸ßÓÐЧ Ïà¹Øº¯Êý */
|
void CMU_OPCCR1_LPUART1CKE_Setable(FunState NewState)
|
{
|
if (NewState == ENABLE)
|
{
|
CMU->OPCCR1 |= (CMU_OPCCR1_LPUART1CKE_Msk);
|
}
|
else
|
{
|
CMU->OPCCR1 &= ~(CMU_OPCCR1_LPUART1CKE_Msk);
|
}
|
}
|
|
FunState CMU_OPCCR1_LPUART1CKE_Getable(void)
|
{
|
if (CMU->OPCCR1 & (CMU_OPCCR1_LPUART1CKE_Msk))
|
{
|
return ENABLE;
|
}
|
else
|
{
|
return DISABLE;
|
}
|
}
|
|
/* LPUART0¹¤×÷ʱÖÓʹÄÜ£¬¸ßÓÐЧ Ïà¹Øº¯Êý */
|
void CMU_OPCCR1_LPUART0CKE_Setable(FunState NewState)
|
{
|
if (NewState == ENABLE)
|
{
|
CMU->OPCCR1 |= (CMU_OPCCR1_LPUART0CKE_Msk);
|
}
|
else
|
{
|
CMU->OPCCR1 &= ~(CMU_OPCCR1_LPUART0CKE_Msk);
|
}
|
}
|
|
FunState CMU_OPCCR1_LPUART0CKE_Getable(void)
|
{
|
if (CMU->OPCCR1 & (CMU_OPCCR1_LPUART0CKE_Msk))
|
{
|
return ENABLE;
|
}
|
else
|
{
|
return DISABLE;
|
}
|
}
|
|
/* LPUART1¹¤×÷ʱÖÓÑ¡Ôñ
|
00£ºLSCLK
|
01£ºRCHF·ÖƵ£¨¸ù¾ÝRCHFµµÎ»×Ô¶¯·ÖƵµ½32768Hz¸½½ü£©
|
10£ºRFU
|
11£ºRFU Ïà¹Øº¯Êý */
|
void CMU_OPCCR1_LPUART1CKS_Set(uint32_t SetValue)
|
{
|
uint32_t tmpreg;
|
tmpreg = CMU->OPCCR1;
|
tmpreg &= ~(CMU_OPCCR1_LPUART1CKS_Msk);
|
tmpreg |= (SetValue & CMU_OPCCR1_LPUART1CKS_Msk);
|
CMU->OPCCR1 = tmpreg;
|
}
|
|
uint32_t CMU_OPCCR1_LPUART1CKS_Get(void)
|
{
|
return (CMU->OPCCR1 & CMU_OPCCR1_LPUART1CKS_Msk);
|
}
|
|
/* LPUART0¹¤×÷ʱÖÓÑ¡Ôñ
|
00£ºLSCLK
|
01£ºRCHF·ÖƵ£¨¸ù¾ÝRCHFµµÎ»×Ô¶¯·ÖƵµ½32768Hz¸½½ü£©
|
10£ºRFU
|
11£ºRFU Ïà¹Øº¯Êý */
|
void CMU_OPCCR1_LPUART0CKS_Set(uint32_t SetValue)
|
{
|
uint32_t tmpreg;
|
tmpreg = CMU->OPCCR1;
|
tmpreg &= ~(CMU_OPCCR1_LPUART0CKS_Msk);
|
tmpreg |= (SetValue & CMU_OPCCR1_LPUART0CKS_Msk);
|
CMU->OPCCR1 = tmpreg;
|
}
|
|
uint32_t CMU_OPCCR1_LPUART0CKS_Get(void)
|
{
|
return (CMU->OPCCR1 & CMU_OPCCR1_LPUART0CKS_Msk);
|
}
|
|
/* I2C1¹¤×÷ʱÖÓʹÄÜ Ïà¹Øº¯Êý */
|
void CMU_OPCCR1_I2C1CKE_Setable(FunState NewState)
|
{
|
if (NewState == ENABLE)
|
{
|
CMU->OPCCR1 |= (CMU_OPCCR1_I2C1CKE_Msk);
|
}
|
else
|
{
|
CMU->OPCCR1 &= ~(CMU_OPCCR1_I2C1CKE_Msk);
|
}
|
}
|
|
FunState CMU_OPCCR1_I2C1CKE_Getable(void)
|
{
|
if (CMU->OPCCR1 & (CMU_OPCCR1_I2C1CKE_Msk))
|
{
|
return ENABLE;
|
}
|
else
|
{
|
return DISABLE;
|
}
|
}
|
|
/* I2C0¹¤×÷ʱÖÓʹÄÜ Ïà¹Øº¯Êý */
|
void CMU_OPCCR1_I2C0CKE_Setable(FunState NewState)
|
{
|
if (NewState == ENABLE)
|
{
|
CMU->OPCCR1 |= (CMU_OPCCR1_I2C0CKE_Msk);
|
}
|
else
|
{
|
CMU->OPCCR1 &= ~(CMU_OPCCR1_I2C0CKE_Msk);
|
}
|
}
|
|
FunState CMU_OPCCR1_I2C0CKE_Getable(void)
|
{
|
if (CMU->OPCCR1 & (CMU_OPCCR1_I2C0CKE_Msk))
|
{
|
return ENABLE;
|
}
|
else
|
{
|
return DISABLE;
|
}
|
}
|
|
/* I2C1Ö÷»ú¹¤×÷ʱÖÓÑ¡Ôñ
|
00£ºAPBCLK
|
01£ºRCHF
|
10£ºSYSCLK
|
11£ºAPBCLK Ïà¹Øº¯Êý */
|
void CMU_OPCCR1_I2C1CKS_Set(uint32_t SetValue)
|
{
|
uint32_t tmpreg;
|
tmpreg = CMU->OPCCR1;
|
tmpreg &= ~(CMU_OPCCR1_I2C1CKS_Msk);
|
tmpreg |= (SetValue & CMU_OPCCR1_I2C1CKS_Msk);
|
CMU->OPCCR1 = tmpreg;
|
}
|
|
uint32_t CMU_OPCCR1_I2C1CKS_Get(void)
|
{
|
return (CMU->OPCCR1 & CMU_OPCCR1_I2C1CKS_Msk);
|
}
|
|
|
/* I2C0Ö÷»ú¹¤×÷ʱÖÓÑ¡Ôñ
|
00£ºAPBCLK
|
01£ºRCHF
|
10£ºSYSCLK
|
11£ºAPBCLK Ïà¹Øº¯Êý */
|
void CMU_OPCCR1_I2C0CKS_Set(uint32_t SetValue)
|
{
|
uint32_t tmpreg;
|
tmpreg = CMU->OPCCR1;
|
tmpreg &= ~(CMU_OPCCR1_I2C0CKS_Msk);
|
tmpreg |= (SetValue & CMU_OPCCR1_I2C0CKS_Msk);
|
CMU->OPCCR1 = tmpreg;
|
}
|
|
uint32_t CMU_OPCCR1_I2C0CKS_Get(void)
|
{
|
return (CMU->OPCCR1 & CMU_OPCCR1_I2C0CKS_Msk);
|
}
|
|
/* UART1¹¤×÷ʱÖÓʹÄÜ£¬¸ßÓÐЧ Ïà¹Øº¯Êý */
|
void CMU_OPCCR1_UART1CKE_Setable(FunState NewState)
|
{
|
if (NewState == ENABLE)
|
{
|
CMU->OPCCR1 |= (CMU_OPCCR1_UART1CKE_Msk);
|
}
|
else
|
{
|
CMU->OPCCR1 &= ~(CMU_OPCCR1_UART1CKE_Msk);
|
}
|
}
|
|
FunState CMU_OPCCR1_UART1CKE_Getable(void)
|
{
|
if (CMU->OPCCR1 & (CMU_OPCCR1_UART1CKE_Msk))
|
{
|
return ENABLE;
|
}
|
else
|
{
|
return DISABLE;
|
}
|
}
|
|
/* UART0¹¤×÷ʱÖÓʹÄÜ£¬¸ßÓÐЧ Ïà¹Øº¯Êý */
|
void CMU_OPCCR1_UART0CKE_Setable(FunState NewState)
|
{
|
if (NewState == ENABLE)
|
{
|
CMU->OPCCR1 |= (CMU_OPCCR1_UART0CKE_Msk);
|
}
|
else
|
{
|
CMU->OPCCR1 &= ~(CMU_OPCCR1_UART0CKE_Msk);
|
}
|
}
|
|
FunState CMU_OPCCR1_UART0CKE_Getable(void)
|
{
|
if (CMU->OPCCR1 & (CMU_OPCCR1_UART0CKE_Msk))
|
{
|
return ENABLE;
|
}
|
else
|
{
|
return DISABLE;
|
}
|
}
|
|
/* UART1¹¤×÷ʱÖÓÑ¡Ôñ
|
00£ºAPBCLK
|
01£ºRCHF
|
10£ºSYSCLK
|
11£ºRFU Ïà¹Øº¯Êý */
|
void CMU_OPCCR1_UART1CKS_Set(uint32_t SetValue)
|
{
|
uint32_t tmpreg;
|
tmpreg = CMU->OPCCR1;
|
tmpreg &= ~(CMU_OPCCR1_UART1CKS_Msk);
|
tmpreg |= (SetValue & CMU_OPCCR1_UART1CKS_Msk);
|
CMU->OPCCR1 = tmpreg;
|
}
|
|
uint32_t CMU_OPCCR1_UART1CKS_Get(void)
|
{
|
return (CMU->OPCCR1 & CMU_OPCCR1_UART1CKS_Msk);
|
}
|
|
/* UART0¹¤×÷ʱÖÓÑ¡Ôñ
|
00£ºAPBCLK
|
01£ºRCHF
|
10£ºSYSCLK
|
11£ºRFU Ïà¹Øº¯Êý */
|
void CMU_OPCCR1_UART0CKS_Set(uint32_t SetValue)
|
{
|
uint32_t tmpreg;
|
tmpreg = CMU->OPCCR1;
|
tmpreg &= ~(CMU_OPCCR1_UART0CKS_Msk);
|
tmpreg |= (SetValue & CMU_OPCCR1_UART0CKS_Msk);
|
CMU->OPCCR1 = tmpreg;
|
}
|
|
uint32_t CMU_OPCCR1_UART0CKS_Get(void)
|
{
|
return (CMU->OPCCR1 & CMU_OPCCR1_UART0CKS_Msk);
|
}
|
|
/* Ëæ»úÊý·¢ÉúÆ÷¹¤×÷ʱÖÓ·ÖƵ
|
000£º²»·ÖƵ
|
001£º2·ÖƵ
|
010£º4·ÖƵ
|
011£º8·ÖƵ
|
100£º16·ÖƵ
|
101£º32·ÖƵ
|
110, 111£ºRFU Ïà¹Øº¯Êý */
|
void CMU_OPCCR2_RNGPRSC_Set(uint32_t SetValue)
|
{
|
uint32_t tmpreg;
|
tmpreg = CMU->OPCCR2;
|
tmpreg &= ~(CMU_OPCCR2_RNGPRSC_Msk);
|
tmpreg |= (SetValue & CMU_OPCCR2_RNGPRSC_Msk);
|
CMU->OPCCR2 = tmpreg;
|
}
|
|
uint32_t CMU_OPCCR2_RNGPRSC_Get(void)
|
{
|
return (CMU->OPCCR2 & CMU_OPCCR2_RNGPRSC_Msk);
|
}
|
|
/* Flash²ÁдʱÖÓʹÄÜ£¬¸ßÓÐЧ Ïà¹Øº¯Êý */
|
void CMU_OPCCR2_NVMCKE_Setable(FunState NewState)
|
{
|
if (NewState == ENABLE)
|
{
|
CMU->OPCCR2 |= (CMU_OPCCR2_NVMCKE_Msk);
|
}
|
else
|
{
|
CMU->OPCCR2 &= ~(CMU_OPCCR2_NVMCKE_Msk);
|
}
|
}
|
|
FunState CMU_OPCCR2_NVMCKE_Getable(void)
|
{
|
if (CMU->OPCCR2 & (CMU_OPCCR2_NVMCKE_Msk))
|
{
|
return ENABLE;
|
}
|
else
|
{
|
return DISABLE;
|
}
|
}
|
|
/* Ëæ»úÊý·¢ÉúÆ÷¹¤×÷ʱÖÓʹÄÜ£¬¸ßÓÐЧ Ïà¹Øº¯Êý */
|
void CMU_OPCCR2_RNGCKE_Setable(FunState NewState)
|
{
|
if (NewState == ENABLE)
|
{
|
CMU->OPCCR2 |= (CMU_OPCCR2_RNGCKE_Msk);
|
}
|
else
|
{
|
CMU->OPCCR2 &= ~(CMU_OPCCR2_RNGCKE_Msk);
|
}
|
}
|
|
FunState CMU_OPCCR2_RNGCKE_Getable(void)
|
{
|
if (CMU->OPCCR2 & (CMU_OPCCR2_RNGCKE_Msk))
|
{
|
return ENABLE;
|
}
|
else
|
{
|
return DISABLE;
|
}
|
}
|
|
/* _¹¤×÷ʱÖÓʹÄÜ£¬¸ßÓÐЧ Ïà¹Øº¯Êý */
|
void CMU_OPCCR2_LPTCKE_Setable(FunState NewState)
|
{
|
if (NewState == ENABLE)
|
{
|
CMU->OPCCR2 |= (CMU_OPCCR2_LPTCKE_Msk);
|
}
|
else
|
{
|
CMU->OPCCR2 &= ~(CMU_OPCCR2_LPTCKE_Msk);
|
}
|
}
|
|
FunState CMU_OPCCR2_LPTCKE_Getable(void)
|
{
|
if (CMU->OPCCR2 & (CMU_OPCCR2_LPTCKE_Msk))
|
{
|
return ENABLE;
|
}
|
else
|
{
|
return DISABLE;
|
}
|
}
|
|
/* _¹¤×÷ʱÖÓÑ¡Ôñ
|
00£ºAPBCLK
|
01£ºLSCLK
|
10£ºRCLP
|
11£ºPLL_L Ïà¹Øº¯Êý */
|
void CMU_OPCCR2_LPTCKS_Set(uint32_t SetValue)
|
{
|
uint32_t tmpreg;
|
tmpreg = CMU->OPCCR2;
|
tmpreg &= ~(CMU_OPCCR2_LPTCKS_Msk);
|
tmpreg |= (SetValue & CMU_OPCCR2_LPTCKS_Msk);
|
CMU->OPCCR2 = tmpreg;
|
}
|
|
uint32_t CMU_OPCCR2_LPTCKS_Get(void)
|
{
|
return (CMU->OPCCR2 & CMU_OPCCR2_LPTCKS_Msk);
|
}
|
|
/* BSTIM¹¤×÷ʱÖÓʹÄÜ£¬¸ßÓÐЧ Ïà¹Øº¯Êý */
|
void CMU_OPCCR2_BSTCKE_Setable(FunState NewState)
|
{
|
if (NewState == ENABLE)
|
{
|
CMU->OPCCR2 |= (CMU_OPCCR2_BSTCKE_Msk);
|
}
|
else
|
{
|
CMU->OPCCR2 &= ~(CMU_OPCCR2_BSTCKE_Msk);
|
}
|
}
|
|
FunState CMU_OPCCR2_BSTCKE_Getable(void)
|
{
|
if (CMU->OPCCR2 & (CMU_OPCCR2_BSTCKE_Msk))
|
{
|
return ENABLE;
|
}
|
else
|
{
|
return DISABLE;
|
}
|
}
|
|
/* BSTIM¹¤×÷ʱÖÓÔ´Ñ¡Ôñ
|
00£ºAPBCLK
|
01£ºLSCLK
|
10£ºRCLP
|
11£ºSYSCLK Ïà¹Øº¯Êý */
|
void CMU_OPCCR2_BSTCKS_Set(uint32_t SetValue)
|
{
|
uint32_t tmpreg;
|
tmpreg = CMU->OPCCR2;
|
tmpreg &= ~(CMU_OPCCR2_BSTCKS_Msk);
|
tmpreg |= (SetValue & CMU_OPCCR2_BSTCKS_Msk);
|
CMU->OPCCR2 = tmpreg;
|
}
|
|
uint32_t CMU_OPCCR2_BSTCKS_Get(void)
|
{
|
return (CMU->OPCCR2 & CMU_OPCCR2_BSTCKS_Msk);
|
}
|
|
void CMU_Deinit(void)
|
{
|
//CMU->SYSCLKCR = ;
|
//CMU->RCHFCR = 0x00000000;
|
//CMU->RCHFTR = 0x00000000;
|
//CMU->PLLLCR = ;
|
//CMU->PLLHCR = 0x00000000;
|
//CMU->XTHFCR = 0x00000000;
|
//CMU->IER = ;
|
//CMU->ISR = ;
|
//CMU->PCLKCR1 = 0x00000058;
|
//CMU->PCLKCR2 = 0x00000000;
|
//CMU->PCLKCR3 = 0x00000000;
|
//CMU->PCLKCR4 = ;
|
//CMU->OPCCR1 = 0x00000000;
|
//CMU->OPCCR2 = 0x00000000;
|
}
|
//Code_End
|
|
|
/********************************
|
»ñȡоƬÒÑÉèÖõIJ»Í¬Ê±ÖÓƵÂʺ¯Êý
|
¹¦ÄÜ:»ñȡоƬÒÑÉèÖõIJ»Í¬Ê±ÖÓƵÂÊ
|
RCHF_Frequency
|
PLL_H_Frequency
|
SYSCLK_Frequency
|
AHBCLK_Frequency
|
APBCLK_Frequency
|
********************************/
|
void CMU_GetClocksFreq(CMU_ClocksType* para)
|
{
|
uint32_t tmp32 = 0;
|
para->RCHF_Frequency = 0;
|
para->PLL_H_Frequency = 0;
|
para->SYSCLK_Frequency = 0;
|
para->AHBCLK_Frequency = 0;
|
para->APBCLK_Frequency = 0;
|
|
/* Get RCHF FSEL */
|
if(ENABLE == CMU_RCHFCR_RCHFEN_Getable())
|
{
|
tmp32 = CMU_RCHFCR_FSEL_Get();
|
tmp32 = tmp32 >> CMU_RCHFCR_FSEL_Pos;
|
/* RCHF clock frequency */
|
para->RCHF_Frequency = __RCHF_INITIAL_CLOCK * (tmp32 + 1);
|
|
}
|
|
if(ENABLE == CMU_PLLHCR_EN_Getable())
|
{
|
/* PLLH±¶Æµ±È */
|
tmp32 = CMU_PLLHCR_PLLHDB_Get();
|
tmp32 = tmp32 >> CMU_PLLHCR_PLLHDB_Pos;
|
para->PLL_H_Frequency = (tmp32 + 1) * 1000000;
|
/* PLLHÊä³öÑ¡Ôñ¼Ä´æÆ÷ */
|
if( CMU_PLLHCR_OSEL_X2 == CMU_PLLHCR_OSEL_Get() )
|
{
|
para->PLL_H_Frequency = (para->PLL_H_Frequency)*2;
|
}
|
}
|
|
/* Get SYSCLK source */
|
tmp32 = CMU_SYSCLKCR_SYSCLKSEL_Get();
|
tmp32 = tmp32 >> CMU_SYSCLKCR_SYSCLKSEL_Pos;
|
switch (tmp32)
|
{
|
case 0x00: /* RCHF used as system clock source */
|
para->SYSCLK_Frequency = para->RCHF_Frequency;
|
break;
|
case 0x01: /* XTHF used as system clock source */
|
para->SYSCLK_Frequency = __XTHF_CLOCK;
|
break;
|
case 0x02: /* PLL_H used as system clock source */
|
para->SYSCLK_Frequency = para->PLL_H_Frequency;
|
break;
|
case 0x03: /* LSCLK used as system clock source */
|
para->SYSCLK_Frequency = __XTLF_CLOCK;
|
break;
|
default:
|
para->SYSCLK_Frequency = para->RCHF_Frequency;
|
break;
|
}
|
|
/* Get AHB PRES */
|
tmp32 = CMU_SYSCLKCR_AHBPRES_Get();
|
tmp32 = tmp32 >> CMU_SYSCLKCR_AHBPRES_Pos;
|
switch(tmp32)
|
{
|
case 0x04: //100:DIV2
|
para->AHBCLK_Frequency = para->SYSCLK_Frequency/2;
|
break;
|
case 0x05: //101:DIV4
|
para->AHBCLK_Frequency = para->SYSCLK_Frequency/4;
|
break;
|
case 0x06: //110:DIV8
|
para->AHBCLK_Frequency = para->SYSCLK_Frequency/8;
|
break;
|
case 0x07: //111:DIV16
|
para->AHBCLK_Frequency = para->SYSCLK_Frequency/16;
|
break;
|
default: //0XX:DIV1
|
para->AHBCLK_Frequency = para->SYSCLK_Frequency;
|
break;
|
}
|
|
/* Get APB PRES */
|
tmp32 = CMU_SYSCLKCR_APBPRES_Get();
|
tmp32 = tmp32 >> CMU_SYSCLKCR_APBPRES_Pos;
|
/* APB clock frequency */
|
switch(tmp32)
|
{
|
case 0x04: //100:DIV2
|
para->APBCLK_Frequency = para->AHBCLK_Frequency/2;
|
break;
|
case 0x05: //101:DIV4
|
para->APBCLK_Frequency = para->AHBCLK_Frequency/4;
|
break;
|
case 0x06: //110:DIV8
|
para->APBCLK_Frequency = para->AHBCLK_Frequency/8;
|
break;
|
case 0x07: //111:DIV16
|
para->APBCLK_Frequency = para->AHBCLK_Frequency/16;
|
break;
|
default: //0XX:DIV1
|
para->APBCLK_Frequency = para->AHBCLK_Frequency;
|
break;
|
}
|
}
|
|
|
/********************************
|
ÍâÉèʱÖÓʹÄܺ¯Êý
|
¹¦ÄÜ:¶ÔÍâÉèÄ£¿éËùÐèÒªµÄ¶ÔӦʱÖÓ½øÐÐʹÄÜ
|
ÊäÈ룺periph_defÍⲿģ¿é±êºÅ
|
NewStateʹÄÜλ
|
********************************/
|
void CMU_PERCLK_SetableEx(uint32_t periph_def, FunState NewState)
|
{
|
__IO uint32_t *p_reg = 0;
|
uint32_t TempREG;
|
|
switch((periph_def & 0x0F000000))
|
{
|
case 0x01000000:
|
p_reg = &(CMU->PCLKCR1);
|
break;
|
|
case 0x02000000:
|
p_reg = &(CMU->PCLKCR2);
|
break;
|
|
case 0x03000000:
|
p_reg = &(CMU->PCLKCR3);
|
break;
|
|
case 0x04000000:
|
p_reg = &(CMU->PCLKCR4);
|
break;
|
|
default:
|
break;
|
}
|
if(p_reg)
|
{
|
periph_def &= 0xFFFF;
|
TempREG = (0x1U << periph_def);
|
|
if (NewState != DISABLE)
|
{
|
*p_reg |= TempREG;
|
}
|
else
|
{
|
*p_reg &= ~TempREG;
|
}
|
}
|
}
|
|
|
/********************************
|
RCHF³õʼ»¯º¯Êý
|
¹¦ÄÜ:¶ÔRCHF½øÐгõʼ»¯
|
ÊäÈ룺RCHFƵÂʺÍʹÄÜ
|
********************************/
|
void CMU_RCHF_Init(CMU_RCHF_InitTypeDef* para)
|
{
|
CMU_RCHFCR_FSEL_Set(para->FSEL);
|
CMU_RCHFCR_RCHFEN_Setable(para->RCHFEN);
|
}
|
|
/********************************
|
PLL H³õʼ»¯º¯Êý
|
¹¦ÄÜ:¶ÔPLL H½øÐгõʼ»¯
|
ÊäÈ룺¶ÔPLL HÉèÖõÄÏà¹Ø²ÎÊý
|
********************************/
|
void CMU_PLL_H_Init(CMU_PLL_H_InitTypeDef* para)
|
{
|
CMU_PLLHCR_PLLHDB_Set(para->PLLHDB);
|
CMU_PLLHCR_REFPRSC_Set(para->REFPRSC);
|
CMU_PLLHCR_OSEL_Set(para->PLLH_OSEL);
|
CMU_PLLHCR_INSEL_Set(para->PLLH_INSEL);
|
CMU_PLLHCR_EN_Setable(para->PLLH_EN);
|
}
|
|
/* ϵͳʱÖÓ³õʼ»¯ */
|
void CMU_SysClk_Init(CMU_SYSCLK_InitTypeDef* para)
|
{
|
CMU_SYSCLKCR_SYSCLKSEL_Set(para->SYSCLKSEL);
|
CMU_SYSCLKCR_AHBPRES_Set(para->AHBPRES);
|
CMU_SYSCLKCR_APBPRES_Set(para->APBPRES);
|
CMU_SYSCLKCR_SLP_ENEXTI_Setable(para->SLP_ENEXTI);
|
}
|
|
/********************************
|
rchf³£ÎÂУ׼ֵÔØÈ뺯Êý
|
¹¦ÄÜ:rchf³£ÎÂУ׼ֵÔØÈë(rchf³£ÎÂУ׼ֵÔØÈë(оƬ¸´Î»ºó×Ô¶¯ÔØÈë8MµÄУ׼ֵ))
|
ÊäÈ룺ҪÉèÖõÄRCHFƵÂÊ
|
ClkMode 1 = 8M
|
ClkMode 2 = 16M
|
ClkMode 3 = 24M
|
ClkMode 4 = 32M
|
********************************/
|
void CMU_Init_RCHF_Trim( uint8_t ClkMode )
|
{
|
uint32_t Temp32;
|
|
if( ClkMode == 1 ) //8M
|
{
|
Temp32 = const_rchf_Trim8;
|
}
|
else if( ClkMode == 2 )//16M
|
{
|
Temp32 = const_rchf_Trim16;
|
}
|
else if( ClkMode == 3 )//24M
|
{
|
Temp32 = const_rchf_Trim24;
|
}
|
else if( ClkMode == 4 )//32M
|
{
|
Temp32 = const_rchf_Trim32;
|
}
|
else//ĬÈÏ8M
|
{
|
Temp32 = const_rchf_Trim8;
|
}
|
|
if( ((Temp32>>16)&0x0000FFFF) == ((~Temp32)&0x0000FFFF) ) //Õý·´ÂëУÑéÅжÏ
|
{
|
CMU_RCHFTR_RCHFTRIM_Set(Temp32&0x000000FF);
|
}
|
else
|
{
|
CMU_RCHFTR_RCHFTRIM_Set(0x0000006B);
|
}
|
}
|
|
/******END OF FILE****/
|
