/**
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******************************************************************************
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* @file fm33a0xxev_lptim.c
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* @author FM33A0XXEV Application Team
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* @version V1.0.0
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* @date 16-April-2020
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* @brief This file provides firmware functions to manage the following
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* functionalities of....:
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*
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "fm33a0xxev_lptim.h"
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/** @addtogroup fm33a0xxev_StdPeriph_Driver
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* @{
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*/
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/** @defgroup LPTIM
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* @brief LPTIM driver modules
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* @{
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*/
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/* LPT_ETRÊäÈëÄ£ÄâÂ˲¨Ê¹ÄÜ(External Trigger input Analog Filter Enable)
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0£º¹Ø±ÕÄ£ÄâÂ˲¨
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1£ºÊ¹ÄÜÄ£ÄâÂ˲¨£¬Â˲¨¿í¶ÈÔ¼100ns Ïà¹Øº¯Êý */
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void LPTIM_CFGR_ETR_AFEN_Setable(FunState NewState)
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{
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if (NewState == ENABLE)
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{
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LPTIM->CFGR |= (LPTIM_CFGR_ETR_AFEN_Msk);
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}
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else
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{
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LPTIM->CFGR &= ~(LPTIM_CFGR_ETR_AFEN_Msk);
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}
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}
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FunState LPTIM_CFGR_ETR_AFEN_Getable(void)
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{
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if (LPTIM->CFGR & (LPTIM_CFGR_ETR_AFEN_Msk))
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{
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return ENABLE;
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}
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else
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{
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return DISABLE;
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}
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}
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/* ʱÖÓÔ¤·ÖƵÊäÈëÑ¡Ôñ(Prescaler input Select)
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0£ºCLKSELÑ¡ÔñµÄʱÖÓ
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1£ºLPTETRF Ïà¹Øº¯Êý */
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void LPTIM_CFGR_PSCSEL_Set(uint32_t SetValue)
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{
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uint32_t tmpreg;
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tmpreg = LPTIM->CFGR;
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tmpreg &= ~(LPTIM_CFGR_PSCSEL_Msk);
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tmpreg |= (SetValue & LPTIM_CFGR_PSCSEL_Msk);
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LPTIM->CFGR = tmpreg;
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}
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uint32_t LPTIM_CFGR_PSCSEL_Get(void)
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{
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return (LPTIM->CFGR & LPTIM_CFGR_PSCSEL_Msk);
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}
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/* ¼ÆÊýʱÖÓ·ÖƵѡÔñ(Counter Clock Divider Select)
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000£º1·ÖƵ
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001£º2·ÖƵ
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010£º4·ÖƵ
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011£º8·ÖƵ
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100£º16·ÖƵ
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101£º32·ÖƵ
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110£º64·ÖƵ
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111£º128·ÖƵ Ïà¹Øº¯Êý */
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void LPTIM_CFGR_DIVSEL_Set(uint32_t SetValue)
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{
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uint32_t tmpreg;
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tmpreg = LPTIM->CFGR;
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tmpreg &= ~(LPTIM_CFGR_DIVSEL_Msk);
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tmpreg |= (SetValue & LPTIM_CFGR_DIVSEL_Msk);
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LPTIM->CFGR = tmpreg;
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}
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uint32_t LPTIM_CFGR_DIVSEL_Get(void)
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{
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return (LPTIM->CFGR & LPTIM_CFGR_DIVSEL_Msk);
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}
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/* ETRÊäÈë±ßÑØÑ¡Ôñ(ETR Clock Edge Select)
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0£ºLPT_ETRµÄÉÏÉýÑؼÆÊý
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1£ºLPT_ETRµÄϽµÑؼÆÊý Ïà¹Øº¯Êý */
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void LPTIM_CFGR_EDGESEL_Set(uint32_t SetValue)
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{
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uint32_t tmpreg;
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tmpreg = LPTIM->CFGR;
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tmpreg &= ~(LPTIM_CFGR_EDGESEL_Msk);
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tmpreg |= (SetValue & LPTIM_CFGR_EDGESEL_Msk);
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LPTIM->CFGR = tmpreg;
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}
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uint32_t LPTIM_CFGR_EDGESEL_Get(void)
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{
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return (LPTIM->CFGR & LPTIM_CFGR_EDGESEL_Msk);
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}
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/* Íⲿ´¥·¢±ßÑØÑ¡Ôñ£¨ÐèʹÓÃÄÚ²¿Ê±ÖÓͬ²½²ÉÑùLPT_ETR£©(ETR trigger Configuration)
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00: LPT_ETRÊäÈëÐźÅÉÏÉýÑØ´¥·¢
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01: LPT_ETRÊäÈëÐźÅϽµÑØ´¥·¢
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10/11: ÍⲿÊäÈëÐźÅÉÏÉýϽµÑØ´¥·¢ Ïà¹Øº¯Êý */
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void LPTIM_CFGR_TRIGCFG_Set(uint32_t SetValue)
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{
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uint32_t tmpreg;
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tmpreg = LPTIM->CFGR;
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tmpreg &= ~(LPTIM_CFGR_TRIGCFG_Msk);
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tmpreg |= (SetValue & LPTIM_CFGR_TRIGCFG_Msk);
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LPTIM->CFGR = tmpreg;
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}
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uint32_t LPTIM_CFGR_TRIGCFG_Get(void)
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{
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return (LPTIM->CFGR & LPTIM_CFGR_TRIGCFG_Msk);
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}
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/* µ¥´Î¼ÆÊýģʽʹÄÜ(One State Timer)
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0£ºÁ¬Ðø¼ÆÊýģʽ£º¼ÆÊýÆ÷±»´¥·¢ºó±£³ÖÔËÐУ¬Ö±µ½±»¹Ø±ÕΪֹ¡£¼ÆÊýÆ÷´ïµ½Ä¿±êÖµºó»Øµ½0ÖØпªÊ¼¼ÆÊý£¬²¢²úÉúÒç³öÖжϡ£
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1£ºµ¥´Î¼ÆÊýģʽ£º¼ÆÊýÆ÷±»´¥·¢ºó¼ÆÊýµ½Ä¿±êÖµºó»Øµ½0£¬²¢×Ô¶¯Í£Ö¹£¬²úÉúÒç³öÖжϡ£ Ïà¹Øº¯Êý */
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void LPTIM_CFGR_ONST_Set(uint32_t SetValue)
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{
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uint32_t tmpreg;
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tmpreg = LPTIM->CFGR;
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tmpreg &= ~(LPTIM_CFGR_ONST_Msk);
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tmpreg |= (SetValue & LPTIM_CFGR_ONST_Msk);
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LPTIM->CFGR = tmpreg;
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}
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uint32_t LPTIM_CFGR_ONST_Get(void)
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{
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return (LPTIM->CFGR & LPTIM_CFGR_ONST_Msk);
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}
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/* ¹¤×÷ģʽѡÔñ(Timer operation Mode)
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00£ºÆÕͨ¶¨Ê±Æ÷ģʽ
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01£ºTriggerÂö³å´¥·¢¼ÆÊýģʽ
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10£ºÍⲿÒì²½Âö³å¼ÆÊýģʽ
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11£ºTimeoutģʽ Ïà¹Øº¯Êý */
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void LPTIM_CFGR_TMODE_Set(uint32_t SetValue)
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{
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uint32_t tmpreg;
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tmpreg = LPTIM->CFGR;
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tmpreg &= ~(LPTIM_CFGR_TMODE_Msk);
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tmpreg |= (SetValue & LPTIM_CFGR_TMODE_Msk);
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LPTIM->CFGR = tmpreg;
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}
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uint32_t LPTIM_CFGR_TMODE_Get(void)
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{
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return (LPTIM->CFGR & LPTIM_CFGR_TMODE_Msk);
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}
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/* 32bit¼ÆÊýÆ÷µ±Ç°¼ÆÊýÖµ(Counter 32bits-wide) Ïà¹Øº¯Êý */
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uint32_t LPTIM_CNTR_Read(void)
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{
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return (LPTIM->CNTR);
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}
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/* ͨµÀ1²¶×½Ô´Ñ¡Ôñ(Capture channel 1 source select)£¬½öÔÚCH1ͨµÀÅäÖÃΪÊäÈ벶׽ʱÓÐЧ
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00£ºLPT_CH1ÊäÈë
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01£ºXTLF
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10£ºRCLP
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11£ºRCMF Ïà¹Øº¯Êý */
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void LPTIM_CCSR_CAP1SSEL_Set(uint32_t SetValue)
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{
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uint32_t tmpreg;
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tmpreg = LPTIM->CCSR;
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tmpreg &= ~(LPTIM_CCSR_CAP1SSEL_Msk);
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tmpreg |= (SetValue & LPTIM_CCSR_CAP1SSEL_Msk);
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LPTIM->CCSR = tmpreg;
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}
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uint32_t LPTIM_CCSR_CAP1SSEL_Get(void)
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{
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return (LPTIM->CCSR & LPTIM_CCSR_CAP1SSEL_Msk);
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}
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/* ͨµÀ4µ±Ç°±»²¶×½µÄ±ßÑØ£¬ÔÚCC2IFÖÃλʱ¸üÐÂ(Channel 4 Captured Edge)
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0£ºÉÏÉýÑØ
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1£ºÏ½µÑØ Ïà¹Øº¯Êý */
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void LPTIM_CCSR_CAP4EDGE_Set(uint32_t SetValue)
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{
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uint32_t tmpreg;
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tmpreg = LPTIM->CCSR;
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tmpreg &= ~(LPTIM_CCSR_CAP4EDGE_Msk);
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tmpreg |= (SetValue & LPTIM_CCSR_CAP4EDGE_Msk);
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LPTIM->CCSR = tmpreg;
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}
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uint32_t LPTIM_CCSR_CAP4EDGE_Get(void)
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{
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return (LPTIM->CCSR & LPTIM_CCSR_CAP4EDGE_Msk);
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}
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void LPTIM_CCSR_CAP3EDGE_Set(uint32_t SetValue)
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{
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uint32_t tmpreg;
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tmpreg = LPTIM->CCSR;
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tmpreg &= ~(LPTIM_CCSR_CAP3EDGE_Msk);
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tmpreg |= (SetValue & LPTIM_CCSR_CAP3EDGE_Msk);
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LPTIM->CCSR = tmpreg;
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}
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uint32_t LPTIM_CCSR_CAP3EDGE_Get(void)
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{
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return (LPTIM->CCSR & LPTIM_CCSR_CAP3EDGE_Msk);
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}
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void LPTIM_CCSR_CAP2EDGE_Set(uint32_t SetValue)
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{
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uint32_t tmpreg;
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tmpreg = LPTIM->CCSR;
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tmpreg &= ~(LPTIM_CCSR_CAP2EDGE_Msk);
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tmpreg |= (SetValue & LPTIM_CCSR_CAP2EDGE_Msk);
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LPTIM->CCSR = tmpreg;
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}
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uint32_t LPTIM_CCSR_CAP2EDGE_Get(void)
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{
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return (LPTIM->CCSR & LPTIM_CCSR_CAP2EDGE_Msk);
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}
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void LPTIM_CCSR_CAP1EDGE_Set(uint32_t SetValue)
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{
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uint32_t tmpreg;
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tmpreg = LPTIM->CCSR;
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tmpreg &= ~(LPTIM_CCSR_CAP1EDGE_Msk);
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tmpreg |= (SetValue & LPTIM_CCSR_CAP1EDGE_Msk);
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LPTIM->CCSR = tmpreg;
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}
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uint32_t LPTIM_CCSR_CAP1EDGE_Get(void)
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{
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return (LPTIM->CCSR & LPTIM_CCSR_CAP1EDGE_Msk);
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}
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/* ͨµÀ4±È½ÏÊä³ö²¨Ðμ«ÐÔÑ¡Ôñ (Channel 4 compare output Polarity)
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0£ºÕý¼«ÐÔ²¨ÐΣ¬ÆðʼΪµÍ£¬¼ÆÊýÖµ==±È½ÏֵʱÖøߣ¬¼ÆÊýÖµ==ARRʱ»Ö¸´ÎªµÍ
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1£º¸º¼«ÐÔ²¨ÐΣ¬Õý¼«ÐÔ²¨ÐÎÈ¡·´ Ïà¹Øº¯Êý */
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void LPTIM_CCSR_POLAR4_Set(uint32_t SetValue)
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{
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uint32_t tmpreg;
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tmpreg = LPTIM->CCSR;
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tmpreg &= ~(LPTIM_CCSR_POLAR4_Msk);
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tmpreg |= (SetValue & LPTIM_CCSR_POLAR4_Msk);
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LPTIM->CCSR = tmpreg;
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}
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uint32_t LPTIM_CCSR_POLAR4_Get(void)
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{
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return (LPTIM->CCSR & LPTIM_CCSR_POLAR4_Msk);
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}
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void LPTIM_CCSR_POLAR3_Set(uint32_t SetValue)
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{
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uint32_t tmpreg;
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tmpreg = LPTIM->CCSR;
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tmpreg &= ~(LPTIM_CCSR_POLAR3_Msk);
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tmpreg |= (SetValue & LPTIM_CCSR_POLAR3_Msk);
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LPTIM->CCSR = tmpreg;
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}
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uint32_t LPTIM_CCSR_POLAR3_Get(void)
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{
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return (LPTIM->CCSR & LPTIM_CCSR_POLAR3_Msk);
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}
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void LPTIM_CCSR_POLAR2_Set(uint32_t SetValue)
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{
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uint32_t tmpreg;
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tmpreg = LPTIM->CCSR;
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tmpreg &= ~(LPTIM_CCSR_POLAR2_Msk);
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tmpreg |= (SetValue & LPTIM_CCSR_POLAR2_Msk);
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LPTIM->CCSR = tmpreg;
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}
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uint32_t LPTIM_CCSR_POLAR2_Get(void)
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{
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return (LPTIM->CCSR & LPTIM_CCSR_POLAR2_Msk);
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}
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void LPTIM_CCSR_POLAR1_Set(uint32_t SetValue)
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{
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uint32_t tmpreg;
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tmpreg = LPTIM->CCSR;
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tmpreg &= ~(LPTIM_CCSR_POLAR1_Msk);
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tmpreg |= (SetValue & LPTIM_CCSR_POLAR1_Msk);
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LPTIM->CCSR = tmpreg;
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}
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uint32_t LPTIM_CCSR_POLAR1_Get(void)
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{
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return (LPTIM->CCSR & LPTIM_CCSR_POLAR1_Msk);
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}
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/* ͨµÀ4²¶×½±ßÑØÑ¡Ôñ(Channel 4 Capture edge Config)
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00£ºÉÏÉýÑز¶×½
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01£ºÏ½µÑز¶×½
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10£ºÉÏÉýϽµÑز¶×½
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11£ºRFU Ïà¹Øº¯Êý */
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void LPTIM_CCSR_CAPCFG4_Set(uint32_t SetValue)
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{
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uint32_t tmpreg;
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tmpreg = LPTIM->CCSR;
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tmpreg &= ~(LPTIM_CCSR_CAPCFG4_Msk);
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tmpreg |= (SetValue & LPTIM_CCSR_CAPCFG4_Msk);
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LPTIM->CCSR = tmpreg;
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}
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uint32_t LPTIM_CCSR_CAPCFG4_Get(void)
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{
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return (LPTIM->CCSR & LPTIM_CCSR_CAPCFG4_Msk);
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}
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void LPTIM_CCSR_CAPCFG3_Set(uint32_t SetValue)
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{
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uint32_t tmpreg;
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tmpreg = LPTIM->CCSR;
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tmpreg &= ~(LPTIM_CCSR_CAPCFG3_Msk);
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tmpreg |= (SetValue & LPTIM_CCSR_CAPCFG3_Msk);
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LPTIM->CCSR = tmpreg;
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}
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uint32_t LPTIM_CCSR_CAPCFG3_Get(void)
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{
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return (LPTIM->CCSR & LPTIM_CCSR_CAPCFG3_Msk);
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}
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void LPTIM_CCSR_CAPCFG2_Set(uint32_t SetValue)
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{
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uint32_t tmpreg;
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tmpreg = LPTIM->CCSR;
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tmpreg &= ~(LPTIM_CCSR_CAPCFG2_Msk);
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tmpreg |= (SetValue & LPTIM_CCSR_CAPCFG2_Msk);
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LPTIM->CCSR = tmpreg;
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}
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uint32_t LPTIM_CCSR_CAPCFG2_Get(void)
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{
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return (LPTIM->CCSR & LPTIM_CCSR_CAPCFG2_Msk);
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}
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void LPTIM_CCSR_CAPCFG1_Set(uint32_t SetValue)
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{
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uint32_t tmpreg;
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tmpreg = LPTIM->CCSR;
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tmpreg &= ~(LPTIM_CCSR_CAPCFG1_Msk);
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tmpreg |= (SetValue & LPTIM_CCSR_CAPCFG1_Msk);
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LPTIM->CCSR = tmpreg;
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}
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uint32_t LPTIM_CCSR_CAPCFG1_Get(void)
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{
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return (LPTIM->CCSR & LPTIM_CCSR_CAPCFG1_Msk);
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}
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/* ͨµÀ4²¶×½/±È½Ï¹¦ÄÜʹÄÜ(Channel 4 Capture/Compare Select)
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00,11£º½ûֹͨµÀ4²¶×½/±È½Ï¹¦ÄÜ
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01£ºÊ¹ÄÜͨµÀ4²¶×½¹¦ÄÜ£¨LPT_CH4ΪÊäÈ룩
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10£ºÊ¹ÄÜͨµÀ4±È½Ï¹¦ÄÜ£¨LPT_CH4ΪÊä³ö£© Ïà¹Øº¯Êý */
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void LPTIM_CCSR_CC4S_Set(uint32_t SetValue)
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{
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uint32_t tmpreg;
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tmpreg = LPTIM->CCSR;
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tmpreg &= ~(LPTIM_CCSR_CC4S_Msk);
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tmpreg |= (SetValue & LPTIM_CCSR_CC4S_Msk);
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LPTIM->CCSR = tmpreg;
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}
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uint32_t LPTIM_CCSR_CC4S_Get(void)
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{
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return (LPTIM->CCSR & LPTIM_CCSR_CC4S_Msk);
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}
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void LPTIM_CCSR_CC3S_Set(uint32_t SetValue)
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{
|
uint32_t tmpreg;
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tmpreg = LPTIM->CCSR;
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tmpreg &= ~(LPTIM_CCSR_CC3S_Msk);
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tmpreg |= (SetValue & LPTIM_CCSR_CC3S_Msk);
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LPTIM->CCSR = tmpreg;
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}
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uint32_t LPTIM_CCSR_CC3S_Get(void)
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{
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return (LPTIM->CCSR & LPTIM_CCSR_CC3S_Msk);
|
}
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void LPTIM_CCSR_CC2S_Set(uint32_t SetValue)
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{
|
uint32_t tmpreg;
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tmpreg = LPTIM->CCSR;
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tmpreg &= ~(LPTIM_CCSR_CC2S_Msk);
|
tmpreg |= (SetValue & LPTIM_CCSR_CC2S_Msk);
|
LPTIM->CCSR = tmpreg;
|
}
|
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uint32_t LPTIM_CCSR_CC2S_Get(void)
|
{
|
return (LPTIM->CCSR & LPTIM_CCSR_CC2S_Msk);
|
}
|
|
void LPTIM_CCSR_CC1S_Set(uint32_t SetValue)
|
{
|
uint32_t tmpreg;
|
tmpreg = LPTIM->CCSR;
|
tmpreg &= ~(LPTIM_CCSR_CC1S_Msk);
|
tmpreg |= (SetValue & LPTIM_CCSR_CC1S_Msk);
|
LPTIM->CCSR = tmpreg;
|
}
|
|
uint32_t LPTIM_CCSR_CC1S_Get(void)
|
{
|
return (LPTIM->CCSR & LPTIM_CCSR_CC1S_Msk);
|
}
|
|
/* ×Ô¶¯ÖØÔØÄ¿±ê¼Ä´æÆ÷(Auto-Reload Register)
|
µ±¼ÆÊýÆ÷¼ÆÊýÖµµÈÓÚARRʱ£¬¼ÆÊýÆ÷»Øµ½³õÖµÖØпªÊ¼ÏòÉϼÆÊý Ïà¹Øº¯Êý */
|
void LPTIM_ARR_Write(uint32_t SetValue)
|
{
|
LPTIM->ARR = (SetValue);
|
}
|
|
uint32_t LPTIM_ARR_Read(void)
|
{
|
return (LPTIM->ARR);
|
}
|
|
/* ͨµÀ4²¶×½Òç³öÖжÏʹÄÜ(Channel 4 Over-Capture Interrupt Enable)
|
1£ºÔÊÐíÖжÏ
|
0£º½ûÖ¹ÖÐ¶Ï Ïà¹Øº¯Êý */
|
void LPTIM_IER_OVR4IE_Setable(FunState NewState)
|
{
|
if (NewState == ENABLE)
|
{
|
LPTIM->IER |= (LPTIM_IER_OVR4IE_Msk);
|
}
|
else
|
{
|
LPTIM->IER &= ~(LPTIM_IER_OVR4IE_Msk);
|
}
|
}
|
|
FunState LPTIM_IER_OVR4IE_Getable(void)
|
{
|
if (LPTIM->IER & (LPTIM_IER_OVR4IE_Msk))
|
{
|
return ENABLE;
|
}
|
else
|
{
|
return DISABLE;
|
}
|
}
|
|
/* ͨµÀ3²¶×½Òç³öÖжÏʹÄÜ(Channel 3 Over-Capture Interrupt Enable)
|
1£ºÔÊÐíÖжÏ
|
0£º½ûÖ¹ÖÐ¶Ï Ïà¹Øº¯Êý */
|
void LPTIM_IER_OVR3IE_Setable(FunState NewState)
|
{
|
if (NewState == ENABLE)
|
{
|
LPTIM->IER |= (LPTIM_IER_OVR3IE_Msk);
|
}
|
else
|
{
|
LPTIM->IER &= ~(LPTIM_IER_OVR3IE_Msk);
|
}
|
}
|
|
FunState LPTIM_IER_OVR3IE_Getable(void)
|
{
|
if (LPTIM->IER & (LPTIM_IER_OVR3IE_Msk))
|
{
|
return ENABLE;
|
}
|
else
|
{
|
return DISABLE;
|
}
|
}
|
|
/* ͨµÀ2²¶×½Òç³öÖжÏʹÄÜ(Channel 2 Over-Capture Interrupt Enable)
|
1£ºÔÊÐíÖжÏ
|
0£º½ûÖ¹ÖÐ¶Ï Ïà¹Øº¯Êý */
|
void LPTIM_IER_OVR2IE_Setable(FunState NewState)
|
{
|
if (NewState == ENABLE)
|
{
|
LPTIM->IER |= (LPTIM_IER_OVR2IE_Msk);
|
}
|
else
|
{
|
LPTIM->IER &= ~(LPTIM_IER_OVR2IE_Msk);
|
}
|
}
|
|
FunState LPTIM_IER_OVR2IE_Getable(void)
|
{
|
if (LPTIM->IER & (LPTIM_IER_OVR2IE_Msk))
|
{
|
return ENABLE;
|
}
|
else
|
{
|
return DISABLE;
|
}
|
}
|
|
/* ͨµÀ1²¶×½Òç³öÖжÏʹÄÜ(Channel 1 Over-Capture Interrupt Enable)
|
1£ºÔÊÐíÖжÏ
|
0£º½ûÖ¹ÖÐ¶Ï Ïà¹Øº¯Êý */
|
void LPTIM_IER_OVR1IE_Setable(FunState NewState)
|
{
|
if (NewState == ENABLE)
|
{
|
LPTIM->IER |= (LPTIM_IER_OVR1IE_Msk);
|
}
|
else
|
{
|
LPTIM->IER &= ~(LPTIM_IER_OVR1IE_Msk);
|
}
|
}
|
|
FunState LPTIM_IER_OVR1IE_Getable(void)
|
{
|
if (LPTIM->IER & (LPTIM_IER_OVR1IE_Msk))
|
{
|
return ENABLE;
|
}
|
else
|
{
|
return DISABLE;
|
}
|
}
|
|
/* Íⲿ´¥·¢µ½À´ÖжÏʹÄÜλ(External Trigger Interrupt Enable)
|
1£ºÍⲿ´¥·¢µ½À´ÖжÏʹÄÜ
|
0£ºÍⲿ´¥·¢µ½À´ÖжϽûÖ¹ Ïà¹Øº¯Êý */
|
void LPTIM_IER_TRIGIE_Setable(FunState NewState)
|
{
|
if (NewState == ENABLE)
|
{
|
LPTIM->IER |= (LPTIM_IER_TRIGIE_Msk);
|
}
|
else
|
{
|
LPTIM->IER &= ~(LPTIM_IER_TRIGIE_Msk);
|
}
|
}
|
|
FunState LPTIM_IER_TRIGIE_Getable(void)
|
{
|
if (LPTIM->IER & (LPTIM_IER_TRIGIE_Msk))
|
{
|
return ENABLE;
|
}
|
else
|
{
|
return DISABLE;
|
}
|
}
|
|
/* ¼ÆÊýÆ÷Òç³öÖжÏʹÄÜλ(Counter Over-Flow Interrupt Enable)
|
1£º¼ÆÊýÆ÷Òç³öÖжÏʹÄÜ
|
0£º¼ÆÊýÆ÷Òç³öÖжϽûÖ¹ Ïà¹Øº¯Êý */
|
void LPTIM_IER_OVIE_Setable(FunState NewState)
|
{
|
if (NewState == ENABLE)
|
{
|
LPTIM->IER |= (LPTIM_IER_OVIE_Msk);
|
}
|
else
|
{
|
LPTIM->IER &= ~(LPTIM_IER_OVIE_Msk);
|
}
|
}
|
|
FunState LPTIM_IER_OVIE_Getable(void)
|
{
|
if (LPTIM->IER & (LPTIM_IER_OVIE_Msk))
|
{
|
return ENABLE;
|
}
|
else
|
{
|
return DISABLE;
|
}
|
}
|
|
/* ²¶×½/±È½ÏͨµÀ4ÖжÏʹÄÜλ(Capture/Compare channel 4 Interrupt Enable)
|
1£º²¶×½/±È½ÏͨµÀ2ÖжÏʹÄÜ
|
0£º²¶×½/±È½ÏͨµÀ2ÖжϽûÖ¹ Ïà¹Øº¯Êý */
|
void LPTIM_IER_CC4IE_Setable(FunState NewState)
|
{
|
if (NewState == ENABLE)
|
{
|
LPTIM->IER |= (LPTIM_IER_CC4IE_Msk);
|
}
|
else
|
{
|
LPTIM->IER &= ~(LPTIM_IER_CC4IE_Msk);
|
}
|
}
|
|
FunState LPTIM_IER_CC4IE_Getable(void)
|
{
|
if (LPTIM->IER & (LPTIM_IER_CC4IE_Msk))
|
{
|
return ENABLE;
|
}
|
else
|
{
|
return DISABLE;
|
}
|
}
|
|
/* ²¶×½/±È½ÏͨµÀ3ÖжÏʹÄÜλ(Capture/Compare channel 3 Interrupt Enable)
|
1£º²¶×½/±È½ÏͨµÀ1ÖжÏʹÄÜ
|
0£º²¶×½/±È½ÏͨµÀ1ÖжϽûÖ¹ Ïà¹Øº¯Êý */
|
void LPTIM_IER_CC3IE_Setable(FunState NewState)
|
{
|
if (NewState == ENABLE)
|
{
|
LPTIM->IER |= (LPTIM_IER_CC3IE_Msk);
|
}
|
else
|
{
|
LPTIM->IER &= ~(LPTIM_IER_CC3IE_Msk);
|
}
|
}
|
|
FunState LPTIM_IER_CC3IE_Getable(void)
|
{
|
if (LPTIM->IER & (LPTIM_IER_CC3IE_Msk))
|
{
|
return ENABLE;
|
}
|
else
|
{
|
return DISABLE;
|
}
|
}
|
|
/* ²¶×½/±È½ÏͨµÀ2ÖжÏʹÄÜλ(Capture/Compare channel 2 Interrupt Enable)
|
1£º²¶×½/±È½ÏͨµÀ2ÖжÏʹÄÜ
|
0£º²¶×½/±È½ÏͨµÀ2ÖжϽûÖ¹ Ïà¹Øº¯Êý */
|
void LPTIM_IER_CC2IE_Setable(FunState NewState)
|
{
|
if (NewState == ENABLE)
|
{
|
LPTIM->IER |= (LPTIM_IER_CC2IE_Msk);
|
}
|
else
|
{
|
LPTIM->IER &= ~(LPTIM_IER_CC2IE_Msk);
|
}
|
}
|
|
FunState LPTIM_IER_CC2IE_Getable(void)
|
{
|
if (LPTIM->IER & (LPTIM_IER_CC2IE_Msk))
|
{
|
return ENABLE;
|
}
|
else
|
{
|
return DISABLE;
|
}
|
}
|
|
/* ²¶×½/±È½ÏͨµÀ1ÖжÏʹÄÜλ(Capture/Compare channel 1 Interrupt Enable)
|
1£º²¶×½/±È½ÏͨµÀ1ÖжÏʹÄÜ
|
0£º²¶×½/±È½ÏͨµÀ1ÖжϽûÖ¹ Ïà¹Øº¯Êý */
|
void LPTIM_IER_CC1IE_Setable(FunState NewState)
|
{
|
if (NewState == ENABLE)
|
{
|
LPTIM->IER |= (LPTIM_IER_CC1IE_Msk);
|
}
|
else
|
{
|
LPTIM->IER &= ~(LPTIM_IER_CC1IE_Msk);
|
}
|
}
|
|
FunState LPTIM_IER_CC1IE_Getable(void)
|
{
|
if (LPTIM->IER & (LPTIM_IER_CC1IE_Msk))
|
{
|
return ENABLE;
|
}
|
else
|
{
|
return DISABLE;
|
}
|
}
|
|
void LPTIM_ISR_CAP4OVR_Clr(void)
|
{
|
LPTIM->ISR = LPTIM_ISR_CAP4OVR_Msk;
|
}
|
|
FlagStatus LPTIM_ISR_CAP4OVR_Chk(void)
|
{
|
if (LPTIM->ISR & LPTIM_ISR_CAP4OVR_Msk)
|
{
|
return SET;
|
}
|
else
|
{
|
return RESET;
|
}
|
}
|
|
void LPTIM_ISR_CAP3OVR_Clr(void)
|
{
|
LPTIM->ISR = LPTIM_ISR_CAP3OVR_Msk;
|
}
|
|
FlagStatus LPTIM_ISR_CAP3OVR_Chk(void)
|
{
|
if (LPTIM->ISR & LPTIM_ISR_CAP3OVR_Msk)
|
{
|
return SET;
|
}
|
else
|
{
|
return RESET;
|
}
|
}
|
|
void LPTIM_ISR_CAP2OVR_Clr(void)
|
{
|
LPTIM->ISR = LPTIM_ISR_CAP2OVR_Msk;
|
}
|
|
FlagStatus LPTIM_ISR_CAP2OVR_Chk(void)
|
{
|
if (LPTIM->ISR & LPTIM_ISR_CAP2OVR_Msk)
|
{
|
return SET;
|
}
|
else
|
{
|
return RESET;
|
}
|
}
|
|
void LPTIM_ISR_CAP1OVR_Clr(void)
|
{
|
LPTIM->ISR = LPTIM_ISR_CAP1OVR_Msk;
|
}
|
|
FlagStatus LPTIM_ISR_CAP1OVR_Chk(void)
|
{
|
if (LPTIM->ISR & LPTIM_ISR_CAP1OVR_Msk)
|
{
|
return SET;
|
}
|
else
|
{
|
return RESET;
|
}
|
}
|
|
void LPTIM_ISR_TRIGIF_Clr(void)
|
{
|
LPTIM->ISR = LPTIM_ISR_TRIGIF_Msk;
|
}
|
|
FlagStatus LPTIM_ISR_TRIGIF_Chk(void)
|
{
|
if (LPTIM->ISR & LPTIM_ISR_TRIGIF_Msk)
|
{
|
return SET;
|
}
|
else
|
{
|
return RESET;
|
}
|
}
|
|
void LPTIM_ISR_OVIF_Clr(void)
|
{
|
LPTIM->ISR = LPTIM_ISR_OVIF_Msk;
|
}
|
|
FlagStatus LPTIM_ISR_OVIF_Chk(void)
|
{
|
if (LPTIM->ISR & LPTIM_ISR_OVIF_Msk)
|
{
|
return SET;
|
}
|
else
|
{
|
return RESET;
|
}
|
}
|
|
void LPTIM_ISR_CC4IF_Clr(void)
|
{
|
LPTIM->ISR = LPTIM_ISR_CC4IF_Msk;
|
}
|
|
FlagStatus LPTIM_ISR_CC4IF_Chk(void)
|
{
|
if (LPTIM->ISR & LPTIM_ISR_CC4IF_Msk)
|
{
|
return SET;
|
}
|
else
|
{
|
return RESET;
|
}
|
}
|
|
void LPTIM_ISR_CC3IF_Clr(void)
|
{
|
LPTIM->ISR = LPTIM_ISR_CC3IF_Msk;
|
}
|
|
FlagStatus LPTIM_ISR_CC3IF_Chk(void)
|
{
|
if (LPTIM->ISR & LPTIM_ISR_CC3IF_Msk)
|
{
|
return SET;
|
}
|
else
|
{
|
return RESET;
|
}
|
}
|
|
void LPTIM_ISR_CC2IF_Clr(void)
|
{
|
LPTIM->ISR = LPTIM_ISR_CC2IF_Msk;
|
}
|
|
FlagStatus LPTIM_ISR_CC2IF_Chk(void)
|
{
|
if (LPTIM->ISR & LPTIM_ISR_CC2IF_Msk)
|
{
|
return SET;
|
}
|
else
|
{
|
return RESET;
|
}
|
}
|
|
void LPTIM_ISR_CC1IF_Clr(void)
|
{
|
LPTIM->ISR = LPTIM_ISR_CC1IF_Msk;
|
}
|
|
FlagStatus LPTIM_ISR_CC1IF_Chk(void)
|
{
|
if (LPTIM->ISR & LPTIM_ISR_CC1IF_Msk)
|
{
|
return SET;
|
}
|
else
|
{
|
return RESET;
|
}
|
}
|
|
/* LPTIMʹÄÜλ(LPTIM Enable)
|
1£ºÊ¹ÄܼÆÊýÆ÷¼ÆÊý
|
0£º½ûÖ¹¼ÆÊýÆ÷¼ÆÊý Ïà¹Øº¯Êý */
|
void LPTIM_CR_EN_Setable(FunState NewState)
|
{
|
if (NewState == ENABLE)
|
{
|
LPTIM->CR |= (LPTIM_CR_EN_Msk);
|
}
|
else
|
{
|
LPTIM->CR &= ~(LPTIM_CR_EN_Msk);
|
}
|
}
|
|
FunState LPTIM_CR_EN_Getable(void)
|
{
|
if (LPTIM->CR & (LPTIM_CR_EN_Msk))
|
{
|
return ENABLE;
|
}
|
else
|
{
|
return DISABLE;
|
}
|
}
|
|
/* ²¶×½/±È½ÏÖµ¼Ä´æÆ÷1 (Channel1 Capture/Compare Register) Ïà¹Øº¯Êý */
|
void LPTIM_CCR1_Write(uint32_t SetValue)
|
{
|
LPTIM->CCR1 = (SetValue);
|
}
|
|
uint32_t LPTIM_CCR1_Read(void)
|
{
|
return (LPTIM->CCR1);
|
}
|
|
/* ²¶×½/±È½ÏÖµ¼Ä´æÆ÷2 (Channel2 Capture/Compare Register) Ïà¹Øº¯Êý */
|
void LPTIM_CCR2_Write(uint32_t SetValue)
|
{
|
LPTIM->CCR2 = (SetValue);
|
}
|
|
uint32_t LPTIM_CCR2_Read(void)
|
{
|
return (LPTIM->CCR2);
|
}
|
|
/* ²¶×½/±È½ÏÖµ¼Ä´æÆ÷3 (Channel3 Capture/Compare Register) Ïà¹Øº¯Êý */
|
void LPTIM_CCR3_Write(uint32_t SetValue)
|
{
|
LPTIM->CCR3 = (SetValue);
|
}
|
|
uint32_t LPTIM_CCR3_Read(void)
|
{
|
return (LPTIM->CCR3);
|
}
|
|
/* ²¶×½/±È½ÏÖµ¼Ä´æÆ÷4 (Channel4 Capture/Compare Register) Ïà¹Øº¯Êý */
|
void LPTIM_CCR4_Write(uint32_t SetValue)
|
{
|
LPTIM->CCR4 = (SetValue);
|
}
|
|
uint32_t LPTIM_CCR4_Read(void)
|
{
|
return (LPTIM->CCR4);
|
}
|
|
void LPTIM_Deinit(void)
|
{
|
//LPTIM->CFGR = 0x00000000;
|
//LPTIM->CNTR = 0x00000000;
|
//LPTIM->CCSR = ;
|
//LPTIM->ARR = 0x00000000;
|
//LPTIM->IER = 0x00000000;
|
//LPTIM->ISR = ;
|
//LPTIM->CR = 0x00000000;
|
//LPTIM->CCR1 = 0x00000000;
|
}
|
|
/******END OF FILE****/
|
