~wujiazhi/SZV103_FM33A0xxEV_SiZhu.git

ELF(D4(ôñ@ºpGÀºpGðµ°FF 8@(Ñÿ!ÉHÿ÷þÿ"Fÿ÷þÿÿ÷þÿ    à8Fÿ÷þÿ        ÿ÷þÿFF !ÿ÷þÿFF À @!ÉBÑ`@
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 ÿ÷þÿûHxBÑàòç¿÷HAxpx@xÁ²ôHÁpÀx(ÜðþðHAxpÿ!1@ÿ÷þÿ% àëHxëI    \ëHAUèHx@Á²æHph²äHÀx¨BíÜâHÀx@ãI\:ßHÁxàH@\²ÜHÀxÜIÝHÿ÷þÿ¸B}ÑÙHxÚIIzBøÑÖH@x(ôÑÖHÀh BpÑÔHz(mÑÒHÿ!1B{ÑÍHx(wÑËHyÍHqÉHÁxËHApÇHyÉHpÄHAyÆHÁpÂHzÄHpÀHAzÂHAp¾H{ÀHp¼HÁz¾HÁpºH|¼H 0r·HÁ{¹H(0ApµH|·H(0p²HA|´H(0Áp°H}²H 0qHÁ|¯H$0Ap«H}H$0p¨HA}ªH$0Áp¦H~¨Hw¤HÁ}¦H0Ap¡H~£H0pHA~¡H0ÁpHHàóãòáÊàà 0pHÁ~H 0ApHH 0pHAH 0Áp·àHÿ!1BøÑHx8(ôÑHyI 9wHÁxH 8AwHyH 8wHAyH 8ÁwHzI 9v~HÁyH 8Av{Hz}H 8vyHAz{H 8ÁvvH{xH 0rtHÁzvH(0ApqH{sH(0poHA{qH(0ÁplH|nH 0qjHÁ{lH$0ApgH|iH$0peHA|gH$0ÁpbH 0}dHw`H 0Á|aH0Ap]H 0}^H0pZH 0A}[H0ÁpWH 0~XH 0pTH 0Á}UH 0ApQH 0~RH 0pNH 0A~OH 0ÁpF(:xFSxCxCÒxCFÿ÷þÿFIp
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xFSxCxCÒxCFÿ÷þÿ:Iq
JqqÈq5Hÿ!1B7Ð2HIB2Ð0H1IB-Ð-HIB(Ð+H-IB#Ð)JxFSxCxCÒxCF%Hh}"Òÿ÷þÿH!I&HAxÀxÁ²HApAæJxFSxCxCÒxCFHh}"Òÿ÷þÿJxFSxCxCÒxCFHàÿÿ hþJÿ÷þÿýJxFSxCxCÒxCF÷Hh÷Jÿ÷þÿòJxFSxCxCÒxCFìHhíJÿ÷þÿçJ2xFSxCxCÒxCFáHhãJÿ÷þÿÜJxFSxCxCÒxCFÖHhÙJÿ÷þÿÿ÷þÿÿ÷þÿÕHx@ÔIpÎHh@ÌI`FhÐIB
Ó ÈI` ÎIp<!ÌHxÿ÷þÿÃH²7 ÿ÷þÿ&ÈHAxÀxÁ²ÅHAp ÅIp Hp p1ÂHÿ÷þÿ1ÁHÿ÷þÿ!¼HpAp ¾Ip¾Ip¾IqF 0@|@Á²»H 0At!tõã¹Hi B{Ñ·Hz(GÑµHÿ!1BÑ®Hy¡H 8p«HÁxH 8Ap©HyH 8p¦HAyH 8Áp,à£HyI@9v¡HÁxH@8AvHyH@8vHAyH@8ÁvF2xFSxCxCÒxCFÿ÷þÿI 9p
JppÈpHIí9B*Ð~J :xFSxCxCÒxCFxHhtJÿ÷þÿH|IHÀy(ÐH&vHAxÀxÁ²sHApuãøàhJ:xFSxCxCÒxCFbHh}"Òÿ÷þÿ]J :xFSxCxCÒxCFWHhSJÿ÷þÿRJxFSxCxCÒxCFLHhLJÿ÷þÿGJxFSxCxCÒxCFAHhBJÿ÷þÿ<J2xFSxCxCÒxCF6Hh8Jÿ÷þÿ1JxFSxCxCÒxCF+Hh.Jÿ÷þÿÿ÷þÿÿ÷þÿ*Hx@)Ip#Hh@!I`Fh%IB
Ó I` #Ip<!!Hxÿ÷þÿH²7 ÿ÷þÿ&HAxÀxÁ²HAp Ip Hp p1Hÿ÷þÿ1Hÿ÷þÿ!HpAp IpIpIqF 0@|@Á²#àh@èh)è5hBîýHAt!t{âüH@i B%ÑúHÀy(!ÑùJxFSxCxCÒxCFóHhóJÿ÷þÿíHðI&ðHAxÀxÁ²íHApQâçHi BXÑåHz(.ÑãHÿ!1BÑæHyàH 0pãHÁxÝH 0ApáHyÛH 0pÞHAyØH 0ÁpàÛHyÕH 0pÙHÁxÓH 0ApÖHyÐH 0pÔHAyÎH 0ÁpÌJ 2xFSxCxCÒxCFÆHhÊJÿ÷þÿÿ÷þÿ¿HÂI&ÂHAxÀxÁ²¿HApõáåá¸HÀi B_Ñ¶Hz(,Ñ´Hÿ!1BÑ·Hy±HwµHÁx¯H0Ap³HyH0p°HAyªH0ÁpàHy§Hw«HÁx¥H0Ap©Hy£H0p¦HAy H0ÁpJ2xFSxCxCÒxCFHhJÿ÷þÿÿ÷þÿH 0|(ÑHIàHI&HAxÀxÁ²HApáHj B}ÑHz(.ÑHÿ!1BÑHyH 0rHÁx}H(0ApHyzH(0p~HAyxH(0Ápà{HyuH 0rxHÁxrH(0ApvHypH(0psHAymH(0ÁplJ(2xFSxCxCÒxCFfHhkJÿ÷þÿ`H 0À|(Ñ]H`I&`HAxÀxÁ²]HAp1áaHx@_IpVHh@UI`Fh\IB
Ó QI` YIp<!XHxÿ÷þÿLH²7 ÿ÷þÿ&KHà)àAxÀxÁ²HHAp EIp Hp p1KHÿ÷þÿ1BHÿ÷þÿ!?HpAp FIpFIp5I 9q3H@|@Á²1HAt!tãà0H@j B~Ñ.Hz(.Ñ,Hÿ!1BÑ/Hy)H 0q,HÁx&H$0Ap*Hy$H$0p'HAy!H$0Ápà$HyH 0q"HÁxH$0ApHyH$0pHAyH$0ÁpJ$2xFSxCxCÒxCFHhJÿ÷þÿHx@Ip    Hh@I`FhIB0Ó I$à  hèh)è5îhB;à` 0Ip<!.Hxÿ÷þÿ-H²7 ÿ÷þÿ&+HAxÀxÁ²(HAp (Ip Hp p1%Hÿ÷þÿ1$Hÿ÷þÿ!HpAp !Ip!Ip!IqF 0@|@Á²H 0At!t#à&HAxÀxÁ²HAp1Hÿ÷þÿ1Hÿ÷þÿ!HpApà
HAxÀxÁ²HAp%àh²HÀx¨BùÜ0Fþ½øµ'    à9Hx
 ÿ÷þÿ6Hx°BÑàôç¿3HAxpx@xÁ²/HÁpÀx(XÝ-HAxpÿ!1@ÿ÷þÿ$ à(Hx(I    \(HU%Hx@Á²#Hp`²!HÀx BíÜHÀx@I \*HÁxH@\²HÀxIHÿ÷þÿ¨BÑHxIIzBÑH@x( ÑHÿ!1BÑHx4(Ñÿ÷þÿFàHAxÀxÁ²HAp$à`²HÀx BùÜ8Fø½ÿÿðµ°'þHy¨tüHAy¨AtúHy¨tøHÁx¨ÁtöHz¨sôHÁy¨AsòH{¨vðHÁz¨AvîHz¨vìHAz¨ÁvêH{¨uèHA{¨AuæH|æHräHA|äH0ApáH|áH0pßHÁ{ßH0ÁpÜH}ÜHqÚHA}ÚHApØH}ØHpÕHÁ|ÕHÁpÓH~ÓH 8wÐHA~ÐHApÎH~ÎHpËHÁ}ËHÁpÉHÉHpÇHAÇHApÅHÅHpÃHÁ~ÃHÁpÁH 0x¨p¾H 0Ax¨Ap¼H 0x¨p¹HÁ¨Áp·H 0yhFwµH 0ÁxhFAw²H 0z¨r°H 0Áy¨ArH 0y¨r«H 0Ay¨Ár¨H 0z¨q¦H 0Az¨Aq$àb«Ñb+2 KÐ#"ÿ÷þÿd,ñÛhFÿ÷þÿF"Kÿ÷þÿÿ÷þÿÿ÷þÿJ@:0#T
1%«T2%«T3#T4 T
5#T6#T 2ÐuF5!F.x1Cnx61C®x61Cîx61C.y0Cny60C®y60Cíy-(C
FFFÿ÷þÿwI 9q
JqqÈqhFÿ÷þÿF"pKÿ÷þÿÿ÷þÿÿ÷þÿhJ@:(#T
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-#T.#T 2ÐsF5!F.x1Cnx61C®x61Cîx61C.y0Cny60C®y60Cíy-(C
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JppÈpx*F]x-*Cx-*CÛxCFDJh}#ÛÐÿ÷þÿ>K ;x*F]x-*Cx-*CÛxCF9Jh8KÐÿ÷þÿ3Kx*F]x-*Cx-*CÛxCF/Jh/KÐÿ÷þÿ)Kx*F]x-*Cx-*CÛxCF$Jh&KÐÿ÷þÿK3x*F]x-*Cx-*CÛxCFJhKÐÿ÷þÿKx*F]x-*Cx-*CÛxCFJhKÐÿ÷þÿÿ÷þÿÿ÷þÿHx@IpHh@I`FhIBà@Y@hèh)è5hBî
Ó I` Ip<!Hxÿ÷þÿH²7 ÿ÷þÿ'HAxÀxÁ²HAp Ip Hp p9Hÿ÷þÿ9Hÿ÷þÿ! HpAp IpIpIqF 0@|@Á²H 0At!t8F°ð½þµFFF HxAphFp!Ap!pÄp)qEq"iFHÿ÷þÿFhFq9Áq!ÿ÷þÿþ½ÿÿøµ' $ ÅIp$áÿ÷þÿdÃHBÓ$ ÀIpáÀHx(Ñÿ÷þÿ¾H|(Ñ¼H 8ºIà¹H 8·I µIHp¶HAxp ²IpÑà±Hx(úÑ¯Hx(~ÑH@x(IÐ«H@x@©IHp p¨H 8ÿ!1B Ñ¥H 8¢I
F¡J :Pz"ÿ÷þÿ©àH 8ÿ!1B ÑH 8I
FJ :Pz"ÿ÷þÿàH 8ÿ!1BÑJJ :Pz"ÿ÷þÿàJJ :Pz"ÿ÷þÿ{à Ip pÿ!1Hÿ÷þÿÿ!1Hÿ÷þÿ!HpApI    h}"Ò!ÿ÷þÿ}I    h|J!ÿ÷þÿyI    hyJ!ÿ÷þÿuI    hvJàAà!ÿ÷þÿpI    hrJ!ÿ÷þÿlI    hoJ!ÿ÷þÿnHx@lIpeHh@dI`FhiIB
Ó `I` fIp<!eHxÿ÷þÿ[H²7 ÿ÷þÿ!`HAt|@Á²^Ht LIp 5à/Ñ' JIp HpHHx($ÐGH 8ÿ!1BÐCH 8IBÑ?Iÿ÷þÿFà=H 8ÿ!1BÑ9Iÿ÷þÿFà6Iÿ÷þÿF1Hx(ÐÕæ¿(Ñÿ÷þÿ3Hh(*Ñ;IhËh/I    h5JIÉ7J*Fÿ÷þÿ4I iKi(I    h.JIÉ1J*Fÿ÷þÿ-IiËi!I    h'JIÉ+J*Fÿ÷þÿ'àHh(#Ð#IhËhI    hIÉ!J*Fÿ÷þÿI iKiI    hIÉJ*Fÿ÷þÿIiËiI    hIÉJ*Fÿ÷þÿø½p hèh)è5hBî ¨z©øµbHx!@(bÐÿ÷þÿ_Jh_KÑ_Jyÿ÷þÿ[Jh]KÑ[JÐxÿ÷þÿWJhZKÑWJyÿ÷þÿSJhWKÑSJxÿ÷þÿOJhTKÑOJPxÿ÷þÿKJhQKÑKJxÿ÷þÿGI    h}"Ò!ÿ÷þÿBI    hIJ!ÿ÷þÿ>I    hFJ!ÿ÷þÿ:I    hCJ!ÿ÷þÿ6I    h@J!ÿ÷þÿ2I    h=J!ÿ÷þÿ-I#1J{{CFÿ÷þÿF6Hi2FÃi Fÿ÷þÿØ!3Hpà!1Hp/IhËh I    hÉ.J"Fÿ÷þÿ)IiKiI    hÉ)J"Fÿ÷þÿ$IiËiI    hÉ%J"Fÿ÷þÿ#Hx@"IpHh@ I`FhIB
Ó     I` Ip<!Hxÿ÷þÿH²7 ÿ÷þÿø½h[^¨aÈdègkhèh)è5hB@¨z©îQHÿ!1B#Ñ NIr Èq!KH 0tAttÁtuAu 8yFIHrFHÈ`ÀaEHHaCHbHbÈaa bwà<Hÿ!1B#Ñ 9Ir Èq!6H 0tAttÁtuAu 8y1IHr2HÈ`aHabHb-H0Èaa bMà'Hÿ!1B!Ñ $Ir Èq!!H 0tAttÁtuAu 8yIHrÿ ù0È`ÀaÀbHbÈaa b%àÿ 0I r Èq!H 0tAttÁtuAu 8y
IHr
HÈ`Àa    HHaHbHbÈaa bpG »pµJHÿ÷þÿFIJxFSxCxCÒxCF)Fÿ÷þÿÓ?Hÿ÷þÿF>JxFSxCxCÒxCF)Fÿ÷þÿdÒ4H(8xBxCÁ@2ID2Iy!Fÿ÷þÿ0IÈxaÿ÷þÿ-Iy¡ÿ÷þÿ+Ixáÿ÷þÿ(IHx!ÿ÷þÿ&Ixaÿ÷þÿ$I ÿ÷þÿH(8x@I(9pFxBxC@²H(8Ap    
pxBxC}!ÉB Û!H(8App I(9ÈpÈxIÿ÷þÿ
H(8xCxCFHÿ÷þÿ I(9Hqà I(9Hqp½(@dêµ%&ÿ÷þÿÿ÷þÿÿ÷þÿÏHx(Ñ ÍIpÿ÷þÿÌJhÌKÑÌJyÿ÷þÿÈJhÊKÑÈJÐxÿ÷þÿÄJhÇKÑÄJyÿ÷þÿÀJhÄKÑÀJxÿ÷þÿ¼JhÁKÑ¼JPxÿ÷þÿ¸Jh¾KÑ¸Jxÿ÷þÿ¼IJ{{CFÿ÷þÿ¸IiÉiFFÿ÷þÿØ!³Hpà!±Hp!É°Hÿ÷þÿ!¯Hÿ÷þÿFàhÅ²!I©H@0ÿ÷þÿ!É¦H@0ÿ÷þÿ!    £H@0ÿ÷þÿd ÿ÷þÿ! Hÿ÷þÿF-Ýà.ÞÑ¿.}ÑHx(Ð !H@0ÿ÷þÿ(#ÑHyð!@(ÑH@0ÿ÷þÿ!ÉH@0ÿ÷þÿà!    H@0ÿ÷þÿ!ÉH@0ÿ÷þÿ!IH@0ÿ÷þÿHÿ!1B    ÐHIBÐHBÑ}JÑxxÿ÷þÿzIyÿ÷þÿÿ÷þÿ} Àÿ÷þÿÈ ÿ÷þÿÿ÷þÿàrJÑxxÿ÷þÿpIyÿ÷þÿÿ÷þÿ!ÉiH@0ÿ÷þÿ!fH@0ÿ÷þÿ!IcH@0ÿ÷þÿ!    `H@0ÿ÷þÿ!É]H@0ÿ÷þÿàà!ÉYHÿ÷þÿ"à!ÉVH@0ÿ÷þÿ!SH@0ÿ÷þÿ!IPH@0ÿ÷þÿ!    MH@0ÿ÷þÿ!ÉJH@0ÿ÷þÿ!ÉGHÿ÷þÿDH 8|(jÝBH 8|(eÚÿ÷þÿ>H@8xBxCÁ@?ID1Iy!Fÿ÷þÿ/IÈxaÿ÷þÿ,Iy¡ÿ÷þÿ*Ixáÿ÷þÿ'IHx!ÿ÷þÿ%Ixaÿ÷þÿ0I ÿ÷þÿ(H@8x@&I@9pFxBxC@²!H@8Ap    
pxBxC}!ÉB Û!H@8App I@9ÈpÈxIÿ÷þÿH@8xCxCFHÿ÷þÿ I@9q½h[^¨aÈdègk#@@ @dêpµJHÿ÷þÿFIJxFSxCxCÒxCF)Fÿ÷þÿÓ?Hÿ÷þÿF>JxFSxCxCÒxCF)Fÿ÷þÿdÒ4H 8xBxCÁ@2ID2Iy!Fÿ÷þÿ0IÈxaÿ÷þÿ-Iy¡ÿ÷þÿ+Ixáÿ÷þÿ(IHx!ÿ÷þÿ&Ixaÿ÷þÿ$I ÿ÷þÿH 8x@I 9pFxBxC@²H 8Ap    
pxBxC}!ÉB Û!H 8App I 9ÈpÈxIÿ÷þÿ
H 8xCxCFHÿ÷þÿ I 9qà I 9qp½ <dêü..\\Pre_Drivers\\ReadDeviceData.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM__asm___16_ReadDeviceData_c_ef47cb5f____REV16P9 ..\\Core\\Include\\core_cminstr.hü..\\Pre_Drivers\\ReadDeviceData.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM__asm___16_ReadDeviceData_c_ef47cb5f____REVSHP9 ..\\Core\\Include\\core_cminstr.h0ÿÿÿÿarmcc+|     
0ÿÿÿÿarmcc+|     
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..\Pre_Drivers\ReadDeviceData.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM..\Pre_Drivers\ReadDeviceData.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMpLLJ_MsgÒpparmAccess^pModbusDlg.pddr_index_28pLast_Data_DDR8pNOW_Data_DDR8pNumDataStoredfpDataStoredFlag8pBeginflag8T..\Pre_Drivers\ReadDeviceData.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM>?ÓLLJ_sendFrame>islaveAddress^idataAddress@ireadDataNum"XcrcW.ÁYsendFrame6`..\Pre_Drivers\ReadDeviceData.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM,?2Pressure_alarm,ZPressure_addrf!..\Pre_Drivers\ReadDeviceData.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM,?STemperature_alarm,ZTemperature_addrf!Ì..\Pre_Drivers\ReadDeviceData.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMz unsigned charunsigned shortfloatint>Ìv    LLJ_ModbusHandle8z iaddressV^^__result8PøZcrc@ZretflagÅ"XiÖUXtempÅd\Tempè\i32Temperatureñ\i32Pressureñ\i32SC_instantñ\i32WC_instantñ..\Pre_Drivers\ReadDeviceData.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM®intdouble>ÁLLJ_ModbusHandle_SIZHUV2_0®^__resultPª    XretflagWXiÅTòYSC_Accumulation_zshYSC_Accumulation_xsdYWC_Accumulation_zs`YWC_Accumulation_xs\YSC_Accumulation_zs_reverseXYSC_Accumulation_xs_reverseTYWC_Accumulation_zs_reversePYWC_Accumulation_xs_reverseL\WC_Accumulation_reverseÌ\SC_Accumulation_reverseÌüYStatus_wordq@Ô..\Pre_Drivers\ReadDeviceData.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMìunsigned charunsigned shortfloatint>Ó¼    LLJ_ModbusHandle_CRCData8ìiaddressVA^__result8PêZcrc#XretflagÅWXiÖTXtempÅV
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 T h W}N} LVLULT}}__DATE__ "Jun 11 2024"__TIME__ "13:38:23"__STDC__ 1__STDC_VERSION__ 199901L__STDC_HOSTED__ 1__STDC_ISO_10646__ 200607__EDG__ 1__EDG_VERSION__ 407__EDG_SIZE_TYPE__ unsigned int__EDG_PTRDIFF_TYPE__ int__GNUC__ 4__GNUC_STDC_INLINE__ 1__GNUC_MINOR__ 7__GNUC_PATCHLEVEL__ 0__VERSION__ "4.7 (EDG gcc mode)"__CHAR16_TYPE__ unsigned short__CHAR32_TYPE__ unsigned int__USER_LABEL_PREFIX__ __CHAR_UNSIGNED__ 1__WCHAR_UNSIGNED__ 1__SIZE_TYPE__ unsigned int__PTRDIFF_TYPE__ int__WCHAR_TYPE__ unsigned short__WINT_TYPE__ unsigned short__INTMAX_TYPE__ long long__UINTMAX_TYPE__ unsigned long long__sizeof_int 4__sizeof_long 4__sizeof_ptr 4__ARMCC_VERSION 5060750__TARGET_CPU_CORTEX_M0 1__TARGET_FPU_SOFTVFP 1__TARGET_FPU_SOFTVFP 1__MICROLIB 1__UVISION_VERSION 525_RTE_ 1__VTOR_PRESENT 1__CC_ARM 1__arm 1__arm__ 1__TARGET_ARCH_6S_M 1__TARGET_ARCH_ARM 0__TARGET_ARCH_THUMB 3__TARGET_ARCH_A64 0__TARGET_ARCH_AARCH32 1__TARGET_PROFILE_M 1__TARGET_FEATURE_HALFWORD 1__TARGET_FEATURE_THUMB 1__TARGET_FEATURE_DMB 1__TARGET_FEATURE_EXTENSION_REGISTER_COUNT 0__APCS_INTERWORK 1__thumb 1__thumb__ 1__t32__ 1__OPTIMISE_SPACE 1__OPTIMIZE_SIZE__ 1__OPTIMISE_LEVEL 0__SOFTFP__ 1¹LLJ_MsgÎparmAccessæModbusDlgýddr_index_2Last_Data_DDR1NOW_Data_DDRKNumDataStoredfDataStoredFlagBeginflag XÅLLJ_sendFrame!ÅPressure_alarm$ÅTemperature_alarm#ÐøLLJ_ModbusHandle-ÖLLJ_ModbusHandle_SIZHUV2_0+ØøLLJ_ModbusHandle_CRCData!ØAnalysis_Float#ÏAnalysis_Float48'ôÅParameter_assignment $ÅModbus_RS485B",ÅRead485_process"ìÅPULSE_RecordingY%.[\]__stdint_h __ARMCLIB_VERSION 5060037__INT64 __int64__INT64_C_SUFFIX__ ll__PASTE2(x,y) x ## y__PASTE(x,y) __PASTE2(x, y)__INT64_C(x) __ESCAPE__(__PASTE(x, __INT64_C_SUFFIX__))__UINT64_C(x) __ESCAPE__(__PASTE(x ## u, __INT64_C_SUFFIX__))__LONGLONG long long#__STDINT_DECLS %__CLIBNS,__CLIBNS yINT8_MIN -128zINT16_MIN -32768{INT32_MIN (~0x7fffffff)|INT64_MIN __INT64_C(~0x7fffffffffffffff)INT8_MAX 127INT16_MAX 32767INT32_MAX 2147483647INT64_MAX __INT64_C(9223372036854775807)UINT8_MAX 255UINT16_MAX 65535UINT32_MAX 4294967295uUINT64_MAX __UINT64_C(18446744073709551615)INT_LEAST8_MIN -128INT_LEAST16_MIN -32768INT_LEAST32_MIN (~0x7fffffff)INT_LEAST64_MIN __INT64_C(~0x7fffffffffffffff)INT_LEAST8_MAX 127INT_LEAST16_MAX 32767INT_LEAST32_MAX 2147483647INT_LEAST64_MAX __INT64_C(9223372036854775807)UINT_LEAST8_MAX 255UINT_LEAST16_MAX 65535UINT_LEAST32_MAX 4294967295uUINT_LEAST64_MAX __UINT64_C(18446744073709551615)¡INT_FAST8_MIN (~0x7fffffff)¢INT_FAST16_MIN (~0x7fffffff)£INT_FAST32_MIN (~0x7fffffff)¤INT_FAST64_MIN __INT64_C(~0x7fffffffffffffff)§INT_FAST8_MAX 2147483647¨INT_FAST16_MAX 2147483647©INT_FAST32_MAX 2147483647ªINT_FAST64_MAX __INT64_C(9223372036854775807)UINT_FAST8_MAX 4294967295u®UINT_FAST16_MAX 4294967295u¯UINT_FAST32_MAX 4294967295u°UINT_FAST64_MAX __UINT64_C(18446744073709551615)¸INTPTR_MIN INT32_MIN¿INTPTR_MAX INT32_MAXÆUINTPTR_MAX UINT32_MAXÌINTMAX_MIN __ESCAPE__(~0x7fffffffffffffffll)ÏINTMAX_MAX __ESCAPE__(9223372036854775807ll)ÒUINTMAX_MAX __ESCAPE__(18446744073709551615ull)ÛPTRDIFF_MIN INT32_MINÜPTRDIFF_MAX INT32_MAXàSIG_ATOMIC_MIN (~0x7fffffff)áSIG_ATOMIC_MAX 2147483647çSIZE_MAX UINT32_MAXíWCHAR_MINîWCHAR_MAXôWCHAR_MIN 0õWCHAR_MAX 65535ùWINT_MIN (~0x7fffffff)úWINT_MAX 2147483647INT8_C(x) (x)INT16_C(x) (x)INT32_C(x) (x)INT64_C(x) __INT64_C(x)UINT8_C(x) (x ## u)UINT16_C(x) (x ## u)UINT32_C(x) (x ## u)UINT64_C(x) __UINT64_C(x)INTMAX_C(x) __ESCAPE__(x ## ll)UINTMAX_C(x) __ESCAPE__(x ## ull)¸__INT64¹__LONGLONGLB D:\Keil5\ARM\ARMCC\Bin\..\include\stdint.h4D:\Keil5\ARM\ARMCC\Bin\..\include\stdint.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]signed charshortintlong longunsigned charunsigned shortunsigned intunsigned long longPint8_t8 Pint16_t9 Pint32_t : Pint64_t§; Puint8_t´> Puint8_t´> Puint16_tÅ? Puint32_t×@ Puint64_tçA Pu32fCPu16VDPu88EPint_least8_tM Pint_least16_tN Pint_least32_t O Pint_least64_t§P Puint_least8_t´S Puint_least16_tÅT Puint_least32_t×U Puint_least64_tçV Pint_fast8_t [ Pint_fast16_t \ Pint_fast32_t ] Pint_fast64_t§^ Puint_fast8_t×a Puint_fast16_t×b Puint_fast32_t×c Puint_fast64_tçd Pintptr_t k Puintptr_t×l Pintmax_t§p!Puintmax_tçq!_`a'__CORE_CMINSTR_H <__NOP __nopD__WFI __wfiL__WFE __wfeS__SEV __sev\__ISB() do { __schedule_barrier(); __isb(0xF); __schedule_barrier(); } while (0)g__DSB() do { __schedule_barrier(); __dsb(0xF); __schedule_barrier(); } while (0)r__DMB() do { __schedule_barrier(); __dmb(0xF); __schedule_barrier(); } while (0)__REV __rev©__ROR __ror´__BKPT(value) __breakpoint(value)Ú__CLZ __clz@6 ..\Core\Include\core_cminstr.h
..\Core\Include\core_cminstr.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM;Á9__RBITf$fvaluea__resultf\resultf\scde'__CORE_CMFUNC_H @5 ..\Core\Include\core_cmfunc.h
..\Core\Include\core_cmfunc.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM;ÿ@__get_CONTROLfa__resultfY__regControlfP<¸M__set_CONTROL$fcontrolY__regControlfP;òZ__get_IPSRfa__resultfY__regIPSRfP;¬g__get_APSRfa__resultfY__regAPSRfP;æt__get_xPSRfa__resultfY__regXPSRfP;¯__get_PSPfa__resultfY__regProcessStackPointerfP<ø__set_PSP$ftopOfProcStackY__regProcessStackPointerfP;¾__get_MSPfa__resultfY__regMainStackPointerfP<¨__set_MSP$ftopOfMainStackY__regMainStackPointerfP;Åµ__get_PRIMASKfa__resultfY__regPriMaskfP<ÿÂ__set_PRIMASK$fpriMaskY__regPriMaskfPghi __CORE_CM0PLUS_H_GENERIC "@__CM0PLUS_CMSIS_VERSION_MAIN ( 5U)A__CM0PLUS_CMSIS_VERSION_SUB ( 0U)B__CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | __CM0PLUS_CMSIS_VERSION_SUB )E__CORTEX_M (0U)Q__ASM __asmR__INLINE __inlineS__STATIC_INLINE static __inlineT__NO_RETURN __declspec(noreturn)U__USED __attribute__((used))V__WEAK __attribute__((weak))W__UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))__FPU_USED 0UÆÇÒ__CORE_CM0PLUS_H_DEPENDANT ÿ__I volatile const__O volatile__IO volatile__IM volatile const__OM volatile__IOM volatile³APSR_N_Pos 31U´APSR_N_Msk (1UL << APSR_N_Pos)¶APSR_Z_Pos 30U·APSR_Z_Msk (1UL << APSR_Z_Pos)¹APSR_C_Pos 29UºAPSR_C_Msk (1UL << APSR_C_Pos)¼APSR_V_Pos 28U½APSR_V_Msk (1UL << APSR_V_Pos)ÎIPSR_ISR_Pos 0UÏIPSR_ISR_Msk (0x1FFUL )æxPSR_N_Pos 31UçxPSR_N_Msk (1UL << xPSR_N_Pos)éxPSR_Z_Pos 30UêxPSR_Z_Msk (1UL << xPSR_Z_Pos)ìxPSR_C_Pos 29UíxPSR_C_Msk (1UL << xPSR_C_Pos)ïxPSR_V_Pos 28UðxPSR_V_Msk (1UL << xPSR_V_Pos)òxPSR_T_Pos 24UóxPSR_T_Msk (1UL << xPSR_T_Pos)õxPSR_ISR_Pos 0UöxPSR_ISR_Msk (0x1FFUL )CONTROL_SPSEL_Pos 1UCONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)CONTROL_nPRIV_Pos 0UCONTROL_nPRIV_Msk (1UL )ÈSCB_CPUID_IMPLEMENTER_Pos 24UÉSCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)ËSCB_CPUID_VARIANT_Pos 20UÌSCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)ÎSCB_CPUID_ARCHITECTURE_Pos 16UÏSCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)ÑSCB_CPUID_PARTNO_Pos 4UÒSCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)ÔSCB_CPUID_REVISION_Pos 0UÕSCB_CPUID_REVISION_Msk (0xFUL )ØSCB_ICSR_NMIPENDSET_Pos 31UÙSCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)ÛSCB_ICSR_PENDSVSET_Pos 28UÜSCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)ÞSCB_ICSR_PENDSVCLR_Pos 27UßSCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)áSCB_ICSR_PENDSTSET_Pos 26UâSCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)äSCB_ICSR_PENDSTCLR_Pos 25UåSCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)çSCB_ICSR_ISRPREEMPT_Pos 23UèSCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)êSCB_ICSR_ISRPENDING_Pos 22UëSCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)íSCB_ICSR_VECTPENDING_Pos 12UîSCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)ðSCB_ICSR_VECTACTIVE_Pos 0UñSCB_ICSR_VECTACTIVE_Msk (0x1FFUL )õSCB_VTOR_TBLOFF_Pos 8UöSCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)úSCB_AIRCR_VECTKEY_Pos 16UûSCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)ýSCB_AIRCR_VECTKEYSTAT_Pos 16UþSCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)SCB_AIRCR_ENDIANESS_Pos 15USCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)SCB_AIRCR_SYSRESETREQ_Pos 2USCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)SCB_AIRCR_VECTCLRACTIVE_Pos 1USCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)SCB_SCR_SEVONPEND_Pos 4USCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)SCB_SCR_SLEEPDEEP_Pos 2USCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)SCB_SCR_SLEEPONEXIT_Pos 1USCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)SCB_CCR_STKALIGN_Pos 9USCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)SCB_CCR_UNALIGN_TRP_Pos 3USCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)SCB_SHCSR_SVCALLPENDED_Pos 15USCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)´SysTick_CTRL_COUNTFLAG_Pos 16UµSysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)·SysTick_CTRL_CLKSOURCE_Pos 2U¸SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)ºSysTick_CTRL_TICKINT_Pos 1U»SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)½SysTick_CTRL_ENABLE_Pos 0U¾SysTick_CTRL_ENABLE_Msk (1UL )ÁSysTick_LOAD_RELOAD_Pos 0UÂSysTick_LOAD_RELOAD_Msk (0xFFFFFFUL )ÅSysTick_VAL_CURRENT_Pos 0UÆSysTick_VAL_CURRENT_Msk (0xFFFFFFUL )ÉSysTick_CALIB_NOREF_Pos 31UÊSysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)ÌSysTick_CALIB_SKEW_Pos 30UÍSysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)ÏSysTick_CALIB_TENMS_Pos 0UÐSysTick_CALIB_TENMS_Msk (0xFFFFFFUL )éMPU_TYPE_IREGION_Pos 16UêMPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)ìMPU_TYPE_DREGION_Pos 8UíMPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)ïMPU_TYPE_SEPARATE_Pos 0UðMPU_TYPE_SEPARATE_Msk (1UL )óMPU_CTRL_PRIVDEFENA_Pos 2UôMPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)öMPU_CTRL_HFNMIENA_Pos 1U÷MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)ùMPU_CTRL_ENABLE_Pos 0UúMPU_CTRL_ENABLE_Msk (1UL )ýMPU_RNR_REGION_Pos 0UþMPU_RNR_REGION_Msk (0xFFUL )MPU_RBAR_ADDR_Pos 8UMPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)MPU_RBAR_VALID_Pos 4UMPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos)MPU_RBAR_REGION_Pos 0UMPU_RBAR_REGION_Msk (0xFUL )MPU_RASR_ATTRS_Pos 16UMPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos)MPU_RASR_XN_Pos 28UMPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos)MPU_RASR_AP_Pos 24UMPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos)MPU_RASR_TEX_Pos 19UMPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos)MPU_RASR_S_Pos 18UMPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos)MPU_RASR_C_Pos 17UMPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos)MPU_RASR_B_Pos 16UMPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) MPU_RASR_SRD_Pos 8U¡MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos)£MPU_RASR_SIZE_Pos 1U¤MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos)¦MPU_RASR_ENABLE_Pos 0U§MPU_RASR_ENABLE_Msk (1UL )Ä_VAL2FLD(field,value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)Ì_FLD2VAL(field,value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)ÙSCS_BASE (0xE000E000UL)ÚSysTick_BASE (SCS_BASE + 0x0010UL)ÛNVIC_BASE (SCS_BASE + 0x0100UL)ÜSCB_BASE (SCS_BASE + 0x0D00UL)ÞSCB ((SCB_Type *) SCB_BASE )ßSysTick ((SysTick_Type *) SysTick_BASE )àNVIC ((NVIC_Type *) NVIC_BASE )ãMPU_BASE (SCS_BASE + 0x0D90UL)äMPU ((MPU_Type *) MPU_BASE )_BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)_SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )_IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) ..\Core\Include\D:\Keil5\ARM\ARMCC\Bin\..\include\core_cm0plus.hstdint.hcore_cminstr.hcore_cmfunc.h°
..\Core\Include\core_cm0plus.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM*!_reserved0f#!Vf#!Cf#!Zf#!Nf#S§bÀwfPAPSR_Type°*å!ISRf#    !_reserved0f#Søb9wfPIPSR_TypeeË*!ISRf#    !_reserved0f#!Tf#!_reserved1f#!Vf#!Cf#!Zf#!Nf#S¦bwfPxPSR_Typeã*ø!nPRIVf#!SPSELf#!_reserved1f#Sb8wfPCONTROL_Typex*  ® ISER¥#ÅfRESERVED0º#ß ICERÖ#÷fRSERVED1ì# ISPR#©fRESERVED2#Ä ICPR;#ÜfRESERVED3Q#ùf?RESERVED4n# IP#tfPNVIC_Type §*¹(CPUID?#ICSR #VTOR #AIRCR #SCR #CCR #RESERVED1f#  SHP#SHCSR #$ft9PSCB_Type¸Å*    CTRL #LOAD #VAL #CALIB?#PSysTick_TypeT±*Þ    TYPE?#CTRL #RNR #RBAR #RASR #PMPU_Typeæ<
NVIC_EnableIRQ$(IRQn<¶
NVIC_DisableIRQ$(IRQn;ò
NVIC_GetPendingIRQf$(IRQna__resultf<ÀNVIC_SetPendingIRQ$(IRQn<ÂÏNVIC_ClearPendingIRQ$(IRQn<öáNVIC_SetPriority$(IRQn$fpriority;°ùNVIC_GetPriorityf$(IRQna__resultf<ÊNVIC_SystemReset;÷¬SCB_GetFPUTypefa__resultf;° ËSysTick_Configf$fticksa__resultfklmn__stdio_h __ARMCLIB_VERSION 5060037"_ARMABI __declspec(__nothrow)%__STDIO_DECLS '__CLIBNS-__CLIBNS <NULL=NULL 0g_SYS_OPEN 16¥stdin (&__CLIBNS __stdin)§stdout (&__CLIBNS __stdout)©stderr (&__CLIBNS __stderr)¬_IOFBF 0x100_IOLBF 0x200®_IONBF 0x400±BUFSIZ (512)³FOPEN_MAX _SYS_OPEN¹FILENAME_MAX 256¾L_tmpnam FILENAME_MAXÄTMP_MAX 256ÌEOF (-1)ÒSEEK_SET 0ÓSEEK_CUR 1ÔSEEK_END 2Ú_IOBIN 0x04Ü__STDIN_BUFSIZ (64)Ý__STDOUT_BUFSIZ (64)Þ__STDERR_BUFSIZ (16)¿getchar() getc(stdin)àputchar(c) putc(c, stdout)LA D:\Keil5\ARM\ARMCC\Bin\..\include\stdio.h´D:\Keil5\ARM\ARMCC\Bin\..\include\stdio.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]unsigned intunsigned long longPsize_t5P__va_listAF*ó__state1#__state2#)¦__fpos_t_struct__pos#__mbstateÎ#Pfpos_tóa-__FILEPFILE4lq__stdin<q__stdout<q__stderr<"<q__aeabi_stdintq__aeabi_stdouttq__aeabi_stderrtl¸H__stdinV__stdoute__stderrx__aeabi_stdin__aeabi_stdout¡__aeabi_stderrpqr$FM33A0XXEV_H .__RCHF_INITIAL_CLOCK (8000000)/__RCMF_CLOCK (2000000)0__RCLP_CLOCK (32000)1__XTLF_CLOCK (32768)n__CM0_REV 0x0100o__MPU_PRESENT 1p__VTOR_PRESENT 1q__NVIC_PRIO_BITS 2r__Vendor_SysTickConfig 0uv¿FLASH_BASE (( uint32_t)0x00000000)ÀSRAM_BASE (( uint32_t)0x20000000)ÁPERIPH_BASE (( uint32_t)0x40000000)ÊPMU_BASE (PERIPH_BASE +0x00002000)ËDBG_BASE (PERIPH_BASE +0x00000000)ÌFLS_BASE (PERIPH_BASE +0x00001000)ÍRMU_BASE (PERIPH_BASE +0x00002800)ÎIWDT_BASE (PERIPH_BASE +0x00011400)ÏWWDT_BASE (PERIPH_BASE +0x00011800)ÐCMU_BASE (PERIPH_BASE +0x00002400)ÑCDIF_BASE (PERIPH_BASE +0x0001E000)ÒVRTC_BASE (PERIPH_BASE +0x0001F800)ÓSVD_BASE (PERIPH_BASE +0x00012800)ÔAES_BASE (PERIPH_BASE +0x00013800)ÕPAE_BASE (PERIPH_BASE +0x00001400)ÖHASH_BASE (PERIPH_BASE +0x00001800)×RNG_BASE (PERIPH_BASE +0x00013C00)ØCOMP_BASE (PERIPH_BASE +0x00015400)ÙI2C0_BASE (PERIPH_BASE +0x00012400)ÚI2C1_BASE (PERIPH_BASE +0x00015000)ÛUARTIR_BASE (PERIPH_BASE +0x00017C00)ÜUART0_BASE (PERIPH_BASE +0x00012000)ÝUART1_BASE (PERIPH_BASE +0x00016800)ÞUART2_BASE (PERIPH_BASE +0x00016C00)ßUART3_BASE (PERIPH_BASE +0x00017000)àUART4_BASE (PERIPH_BASE +0x00017400)áUART5_BASE (PERIPH_BASE +0x00017800)âLPUART0_BASE (PERIPH_BASE +0x00014000)ãLPUART1_BASE (PERIPH_BASE +0x00014400)äSPI0_BASE (PERIPH_BASE +0x00010400)åSPI1_BASE (PERIPH_BASE +0x00010800)æSPI2_BASE (PERIPH_BASE +0x00014800)çSPI3_BASE (PERIPH_BASE +0x00014C00)èSPI4_BASE (PERIPH_BASE +0x00016400)éU7816_BASE (PERIPH_BASE +0x00011C00)êQSPI_BASE (PERIPH_BASE +0x00000800)ëDMA_BASE (PERIPH_BASE +0x00000400)ìCRC_BASE (PERIPH_BASE +0x00010000)íBT1_BASE (PERIPH_BASE +0x00013000)îBT2_BASE (PERIPH_BASE +0x00013044)ïET1_BASE (PERIPH_BASE +0x00013090)ðET2_BASE (PERIPH_BASE +0x000130B0)ñET3_BASE (PERIPH_BASE +0x000130D0)òET4_BASE (PERIPH_BASE +0x000130F0)óETCNT_BASE (PERIPH_BASE +0x00013110)ôBSTIM_BASE (PERIPH_BASE +0x00016000)õLPTIM_BASE (PERIPH_BASE +0x00013400)öRTC_BASE (PERIPH_BASE +0x00011000)÷LCD_BASE (PERIPH_BASE +0x00010C00)øADC_BASE (PERIPH_BASE +0x0001FA00)ùCIC_BASE (PERIPH_BASE +0x00015C00)úGPIOA_BASE (PERIPH_BASE +0x00000C00)ûGPIOB_BASE (PERIPH_BASE +0x00000C40)üGPIOC_BASE (PERIPH_BASE +0x00000C80)ýGPIOD_BASE (PERIPH_BASE +0x00000CC0)þGPIOE_BASE (PERIPH_BASE +0x00000D00)ÿGPIOF_BASE (PERIPH_BASE +0x00000D40)GPIOG_BASE (PERIPH_BASE +0x00000D80)GPIOH_BASE (PERIPH_BASE +0x0001FC00)GPIO_BASE (PERIPH_BASE +0x00000DC0)PMU ((PMU_Type *) PMU_BASE )DBG ((DBG_Type *) DBG_BASE )FLS ((FLS_Type *) FLS_BASE )RMU ((RMU_Type *) RMU_BASE )IWDT ((IWDT_Type *) IWDT_BASE )WWDT ((WWDT_Type *) WWDT_BASE )CMU ((CMU_Type *) CMU_BASE )CDIF ((CDIF_Type *) CDIF_BASE )VRTC ((VRTC_Type *) VRTC_BASE )SVD ((SVD_Type *) SVD_BASE )AES ((AES_Type *) AES_BASE )PAE ((PAE_Type *) PAE_BASE )HASH ((HASH_Type *) HASH_BASE )RNG ((RNG_Type *) RNG_BASE )COMP ((COMP_Type *) COMP_BASE )I2C0 ((I2C_Type *) I2C0_BASE )I2C1 ((I2C_Type *) I2C1_BASE )UARTIR ((UARTIR_Type *) UARTIR_BASE )UART0 ((UART_Type *) UART0_BASE )UART1 ((UART_Type *) UART1_BASE )UART2 ((UART_Type *) UART2_BASE )UART3 ((UART_Type *) UART3_BASE )UART4 ((UART_Type *) UART4_BASE )UART5 ((UART_Type *) UART5_BASE ) LPUART0 ((LPUART_Type *) LPUART0_BASE )¡LPUART1 ((LPUART_Type *) LPUART1_BASE )¢SPI0 ((SPI_Type *) SPI0_BASE )£SPI1 ((SPI_Type *) SPI1_BASE )¤SPI2 ((SPI_Type *) SPI2_BASE )¥SPI3 ((SPI_Type *) SPI3_BASE )¦SPI4 ((SPI_Type *) SPI4_BASE )§U7816 ((U7816_Type *) U7816_BASE )¨QSPI ((QSPI_Type *) QSPI_BASE )©DMA ((DMA_Type *) DMA_BASE )ªCRC ((CRC_Type *) CRC_BASE )«BT1 ((BT_Type *) BT1_BASE )¬BT2 ((BT_Type *) BT2_BASE )ET1 ((ET_Type *) ET1_BASE )®ET2 ((ET_Type *) ET2_BASE )¯ET3 ((ET_Type *) ET3_BASE )°ET4 ((ET_Type *) ET4_BASE )±ETCNT ((ETCNT_Type *) ETCNT_BASE )²BSTIM ((BSTIM_Type *) BSTIM_BASE )³LPTIM ((LPTIM_Type *) LPTIM_BASE )´RTC ((RTC_Type *) RTC_BASE )µLCD ((LCD_Type *) LCD_BASE )¶ADC ((ADC_Type *) ADC_BASE )·CIC ((CIC_Type *) CIC_BASE )¸GPIOA ((GPIO_Type *) GPIOA_BASE )¹GPIOB ((GPIO_Type *) GPIOB_BASE )ºGPIOC ((GPIO_Type *) GPIOC_BASE )»GPIOD ((GPIO_Type *) GPIOD_BASE )¼GPIOE ((GPIO_Type *) GPIOE_BASE )½GPIOF ((GPIO_Type *) GPIOF_BASE )¾GPIOG ((GPIO_Type *) GPIOG_BASE )¿GPIOH ((GPIOH_Type *) GPIOH_BASE )ÀGPIO ((GPIO_COMMON_Type *) GPIO_BASE )h] ..\Core\Include\FM33A0XXEV.hcore_cm0plus.hsystem_FM33A0XXEV.h¬
..\Core\Include\FM33A0XXEV.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMÓRESETSETPFlagStatus¾*(PITStatus¾*4DISABLEENABLEPFunStateõ+/´FAILPASSPErrorStatus,'¨Reset_IRQnqNMI_IRQnrHardFault_IRQnsSVC_IRQn{PendSV_IRQn~SysTick_IRQnWWDT_IRQnSVD_IRQnRTC_IRQnFLASH_IRQnCMU_IRQnADC_IRQnSPI0_IRQnSPI1_IRQnSPI2_IRQnUART0_IRQn    UART1_IRQn
UART2_IRQnUART3_IRQnUART4_IRQn UART5_IRQnU7816_IRQnLPUART0_IRQnI2Cx_IRQnRSV_IRQnCRYPTO_IRQnLPTIM_IRQnDMA_IRQnWKUPx_IRQnCOMP_IRQnBTx_IRQnQSPI_IRQnETx_IRQnBSTIM_IRQnSPI3_IRQnSPI4_IRQnGPIO_IRQnLPUART1_IRQnPIRQn_TypeGb*öCRv#WKTRv#WKFRv#IERv#ISRv#tfPPMU_Type9*´RSV1v#CRv#HDFRv#PDBG_Type¨*    XRDCRv#PFCRv#OPTBR#÷vRSV1î#EPCRv#KEYv#IERv#ISRv# ¹vRSV20#$ACLOCK1v#HACLOCK2v#LACLOCK3v#PACLOCK4v#TftPFLS_TypeÅ¾*
$PDRCRv#BORCRv#RSTCFGRv#SOFTRSTv#RSRv#PRSTENv#AHBRSTv#APBRST1v#APBRST2v# PRMU_TypeÐ*Ù
SERVv#CFGRv#CNTR#PIWDT_Type0Ü*´CRv#CFGRv#CNTR#IERv#ISRv#PSCR#PWWDT_Typekë* 8SYSCLKCRv#RCHFCRv#RCHFTRv#PLLLCRv#PLLHCRv#XTHFCRv#IERv#ISRv#PCLKCR1v# PCLKCR2v#$PCLKCR3v#(PCLKCR4v#,OPCCR1v#0OPCCR2v#4PCMU_TypeÆ*» CRv#PSCRv#PCDIF_Type *Õ0PDRCRv#ç vRSV1Þ#RCMFCRv#RCLPCRv#RCLPTRv#XTLFCRv# ADCCRv#$LFDIERv#(LFDISRv#,PVRTC_TypeÍ*£CFGRv#CRv#IERv#ISRv#VSRv#PSVD_Typeg¬*§TCRv#IERv#ISRv#DIRv#DOR#KEY0v#KEY1v#KEY2v#KEY3v# KEY4v#$KEY5v#(KEY6v#,KEY7v#0IVR0v#4IVR1v#8IVR2v#<IVR3v#@H0v#DH1v#HH2v#LH3v#PPAES_Type´Ê* CSRv#MLRv#MPRv#M0CFGv#M1CFGv#M2CFGv#M3CFGv#WORDv#PPAE_Type¸Û*ÊCSRv#DTRv#PHASH_Type/    æ*À CRv#DOR#þvRSV1u    #SRv#CRC_CRv#CRC_DIRv#CRC_SRv#PRNG_Type\    ö*CR1v#CR2v#ICRv#ISRv#PCRv#PCOMP_TypeÑ    *$CFGRv#CRv#IERv#ISRv#SRv#BRGv#BUFv#TIMINGv#TOv# PI2C_Type
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 *CSRv#IERv#ISRv#TODRv#RXBUF#TXBUFv#BGRv#PUART_Type¼
°*ûCSRv#IERv#ISRv#BMRv#RXBUFv#TXBUFv#DMRv#PLPUART_Type%À*åCR1v#CR2v#CR3v#IERv#ISRv#TXBUFv#RXBUF#PSPI_TypeÐ*â$CRv#FFRv#EGTRv#PSCv#BGRv#RXBUF#TXBUFv#IERv#ISRv# PU7816_Typeöâ*0CRv#CFGv#SRv#DATALENv#CCRv#ADDRv#ABRv#DRv#SMSKv# SMATv#$PITVv#(TOv#,PQSPI_Typeu÷*õ¸GCRv#CH0CRv#CH0MARv#CH1CRv#CH1MARv#CH2CRv#CH2MARv#CH3CRv#CH3MARv# CH4CRv#$CH4MARv#(CH5CRv#,CH5MARv#0CH6CRv#4CH6MARv#8CH7CRv#<CH7MARv#@CH8CRv#DCH8MARv#HCH9CRv#LCH9MARv#PCH10CRv#TCH10MARv#XCH11CRv#\CH11FARv#`CH11RARv#dISRv#hv$RSV1#lCH0CSRv#CH0MASRv#CH1CSRv#CH1MASRv#CH2CSRv#CH2MASRv#CH3CSRv#CH3MASRv#CH4CSRv# CH4MASRv#¤CH5CSRv#¨CH5MASRv#¬CH6CSRv#°CH6MASRv#´PDMA_Type ª*× DRv#CRv#LFSRv#XORv#¾vRSV1µ#POLYv#PCRC_Type¹*¾!DCR1v#CR2v#CFGR1v#CFGR2v#PRESv#LOADCRv#CNTL#CNTH#PRESETv# LOADLv#$LOADHv#(CMPLv#,CMPHv#0OUTCNTv#4OCRv#8IERv#<ISRv#@PBT_TypeèÓ*°" CRv#INSRv#PSCR1v#PSCR2v#IVRv#CMPRv#IERv#ISRv#PET_TypeÎä*õ"CNT1v#CNT2v#CNT3v#CNT4v#PETCNT_Type@ï*$0CR1v#CR2v#RSV1v#IERv#ISRv#EGRv#Ø#vRSV2Ï#CNTRv#$PSCRv#(ARRv#,PBSTIM_Type*«%0CFGRv#CNTR#CCSRv#ARRv#IERv#ISRv#CRv#RSV1v#CCR1v# CCR2v#$CCR3v#(CCR4v#,PLPTIM_Type*ø'WERv#IERv#ISRv#BCDSECv#BCDMINv#BCDHOURv#BCDDATEv#BCDWEEKv#BCDMONTHv# BCDYEARv#$ALARMv#(TMSELv#,ADJUSTv#0ADSIGNv#4VCALv#8MSCNTv#<CALSTEPv#@ADCNT#DSSR#HSSAv#LDTRv#Pá'v    RSV1Ø#TCRv#|PRTC_Type¾¶*¿*`CRv#TESTv#FCRv#FLKTv#RSV1v#IERv#ISRv#å(vRSV2\#DATA0v#$DATA1v#(DATA2v#,DATA3v#0DATA4v#4DATA5v#8DATA6v#<DATA7v#@DATA8v#DDATA9v#Hü)vRSV3ó#LCOMENv#PSEGEN0v#TSEGEN1v#XBSTCRv#\PLCD_Type    Õ*+CRv#TRIMv#DR#ISRv#CFGRv#PADC_TypePã*×+DR#OSv#USDR#CRv#ISRv#PCIC_Typeñ*ë,,INENv#PUENv#ODENv#FCRv#DOv#DSETv#DRSTv#DIN#DFSv# RSVv#$ANENv#(PGPIO_Typeè*º-INENv#PUENv#FCRv#DOv#DINv#PGPIOH_Type}*/ÄEXTISEL0v#EXTISEL1v#EXTIEDS0v#EXTIEDS1v#EXTIDFv#EXTIISRv#EXTIDI#Æ.vRSV1=#FOUTSELv#@IOMCRv#D÷.v=RSV2n#HPINWKENv#ÀPGPIO_COMMON_TypeÍ¦tuvw(SYSTEM_FM33A0XXEV_H 234O__SYSTEM_CLOCK (8000000)PDELAY_US (__SYSTEM_CLOCK/1000000)QDELAY_MS (__SYSTEM_CLOCK/1000)TDo_DelayStart() { uint32_t LastTick = SysTick->VAL; do {WWhile_DelayMsEnd(Count) }while(((LastTick - SysTick->VAL)&0xFFFFFF)<DELAY_MS*Count); }ZWhile_DelayUsEnd(Count) }while(((LastTick - SysTick->VAL)&0xFFFFFF)<DELAY_US*Count); } ..\Core\Include\D:\Keil5\ARM\ARMCC\Bin\..\include\system_FM33A0XXEV.hstdint.hstdio.hFM33A0XXEV.hÜ
..\Core\Include\system_FM33A0XXEV.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMqSystemCoreClockf"àÅSystemCoreClockyz{__FM33A0XXEV_AES_H )AES_CR_KEYLEN_Pos 13/AES_CR_KEYLEN_Msk (0x3U << AES_CR_KEYLEN_Pos)0AES_CR_KEYLEN_128BIT (0x0U << AES_CR_KEYLEN_Pos)1AES_CR_KEYLEN_192BIT (0x1U << AES_CR_KEYLEN_Pos)2AES_CR_KEYLEN_256BIT (0x2U << AES_CR_KEYLEN_Pos)3AES_CR_KEYLEN_ (0x3U << AES_CR_KEYLEN_Pos)5AES_CR_DMAOEN_Pos 12:AES_CR_DMAOEN_Msk (0x1U << AES_CR_DMAOEN_Pos)=AES_CR_DMAIEN_Pos 11BAES_CR_DMAIEN_Msk (0x1U << AES_CR_DMAIEN_Pos)EAES_CR_CHMOD_Pos 5KAES_CR_CHMOD_Msk (0x3U << AES_CR_CHMOD_Pos)LAES_CR_CHMOD_ECB (0x0U << AES_CR_CHMOD_Pos)MAES_CR_CHMOD_CBC (0x1U << AES_CR_CHMOD_Pos)NAES_CR_CHMOD_CTR (0x2U << AES_CR_CHMOD_Pos)OAES_CR_CHMOD_MULTH (0x3U << AES_CR_CHMOD_Pos)QAES_CR_MODE_Pos 3XAES_CR_MODE_Msk (0x3U << AES_CR_MODE_Pos)YAES_CR_MODE_ENCRYPT (0x0U << AES_CR_MODE_Pos)ZAES_CR_MODE_KEYEXP (0x1U << AES_CR_MODE_Pos)[AES_CR_MODE_DECRYPT (0x2U << AES_CR_MODE_Pos)\AES_CR_MODE_KEYEXPDECRYPT (0x3U << AES_CR_MODE_Pos)^AES_CR_DATATYP_Pos 1dAES_CR_DATATYP_Msk (0x3U << AES_CR_DATATYP_Pos)eAES_CR_DATATYP_32BITNOEX (0x0U << AES_CR_DATATYP_Pos)fAES_CR_DATATYP_16BITEX (0x1U << AES_CR_DATATYP_Pos)gAES_CR_DATATYP_8BITEX (0x2U << AES_CR_DATATYP_Pos)hAES_CR_DATATYP_1BITEX (0x3U << AES_CR_DATATYP_Pos)jAES_CR_EN_Pos 0oAES_CR_EN_Msk (0x1U << AES_CR_EN_Pos)sAES_IER_WRERR_IE_Pos 2tAES_IER_WRERR_IE_Msk (0x1U << AES_IER_WRERR_IE_Pos)vAES_IER_RDERR_IE_Pos 1wAES_IER_RDERR_IE_Msk (0x1U << AES_IER_RDERR_IE_Pos)yAES_IER_CCF_IE_Pos 0zAES_IER_CCF_IE_Msk (0x1U << AES_IER_CCF_IE_Pos)|AES_DIR_DIN_Pos 0AES_DIR_DIN_Msk (0xffffffffU << AES_DIR_DIN_Pos)AES_DOR_DOUT_Pos 0AES_DOR_DOUT_Msk (0xffffffffU << AES_DOR_DOUT_Pos)AES_KEY0_KEYx_Pos 0AES_KEY0_KEYx_Msk (0xffffffffU << AES_KEY0_KEYx_Pos)AES_KEY1_KEYx_Pos 0AES_KEY1_KEYx_Msk (0xffffffffU << AES_KEY1_KEYx_Pos)AES_KEY2_KEYx_Pos 0AES_KEY2_KEYx_Msk (0xffffffffU << AES_KEY2_KEYx_Pos)AES_KEY3_KEYx_Pos 0AES_KEY3_KEYx_Msk (0xffffffffU << AES_KEY3_KEYx_Pos)AES_KEY4_KEYx_Pos 0AES_KEY4_KEYx_Msk (0xffffffffU << AES_KEY4_KEYx_Pos)AES_KEY5_KEYx_Pos 0 AES_KEY5_KEYx_Msk (0xffffffffU << AES_KEY5_KEYx_Pos)¢AES_KEY6_KEYx_Pos 0¤AES_KEY6_KEYx_Msk (0xffffffffU << AES_KEY6_KEYx_Pos)¦AES_KEY7_KEYx_Pos 0¨AES_KEY7_KEYx_Msk (0xffffffffU << AES_KEY7_KEYx_Pos)ªAES_IVR0_IVRx_Pos 0¬AES_IVR0_IVRx_Msk (0xffffffffU << AES_IVR0_IVRx_Pos)®AES_IVR1_IVRx_Pos 0°AES_IVR1_IVRx_Msk (0xffffffffU << AES_IVR1_IVRx_Pos)²AES_IVR2_IVRx_Pos 0´AES_IVR2_IVRx_Msk (0xffffffffU << AES_IVR2_IVRx_Pos)¶AES_IVR3_IVRx_Pos 0¸AES_IVR3_IVRx_Msk (0xffffffffU << AES_IVR3_IVRx_Pos)ºAES_H0_Hx_Pos 0¼AES_H0_Hx_Msk (0xffffffffU << AES_H0_Hx_Pos)¾AES_H1_Hx_Pos 0ÀAES_H1_Hx_Msk (0xffffffffU << AES_H1_Hx_Pos)ÂAES_H2_Hx_Pos 0ÄAES_H2_Hx_Msk (0xffffffffU << AES_H2_Hx_Pos)ÆAES_H3_Hx_Pos 0ÈAES_H3_Hx_Msk (0xffffffffU << AES_H3_Hx_Pos)ÊAES_ISR_WRERR_Pos 2ËAES_ISR_WRERR_Msk (0x1U << AES_ISR_WRERR_Pos)ÍAES_ISR_RDERR_Pos 1ÎAES_ISR_RDERR_Msk (0x1U << AES_ISR_RDERR_Pos)ÐAES_ISR_CCF_Pos 0ÓAES_ISR_CCF_Msk (0x1U << AES_ISR_CCF_Pos)`T ..\Drivers\..\Core\Include\fm33a0xxev_aes.hFM33A0XXEV.ht
..\Drivers\fm33a0xxev_aes.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM*ÞKEYLENf#CHMODf#MODEf#DATATYPf#DMAOEN#DMAIEN#WERRIE#RERRIE#CCFIE#AESEN#PAES_InitTypeDef½'}~__FM33A0XXEV_ADC_H ADC_CR_ADC_IE_Pos 7ADC_CR_ADC_IE_Msk (0x1U << ADC_CR_ADC_IE_Pos)ADC_CR_ACC_IE_Pos 6ADC_CR_ACC_IE_Msk (0x1U << ADC_CR_ACC_IE_Pos)ADC_CR_HPEN_Pos 3"ADC_CR_HPEN_Msk (0x1U << ADC_CR_HPEN_Pos)#ADC_CR_HPEN_1MHZ (0x0U << ADC_CR_HPEN_Pos)$ADC_CR_HPEN_2MHZ (0x1U << ADC_CR_HPEN_Pos)&ADC_CR_MODE_Pos 2)ADC_CR_MODE_Msk (0x1U << ADC_CR_MODE_Pos)*ADC_CR_MODE_INNER (0x0U << ADC_CR_MODE_Pos)+ADC_CR_MODE_EXTERNAL (0x1U << ADC_CR_MODE_Pos)-ADC_CR_RSTCTRL_EN_Pos 10ADC_CR_RSTCTRL_EN_Msk (0x1U << ADC_CR_RSTCTRL_EN_Pos)4ADC_CR_EN_Pos 09ADC_CR_EN_Msk (0x1U << ADC_CR_EN_Pos)>ADC_TRIM_ADC_TRIM_Pos 0AADC_TRIM_ADC_TRIM_Msk (0x7ffU << ADC_TRIM_ADC_TRIM_Pos)CADC_DR_ADC_DATA_Pos 0FADC_DR_ADC_DATA_Msk (0xffffU << ADC_DR_ADC_DATA_Pos)HADC_ISR_INIT_RDY_Pos 9MADC_ISR_INIT_RDY_Msk (0x1U << ADC_ISR_INIT_RDY_Pos)OADC_ISR_ACC_IF_Pos 8PADC_ISR_ACC_IF_Msk (0x1U << ADC_ISR_ACC_IF_Pos)RADC_ISR_ADC_DONE_Pos 1TADC_ISR_ADC_DONE_Msk (0x1U << ADC_ISR_ADC_DONE_Pos)VADC_ISR_ADC_IF_Pos 0WADC_ISR_ADC_IF_Msk (0x1U << ADC_ISR_ADC_IF_Pos)YADC_CFGR_ACC_PERIOD_Pos 16`ADC_CFGR_ACC_PERIOD_Msk (0x7U << ADC_CFGR_ACC_PERIOD_Pos)aADC_CFGR_ACC_PERIOD_10BITS (0x0U << ADC_CFGR_ACC_PERIOD_Pos)bADC_CFGR_ACC_PERIOD_11BITS (0x1U << ADC_CFGR_ACC_PERIOD_Pos)cADC_CFGR_ACC_PERIOD_12BITS (0x2U << ADC_CFGR_ACC_PERIOD_Pos)dADC_CFGR_ACC_PERIOD_13BITS (0x3U << ADC_CFGR_ACC_PERIOD_Pos)eADC_CFGR_ACC_PERIOD_14BITS (0x4U << ADC_CFGR_ACC_PERIOD_Pos)gADC_CFGR_RST_CTRL_DELAY_Pos 8lADC_CFGR_RST_CTRL_DELAY_Msk (0xffU << ADC_CFGR_RST_CTRL_DELAY_Pos)nADC_CFGR_BUFEN_Pos 5oADC_CFGR_BUFEN_Msk (0x1U << ADC_CFGR_BUFEN_Pos)qADC_CFGR_BUFSEL_Pos 0ADC_CFGR_BUFSEL_Msk (0xfU << ADC_CFGR_BUFSEL_Pos)ADC_CFGR_BUFSEL_ADC_IN1 (0x1U << ADC_CFGR_BUFSEL_Pos)ADC_CFGR_BUFSEL_ADC_IN2 (0x2U << ADC_CFGR_BUFSEL_Pos)ADC_CFGR_BUFSEL_ADC_IN3 (0x3U << ADC_CFGR_BUFSEL_Pos)ADC_CFGR_BUFSEL_ADC_IN4 (0x4U << ADC_CFGR_BUFSEL_Pos)ADC_CFGR_BUFSEL_ADC_IN5 (0x5U << ADC_CFGR_BUFSEL_Pos)ADC_CFGR_BUFSEL_ADC_IN6 (0x6U << ADC_CFGR_BUFSEL_Pos)ADC_CFGR_BUFSEL_ADC_IN7 (0x7U << ADC_CFGR_BUFSEL_Pos)ADC_CFGR_BUFSEL_ADC_IN8 (0x8U << ADC_CFGR_BUFSEL_Pos)ADC_CFGR_BUFSEL_ADC_IN9 (0x9U << ADC_CFGR_BUFSEL_Pos)ADC_CFGR_BUFSEL_ADC_IN10 (0xaU << ADC_CFGR_BUFSEL_Pos)ADC_CFGR_BUFSEL_ADC_IN11 (0xbU << ADC_CFGR_BUFSEL_Pos)ADC_CFGR_BUFSEL_ADC_IN12 (0xcU << ADC_CFGR_BUFSEL_Pos)ADC_CFGR_BUFSEL_VBAT (0xeU << ADC_CFGR_BUFSEL_Pos)ADC_CFGR_BUFSEL_TS (0xfU << ADC_CFGR_BUFSEL_Pos)CIC_DR_ADC_CIC_DATA_Pos 0CIC_DR_ADC_CIC_DATA_Msk (0xffffffU << CIC_DR_ADC_CIC_DATA_Pos)CIC_OS_ADC_CIC_OS_Pos 0CIC_OS_ADC_CIC_OS_Msk (0xffffffU << CIC_OS_ADC_CIC_OS_Pos)CIC_USDR_ADC_CIC_USDR_Pos 0CIC_USDR_ADC_CIC_USDR_Msk (0xffffffU << CIC_USDR_ADC_CIC_USDR_Pos)CIC_CR_CIC_EN_Pos 31CIC_CR_CIC_EN_Msk (0x1U << CIC_CR_CIC_EN_Pos)¢CIC_CR_NS_DISC_Pos 8¥CIC_CR_NS_DISC_Msk (0xffU << CIC_CR_NS_DISC_Pos)§CIC_CR_OVR_IE_Pos 7ªCIC_CR_OVR_IE_Msk (0x1U << CIC_CR_OVR_IE_Pos)®CIC_CR_CIC_IE_Pos 6±CIC_CR_CIC_IE_Msk (0x1U << CIC_CR_CIC_IE_Pos)µCIC_CR_TRUNC_Pos 3·CIC_CR_TRUNC_Msk (0x7U << CIC_CR_TRUNC_Pos)¹CIC_CR_OSR_Pos 0ÂCIC_CR_OSR_Msk (0x7U << CIC_CR_OSR_Pos)ÃCIC_CR_OSR_X8 (0x0U << CIC_CR_OSR_Pos)ÄCIC_CR_OSR_X16 (0x1U << CIC_CR_OSR_Pos)ÅCIC_CR_OSR_X32 (0x2U << CIC_CR_OSR_Pos)ÆCIC_CR_OSR_X64 (0x3U << CIC_CR_OSR_Pos)ÇCIC_CR_OSR_X128 (0x4U << CIC_CR_OSR_Pos)ÈCIC_CR_OSR_X256 (0x5U << CIC_CR_OSR_Pos)ÉCIC_CR_OSR_X512 (0x6U << CIC_CR_OSR_Pos)ÊCIC_CR_OSR_X1024 (0x7U << CIC_CR_OSR_Pos)ÌCIC_ISR_CIC_OVR_Pos 1ÍCIC_ISR_CIC_OVR_Msk (0x1U << CIC_ISR_CIC_OVR_Pos)ÏCIC_ISR_CIC_IF_Pos 0ÐCIC_ISR_CIC_IF_Msk (0x1U << CIC_ISR_CIC_IF_Pos)`T ..\Drivers\..\Core\Include\fm33a0xxev_adc.hFM33A0XXEV.h¼
..\Drivers\fm33a0xxev_adc.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM__FM33A0XXEV_BSTIM_H BSTIM_CR1_ARPE_Pos 7BSTIM_CR1_ARPE_Msk (0x1U << BSTIM_CR1_ARPE_Pos) BSTIM_CR1_OPM_Pos 3#BSTIM_CR1_OPM_Msk (0x1U << BSTIM_CR1_OPM_Pos)$BSTIM_CR1_OPM_CONTINUE (0x0U << BSTIM_CR1_OPM_Pos)%BSTIM_CR1_OPM_STOP (0x1U << BSTIM_CR1_OPM_Pos)'BSTIM_CR1_URS_Pos 2-BSTIM_CR1_URS_Msk (0x1U << BSTIM_CR1_URS_Pos).BSTIM_CR1_URS_ALL (0x0U << BSTIM_CR1_URS_Pos)/BSTIM_CR1_URS_COUNT (0x1U << BSTIM_CR1_URS_Pos)1BSTIM_CR1_UDIS_Pos 17BSTIM_CR1_UDIS_Msk (0x1U << BSTIM_CR1_UDIS_Pos);BSTIM_CR1_CEN_Pos 0?BSTIM_CR1_CEN_Msk (0x1U << BSTIM_CR1_CEN_Pos)DBSTIM_CR2_MMS_Pos 4KBSTIM_CR2_MMS_Msk (0x7U << BSTIM_CR2_MMS_Pos)MBSTIM_IER_UIE_Pos 0PBSTIM_IER_UIE_Msk (0x1U << BSTIM_IER_UIE_Pos)TBSTIM_ISR_UIF_Pos 0YBSTIM_ISR_UIF_Msk (0x1U << BSTIM_ISR_UIF_Pos)[BSTIM_EGR_UG_Pos 0]BSTIM_EGR_UG_Msk (0x1U << BSTIM_EGR_UG_Pos)_BSTIM_CNTR_CNT_Pos 0`BSTIM_CNTR_CNT_Msk (0xffffffffU << BSTIM_CNTR_CNT_Pos)bBSTIM_PSCR_PSC_Pos 0eBSTIM_PSCR_PSC_Msk (0xffffffffU << BSTIM_PSCR_PSC_Pos)gBSTIM_ARR_ARR_Pos 0iBSTIM_ARR_ARR_Msk (0xffffffffU << BSTIM_ARR_ARR_Pos)`V ..\Drivers\..\Core\Include\fm33a0xxev_bstim.hFM33A0XXEV.hÀ
..\Drivers\fm33a0xxev_bstim.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM__FM33A0XXEV_COMP_H COMP_CR1_DFLEN_Pos 19COMP_CR1_DFLEN_Msk (0x1fU << COMP_CR1_DFLEN_Pos)COMP_CR1_DFLEN_X3 (0x2U << COMP_CR1_DFLEN_Pos)COMP_CR1_DFLEN_X32 (0x1fU << COMP_CR1_DFLEN_Pos)!COMP_CR1_WINMODE_Pos 18$COMP_CR1_WINMODE_Msk (0x1U << COMP_CR1_WINMODE_Pos)(COMP_CR1_POLAR_Pos 17+COMP_CR1_POLAR_Msk (0x1U << COMP_CR1_POLAR_Pos),COMP_CR1_POLAR_POS (0x0U << COMP_CR1_POLAR_Pos)-COMP_CR1_POLAR_NEG (0x1U << COMP_CR1_POLAR_Pos)/COMP_CR1_DFEN_Pos 162COMP_CR1_DFEN_Msk (0x1U << COMP_CR1_DFEN_Pos)6COMP_CR1_CMP1OR_Pos 97COMP_CR1_CMP1OR_Msk (0x1U << COMP_CR1_CMP1OR_Pos)9COMP_CR1_CMP1OF_Pos 8:COMP_CR1_CMP1OF_Msk (0x1U << COMP_CR1_CMP1OF_Pos)<COMP_CR1_V1NSEL_Pos 4ECOMP_CR1_V1NSEL_Msk (0x7U << COMP_CR1_V1NSEL_Pos)FCOMP_CR1_V1NSEL_COMP1_INN1 (0x0U << COMP_CR1_V1NSEL_Pos)GCOMP_CR1_V1NSEL_COMP1_INN2 (0x1U << COMP_CR1_V1NSEL_Pos)HCOMP_CR1_V1NSEL_VREF (0x2U << COMP_CR1_V1NSEL_Pos)ICOMP_CR1_V1NSEL_3_4_VREF (0x3U << COMP_CR1_V1NSEL_Pos)JCOMP_CR1_V1NSEL_1_2_VREF (0x4U << COMP_CR1_V1NSEL_Pos)KCOMP_CR1_V1NSEL_1_4_VREF (0x5U << COMP_CR1_V1NSEL_Pos)LCOMP_CR1_V1NSEL_1_8_VREF (0x6U << COMP_CR1_V1NSEL_Pos)NCOMP_CR1_V1PSEL_Pos 1SCOMP_CR1_V1PSEL_Msk (0x3U << COMP_CR1_V1PSEL_Pos)TCOMP_CR1_V1PSEL_COMP1_INP1 (0x0U << COMP_CR1_V1PSEL_Pos)UCOMP_CR1_V1PSEL_COMP1_INP2 (0x1U << COMP_CR1_V1PSEL_Pos)VCOMP_CR1_V1PSEL_COMP1_INP3 (0x2U << COMP_CR1_V1PSEL_Pos)WCOMP_CR1_V1PSEL_COMP1_INP4 (0x3U << COMP_CR1_V1PSEL_Pos)YCOMP_CR1_CMP1EN_Pos 0\COMP_CR1_CMP1EN_Msk (0x1U << COMP_CR1_CMP1EN_Pos)`COMP_CR2_DFLEN_Pos 19dCOMP_CR2_DFLEN_Msk (0x1fU << COMP_CR2_DFLEN_Pos)eCOMP_CR2_DFLEN_X3 (0x2U << COMP_CR2_DFLEN_Pos)fCOMP_CR2_DFLEN_X32 (0x1fU << COMP_CR2_DFLEN_Pos)hCOMP_CR2_WINMODE_Pos 18kCOMP_CR2_WINMODE_Msk (0x1U << COMP_CR2_WINMODE_Pos)oCOMP_CR2_POLAR_Pos 17rCOMP_CR2_POLAR_Msk (0x1U << COMP_CR2_POLAR_Pos)sCOMP_CR2_POLAR_POS (0x0U << COMP_CR2_POLAR_Pos)tCOMP_CR2_POLAR_NEG (0x1U << COMP_CR2_POLAR_Pos)vCOMP_CR2_DFEN_Pos 16yCOMP_CR2_DFEN_Msk (0x1U << COMP_CR2_DFEN_Pos)}COMP_CR2_CMP2OR_Pos 9~COMP_CR2_CMP2OR_Msk (0x1U << COMP_CR2_CMP2OR_Pos)COMP_CR2_CMP2OF_Pos 8COMP_CR2_CMP2OF_Msk (0x1U << COMP_CR2_CMP2OF_Pos)COMP_CR2_V2NSEL_Pos 4COMP_CR2_V2NSEL_Msk (0x7U << COMP_CR2_V2NSEL_Pos)COMP_CR2_V2NSEL_COMP2_INN1 (0x0U << COMP_CR2_V2NSEL_Pos)COMP_CR2_V2NSEL_COMP2_INN2 (0x1U << COMP_CR2_V2NSEL_Pos)COMP_CR2_V2NSEL_VREF (0x2U << COMP_CR2_V2NSEL_Pos)COMP_CR2_V2NSEL_3_4_VREF (0x3U << COMP_CR2_V2NSEL_Pos)COMP_CR2_V2NSEL_1_2_VREF (0x4U << COMP_CR2_V2NSEL_Pos)COMP_CR2_V2NSEL_1_4_VREF (0x5U << COMP_CR2_V2NSEL_Pos)COMP_CR2_V2NSEL_1_8_VREF (0x6U << COMP_CR2_V2NSEL_Pos)COMP_CR2_V2NSEL_REFIN (0x7U << COMP_CR2_V2NSEL_Pos)COMP_CR2_V2PSEL_Pos 1COMP_CR2_V2PSEL_Msk (0x7U << COMP_CR2_V2PSEL_Pos)COMP_CR2_V2PSEL_COMP2_INP1 (0x0U << COMP_CR2_V2PSEL_Pos) COMP_CR2_V2PSEL_COMP2_INP2 (0x1U << COMP_CR2_V2PSEL_Pos)¡COMP_CR2_V2PSEL_COMP1_INP1 (0x2U << COMP_CR2_V2PSEL_Pos)¢COMP_CR2_V2PSEL_COMP1_INP2 (0x3U << COMP_CR2_V2PSEL_Pos)£COMP_CR2_V2PSEL_AVREF (0x4U << COMP_CR2_V2PSEL_Pos)¤COMP_CR2_V2PSEL_VDD15 (0x5U << COMP_CR2_V2PSEL_Pos)¦COMP_CR2_CMP2EN_Pos 0©COMP_CR2_CMP2EN_Msk (0x1U << COMP_CR2_CMP2EN_Pos)COMP_ICR_OOW_IE_Pos 9®COMP_ICR_OOW_IE_Msk (0x1U << COMP_ICR_OOW_IE_Pos)°COMP_ICR_WIN_IE_Pos 8±COMP_ICR_WIN_IE_Msk (0x1U << COMP_ICR_WIN_IE_Pos)³COMP_ICR_BUFBYP_Pos 7¶COMP_ICR_BUFBYP_Msk (0x1U << COMP_ICR_BUFBYP_Pos)¸COMP_ICR_BUF_OFF_Pos 6»COMP_ICR_BUF_OFF_Msk (0x1U << COMP_ICR_BUF_OFF_Pos)½COMP_ICR_CMP2SEL_Pos 4ÁCOMP_ICR_CMP2SEL_Msk (0x3U << COMP_ICR_CMP2SEL_Pos)ÂCOMP_ICR_CMP2SEL_BOTH (0x0U << COMP_ICR_CMP2SEL_Pos)ÃCOMP_ICR_CMP2SEL_RISING (0x1U << COMP_ICR_CMP2SEL_Pos)ÄCOMP_ICR_CMP2SEL_FALLING (0x2U << COMP_ICR_CMP2SEL_Pos)ÆCOMP_ICR_CMP1SEL_Pos 2ÊCOMP_ICR_CMP1SEL_Msk (0x3U << COMP_ICR_CMP1SEL_Pos)ËCOMP_ICR_CMP1SEL_BOTH (0x0U << COMP_ICR_CMP1SEL_Pos)ÌCOMP_ICR_CMP1SEL_RISING (0x1U << COMP_ICR_CMP1SEL_Pos)ÍCOMP_ICR_CMP1SEL_FALLING (0x2U << COMP_ICR_CMP1SEL_Pos)ÏCOMP_ICR_CMP2IE_Pos 1ÐCOMP_ICR_CMP2IE_Msk (0x1U << COMP_ICR_CMP2IE_Pos)ÒCOMP_ICR_CMP1IE_Pos 0ÓCOMP_ICR_CMP1IE_Msk (0x1U << COMP_ICR_CMP1IE_Pos)ÕCOMP_ISR_OOW_IF_Pos 3ÖCOMP_ISR_OOW_IF_Msk (0x1U << COMP_ISR_OOW_IF_Pos)ØCOMP_ISR_WIN_IF_Pos 2ÙCOMP_ISR_WIN_IF_Msk (0x1U << COMP_ISR_WIN_IF_Pos)ÛCOMP_ISR_CMP2IF_Pos 1ÜCOMP_ISR_CMP2IF_Msk (0x1U << COMP_ISR_CMP2IF_Pos)ÞCOMP_ISR_CMP1IF_Pos 0ßCOMP_ISR_CMP1IF_Msk (0x1U << COMP_ISR_CMP1IF_Pos)áCOMP_PCR_HSCMPBUF_EN_Pos 2äCOMP_PCR_HSCMPBUF_EN_Msk (0x1U << COMP_PCR_HSCMPBUF_EN_Pos)åCOMP_PCR_HSCMPBUF_EN_SLOW (0x0U << COMP_PCR_HSCMPBUF_EN_Pos)æCOMP_PCR_HSCMPBUF_EN_FAST (0x1U << COMP_PCR_HSCMPBUF_EN_Pos)èCOMP_PCR_HSCMP2_EN_Pos 1ëCOMP_PCR_HSCMP2_EN_Msk (0x1U << COMP_PCR_HSCMP2_EN_Pos)ìCOMP_PCR_HSCMP2_EN_SLOW (0x0U << COMP_PCR_HSCMP2_EN_Pos)íCOMP_PCR_HSCMP2_EN_FAST (0x1U << COMP_PCR_HSCMP2_EN_Pos)ïCOMP_PCR_HSCMP1_EN_Pos 0òCOMP_PCR_HSCMP1_EN_Msk (0x1U << COMP_PCR_HSCMP1_EN_Pos)óCOMP_PCR_HSCMP1_EN_SLOW (0x0U << COMP_PCR_HSCMP1_EN_Pos)ôCOMP_PCR_HSCMP1_EN_FAST (0x1U << COMP_PCR_HSCMP1_EN_Pos)`U ..\Drivers\..\Core\Include\fm33a0xxev_comp.hFM33A0XXEV.h¼
..\Drivers\fm33a0xxev_comp.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM__FM33A0XXEV_RMU_H RMU_PDRCR_PDRCFG_Pos 1RMU_PDRCR_PDRCFG_Msk (0x3U << RMU_PDRCR_PDRCFG_Pos)RMU_PDRCR_PDRCFG_1P5V (0x0U << RMU_PDRCR_PDRCFG_Pos)RMU_PDRCR_PDRCFG_1P25V (0x1U << RMU_PDRCR_PDRCFG_Pos)RMU_PDRCR_PDRCFG_1P35V (0x2U << RMU_PDRCR_PDRCFG_Pos)RMU_PDRCR_PDRCFG_1P4V (0x3U << RMU_PDRCR_PDRCFG_Pos) RMU_PDRCR_PDREN_Pos 0!RMU_PDRCR_PDREN_Msk (0x1U << RMU_PDRCR_PDREN_Pos)%RMU_BORCR_BOR_PDRCFG_Pos 1&RMU_BORCR_BOR_PDRCFG_Msk (0x3U << RMU_BORCR_BOR_PDRCFG_Pos)'RMU_BORCR_BOR_PDRCFG_1P7V (0x0U << RMU_BORCR_BOR_PDRCFG_Pos)(RMU_BORCR_BOR_PDRCFG_1P6V (0x1U << RMU_BORCR_BOR_PDRCFG_Pos))RMU_BORCR_BOR_PDRCFG_1P65V (0x2U << RMU_BORCR_BOR_PDRCFG_Pos)*RMU_BORCR_BOR_PDRCFG_1P75V (0x3U << RMU_BORCR_BOR_PDRCFG_Pos),RMU_BORCR_OFF_BOR_Pos 0-RMU_BORCR_OFF_BOR_Msk (0x1U << RMU_BORCR_OFF_BOR_Pos)1RMU_RSTCFGR_LKUPRST_EN_Pos 12RMU_RSTCFGR_LKUPRST_EN_Msk (0x1U << RMU_RSTCFGR_LKUPRST_EN_Pos)6RMU_SOFTRST_SOFTRST_Pos 07RMU_SOFTRST_SOFTRST_Msk (0xffffffffU << RMU_SOFTRST_SOFTRST_Pos)9RMU_RSR_NRSTN_FLAG_Pos 11:RMU_RSR_NRSTN_FLAG_Msk (0x1U << RMU_RSR_NRSTN_FLAG_Pos)<RMU_RSR_TESTN_FLAG_Pos 10=RMU_RSR_TESTN_FLAG_Msk (0x1U << RMU_RSR_TESTN_FLAG_Pos)?RMU_RSR_PORN_FLAG_Pos 9@RMU_RSR_PORN_FLAG_Msk (0x1U << RMU_RSR_PORN_FLAG_Pos)BRMU_RSR_PDRN_FLAG_Pos 8CRMU_RSR_PDRN_FLAG_Msk (0x1U << RMU_RSR_PDRN_FLAG_Pos)ERMU_RSR_SOFTN_FLAG_Pos 5FRMU_RSR_SOFTN_FLAG_Msk (0x1U << RMU_RSR_SOFTN_FLAG_Pos)HRMU_RSR_IWDTN_FLAG_Pos 4IRMU_RSR_IWDTN_FLAG_Msk (0x1U << RMU_RSR_IWDTN_FLAG_Pos)KRMU_RSR_WWDTN_FLAG_Pos 2LRMU_RSR_WWDTN_FLAG_Msk (0x1U << RMU_RSR_WWDTN_FLAG_Pos)NRMU_RSR_LKUPN_FLAG_Pos 1ORMU_RSR_LKUPN_FLAG_Msk (0x1U << RMU_RSR_LKUPN_FLAG_Pos)QRMU_RSR_NVICN_FLAG_Pos 0RRMU_RSR_NVICN_FLAG_Msk (0x1U << RMU_RSR_NVICN_FLAG_Pos)TRMU_PRSTEN_PERHRSTEN_Pos 0URMU_PRSTEN_PERHRSTEN_Msk (0xffffffffU << RMU_PRSTEN_PERHRSTEN_Pos)WRMU_AHBRST_HASHRST_Pos 2XRMU_AHBRST_HASHRST_Msk (0x1U << RMU_AHBRST_HASHRST_Pos)\RMU_AHBRST_PAERST_Pos 1]RMU_AHBRST_PAERST_Msk (0x1U << RMU_AHBRST_PAERST_Pos)aRMU_AHBRST_DMARST_Pos 0bRMU_AHBRST_DMARST_Msk (0x1U << RMU_AHBRST_DMARST_Pos)fRMU_APBRST1_UART5RST_Pos 31gRMU_APBRST1_UART5RST_Msk (0x1U << RMU_APBRST1_UART5RST_Pos)kRMU_APBRST1_UART4RST_Pos 30lRMU_APBRST1_UART4RST_Msk (0x1U << RMU_APBRST1_UART4RST_Pos)pRMU_APBRST1_UART3RST_Pos 29qRMU_APBRST1_UART3RST_Msk (0x1U << RMU_APBRST1_UART3RST_Pos)uRMU_APBRST1_UART2RST_Pos 28vRMU_APBRST1_UART2RST_Msk (0x1U << RMU_APBRST1_UART2RST_Pos)zRMU_APBRST1_TIMARST_Pos 23{RMU_APBRST1_TIMARST_Msk (0x1U << RMU_APBRST1_TIMARST_Pos)RMU_APBRST1_LCDRST_Pos 16RMU_APBRST1_LCDRST_Msk (0x1U << RMU_APBRST1_LCDRST_Pos)RMU_APBRST1_U7816RST_Pos 14RMU_APBRST1_U7816RST_Msk (0x1U << RMU_APBRST1_U7816RST_Pos)RMU_APBRST1_SPI4RST_Pos 12RMU_APBRST1_SPI4RST_Msk (0x1U << RMU_APBRST1_SPI4RST_Pos)RMU_APBRST1_SPI3RST_Pos 11RMU_APBRST1_SPI3RST_Msk (0x1U << RMU_APBRST1_SPI3RST_Pos)RMU_APBRST1_SPI2RST_Pos 10RMU_APBRST1_SPI2RST_Msk (0x1U << RMU_APBRST1_SPI2RST_Pos)RMU_APBRST1_LPUART0RST_Pos 6RMU_APBRST1_LPUART0RST_Msk (0x1U << RMU_APBRST1_LPUART0RST_Pos)RMU_APBRST1_I2C1RST_Pos 3RMU_APBRST1_I2C1RST_Msk (0x1U << RMU_APBRST1_I2C1RST_Pos)¢RMU_APBRST1_LPTRST_Pos 0£RMU_APBRST1_LPTRST_Msk (0x1U << RMU_APBRST1_LPTRST_Pos)§RMU_APBRST2_UART1RST_Pos 31¨RMU_APBRST2_UART1RST_Msk (0x1U << RMU_APBRST2_UART1RST_Pos)¬RMU_APBRST2_UART0RST_Pos 30RMU_APBRST2_UART0RST_Msk (0x1U << RMU_APBRST2_UART0RST_Pos)±RMU_APBRST2_UARTIRRST_Pos 29²RMU_APBRST2_UARTIRRST_Msk (0x1U << RMU_APBRST2_UARTIRRST_Pos)¶RMU_APBRST2_BSTRST_Pos 28·RMU_APBRST2_BSTRST_Msk (0x1U << RMU_APBRST2_BSTRST_Pos)»RMU_APBRST2_CICRST_Pos 24¼RMU_APBRST2_CICRST_Msk (0x1U << RMU_APBRST2_CICRST_Pos)ÀRMU_APBRST2_ADCRST_Pos 23ÁRMU_APBRST2_ADCRST_Msk (0x1U << RMU_APBRST2_ADCRST_Pos)ÅRMU_APBRST2_AESRST_Pos 18ÆRMU_APBRST2_AESRST_Msk (0x1U << RMU_APBRST2_AESRST_Pos)ÊRMU_APBRST2_CRCRST_Pos 17ËRMU_APBRST2_CRCRST_Msk (0x1U << RMU_APBRST2_CRCRST_Pos)ÏRMU_APBRST2_RNGRST_Pos 16ÐRMU_APBRST2_RNGRST_Msk (0x1U << RMU_APBRST2_RNGRST_Pos)ÔRMU_APBRST2_SPI1RST_Pos 9ÕRMU_APBRST2_SPI1RST_Msk (0x1U << RMU_APBRST2_SPI1RST_Pos)ÙRMU_APBRST2_SPI0RST_Pos 8ÚRMU_APBRST2_SPI0RST_Msk (0x1U << RMU_APBRST2_SPI0RST_Pos)ÞRMU_APBRST2_LPUART1RST_Pos 7ßRMU_APBRST2_LPUART1RST_Msk (0x1U << RMU_APBRST2_LPUART1RST_Pos)ãRMU_APBRST2_I2C0RST_Pos 4äRMU_APBRST2_I2C0RST_Msk (0x1U << RMU_APBRST2_I2C0RST_Pos)èRMU_APBRST2_SVDRST_Pos 1éRMU_APBRST2_SVDRST_Msk (0x1U << RMU_APBRST2_SVDRST_Pos)íRMU_APBRST2_COMPRST_Pos 0îRMU_APBRST2_COMPRST_Msk (0x1U << RMU_APBRST2_COMPRST_Pos)`T ..\Drivers\..\Core\Include\fm33a0xxev_rmu.hFM33A0XXEV.h¼
..\Drivers\fm33a0xxev_rmu.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM__FM33A0XXEV_CRC_H &CRC_DR_DR_Pos 0)CRC_DR_DR_Msk (0xffffffffU << CRC_DR_DR_Pos)+CRC_CR_OPWD_Pos 9.CRC_CR_OPWD_Msk (0x1U << CRC_CR_OPWD_Pos)/CRC_CR_OPWD_BYTE (0x0U << CRC_CR_OPWD_Pos)0CRC_CR_OPWD_WORD (0x1U << CRC_CR_OPWD_Pos)2CRC_CR_PARA_Pos 85CRC_CR_PARA_Msk (0x1U << CRC_CR_PARA_Pos)6CRC_CR_PARA_SERIAL (0x0U << CRC_CR_PARA_Pos)7CRC_CR_PARA_PARALLEL (0x1U << CRC_CR_PARA_Pos)9CRC_CR_RFLTIN_Pos 6ACRC_CR_RFLTIN_Msk (0x3U << CRC_CR_RFLTIN_Pos)BCRC_CR_RFLTIN_NONE (0x0U << CRC_CR_RFLTIN_Pos)CCRC_CR_RFLTIN_BYTE (0x1U << CRC_CR_RFLTIN_Pos)DCRC_CR_RFLTIN_HALFWORD (0x2U << CRC_CR_RFLTIN_Pos)ECRC_CR_RFLTIN_WORD (0x3U << CRC_CR_RFLTIN_Pos)GCRC_CR_RFLTO_Pos 5LCRC_CR_RFLTO_Msk (0x1U << CRC_CR_RFLTO_Pos)MCRC_CR_RFLTO_NON (0x0U << CRC_CR_RFLTO_Pos)NCRC_CR_RFLTO_BYTE (0x1U << CRC_CR_RFLTO_Pos)PCRC_CR_RES_Pos 4SCRC_CR_RES_Msk (0x1U << CRC_CR_RES_Pos)UCRC_CR_BUSY_Pos 3XCRC_CR_BUSY_Msk (0x1U << CRC_CR_BUSY_Pos)ZCRC_CR_XOR_Pos 2]CRC_CR_XOR_Msk (0x1U << CRC_CR_XOR_Pos)aCRC_CR_SEL_Pos 0fCRC_CR_SEL_Msk (0x3U << CRC_CR_SEL_Pos)gCRC_CR_SEL_CRC32 (0x0U << CRC_CR_SEL_Pos)hCRC_CR_SEL_CRC16 (0x1U << CRC_CR_SEL_Pos)iCRC_CR_SEL_CRC8 (0x2U << CRC_CR_SEL_Pos)jCRC_CR_SEL_CRC7 (0x3U << CRC_CR_SEL_Pos)lCRC_LFSR_LFSR_Pos 0nCRC_LFSR_LFSR_Msk (0xffffffffU << CRC_LFSR_LFSR_Pos)pCRC_XOR_XOR_Pos 0rCRC_XOR_XOR_Msk (0xffffffffU << CRC_XOR_XOR_Pos)tCRC_POLY_POLY_Pos 0uCRC_POLY_POLY_Msk (0xffffffffU << CRC_POLY_POLY_Pos)`T ..\Drivers\..\Core\Include\fm33a0xxev_crc.hFM33A0XXEV.h`
..\Drivers\fm33a0xxev_crc.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM*Ê$CRCSELf#OPWDf#PARAf#RFLTINf#RFLTOf#XOR#CRC_XORf#CRCPOLYf#LFSRf# PCRC_InitTypeDef½$__FM33A0XXEV_LCD_H LCD_CR_SCSEL_Pos 20"LCD_CR_SCSEL_Msk (0x7U << LCD_CR_SCSEL_Pos)#LCD_CR_SCSEL_LSCLK_COM (0x0U << LCD_CR_SCSEL_Pos)$LCD_CR_SCSEL_LSCLK_8 (0x1U << LCD_CR_SCSEL_Pos)%LCD_CR_SCSEL_LSCLK_16 (0x2U << LCD_CR_SCSEL_Pos)&LCD_CR_SCSEL_LSCLK_32 (0x3U << LCD_CR_SCSEL_Pos)'LCD_CR_SCSEL_LSCLK_64 (0x4U << LCD_CR_SCSEL_Pos)(LCD_CR_SCSEL_LSCLK_128 (0x5U << LCD_CR_SCSEL_Pos))LCD_CR_SCSEL_LSCLK_256 (0x6U << LCD_CR_SCSEL_Pos)*LCD_CR_SCSEL_LSCLK_512 (0x7U << LCD_CR_SCSEL_Pos),LCD_CR_SC_CTRL_Pos 181LCD_CR_SC_CTRL_Msk (0x3U << LCD_CR_SC_CTRL_Pos)2LCD_CR_SC_CTRL_S0 (0x0U << LCD_CR_SC_CTRL_Pos)3LCD_CR_SC_CTRL_S1 (0x1U << LCD_CR_SC_CTRL_Pos)4LCD_CR_SC_CTRL_S2 (0x2U << LCD_CR_SC_CTRL_Pos)5LCD_CR_SC_CTRL_S3 (0x3U << LCD_CR_SC_CTRL_Pos)8LCD_CR_IC_CTRL_Pos 16=LCD_CR_IC_CTRL_Msk (0x3U << LCD_CR_IC_CTRL_Pos)>LCD_CR_IC_CTRL_L3 (0x0U << LCD_CR_IC_CTRL_Pos)?LCD_CR_IC_CTRL_L2 (0x1U << LCD_CR_IC_CTRL_Pos)@LCD_CR_IC_CTRL_L1 (0x2U << LCD_CR_IC_CTRL_Pos)ALCD_CR_IC_CTRL_L0 (0x3U << LCD_CR_IC_CTRL_Pos)CLCD_CR_ENMODE_Pos 15FLCD_CR_ENMODE_Msk (0x1U << LCD_CR_ENMODE_Pos)GLCD_CR_ENMODE_EXTERNALCAP (0x0U << LCD_CR_ENMODE_Pos)HLCD_CR_ENMODE_INNERRESISTER (0x1U << LCD_CR_ENMODE_Pos)JLCD_CR_FLICK_Pos 14MLCD_CR_FLICK_Msk (0x1U << LCD_CR_FLICK_Pos)QLCD_CR_BIAS_Pos 8RLCD_CR_BIAS_Msk (0xfU << LCD_CR_BIAS_Pos)TLCD_CR_BIASMD_Pos 5WLCD_CR_BIASMD_Msk (0x1U << LCD_CR_BIASMD_Pos)XLCD_CR_BIASMD_3BIAS (0x1U << LCD_CR_BIASMD_Pos)YLCD_CR_BIASMD_4BIAS (0x0U << LCD_CR_BIASMD_Pos)[LCD_CR_ANTIPOLAR_Pos 4^LCD_CR_ANTIPOLAR_Msk (0x1U << LCD_CR_ANTIPOLAR_Pos)_LCD_CR_ANTIPOLAR_GND (0x1U << LCD_CR_ANTIPOLAR_Pos)`LCD_CR_ANTIPOLAR_FLOAT (0x0U << LCD_CR_ANTIPOLAR_Pos)bLCD_CR_WFT_Pos 3eLCD_CR_WFT_Msk (0x1U << LCD_CR_WFT_Pos)fLCD_CR_WFT_BTYPE (0x1U << LCD_CR_WFT_Pos)gLCD_CR_WFT_ATYPE (0x0U << LCD_CR_WFT_Pos)iLCD_CR_LMUX_Pos 1mLCD_CR_LMUX_Msk (0x3U << LCD_CR_LMUX_Pos)nLCD_CR_LMUX_4COM (0x0U << LCD_CR_LMUX_Pos)oLCD_CR_LMUX_6COM (0x1U << LCD_CR_LMUX_Pos)pLCD_CR_LMUX_8COM (0x2U << LCD_CR_LMUX_Pos)sLCD_CR_EN_Pos 0vLCD_CR_EN_Msk (0x1U << LCD_CR_EN_Pos)zLCD_TEST_LCCTRL_Pos 7|LCD_TEST_LCCTRL_Msk (0x1U << LCD_TEST_LCCTRL_Pos)}LCD_TEST_LCCTRL_LOW (0x0U << LCD_TEST_LCCTRL_Pos)~LCD_TEST_LCCTRL_HIGH (0x1U << LCD_TEST_LCCTRL_Pos)LCD_TEST_TESTEN_Pos 0LCD_TEST_TESTEN_Msk (0x1U << LCD_TEST_TESTEN_Pos)LCD_FCR_DF_Pos 0LCD_FCR_DF_Msk (0xffU << LCD_FCR_DF_Pos)LCD_FLKT_TOFF_Pos 8LCD_FLKT_TOFF_Msk (0xffU << LCD_FLKT_TOFF_Pos)LCD_FLKT_TON_Pos 0LCD_FLKT_TON_Msk (0xffU << LCD_FLKT_TON_Pos)LCD_IER_DONIE_Pos 1LCD_IER_DONIE_Msk (0x1U << LCD_IER_DONIE_Pos)LCD_IER_DOFFIE_Pos 0LCD_IER_DOFFIE_Msk (0x1U << LCD_IER_DOFFIE_Pos) LCD_ISR_DONIF_Pos 1¢LCD_ISR_DONIF_Msk (0x1U << LCD_ISR_DONIF_Pos)¤LCD_ISR_DOFFIF_Pos 0¦LCD_ISR_DOFFIF_Msk (0x1U << LCD_ISR_DOFFIF_Pos)¨LCD_BSTCR_OSC_CFG_Pos 12©LCD_BSTCR_OSC_CFG_Msk (0xfU << LCD_BSTCR_OSC_CFG_Pos)«LCD_BSTCR_BUF_OFF_Pos 9¬LCD_BSTCR_BUF_OFF_Msk (0x1U << LCD_BSTCR_BUF_OFF_Pos)®LCD_BSTCR_BUFBYP_Pos 8¯LCD_BSTCR_BUFBYP_Msk (0x1U << LCD_BSTCR_BUFBYP_Pos)±LCD_BSTCR_VLCDPD_Pos 7²LCD_BSTCR_VLCDPD_Msk (0x1U << LCD_BSTCR_VLCDPD_Pos)´LCD_BSTCR_VLCDCFG_Pos 2µLCD_BSTCR_VLCDCFG_Msk (0x1fU << LCD_BSTCR_VLCDCFG_Pos)¶LCD_BSTCR_VLCDCFG_2_4V (0x0U << LCD_BSTCR_VLCDCFG_Pos)·LCD_BSTCR_VLCDCFG_2_6V (0x1U << LCD_BSTCR_VLCDCFG_Pos)¸LCD_BSTCR_VLCDCFG_2_8V (0x2U << LCD_BSTCR_VLCDCFG_Pos)¹LCD_BSTCR_VLCDCFG_3_0V (0x3U << LCD_BSTCR_VLCDCFG_Pos)ºLCD_BSTCR_VLCDCFG_3_2V (0x4U << LCD_BSTCR_VLCDCFG_Pos)»LCD_BSTCR_VLCDCFG_3_4V (0x5U << LCD_BSTCR_VLCDCFG_Pos)¼LCD_BSTCR_VLCDCFG_3_6V (0x6U << LCD_BSTCR_VLCDCFG_Pos)½LCD_BSTCR_VLCDCFG_3_8V (0x7U << LCD_BSTCR_VLCDCFG_Pos)¾LCD_BSTCR_VLCDCFG_4_0V (0x8U << LCD_BSTCR_VLCDCFG_Pos)¿LCD_BSTCR_VLCDCFG_4_2V (0x9U << LCD_BSTCR_VLCDCFG_Pos)ÀLCD_BSTCR_VLCDCFG_4_4V (0xaU << LCD_BSTCR_VLCDCFG_Pos)ÁLCD_BSTCR_VLCDCFG_4_6V (0xbU << LCD_BSTCR_VLCDCFG_Pos)ÂLCD_BSTCR_VLCDCFG_4_8V (0xcU << LCD_BSTCR_VLCDCFG_Pos)ÃLCD_BSTCR_VLCDCFG_5_0V (0xdU << LCD_BSTCR_VLCDCFG_Pos)ÄLCD_BSTCR_VLCDCFG_5_2V (0xeU << LCD_BSTCR_VLCDCFG_Pos)ÅLCD_BSTCR_VLCDCFG_5_4V (0xfU << LCD_BSTCR_VLCDCFG_Pos)ÇLCD_BSTCR_BOOST_TEN_Pos 1ÈLCD_BSTCR_BOOST_TEN_Msk (0x1U << LCD_BSTCR_BOOST_TEN_Pos)ÊLCD_BSTCR_BOOST_EN_Pos 0ËLCD_BSTCR_BOOST_EN_Msk (0x1U << LCD_BSTCR_BOOST_EN_Pos)ÍLCD_COM_EN_COMEN_Pos 0ÎLCD_COM_EN_COMEN_Msk (0xfU << LCD_COM_EN_COMEN_Pos)ÐLCD_SEG_EN0_SEGENx_Pos 0ÑLCD_SEG_EN0_SEGENx_Msk (0xffffffffU << LCD_SEG_EN0_SEGENx_Pos)ÓLCD_SEG_EN1_SEGENx_Pos 0ÔLCD_SEG_EN1_SEGENx_Msk (0xfffU << LCD_SEG_EN1_SEGENx_Pos)ÖLCD_COM_EN_COMEN3_Pos 3×LCD_COM_EN_COMEN3_Msk (0x1U << LCD_COM_EN_COMEN3_Pos)ÙLCD_COM_EN_COMEN2_Pos 2ÚLCD_COM_EN_COMEN2_Msk (0x1U << LCD_COM_EN_COMEN2_Pos)ÜLCD_COM_EN_COMEN1_Pos 1ÝLCD_COM_EN_COMEN1_Msk (0x1U << LCD_COM_EN_COMEN1_Pos)ßLCD_COM_EN_COMEN0_Pos 0àLCD_COM_EN_COMEN0_Msk (0x1U << LCD_COM_EN_COMEN0_Pos)âLCD_SEG_EN0_SEGEN31_Pos 31ãLCD_SEG_EN0_SEGEN31_Msk (0x1U << LCD_SEG_EN0_SEGEN31_Pos)åLCD_SEG_EN0_SEGEN30_Pos 30æLCD_SEG_EN0_SEGEN30_Msk (0x1U << LCD_SEG_EN0_SEGEN30_Pos)èLCD_SEG_EN0_SEGEN29_Pos 29éLCD_SEG_EN0_SEGEN29_Msk (0x1U << LCD_SEG_EN0_SEGEN29_Pos)ëLCD_SEG_EN0_SEGEN28_Pos 28ìLCD_SEG_EN0_SEGEN28_Msk (0x1U << LCD_SEG_EN0_SEGEN28_Pos)îLCD_SEG_EN0_SEGEN27_Pos 27ïLCD_SEG_EN0_SEGEN27_Msk (0x1U << LCD_SEG_EN0_SEGEN27_Pos)ñLCD_SEG_EN0_SEGEN26_Pos 26òLCD_SEG_EN0_SEGEN26_Msk (0x1U << LCD_SEG_EN0_SEGEN26_Pos)ôLCD_SEG_EN0_SEGEN25_Pos 25õLCD_SEG_EN0_SEGEN25_Msk (0x1U << LCD_SEG_EN0_SEGEN25_Pos)÷LCD_SEG_EN0_SEGEN24_Pos 24øLCD_SEG_EN0_SEGEN24_Msk (0x1U << LCD_SEG_EN0_SEGEN24_Pos)úLCD_SEG_EN0_SEGEN23_Pos 23ûLCD_SEG_EN0_SEGEN23_Msk (0x1U << LCD_SEG_EN0_SEGEN23_Pos)ýLCD_SEG_EN0_SEGEN22_Pos 22þLCD_SEG_EN0_SEGEN22_Msk (0x1U << LCD_SEG_EN0_SEGEN22_Pos)LCD_SEG_EN0_SEGEN21_Pos 21LCD_SEG_EN0_SEGEN21_Msk (0x1U << LCD_SEG_EN0_SEGEN21_Pos)LCD_SEG_EN0_SEGEN20_Pos 20LCD_SEG_EN0_SEGEN20_Msk (0x1U << LCD_SEG_EN0_SEGEN20_Pos)LCD_SEG_EN0_SEGEN19_Pos 19LCD_SEG_EN0_SEGEN19_Msk (0x1U << LCD_SEG_EN0_SEGEN19_Pos)LCD_SEG_EN0_SEGEN18_Pos 18LCD_SEG_EN0_SEGEN18_Msk (0x1U << LCD_SEG_EN0_SEGEN18_Pos)LCD_SEG_EN0_SEGEN17_Pos 17LCD_SEG_EN0_SEGEN17_Msk (0x1U << LCD_SEG_EN0_SEGEN17_Pos)LCD_SEG_EN0_SEGEN16_Pos 16LCD_SEG_EN0_SEGEN16_Msk (0x1U << LCD_SEG_EN0_SEGEN16_Pos)LCD_SEG_EN0_SEGEN15_Pos 15LCD_SEG_EN0_SEGEN15_Msk (0x1U << LCD_SEG_EN0_SEGEN15_Pos)LCD_SEG_EN0_SEGEN14_Pos 14LCD_SEG_EN0_SEGEN14_Msk (0x1U << LCD_SEG_EN0_SEGEN14_Pos)LCD_SEG_EN0_SEGEN13_Pos 13LCD_SEG_EN0_SEGEN13_Msk (0x1U << LCD_SEG_EN0_SEGEN13_Pos)LCD_SEG_EN0_SEGEN12_Pos 12LCD_SEG_EN0_SEGEN12_Msk (0x1U << LCD_SEG_EN0_SEGEN12_Pos)LCD_SEG_EN0_SEGEN11_Pos 11LCD_SEG_EN0_SEGEN11_Msk (0x1U << LCD_SEG_EN0_SEGEN11_Pos)¡LCD_SEG_EN0_SEGEN10_Pos 10¢LCD_SEG_EN0_SEGEN10_Msk (0x1U << LCD_SEG_EN0_SEGEN10_Pos)¤LCD_SEG_EN0_SEGEN9_Pos 9¥LCD_SEG_EN0_SEGEN9_Msk (0x1U << LCD_SEG_EN0_SEGEN9_Pos)§LCD_SEG_EN0_SEGEN8_Pos 8¨LCD_SEG_EN0_SEGEN8_Msk (0x1U << LCD_SEG_EN0_SEGEN8_Pos)ªLCD_SEG_EN0_SEGEN7_Pos 7«LCD_SEG_EN0_SEGEN7_Msk (0x1U << LCD_SEG_EN0_SEGEN7_Pos)LCD_SEG_EN0_SEGEN6_Pos 6®LCD_SEG_EN0_SEGEN6_Msk (0x1U << LCD_SEG_EN0_SEGEN6_Pos)°LCD_SEG_EN0_SEGEN5_Pos 5±LCD_SEG_EN0_SEGEN5_Msk (0x1U << LCD_SEG_EN0_SEGEN5_Pos)³LCD_SEG_EN0_SEGEN4_Pos 4´LCD_SEG_EN0_SEGEN4_Msk (0x1U << LCD_SEG_EN0_SEGEN4_Pos)¶LCD_SEG_EN0_SEGEN3_Pos 3·LCD_SEG_EN0_SEGEN3_Msk (0x1U << LCD_SEG_EN0_SEGEN3_Pos)¹LCD_SEG_EN0_SEGEN2_Pos 2ºLCD_SEG_EN0_SEGEN2_Msk (0x1U << LCD_SEG_EN0_SEGEN2_Pos)¼LCD_SEG_EN0_SEGEN1_Pos 1½LCD_SEG_EN0_SEGEN1_Msk (0x1U << LCD_SEG_EN0_SEGEN1_Pos)¿LCD_SEG_EN0_SEGEN0_Pos 0ÀLCD_SEG_EN0_SEGEN0_Msk (0x1U << LCD_SEG_EN0_SEGEN0_Pos)ÂLCD_SEG_EN1_SEGEN43_Pos 11ÃLCD_SEG_EN1_SEGEN43_Msk (0x1U << LCD_SEG_EN1_SEGEN43_Pos)ÅLCD_SEG_EN1_SEGEN42_Pos 10ÆLCD_SEG_EN1_SEGEN42_Msk (0x1U << LCD_SEG_EN1_SEGEN42_Pos)ÈLCD_SEG_EN1_SEGEN41_Pos 9ÉLCD_SEG_EN1_SEGEN41_Msk (0x1U << LCD_SEG_EN1_SEGEN41_Pos)ËLCD_SEG_EN1_SEGEN40_Pos 8ÌLCD_SEG_EN1_SEGEN40_Msk (0x1U << LCD_SEG_EN1_SEGEN40_Pos)ÎLCD_SEG_EN1_SEGEN39_Pos 7ÏLCD_SEG_EN1_SEGEN39_Msk (0x1U << LCD_SEG_EN1_SEGEN39_Pos)ÑLCD_SEG_EN1_SEGEN38_Pos 6ÒLCD_SEG_EN1_SEGEN38_Msk (0x1U << LCD_SEG_EN1_SEGEN38_Pos)ÔLCD_SEG_EN1_SEGEN37_Pos 5ÕLCD_SEG_EN1_SEGEN37_Msk (0x1U << LCD_SEG_EN1_SEGEN37_Pos)×LCD_SEG_EN1_SEGEN36_Pos 4ØLCD_SEG_EN1_SEGEN36_Msk (0x1U << LCD_SEG_EN1_SEGEN36_Pos)ÚLCD_SEG_EN1_SEGEN35_Pos 3ÛLCD_SEG_EN1_SEGEN35_Msk (0x1U << LCD_SEG_EN1_SEGEN35_Pos)ÝLCD_SEG_EN1_SEGEN34_Pos 2ÞLCD_SEG_EN1_SEGEN34_Msk (0x1U << LCD_SEG_EN1_SEGEN34_Pos)àLCD_SEG_EN1_SEGEN33_Pos 1áLCD_SEG_EN1_SEGEN33_Msk (0x1U << LCD_SEG_EN1_SEGEN33_Pos)ãLCD_SEG_EN1_SEGEN32_Pos 0äLCD_SEG_EN1_SEGEN32_Msk (0x1U << LCD_SEG_EN1_SEGEN32_Pos)æLCD_SEG_EN1_COMEN7_Pos 11çLCD_SEG_EN1_COMEN7_Msk (0x1U << LCD_SEG_EN1_COMEN7_Pos)éLCD_SEG_EN1_COMEN6_Pos 10êLCD_SEG_EN1_COMEN6_Msk (0x1U << LCD_SEG_EN1_COMEN6_Pos)ìLCD_SEG_EN1_COMEN5_Pos 9íLCD_SEG_EN1_COMEN5_Msk (0x1U << LCD_SEG_EN1_COMEN5_Pos)ïLCD_SEG_EN1_COMEN4_Pos 8ðLCD_SEG_EN1_COMEN4_Msk (0x1U << LCD_SEG_EN1_COMEN4_Pos)`T ..\Drivers\..\Core\Include\fm33a0xxev_lcd.hFM33A0XXEV.h¼
..\Drivers\fm33a0xxev_lcd.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM__FM33A0XXEV_DMA_H 2DMA_GCR_DMA_ADDRERR_EN_Pos 15DMA_GCR_DMA_ADDRERR_EN_Msk (0x1U << DMA_GCR_DMA_ADDRERR_EN_Pos)7DMA_GCR_DMAEN_Pos 0:DMA_GCR_DMAEN_Msk (0x1U << DMA_GCR_DMAEN_Pos)<DMA_CHxCR_CHxTSIZE_Pos 16=DMA_CHxCR_CHxTSIZE_Msk (0x1fffU << DMA_CHxCR_CHxTSIZE_Pos)?DMA_CHxCR_CHxPRI_Pos 12DDMA_CHxCR_CHxPRI_Msk (0x3U << DMA_CHxCR_CHxPRI_Pos)EDMA_CHxCR_CHxPRI_LOW (0x0U << DMA_CHxCR_CHxPRI_Pos)FDMA_CHxCR_CHxPRI_MEDIUM (0x1U << DMA_CHxCR_CHxPRI_Pos)GDMA_CHxCR_CHxPRI_HIGH (0x2U << DMA_CHxCR_CHxPRI_Pos)HDMA_CHxCR_CHxPRI_VERY_HIGH (0x3U << DMA_CHxCR_CHxPRI_Pos)JDMA_CHxCR_CHxINC_Pos 11MDMA_CHxCR_CHxINC_Msk (0x1U << DMA_CHxCR_CHxINC_Pos)NDMA_CHxCR_CHxINC_INCREASE (0x1U << DMA_CHxCR_CHxINC_Pos)ODMA_CHxCR_CHxINC_DECREASE (0x0U << DMA_CHxCR_CHxINC_Pos)QDMA_CHxCR_CHxSSEL_Pos 8SDMA_CHxCR_CHxSSEL_Msk (0x7U << DMA_CHxCR_CHxSSEL_Pos)UDMA_CHxCR_CH0SSEL_ADC (0x0U << DMA_CHxCR_CHxSSEL_Pos)VDMA_CHxCR_CH0SSEL_SPI3_RX (0x1U << DMA_CHxCR_CHxSSEL_Pos)WDMA_CHxCR_CH0SSEL_LPUART0_RX (0x2U << DMA_CHxCR_CHxSSEL_Pos)XDMA_CHxCR_CH0SSEL_LPUART1_RX (0x3U << DMA_CHxCR_CHxSSEL_Pos)YDMA_CHxCR_CH0SSEL_UART2_RX (0x4U << DMA_CHxCR_CHxSSEL_Pos)ZDMA_CHxCR_CH0SSEL_UART4_RX (0x5U << DMA_CHxCR_CHxSSEL_Pos)[DMA_CHxCR_CH0SSEL_AES_IN (0x6U << DMA_CHxCR_CHxSSEL_Pos)\DMA_CHxCR_CH0SSEL_QSPI (0x7U << DMA_CHxCR_CHxSSEL_Pos)^DMA_CHxCR_CH1SSEL_ADC (0x0U << DMA_CHxCR_CHxSSEL_Pos)_DMA_CHxCR_CH1SSEL_SPI0_RX (0x1U << DMA_CHxCR_CHxSSEL_Pos)`DMA_CHxCR_CH1SSEL_SPI2_RX (0x2U << DMA_CHxCR_CHxSSEL_Pos)aDMA_CHxCR_CH1SSEL_SPI3_TX (0x3U << DMA_CHxCR_CHxSSEL_Pos)bDMA_CHxCR_CH1SSEL_UART0_RX (0x4U << DMA_CHxCR_CHxSSEL_Pos)cDMA_CHxCR_CH1SSEL_UART2_TX (0x5U << DMA_CHxCR_CHxSSEL_Pos)dDMA_CHxCR_CH1SSEL_UART3_RX (0x6U << DMA_CHxCR_CHxSSEL_Pos)eDMA_CHxCR_CH1SSEL_U7816_RX (0x7U << DMA_CHxCR_CHxSSEL_Pos)gDMA_CHxCR_CH2SSEL_SPI0_TX (0x0U << DMA_CHxCR_CHxSSEL_Pos)hDMA_CHxCR_CH2SSEL_SPI2_TX (0x1U << DMA_CHxCR_CHxSSEL_Pos)iDMA_CHxCR_CH2SSEL_SPI4_RX (0x2U << DMA_CHxCR_CHxSSEL_Pos)jDMA_CHxCR_CH2SSEL_UART0_TX (0x3U << DMA_CHxCR_CHxSSEL_Pos)kDMA_CHxCR_CH2SSEL_UART3_TX (0x4U << DMA_CHxCR_CHxSSEL_Pos)lDMA_CHxCR_CH2SSEL_UART5_RX (0x5U << DMA_CHxCR_CHxSSEL_Pos)mDMA_CHxCR_CH2SSEL_U7816_TX (0x6U << DMA_CHxCR_CHxSSEL_Pos)nDMA_CHxCR_CH2SSEL_AES_OUT (0x7U << DMA_CHxCR_CHxSSEL_Pos)pDMA_CHxCR_CH3SSEL_SPI1_RX (0x0U << DMA_CHxCR_CHxSSEL_Pos)qDMA_CHxCR_CH3SSEL_SPI4_TX (0x1U << DMA_CHxCR_CHxSSEL_Pos)rDMA_CHxCR_CH3SSEL_LPUART0_RX (0x2U << DMA_CHxCR_CHxSSEL_Pos)sDMA_CHxCR_CH3SSEL_UART1_RX (0x3U << DMA_CHxCR_CHxSSEL_Pos)tDMA_CHxCR_CH3SSEL_UART4_RX (0x4U << DMA_CHxCR_CHxSSEL_Pos)uDMA_CHxCR_CH3SSEL_UART5_TX (0x5U << DMA_CHxCR_CHxSSEL_Pos)vDMA_CHxCR_CH3SSEL_I2C0_TX (0x6U << DMA_CHxCR_CHxSSEL_Pos)wDMA_CHxCR_CH3SSEL_AES_IN (0x7U << DMA_CHxCR_CHxSSEL_Pos)yDMA_CHxCR_CH4SSEL_SPI1_TX (0x0U << DMA_CHxCR_CHxSSEL_Pos)zDMA_CHxCR_CH4SSEL_SPI3_RX (0x1U << DMA_CHxCR_CHxSSEL_Pos){DMA_CHxCR_CH4SSEL_LPUART0_TX (0x2U << DMA_CHxCR_CHxSSEL_Pos)|DMA_CHxCR_CH4SSEL_UART1_TX (0x3U << DMA_CHxCR_CHxSSEL_Pos)}DMA_CHxCR_CH4SSEL_UART2_RX (0x4U << DMA_CHxCR_CHxSSEL_Pos)~DMA_CHxCR_CH4SSEL_UART4_TX (0x5U << DMA_CHxCR_CHxSSEL_Pos)DMA_CHxCR_CH4SSEL_I2C0_RX (0x6U << DMA_CHxCR_CHxSSEL_Pos)DMA_CHxCR_CH4SSEL_AES_OUT (0x7U << DMA_CHxCR_CHxSSEL_Pos)DMA_CHxCR_CH5SSEL_SPI0_RX (0x0U << DMA_CHxCR_CHxSSEL_Pos)DMA_CHxCR_CH5SSEL_SPI2_RX (0x1U << DMA_CHxCR_CHxSSEL_Pos)DMA_CHxCR_CH5SSEL_LPUART1_RX (0x2U << DMA_CHxCR_CHxSSEL_Pos)DMA_CHxCR_CH5SSEL_UART1_RX (0x3U << DMA_CHxCR_CHxSSEL_Pos)DMA_CHxCR_CH5SSEL_UART2_TX (0x4U << DMA_CHxCR_CHxSSEL_Pos)DMA_CHxCR_CH5SSEL_UART3_RX (0x5U << DMA_CHxCR_CHxSSEL_Pos)DMA_CHxCR_CH5SSEL_UART5_RX (0x6U << DMA_CHxCR_CHxSSEL_Pos)DMA_CHxCR_CH5SSEL_I2C1_TX (0x7U << DMA_CHxCR_CHxSSEL_Pos)DMA_CHxCR_CH6SSEL_SPI0_TX (0x0U << DMA_CHxCR_CHxSSEL_Pos)DMA_CHxCR_CH6SSEL_SPI2_TX (0x1U << DMA_CHxCR_CHxSSEL_Pos)DMA_CHxCR_CH6SSEL_LPUART1_TX (0x2U << DMA_CHxCR_CHxSSEL_Pos)DMA_CHxCR_CH6SSEL_UART1_TX (0x3U << DMA_CHxCR_CHxSSEL_Pos)DMA_CHxCR_CH6SSEL_UART3_TX (0x4U << DMA_CHxCR_CHxSSEL_Pos)DMA_CHxCR_CH6SSEL_UART5_TX (0x5U << DMA_CHxCR_CHxSSEL_Pos)DMA_CHxCR_CH6SSEL_I2C1_RX (0x6U << DMA_CHxCR_CHxSSEL_Pos)DMA_CHxCR_CH6SSEL_CRC (0x7U << DMA_CHxCR_CHxSSEL_Pos)DMA_CHxCR_CH7SSEL_ADC (0x0U << DMA_CHxCR_CHxSSEL_Pos)DMA_CHxCR_CH7SSEL_SPI1_RX (0x1U << DMA_CHxCR_CHxSSEL_Pos)DMA_CHxCR_CH7SSEL_SPI3_RX (0x2U << DMA_CHxCR_CHxSSEL_Pos)DMA_CHxCR_CH7SSEL_LPUART0_RX (0x3U << DMA_CHxCR_CHxSSEL_Pos)DMA_CHxCR_CH7SSEL_UART0_RX (0x4U << DMA_CHxCR_CHxSSEL_Pos)DMA_CHxCR_CH7SSEL_UART2_RX (0x5U << DMA_CHxCR_CHxSSEL_Pos)DMA_CHxCR_CH7SSEL_UART4_RX (0x6U << DMA_CHxCR_CHxSSEL_Pos)DMA_CHxCR_CH7SSEL_QSPI (0x7U << DMA_CHxCR_CHxSSEL_Pos)DMA_CHxCR_CH8SSEL_ADC (0x0U << DMA_CHxCR_CHxSSEL_Pos)DMA_CHxCR_CH8SSEL_SPI1_TX (0x1U << DMA_CHxCR_CHxSSEL_Pos)DMA_CHxCR_CH8SSEL_SPI2_RX (0x2U << DMA_CHxCR_CHxSSEL_Pos) DMA_CHxCR_CH8SSEL_SPI3_TX (0x3U << DMA_CHxCR_CHxSSEL_Pos)¡DMA_CHxCR_CH8SSEL_LPUART0_TX (0x4U << DMA_CHxCR_CHxSSEL_Pos)¢DMA_CHxCR_CH8SSEL_UART0_TX (0x5U << DMA_CHxCR_CHxSSEL_Pos)£DMA_CHxCR_CH8SSEL_UART2_TX (0x6U << DMA_CHxCR_CHxSSEL_Pos)¤DMA_CHxCR_CH8SSEL_UART4_TX (0x7U << DMA_CHxCR_CHxSSEL_Pos)¦DMA_CHxCR_CH9SSEL_SPI0_RX (0x0U << DMA_CHxCR_CHxSSEL_Pos)§DMA_CHxCR_CH9SSEL_SPI2_TX (0x1U << DMA_CHxCR_CHxSSEL_Pos)¨DMA_CHxCR_CH9SSEL_SPI4_RX (0x2U << DMA_CHxCR_CHxSSEL_Pos)©DMA_CHxCR_CH9SSEL_LPUART1_RX (0x3U << DMA_CHxCR_CHxSSEL_Pos)ªDMA_CHxCR_CH9SSEL_UART1_RX (0x4U << DMA_CHxCR_CHxSSEL_Pos)«DMA_CHxCR_CH9SSEL_UART3_RX (0x5U << DMA_CHxCR_CHxSSEL_Pos)¬DMA_CHxCR_CH9SSEL_UART5_RX (0x6U << DMA_CHxCR_CHxSSEL_Pos)DMA_CHxCR_CH9SSEL_I2C0_TX (0x7U << DMA_CHxCR_CHxSSEL_Pos)¯DMA_CHxCR_CH10SSEL_SPI0_TX (0x0U << DMA_CHxCR_CHxSSEL_Pos)°DMA_CHxCR_CH10SSEL_SPI4_TX (0x1U << DMA_CHxCR_CHxSSEL_Pos)±DMA_CHxCR_CH10SSEL_LPUART1_TX (0x2U << DMA_CHxCR_CHxSSEL_Pos)²DMA_CHxCR_CH10SSEL_UART1_TX (0x3U << DMA_CHxCR_CHxSSEL_Pos)³DMA_CHxCR_CH10SSEL_UART3_TX (0x4U << DMA_CHxCR_CHxSSEL_Pos)´DMA_CHxCR_CH10SSEL_UART5_TX (0x5U << DMA_CHxCR_CHxSSEL_Pos)µDMA_CHxCR_CH10SSEL_I2C0_RX (0x6U << DMA_CHxCR_CHxSSEL_Pos)¶DMA_CHxCR_CH10SSEL_CRC (0x7U << DMA_CHxCR_CHxSSEL_Pos)¸DMA_CHxCR_CIRC_UPD_Pos 7¼DMA_CHxCR_CIRC_UPD_Msk (0x1U << DMA_CHxCR_CIRC_UPD_Pos)ÁDMA_CHxCR_DIR_Pos 6ÄDMA_CHxCR_DIR_Msk (0x1U << DMA_CHxCR_DIR_Pos)ÅDMA_CHxCR_DIR_TO_RAM (0x0U << DMA_CHxCR_DIR_Pos)ÆDMA_CHxCR_DIR_TO_PER (0x1U << DMA_CHxCR_DIR_Pos)ÈDMA_CHxCR_BDW_Pos 4ÍDMA_CHxCR_BDW_Msk (0x3U << DMA_CHxCR_BDW_Pos)ÎDMA_CHxCR_BDW_8BITS (0x0U << DMA_CHxCR_BDW_Pos)ÏDMA_CHxCR_BDW_16BITS (0x1U << DMA_CHxCR_BDW_Pos)ÐDMA_CHxCR_BDW_32BITS (0x2U << DMA_CHxCR_BDW_Pos)ÒDMA_CHxCR_CIRC_Pos 3ÕDMA_CHxCR_CIRC_Msk (0x1U << DMA_CHxCR_CIRC_Pos)ÙDMA_CHxCR_CHxFTIE_Pos 2ÜDMA_CHxCR_CHxFTIE_Msk (0x1U << DMA_CHxCR_CHxFTIE_Pos)àDMA_CHxCR_CHxHTIE_Pos 1ãDMA_CHxCR_CHxHTIE_Msk (0x1U << DMA_CHxCR_CHxHTIE_Pos)çDMA_CHxCR_ChxEN_Pos 0êDMA_CHxCR_ChxEN_Msk (0x1U << DMA_CHxCR_ChxEN_Pos)îDMA_CHxMAR_CHxMEMAD_Pos 0ôDMA_CHxMAR_CHxMEMAD_Msk (0xffffffffU << DMA_CHxMAR_CHxMEMAD_Pos)öDMA_CH11CR_CH11TSIZE_Pos 16÷DMA_CH11CR_CH11TSIZE_Msk (0x1fffU << DMA_CH11CR_CH11TSIZE_Pos)ùDMA_CH11CR_CH11PRI_Pos 12þDMA_CH11CR_CH11PRI_Msk (0x3U << DMA_CH11CR_CH11PRI_Pos)ÿDMA_CH11CR_CH11PRI_LOW (0x0U << DMA_CH11CR_CH11PRI_Pos)DMA_CH11CR_CH11PRI_MEDIUM (0x1U << DMA_CH11CR_CH11PRI_Pos)DMA_CH11CR_CH11PRI_HIGH (0x2U << DMA_CH11CR_CH11PRI_Pos)DMA_CH11CR_CH11PRI_VERY_HIGH (0x3U << DMA_CH11CR_CH11PRI_Pos)DMA_CH11CR_CH11DIR_Pos 10DMA_CH11CR_CH11DIR_Msk (0x1U << DMA_CH11CR_CH11DIR_Pos)DMA_CH11CR_CH11DIR_TO_RAM (0x1U << DMA_CH11CR_CH11DIR_Pos)DMA_CH11CR_CH11DIR_TO_FLASH (0x0U << DMA_CH11CR_CH11DIR_Pos)DMA_CH11CR_CH11RI_Pos 9DMA_CH11CR_CH11RI_Msk (0x1U << DMA_CH11CR_CH11RI_Pos)DMA_CH11CR_CH11RI_INCREASE (0x1U << DMA_CH11CR_CH11RI_Pos)DMA_CH11CR_CH11RI_DECREASE (0x0U << DMA_CH11CR_CH11RI_Pos)DMA_CH11CR_CH11FI_Pos 8DMA_CH11CR_CH11FI_Msk (0x1U << DMA_CH11CR_CH11FI_Pos)DMA_CH11CR_CH11FI_INCREASE (0x1U << DMA_CH11CR_CH11FI_Pos)DMA_CH11CR_CH11FI_DECREASE (0x0U << DMA_CH11CR_CH11FI_Pos)DMA_CH11CR_CH11FTIE_Pos 2DMA_CH11CR_CH11FTIE_Msk (0x1U << DMA_CH11CR_CH11FTIE_Pos) DMA_CH11CR_CH11HTIE_Pos 1£DMA_CH11CR_CH11HTIE_Msk (0x1U << DMA_CH11CR_CH11HTIE_Pos)§DMA_CH11CR_CH11EN_Pos 0ªDMA_CH11CR_CH11EN_Msk (0x1U << DMA_CH11CR_CH11EN_Pos)®DMA_CH11FAR_CH11FLSAD_Pos 0±DMA_CH11FAR_CH11FLSAD_Msk (0x7fffU << DMA_CH11FAR_CH11FLSAD_Pos)³DMA_CH11RAR_CH7RAMAD_Pos 0µDMA_CH11RAR_CH7RAMAD_Msk (0x7fffU << DMA_CH11RAR_CH7RAMAD_Pos)·DMA_ISR_DMA_ADDRERR_Pos 28¸DMA_ISR_DMA_ADDRERR_Msk (0x1U << DMA_ISR_DMA_ADDRERR_Pos)ºDMA_ISR_DMACHFT_Pos 16½DMA_ISR_DMACHFT_Msk (0xfffU << DMA_ISR_DMACHFT_Pos)¿DMA_ISR_DMACHHT_Pos 0ÀDMA_ISR_DMACHHT_Msk (0xfffU << DMA_ISR_DMACHHT_Pos)ÂDMA_CHxCSR_CHxTSIZE_SDW_Pos 16ÃDMA_CHxCSR_CHxTSIZE_SDW_Msk (0x1fffU << DMA_CHxCSR_CHxTSIZE_SDW_Pos)ÅDMA_CHxCSR_CHxINC_SDW_Pos 11ÆDMA_CHxCSR_CHxINC_SDW_Msk (0x1U << DMA_CHxCSR_CHxINC_SDW_Pos)ÈDMA_CHxMASR_CHxMAD_SDW_Pos 0ÊDMA_CHxMASR_CHxMAD_SDW_Msk (0xffffffffU << DMA_CHxMASR_CHxMAD_SDW_Pos)`T ..\Drivers\..\Core\Include\fm33a0xxev_dma.hFM33A0XXEV.hl
..\Drivers\fm33a0xxev_dma.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMÈDMA_CH0DMA_CH1DMA_CH2DMA_CH3DMA_CH4DMA_CH5DMA_CH6DMA_CH7DMA_CH8DMA_CH9    DMA_CH10
DMA_CH11PDMA_CH_Type½*Õ0CHxH#CHxTSIZEf#CHxPRIf#CHxINCf#CHxSSELf#CHxDIRf#CHxBDWf#CHxCICR#CHxFTIE#CHxHTIE#CHxEN#CHxRAMADf# CH11RIf#$CH11FIf#(CH11FLSADf#,PDMA_InitTypeDef[0__FM33A0XXEV_GPIO_H cIS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))lIS_GPIO_INTERRUPT_TRIGER_EDGE(EDGE) (((EDGE) == EXTI_RISING) || ((EDGE) == EXTI_FALLING)|| ((EDGE) == EXTI_BOTH)|| ((EDGE) == EXTIDISABLE))}IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || ((PERIPH) == GPIOB) || ((PERIPH) == GPIOC) || ((PERIPH) == GPIOD) || ((PERIPH) == GPIOE) || ((PERIPH) == GPIOF) || ((PERIPH) == GPIOG))IS_GPIO_HD_PERIPH(PERIPH) ((PERIPH) == GPIOH)GPIO_Pin_0 ((uint32_t)0x00000001)GPIO_Pin_1 ((uint32_t)0x00000002)GPIO_Pin_2 ((uint32_t)0x00000004)GPIO_Pin_3 ((uint32_t)0x00000008)GPIO_Pin_4 ((uint32_t)0x00000010)GPIO_Pin_5 ((uint32_t)0x00000020)GPIO_Pin_6 ((uint32_t)0x00000040)GPIO_Pin_7 ((uint32_t)0x00000080)GPIO_Pin_8 ((uint32_t)0x00000100)GPIO_Pin_9 ((uint32_t)0x00000200)GPIO_Pin_10 ((uint32_t)0x00000400)GPIO_Pin_11 ((uint32_t)0x00000800)GPIO_Pin_12 ((uint32_t)0x00001000)GPIO_Pin_13 ((uint32_t)0x00002000)GPIO_Pin_14 ((uint32_t)0x00004000)GPIO_Pin_15 ((uint32_t)0x00008000)GPIO_Pin_All ((uint16_t)0xFFFF)IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00))IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || ((PIN) == GPIO_Pin_1) || ((PIN) == GPIO_Pin_2) || ((PIN) == GPIO_Pin_3) || ((PIN) == GPIO_Pin_4) || ((PIN) == GPIO_Pin_5) || ((PIN) == GPIO_Pin_6) || ((PIN) == GPIO_Pin_7) || ((PIN) == GPIO_Pin_8) || ((PIN) == GPIO_Pin_9) || ((PIN) == GPIO_Pin_10) || ((PIN) == GPIO_Pin_11) || ((PIN) == GPIO_Pin_12) || ((PIN) == GPIO_Pin_13) || ((PIN) == GPIO_Pin_14) || ((PIN) == GPIO_Pin_15))¯IS_GET_GPIOH_PIN(PIN) (((PIN) == GPIO_Pin_0) || ((PIN) == GPIO_Pin_1) || ((PIN) == GPIO_Pin_2) || ((PIN) == GPIO_Pin_3))·PINWKEN_PD6 7¸PINWKEN_PE9 6¹PINWKEN_PE2 5ºPINWKEN_PA13 4»PINWKEN_PG7 3¼PINWKEN_PC13 2½PINWKEN_PB0 1¾PINWKEN_PF5 0ÁGPIOx_INEN_INEN_Pos 0ÂGPIOx_INEN_INEN_Msk (0xffffU << GPIOx_INEN_INEN_Pos)ÈGPIOx_PUEN_PUEN_Pos 0ÉGPIOx_PUEN_PUEN_Msk (0xffffU << GPIOx_PUEN_PUEN_Pos)ÏGPIOx_ODEN_ODEN_Pos 0ÐGPIOx_ODEN_ODEN_Msk (0xffffU << GPIOx_ODEN_ODEN_Pos)ÖGPIOx_FCR_Px15FCR_Pos 30×GPIOx_FCR_Px15FCR_Msk (0x03U << GPIOx_FCR_Px15FCR_Pos)ÝGPIOx_FCR_Px14FCR_Pos 28ÞGPIOx_FCR_Px14FCR_Msk (0x03U << GPIOx_FCR_Px14FCR_Pos)äGPIOx_FCR_Px13FCR_Pos 26åGPIOx_FCR_Px13FCR_Msk (0x03U << GPIOx_FCR_Px13FCR_Pos)ëGPIOx_FCR_Px12FCR_Pos 24ìGPIOx_FCR_Px12FCR_Msk (0x03U << GPIOx_FCR_Px12FCR_Pos)òGPIOx_FCR_Px11FCR_Pos 22óGPIOx_FCR_Px11FCR_Msk (0x03U << GPIOx_FCR_Px11FCR_Pos)ùGPIOx_FCR_Px10FCR_Pos 20úGPIOx_FCR_Px10FCR_Msk (0x03U << GPIOx_FCR_Px10FCR_Pos)GPIOx_FCR_Px9FCR_Pos 18GPIOx_FCR_Px9FCR_Msk (0x03U << GPIOx_FCR_Px9FCR_Pos)GPIOx_FCR_Px8FCR_Pos 16GPIOx_FCR_Px8FCR_Msk (0x03U << GPIOx_FCR_Px8FCR_Pos)GPIOx_FCR_Px7FCR_Pos 14GPIOx_FCR_Px7FCR_Msk (0x03U << GPIOx_FCR_Px7FCR_Pos)GPIOx_FCR_Px6FCR_Pos 12GPIOx_FCR_Px6FCR_Msk (0x03U << GPIOx_FCR_Px6FCR_Pos)GPIOx_FCR_Px5FCR_Pos 10GPIOx_FCR_Px5FCR_Msk (0x03U << GPIOx_FCR_Px5FCR_Pos)£GPIOx_FCR_Px4FCR_Pos 8¤GPIOx_FCR_Px4FCR_Msk (0x03U << GPIOx_FCR_Px4FCR_Pos)ªGPIOx_FCR_Px3FCR_Pos 6«GPIOx_FCR_Px3FCR_Msk (0x03U << GPIOx_FCR_Px3FCR_Pos)±GPIOx_FCR_Px2FCR_Pos 4²GPIOx_FCR_Px2FCR_Msk (0x03U << GPIOx_FCR_Px2FCR_Pos)¸GPIOx_FCR_Px1FCR_Pos 2¹GPIOx_FCR_Px1FCR_Msk (0x03U << GPIOx_FCR_Px1FCR_Pos)¿GPIOx_FCR_Px0FCR_Pos 0ÀGPIOx_FCR_Px0FCR_Msk (0x03U << GPIOx_FCR_Px0FCR_Pos)ÈGPIOx_DO_DO_Pos 0ÉGPIOx_DO_DO_Msk (0xffffU << GPIOx_DO_DO_Pos)ÍGPIOx_DSET_DSET_Pos 0ÎGPIOx_DSET_DSET_Msk (0xffffU << GPIOx_DSET_DSET_Pos)ÔGPIOx_DRST_DRESET_Pos 0ÕGPIOx_DRST_DRESET_Msk (0xffffU << GPIOx_DRST_DRESET_Pos)ÛGPIOx_DIN_DIN_Pos 0ÜGPIOx_DIN_DIN_Msk (0xffffU << GPIOx_DIN_DIN_Pos)âGPIOx_DFS_DFS_Pos 0ãGPIOx_DFS_DFS_Msk (0xffffU << GPIOx_DFS_DFS_Pos)éGPIOx_ANEN_ANEN_Pos 0êGPIOx_ANEN_ANEN_Msk (0xffffU << GPIOx_ANEN_ANEN_Pos)öGPIO_FOUTSEL_FOUT1SEL_Pos 8÷GPIO_FOUTSEL_FOUT1SEL_Msk (0x1fU << GPIO_FOUTSEL_FOUT1SEL_Pos)øGPIO_FOUTSEL_FOUT1SEL_XTLF (0x0U << GPIO_FOUTSEL_FOUT1SEL_Pos)ùGPIO_FOUTSEL_FOUT1SEL_RCLP (0x1U << GPIO_FOUTSEL_FOUT1SEL_Pos)úGPIO_FOUTSEL_FOUT1SEL_RCHFD64 (0x2U << GPIO_FOUTSEL_FOUT1SEL_Pos)ûGPIO_FOUTSEL_FOUT1SEL_LSCLK (0x3U << GPIO_FOUTSEL_FOUT1SEL_Pos)üGPIO_FOUTSEL_FOUT1SEL_AHBCLKD64 (0x4U << GPIO_FOUTSEL_FOUT1SEL_Pos)ýGPIO_FOUTSEL_FOUT1SEL_RTC_TM (0x5U << GPIO_FOUTSEL_FOUT1SEL_Pos)þGPIO_FOUTSEL_FOUT1SEL_PLLHD64 (0x6U << GPIO_FOUTSEL_FOUT1SEL_Pos)ÿGPIO_FOUTSEL_FOUT1SEL_RTCCLK64Hz (0x7U << GPIO_FOUTSEL_FOUT1SEL_Pos)GPIO_FOUTSEL_FOUT1SEL_APBCLKD64 (0x8U << GPIO_FOUTSEL_FOUT1SEL_Pos)GPIO_FOUTSEL_FOUT1SEL_PLL_L (0x9U << GPIO_FOUTSEL_FOUT1SEL_Pos)GPIO_FOUTSEL_FOUT1SEL_RCMF (0xAU << GPIO_FOUTSEL_FOUT1SEL_Pos)GPIO_FOUTSEL_FOUT1SEL_RCHF (0xBU << GPIO_FOUTSEL_FOUT1SEL_Pos)GPIO_FOUTSEL_FOUT1SEL_XTHFD64 (0xCU << GPIO_FOUTSEL_FOUT1SEL_Pos)GPIO_FOUTSEL_FOUT1SEL_ADCCLK (0xDU << GPIO_FOUTSEL_FOUT1SEL_Pos)GPIO_FOUTSEL_FOUT1SEL_PLL_H (0xEU << GPIO_FOUTSEL_FOUT1SEL_Pos)GPIO_FOUTSEL_FOUT1SEL_BOOST_FLAG (0x10U << GPIO_FOUTSEL_FOUT1SEL_Pos)GPIO_FOUTSEL_FOUT1SEL_AUTOTRIM_OUTPUT (0x11U << GPIO_FOUTSEL_FOUT1SEL_Pos)GPIO_FOUTSEL_FOUT0SEL_Pos 0GPIO_FOUTSEL_FOUT0SEL_Msk (0x1fU << GPIO_FOUTSEL_FOUT0SEL_Pos)GPIO_FOUTSEL_FOUT0SEL_XTLF (0x0U << GPIO_FOUTSEL_FOUT0SEL_Pos)GPIO_FOUTSEL_FOUT0SEL_RCLP (0x1U << GPIO_FOUTSEL_FOUT0SEL_Pos)GPIO_FOUTSEL_FOUT0SEL_RCHFD64 (0x2U << GPIO_FOUTSEL_FOUT0SEL_Pos)GPIO_FOUTSEL_FOUT0SEL_LSCLK (0x3U << GPIO_FOUTSEL_FOUT0SEL_Pos)GPIO_FOUTSEL_FOUT0SEL_AHBCLKD64 (0x4U << GPIO_FOUTSEL_FOUT0SEL_Pos)GPIO_FOUTSEL_FOUT0SEL_RTC_TM (0x5U << GPIO_FOUTSEL_FOUT0SEL_Pos)GPIO_FOUTSEL_FOUT0SEL_PLLHD64 (0x6U << GPIO_FOUTSEL_FOUT0SEL_Pos)GPIO_FOUTSEL_FOUT0SEL_RTCCLK64Hz (0x7U << GPIO_FOUTSEL_FOUT0SEL_Pos)GPIO_FOUTSEL_FOUT0SEL_APBCLKD64 (0x8U << GPIO_FOUTSEL_FOUT0SEL_Pos)GPIO_FOUTSEL_FOUT0SEL_PLL_L (0x9U << GPIO_FOUTSEL_FOUT0SEL_Pos)GPIO_FOUTSEL_FOUT0SEL_RCMF (0xAU << GPIO_FOUTSEL_FOUT0SEL_Pos)GPIO_FOUTSEL_FOUT0SEL_RCHF (0xBU << GPIO_FOUTSEL_FOUT0SEL_Pos)GPIO_FOUTSEL_FOUT0SEL_XTHFD64 (0xCU << GPIO_FOUTSEL_FOUT0SEL_Pos)GPIO_FOUTSEL_FOUT0SEL_ADCCLK (0xDU << GPIO_FOUTSEL_FOUT0SEL_Pos)GPIO_FOUTSEL_FOUT0SEL_PLL_H (0xEU << GPIO_FOUTSEL_FOUT0SEL_Pos)GPIO_FOUTSEL_FOUT0SEL_BOOST_FLAG (0x10U << GPIO_FOUTSEL_FOUT0SEL_Pos)GPIO_IOMCR_IOMUXSEL_Pos 1GPIO_IOMCR_IOMUXSEL_Msk (0x3U << GPIO_IOMCR_IOMUXSEL_Pos) GPIO_IOMCR_IOMUXSEL_PD6 (0x0U << GPIO_IOMCR_IOMUXSEL_Pos)¡GPIO_IOMCR_IOMUXSEL_PD7 (0x1U << GPIO_IOMCR_IOMUXSEL_Pos)¢GPIO_IOMCR_IOMUXSEL_PG2 (0x2U << GPIO_IOMCR_IOMUXSEL_Pos)£GPIO_IOMCR_IOMUXSEL_PG3 (0x3U << GPIO_IOMCR_IOMUXSEL_Pos)¥GPIO_IOMCR_IOMUXEN_Pos 0¦GPIO_IOMCR_IOMCUEN_Msk (0x1U << GPIO_IOMCR_IOMUXEN_Pos)¨GPIO_PINWKEN_WKISEL_Pos 31©GPIO_PINWKEN_WKISEL_Msk (0x1U << GPIO_PINWKEN_WKISEL_Pos)ªGPIO_PINWKEN_WKISEL_NMI (0x0U << GPIO_PINWKEN_WKISEL_Pos)«GPIO_PINWKEN_WKISEL_46 (0x1U << GPIO_PINWKEN_WKISEL_Pos)GPIO_PINWKEN_PINWKSEL_Pos 8®GPIO_PINWKEN_PINWKSEL_Msk (0xffffU << GPIO_PINWKEN_PINWKSEL_Pos)¯GPIO_PINWKEN_PINWKSEL_FALLING 0°GPIO_PINWKEN_PINWKSEL_RISING 1±GPIO_PINWKEN_PINWKSEL_BOTH 2³GPIO_PINWKEN_PINWKEN_Pos 0´GPIO_PINWKEN_PINWKEN_Msk (0xffU << GPIO_PINWKEN_PINWKEN_Pos)¸GPIOH_DO_PHDO_Pos 0¹GPIOH_DO_PHDO_Msk (0xfU << GPIOH_DO_PHDO_Pos)¼GPIOH_DIN_PHDIN_Pos 0½GPIOH_DIN_PHDIN_Msk (0xfU << GPIOH_DIN_PHDIN_Pos)`U ..\Drivers\..\Core\Include\fm33a0xxev_gpio.hFM33A0XXEV.h$
..\Drivers\fm33a0xxev_gpio.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMGPIO_FCR_INGPIO_FCR_OUTGPIO_FCR_DIGGPIO_FCR_ANAPGPIO_FCR_TypeDef¾ ¼GPIO_OD_DisGPIO_OD_EnPGPIO_ODEN_TypeDef)÷GPIO_PU_DisGPIO_PU_EnPGPIO_PUEN_TypeDefU2²GPIO_IN_DisGPIO_IN_EnPGPIO_INEN_TypeDef;íGPIO_HD_DisGPIO_HD_EnPGPIO_HD_TypeDefËDªGPIO_ANEN_DisGPIO_ANEN_EnPGPIO_ANEN_TypeDefM*Pinf#PxFCR#PxODEN<#PxPUENw#PxINEN²#PGPIO_InitTypeDefCYÁBit_RESETBit_SETPBitAction¤bEXTI_RISINGEXTI_FALLINGEXTI_BOTHEXTIDISABLEPGPIOExtiEdgeÒk__FM33A0XXEV_I2C_H I2C_SEND_STARTBIT(I2Cx) I2Cx_CR_SEN_Setable(I2Cx,ENABLE)I2C_SEND_RESTARTBIT(I2Cx) I2Cx_CR_RSEN_Setable(I2Cx,ENABLE)I2C_SEND_STOPBIT(I2Cx) I2Cx_CR_PEN_Setable(I2Cx,ENABLE)I2C_SEND_ACK_0(I2Cx) I2Cx_SR_ACKMO_Set(I2Cx,I2Cx_SR_ACKMO_RESET)I2C_SEND_ACK_1(I2Cx) I2Cx_SR_ACKMO_Set(I2Cx,I2Cx_SR_ACKMO_SET)!I2Cx_CFGR_AUTOEND_Pos 17$I2Cx_CFGR_AUTOEND_Msk (0x1U << I2Cx_CFGR_AUTOEND_Pos)%I2Cx_CFGR_AUTOEND_AUTO (0x1U << I2Cx_CFGR_AUTOEND_Pos)&I2Cx_CFGR_AUTOEND_MANUAL (0x0U << I2Cx_CFGR_AUTOEND_Pos)(I2Cx_CFGR_MSP_DMAEN_Pos 16+I2Cx_CFGR_MSP_DMAEN_Msk (0x1U << I2Cx_CFGR_MSP_DMAEN_Pos)/I2Cx_CFGR_TOEN_Pos 12I2Cx_CFGR_TOEN_Msk (0x1U << I2Cx_CFGR_TOEN_Pos)3I2Cx_CFGR_TOEN_ENABLE (0x1U << I2Cx_CFGR_TOEN_Pos)4I2Cx_CFGR_TOEN_DISABLE (0x0U << I2Cx_CFGR_TOEN_Pos)6I2Cx_CFGR_MSPEN_Pos 07I2Cx_CFGR_MSPEN_Msk (0x1U << I2Cx_CFGR_MSPEN_Pos)9I2Cx_CR_RCEN_Pos 3<I2Cx_CR_RCEN_Msk (0x1U << I2Cx_CR_RCEN_Pos)>I2Cx_CR_PEN_Pos 2?I2Cx_CR_PEN_Msk (0x1U << I2Cx_CR_PEN_Pos)AI2Cx_CR_RSEN_Pos 1BI2Cx_CR_RSEN_Msk (0x1U << I2Cx_CR_RSEN_Pos)DI2Cx_CR_SEN_Pos 0EI2Cx_CR_SEN_Msk (0x1U << I2Cx_CR_SEN_Pos)GI2Cx_IER_WCOLE_Pos 6JI2Cx_IER_WCOLE_Msk (0x1U << I2Cx_IER_WCOLE_Pos)NI2Cx_IER_TOE_Pos 5QI2Cx_IER_TOE_Msk (0x1U << I2Cx_IER_TOE_Pos)SI2Cx_IER_SE_Pos 4VI2Cx_IER_SE_Msk (0x1U << I2Cx_IER_SE_Pos)ZI2Cx_IER_PE_Pos 3]I2Cx_IER_PE_Msk (0x1U << I2Cx_IER_PE_Pos)aI2Cx_IER_NACKE_Pos 2dI2Cx_IER_NACKE_Msk (0x1U << I2Cx_IER_NACKE_Pos)hI2Cx_IER_TXIE_Pos 1kI2Cx_IER_TXIE_Msk (0x1U << I2Cx_IER_TXIE_Pos)oI2Cx_IER_RXIE_Pos 0rI2Cx_IER_RXIE_Msk (0x1U << I2Cx_IER_RXIE_Pos)vI2Cx_ISR_WCOL_Pos 6zI2Cx_ISR_WCOL_Msk (0x1U << I2Cx_ISR_WCOL_Pos)|I2Cx_ISR_TO_Pos 5}I2Cx_ISR_TO_Msk (0x1U << I2Cx_ISR_TO_Pos)I2Cx_ISR_S_Pos 4I2Cx_ISR_S_Msk (0x1U << I2Cx_ISR_S_Pos)I2Cx_ISR_P_Pos 3I2Cx_ISR_P_Msk (0x1U << I2Cx_ISR_P_Pos)I2Cx_ISR_ACKSTA_Pos 2I2Cx_ISR_ACKSTA_Msk (0x1U << I2Cx_ISR_ACKSTA_Pos)I2Cx_ISR_TXIF_Pos 1I2Cx_ISR_TXIF_Msk (0x1U << I2Cx_ISR_TXIF_Pos)I2Cx_ISR_RXIF_Pos 0I2Cx_ISR_RXIF_Msk (0x1U << I2Cx_ISR_RXIF_Pos)I2Cx_SR_BUSY_Pos 5I2Cx_SR_BUSY_Msk (0x1U << I2Cx_SR_BUSY_Pos)I2Cx_SR_RW_Pos 4I2Cx_SR_RW_Msk (0x1U << I2Cx_SR_RW_Pos)I2Cx_SR_BF_Pos 2¤I2Cx_SR_BF_Msk (0x1U << I2Cx_SR_BF_Pos)¦I2Cx_SR_ACKMO_Pos 0¬I2Cx_SR_ACKMO_Msk (0x1U << I2Cx_SR_ACKMO_Pos)I2Cx_SR_ACKMO_RESET (0x0U << I2Cx_SR_ACKMO_Pos)®I2Cx_SR_ACKMO_SET (0x1U << I2Cx_SR_ACKMO_Pos)°I2Cx_BRG_MSPBRGH_Pos 16±I2Cx_BRG_MSPBRGH_Msk (0x1ffU << I2Cx_BRG_MSPBRGH_Pos)³I2Cx_BRG_MSPBRGL_Pos 0´I2Cx_BRG_MSPBRGL_Msk (0x1ffU << I2Cx_BRG_MSPBRGL_Pos)¶I2Cx_BUF_WR_Pos 0·I2Cx_BUF_WR_Msk (0xffU << I2Cx_BUF_WR_Pos)¹I2Cx_TIMING_SDAHD_Pos 0»I2Cx_TIMING_SDAHD_Msk (0x1ffU << I2Cx_TIMING_SDAHD_Pos)½I2Cx_TO_TIMEOUT_Pos 0¿I2Cx_TO_TIMEOUT_Msk (0xfffU << I2Cx_TO_TIMEOUT_Pos)`T ..\Drivers\..\Core\Include\fm33a0xxev_i2c.hFM33A0XXEV.h¼
..\Drivers\fm33a0xxev_i2c.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM¡¢£__FM33A0XXEV_IWDT_H IWDT_SERV_IWDTSERV_KEY 0x12345A5AUIWDT_SERV_IWDTSERV_Pos 0IWDT_SERV_IWDTSERV_Msk (0xffffffffU << IWDT_SERV_IWDTSERV_Pos)IWDT_CFGR_IWDTOVP_Pos 0"IWDT_CFGR_IWDTOVP_Msk (0x7U << IWDT_CFGR_IWDTOVP_Pos)#IWDT_IWDTOVP_125MS (0x0U << IWDT_CFGR_IWDTOVP_Pos)$IWDT_IWDTOVP_500MS (0x1U << IWDT_CFGR_IWDTOVP_Pos)%IWDT_IWDTOVP_2S (0x2U << IWDT_CFGR_IWDTOVP_Pos)&IWDT_IWDTOVP_8S (0x3U << IWDT_CFGR_IWDTOVP_Pos)(IWDT_IWDTOVP_4096S (0x4U << IWDT_CFGR_IWDTOVP_Pos)*IWDT_CNTR_IWDTCNT_Pos 0+IWDT_CNTR_IWDTCNT_Msk (0xfffffU << IWDT_CNTR_IWDTCNT_Pos)`U ..\Drivers\..\Core\Include\fm33a0xxev_iwdt.hFM33A0XXEV.h¼
..\Drivers\fm33a0xxev_iwdt.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM¥¦§__FM33A0XXEV_LPUART_H LPUARTx_MCTL_FOR9600 (0x00000552<<16)LPUARTx_MCTL_FOR4800 (0x00001EFB<<16)LPUARTx_MCTL_FOR2400 (0x000016DB<<16)LPUARTx_MCTL_FOR1200 (0x00000492<<16)LPUARTx_MCTL_FOR600 (0x000016D6<<16)LPUARTx_MCTL_FOR300 (0x00000842<<16) LPUARTx_CSR_BUSY_Pos 24#LPUARTx_CSR_BUSY_Msk (0x1U << LPUARTx_CSR_BUSY_Pos)%LPUARTx_CSR_WKBYTECFG_Pos 19(LPUARTx_CSR_WKBYTECFG_Msk (0x1U << LPUARTx_CSR_WKBYTECFG_Pos)*LPUARTx_CSR_RXEV_Pos 160LPUARTx_CSR_RXEV_Msk (0x3U << LPUARTx_CSR_RXEV_Pos)1LPUARTx_CSR_RXEV_START (0x0U << LPUARTx_CSR_RXEV_Pos)2LPUARTx_CSR_RXEV_1BYTE (0x1U << LPUARTx_CSR_RXEV_Pos)3LPUARTx_CSR_RXEV_MATCH (0x2U << LPUARTx_CSR_RXEV_Pos)4LPUARTx_CSR_RXEV_FALLING (0x3U << LPUARTx_CSR_RXEV_Pos)6LPUARTx_CSR_IOSWAP_Pos 119LPUARTx_CSR_IOSWAP_Msk (0x1U << LPUARTx_CSR_IOSWAP_Pos):LPUARTx_CSR_IOSWAP_DEFUALT (0x0U << LPUARTx_CSR_IOSWAP_Pos);LPUARTx_CSR_IOSWAP_SWAP (0x1U << LPUARTx_CSR_IOSWAP_Pos)>LPUARTx_CSR_DMATXIFCFG_Pos 10ALPUARTx_CSR_DMATXIFCFG_Msk (0x1U << LPUARTx_CSR_DMATXIFCFG_Pos)ELPUARTx_CSR_BITORD_Pos 9HLPUARTx_CSR_BITORD_Msk (0x1U << LPUARTx_CSR_BITORD_Pos)ILPUARTx_CSR_BITORD_LSB (0x0U << LPUARTx_CSR_BITORD_Pos)JLPUARTx_CSR_BITORD_MSB (0x1U << LPUARTx_CSR_BITORD_Pos)LLPUARTx_CSR_STOPCFG_Pos 8OLPUARTx_CSR_STOPCFG_Msk (0x1U << LPUARTx_CSR_STOPCFG_Pos)PLPUARTx_CSR_STOPCFG_1STOP (0x0U << LPUARTx_CSR_STOPCFG_Pos)QLPUARTx_CSR_STOPCFG_2STOP (0x1U << LPUARTx_CSR_STOPCFG_Pos)SLPUARTx_CSR_PDSEL_Pos 6YLPUARTx_CSR_PDSEL_Msk (0x3U << LPUARTx_CSR_PDSEL_Pos)ZLPUARTx_CSR_PDSEL_7BITS (0x0U << LPUARTx_CSR_PDSEL_Pos)[LPUARTx_CSR_PDSEL_8BITS (0x1U << LPUARTx_CSR_PDSEL_Pos)\LPUARTx_CSR_PDSEL_9BITS (0x2U << LPUARTx_CSR_PDSEL_Pos)]LPUARTx_CSR_PDSEL_6BITS (0x3U << LPUARTx_CSR_PDSEL_Pos)_LPUARTx_CSR_PARITY_Pos 4dLPUARTx_CSR_PARITY_Msk (0x3U << LPUARTx_CSR_PARITY_Pos)eLPUARTx_CSR_PARITY_NON (0x0U << LPUARTx_CSR_PARITY_Pos)fLPUARTx_CSR_PARITY_EVEN (0x1U << LPUARTx_CSR_PARITY_Pos)gLPUARTx_CSR_PARITY_ODD (0x2U << LPUARTx_CSR_PARITY_Pos)iLPUARTx_CSR_RXPOL_Pos 3lLPUARTx_CSR_RXPOL_Msk (0x1U << LPUARTx_CSR_RXPOL_Pos)mLPUARTx_CSR_RXPOL_POS (0x0U << LPUARTx_CSR_RXPOL_Pos)nLPUARTx_CSR_RXPOL_NEG (0x1U << LPUARTx_CSR_RXPOL_Pos)pLPUARTx_CSR_TXPOL_Pos 2sLPUARTx_CSR_TXPOL_Msk (0x1U << LPUARTx_CSR_TXPOL_Pos)tLPUARTx_CSR_TXPOL_POS (0x0U << LPUARTx_CSR_TXPOL_Pos)uLPUARTx_CSR_TXPOL_NEG (0x1U << LPUARTx_CSR_TXPOL_Pos)wLPUARTx_CSR_RXEN_Pos 1xLPUARTx_CSR_RXEN_Msk (0x1U << LPUARTx_CSR_RXEN_Pos)zLPUARTx_CSR_TXEN_Pos 0{LPUARTx_CSR_TXEN_Msk (0x1U << LPUARTx_CSR_TXEN_Pos)}LPUARTx_IER_RXEV_IE_Pos 12~LPUARTx_IER_RXEV_IE_Msk (0x1U << LPUARTx_IER_RXEV_IE_Pos)LPUARTx_IER_RXERR_IE_Pos 10LPUARTx_IER_RXERR_IE_Msk (0x1U << LPUARTx_IER_RXERR_IE_Pos)LPUARTx_IER_RXBF_IE_Pos 8LPUARTx_IER_RXBF_IE_Msk (0x1U << LPUARTx_IER_RXBF_IE_Pos)LPUARTx_IER_TXBE_IE_Pos 1LPUARTx_IER_TXBE_IE_Msk (0x1U << LPUARTx_IER_TXBE_IE_Pos)LPUARTx_IER_TXSE_IE_Pos 0LPUARTx_IER_TXSE_IE_Msk (0x1U << LPUARTx_IER_TXSE_IE_Pos)LPUARTx_ISR_RXEVF_Pos 24LPUARTx_ISR_RXEVF_Msk (0x1U << LPUARTx_ISR_RXEVF_Pos)LPUARTx_ISR_TXOV_Pos 19LPUARTx_ISR_TXOV_Msk (0x1U << LPUARTx_ISR_TXOV_Pos)LPUARTx_ISR_PERR_Pos 18LPUARTx_ISR_PERR_Msk (0x1U << LPUARTx_ISR_PERR_Pos)LPUARTx_ISR_FERR_Pos 17LPUARTx_ISR_FERR_Msk (0x1U << LPUARTx_ISR_FERR_Pos)LPUARTx_ISR_OERR_Pos 16LPUARTx_ISR_OERR_Msk (0x1U << LPUARTx_ISR_OERR_Pos)LPUARTx_ISR_RXBF_Pos 8LPUARTx_ISR_RXBF_Msk (0x1U << LPUARTx_ISR_RXBF_Pos) LPUARTx_ISR_TXBE_Pos 1¡LPUARTx_ISR_TXBE_Msk (0x1U << LPUARTx_ISR_TXBE_Pos)£LPUARTx_ISR_TXSE_Pos 0¤LPUARTx_ISR_TXSE_Msk (0x1U << LPUARTx_ISR_TXSE_Pos)¦LPUARTx_BMR_MCTL_Pos 16§LPUARTx_BMR_MCTL_Msk (0x1fffU << LPUARTx_BMR_MCTL_Pos)©LPUARTx_BMR_BAUD_Pos 0°LPUARTx_BMR_BAUD_Msk (0x7U << LPUARTx_BMR_BAUD_Pos)±LPUARTx_BMR_BAUD_9600 (0x0U << LPUARTx_BMR_BAUD_Pos)²LPUARTx_BMR_BAUD_4800 (0x1U << LPUARTx_BMR_BAUD_Pos)³LPUARTx_BMR_BAUD_2400 (0x2U << LPUARTx_BMR_BAUD_Pos)´LPUARTx_BMR_BAUD_1200 (0x3U << LPUARTx_BMR_BAUD_Pos)µLPUARTx_BMR_BAUD_600 (0x4U << LPUARTx_BMR_BAUD_Pos)¶LPUARTx_BMR_BAUD_300 (0x5U << LPUARTx_BMR_BAUD_Pos)¸LPUARTx_RXBUF_RXBUF_Pos 0¹LPUARTx_RXBUF_RXBUF_Msk (0x1ffU << LPUARTx_RXBUF_RXBUF_Pos)»LPUARTx_TXBUF_TXBUF_Pos 0¼LPUARTx_TXBUF_TXBUF_Msk (0x1ffU << LPUARTx_TXBUF_TXBUF_Pos)¾LPUARTx_DMR_MATD_Pos 0ÀLPUARTx_DMR_MATD_Msk (0x1ffU << LPUARTx_DMR_MATD_Pos)`W ..\Drivers\..\Core\Include\fm33a0xxev_lpuart.hFM33A0XXEV.hÀ
..\Drivers\fm33a0xxev_lpuart.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM©ª«__FM33A0XXEV_FLASH_H FLS_RDCR_WAIT_Pos 0FLS_RDCR_WAIT_Msk (0x3U << FLS_RDCR_WAIT_Pos)FLS_RDCR_WAIT_0CYCLE (0x0U << FLS_RDCR_WAIT_Pos) FLS_RDCR_WAIT_1CYCLE (0x1U << FLS_RDCR_WAIT_Pos)!FLS_RDCR_WAIT_2CYCLE (0x2U << FLS_RDCR_WAIT_Pos)#FLS_PFCR_PRFTEN_Pos 0&FLS_PFCR_PRFTEN_Msk (0x1U << FLS_PFCR_PRFTEN_Pos)*FLS_OPTBR_DBGCFGEN_Pos 31+FLS_OPTBR_DBGCFGEN_Msk (0x1U << FLS_OPTBR_DBGCFGEN_Pos)-FLS_OPTBR_IF2LOCK_Pos 180FLS_OPTBR_IF2LOCK_Msk (0x1U << FLS_OPTBR_IF2LOCK_Pos)2FLS_OPTBR_IF1LOCK_Pos 175FLS_OPTBR_IF1LOCK_Msk (0x1U << FLS_OPTBR_IF1LOCK_Pos)7FLS_OPTBR_DFLSEN_Pos 10:FLS_OPTBR_DFLSEN_Msk (0x1U << FLS_OPTBR_DFLSEN_Pos)>FLS_OPTBR_BTSEN_Pos 8AFLS_OPTBR_BTSEN_Msk (0x3U << FLS_OPTBR_BTSEN_Pos)GFLS_OPTBR_ACLOCKEN_Pos 4JFLS_OPTBR_ACLOCKEN_Msk (0x3U << FLS_OPTBR_ACLOCKEN_Pos)PFLS_OPTBR_DBRDPEN_Pos 0SFLS_OPTBR_DBRDPEN_Msk (0xfU << FLS_OPTBR_DBRDPEN_Pos)YFLS_OPTBR_LOCK1_Pos 0ZFLS_OPTBR_LOCK1_Msk (0xffffffffU << FLS_OPTBR_LOCK1_Pos)\FLS_OPTBR_LOCK2_Pos 0]FLS_OPTBR_LOCK2_Msk (0xffffffffU << FLS_OPTBR_LOCK2_Pos)_FLS_OPTBR_LOCK3_Pos 0`FLS_OPTBR_LOCK3_Msk (0xffffffffU << FLS_OPTBR_LOCK3_Pos)bFLS_OPTBR_LOCK4_Pos 0cFLS_OPTBR_LOCK4_Msk (0xffffffffU << FLS_OPTBR_LOCK4_Pos)eFLS_EPCR_ERTYPE_Pos 8iFLS_EPCR_ERTYPE_Msk (0x3U << FLS_EPCR_ERTYPE_Pos)jFLS_EPCR_ERTYPE_PAGE (0x0U << FLS_EPCR_ERTYPE_Pos)kFLS_EPCR_ERTYPE_SECTOR (0x1U << FLS_EPCR_ERTYPE_Pos)lFLS_EPCR_ERTYPE_CHIP_ERASE (0x2U << FLS_EPCR_ERTYPE_Pos)nFLS_EPCR_PREQ_Pos 1pFLS_EPCR_PREQ_Msk (0x1U << FLS_EPCR_PREQ_Pos)rFLS_EPCR_EREQ_Pos 0tFLS_EPCR_EREQ_Msk (0x1U << FLS_EPCR_EREQ_Pos)vFLS_KEY_KEY_Pos 0wFLS_KEY_KEY_Msk (0xffffffffU << FLS_KEY_KEY_Pos)yFLS_IER_OTPIE_Pos 11zFLS_IER_OTPIE_Msk (0x1U << FLS_IER_OTPIE_Pos)|FLS_IER_AUTHIE_Pos 10}FLS_IER_AUTHIE_Msk (0x1U << FLS_IER_AUTHIE_Pos)FLS_IER_KEYIE_Pos 9FLS_IER_KEYIE_Msk (0x1U << FLS_IER_KEYIE_Pos)FLS_IER_CKIE_Pos 8FLS_IER_CKIE_Msk (0x1U << FLS_IER_CKIE_Pos)FLS_IER_PRDIE_Pos 1FLS_IER_PRDIE_Msk (0x1U << FLS_IER_PRDIE_Pos)FLS_IER_ERDIE_Pos 0FLS_IER_ERDIE_Msk (0x1U << FLS_IER_ERDIE_Pos)FLS_ISR_KEYSTA_Pos 17FLS_ISR_KEYSTA_Msk (0x7U << FLS_ISR_KEYSTA_Pos)FLS_ISR_KEYSTA_KEY_NONE_PROTECT (0x0U << FLS_ISR_KEYSTA_Pos)FLS_ISR_KEYSTA_CHIP_ERASE (0x1U << FLS_ISR_KEYSTA_Pos)FLS_ISR_KEYSTA_SECTOR_ERASE (0x2U << FLS_ISR_KEYSTA_Pos)FLS_ISR_KEYSTA_PROGRAM (0x3U << FLS_ISR_KEYSTA_Pos)FLS_ISR_KEYSTA_KEY_ERR_PROTECT (0x4U << FLS_ISR_KEYSTA_Pos)FLS_ISR_BTSF_Pos 16FLS_ISR_BTSF_Msk (0x1U << FLS_ISR_BTSF_Pos)FLS_ISR_BTSF_START_0000H (0x0U << FLS_ISR_BTSF_Pos)FLS_ISR_BTSF_START_2000H (0x1U << FLS_ISR_BTSF_Pos) FLS_ISR_OTPERR_Pos 11£FLS_ISR_OTPERR_Msk (0x1U << FLS_ISR_OTPERR_Pos)¥FLS_ISR_AUTHERR_Pos 10¨FLS_ISR_AUTHERR_Msk (0x1U << FLS_ISR_AUTHERR_Pos)ªFLS_ISR_KEYERR_Pos 9«FLS_ISR_KEYERR_Msk (0x1U << FLS_ISR_KEYERR_Pos)FLS_ISR_CKERR_Pos 8®FLS_ISR_CKERR_Msk (0x1U << FLS_ISR_CKERR_Pos)°FLS_ISR_PRD_Pos 1±FLS_ISR_PRD_Msk (0x1U << FLS_ISR_PRD_Pos)³FLS_ISR_ERD_Pos 0´FLS_ISR_ERD_Msk (0x1U << FLS_ISR_ERD_Pos)`V ..\Drivers\..\Core\Include\fm33a0xxev_flash.hFM33A0XXEV.hÀ
..\Drivers\fm33a0xxev_flash.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM®¯__FM33A0XXEV_PMU_H  PMU_CR_LDO15EN_Pos 17#PMU_CR_LDO15EN_Msk (0x1U << PMU_CR_LDO15EN_Pos)%PMU_CR_LDO15EN_B_Pos 16&PMU_CR_LDO15EN_B_Msk (0x1U << PMU_CR_LDO15EN_B_Pos)(PMU_CR_WKFSEL_Pos 10-PMU_CR_WKFSEL_Msk (0x3U << PMU_CR_WKFSEL_Pos).PMU_CR_WKFSEL_RCHF_8M (0x0U << PMU_CR_WKFSEL_Pos)/PMU_CR_WKFSEL_RCHF_16M (0x1U << PMU_CR_WKFSEL_Pos)0PMU_CR_WKFSEL_RCHF_24M (0x2U << PMU_CR_WKFSEL_Pos)1PMU_CR_WKFSEL_RCHF_32M (0x3U << PMU_CR_WKFSEL_Pos)3PMU_CR_SLPDP_Pos 98PMU_CR_SLPDP_Msk (0x1U << PMU_CR_SLPDP_Pos)9PMU_CR_SLPDP_DEEPSLEEP (0x1U << PMU_CR_SLPDP_Pos):PMU_CR_SLPDP_SLEEP (0x0U << PMU_CR_SLPDP_Pos)<PMU_CR_CVS_Pos 8@PMU_CR_CVS_Msk (0x1U << PMU_CR_CVS_Pos)APMU_CR_CVS_DISABLE (0x0U << PMU_CR_CVS_Pos)BPMU_CR_CVS_ENABLE (0x1U << PMU_CR_CVS_Pos)DPMU_CR_PMOD_Pos 0IPMU_CR_PMOD_Msk (0x3U << PMU_CR_PMOD_Pos)JPMU_CR_PMOD_ACTIVE (0x0U << PMU_CR_PMOD_Pos)KPMU_CR_PMOD_LPRUN (0x1U << PMU_CR_PMOD_Pos)LPMU_CR_PMOD_SLEEP (0x2U << PMU_CR_PMOD_Pos)NPMU_WKTR_STPCLR_Pos 2QPMU_WKTR_STPCLR_Msk (0x1U << PMU_WKTR_STPCLR_Pos)RPMU_WKTR_STPCLR_SYN (0x0U << PMU_WKTR_STPCLR_Pos)SPMU_WKTR_STPCLR_ASY (0x1U << PMU_WKTR_STPCLR_Pos)UPMU_WKTR_T1A_Pos 0[PMU_WKTR_T1A_Msk (0x3U << PMU_WKTR_T1A_Pos)\PMU_WKTR_T1A_0US (0x0U << PMU_WKTR_T1A_Pos)]PMU_WKTR_T1A_2US (0x1U << PMU_WKTR_T1A_Pos)^PMU_WKTR_T1A_4US (0x2U << PMU_WKTR_T1A_Pos)_PMU_WKTR_T1A_8US (0x3U << PMU_WKTR_T1A_Pos)aPMU_WKFR_ADCWKF_Pos 31bPMU_WKFR_ADCWKF_Msk (0x1U << PMU_WKFR_ADCWKF_Pos)dPMU_WKFR_RTCWKF_Pos 28ePMU_WKFR_RTCWKF_Msk (0x1U << PMU_WKFR_RTCWKF_Pos)gPMU_WKFR_SVDWKF_Pos 27hPMU_WKFR_SVDWKF_Msk (0x1U << PMU_WKFR_SVDWKF_Pos)jPMU_WKFR_LFDETWKF_Pos 26kPMU_WKFR_LFDETWKF_Msk (0x1U << PMU_WKFR_LFDETWKF_Pos)mPMU_WKFR_IOWKF_Pos 24nPMU_WKFR_IOWKF_Msk (0x1U << PMU_WKFR_IOWKF_Pos)pPMU_WKFR_LPU1WKF_Pos 21qPMU_WKFR_LPU1WKF_Msk (0x1U << PMU_WKFR_LPU1WKF_Pos)sPMU_WKFR_LPU0WKF_Pos 20tPMU_WKFR_LPU0WKF_Msk (0x1U << PMU_WKFR_LPU0WKF_Pos)vPMU_WKFR_COMP_OOWF_Pos 19wPMU_WKFR_COMP_OOWF_Msk (0x1U << PMU_WKFR_COMP_OOWF_Pos)yPMU_WKFR_COMP_WINF_Pos 18zPMU_WKFR_COMP_WINF_Msk (0x1U << PMU_WKFR_COMP_WINF_Pos)|PMU_WKFR_COMP2WKF_Pos 17}PMU_WKFR_COMP2WKF_Msk (0x1U << PMU_WKFR_COMP2WKF_Pos)PMU_WKFR_COMP1WKF_Pos 16PMU_WKFR_COMP1WKF_Msk (0x1U << PMU_WKFR_COMP1WKF_Pos)PMU_WKFR_LPTWKF_Pos 10PMU_WKFR_LPTWKF_Msk (0x1U << PMU_WKFR_LPTWKF_Pos)PMU_WKFR_BSTWKF_Pos 9PMU_WKFR_BSTWKF_Msk (0x1U << PMU_WKFR_BSTWKF_Pos)PMU_WKFR_DBGWKF_Pos 8PMU_WKFR_DBGWKF_Msk (0x1U << PMU_WKFR_DBGWKF_Pos)PMU_IER_SLPEIE_Pos 1PMU_IER_SLPEIE_Msk (0x1U << PMU_IER_SLPEIE_Pos)PMU_IER_RTCEIE_Pos 0PMU_IER_RTCEIE_Msk (0x1U << PMU_IER_RTCEIE_Pos)PMU_ISR_SLPEIF_Pos 1PMU_ISR_SLPEIF_Msk (0x1U << PMU_ISR_SLPEIF_Pos)PMU_ISR_RTCEIF_Pos 0¢PMU_ISR_RTCEIF_Msk (0x1U << PMU_ISR_RTCEIF_Pos)`T ..\Drivers\..\Core\Include\fm33a0xxev_pmu.hFM33A0XXEV.h$
..\Drivers\fm33a0xxev_pmu.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM*PMODf#SLPDPf#CVS#SCRf#TIAf#PPMU_SleepCfg_InitTypeDef½±²³__FM33A0XXEV_CMU_H HXVAR(object,addr) (*((object *) (addr)))const_rchf_Trim8 HXVAR( uint32_t, 0x1FFFFB40 )const_rchf_Trim16 HXVAR( uint32_t, 0x1FFFFB3C )const_rchf_Trim24 HXVAR( uint32_t, 0x1FFFFB38 )const_rchf_Trim32 HXVAR( uint32_t, 0x1FFFFB34)!__XTHF_CLOCK (12000000)RCMU_SYSCLKCR_SLP_ENEXTI_Pos 25SCMU_SYSCLKCR_SLP_ENEXTI_Msk (0x1U << CMU_SYSCLKCR_SLP_ENEXTI_Pos)UCMU_SYSCLKCR_APBPRES_Pos 16[CMU_SYSCLKCR_APBPRES_Msk (0x7U << CMU_SYSCLKCR_APBPRES_Pos)\CMU_SYSCLKCR_APBPRES_DIV1 (0x0U << CMU_SYSCLKCR_APBPRES_Pos)]CMU_SYSCLKCR_APBPRES_DIV2 (0x4U << CMU_SYSCLKCR_APBPRES_Pos)^CMU_SYSCLKCR_APBPRES_DIV4 (0x5U << CMU_SYSCLKCR_APBPRES_Pos)_CMU_SYSCLKCR_APBPRES_DIV8 (0x6U << CMU_SYSCLKCR_APBPRES_Pos)`CMU_SYSCLKCR_APBPRES_DIV16 (0x7U << CMU_SYSCLKCR_APBPRES_Pos)bCMU_SYSCLKCR_AHBPRES_Pos 8hCMU_SYSCLKCR_AHBPRES_Msk (0x7U << CMU_SYSCLKCR_AHBPRES_Pos)iCMU_SYSCLKCR_AHBPRES_DIV1 (0x0U << CMU_SYSCLKCR_AHBPRES_Pos)jCMU_SYSCLKCR_AHBPRES_DIV2 (0x4U << CMU_SYSCLKCR_AHBPRES_Pos)kCMU_SYSCLKCR_AHBPRES_DIV4 (0x5U << CMU_SYSCLKCR_AHBPRES_Pos)lCMU_SYSCLKCR_AHBPRES_DIV8 (0x6U << CMU_SYSCLKCR_AHBPRES_Pos)mCMU_SYSCLKCR_AHBPRES_DIV16 (0x7U << CMU_SYSCLKCR_AHBPRES_Pos)oCMU_SYSCLKCR_STCLKSEL_Pos 6tCMU_SYSCLKCR_STCLKSEL_Msk (0x3U << CMU_SYSCLKCR_STCLKSEL_Pos)uCMU_SYSCLKCR_STCLKSEL_SCLK (0x0U << CMU_SYSCLKCR_STCLKSEL_Pos)vCMU_SYSCLKCR_STCLKSEL_LSCLK (0x1U << CMU_SYSCLKCR_STCLKSEL_Pos)wCMU_SYSCLKCR_STCLKSEL_RC4M (0x2U << CMU_SYSCLKCR_STCLKSEL_Pos)xCMU_SYSCLKCR_STCLKSEL_SYSCLK (0x3U << CMU_SYSCLKCR_STCLKSEL_Pos)zCMU_SYSCLKCR_SYSCLKSEL_Pos 0{CMU_SYSCLKCR_SYSCLKSEL_Msk (0x7U << CMU_SYSCLKCR_SYSCLKSEL_Pos)|CMU_SYSCLKCR_SYSCLKSEL_RCHF (0x0U << CMU_SYSCLKCR_SYSCLKSEL_Pos)}CMU_SYSCLKCR_SYSCLKSEL_XTHF (0x1U << CMU_SYSCLKCR_SYSCLKSEL_Pos)~CMU_SYSCLKCR_SYSCLKSEL_PLL_H (0x2U << CMU_SYSCLKCR_SYSCLKSEL_Pos)CMU_SYSCLKCR_SYSCLKSEL_LSCLK (0x3U << CMU_SYSCLKCR_SYSCLKSEL_Pos)CMU_RCHFCR_FSEL_Pos 16CMU_RCHFCR_FSEL_Msk (0xfU << CMU_RCHFCR_FSEL_Pos)CMU_RCHFCR_FSEL_8MHZ (0x0U << CMU_RCHFCR_FSEL_Pos)CMU_RCHFCR_FSEL_16MHZ (0x1U << CMU_RCHFCR_FSEL_Pos)CMU_RCHFCR_FSEL_24MHZ (0x2U << CMU_RCHFCR_FSEL_Pos)CMU_RCHFCR_FSEL_32MHZ (0x3U << CMU_RCHFCR_FSEL_Pos)CMU_RCHFCR_RCHFEN_Pos 0CMU_RCHFCR_RCHFEN_Msk (0x1U << CMU_RCHFCR_RCHFEN_Pos)CMU_RCHFTR_RCHFTRIM_Pos 0CMU_RCHFTR_RCHFTRIM_Msk (0xffU << CMU_RCHFTR_RCHFTRIM_Pos)CMU_PLLLCR_PLLDB_Pos 16CMU_PLLLCR_PLLDB_Msk (0x3ffU << CMU_PLLLCR_PLLDB_Pos)CMU_PLLLCR_LOCKED_Pos 7CMU_PLLLCR_LOCKED_Msk (0x1U << CMU_PLLLCR_LOCKED_Pos) CMU_PLLLCR_PLLEN_Pos 0£CMU_PLLLCR_PLLEN_Msk (0x1U << CMU_PLLLCR_PLLEN_Pos)¥CMU_PLLHCR_PLLHDB_Pos 16¨CMU_PLLHCR_PLLHDB_Msk (0x3ffU << CMU_PLLHCR_PLLHDB_Pos)©CMU_PLLHCR_PLLHDB_X32 (0x1fU << CMU_PLLHCR_PLLHDB_Pos)ªCMU_PLLHCR_PLLHDB_X48 (0x2fU << CMU_PLLHCR_PLLHDB_Pos)«CMU_PLLHCR_PLLHDB_X64 (0x3fU << CMU_PLLHCR_PLLHDB_Pos)CMU_PLLHCR_LOCKED_Pos 7°CMU_PLLHCR_LOCKED_Msk (0x1U << CMU_PLLHCR_LOCKED_Pos)²CMU_PLLHCR_REFPRSC_Pos 4»CMU_PLLHCR_REFPRSC_Msk (0x7U << CMU_PLLHCR_REFPRSC_Pos)¼CMU_PLLHCR_REFPRSC_DIV1 (0x0U << CMU_PLLHCR_REFPRSC_Pos)½CMU_PLLHCR_REFPRSC_DIV2 (0x1U << CMU_PLLHCR_REFPRSC_Pos)¾CMU_PLLHCR_REFPRSC_DIV4 (0x2U << CMU_PLLHCR_REFPRSC_Pos)¿CMU_PLLHCR_REFPRSC_DIV8 (0x3U << CMU_PLLHCR_REFPRSC_Pos)ÀCMU_PLLHCR_REFPRSC_DIV12 (0x4U << CMU_PLLHCR_REFPRSC_Pos)ÁCMU_PLLHCR_REFPRSC_DIV16 (0x5U << CMU_PLLHCR_REFPRSC_Pos)ÂCMU_PLLHCR_REFPRSC_DIV24 (0x6U << CMU_PLLHCR_REFPRSC_Pos)ÃCMU_PLLHCR_REFPRSC_DIV32 (0x7U << CMU_PLLHCR_REFPRSC_Pos)ÅCMU_PLLHCR_OSEL_Pos 3ÈCMU_PLLHCR_OSEL_Msk (0x1U << CMU_PLLHCR_OSEL_Pos)ÉCMU_PLLHCR_OSEL_X1 (0x0U << CMU_PLLHCR_OSEL_Pos)ÊCMU_PLLHCR_OSEL_X2 (0x1U << CMU_PLLHCR_OSEL_Pos)ÌCMU_PLLHCR_INSEL_Pos 1ÏCMU_PLLHCR_INSEL_Msk (0x1U << CMU_PLLHCR_INSEL_Pos)ÐCMU_PLLHCR_INSEL_RCHF (0x0U << CMU_PLLHCR_INSEL_Pos)ÑCMU_PLLHCR_INSEL_XTHF (0x1U << CMU_PLLHCR_INSEL_Pos)ÓCMU_PLLHCR_EN_Pos 0ÖCMU_PLLHCR_EN_Msk (0x1U << CMU_PLLHCR_EN_Pos)ØCMU_XTHFCR_XTHF_CFG_Pos 8ÛCMU_XTHFCR_XTHF_CFG_Msk (0x7U << CMU_XTHFCR_XTHF_CFG_Pos)ÜCMU_XTHFCR_XTHF_CFG_MIN (0x0U << CMU_XTHFCR_XTHF_CFG_Pos)ÝCMU_XTHFCR_XTHF_CFG_MAX (0x7U << CMU_XTHFCR_XTHF_CFG_Pos)ßCMU_XTHFCR_XTHFEN_Pos 0âCMU_XTHFCR_XTHFEN_Msk (0x1U << CMU_XTHFCR_XTHFEN_Pos)æCMU_IER_SYSCSE_IE_Pos 1çCMU_IER_SYSCSE_IE_Msk (0x1U << CMU_IER_SYSCSE_IE_Pos)éCMU_IER_HFDET_IE_Pos 0êCMU_IER_HFDET_IE_Msk (0x1U << CMU_IER_HFDET_IE_Pos)íCMU_ISR_HFDETO_Pos 8ðCMU_ISR_HFDETO_Msk (0x1U << CMU_ISR_HFDETO_Pos)òCMU_ISR_SYSCSE_IF_Pos 1óCMU_ISR_SYSCSE_IF_Msk (0x1U << CMU_ISR_SYSCSE_IF_Pos)õCMU_ISR_HFDET_IF_Pos 0öCMU_ISR_HFDET_IF_Msk (0x1U << CMU_ISR_HFDET_IF_Pos)øCMU_PCLKCR1_COMP_PCE_Pos 9ùCMU_PCLKCR1_COMP_PCE_Msk (0x1U << CMU_PCLKCR1_COMP_PCE_Pos)ûCMU_PCLKCR1_SVD_PCE_Pos 8üCMU_PCLKCR1_SVD_PCE_Msk (0x1U << CMU_PCLKCR1_SVD_PCE_Pos)þCMU_PCLKCR1_PAD_PCE_Pos 7ÿCMU_PCLKCR1_PAD_PCE_Msk (0x1U << CMU_PCLKCR1_PAD_PCE_Pos)CMU_PCLKCR1_ANAC_PCE_Pos 6CMU_PCLKCR1_ANAC_PCE_Msk (0x1U << CMU_PCLKCR1_ANAC_PCE_Pos)CMU_PCLKCR1_IWDT_PCE_Pos 5CMU_PCLKCR1_IWDT_PCE_Msk (0x1U << CMU_PCLKCR1_IWDT_PCE_Pos)CMU_PCLKCR1_SCU_PCE_Pos 4CMU_PCLKCR1_SCU_PCE_Msk (0x1U << CMU_PCLKCR1_SCU_PCE_Pos)CMU_PCLKCR1_PMU_PCE_Pos 3CMU_PCLKCR1_PMU_PCE_Msk (0x1U << CMU_PCLKCR1_PMU_PCE_Pos)CMU_PCLKCR1_RTC_PCE_Pos 2CMU_PCLKCR1_RTC_PCE_Msk (0x1U << CMU_PCLKCR1_RTC_PCE_Pos)CMU_PCLKCR1_LPT_PCE_Pos 0CMU_PCLKCR1_LPT_PCE_Msk (0x1U << CMU_PCLKCR1_LPT_PCE_Pos)CMU_PCLKCR2_PAE_PCE_Pos 17CMU_PCLKCR2_PAE_PCE_Msk (0x1U << CMU_PCLKCR2_PAE_PCE_Pos)CMU_PCLKCR2_SHA_PCE_Pos 16CMU_PCLKCR2_SHA_PCE_Msk (0x1U << CMU_PCLKCR2_SHA_PCE_Pos)CMU_PCLKCR2_CIC_PCE_Pos 8CMU_PCLKCR2_CIC_PCE_Msk (0x1U << CMU_PCLKCR2_CIC_PCE_Pos)CMU_PCLKCR2_WWDT_PCE_Pos 7CMU_PCLKCR2_WWDT_PCE_Msk (0x1U << CMU_PCLKCR2_WWDT_PCE_Pos) CMU_PCLKCR2_RAMBIST_PCE_Pos 6¡CMU_PCLKCR2_RAMBIST_PCE_Msk (0x1U << CMU_PCLKCR2_RAMBIST_PCE_Pos)£CMU_PCLKCR2_NVM_PCE_Pos 5¤CMU_PCLKCR2_NVM_PCE_Msk (0x1U << CMU_PCLKCR2_NVM_PCE_Pos)¦CMU_PCLKCR2_DMA_PCE_Pos 4§CMU_PCLKCR2_DMA_PCE_Msk (0x1U << CMU_PCLKCR2_DMA_PCE_Pos)©CMU_PCLKCR2_LCD_PCE_Pos 3ªCMU_PCLKCR2_LCD_PCE_Msk (0x1U << CMU_PCLKCR2_LCD_PCE_Pos)¬CMU_PCLKCR2_AES_PCE_Pos 2CMU_PCLKCR2_AES_PCE_Msk (0x1U << CMU_PCLKCR2_AES_PCE_Pos)¯CMU_PCLKCR2_TRNG_PCE_Pos 1°CMU_PCLKCR2_TRNG_PCE_Msk (0x1U << CMU_PCLKCR2_TRNG_PCE_Pos)²CMU_PCLKCR2_CRC_PCE_Pos 0³CMU_PCLKCR2_CRC_PCE_Msk (0x1U << CMU_PCLKCR2_CRC_PCE_Pos)µCMU_PCLKCR3_I2C1_PCE_Pos 25¶CMU_PCLKCR3_I2C1_PCE_Msk (0x1U << CMU_PCLKCR3_I2C1_PCE_Pos)¸CMU_PCLKCR3_I2C0_PCE_Pos 24¹CMU_PCLKCR3_I2C0_PCE_Msk (0x1U << CMU_PCLKCR3_I2C0_PCE_Pos)»CMU_PCLKCR3_LPUART1_PCE_Pos 18¼CMU_PCLKCR3_LPUART1_PCE_Msk (0x1U << CMU_PCLKCR3_LPUART1_PCE_Pos)¾CMU_PCLKCR3_U7816_PCE_Pos 16¿CMU_PCLKCR3_U7816_PCE_Msk (0x1U << CMU_PCLKCR3_U7816_PCE_Pos)ÁCMU_PCLKCR3_LPUART0_PCE_Pos 15ÂCMU_PCLKCR3_LPUART0_PCE_Msk (0x1U << CMU_PCLKCR3_LPUART0_PCE_Pos)ÄCMU_PCLKCR3_UICR_PCE_Pos 14ÅCMU_PCLKCR3_UICR_PCE_Msk (0x1U << CMU_PCLKCR3_UICR_PCE_Pos)ÇCMU_PCLKCR3_UART5_PCE_Pos 13ÈCMU_PCLKCR3_UART5_PCE_Msk (0x1U << CMU_PCLKCR3_UART5_PCE_Pos)ÊCMU_PCLKCR3_UART4_PCE_Pos 12ËCMU_PCLKCR3_UART4_PCE_Msk (0x1U << CMU_PCLKCR3_UART4_PCE_Pos)ÍCMU_PCLKCR3_UART3_PCE_Pos 11ÎCMU_PCLKCR3_UART3_PCE_Msk (0x1U << CMU_PCLKCR3_UART3_PCE_Pos)ÐCMU_PCLKCR3_UART2_PCE_Pos 10ÑCMU_PCLKCR3_UART2_PCE_Msk (0x1U << CMU_PCLKCR3_UART2_PCE_Pos)ÓCMU_PCLKCR3_UART1_PCE_Pos 9ÔCMU_PCLKCR3_UART1_PCE_Msk (0x1U << CMU_PCLKCR3_UART1_PCE_Pos)ÖCMU_PCLKCR3_UART0_PCE_Pos 8×CMU_PCLKCR3_UART0_PCE_Msk (0x1U << CMU_PCLKCR3_UART0_PCE_Pos)ÙCMU_PCLKCR3_QSPI_PCE_Pos 7ÚCMU_PCLKCR3_QSPI_PCE_Msk (0x1U << CMU_PCLKCR3_QSPI_PCE_Pos)ÜCMU_PCLKCR3_SPI4_PCE_Pos 4ÝCMU_PCLKCR3_SPI4_PCE_Msk (0x1U << CMU_PCLKCR3_SPI4_PCE_Pos)ßCMU_PCLKCR3_SPI3_PCE_Pos 3àCMU_PCLKCR3_SPI3_PCE_Msk (0x1U << CMU_PCLKCR3_SPI3_PCE_Pos)âCMU_PCLKCR3_SPI2_PCE_Pos 2ãCMU_PCLKCR3_SPI2_PCE_Msk (0x1U << CMU_PCLKCR3_SPI2_PCE_Pos)åCMU_PCLKCR3_SPI1_PCE_Pos 1æCMU_PCLKCR3_SPI1_PCE_Msk (0x1U << CMU_PCLKCR3_SPI1_PCE_Pos)èCMU_PCLKCR3_SPI0_PCE_Pos 0éCMU_PCLKCR3_SPI0_PCE_Msk (0x1U << CMU_PCLKCR3_SPI0_PCE_Pos)ëCMU_PCLKCR4_ET4_PCE_Pos 6ìCMU_PCLKCR4_ET4_PCE_Msk (0x1U << CMU_PCLKCR4_ET4_PCE_Pos)îCMU_PCLKCR4_ET3_PCE_Pos 5ïCMU_PCLKCR4_ET3_PCE_Msk (0x1U << CMU_PCLKCR4_ET3_PCE_Pos)ñCMU_PCLKCR4_ET2_PCE_Pos 4òCMU_PCLKCR4_ET2_PCE_Msk (0x1U << CMU_PCLKCR4_ET2_PCE_Pos)ôCMU_PCLKCR4_ET1_PCE_Pos 3õCMU_PCLKCR4_ET1_PCE_Msk (0x1U << CMU_PCLKCR4_ET1_PCE_Pos)÷CMU_PCLKCR4_BT2_PCE_Pos 2øCMU_PCLKCR4_BT2_PCE_Msk (0x1U << CMU_PCLKCR4_BT2_PCE_Pos)úCMU_PCLKCR4_BT1_PCE_Pos 1ûCMU_PCLKCR4_BT1_PCE_Msk (0x1U << CMU_PCLKCR4_BT1_PCE_Pos)ýCMU_PCLKCR4_BSTIM_PCE_Pos 0þCMU_PCLKCR4_BSTIM_PCE_Msk (0x1U << CMU_PCLKCR4_BSTIM_PCE_Pos)CMU_OPCCR1_EXTICKE_Pos 31CMU_OPCCR1_EXTICKE_Msk (0x1U << CMU_OPCCR1_EXTICKE_Pos)CMU_OPCCR1_EXTICKSEL_Pos 30CMU_OPCCR1_EXTICKSEL_Msk (0x1U << CMU_OPCCR1_EXTICKSEL_Pos)CMU_OPCCR1_EXTICKSEL_LSCLK (0x1U << CMU_OPCCR1_EXTICKSEL_Pos)CMU_OPCCR1_EXTICKSEL_HCLK (0x0U << CMU_OPCCR1_EXTICKSEL_Pos)CMU_OPCCR1_LPUART1CKE_Pos 29CMU_OPCCR1_LPUART1CKE_Msk (0x1U << CMU_OPCCR1_LPUART1CKE_Pos)CMU_OPCCR1_LPUART0CKE_Pos 28CMU_OPCCR1_LPUART0CKE_Msk (0x1U << CMU_OPCCR1_LPUART0CKE_Pos)CMU_OPCCR1_LPUART1CKS_Pos 26CMU_OPCCR1_LPUART1CKS_Msk (0x3U << CMU_OPCCR1_LPUART1CKS_Pos)CMU_OPCCR1_LPUART1CKS_LSCLK (0x0U << CMU_OPCCR1_LPUART1CKS_Pos)CMU_OPCCR1_LPUART1CKS_RCHF (0x1U << CMU_OPCCR1_LPUART1CKS_Pos)CMU_OPCCR1_LPUART0CKS_Pos 24CMU_OPCCR1_LPUART0CKS_Msk (0x3U << CMU_OPCCR1_LPUART0CKS_Pos)CMU_OPCCR1_LPUART0CKS_LSCLK (0x0U << CMU_OPCCR1_LPUART0CKS_Pos)CMU_OPCCR1_LPUART0CKS_RCHF (0x1U << CMU_OPCCR1_LPUART0CKS_Pos) CMU_OPCCR1_I2C1CKE_Pos 21¡CMU_OPCCR1_I2C1CKE_Msk (0x1U << CMU_OPCCR1_I2C1CKE_Pos)£CMU_OPCCR1_I2C0CKE_Pos 20¤CMU_OPCCR1_I2C0CKE_Msk (0x1U << CMU_OPCCR1_I2C0CKE_Pos)¦CMU_OPCCR1_I2C1CKS_Pos 18«CMU_OPCCR1_I2C1CKS_Msk (0x3U << CMU_OPCCR1_I2C1CKS_Pos)¬CMU_OPCCR1_I2C1CKS_APBCLK (0x0U << CMU_OPCCR1_I2C1CKS_Pos)CMU_OPCCR1_I2C1CKS_RCHF (0x1U << CMU_OPCCR1_I2C1CKS_Pos)®CMU_OPCCR1_I2C1CKS_SYSCLK (0x2U << CMU_OPCCR1_I2C1CKS_Pos)°CMU_OPCCR1_I2C0CKS_Pos 16µCMU_OPCCR1_I2C0CKS_Msk (0x3U << CMU_OPCCR1_I2C0CKS_Pos)¶CMU_OPCCR1_I2C0CKS_APBCLK (0x0U << CMU_OPCCR1_I2C0CKS_Pos)·CMU_OPCCR1_I2C0CKS_RCHF (0x1U << CMU_OPCCR1_I2C0CKS_Pos)¸CMU_OPCCR1_I2C0CKS_SYSCLK (0x2U << CMU_OPCCR1_I2C0CKS_Pos)ºCMU_OPCCR1_UART1CKE_Pos 9»CMU_OPCCR1_UART1CKE_Msk (0x1U << CMU_OPCCR1_UART1CKE_Pos)½CMU_OPCCR1_UART0CKE_Pos 8¾CMU_OPCCR1_UART0CKE_Msk (0x1U << CMU_OPCCR1_UART0CKE_Pos)ÀCMU_OPCCR1_UART1CKS_Pos 2ÅCMU_OPCCR1_UART1CKS_Msk (0x3U << CMU_OPCCR1_UART1CKS_Pos)ÆCMU_OPCCR1_UART1CKS_APBCLK (0x0U << CMU_OPCCR1_UART1CKS_Pos)ÇCMU_OPCCR1_UART1CKS_RCHF (0x1U << CMU_OPCCR1_UART1CKS_Pos)ÈCMU_OPCCR1_UART1CKS_SYSCLK (0x2U << CMU_OPCCR1_UART1CKS_Pos)ÊCMU_OPCCR1_UART0CKS_Pos 0ÏCMU_OPCCR1_UART0CKS_Msk (0x3U << CMU_OPCCR1_UART0CKS_Pos)ÐCMU_OPCCR1_UART0CKS_APBCLK (0x0U << CMU_OPCCR1_UART0CKS_Pos)ÑCMU_OPCCR1_UART0CKS_RCHF (0x1U << CMU_OPCCR1_UART0CKS_Pos)ÒCMU_OPCCR1_UART0CKS_SYSCLK (0x2U << CMU_OPCCR1_UART0CKS_Pos)ÔCMU_OPCCR2_RNGPRSC_Pos 28ÜCMU_OPCCR2_RNGPRSC_Msk (0x7U << CMU_OPCCR2_RNGPRSC_Pos)ÝCMU_OPCCR2_RNGPRSC_DIV1 (0x0U << CMU_OPCCR2_RNGPRSC_Pos)ÞCMU_OPCCR2_RNGPRSC_DIV2 (0x1U << CMU_OPCCR2_RNGPRSC_Pos)ßCMU_OPCCR2_RNGPRSC_DIV4 (0x2U << CMU_OPCCR2_RNGPRSC_Pos)àCMU_OPCCR2_RNGPRSC_DIV8 (0x3U << CMU_OPCCR2_RNGPRSC_Pos)áCMU_OPCCR2_RNGPRSC_DIV16 (0x4U << CMU_OPCCR2_RNGPRSC_Pos)âCMU_OPCCR2_RNGPRSC_DIV32 (0x5U << CMU_OPCCR2_RNGPRSC_Pos)äCMU_OPCCR2_NVMCKE_Pos 22åCMU_OPCCR2_NVMCKE_Msk (0x1U << CMU_OPCCR2_NVMCKE_Pos)çCMU_OPCCR2_RNGCKE_Pos 21èCMU_OPCCR2_RNGCKE_Msk (0x1U << CMU_OPCCR2_RNGCKE_Pos)êCMU_OPCCR2_LPTCKE_Pos 12ëCMU_OPCCR2_LPTCKE_Msk (0x1U << CMU_OPCCR2_LPTCKE_Pos)íCMU_OPCCR2_LPTCKS_Pos 8òCMU_OPCCR2_LPTCKS_Msk (0x3U << CMU_OPCCR2_LPTCKS_Pos)óCMU_OPCCR2_LPTCKS_APBCLK (0x0U << CMU_OPCCR2_LPTCKS_Pos)ôCMU_OPCCR2_LPTCKS_LSCLK (0x1U << CMU_OPCCR2_LPTCKS_Pos)õCMU_OPCCR2_LPTCKS_RCLP (0x2U << CMU_OPCCR2_LPTCKS_Pos)öCMU_OPCCR2_LPTCKS_PLL_L (0x3U << CMU_OPCCR2_LPTCKS_Pos)øCMU_OPCCR2_BSTCKE_Pos 4ùCMU_OPCCR2_BSTCKE_Msk (0x1U << CMU_OPCCR2_BSTCKE_Pos)ûCMU_OPCCR2_BSTCKS_Pos 0CMU_OPCCR2_BSTCKS_Msk (0x3U << CMU_OPCCR2_BSTCKS_Pos)CMU_OPCCR2_BSTCKS_APBCLK (0x0U << CMU_OPCCR2_BSTCKS_Pos)CMU_OPCCR2_BSTCKS_LSCLK (0x1U << CMU_OPCCR2_BSTCKS_Pos)CMU_OPCCR2_BSTCKS_RCLP (0x2U << CMU_OPCCR2_BSTCKS_Pos)CMU_OPCCR2_BSTCKS_SYSCLK (0x3U << CMU_OPCCR2_BSTCKS_Pos)£COMPCLK (0x01000000 + CMU_PCLKCR1_COMP_PCE_Pos)¤SVDCLK (0x01000000 + CMU_PCLKCR1_SVD_PCE_Pos)¥PADCLK (0x01000000 + CMU_PCLKCR1_PAD_PCE_Pos)¦ANACCLK (0x01000000 + CMU_PCLKCR1_ANAC_PCE_Pos)§IWDTCLK (0x01000000 + CMU_PCLKCR1_IWDT_PCE_Pos)¨SCUCLK (0x01000000 + CMU_PCLKCR1_SCU_PCE_Pos)©PMUCLK (0x01000000 + CMU_PCLKCR1_PMU_PCE_Pos)ªRTCCLK (0x01000000 + CMU_PCLKCR1_RTC_PCE_Pos)«LPTCLK (0x01000000 + CMU_PCLKCR1_LPT_PCE_Pos)®PAECLK (0x02000000 + CMU_PCLKCR2_PAE_PCE_Pos)¯SHACLK (0x02000000 + CMU_PCLKCR2_SHA_PCE_Pos)°CICCLK (0x02000000 + CMU_PCLKCR2_CIC_PCE_Pos)±WWDTCLK (0x02000000 + CMU_PCLKCR2_WWDT_PCE_Pos)²RAMBISTCLK (0x02000000 + CMU_PCLKCR2_RAMBIST_PCE_Pos)³FLASHCLK (0x02000000 + CMU_PCLKCR2_NVM_PCE_Pos)´DMACLK (0x02000000 + CMU_PCLKCR2_DMA_PCE_Pos)µLCDCLK (0x02000000 + CMU_PCLKCR2_LCD_PCE_Pos)¶AESCLK (0x02000000 + CMU_PCLKCR2_AES_PCE_Pos)·TRNGCLK (0x02000000 + CMU_PCLKCR2_TRNG_PCE_Pos)¸CRCCLK (0x02000000 + CMU_PCLKCR2_CRC_PCE_Pos)ºI2C1CLK (0x03000000 + CMU_PCLKCR3_I2C1_PCE_Pos)»I2C0CLK (0x03000000 + CMU_PCLKCR3_I2C0_PCE_Pos)¼LPUART1CLK (0x03000000 + CMU_PCLKCR3_LPUART1_PCE_Pos)½U7816CLK (0x03000000 + CMU_PCLKCR3_U7816_PCE_Pos)¾LPUART0CLK (0x03000000 + CMU_PCLKCR3_LPUART0_PCE_Pos)¿UARTIRCLK (0x03000000 + CMU_PCLKCR3_UICR_PCE_Pos)ÀUART5CLK (0x03000000 + CMU_PCLKCR3_UART5_PCE_Pos)ÁUART4CLK (0x03000000 + CMU_PCLKCR3_UART4_PCE_Pos)ÂUART3CLK (0x03000000 + CMU_PCLKCR3_UART3_PCE_Pos)ÃUART2CLK (0x03000000 + CMU_PCLKCR3_UART2_PCE_Pos)ÄUART1CLK (0x03000000 + CMU_PCLKCR3_UART1_PCE_Pos)ÅUART0CLK (0x03000000 + CMU_PCLKCR3_UART0_PCE_Pos)ÆQSPICLK (0x03000000 + CMU_PCLKCR3_QSPI_PCE_Pos)ÇSPI4CLK (0x03000000 + CMU_PCLKCR3_SPI4_PCE_Pos)ÈSPI3CLK (0x03000000 + CMU_PCLKCR3_SPI3_PCE_Pos)ÉSPI2CLK (0x03000000 + CMU_PCLKCR3_SPI2_PCE_Pos)ÊSPI1CLK (0x03000000 + CMU_PCLKCR3_SPI1_PCE_Pos)ËSPI0CLK (0x03000000 + CMU_PCLKCR3_SPI0_PCE_Pos)ÎET4CLK (0x04000000 + CMU_PCLKCR4_ET4_PCE_Pos)ÏET3CLK (0x04000000 + CMU_PCLKCR4_ET3_PCE_Pos)ÐET2CLK (0x04000000 + CMU_PCLKCR4_ET2_PCE_Pos)ÑET1CLK (0x04000000 + CMU_PCLKCR4_ET1_PCE_Pos)ÒBT2CLK (0x04000000 + CMU_PCLKCR4_BT2_PCE_Pos)ÓBT1CLK (0x04000000 + CMU_PCLKCR4_BT1_PCE_Pos)ÔBSTIMCLK (0x04000000 + CMU_PCLKCR4_BSTIM_PCE_Pos)`T ..\Drivers\..\Core\Include\fm33a0xxev_cmu.hFM33A0XXEV.hð
..\Drivers\fm33a0xxev_cmu.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM*àFSELf#RCHFEN#PCMU_RCHF_InitTypeDef½)*¢PLLLDBf#PLLL_EN#PCMU_PLL_L_InitTypeDefü/*PLLHDBf#REFPRSCf#PLLH_OSELf#PLLH_INSELf#PLLH_EN#PCMU_PLL_H_InitTypeDef?9*SYSCLKSELf#AHBPRESf#APBPRESf#SLP_ENEXTI#PCMU_SYSCLK_InitTypeDefºC*ÛSYSCLK_Frequencyf#AHBCLK_Frequencyf#APBCLK_Frequencyf#RCHF_Frequencyf#PLL_H_Frequencyf#XTHF_Frequencyf#LSCLK_Frequencyf#PCMU_ClocksType&Nµ¶·__FM33A0XXEV_RTC_H /RTC_WRITE_ENABLE ((uint32_t)0xACACACAC)0RTC_WRITE_DISABLE ((uint32_t)0x55AA55AA)2RTC_WER_RTCWE_Pos 04RTC_WER_RTCWE_Msk (0x1U << RTC_WER_RTCWE_Pos)6RTC_IER_ADJ_IE_Pos 129RTC_IER_ADJ_IE_Msk (0x1U << RTC_IER_ADJ_IE_Pos)=RTC_IER_ALARM_IE_Pos 11@RTC_IER_ALARM_IE_Msk (0x1U << RTC_IER_ALARM_IE_Pos)DRTC_IER_1KHZ_IE_Pos 10GRTC_IER_1KHZ_IE_Msk (0x1U << RTC_IER_1KHZ_IE_Pos)KRTC_IER_256HZ_IE_Pos 9NRTC_IER_256HZ_IE_Msk (0x1U << RTC_IER_256HZ_IE_Pos)RRTC_IER_64HZ_IE_Pos 8URTC_IER_64HZ_IE_Msk (0x1U << RTC_IER_64HZ_IE_Pos)YRTC_IER_16HZ_IE_Pos 7\RTC_IER_16HZ_IE_Msk (0x1U << RTC_IER_16HZ_IE_Pos)`RTC_IER_8HZ_IE_Pos 6cRTC_IER_8HZ_IE_Msk (0x1U << RTC_IER_8HZ_IE_Pos)gRTC_IER_4HZ_IE_Pos 5jRTC_IER_4HZ_IE_Msk (0x1U << RTC_IER_4HZ_IE_Pos)nRTC_IER_2HZ_IE_Pos 4qRTC_IER_2HZ_IE_Msk (0x1U << RTC_IER_2HZ_IE_Pos)uRTC_IER_SEC_IE_Pos 3xRTC_IER_SEC_IE_Msk (0x1U << RTC_IER_SEC_IE_Pos)|RTC_IER_MIN_IE_Pos 2RTC_IER_MIN_IE_Msk (0x1U << RTC_IER_MIN_IE_Pos)RTC_IER_HOUR_IE_Pos 1RTC_IER_HOUR_IE_Msk (0x1U << RTC_IER_HOUR_IE_Pos)RTC_IER_DATE_IE_Pos 0RTC_IER_DATE_IE_Msk (0x1U << RTC_IER_DATE_IE_Pos)RTC_ISR_ADJ_IF_Pos 12RTC_ISR_ADJ_IF_Msk (0x1U << RTC_ISR_ADJ_IF_Pos)RTC_ISR_ALARM_IF_Pos 11RTC_ISR_ALARM_IF_Msk (0x1U << RTC_ISR_ALARM_IF_Pos)RTC_ISR_1KHZ_IF_Pos 10RTC_ISR_1KHZ_IF_Msk (0x1U << RTC_ISR_1KHZ_IF_Pos) RTC_ISR_256HZ_IF_Pos 9£RTC_ISR_256HZ_IF_Msk (0x1U << RTC_ISR_256HZ_IF_Pos)¦RTC_ISR_64HZ_IF_Pos 8©RTC_ISR_64HZ_IF_Msk (0x1U << RTC_ISR_64HZ_IF_Pos)¬RTC_ISR_16HZ_IF_Pos 7¯RTC_ISR_16HZ_IF_Msk (0x1U << RTC_ISR_16HZ_IF_Pos)±RTC_ISR_8HZ_IF_Pos 6´RTC_ISR_8HZ_IF_Msk (0x1U << RTC_ISR_8HZ_IF_Pos)¶RTC_ISR_4HZ_IF_Pos 5¹RTC_ISR_4HZ_IF_Msk (0x1U << RTC_ISR_4HZ_IF_Pos)»RTC_ISR_2HZ_IF_Pos 4¾RTC_ISR_2HZ_IF_Msk (0x1U << RTC_ISR_2HZ_IF_Pos)ÀRTC_ISR_SEC_IF_Pos 3ÃRTC_ISR_SEC_IF_Msk (0x1U << RTC_ISR_SEC_IF_Pos)ÅRTC_ISR_MIN_IF_Pos 2ÈRTC_ISR_MIN_IF_Msk (0x1U << RTC_ISR_MIN_IF_Pos)ÊRTC_ISR_HOUR_IF_Pos 1ÍRTC_ISR_HOUR_IF_Msk (0x1U << RTC_ISR_HOUR_IF_Pos)ÏRTC_ISR_DATE_IF_Pos 0ÒRTC_ISR_DATE_IF_Msk (0x1U << RTC_ISR_DATE_IF_Pos)ÔRTC_BCDSEC_BCDSEC_Pos 0ÕRTC_BCDSEC_BCDSEC_Msk (0x7fU << RTC_BCDSEC_BCDSEC_Pos)×RTC_BCDMIN_BCDMIN_Pos 0ØRTC_BCDMIN_BCDMIN_Msk (0x7fU << RTC_BCDMIN_BCDMIN_Pos)ÚRTC_BCDHOUR_BCDHOUR_Pos 0ÛRTC_BCDHOUR_BCDHOUR_Msk (0x3fU << RTC_BCDHOUR_BCDHOUR_Pos)ÝRTC_BCDDATE_BCDDATE_Pos 0ÞRTC_BCDDATE_BCDDATE_Msk (0x3fU << RTC_BCDDATE_BCDDATE_Pos)àRTC_BCDWEEK_BCDWEEK_Pos 0áRTC_BCDWEEK_BCDWEEK_Msk (0x7U << RTC_BCDWEEK_BCDWEEK_Pos)ãRTC_BCDMONTH_BCDMONTH_Pos 0äRTC_BCDMONTH_BCDMONTH_Msk (0x1fU << RTC_BCDMONTH_BCDMONTH_Pos)æRTC_BCDYEAR_BCDYEAR_Pos 0çRTC_BCDYEAR_BCDYEAR_Msk (0xffU << RTC_BCDYEAR_BCDYEAR_Pos)éRTC_ALARM_ALMEN_Pos 31ìRTC_ALARM_ALMEN_Msk (0x1U << RTC_ALARM_ALMEN_Pos)ðRTC_ALARM_ALARMHOUR_Pos 16ñRTC_ALARM_ALARMHOUR_Msk (0x3fU << RTC_ALARM_ALARMHOUR_Pos)óRTC_ALARM_ALARMMIN_Pos 8ôRTC_ALARM_ALARMMIN_Msk (0x7fU << RTC_ALARM_ALARMMIN_Pos)öRTC_ALARM_ALARMSEC_Pos 0÷RTC_ALARM_ALARMSEC_Msk (0x7fU << RTC_ALARM_ALARMSEC_Pos)ùRTC_TMSEL_FSEL_Pos 0RTC_TMSEL_FSEL_Msk (0xfU << RTC_TMSEL_FSEL_Pos)RTC_TMSEL_FSEL_PLL1HZ (0x0U << RTC_TMSEL_FSEL_Pos)RTC_TMSEL_FSEL_PLLD1HZ (0x1U << RTC_TMSEL_FSEL_Pos)RTC_TMSEL_FSEL_SECOND (0x2U << RTC_TMSEL_FSEL_Pos)RTC_TMSEL_FSEL_MINUTE (0x3U << RTC_TMSEL_FSEL_Pos)RTC_TMSEL_FSEL_HOUR (0x4U << RTC_TMSEL_FSEL_Pos)RTC_TMSEL_FSEL_DAY (0x5U << RTC_TMSEL_FSEL_Pos)RTC_TMSEL_FSEL_ALARM (0x6U << RTC_TMSEL_FSEL_Pos)RTC_TMSEL_FSEL_256S (0x7U << RTC_TMSEL_FSEL_Pos)RTC_TMSEL_FSEL_PLLD1HZREV (0x8U << RTC_TMSEL_FSEL_Pos)RTC_TMSEL_FSEL_SECONDREV (0x9U << RTC_TMSEL_FSEL_Pos)RTC_TMSEL_FSEL_MINUTEREV (0xaU << RTC_TMSEL_FSEL_Pos)RTC_TMSEL_FSEL_HOURREV (0xbU << RTC_TMSEL_FSEL_Pos)RTC_TMSEL_FSEL_DAYREV (0xcU << RTC_TMSEL_FSEL_Pos)RTC_TMSEL_FSEL_ALARMREV (0xdU << RTC_TMSEL_FSEL_Pos)RTC_TMSEL_FSEL_PLL1HZREV (0xeU << RTC_TMSEL_FSEL_Pos)RTC_TMSEL_FSEL_SECONDRUN (0xfU << RTC_TMSEL_FSEL_Pos) RTC_ADJUST_ADJUST_Pos 0¡RTC_ADJUST_ADJUST_Msk (0x1fffU << RTC_ADJUST_ADJUST_Pos)£RTC_ADSIGN_ADSIGN_Pos 0¦RTC_ADSIGN_ADSIGN_Msk (0x1U << RTC_ADSIGN_ADSIGN_Pos)§RTC_ADSIGN_ADSIGN_INCREASE (0x0U << RTC_ADSIGN_ADSIGN_Pos)¨RTC_ADSIGN_ADSIGN_DECREASE (0x1U << RTC_ADSIGN_ADSIGN_Pos)ªRTC_VCAL_PR1SEN_Pos 0RTC_VCAL_PR1SEN_Msk (0x1U << RTC_VCAL_PR1SEN_Pos)±RTC_MSCNT_MSCNT_Pos 0µRTC_MSCNT_MSCNT_Msk (0xffU << RTC_MSCNT_MSCNT_Pos)·RTC_CALSTEP_CALSTEP_Pos 0»RTC_CALSTEP_CALSTEP_Msk (0x1U << RTC_CALSTEP_CALSTEP_Pos)¼RTC_CALSTEP_CALSTEP_006PPM (0x2U << RTC_CALSTEP_CALSTEP_Pos)½RTC_CALSTEP_CALSTEP_0119PPM (0x1U << RTC_CALSTEP_CALSTEP_Pos)¾RTC_CALSTEP_CALSTEP_0238PPM (0x0U << RTC_CALSTEP_CALSTEP_Pos)ÀRTC_ADCNT_ADJCNT_Pos 0ÁRTC_ADCNT_ADJCNT_Msk (0x1ffU << RTC_ADCNT_ADJCNT_Pos)ÃRTC_SSR_SSR_Pos 0ÅRTC_SSR_SSR_Msk (0x3fU << RTC_SSR_SSR_Pos)ÇRTC_SSA_SSAEN_Pos 7ÊRTC_SSA_SSAEN_Msk (0x1U << RTC_SSA_SSAEN_Pos)ÎRTC_SSA_SS_ALARM_Pos 0ÐRTC_SSA_SS_ALARM_Msk (0x3fU << RTC_SSA_SS_ALARM_Pos)ÒRTC_DTR_DUTY_Pos 0ÓRTC_DTR_DUTY_Msk (0x1ffffffU << RTC_DTR_DUTY_Pos)ÕRTC_CR_RTC_EN_Pos 0ÚRTC_CR_RTC_EN_Msk (0x1U << RTC_CR_RTC_EN_Pos)`T ..\Drivers\..\Core\Include\fm33a0xxev_rtc.hFM33A0XXEV.h°
..\Drivers\fm33a0xxev_rtc.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM*©Year8#Month8#Date8#Hour8#Minute8#Second8#Week8#PRTC_TimeDateTypeDef½#PRTC_StampTmieTypeDef½#*Hour8#Minute8#Second8#PRTC_AlarmTmieTypeDef`+¹º»__FM33A0XXEV_DBG_H DBG_CR_DBG_LPT_STOP_Pos 15DBG_CR_DBG_LPT_STOP_Msk (0x1U << DBG_CR_DBG_LPT_STOP_Pos) DBG_CR_DBG_BST_STOP_Pos 14#DBG_CR_DBG_BST_STOP_Msk (0x1U << DBG_CR_DBG_BST_STOP_Pos)'DBG_CR_DBG_ET4_STOP_Pos 13*DBG_CR_DBG_ET4_STOP_Msk (0x1U << DBG_CR_DBG_ET4_STOP_Pos).DBG_CR_DBG_ET3_STOP_Pos 121DBG_CR_DBG_ET3_STOP_Msk (0x1U << DBG_CR_DBG_ET3_STOP_Pos)5DBG_CR_DBG_ET2_STOP_Pos 118DBG_CR_DBG_ET2_STOP_Msk (0x1U << DBG_CR_DBG_ET2_STOP_Pos)<DBG_CR_DBG_ET1_STOP_Pos 10?DBG_CR_DBG_ET1_STOP_Msk (0x1U << DBG_CR_DBG_ET1_STOP_Pos)CDBG_CR_DBG_BT2_STOP_Pos 9FDBG_CR_DBG_BT2_STOP_Msk (0x1U << DBG_CR_DBG_BT2_STOP_Pos)JDBG_CR_DBG_BT1_STOP_Pos 8MDBG_CR_DBG_BT1_STOP_Msk (0x1U << DBG_CR_DBG_BT1_STOP_Pos)QDBG_CR_DBG_WWDT_STOP_Pos 1TDBG_CR_DBG_WWDT_STOP_Msk (0x1U << DBG_CR_DBG_WWDT_STOP_Pos)XDBG_CR_DBG_IWDT_STOP_Pos 0[DBG_CR_DBG_IWDT_STOP_Msk (0x1U << DBG_CR_DBG_IWDT_STOP_Pos)_DBG_HDFR_DABORT_ADDR_FLAG_Pos 6bDBG_HDFR_DABORT_ADDR_FLAG_Msk (0x1U << DBG_HDFR_DABORT_ADDR_FLAG_Pos)dDBG_HDFR_DABORT_RESP_FLAG_Pos 5gDBG_HDFR_DABORT_RESP_FLAG_Msk (0x1U << DBG_HDFR_DABORT_RESP_FLAG_Pos)iDBG_HDFR_SVCUNDEF_FLAG_Pos 4nDBG_HDFR_SVCUNDEF_FLAG_Msk (0x1U << DBG_HDFR_SVCUNDEF_FLAG_Pos)pDBG_HDFR_BKPT_FLAG_Pos 3sDBG_HDFR_BKPT_FLAG_Msk (0x1U << DBG_HDFR_BKPT_FLAG_Pos)uDBG_HDFR_TBIT_FLAG_Pos 2xDBG_HDFR_TBIT_FLAG_Msk (0x1U << DBG_HDFR_TBIT_FLAG_Pos)zDBG_HDFR_SPECIAL_OP_FLAG_Pos 1}DBG_HDFR_SPECIAL_OP_FLAG_Msk (0x1U << DBG_HDFR_SPECIAL_OP_FLAG_Pos)DBG_HDFR_HDF_REQUEST_FLAG_Pos 0DBG_HDFR_HDF_REQUEST_FLAG_Msk (0x1U << DBG_HDFR_HDF_REQUEST_FLAG_Pos)`T ..\Drivers\..\Core\Include\fm33a0xxev_dbg.hFM33A0XXEV.h¼
..\Drivers\fm33a0xxev_dbg.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM½¾¿__FM33A0XXEV_SPI_H SPIx_CR1_IOSWAP_Pos 11SPIx_CR1_IOSWAP_Msk (0x1U << SPIx_CR1_IOSWAP_Pos)SPIx_CR1_IOSWAP_DEFAULT (0x0U << SPIx_CR1_IOSWAP_Pos) SPIx_CR1_IOSWAP_EXCHANGE (0x1U << SPIx_CR1_IOSWAP_Pos)"SPIx_CR1_MSPA_Pos 10%SPIx_CR1_MSPA_Msk (0x1U << SPIx_CR1_MSPA_Pos)&SPIx_CR1_MSPA_DELAY (0x1U << SPIx_CR1_MSPA_Pos)'SPIx_CR1_MSPA_NORMAL (0x0U << SPIx_CR1_MSPA_Pos))SPIx_CR1_SSPA_Pos 9,SPIx_CR1_SSPA_Msk (0x1U << SPIx_CR1_SSPA_Pos)-SPIx_CR1_SSPA_EARLY (0x1U << SPIx_CR1_SSPA_Pos).SPIx_CR1_SSPA_NORMAL (0x0U << SPIx_CR1_SSPA_Pos)0SPIx_CR1_MM_Pos 81SPIx_CR1_MM_Msk (0x1U << SPIx_CR1_MM_Pos)2SPIx_CR1_MM_MASTER (0x1U << SPIx_CR1_MM_Pos)3SPIx_CR1_MM_SLAVE (0x0U << SPIx_CR1_MM_Pos)5SPIx_CR1_WAIT_Pos 66SPIx_CR1_WAIT_Msk (0x3U << SPIx_CR1_WAIT_Pos)7SPIx_CR1_WAIT_1WAIT (0x0U << SPIx_CR1_WAIT_Pos)8SPIx_CR1_WAIT_2WAIT (0x1U << SPIx_CR1_WAIT_Pos)9SPIx_CR1_WAIT_3WAIT (0x2U << SPIx_CR1_WAIT_Pos):SPIx_CR1_WAIT_4WAIT (0x3U << SPIx_CR1_WAIT_Pos)<SPIx_CR1_BAUD_Pos 3=SPIx_CR1_BAUD_Msk (0x7U << SPIx_CR1_BAUD_Pos)>SPIx_CR1_BAUD_DIV2 (0x0U << SPIx_CR1_BAUD_Pos)?SPIx_CR1_BAUD_DIV4 (0x1U << SPIx_CR1_BAUD_Pos)@SPIx_CR1_BAUD_DIV8 (0x2U << SPIx_CR1_BAUD_Pos)ASPIx_CR1_BAUD_DIV16 (0x3U << SPIx_CR1_BAUD_Pos)BSPIx_CR1_BAUD_DIV32 (0x4U << SPIx_CR1_BAUD_Pos)CSPIx_CR1_BAUD_DIV64 (0x5U << SPIx_CR1_BAUD_Pos)DSPIx_CR1_BAUD_DIV128 (0x6U << SPIx_CR1_BAUD_Pos)ESPIx_CR1_BAUD_DIV256 (0x7U << SPIx_CR1_BAUD_Pos)GSPIx_CR1_LSBF_Pos 2HSPIx_CR1_LSBF_Msk (0x1U << SPIx_CR1_LSBF_Pos)ISPIx_CR1_LSBF_MSB (0x0U << SPIx_CR1_LSBF_Pos)JSPIx_CR1_LSBF_LSB (0x1U << SPIx_CR1_LSBF_Pos)LSPIx_CR1_CPHOL_Pos 1MSPIx_CR1_CPHOL_Msk (0x1U << SPIx_CR1_CPHOL_Pos)NSPIx_CR1_CPHOL_LOW (0x0U << SPIx_CR1_CPHOL_Pos)OSPIx_CR1_CPHOL_HIGH (0x1U << SPIx_CR1_CPHOL_Pos)QSPIx_CR1_CPHA_Pos 0RSPIx_CR1_CPHA_Msk (0x1U << SPIx_CR1_CPHA_Pos)SSPIx_CR1_CPHA_1CLOCK (0x0U << SPIx_CR1_CPHA_Pos)TSPIx_CR1_CPHA_2CLOCK (0x1U << SPIx_CR1_CPHA_Pos)VSPIx_CR2_DUMMY_EN_Pos 15ZSPIx_CR2_DUMMY_EN_Msk (0x1U << SPIx_CR2_DUMMY_EN_Pos)^SPIx_CR2_RXO_Pos 11aSPIx_CR2_RXO_Msk (0x1U << SPIx_CR2_RXO_Pos)eSPIx_CR2_DLEN_Pos 9jSPIx_CR2_DLEN_Msk (0x3U << SPIx_CR2_DLEN_Pos)kSPIx_CR2_DLEN_8BIT (0x0U << SPIx_CR2_DLEN_Pos)lSPIx_CR2_DLEN_16BIT (0x1U << SPIx_CR2_DLEN_Pos)mSPIx_CR2_DLEN_24BIT (0x2U << SPIx_CR2_DLEN_Pos)nSPIx_CR2_DLEN_32BIT (0x3U << SPIx_CR2_DLEN_Pos)pSPIx_CR2_HALFDUPLEX_Pos 8sSPIx_CR2_HALFDUPLEX_Msk (0x1U << SPIx_CR2_HALFDUPLEX_Pos)tSPIx_CR2_HALFDUPLEX_SPI (0x0U << SPIx_CR2_HALFDUPLEX_Pos)uSPIx_CR2_HALFDUPLEX_DCN (0x1U << SPIx_CR2_HALFDUPLEX_Pos)wSPIx_CR2_HD_RW_Pos 7zSPIx_CR2_HD_RW_Msk (0x1U << SPIx_CR2_HD_RW_Pos){SPIx_CR2_HD_RW_WRITE (0x0U << SPIx_CR2_HD_RW_Pos)|SPIx_CR2_HD_RW_READ (0x1U << SPIx_CR2_HD_RW_Pos)~SPIx_CR2_CMD8b_Pos 6SPIx_CR2_CMD8b_Msk (0x1U << SPIx_CR2_CMD8b_Pos)SPIx_CR2_CMD8b_8BIT (0x1U << SPIx_CR2_CMD8b_Pos)SPIx_CR2_CMD8b_DLEN (0x0U << SPIx_CR2_CMD8b_Pos)SPIx_CR2_SSNM_Pos 5SPIx_CR2_SSNM_Msk (0x1U << SPIx_CR2_SSNM_Pos)SPIx_CR2_SSNM_HIGH (0x1U << SPIx_CR2_SSNM_Pos)SPIx_CR2_SSNM_LOW (0x0U << SPIx_CR2_SSNM_Pos)SPIx_CR2_TXO_AC_Pos 4SPIx_CR2_TXO_AC_Msk (0x1U << SPIx_CR2_TXO_AC_Pos)SPIx_CR2_TXO_Pos 3SPIx_CR2_TXO_Msk (0x1U << SPIx_CR2_TXO_Pos)SPIx_CR2_SSN_Pos 2SPIx_CR2_SSN_Msk (0x1U << SPIx_CR2_SSN_Pos)SPIx_CR2_SSN_LOW (0x0U << SPIx_CR2_SSN_Pos)SPIx_CR2_SSN_HIGH (0x1U << SPIx_CR2_SSN_Pos)SPIx_CR2_SSNSEN_Pos 1SPIx_CR2_SSNSEN_Msk (0x1U << SPIx_CR2_SSNSEN_Pos)£SPIx_CR2_SPIEN_Pos 0¤SPIx_CR2_SPIEN_Msk (0x1U << SPIx_CR2_SPIEN_Pos)¦SPIx_CR3_TXBFC_Pos 3§SPIx_CR3_TXBFC_Msk (0x1U << SPIx_CR3_TXBFC_Pos)©SPIx_CR3_RXBFC_Pos 2ªSPIx_CR3_RXBFC_Msk (0x1U << SPIx_CR3_RXBFC_Pos)¬SPIx_CR3_MERRC_Pos 1SPIx_CR3_MERRC_Msk (0x1U << SPIx_CR3_MERRC_Pos)¯SPIx_CR3_SERRC_Pos 0°SPIx_CR3_SERRC_Msk (0x1U << SPIx_CR3_SERRC_Pos)²SPIx_IER_ERRIE_Pos 2³SPIx_IER_ERRIE_Msk (0x1U << SPIx_IER_ERRIE_Pos)µSPIx_IER_TXIE_Pos 1¶SPIx_IER_TXIE_Msk (0x1U << SPIx_IER_TXIE_Pos)¸SPIx_IER_RXIE_Pos 0¹SPIx_IER_RXIE_Msk (0x1U << SPIx_IER_RXIE_Pos)»SPIx_ISR_DCN_TX_Pos 12¿SPIx_ISR_DCN_TX_Msk (0x1U << SPIx_ISR_DCN_TX_Pos)ÀSPIx_ISR_DCN_TX_COMMAND (0x0U << SPIx_ISR_DCN_TX_Pos)ÁSPIx_ISR_DCN_TX_DATA (0x1U << SPIx_ISR_DCN_TX_Pos)ÃSPIx_ISR_RXCOL_Pos 10ÄSPIx_ISR_RXCOL_Msk (0x1U << SPIx_ISR_RXCOL_Pos)ÆSPIx_ISR_TXCOL_Pos 9ÇSPIx_ISR_TXCOL_Msk (0x1U << SPIx_ISR_TXCOL_Pos)ÉSPIx_ISR_BUSY_Pos 8ÌSPIx_ISR_BUSY_Msk (0x1U << SPIx_ISR_BUSY_Pos)ÎSPIx_ISR_MERR_Pos 6ÐSPIx_ISR_MERR_Msk (0x1U << SPIx_ISR_MERR_Pos)ÒSPIx_ISR_SERR_Pos 5ÔSPIx_ISR_SERR_Msk (0x1U << SPIx_ISR_SERR_Pos)ÖSPIx_ISR_TXBE_Pos 1ÙSPIx_ISR_TXBE_Msk (0x1U << SPIx_ISR_TXBE_Pos)ÛSPIx_ISR_RXBF_Pos 0ÞSPIx_ISR_RXBF_Msk (0x1U << SPIx_ISR_RXBF_Pos)àSPIx_TXBUF_TXBUF_Pos 0áSPIx_TXBUF_TXBUF_Msk (0xffffffffU << SPIx_TXBUF_TXBUF_Pos)ãSPIx_RXBUF_RXBUF_Pos 0äSPIx_RXBUF_RXBUF_Msk (0xffffffffU << SPIx_RXBUF_RXBUF_Pos)`T ..\Drivers\..\Core\Include\fm33a0xxev_spi.hFM33A0XXEV.h¼
..\Drivers\fm33a0xxev_spi.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMÁÂÃ__FM33A0XXEV_RNG_H RNG_CR_EN_Pos 0RNG_CR_EN_Msk (0x1U << RNG_CR_EN_Pos) RNG_DOR_OUT_Pos 0"RNG_DOR_OUT_Msk (0xffffffffU << RNG_DOR_OUT_Pos)$RNG_SR_LFSREN_Pos 1(RNG_SR_LFSREN_Msk (0x1U << RNG_SR_LFSREN_Pos)-RNG_SR_RNF_Pos 00RNG_SR_RNF_Msk (0x1U << RNG_SR_RNF_Pos)2RNG_CRC_CR_CRCEN_Pos 05RNG_CRC_CR_CRCEN_Msk (0x1U << RNG_CRC_CR_CRCEN_Pos)9RNG_CRC_DIR_CRCIN_Pos 0:RNG_CRC_DIR_CRCIN_Msk (0xffffffffU << RNG_CRC_DIR_CRCIN_Pos)<RNG_CRC_SR_CRCDONE_Pos 0?RNG_CRC_SR_CRCDONE_Msk (0x1U << RNG_CRC_SR_CRCDONE_Pos)`T ..\Drivers\..\Core\Include\fm33a0xxev_rng.hFM33A0XXEV.h¼
..\Drivers\fm33a0xxev_rng.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMÅÆÇ__FM33A0XXEV_U7816_H 7U7816_CR_TXEN_Pos 58U7816_CR_TXEN_Msk (0x1U << U7816_CR_TXEN_Pos):U7816_CR_RXEN_Pos 4;U7816_CR_RXEN_Msk (0x1U << U7816_CR_RXEN_Pos)=U7816_CR_CKOEN_Pos 3>U7816_CR_CKOEN_Msk (0x1U << U7816_CR_CKOEN_Pos)@U7816_CR_HPUAT_Pos 2AU7816_CR_HPUAT_Msk (0x1U << U7816_CR_HPUAT_Pos)CU7816_CR_HPUEN_Pos 1DU7816_CR_HPUEN_Msk (0x1U << U7816_CR_HPUEN_Pos)FU7816_FFR_SFREN_Pos 11GU7816_FFR_SFREN_Msk (0x1U << U7816_FFR_SFREN_Pos)HU7816_FFR_SFREN_3ETU (0x1U << U7816_FFR_SFREN_Pos)IU7816_FFR_SFREN_2ETU (0x0U << U7816_FFR_SFREN_Pos)KU7816_FFR_ERSW_Pos 9LU7816_FFR_ERSW_Msk (0x3U << U7816_FFR_ERSW_Pos)MU7816_FFR_ERSW_1ETU (0x0U << U7816_FFR_ERSW_Pos)NU7816_FFR_ERSW_1P5ETU (0x1U << U7816_FFR_ERSW_Pos)OU7816_FFR_ERSW_2ETU (0x2U << U7816_FFR_ERSW_Pos)QU7816_FFR_ERSGD_Pos 8SU7816_FFR_ERSGD_Msk (0x1U << U7816_FFR_ERSGD_Pos)TU7816_FFR_ERSGD_1ETU (0x1U << U7816_FFR_ERSGD_Pos)UU7816_FFR_ERSGD_2ETU (0x0U << U7816_FFR_ERSGD_Pos)WU7816_FFR_BGTEN_Pos 7XU7816_FFR_BGTEN_Msk (0x1U << U7816_FFR_BGTEN_Pos)ZU7816_FFR_REP_T_Pos 6[U7816_FFR_REP_T_Msk (0x1U << U7816_FFR_REP_T_Pos)\U7816_FFR_REP_T_1TIMES (0x0U << U7816_FFR_REP_T_Pos)]U7816_FFR_REP_T_3TIMES (0x1U << U7816_FFR_REP_T_Pos)_U7816_FFR_PAR_Pos 4`U7816_FFR_PAR_Msk (0x3U << U7816_FFR_PAR_Pos)aU7816_FFR_PAR_EVEN (0x0U << U7816_FFR_PAR_Pos)bU7816_FFR_PAR_ODD (0x1U << U7816_FFR_PAR_Pos)cU7816_FFR_PAR_1ALAWAYS (0x2U << U7816_FFR_PAR_Pos)dU7816_FFR_PAR_NON (0x3U << U7816_FFR_PAR_Pos)fU7816_FFR_RFREN_Pos 3gU7816_FFR_RFREN_Msk (0x1U << U7816_FFR_RFREN_Pos)hU7816_FFR_RFREN_1ETU (0x1U << U7816_FFR_RFREN_Pos)iU7816_FFR_RFREN_2ETU (0x0U << U7816_FFR_RFREN_Pos)kU7816_FFR_TREPEN_Pos 2lU7816_FFR_TREPEN_Msk (0x1U << U7816_FFR_TREPEN_Pos)nU7816_FFR_RREPEN_Pos 1oU7816_FFR_RREPEN_Msk (0x1U << U7816_FFR_RREPEN_Pos)qU7816_FFR_DICONV_Pos 0rU7816_FFR_DICONV_Msk (0x1U << U7816_FFR_DICONV_Pos)sU7816_FFR_DICONV_FORWARD (0x0U << U7816_FFR_DICONV_Pos)tU7816_FFR_DICONV_REVERSE (0x1U << U7816_FFR_DICONV_Pos)vU7816_EGTR_TXEGT_Pos 0xU7816_EGTR_TXEGT_Msk (0xffU << U7816_EGTR_TXEGT_Pos)zU7816_PSC_CLKDIV_Pos 0{U7816_PSC_CLKDIV_Msk (0x1fU << U7816_PSC_CLKDIV_Pos)}U7816_BGR_PDIV_Pos 0U7816_BGR_PDIV_Msk (0xfffU << U7816_BGR_PDIV_Pos)U7816_RXBUF_RXBUF_Pos 0U7816_RXBUF_RXBUF_Msk (0xffU << U7816_RXBUF_RXBUF_Pos)U7816_TXBUF_TXBUF_Pos 0U7816_TXBUF_TXBUF_Msk (0xffU << U7816_TXBUF_TXBUF_Pos)U7816_IER_RXIE_Pos 2U7816_IER_RXIE_Msk (0x1U << U7816_IER_RXIE_Pos)U7816_IER_TXIE_Pos 1U7816_IER_TXIE_Msk (0x1U << U7816_IER_TXIE_Pos)U7816_IER_LSIE_Pos 0U7816_IER_LSIE_Msk (0x1U << U7816_IER_LSIE_Pos)U7816_ISR_WAIT_RPT_Pos 18U7816_ISR_WAIT_RPT_Msk (0x1U << U7816_ISR_WAIT_RPT_Pos)U7816_ISR_TXBUSY_Pos 17U7816_ISR_TXBUSY_Msk (0x1U << U7816_ISR_TXBUSY_Pos)U7816_ISR_RXBUSY_Pos 16U7816_ISR_RXBUSY_Msk (0x1U << U7816_ISR_RXBUSY_Pos)U7816_ISR_TPARERR_Pos 11U7816_ISR_TPARERR_Msk (0x1U << U7816_ISR_TPARERR_Pos)U7816_ISR_RPARERR_Pos 10U7816_ISR_RPARERR_Msk (0x1U << U7816_ISR_RPARERR_Pos) U7816_ISR_FRERR_Pos 9¡U7816_ISR_FRERR_Msk (0x1U << U7816_ISR_FRERR_Pos)£U7816_ISR_OVERR_Pos 8¤U7816_ISR_OVERR_Msk (0x1U << U7816_ISR_OVERR_Pos)¦U7816_ISR_RXIF_Pos 2§U7816_ISR_RXIF_Msk (0x1U << U7816_ISR_RXIF_Pos)©U7816_ISR_TXIF_Pos 1ªU7816_ISR_TXIF_Msk (0x1U << U7816_ISR_TXIF_Pos)¬U7816_ISR_ERRIF_Pos 0U7816_ISR_ERRIF_Msk (0x1U << U7816_ISR_ERRIF_Pos)`V ..\Drivers\..\Core\Include\fm33a0xxev_u7816.hFM33A0XXEV.h
..\Drivers\fm33a0xxev_u7816.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM*ú8TXEN#RXEN#CKOEN#HPUAT#HPUEN#ERSWf#ERSGDf#BGTEN#REP_Tf#PARf#SFRENf#RFRENf# TREPEN#$RREPEN#%DICONV#&TXEGTf#(CLKDIVf#,PDIVf#0RXIE#4TXIE#5LSIE#6PU7816_InitTypeDef¿4ÉÊË__FM33A0XXEV_UART_H OUARTIR_CR_IRFLAG_Pos 15RUARTIR_CR_IRFLAG_Msk (0x1U << UARTIR_CR_IRFLAG_Pos)SUARTIR_CR_IRFLAG_POSITIVE (0x0U << UARTIR_CR_IRFLAG_Pos)TUARTIR_CR_IRFLAG_NEGTIVE (0x1U << UARTIR_CR_IRFLAG_Pos)VUARTIR_CR_TH_Pos 11WUARTIR_CR_TH_Msk (0xfU << UARTIR_CR_TH_Pos)YUARTIR_CR_TZBRG_Pos 0ZUARTIR_CR_TZBRG_Msk (0x7ffU << UARTIR_CR_TZBRG_Pos)\UARTx_CSR_BUSY_Pos 24_UARTx_CSR_BUSY_Msk (0x1U << UARTx_CSR_BUSY_Pos)aUARTx_CSR_TXIREN_Pos 17dUARTx_CSR_TXIREN_Msk (0x1U << UARTx_CSR_TXIREN_Pos)hUARTx_CSR_RXTOEN_Pos 16kUARTx_CSR_RXTOEN_Msk (0x1U << UARTx_CSR_RXTOEN_Pos)oUARTx_CSR_IOSWAP_Pos 12rUARTx_CSR_IOSWAP_Msk (0x1U << UARTx_CSR_IOSWAP_Pos)sUARTx_CSR_IOSWAP_DEFAULT (0x0U << UARTx_CSR_IOSWAP_Pos)tUARTx_CSR_IOSWAP_EXCHANGE (0x1U << UARTx_CSR_IOSWAP_Pos)vUARTx_CSR_DMATXIFCFG_Pos 10yUARTx_CSR_DMATXIFCFG_Msk (0x1U << UARTx_CSR_DMATXIFCFG_Pos)}UARTx_CSR_BITORD_Pos 9UARTx_CSR_BITORD_Msk (0x1U << UARTx_CSR_BITORD_Pos)UARTx_CSR_BITORD_LSB (0x0U << UARTx_CSR_BITORD_Pos)UARTx_CSR_BITORD_MSB (0x1U << UARTx_CSR_BITORD_Pos)UARTx_CSR_STOPCFG_Pos 8UARTx_CSR_STOPCFG_Msk (0x1U << UARTx_CSR_STOPCFG_Pos)UARTx_CSR_STOPCFG_1STOPBIT (0x0U << UARTx_CSR_STOPCFG_Pos)UARTx_CSR_STOPCFG_2STOPBIT (0x1U << UARTx_CSR_STOPCFG_Pos)UARTx_CSR_PDSEL_Pos 6UARTx_CSR_PDSEL_Msk (0x3U << UARTx_CSR_PDSEL_Pos)UARTx_CSR_PDSEL_7BIT (0x0U << UARTx_CSR_PDSEL_Pos)UARTx_CSR_PDSEL_8BIT (0x1U << UARTx_CSR_PDSEL_Pos)UARTx_CSR_PDSEL_9BIT (0x2U << UARTx_CSR_PDSEL_Pos)UARTx_CSR_PDSEL_6BIT (0x3U << UARTx_CSR_PDSEL_Pos)UARTx_CSR_PARITY_Pos 4UARTx_CSR_PARITY_Msk (0x3U << UARTx_CSR_PARITY_Pos)UARTx_CSR_PARITY_NONE (0x0U << UARTx_CSR_PARITY_Pos)UARTx_CSR_PARITY_EVEN (0x1U << UARTx_CSR_PARITY_Pos)UARTx_CSR_PARITY_ODD (0x2U << UARTx_CSR_PARITY_Pos) UARTx_CSR_RXPOL_Pos 3£UARTx_CSR_RXPOL_Msk (0x1U << UARTx_CSR_RXPOL_Pos)¤UARTx_CSR_RXPOL_POSITIVE (0x0U << UARTx_CSR_RXPOL_Pos)¥UARTx_CSR_RXPOL_NEGTIVE (0x1U << UARTx_CSR_RXPOL_Pos)§UARTx_CSR_TXPOL_Pos 2ªUARTx_CSR_TXPOL_Msk (0x1U << UARTx_CSR_TXPOL_Pos)«UARTx_CSR_TXPOL_POSITIVE (0x0U << UARTx_CSR_TXPOL_Pos)¬UARTx_CSR_TXPOL_NEGTIVE (0x1U << UARTx_CSR_TXPOL_Pos)®UARTx_CSR_RXEN_Pos 1¯UARTx_CSR_RXEN_Msk (0x1U << UARTx_CSR_RXEN_Pos)°UARTx_CSR_RXEN_DISBALE (0x0U << UARTx_CSR_RXEN_Pos)±UARTx_CSR_RXEN_ENABLE (0x1U << UARTx_CSR_RXEN_Pos)³UARTx_CSR_TXEN_Pos 0´UARTx_CSR_TXEN_Msk (0x1U << UARTx_CSR_TXEN_Pos)µUARTx_CSR_TXEN_DISBALE (0x0U << UARTx_CSR_TXEN_Pos)¶UARTx_CSR_TXEN_ENABLE (0x1U << UARTx_CSR_TXEN_Pos)¸UARTx_IER_RXTO_IE_Pos 11ºUARTx_IER_RXTO_IE_Msk (0x1U << UARTx_IER_RXTO_IE_Pos)¼UARTx_IER_RXERR_IE_Pos 10½UARTx_IER_RXERR_IE_Msk (0x1U << UARTx_IER_RXERR_IE_Pos)¿UARTx_IER_RXBF_IE_Pos 8ÀUARTx_IER_RXBF_IE_Msk (0x1U << UARTx_IER_RXBF_IE_Pos)ÂUARTx_IER_NEWUP_IE_Pos 7ÃUARTx_IER_NEWUP_IE_Msk (0x1U << UARTx_IER_NEWUP_IE_Pos)ÅUARTx_IER_TXBE_IE_Pos 1ÆUARTx_IER_TXBE_IE_Msk (0x1U << UARTx_IER_TXBE_IE_Pos)ÈUARTx_IER_TXSE_IE_Pos 0ÉUARTx_IER_TXSE_IE_Msk (0x1U << UARTx_IER_TXSE_IE_Pos)ËUARTx_ISR_PERR_Pos 18ÌUARTx_ISR_PERR_Msk (0x1U << UARTx_ISR_PERR_Pos)ÎUARTx_ISR_FERR_Pos 17ÏUARTx_ISR_FERR_Msk (0x1U << UARTx_ISR_FERR_Pos)ÑUARTx_ISR_OERR_Pos 16ÓUARTx_ISR_OERR_Msk (0x1U << UARTx_ISR_OERR_Pos)ÕUARTx_ISR_RXTO_Pos 11×UARTx_ISR_RXTO_Msk (0x1U << UARTx_ISR_RXTO_Pos)ÙUARTx_ISR_RXBF_Pos 8ÚUARTx_ISR_RXBF_Msk (0x1U << UARTx_ISR_RXBF_Pos)ÜUARTx_ISR_TXBE_Pos 1ÝUARTx_ISR_TXBE_Msk (0x1U << UARTx_ISR_TXBE_Pos)ßUARTx_ISR_TXSE_Pos 0àUARTx_ISR_TXSE_Msk (0x1U << UARTx_ISR_TXSE_Pos)âUARTx_TODR_TXDLY_LEN_Pos 8ãUARTx_TODR_TXDLY_LEN_Msk (0xffU << UARTx_TODR_TXDLY_LEN_Pos)åUARTx_TODR_RXTO_LEN_Pos 0æUARTx_TODR_RXTO_LEN_Msk (0xffU << UARTx_TODR_RXTO_LEN_Pos)èUARTx_RXBUF_RXBUF_Pos 0éUARTx_RXBUF_RXBUF_Msk (0x1ffU << UARTx_RXBUF_RXBUF_Pos)ëUARTx_TXBUF_TXBUF_Pos 0ìUARTx_TXBUF_TXBUF_Msk (0x1ffU << UARTx_TXBUF_TXBUF_Pos)îUARTx_BRG_SPBRG_Pos 0ïUARTx_BRG_SPBRG_Msk (0xffffU << UARTx_BRG_SPBRG_Pos)ti ..\Drivers\..\Core\Include\fm33a0xxev_uart.hFM33A0XXEV.hfm33a0xxev_CMU.h
..\Drivers\fm33a0xxev_uart.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMÕRxIntTxIntPUART_IntTypeDef¾¢Seven7BitEight8BitNine9BitSix6BitPUART_DataBitTypeDefì%ÙNONEEVENODDPUART_ParityBitTypeDef=,OneBitTwoBitPUART_StopBitTypeDefv2*BaudRatef#DataBit"#ParityBitY#StopBit#ClockSrcf#PUART_SInitTypeDefª;*þRXBF_IE#TXBE_IE#TXSE_IE#SPBRGf#PDSELf#PARITYf#RXTO_IE#ERRIE#RXEN#STOPSELf#TXEN#IREN#RXDFLAG#TXDFLAG#PUART_InitTypeDefMÍÎÏ__FM33A0XXEV_LPTIM_H LPTIM_CFGR_ETR_AFEN_Pos 24LPTIM_CFGR_ETR_AFEN_Msk (0x1U << LPTIM_CFGR_ETR_AFEN_Pos) LPTIM_CFGR_PSCSEL_Pos 14#LPTIM_CFGR_PSCSEL_Msk (0x1U << LPTIM_CFGR_PSCSEL_Pos)$LPTIM_CFGR_PSCSEL_CLKSEL (0x0U << LPTIM_CFGR_PSCSEL_Pos)%LPTIM_CFGR_PSCSEL_LPTETRF (0x1U << LPTIM_CFGR_PSCSEL_Pos)'LPTIM_CFGR_DIVSEL_Pos 100LPTIM_CFGR_DIVSEL_Msk (0x7U << LPTIM_CFGR_DIVSEL_Pos)1LPTIM_CFGR_DIVSEL_DIV1 (0x0U << LPTIM_CFGR_DIVSEL_Pos)2LPTIM_CFGR_DIVSEL_DIV2 (0x1U << LPTIM_CFGR_DIVSEL_Pos)3LPTIM_CFGR_DIVSEL_DIV4 (0x2U << LPTIM_CFGR_DIVSEL_Pos)4LPTIM_CFGR_DIVSEL_DIV8 (0x3U << LPTIM_CFGR_DIVSEL_Pos)5LPTIM_CFGR_DIVSEL_DIV16 (0x4U << LPTIM_CFGR_DIVSEL_Pos)6LPTIM_CFGR_DIVSEL_DIV32 (0x5U << LPTIM_CFGR_DIVSEL_Pos)7LPTIM_CFGR_DIVSEL_DIV64 (0x6U << LPTIM_CFGR_DIVSEL_Pos)8LPTIM_CFGR_DIVSEL_DIV128 (0x7U << LPTIM_CFGR_DIVSEL_Pos):LPTIM_CFGR_EDGESEL_Pos 7=LPTIM_CFGR_EDGESEL_Msk (0x1U << LPTIM_CFGR_EDGESEL_Pos)>LPTIM_CFGR_EDGESEL_RISING (0x0U << LPTIM_CFGR_EDGESEL_Pos)?LPTIM_CFGR_EDGESEL_FALLING (0x1U << LPTIM_CFGR_EDGESEL_Pos)ALPTIM_CFGR_TRIGCFG_Pos 5ELPTIM_CFGR_TRIGCFG_Msk (0x3U << LPTIM_CFGR_TRIGCFG_Pos)FLPTIM_CFGR_TRIGCFG_RISING (0x0U << LPTIM_CFGR_TRIGCFG_Pos)GLPTIM_CFGR_TRIGCFG_FALLING (0x1U << LPTIM_CFGR_TRIGCFG_Pos)HLPTIM_CFGR_TRIGCFG_EXTERNAL (0x2U << LPTIM_CFGR_TRIGCFG_Pos)JLPTIM_CFGR_ONST_Pos 2MLPTIM_CFGR_ONST_Msk (0x1U << LPTIM_CFGR_ONST_Pos)NLPTIM_CFGR_ONST_CONTINUE (0x0U << LPTIM_CFGR_ONST_Pos)OLPTIM_CFGR_ONST_SINGLE (0x1U << LPTIM_CFGR_ONST_Pos)QLPTIM_CFGR_TMODE_Pos 0VLPTIM_CFGR_TMODE_Msk (0x3U << LPTIM_CFGR_TMODE_Pos)WLPTIM_CFGR_TMODE_COUNTER (0x0U << LPTIM_CFGR_TMODE_Pos)XLPTIM_CFGR_TMODE_PULSE (0x1U << LPTIM_CFGR_TMODE_Pos)YLPTIM_CFGR_TMODE_ASY (0x2U << LPTIM_CFGR_TMODE_Pos)ZLPTIM_CFGR_TMODE_TIMEOUT (0x3U << LPTIM_CFGR_TMODE_Pos)\LPTIM_CNTR_CNT32_Pos 0]LPTIM_CNTR_CNT32_Msk (0xffffffffU << LPTIM_CNTR_CNT32_Pos)_LPTIM_CCSR_CAP1SSEL_Pos 24dLPTIM_CCSR_CAP1SSEL_Msk (0x3U << LPTIM_CCSR_CAP1SSEL_Pos)eLPTIM_CCSR_CAP1SSEL_LPT_CH1 (0x0U << LPTIM_CCSR_CAP1SSEL_Pos)fLPTIM_CCSR_CAP1SSEL_XTLF (0x1U << LPTIM_CCSR_CAP1SSEL_Pos)gLPTIM_CCSR_CAP1SSEL_RCLP (0x2U << LPTIM_CCSR_CAP1SSEL_Pos)hLPTIM_CCSR_CAP1SSEL_RCMF (0x3U << LPTIM_CCSR_CAP1SSEL_Pos)jLPTIM_CCSR_CAP4EDGE_Pos 23mLPTIM_CCSR_CAP4EDGE_Msk (0x1U << LPTIM_CCSR_CAP4EDGE_Pos)nLPTIM_CCSR_CAP4EDGE_RISING (0x0U << LPTIM_CCSR_CAP4EDGE_Pos)oLPTIM_CCSR_CAP4EDGE_FALLING (0x1U << LPTIM_CCSR_CAP4EDGE_Pos)qLPTIM_CCSR_CAP3EDGE_Pos 22rLPTIM_CCSR_CAP3EDGE_Msk (0x1U << LPTIM_CCSR_CAP3EDGE_Pos)sLPTIM_CCSR_CAP3EDGE_RISING (0x0U << LPTIM_CCSR_CAP3EDGE_Pos)tLPTIM_CCSR_CAP3EDGE_FALLING (0x1U << LPTIM_CCSR_CAP3EDGE_Pos)vLPTIM_CCSR_CAP2EDGE_Pos 21wLPTIM_CCSR_CAP2EDGE_Msk (0x1U << LPTIM_CCSR_CAP2EDGE_Pos)xLPTIM_CCSR_CAP2EDGE_RISING (0x0U << LPTIM_CCSR_CAP2EDGE_Pos)yLPTIM_CCSR_CAP2EDGE_FALLING (0x1U << LPTIM_CCSR_CAP2EDGE_Pos){LPTIM_CCSR_CAP1EDGE_Pos 20|LPTIM_CCSR_CAP1EDGE_Msk (0x1U << LPTIM_CCSR_CAP1EDGE_Pos)}LPTIM_CCSR_CAP1EDGE_RISING (0x0U << LPTIM_CCSR_CAP1EDGE_Pos)~LPTIM_CCSR_CAP1EDGE_FALLING (0x1U << LPTIM_CCSR_CAP1EDGE_Pos)LPTIM_CCSR_POLAR4_Pos 19LPTIM_CCSR_POLAR4_Msk (0x1U << LPTIM_CCSR_POLAR4_Pos)LPTIM_CCSR_POLAR4_POS (0x0U << LPTIM_CCSR_POLAR4_Pos)LPTIM_CCSR_POLAR4_NEG (0x1U << LPTIM_CCSR_POLAR4_Pos)LPTIM_CCSR_POLAR3_Pos 18LPTIM_CCSR_POLAR3_Msk (0x1U << LPTIM_CCSR_POLAR3_Pos)LPTIM_CCSR_POLAR3_POS (0x0U << LPTIM_CCSR_POLAR3_Pos)LPTIM_CCSR_POLAR3_NEG (0x1U << LPTIM_CCSR_POLAR3_Pos)LPTIM_CCSR_POLAR2_Pos 17LPTIM_CCSR_POLAR2_Msk (0x1U << LPTIM_CCSR_POLAR2_Pos)LPTIM_CCSR_POLAR2_POS (0x0U << LPTIM_CCSR_POLAR2_Pos)LPTIM_CCSR_POLAR2_NEG (0x1U << LPTIM_CCSR_POLAR2_Pos)LPTIM_CCSR_POLAR1_Pos 16LPTIM_CCSR_POLAR1_Msk (0x1U << LPTIM_CCSR_POLAR1_Pos)LPTIM_CCSR_POLAR1_POS (0x0U << LPTIM_CCSR_POLAR1_Pos)LPTIM_CCSR_POLAR1_NEG (0x1U << LPTIM_CCSR_POLAR1_Pos)LPTIM_CCSR_CAPCFG4_Pos 14LPTIM_CCSR_CAPCFG4_Msk (0x3U << LPTIM_CCSR_CAPCFG4_Pos)LPTIM_CCSR_CAPCFG4_RISING (0x0U << LPTIM_CCSR_CAPCFG4_Pos)LPTIM_CCSR_CAPCFG4_FALLING (0x1U << LPTIM_CCSR_CAPCFG4_Pos)LPTIM_CCSR_CAPCFG4_BOTH (0x2U << LPTIM_CCSR_CAPCFG4_Pos) LPTIM_CCSR_CAPCFG3_Pos 12¡LPTIM_CCSR_CAPCFG3_Msk (0x3U << LPTIM_CCSR_CAPCFG3_Pos)¢LPTIM_CCSR_CAPCFG3_RISING (0x0U << LPTIM_CCSR_CAPCFG3_Pos)£LPTIM_CCSR_CAPCFG3_FALLING (0x1U << LPTIM_CCSR_CAPCFG3_Pos)¤LPTIM_CCSR_CAPCFG3_BOTH (0x2U << LPTIM_CCSR_CAPCFG3_Pos)¦LPTIM_CCSR_CAPCFG2_Pos 10§LPTIM_CCSR_CAPCFG2_Msk (0x3U << LPTIM_CCSR_CAPCFG2_Pos)¨LPTIM_CCSR_CAPCFG2_RISING (0x0U << LPTIM_CCSR_CAPCFG2_Pos)©LPTIM_CCSR_CAPCFG2_FALLING (0x1U << LPTIM_CCSR_CAPCFG2_Pos)ªLPTIM_CCSR_CAPCFG2_BOTH (0x2U << LPTIM_CCSR_CAPCFG2_Pos)¬LPTIM_CCSR_CAPCFG1_Pos 8LPTIM_CCSR_CAPCFG1_Msk (0x3U << LPTIM_CCSR_CAPCFG1_Pos)®LPTIM_CCSR_CAPCFG1_RISING (0x0U << LPTIM_CCSR_CAPCFG1_Pos)¯LPTIM_CCSR_CAPCFG1_FALLING (0x1U << LPTIM_CCSR_CAPCFG1_Pos)°LPTIM_CCSR_CAPCFG1_BOTH (0x2U << LPTIM_CCSR_CAPCFG1_Pos)²LPTIM_CCSR_CC4S_Pos 6¶LPTIM_CCSR_CC4S_Msk (0x3U << LPTIM_CCSR_CC4S_Pos)·LPTIM_CCSR_CC4S_NON (0x0U << LPTIM_CCSR_CC4S_Pos)¸LPTIM_CCSR_CC4S_LPT_CH4_IN (0x1U << LPTIM_CCSR_CC4S_Pos)¹LPTIM_CCSR_CC4S_LPT_CH4_OUT (0x2U << LPTIM_CCSR_CC4S_Pos)»LPTIM_CCSR_CC3S_Pos 4¼LPTIM_CCSR_CC3S_Msk (0x3U << LPTIM_CCSR_CC3S_Pos)½LPTIM_CCSR_CC3S_NON (0x0U << LPTIM_CCSR_CC3S_Pos)¾LPTIM_CCSR_CC3S_LPT_CH3_IN (0x1U << LPTIM_CCSR_CC3S_Pos)¿LPTIM_CCSR_CC3S_LPT_CH3_OUT (0x2U << LPTIM_CCSR_CC3S_Pos)ÁLPTIM_CCSR_CC2S_Pos 2ÂLPTIM_CCSR_CC2S_Msk (0x3U << LPTIM_CCSR_CC2S_Pos)ÃLPTIM_CCSR_CC2S_NON (0x0U << LPTIM_CCSR_CC2S_Pos)ÄLPTIM_CCSR_CC2S_LPT_CH2_IN (0x1U << LPTIM_CCSR_CC2S_Pos)ÅLPTIM_CCSR_CC2S_LPT_CH2_OUT (0x2U << LPTIM_CCSR_CC2S_Pos)ÇLPTIM_CCSR_CC1S_Pos 0ÈLPTIM_CCSR_CC1S_Msk (0x3U << LPTIM_CCSR_CC1S_Pos)ÉLPTIM_CCSR_CC1S_NON (0x0U << LPTIM_CCSR_CC1S_Pos)ÊLPTIM_CCSR_CC1S_LPT_CH1_IN (0x1U << LPTIM_CCSR_CC1S_Pos)ËLPTIM_CCSR_CC1S_LPT_CH1_OUT (0x2U << LPTIM_CCSR_CC1S_Pos)ÍLPTIM_ARR_ARR_Pos 0ÏLPTIM_ARR_ARR_Msk (0xffffffffU << LPTIM_ARR_ARR_Pos)ÑLPTIM_IER_OVR4IE_Pos 11ÔLPTIM_IER_OVR4IE_Msk (0x1U << LPTIM_IER_OVR4IE_Pos)ØLPTIM_IER_OVR3IE_Pos 10ÛLPTIM_IER_OVR3IE_Msk (0x1U << LPTIM_IER_OVR3IE_Pos)ßLPTIM_IER_OVR2IE_Pos 9âLPTIM_IER_OVR2IE_Msk (0x1U << LPTIM_IER_OVR2IE_Pos)æLPTIM_IER_OVR1IE_Pos 8éLPTIM_IER_OVR1IE_Msk (0x1U << LPTIM_IER_OVR1IE_Pos)íLPTIM_IER_TRIGIE_Pos 7ðLPTIM_IER_TRIGIE_Msk (0x1U << LPTIM_IER_TRIGIE_Pos)ôLPTIM_IER_OVIE_Pos 6÷LPTIM_IER_OVIE_Msk (0x1U << LPTIM_IER_OVIE_Pos)ûLPTIM_IER_CC4IE_Pos 3þLPTIM_IER_CC4IE_Msk (0x1U << LPTIM_IER_CC4IE_Pos)LPTIM_IER_CC3IE_Pos 2LPTIM_IER_CC3IE_Msk (0x1U << LPTIM_IER_CC3IE_Pos)LPTIM_IER_CC2IE_Pos 1LPTIM_IER_CC2IE_Msk (0x1U << LPTIM_IER_CC2IE_Pos)LPTIM_IER_CC1IE_Pos 0LPTIM_IER_CC1IE_Msk (0x1U << LPTIM_IER_CC1IE_Pos)LPTIM_ISR_CAP4OVR_Pos 11LPTIM_ISR_CAP4OVR_Msk (0x1U << LPTIM_ISR_CAP4OVR_Pos)LPTIM_ISR_CAP3OVR_Pos 10LPTIM_ISR_CAP3OVR_Msk (0x1U << LPTIM_ISR_CAP3OVR_Pos)LPTIM_ISR_CAP2OVR_Pos 9LPTIM_ISR_CAP2OVR_Msk (0x1U << LPTIM_ISR_CAP2OVR_Pos) LPTIM_ISR_CAP1OVR_Pos 8¡LPTIM_ISR_CAP1OVR_Msk (0x1U << LPTIM_ISR_CAP1OVR_Pos)£LPTIM_ISR_TRIGIF_Pos 7¤LPTIM_ISR_TRIGIF_Msk (0x1U << LPTIM_ISR_TRIGIF_Pos)¦LPTIM_ISR_OVIF_Pos 6§LPTIM_ISR_OVIF_Msk (0x1U << LPTIM_ISR_OVIF_Pos)©LPTIM_ISR_CC4IF_Pos 3ªLPTIM_ISR_CC4IF_Msk (0x1U << LPTIM_ISR_CC4IF_Pos)¬LPTIM_ISR_CC3IF_Pos 2LPTIM_ISR_CC3IF_Msk (0x1U << LPTIM_ISR_CC3IF_Pos)¯LPTIM_ISR_CC2IF_Pos 1°LPTIM_ISR_CC2IF_Msk (0x1U << LPTIM_ISR_CC2IF_Pos)²LPTIM_ISR_CC1IF_Pos 0³LPTIM_ISR_CC1IF_Msk (0x1U << LPTIM_ISR_CC1IF_Pos)µLPTIM_CR_EN_Pos 0¸LPTIM_CR_EN_Msk (0x1U << LPTIM_CR_EN_Pos)¼LPTIM_CCR1_CCR1_Pos 0½LPTIM_CCR1_CCR1_Msk (0xffffffffU << LPTIM_CCR1_CCR1_Pos)¿LPTIM_CCR2_CCR2_Pos 0ÀLPTIM_CCR2_CCR2_Msk (0xffffffffU << LPTIM_CCR2_CCR2_Pos)ÂLPTIM_CCR3_CCR3_Pos 0ÃLPTIM_CCR3_CCR3_Msk (0xffffffffU << LPTIM_CCR3_CCR3_Pos)ÅLPTIM_CCR4_CCR4_Pos 0ÆLPTIM_CCR4_CCR4_Msk (0xffffffffU << LPTIM_CCR4_CCR4_Pos)`V ..\Drivers\..\Core\Include\fm33a0xxev_lptim.hFM33A0XXEV.hÀ
..\Drivers\fm33a0xxev_lptim.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMÑÒÓ__FM33A0XXEV_WWDT_H WWDT_CR_CON_Pos 0WWDT_CR_CON_Msk (0xffU << WWDT_CR_CON_Pos)WWDT_CFGR_CFG_Pos 0&WWDT_CFGR_CFG_Msk (0x7U << WWDT_CFGR_CFG_Pos)(WWDT_CNTR_CNT_Pos 0)WWDT_CNTR_CNT_Msk (0x3ffU << WWDT_CNTR_CNT_Pos)+WWDT_IER_IE_Pos 0.WWDT_IER_IE_Msk (0x1U << WWDT_IER_IE_Pos)2WWDT_ISR_NOVF_Pos 06WWDT_ISR_NOVF_Msk (0x1U << WWDT_ISR_NOVF_Pos)8WWDT_PSCR_DIV_CNT_Pos 09WWDT_PSCR_DIV_CNT_Msk (0xfffU << WWDT_PSCR_DIV_CNT_Pos)`U ..\Drivers\..\Core\Include\fm33a0xxev_wwdt.hFM33A0XXEV.h¼
..\Drivers\fm33a0xxev_wwdt.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMÕÖ×__FM33A0XXEV_SVD_H %SVD_CFGR_LVL_Pos 4'SVD_CFGR_LVL_Msk (0xfU << SVD_CFGR_LVL_Pos)(SVD_CFGR_LVL_1P800V (0x0U << SVD_CFGR_LVL_Pos))SVD_CFGR_LVL_2P014V (0x1U << SVD_CFGR_LVL_Pos)*SVD_CFGR_LVL_2P229V (0x2U << SVD_CFGR_LVL_Pos)+SVD_CFGR_LVL_2P443V (0x3U << SVD_CFGR_LVL_Pos),SVD_CFGR_LVL_2P657V (0x4U << SVD_CFGR_LVL_Pos)-SVD_CFGR_LVL_2P871V (0x5U << SVD_CFGR_LVL_Pos).SVD_CFGR_LVL_3P086V (0x6U << SVD_CFGR_LVL_Pos)/SVD_CFGR_LVL_3P300V (0x7U << SVD_CFGR_LVL_Pos)0SVD_CFGR_LVL_3P514V (0x8U << SVD_CFGR_LVL_Pos)1SVD_CFGR_LVL_3P729V (0x9U << SVD_CFGR_LVL_Pos)2SVD_CFGR_LVL_3P943V (0xaU << SVD_CFGR_LVL_Pos)3SVD_CFGR_LVL_4P157V (0xbU << SVD_CFGR_LVL_Pos)4SVD_CFGR_LVL_4P371V (0xcU << SVD_CFGR_LVL_Pos)5SVD_CFGR_LVL_4P586V (0xdU << SVD_CFGR_LVL_Pos)6SVD_CFGR_LVL_4P800V (0xeU << SVD_CFGR_LVL_Pos)7SVD_CFGR_LVL_SVS (0xfU << SVD_CFGR_LVL_Pos)9SVD_CFGR_DFEN_Pos 3=SVD_CFGR_DFEN_Msk (0x1U << SVD_CFGR_DFEN_Pos)ASVD_CFGR_MOD_Pos 2FSVD_CFGR_MOD_Msk (0x1U << SVD_CFGR_MOD_Pos)GSVD_CFGR_MOD_INTERVAL (0x1U << SVD_CFGR_MOD_Pos)HSVD_CFGR_MOD_ALWAYSON (0x0U << SVD_CFGR_MOD_Pos)JSVD_CFGR_ITVL_Pos 0OSVD_CFGR_ITVL_Msk (0x3U << SVD_CFGR_ITVL_Pos)PSVD_CFGR_ITVL_62P5MS (0x0U << SVD_CFGR_ITVL_Pos)QSVD_CFGR_ITVL_256MS (0x1U << SVD_CFGR_ITVL_Pos)RSVD_CFGR_ITVL_1S (0x2U << SVD_CFGR_ITVL_Pos)SSVD_CFGR_ITVL_4S (0x3U << SVD_CFGR_ITVL_Pos)XSVD_CR_TE_Pos 8YSVD_CR_TE_Msk (0x1U << SVD_CR_TE_Pos)[SVD_CR_SVSEN_Pos 1`SVD_CR_SVSEN_Msk (0x1U << SVD_CR_SVSEN_Pos)dSVD_CR_SVDEN_Pos 0eSVD_CR_SVDEN_Msk (0x1U << SVD_CR_SVDEN_Pos)gSVD_IER_PFIE_Pos 1hSVD_IER_PFIE_Msk (0x1U << SVD_IER_PFIE_Pos)jSVD_IER_PRIE_Pos 0kSVD_IER_PRIE_Msk (0x1U << SVD_IER_PRIE_Pos)mSVD_ISR_SVDO_Pos 8pSVD_ISR_SVDO_Msk (0x1U << SVD_ISR_SVDO_Pos)rSVD_ISR_SVDR_Pos 7tSVD_ISR_SVDR_Msk (0x1U << SVD_ISR_SVDR_Pos)vSVD_ISR_PFF_Pos 1wSVD_ISR_PFF_Msk (0x1U << SVD_ISR_PFF_Pos)ySVD_ISR_PRF_Pos 0zSVD_ISR_PRF_Msk (0x1U << SVD_ISR_PRF_Pos)|SVD_VSR_V1P0EN_Pos 2SVD_VSR_V1P0EN_Msk (0x1U << SVD_VSR_V1P0EN_Pos)SVD_VSR_V0P95EN_Pos 1SVD_VSR_V0P95EN_Msk (0x1U << SVD_VSR_V0P95EN_Pos)SVD_VSR_V0P9EN_Pos 0SVD_VSR_V0P9EN_Msk (0x1U << SVD_VSR_V0P9EN_Pos)`T ..\Drivers\..\Core\Include\fm33a0xxev_svd.hFM33A0XXEV.hD
..\Drivers\fm33a0xxev_svd.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM*¬SVDMODf#SVDITVLf#SVDLVLf#DFEN#PFIE# PRIE#SVDEN#PSVD_InitTypeDef½#ÙÚÛ__FM33A0XXEV_PAE_H ECC_STD_DBL 0x00ECC_STD_ADD 0x01ECC_ALG1_DBLADD 0x02ECC_ALG2_ECDBL 0x03ECC_ALG2_ECADDDBL 0x04 ECC_ALG2_YRECOVER 0x05'PAE_CSR_DATA_TYPE_Pos 8-PAE_CSR_DATA_TYPE_Msk (0x3U << PAE_CSR_DATA_TYPE_Pos).PAE_CSR_DATA_TYPE_NONE (0x0U << PAE_CSR_DATA_TYPE_Pos)/PAE_CSR_DATA_TYPE_HALFWORD (0x1U << PAE_CSR_DATA_TYPE_Pos)0PAE_CSR_DATA_TYPE_BYTE (0x2U << PAE_CSR_DATA_TYPE_Pos)1PAE_CSR_DATA_TYPE_BIT (0x3U << PAE_CSR_DATA_TYPE_Pos)3PAE_CSR_START_Pos 74PAE_CSR_START_Msk (0x1U << PAE_CSR_START_Pos)6PAE_CSR_RUN_MODE_Pos 4;PAE_CSR_RUN_MODE_Msk (0x3U << PAE_CSR_RUN_MODE_Pos)<PAE_CSR_RUN_MODE_MOD (0x0U << PAE_CSR_RUN_MODE_Pos)=PAE_CSR_RUN_MODE_DOT (0x1U << PAE_CSR_RUN_MODE_Pos)>PAE_CSR_RUN_MODE_RSA (0x2U << PAE_CSR_RUN_MODE_Pos)?PAE_CSR_RUN_MODE_ECC (0x3U << PAE_CSR_RUN_MODE_Pos)APAE_CSR_SOFT_RST_Pos 3CPAE_CSR_SOFT_RST_Msk (0x1U << PAE_CSR_SOFT_RST_Pos)FPAE_CSR_PAEIE_Pos 2IPAE_CSR_PAEIE_Msk (0x1U << PAE_CSR_PAEIE_Pos)JPAE_CSR_PAEIE_ENABLE (0x1U << PAE_CSR_PAEIE_Pos)KPAE_CSR_PAEIE_DISABLE (0x0U << PAE_CSR_PAEIE_Pos)MPAE_CSR_PAEIF_Pos 1NPAE_CSR_PAEIF_Msk (0x1U << PAE_CSR_PAEIF_Pos)PPAE_CSR_BUSY_Pos 0SPAE_CSR_BUSY_Msk (0x1U << PAE_CSR_BUSY_Pos)UPAE_MLR_PAE_MLR_Pos 0YPAE_MLR_PAE_MLR_Msk (0x3fU << PAE_MLR_PAE_MLR_Pos)[PAE_MPR_PAE_MPR_Pos 0\PAE_MPR_PAE_MPR_Msk (0xffffffffU << PAE_MPR_PAE_MPR_Pos)^PAE_M0CFG_BLKCFG_Pos 15aPAE_M0CFG_BLKCFG_Msk (0x1U << PAE_M0CFG_BLKCFG_Pos)bPAE_M0CFG_BLKCFG_16BLOCK (0x1U << PAE_M0CFG_BLKCFG_Pos)cPAE_M0CFG_BLKCFG_4BLOCK (0x0U << PAE_M0CFG_BLKCFG_Pos)ePAE_M0CFG_INS_M0_Pos 12jPAE_M0CFG_INS_M0_Msk (0x3U << PAE_M0CFG_INS_M0_Pos)kPAE_M0CFG_INS_M0_MUL (0x0U << PAE_M0CFG_INS_M0_Pos)lPAE_M0CFG_INS_M0_ADD (0x1U << PAE_M0CFG_INS_M0_Pos)mPAE_M0CFG_INS_M0_SUB (0x3U << PAE_M0CFG_INS_M0_Pos)oPAE_M0CFG_RES_BLK_Pos 8rPAE_M0CFG_RES_BLK_Msk (0xfU << PAE_M0CFG_RES_BLK_Pos)sPAE_M0CFG_RES_BLK_BLOCK0 (0x0U << PAE_M0CFG_RES_BLK_Pos)tPAE_M0CFG_RES_BLK_BLOCK1 (0x1U << PAE_M0CFG_RES_BLK_Pos)uPAE_M0CFG_RES_BLK_BLOCK2 (0x2U << PAE_M0CFG_RES_BLK_Pos)vPAE_M0CFG_RES_BLK_BLOCK3 (0x3U << PAE_M0CFG_RES_BLK_Pos)wPAE_M0CFG_RES_BLK_BLOCK4 (0x4U << PAE_M0CFG_RES_BLK_Pos)xPAE_M0CFG_RES_BLK_BLOCK5 (0x5U << PAE_M0CFG_RES_BLK_Pos)yPAE_M0CFG_RES_BLK_BLOCK6 (0x6U << PAE_M0CFG_RES_BLK_Pos)zPAE_M0CFG_RES_BLK_BLOCK7 (0x7U << PAE_M0CFG_RES_BLK_Pos){PAE_M0CFG_RES_BLK_BLOCK8 (0x8U << PAE_M0CFG_RES_BLK_Pos)|PAE_M0CFG_RES_BLK_BLOCK9 (0x9U << PAE_M0CFG_RES_BLK_Pos)}PAE_M0CFG_RES_BLK_BLOCK10 (0xAU << PAE_M0CFG_RES_BLK_Pos)~PAE_M0CFG_RES_BLK_BLOCK11 (0xBU << PAE_M0CFG_RES_BLK_Pos)PAE_M0CFG_RES_BLK_BLOCK12 (0xCU << PAE_M0CFG_RES_BLK_Pos)PAE_M0CFG_RES_BLK_BLOCK13 (0xDU << PAE_M0CFG_RES_BLK_Pos)PAE_M0CFG_RES_BLK_BLOCK14 (0xEU << PAE_M0CFG_RES_BLK_Pos)PAE_M0CFG_RES_BLK_BLOCK15 (0xFU << PAE_M0CFG_RES_BLK_Pos)PAE_M0CFG_OP1_BLK_Pos 4PAE_M0CFG_OP1_BLK_Msk (0xfU << PAE_M0CFG_OP1_BLK_Pos)PAE_M0CFG_OP1_BLK_BLOCK0 (0x0U << PAE_M0CFG_OP1_BLK_Pos)PAE_M0CFG_OP1_BLK_BLOCK1 (0x1U << PAE_M0CFG_OP1_BLK_Pos)PAE_M0CFG_OP1_BLK_BLOCK2 (0x2U << PAE_M0CFG_OP1_BLK_Pos)PAE_M0CFG_OP1_BLK_BLOCK3 (0x3U << PAE_M0CFG_OP1_BLK_Pos)PAE_M0CFG_OP1_BLK_BLOCK4 (0x4U << PAE_M0CFG_OP1_BLK_Pos)PAE_M0CFG_OP1_BLK_BLOCK5 (0x5U << PAE_M0CFG_OP1_BLK_Pos)PAE_M0CFG_OP1_BLK_BLOCK6 (0x6U << PAE_M0CFG_OP1_BLK_Pos)PAE_M0CFG_OP1_BLK_BLOCK7 (0x7U << PAE_M0CFG_OP1_BLK_Pos)PAE_M0CFG_OP1_BLK_BLOCK8 (0x8U << PAE_M0CFG_OP1_BLK_Pos)PAE_M0CFG_OP1_BLK_BLOCK9 (0x9U << PAE_M0CFG_OP1_BLK_Pos)PAE_M0CFG_OP1_BLK_BLOCK10 (0xAU << PAE_M0CFG_OP1_BLK_Pos)PAE_M0CFG_OP1_BLK_BLOCK11 (0xBU << PAE_M0CFG_OP1_BLK_Pos)PAE_M0CFG_OP1_BLK_BLOCK12 (0xCU << PAE_M0CFG_OP1_BLK_Pos)PAE_M0CFG_OP1_BLK_BLOCK13 (0xDU << PAE_M0CFG_OP1_BLK_Pos)PAE_M0CFG_OP1_BLK_BLOCK14 (0xEU << PAE_M0CFG_OP1_BLK_Pos)PAE_M0CFG_OP1_BLK_BLOCK15 (0xFU << PAE_M0CFG_OP1_BLK_Pos)¡PAE_M0CFG_OP2_BLK_Pos 0¤PAE_M0CFG_OP2_BLK_Msk (0xfU << PAE_M0CFG_OP2_BLK_Pos)¥PAE_M0CFG_OP2_BLK_BLOCK0 (0x0U << PAE_M0CFG_OP2_BLK_Pos)¦PAE_M0CFG_OP2_BLK_BLOCK1 (0x1U << PAE_M0CFG_OP2_BLK_Pos)§PAE_M0CFG_OP2_BLK_BLOCK2 (0x2U << PAE_M0CFG_OP2_BLK_Pos)¨PAE_M0CFG_OP2_BLK_BLOCK3 (0x3U << PAE_M0CFG_OP2_BLK_Pos)©PAE_M0CFG_OP2_BLK_BLOCK4 (0x4U << PAE_M0CFG_OP2_BLK_Pos)ªPAE_M0CFG_OP2_BLK_BLOCK5 (0x5U << PAE_M0CFG_OP2_BLK_Pos)«PAE_M0CFG_OP2_BLK_BLOCK6 (0x6U << PAE_M0CFG_OP2_BLK_Pos)¬PAE_M0CFG_OP2_BLK_BLOCK7 (0x7U << PAE_M0CFG_OP2_BLK_Pos)PAE_M0CFG_OP2_BLK_BLOCK8 (0x8U << PAE_M0CFG_OP2_BLK_Pos)®PAE_M0CFG_OP2_BLK_BLOCK9 (0x9U << PAE_M0CFG_OP2_BLK_Pos)¯PAE_M0CFG_OP2_BLK_BLOCK10 (0xAU << PAE_M0CFG_OP2_BLK_Pos)°PAE_M0CFG_OP2_BLK_BLOCK11 (0xBU << PAE_M0CFG_OP2_BLK_Pos)±PAE_M0CFG_OP2_BLK_BLOCK12 (0xCU << PAE_M0CFG_OP2_BLK_Pos)²PAE_M0CFG_OP2_BLK_BLOCK13 (0xDU << PAE_M0CFG_OP2_BLK_Pos)³PAE_M0CFG_OP2_BLK_BLOCK14 (0xEU << PAE_M0CFG_OP2_BLK_Pos)´PAE_M0CFG_OP2_BLK_BLOCK15 (0xFU << PAE_M0CFG_OP2_BLK_Pos)·PAE_M1CFG_INS_M1_Pos 4ÀPAE_M1CFG_INS_M1_Msk (0x7U << PAE_M1CFG_INS_M1_Pos)ÁPAE_M1CFG_INS_M1_JACOBIN (0x0U << PAE_M1CFG_INS_M1_Pos)ÂPAE_M1CFG_INS_M1_MIXADD (0x1U << PAE_M1CFG_INS_M1_Pos)ÃPAE_M1CFG_INS_M1_ECDBL (0x3U << PAE_M1CFG_INS_M1_Pos)ÄPAE_M1CFG_INS_M1_ECADDDBL (0x4U << PAE_M1CFG_INS_M1_Pos)ÅPAE_M1CFG_INS_M1_ECYRECOVER (0x5U << PAE_M1CFG_INS_M1_Pos)ÇPAE_M1CFG_AEN3_M1_Pos 1ÊPAE_M1CFG_AEN3_M1_Msk (0x1U << PAE_M1CFG_AEN3_M1_Pos)ËPAE_M1CFG_AEN3_M1_NE3 (0x1U << PAE_M1CFG_AEN3_M1_Pos)ÌPAE_M1CFG_AEN3_M1_EQ3 (0x0U << PAE_M1CFG_AEN3_M1_Pos)ÎPAE_M1CFG_BIT_VALUE_M1_Pos 0ÑPAE_M1CFG_BIT_VALUE_M1_Msk (0x1U << PAE_M1CFG_BIT_VALUE_M1_Pos)ÒPAE_M1CFG_BIT_VALUE_M1_VALUE1 (0x1U << PAE_M1CFG_BIT_VALUE_M1_Pos)ÓPAE_M1CFG_BIT_VALUE_M1_VALUE0 (0x0U << PAE_M1CFG_BIT_VALUE_M1_Pos)ÕPAE_M2CFG_ALWAYS_MULT_Pos 4ØPAE_M2CFG_ALWAYS_MULT_Msk (0x1U << PAE_M2CFG_ALWAYS_MULT_Pos)ÙPAE_M2CFG_ALWAYS_MULT_ALWAYS (0x1U << PAE_M2CFG_ALWAYS_MULT_Pos)ÚPAE_M2CFG_ALWAYS_MULT_NONE (0x0U << PAE_M2CFG_ALWAYS_MULT_Pos)ÜPAE_M2CFG_FBO_M2_Pos 0ßPAE_M2CFG_FBO_M2_Msk (0x1U << PAE_M2CFG_FBO_M2_Pos)àPAE_M2CFG_FBO_M2_FB1 (0x1U << PAE_M2CFG_FBO_M2_Pos)áPAE_M2CFG_FBO_M2_NFB1 (0x0U << PAE_M2CFG_FBO_M2_Pos)ãPAE_M3CFG_AEN3_M3_Pos 4æPAE_M3CFG_AEN3_M3_Msk (0x1U << PAE_M3CFG_AEN3_M3_Pos)çPAE_M3CFG_AEN3_M3_EQ3 (0x1U << PAE_M3CFG_AEN3_M3_Pos)èPAE_M3CFG_AEN3_M3_NE3 (0x0U << PAE_M3CFG_AEN3_M3_Pos)êPAE_M3CFG_FBO_M3_Pos 0íPAE_M3CFG_FBO_M3_Msk (0x1U << PAE_M3CFG_FBO_M3_Pos)îPAE_M3CFG_FBO_M3_FB1 (0x1U << PAE_M3CFG_FBO_M3_Pos)ïPAE_M3CFG_FBO_M3_NFB1 (0x0U << PAE_M3CFG_FBO_M3_Pos)ñPAE_WORD_PAE_WORD_Pos 0òPAE_WORD_PAE_WORD_Msk (0xffffffffU << PAE_WORD_PAE_WORD_Pos)`T ..\Drivers\..\Core\Include\fm33a0xxev_pae.hFM33A0XXEV.h¼
..\Drivers\fm33a0xxev_pae.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMÝÞß__FM33A0XXEV_HASH_H HASH_CSR_START_Pos 7HASH_CSR_START_Msk (0x1U << HASH_CSR_START_Pos)HASH_CSR_BUSY_Pos 6HASH_CSR_BUSY_Msk (0x1U << HASH_CSR_BUSY_Pos)HASH_CSR_HASHSEL_Pos 1 HASH_CSR_HASHSEL_Msk (0x1U << HASH_CSR_HASHSEL_Pos)!HASH_CSR_HASHSEL_SHA256 (0x0U << HASH_CSR_HASHSEL_Pos)"HASH_CSR_HASHSEL_SHA1 (0x1U << HASH_CSR_HASHSEL_Pos)$HASH_DTR_DATA_TYPE_Pos 0+HASH_DTR_DATA_TYPE_Msk (0x3U << HASH_DTR_DATA_TYPE_Pos),HASH_DTR_DATA_TYPE_NONE (0x0U << HASH_DTR_DATA_TYPE_Pos)-HASH_DTR_DATA_TYPE_HALFWORD (0x1U << HASH_DTR_DATA_TYPE_Pos).HASH_DTR_DATA_TYPE_BYTE (0x2U << HASH_DTR_DATA_TYPE_Pos)/HASH_DTR_DATA_TYPE_BIT (0x3U << HASH_DTR_DATA_TYPE_Pos)`U ..\Drivers\..\Core\Include\fm33a0xxev_hash.hFM33A0XXEV.h¼
..\Drivers\fm33a0xxev_hash.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMáâã__FM33A0XXEV_QSPI_H )QSPI_CR_PRESCALER_Pos 24*QSPI_CR_PRESCALER_Msk (0xffU << QSPI_CR_PRESCALER_Pos),QSPI_CR_PMM_Pos 23/QSPI_CR_PMM_Msk (0x1U << QSPI_CR_PMM_Pos)0QSPI_CR_PMM_AND (0x0U << QSPI_CR_PMM_Pos)1QSPI_CR_PMM_OR (0x1U << QSPI_CR_PMM_Pos)3QSPI_CR_TOIE_Pos 206QSPI_CR_TOIE_Msk (0x1U << QSPI_CR_TOIE_Pos):QSPI_CR_SMIE_Pos 19=QSPI_CR_SMIE_Msk (0x1U << QSPI_CR_SMIE_Pos)AQSPI_CR_FTIE_Pos 18DQSPI_CR_FTIE_Msk (0x1U << QSPI_CR_FTIE_Pos)HQSPI_CR_TCIE_Pos 17KQSPI_CR_TCIE_Msk (0x1U << QSPI_CR_TCIE_Pos)OQSPI_CR_TEIE_Pos 16RQSPI_CR_TEIE_Msk (0x1U << QSPI_CR_TEIE_Pos)VQSPI_CR_FIFOTHR_Pos 8aQSPI_CR_FIFOTHR_Msk (0xfU << QSPI_CR_FIFOTHR_Pos)bQSPI_CR_FIFOTHR_1 (0x0U << QSPI_CR_FIFOTHR_Pos)cQSPI_CR_FIFOTHR_2 (0x1U << QSPI_CR_FIFOTHR_Pos)dQSPI_CR_FIFOTHR_3 (0x2U << QSPI_CR_FIFOTHR_Pos)eQSPI_CR_FIFOTHR_4 (0x3U << QSPI_CR_FIFOTHR_Pos)fQSPI_CR_FIFOTHR_5 (0x4U << QSPI_CR_FIFOTHR_Pos)gQSPI_CR_FIFOTHR_6 (0x5U << QSPI_CR_FIFOTHR_Pos)hQSPI_CR_FIFOTHR_7 (0x6U << QSPI_CR_FIFOTHR_Pos)iQSPI_CR_FIFOTHR_8 (0x7U << QSPI_CR_FIFOTHR_Pos)jQSPI_CR_FIFOTHR_9 (0x8U << QSPI_CR_FIFOTHR_Pos)kQSPI_CR_FIFOTHR_10 (0x9U << QSPI_CR_FIFOTHR_Pos)lQSPI_CR_FIFOTHR_11 (0x10U << QSPI_CR_FIFOTHR_Pos)mQSPI_CR_FIFOTHR_12 (0x11U << QSPI_CR_FIFOTHR_Pos)nQSPI_CR_FIFOTHR_13 (0x12U << QSPI_CR_FIFOTHR_Pos)oQSPI_CR_FIFOTHR_14 (0x13U << QSPI_CR_FIFOTHR_Pos)pQSPI_CR_FIFOTHR_15 (0x14U << QSPI_CR_FIFOTHR_Pos)qQSPI_CR_FIFOTHR_16 (0x15U << QSPI_CR_FIFOTHR_Pos)sQSPI_CR_SSHFT_Pos 4vQSPI_CR_SSHFT_Msk (0x1U << QSPI_CR_SSHFT_Pos)zQSPI_CR_TCEN_Pos 3~QSPI_CR_TCEN_Msk (0x1U << QSPI_CR_TCEN_Pos)QSPI_CR_DMAEN_Pos 2QSPI_CR_DMAEN_Msk (0x1U << QSPI_CR_DMAEN_Pos)QSPI_CR_ABORT_Pos 1QSPI_CR_ABORT_Msk (0x1U << QSPI_CR_ABORT_Pos)QSPI_CR_EN_Pos 0QSPI_CR_EN_Msk (0x1U << QSPI_CR_EN_Pos)QSPI_CFG_CSHT_Pos 8QSPI_CFG_CSHT_Msk (0x7U << QSPI_CFG_CSHT_Pos)QSPI_CFG_CSHT_1CYCLE (0x0U << QSPI_CFG_CSHT_Pos)QSPI_CFG_CSHT_2CYCLES (0x1U << QSPI_CFG_CSHT_Pos)QSPI_CFG_CSHT_3CYCLES (0x2U << QSPI_CFG_CSHT_Pos)QSPI_CFG_CSHT_4CYCLES (0x3U << QSPI_CFG_CSHT_Pos)QSPI_CFG_CSHT_5CYCLES (0x4U << QSPI_CFG_CSHT_Pos)QSPI_CFG_CSHT_6CYCLES (0x5U << QSPI_CFG_CSHT_Pos)QSPI_CFG_CSHT_7CYCLES (0x6U << QSPI_CFG_CSHT_Pos) QSPI_CFG_CSHT_8CYCLES (0x7U << QSPI_CFG_CSHT_Pos)¢QSPI_CFG_CKMODE_Pos 0¥QSPI_CFG_CKMODE_Msk (0x1U << QSPI_CFG_CKMODE_Pos)¦QSPI_CFG_CKMODE_MODE0 (0x0U << QSPI_CFG_CKMODE_Pos)§QSPI_CFG_CKMODE_MODE3 (0x1U << QSPI_CFG_CKMODE_Pos)©QSPI_SR_FIFOLVL_Pos 8¬QSPI_SR_FIFOLVL_Msk (0x1fU << QSPI_SR_FIFOLVL_Pos)®QSPI_SR_BUSY_Pos 5¯QSPI_SR_BUSY_Msk (0x1U << QSPI_SR_BUSY_Pos)±QSPI_SR_TOF_Pos 4²QSPI_SR_TOF_Msk (0x1U << QSPI_SR_TOF_Pos)´QSPI_SR_SMF_Pos 3µQSPI_SR_SMF_Msk (0x1U << QSPI_SR_SMF_Pos)·QSPI_SR_FTF_Pos 2¹QSPI_SR_FTF_Msk (0x1U << QSPI_SR_FTF_Pos)»QSPI_SR_TCF_Pos 1¼QSPI_SR_TCF_Msk (0x1U << QSPI_SR_TCF_Pos)¾QSPI_DATALEN_QSPI_DATALEN_Pos 0¿QSPI_DATALEN_QSPI_DATALEN_Msk (0xffffffffU << QSPI_DATALEN_QSPI_DATALEN_Pos)ÁQSPI_CCR_CRM_Pos 28ÄQSPI_CCR_CRM_Msk (0x1U << QSPI_CCR_CRM_Pos)ÅQSPI_CCR_CRM_ALWAYS (0x0U << QSPI_CCR_CRM_Pos)ÆQSPI_CCR_CRM_ONLY (0x1U << QSPI_CCR_CRM_Pos)ÈQSPI_CCR_OPMODE_Pos 26ÍQSPI_CCR_OPMODE_Msk (0x3U << QSPI_CCR_OPMODE_Pos)ÎQSPI_CCR_OPMODE_WRITE (0x0U << QSPI_CCR_OPMODE_Pos)ÏQSPI_CCR_OPMODE_READ (0x1U << QSPI_CCR_OPMODE_Pos)ÐQSPI_CCR_OPMODE_QUERY (0x2U << QSPI_CCR_OPMODE_Pos)ÑQSPI_CCR_OPMODE_MAP (0x3U << QSPI_CCR_OPMODE_Pos)ÓQSPI_CCR_DMODE_Pos 24ØQSPI_CCR_DMODE_Msk (0x3U << QSPI_CCR_DMODE_Pos)ÙQSPI_CCR_DMODE_NONE (0x0U << QSPI_CCR_DMODE_Pos)ÚQSPI_CCR_DMODE_SINGLE (0x1U << QSPI_CCR_DMODE_Pos)ÛQSPI_CCR_DMODE_DOUBLE (0x2U << QSPI_CCR_DMODE_Pos)ÜQSPI_CCR_DMODE_FOUR (0x3U << QSPI_CCR_DMODE_Pos)ÞQSPI_CCR_DUMCYC_Pos 18ßQSPI_CCR_DUMCYC_Msk (0x1fU << QSPI_CCR_DUMCYC_Pos)áQSPI_CCR_ABSIZE_Pos 16æQSPI_CCR_ABSIZE_Msk (0x3U << QSPI_CCR_ABSIZE_Pos)çQSPI_CCR_ABSIZE_8BITS (0x0U << QSPI_CCR_ABSIZE_Pos)èQSPI_CCR_ABSIZE_16BITS (0x1U << QSPI_CCR_ABSIZE_Pos)éQSPI_CCR_ABSIZE_24BITS (0x2U << QSPI_CCR_ABSIZE_Pos)êQSPI_CCR_ABSIZE_32BITS (0x3U << QSPI_CCR_ABSIZE_Pos)ìQSPI_CCR_ABMODE_Pos 14ñQSPI_CCR_ABMODE_Msk (0x3U << QSPI_CCR_ABMODE_Pos)òQSPI_CCR_ABMODE_NONE (0x0U << QSPI_CCR_ABMODE_Pos)óQSPI_CCR_ABMODE_SINGLE (0x1U << QSPI_CCR_ABMODE_Pos)ôQSPI_CCR_ABMODE_DOUBLE (0x2U << QSPI_CCR_ABMODE_Pos)õQSPI_CCR_ABMODE_FOUR (0x3U << QSPI_CCR_ABMODE_Pos)÷QSPI_CCR_ADSIZE_Pos 12üQSPI_CCR_ADSIZE_Msk (0x3U << QSPI_CCR_ADSIZE_Pos)ýQSPI_CCR_ADSIZE_8BITS (0x0U << QSPI_CCR_ADSIZE_Pos)þQSPI_CCR_ADSIZE_16BITS (0x1U << QSPI_CCR_ADSIZE_Pos)ÿQSPI_CCR_ADSIZE_24BITS (0x2U << QSPI_CCR_ADSIZE_Pos)QSPI_CCR_ADSIZE_32BITS (0x3U << QSPI_CCR_ADSIZE_Pos)QSPI_CCR_ADMODE_Pos 10QSPI_CCR_ADMODE_Msk (0x3U << QSPI_CCR_ADMODE_Pos)QSPI_CCR_ADMODE_NONE (0x0U << QSPI_CCR_ADMODE_Pos)QSPI_CCR_ADMODE_SINGLE (0x1U << QSPI_CCR_ADMODE_Pos)QSPI_CCR_ADMODE_DOUBLE (0x2U << QSPI_CCR_ADMODE_Pos)QSPI_CCR_ADMODE_FOUR (0x3U << QSPI_CCR_ADMODE_Pos)QSPI_CCR_IMODE_Pos 8QSPI_CCR_IMODE_Msk (0x3U << QSPI_CCR_IMODE_Pos)QSPI_CCR_IMODE_NONE (0x0U << QSPI_CCR_IMODE_Pos)QSPI_CCR_IMODE_SINGLE (0x1U << QSPI_CCR_IMODE_Pos)QSPI_CCR_IMODE_DOUBLE (0x2U << QSPI_CCR_IMODE_Pos)QSPI_CCR_IMODE_FOUR (0x3U << QSPI_CCR_IMODE_Pos)QSPI_CCR_INSTRUCTION_Pos 0QSPI_CCR_INSTRUCTION_Msk (0xffU << QSPI_CCR_INSTRUCTION_Pos)QSPI_ADDR_QSPI_ADDR_Pos 0QSPI_ADDR_QSPI_ADDR_Msk (0xffffffffU << QSPI_ADDR_QSPI_ADDR_Pos)QSPI_ABR_QSPI_ABR_Pos 0QSPI_ABR_QSPI_ABR_Msk (0xffffffffU << QSPI_ABR_QSPI_ABR_Pos)¡QSPI_DR_QSPI_DATA_Pos 0¥QSPI_DR_QSPI_DATA_Msk (0xffffffffU << QSPI_DR_QSPI_DATA_Pos)§QSPI_SMSK_QSPI_SMSK_Pos 0¨QSPI_SMSK_QSPI_SMSK_Msk (0xffffffffU << QSPI_SMSK_QSPI_SMSK_Pos)ªQSPI_SMAT_QSPI_SMAT_Pos 0¬QSPI_SMAT_QSPI_SMAT_Msk (0xffffffffU << QSPI_SMAT_QSPI_SMAT_Pos)®QSPI_PITV_QSPI_PITV_Pos 0¯QSPI_PITV_QSPI_PITV_Msk (0xffffU << QSPI_PITV_QSPI_PITV_Pos)±QSPI_TO_QSPI_TO_Pos 0³QSPI_TO_QSPI_TO_Msk (0xffffU << QSPI_TO_QSPI_TO_Pos)µQSPI_CCR_DUMCYC_SET(value) ((value << QSPI_CCR_DUMCYC_Pos) & QSPI_CCR_DUMCYC_Msk)¶QSPI_CCR_DUMCYC_GET(value) ((value >> QSPI_CCR_DUMCYC_Pos) & QSPI_CCR_DUMCYC_Msk)·QSPI_CCR_INSTRUCTION_SET(value) ((value << QSPI_CCR_INSTRUCTION_Pos) & QSPI_CCR_INSTRUCTION_Msk)¸QSPI_CCR_INSTRUCTION_GET(value) ((value >> QSPI_CCR_INSTRUCTION_Pos) & QSPI_CCR_INSTRUCTION_Msk)`U ..\Drivers\..\Core\Include\fm33a0xxev_qspi.hFM33A0XXEV.h¸
..\Drivers\fm33a0xxev_qspi.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM* (Instructionf#Addressf#AlternateBytef#AddressSizef#AlternateByteSizef#DummyCyclesf#InstructionModef#AddressModef#AlternateByteModef# DataModef#$PQSPI_CmdTypeDef¾'åæç__FM33A0XXEV_BT_H BTx_CR1_CHEN_Pos 7BTx_CR1_CHEN_Msk (0x1U << BTx_CR1_CHEN_Pos)BTx_CR1_CLEN_Pos 6 BTx_CR1_CLEN_Msk (0x1U << BTx_CR1_CLEN_Pos)$BTx_CR1_MODE_Pos 5'BTx_CR1_MODE_Msk (0x1U << BTx_CR1_MODE_Pos)(BTx_CR1_MODE_CAPTURE (0x1U << BTx_CR1_MODE_Pos))BTx_CR1_MODE_COUNTER (0x0U << BTx_CR1_MODE_Pos)+BTx_CR1_EDGESEL_Pos 4/BTx_CR1_EDGESEL_Msk (0x1U << BTx_CR1_EDGESEL_Pos)0BTx_CR1_EDGESEL_FALLING (0x1U << BTx_CR1_EDGESEL_Pos)1BTx_CR1_EDGESEL_RISING (0x0U << BTx_CR1_EDGESEL_Pos)3BTx_CR1_CAPMOD_Pos 36BTx_CR1_CAPMOD_Msk (0x1U << BTx_CR1_CAPMOD_Pos)7BTx_CR1_CAPMOD_PULSE (0x1U << BTx_CR1_CAPMOD_Pos)8BTx_CR1_CAPMOD_CYCLE (0x0U << BTx_CR1_CAPMOD_Pos):BTx_CR1_CAPCLR_Pos 2=BTx_CR1_CAPCLR_Msk (0x1U << BTx_CR1_CAPCLR_Pos)ABTx_CR1_CAPONCE_Pos 1DBTx_CR1_CAPONCE_Msk (0x1U << BTx_CR1_CAPONCE_Pos)EBTx_CR1_CAPONCE_SINGLE (0x1U << BTx_CR1_CAPONCE_Pos)FBTx_CR1_CAPONCE_CONTINUE (0x0U << BTx_CR1_CAPONCE_Pos)HBTx_CR1_PWM_Pos 0KBTx_CR1_PWM_Msk (0x1U << BTx_CR1_PWM_Pos)OBTx_CR2_SIG2SEL_Pos 7RBTx_CR2_SIG2SEL_Msk (0x1U << BTx_CR2_SIG2SEL_Pos)SBTx_CR2_SIG2SEL_GROUP2 (0x1U << BTx_CR2_SIG2SEL_Pos)TBTx_CR2_SIG2SEL_GROUP1 (0x0U << BTx_CR2_SIG2SEL_Pos)VBTx_CR2_SIG1SEL_Pos 6YBTx_CR2_SIG1SEL_Msk (0x1U << BTx_CR2_SIG1SEL_Pos)ZBTx_CR2_SIG1SEL_GROUP1 (0x1U << BTx_CR2_SIG1SEL_Pos)[BTx_CR2_SIG1SEL_GROUP2 (0x0U << BTx_CR2_SIG1SEL_Pos)]BTx_CR2_CNTHSEL_Pos 4aBTx_CR2_CNTHSEL_Msk (0x3U << BTx_CR2_CNTHSEL_Pos)bBTx_CR2_CNTHSEL_COUNTER (0x0U << BTx_CR2_CNTHSEL_Pos)cBTx_CR2_CNTHSEL_CAPTURE (0x1U << BTx_CR2_CNTHSEL_Pos)dBTx_CR2_CNTHSEL_INNER (0x2U << BTx_CR2_CNTHSEL_Pos)fBTx_CR2_DIREN_Pos 3iBTx_CR2_DIREN_Msk (0x1U << BTx_CR2_DIREN_Pos)mBTx_CR2_STDIR_Pos 2oBTx_CR2_STDIR_Msk (0x1U << BTx_CR2_STDIR_Pos)rBTx_CR2_SRCSEL_Pos 1uBTx_CR2_SRCSEL_Msk (0x1U << BTx_CR2_SRCSEL_Pos)xBTx_CR2_DIRPO_Pos 0{BTx_CR2_DIRPO_Msk (0x1U << BTx_CR2_DIRPO_Pos)|BTx_CR2_DIRPO_REVERSE (0x1U << BTx_CR2_DIRPO_Pos)}BTx_CR2_DIRPO_NON (0x0U << BTx_CR2_DIRPO_Pos)BTx_CFGR1_RTCSEL2_Pos 6BTx_CFGR1_RTCSEL2_Msk (0x3U << BTx_CFGR1_RTCSEL2_Pos)BTx_CFGR1_RTCSEL2_32768HZ (0x0U << BTx_CFGR1_RTCSEL2_Pos)BTx_CFGR1_RTCSEL2_RTC_SEC (0x1U << BTx_CFGR1_RTCSEL2_Pos)BTx_CFGR1_RTCSEL2_RTC_MIN (0x2U << BTx_CFGR1_RTCSEL2_Pos)BTx_CFGR1_RTCSEL1_Pos 4BTx_CFGR1_RTCSEL1_Msk (0x3U << BTx_CFGR1_RTCSEL1_Pos)BTx_CFGR1_RTCSEL1_32768HZ (0x0U << BTx_CFGR1_RTCSEL1_Pos)BTx_CFGR1_RTCSEL1_RTC_SEC (0x1U << BTx_CFGR1_RTCSEL1_Pos)BTx_CFGR1_RTCSEL1_RTC_MIN (0x2U << BTx_CFGR1_RTCSEL1_Pos)BTx_CFGR1_GRP2SEL_Pos 2BTx_CFGR1_GRP2SEL_Msk (0x3U << BTx_CFGR1_GRP2SEL_Pos)BTx_CFGR1_GRP2SEL_APBCLK (0x0U << BTx_CFGR1_GRP2SEL_Pos)BTx_CFGR1_GRP2SEL_RTCOUT2 (0x1U << BTx_CFGR1_GRP2SEL_Pos)BTx_CFGR1_GRP2SEL_IN_SIG2 (0x2U << BTx_CFGR1_GRP2SEL_Pos)BTx_CFGR1_GRP2SEL_EX_SIG2 (0x3U << BTx_CFGR1_GRP2SEL_Pos)BTx_CFGR1_GRP1SEL_Pos 0¥BTx_CFGR1_GRP1SEL_Msk (0x3U << BTx_CFGR1_GRP1SEL_Pos)¦BTx_CFGR1_GRP1SEL_APBCLK (0x0U << BTx_CFGR1_GRP1SEL_Pos)§BTx_CFGR1_GRP1SEL_RTCOUT1 (0x1U << BTx_CFGR1_GRP1SEL_Pos)¨BTx_CFGR1_GRP1SEL_IN_SIG1 (0x2U << BTx_CFGR1_GRP1SEL_Pos)©BTx_CFGR1_GRP1SEL_EX_SIG1 (0x3U << BTx_CFGR1_GRP1SEL_Pos)«BTx_CFGR2_EXSEL2_Pos 6°BTx_CFGR2_EXSEL2_Msk (0x3U << BTx_CFGR2_EXSEL2_Pos)±BTx_CFGR2_EXSEL2_IN0 (0x0U << BTx_CFGR2_EXSEL2_Pos)²BTx_CFGR2_EXSEL2_IN1 (0x1U << BTx_CFGR2_EXSEL2_Pos)³BTx_CFGR2_EXSEL2_IN2 (0x2U << BTx_CFGR2_EXSEL2_Pos)´BTx_CFGR2_EXSEL2_IN3 (0x3U << BTx_CFGR2_EXSEL2_Pos)¶BTx_CFGR2_EXSEL1_Pos 4»BTx_CFGR2_EXSEL1_Msk (0x3U << BTx_CFGR2_EXSEL1_Pos)¼BTx_CFGR2_EXSEL1_IN0 (0x0U << BTx_CFGR2_EXSEL1_Pos)½BTx_CFGR2_EXSEL1_IN1 (0x1U << BTx_CFGR2_EXSEL1_Pos)¾BTx_CFGR2_EXSEL1_IN2 (0x2U << BTx_CFGR2_EXSEL1_Pos)¿BTx_CFGR2_EXSEL1_IN3 (0x3U << BTx_CFGR2_EXSEL1_Pos)ÁBTx_CFGR2_INSEL2_Pos 2ÆBTx_CFGR2_INSEL2_Msk (0x3U << BTx_CFGR2_INSEL2_Pos)ÇBTx_CFGR2_INSEL2_RX3 (0x0U << BTx_CFGR2_INSEL2_Pos)ÈBTx_CFGR2_INSEL2_RX4 (0x1U << BTx_CFGR2_INSEL2_Pos)ÉBTx_CFGR2_INSEL2_RX5 (0x2U << BTx_CFGR2_INSEL2_Pos)ÊBTx_CFGR2_INSEL2_RCLP (0x3U << BTx_CFGR2_INSEL2_Pos)ÌBTx_CFGR2_INSEL1_Pos 0ÑBTx_CFGR2_INSEL1_Msk (0x3U << BTx_CFGR2_INSEL1_Pos)ÒBTx_CFGR2_INSEL1_RX0 (0x0U << BTx_CFGR2_INSEL1_Pos)ÓBTx_CFGR2_INSEL1_RX1 (0x1U << BTx_CFGR2_INSEL1_Pos)ÔBTx_CFGR2_INSEL1_RX2 (0x2U << BTx_CFGR2_INSEL1_Pos)ÕBTx_CFGR2_INSEL1_RCLP (0x3U << BTx_CFGR2_INSEL1_Pos)×BTx_PRES_PRESCALE_Pos 0ÙBTx_PRES_PRESCALE_Msk (0xffU << BTx_PRES_PRESCALE_Pos)ÛBTx_LOADCR_LHEN_Pos 4ÝBTx_LOADCR_LHEN_Msk (0x1U << BTx_LOADCR_LHEN_Pos)ßBTx_LOADCR_LLEN_Pos 0áBTx_LOADCR_LLEN_Msk (0x1U << BTx_LOADCR_LLEN_Pos)ãBTx_CNTL_CNTL_Pos 0åBTx_CNTL_CNTL_Msk (0xffU << BTx_CNTL_CNTL_Pos)çBTx_CNTH_CNTH_Pos 0éBTx_CNTH_CNTH_Msk (0xffU << BTx_CNTH_CNTH_Pos)ëBTx_PRESET_PRESETH_Pos 8íBTx_PRESET_PRESETH_Msk (0xffU << BTx_PRESET_PRESETH_Pos)ïBTx_PRESET_PRESETL_Pos 0ñBTx_PRESET_PRESETL_Msk (0xffU << BTx_PRESET_PRESETL_Pos)óBTx_LOADL_LOADL_Pos 0õBTx_LOADL_LOADL_Msk (0xffU << BTx_LOADL_LOADL_Pos)÷BTx_LOADH_LOADH_Pos 0ùBTx_LOADH_LOADH_Msk (0xffU << BTx_LOADH_LOADH_Pos)ûBTx_CMPL_CMPL_Pos 0ýBTx_CMPL_CMPL_Msk (0xffU << BTx_CMPL_CMPL_Pos)ÿBTx_CMPH_CMPH_Pos 0BTx_CMPH_CMPH_Msk (0xffU << BTx_CMPH_CMPH_Pos)BTx_OUTCNT_OUTCNT_Pos 0BTx_OUTCNT_OUTCNT_Msk (0xfffU << BTx_OUTCNT_OUTCNT_Pos)BTx_OCR_OUTCLR_Pos 5BTx_OCR_OUTCLR_Msk (0x1U << BTx_OCR_OUTCLR_Pos)BTx_OCR_OUTCLR_INVALID (0x0U << BTx_OCR_OUTCLR_Pos)BTx_OCR_OUTCLR_CLEAR (0x1U << BTx_OCR_OUTCLR_Pos)BTx_OCR_OUTINV_Pos 4BTx_OCR_OUTINV_Msk (0x1U << BTx_OCR_OUTINV_Pos)BTx_OCR_OUTINV_NORMAL (0x0U << BTx_OCR_OUTINV_Pos)BTx_OCR_OUTINV_REVERSE (0x1U << BTx_OCR_OUTINV_Pos)BTx_OCR_OUTMOD_Pos 3BTx_OCR_OUTMOD_Msk (0x1U << BTx_OCR_OUTMOD_Pos)BTx_OCR_OUTMOD_PULSE_SHIFT (0x0U << BTx_OCR_OUTMOD_Pos)BTx_OCR_OUTMOD_NEG (0x1U << BTx_OCR_OUTMOD_Pos)BTx_OCR_OUTSEL_Pos 0BTx_OCR_OUTSEL_Msk (0x7U << BTx_OCR_OUTSEL_Pos)BTx_OCR_OUTSEL_HIGH (0x0U << BTx_OCR_OUTSEL_Pos)BTx_OCR_OUTSEL_LOW (0x1U << BTx_OCR_OUTSEL_Pos)BTx_OCR_OUTSEL_GROUP1 (0x2U << BTx_OCR_OUTSEL_Pos)BTx_OCR_OUTSEL_GROUP2 (0x3U << BTx_OCR_OUTSEL_Pos)BTx_OCR_OUTSEL_PWM (0x4U << BTx_OCR_OUTSEL_Pos)BTx_IER_CMPHIE_Pos 4¡BTx_IER_CMPHIE_Msk (0x1U << BTx_IER_CMPHIE_Pos)£BTx_IER_CMPLIE_Pos 3¦BTx_IER_CMPLIE_Msk (0x1U << BTx_IER_CMPLIE_Pos)¨BTx_IER_OVHIE_Pos 2«BTx_IER_OVHIE_Msk (0x1U << BTx_IER_OVHIE_Pos)BTx_IER_OVLIE_Pos 1°BTx_IER_OVLIE_Msk (0x1U << BTx_IER_OVLIE_Pos)²BTx_IER_CAPIE_Pos 0µBTx_IER_CAPIE_Msk (0x1U << BTx_IER_CAPIE_Pos)·BTx_ISR_EDGESTA_Pos 5ºBTx_ISR_EDGESTA_Msk (0x1U << BTx_ISR_EDGESTA_Pos)¼BTx_ISR_CMPHIF_Pos 4¿BTx_ISR_CMPHIF_Msk (0x1U << BTx_ISR_CMPHIF_Pos)ÁBTx_ISR_CMPLIF_Pos 3ÄBTx_ISR_CMPLIF_Msk (0x1U << BTx_ISR_CMPLIF_Pos)ÆBTx_ISR_OVHIF_Pos 2ÉBTx_ISR_OVHIF_Msk (0x1U << BTx_ISR_OVHIF_Pos)ËBTx_ISR_OVLIF_Pos 1ÎBTx_ISR_OVLIF_Msk (0x1U << BTx_ISR_OVLIF_Pos)ÐBTx_ISR_CAPIF_Pos 0ÓBTx_ISR_CAPIF_Msk (0x1U << BTx_ISR_CAPIF_Pos)\S ..\Drivers\..\Core\Include\fm33a0xxev_bt.hFM33A0XXEV.h¼
..\Drivers\fm33a0xxev_bt.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMéêë__FM33A0XXEV_ET_H ETx_CR_OPOL_Pos 10ETx_CR_OPOL_Msk (0x1U << ETx_CR_OPOL_Pos)ETx_CR_OPOL_NORMAL (0x0U << ETx_CR_OPOL_Pos)ETx_CR_OPOL_REVERSE (0x1U << ETx_CR_OPOL_Pos) ETx_CR_EXFLT_Pos 9#ETx_CR_EXFLT_Msk (0x1U << ETx_CR_EXFLT_Pos)$ETx_CR_EXFLT_OPEN (0x1U << ETx_CR_EXFLT_Pos)%ETx_CR_EXFLT_CLOSE (0x0U << ETx_CR_EXFLT_Pos)'ETx_CR_PWM_Pos 8*ETx_CR_PWM_Msk (0x1U << ETx_CR_PWM_Pos),ETx_CR_CEN_Pos 7/ETx_CR_CEN_Msk (0x1U << ETx_CR_CEN_Pos)1ETx_CR_MOD_Pos 64ETx_CR_MOD_Msk (0x1U << ETx_CR_MOD_Pos)5ETx_CR_MOD_CAPTURE (0x1U << ETx_CR_MOD_Pos)6ETx_CR_MOD_COUNTER (0x0U << ETx_CR_MOD_Pos)8ETx_CR_CASEN_Pos 5;ETx_CR_CASEN_Msk (0x1U << ETx_CR_CASEN_Pos)<ETx_CR_CASEN_32BITS (0x1U << ETx_CR_CASEN_Pos)=ETx_CR_CASEN_16BITS (0x0U << ETx_CR_CASEN_Pos)?ETx_CR_EDGESEL_Pos 4CETx_CR_EDGESEL_Msk (0x1U << ETx_CR_EDGESEL_Pos)DETx_CR_EDGESEL_FALLING (0x1U << ETx_CR_EDGESEL_Pos)EETx_CR_EDGESEL_RISING (0x0U << ETx_CR_EDGESEL_Pos)GETx_CR_CAPMOD_Pos 3JETx_CR_CAPMOD_Msk (0x1U << ETx_CR_CAPMOD_Pos)KETx_CR_CAPMOD_PULSE (0x1U << ETx_CR_CAPMOD_Pos)LETx_CR_CAPMOD_CYCLE (0x0U << ETx_CR_CAPMOD_Pos)NETx_CR_CAPCLR_Pos 2QETx_CR_CAPCLR_Msk (0x1U << ETx_CR_CAPCLR_Pos)TETx_CR_CAPONCE_Pos 1WETx_CR_CAPONCE_Msk (0x1U << ETx_CR_CAPONCE_Pos)XETx_CR_CAPONCE_SINGLE (0x1U << ETx_CR_CAPONCE_Pos)YETx_CR_CAPONCE_CONTINUE (0x0U << ETx_CR_CAPONCE_Pos)[ETx_CR_CAPEDGE_Pos 0^ETx_CR_CAPEDGE_Msk (0x1U << ETx_CR_CAPEDGE_Pos)_ETx_CR_CAPEDGE_FALLING (0x1U << ETx_CR_CAPEDGE_Pos)`ETx_CR_CAPEDGE_RISING (0x0U << ETx_CR_CAPEDGE_Pos)bETx_INSR_SIG2SEL_Pos 7eETx_INSR_SIG2SEL_Msk (0x1U << ETx_INSR_SIG2SEL_Pos)fETx_INSR_SIG2SEL_GROUP1 (0x1U << ETx_INSR_SIG2SEL_Pos)gETx_INSR_SIG2SEL_GROUP2 (0x0U << ETx_INSR_SIG2SEL_Pos)iETx_INSR_SIG1SEL_Pos 6lETx_INSR_SIG1SEL_Msk (0x1U << ETx_INSR_SIG1SEL_Pos)mETx_INSR_SIG1SEL_GROUP2 (0x1U << ETx_INSR_SIG1SEL_Pos)nETx_INSR_SIG1SEL_GROUP1 (0x0U << ETx_INSR_SIG1SEL_Pos)pETx_INSR_GRP2SEL_Pos 2ETx_INSR_GRP2SEL_Msk (0x7U << ETx_INSR_GRP2SEL_Pos)ETx_INSR_GRP2SEL_ET1_UART0_RX (0x0U << ETx_INSR_GRP2SEL_Pos)ETx_INSR_GRP2SEL_ET1_UART1_RX (0x1U << ETx_INSR_GRP2SEL_Pos)ETx_INSR_GRP2SEL_ET1_XTLF (0x2U << ETx_INSR_GRP2SEL_Pos)ETx_INSR_GRP2SEL_ET1_IN1 (0x3U << ETx_INSR_GRP2SEL_Pos)ETx_INSR_GRP2SEL_ET1_IN2 (0x4U << ETx_INSR_GRP2SEL_Pos)ETx_INSR_GRP2SEL_ET1_CMP1O (0x5U << ETx_INSR_GRP2SEL_Pos)ETx_INSR_GRP2SEL_ET1_CMP2O (0x6U << ETx_INSR_GRP2SEL_Pos)ETx_INSR_GRP2SEL_ET1_RCMF (0x7U << ETx_INSR_GRP2SEL_Pos)ETx_INSR_GRP2SEL_ET2_UART2_RX (0x0U << ETx_INSR_GRP2SEL_Pos)ETx_INSR_GRP2SEL_ET2_UART3_RX (0x1U << ETx_INSR_GRP2SEL_Pos)ETx_INSR_GRP2SEL_ET2_XTLF (0x2U << ETx_INSR_GRP2SEL_Pos)ETx_INSR_GRP2SEL_ET2_IN1 (0x3U << ETx_INSR_GRP2SEL_Pos) ETx_INSR_GRP2SEL_ET2_IN2 (0x4U << ETx_INSR_GRP2SEL_Pos)¡ETx_INSR_GRP2SEL_ET2_CMP1O (0x5U << ETx_INSR_GRP2SEL_Pos)¢ETx_INSR_GRP2SEL_ET2_CMP2O (0x6U << ETx_INSR_GRP2SEL_Pos)£ETx_INSR_GRP2SEL_ET2_RCMF (0x7U << ETx_INSR_GRP2SEL_Pos)¤ETx_INSR_GRP2SEL_ET3_IN1 (0x0U << ETx_INSR_GRP2SEL_Pos)¥ETx_INSR_GRP2SEL_ET3_XTLF (0x1U << ETx_INSR_GRP2SEL_Pos)¦ETx_INSR_GRP2SEL_ET3_UART4_RX (0x2U << ETx_INSR_GRP2SEL_Pos)§ETx_INSR_GRP2SEL_ET3_UART5_RX (0x3U << ETx_INSR_GRP2SEL_Pos)¨ETx_INSR_GRP2SEL_ET3_RTCSEC (0x4U << ETx_INSR_GRP2SEL_Pos)©ETx_INSR_GRP2SEL_ET4_IN (0x0U << ETx_INSR_GRP2SEL_Pos)ªETx_INSR_GRP2SEL_ET4_XTLF (0x1U << ETx_INSR_GRP2SEL_Pos)«ETx_INSR_GRP2SEL_ET4_UART_RX2 (0x2U << ETx_INSR_GRP2SEL_Pos)¬ETx_INSR_GRP2SEL_ET4_UART_RX0 (0x3U << ETx_INSR_GRP2SEL_Pos)ETx_INSR_GRP2SEL_ET4_CMP1O (0x4U << ETx_INSR_GRP2SEL_Pos)®ETx_INSR_GRP2SEL_ET4_CMP2O (0x5U << ETx_INSR_GRP2SEL_Pos)¯ETx_INSR_GRP2SEL_ET4_RTCSEC (0x6U << ETx_INSR_GRP2SEL_Pos)°ETx_INSR_GRP2SEL_ET4_RCMF (0x7U << ETx_INSR_GRP2SEL_Pos)²ETx_INSR_GRP1SEL_Pos 0ÇETx_INSR_GRP1SEL_Msk (0x3U << ETx_INSR_GRP1SEL_Pos)ÈETx_INSR_GRP1SEL_ET1_APBCLK (0x0U << ETx_INSR_GRP1SEL_Pos)ÉETx_INSR_GRP1SEL_ET1_XTLF (0x1U << ETx_INSR_GRP1SEL_Pos)ÊETx_INSR_GRP1SEL_ET1_RCLP (0x2U << ETx_INSR_GRP1SEL_Pos)ËETx_INSR_GRP1SEL_ET1_IN0 (0x3U << ETx_INSR_GRP1SEL_Pos)ÌETx_INSR_GRP1SEL_ET2_APBCLK (0x0U << ETx_INSR_GRP1SEL_Pos)ÍETx_INSR_GRP1SEL_ET2_XTLF (0x1U << ETx_INSR_GRP1SEL_Pos)ÎETx_INSR_GRP1SEL_ET2_RCLP (0x2U << ETx_INSR_GRP1SEL_Pos)ÏETx_INSR_GRP1SEL_ET2_IN0 (0x3U << ETx_INSR_GRP1SEL_Pos)ÐETx_INSR_GRP1SEL_ET3_APBCLK (0x0U << ETx_INSR_GRP1SEL_Pos)ÑETx_INSR_GRP1SEL_ET3_IN0 (0x1U << ETx_INSR_GRP1SEL_Pos)ÒETx_INSR_GRP1SEL_ET3_RTCSEC (0x2U << ETx_INSR_GRP1SEL_Pos)ÓETx_INSR_GRP1SEL_ET3_RCLP (0x3U << ETx_INSR_GRP1SEL_Pos)ÔETx_INSR_GRP1SEL_ET4_APBCLK (0x0U << ETx_INSR_GRP1SEL_Pos)ÕETx_INSR_GRP1SEL_ET4_IN0 (0x1U << ETx_INSR_GRP1SEL_Pos)ÖETx_INSR_GRP1SEL_ET4_RTC64HZ (0x2U << ETx_INSR_GRP1SEL_Pos)×ETx_INSR_GRP1SEL_ET4_RCMF (0x3U << ETx_INSR_GRP1SEL_Pos)ÙETx_PSCR1_PRESCALE1_Pos 0ÛETx_PSCR1_PRESCALE1_Msk (0xffU << ETx_PSCR1_PRESCALE1_Pos)ÝETx_PSCR2_PRESCALE2_Pos 0ßETx_PSCR2_PRESCALE2_Msk (0xffU << ETx_PSCR2_PRESCALE2_Pos)áETx_IVR_INITVALUE_Pos 0âETx_IVR_INITVALUE_Msk (0xffffU << ETx_IVR_INITVALUE_Pos)äETx_CMPR_CMP_Pos 0æETx_CMPR_CMP_Msk (0xffffU << ETx_CMPR_CMP_Pos)èETx_IER_CMPIE_Pos 2ëETx_IER_CMPIE_Msk (0x1U << ETx_IER_CMPIE_Pos)íETx_IER_CAPIE_Pos 1ðETx_IER_CAPIE_Msk (0x1U << ETx_IER_CAPIE_Pos)òETx_IER_OVIE_Pos 0õETx_IER_OVIE_Msk (0x1U << ETx_IER_OVIE_Pos)÷ETx_ISR_CMPIF_Pos 3úETx_ISR_CMPIF_Msk (0x1U << ETx_ISR_CMPIF_Pos)üETx_ISR_EDGESTA_Pos 2ÿETx_ISR_EDGESTA_Msk (0x1U << ETx_ISR_EDGESTA_Pos)ETx_ISR_CAPIF_Pos 1ETx_ISR_CAPIF_Msk (0x1U << ETx_ISR_CAPIF_Pos)ETx_ISR_OVIF_Pos 0ETx_ISR_OVIF_Msk (0x1U << ETx_ISR_OVIF_Pos)ETCNTx_CNT_Pos 0ETCNTx_CNT_Msk (0xffffU << ETCNTx_CNT_Pos)\S ..\Drivers\..\Core\Include\fm33a0xxev_et.hFM33A0XXEV.h¼
..\Drivers\fm33a0xxev_et.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMíîï__FM33A0XXEV_VRTC_H HXVAR(object,addr) (*((object *) (addr)))const_rcmf_Trim HXVAR( uint32_t, 0x1FFFFB44 )const_rclp_Trim HXVAR( uint32_t, 0x1FFFFB20 )VRTC_PDRCR_CFG_Pos 0VRTC_PDRCR_CFG_Msk (0x1U << VRTC_PDRCR_CFG_Pos)"VRTC_RCMFCR_EN_Msk (0x1U << VRTC_RCMFCR_EN_Pos)&VRTC_RCMFCR_EN_Pos 7*VRTC_RCMFCR_EN_Msk (0x1U << VRTC_RCMFCR_EN_Pos).VRTC_RCMFCR_TRIM_Pos 0/VRTC_RCMFCR_TRIM_Msk (0x3fU << VRTC_RCMFCR_TRIM_Pos)1VRTC_RCLPCR_CHOPEN_Pos 12VRTC_RCLPCR_CHOPEN_Msk (0x1U << VRTC_RCLPCR_CHOPEN_Pos)4VRTC_RCLPCR_RCLP_OFF_Pos 08VRTC_RCLPCR_RCLP_OFF_Msk (0x1U << VRTC_RCLPCR_RCLP_OFF_Pos)<VRTC_RCLPTR_RCLP_TRIM_Pos 0?VRTC_RCLPTR_RCLP_TRIM_Msk (0xffU << VRTC_RCLPTR_RCLP_TRIM_Pos)AVRTC_XTLFCR_XTLFIPW_Pos 0BVRTC_XTLFCR_XTLFIPW_Msk (0xfU << VRTC_XTLFCR_XTLFIPW_Pos)CVRTC_XTLFCR_XTLFIPW_850NA (0x0U << VRTC_XTLFCR_XTLFIPW_Pos)DVRTC_XTLFCR_XTLFIPW_800NA (0x1U << VRTC_XTLFCR_XTLFIPW_Pos)EVRTC_XTLFCR_XTLFIPW_750NA (0x2U << VRTC_XTLFCR_XTLFIPW_Pos)FVRTC_XTLFCR_XTLFIPW_700NA (0x3U << VRTC_XTLFCR_XTLFIPW_Pos)GVRTC_XTLFCR_XTLFIPW_650NA (0x4U << VRTC_XTLFCR_XTLFIPW_Pos)HVRTC_XTLFCR_XTLFIPW_600NA (0x5U << VRTC_XTLFCR_XTLFIPW_Pos)IVRTC_XTLFCR_XTLFIPW_550NA (0x6U << VRTC_XTLFCR_XTLFIPW_Pos)JVRTC_XTLFCR_XTLFIPW_500NA (0x7U << VRTC_XTLFCR_XTLFIPW_Pos)KVRTC_XTLFCR_XTLFIPW_450NA (0x8U << VRTC_XTLFCR_XTLFIPW_Pos)LVRTC_XTLFCR_XTLFIPW_400NA (0x9U << VRTC_XTLFCR_XTLFIPW_Pos)MVRTC_XTLFCR_XTLFIPW_350NA (0xaU << VRTC_XTLFCR_XTLFIPW_Pos)NVRTC_XTLFCR_XTLFIPW_300NA (0xbU << VRTC_XTLFCR_XTLFIPW_Pos)OVRTC_XTLFCR_XTLFIPW_250NA (0xcU << VRTC_XTLFCR_XTLFIPW_Pos)PVRTC_XTLFCR_XTLFIPW_200NA (0xdU << VRTC_XTLFCR_XTLFIPW_Pos)QVRTC_XTLFCR_XTLFIPW_150NA (0xeU << VRTC_XTLFCR_XTLFIPW_Pos)RVRTC_XTLFCR_XTLFIPW_100NA (0xfU << VRTC_XTLFCR_XTLFIPW_Pos)TVRTC_ADCCR_CKS_Pos 1]VRTC_ADCCR_CKS_Msk (0x7U << VRTC_ADCCR_CKS_Pos)^VRTC_ADCCR_CKS_RCMF (0x0U << VRTC_ADCCR_CKS_Pos)_VRTC_ADCCR_CKS_RCMF_2 (0x1U << VRTC_ADCCR_CKS_Pos)`VRTC_ADCCR_CKS_RCMF_4 (0x2U << VRTC_ADCCR_CKS_Pos)aVRTC_ADCCR_CKS_RCMF_8 (0x3U << VRTC_ADCCR_CKS_Pos)bVRTC_ADCCR_CKS_RCMF_16 (0x4U << VRTC_ADCCR_CKS_Pos)cVRTC_ADCCR_CKS_RCMF_32 (0x5U << VRTC_ADCCR_CKS_Pos)dVRTC_ADCCR_CKS_RCLP (0x6U << VRTC_ADCCR_CKS_Pos)eVRTC_ADCCR_CKS_XTLF (0x7U << VRTC_ADCCR_CKS_Pos)gVRTC_ADCCR_CKE_Pos 0jVRTC_ADCCR_CKE_Msk (0x1U << VRTC_ADCCR_CKE_Pos)nVRTC_LFDIER_LFDET_IE_Pos 0oVRTC_LFDIER_LFDET_IE_Msk (0x1U << VRTC_LFDIER_LFDET_IE_Pos)qVRTC_LFDISR_LFDETO_Pos 1tVRTC_LFDISR_LFDETO_Msk (0x1U << VRTC_LFDISR_LFDETO_Pos)vVRTC_LFDISR_LFDET_IF_Pos 0wVRTC_LFDISR_LFDET_IF_Msk (0x1U << VRTC_LFDISR_LFDET_IF_Pos)`U ..\Drivers\..\Core\Include\fm33a0xxev_vrtc.hFM33A0XXEV.h¼
..\Drivers\fm33a0xxev_vrtc.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMñòó__FM33A0XXEV_CDIF_H CDIF_CR_INTF_EN_Pos 0CDIF_CR_INTF_EN_Msk (0xfU << CDIF_CR_INTF_EN_Pos)CDIF_CR_INTF_EN_ENABLE (0xAU << CDIF_CR_INTF_EN_Pos)CDIF_CR_INTF_EN_DISABLE (0x5U << CDIF_CR_INTF_EN_Pos)!CDIF_PSCR_PRSC_Pos 0"CDIF_PSCR_PRSC_Msk (0x7U << CDIF_PSCR_PRSC_Pos)#CDIF_PSCR_PRSC_DIV1 (0x0U)$CDIF_PSCR_PRSC_DIV2 (0x1U)%CDIF_PSCR_PRSC_DIV4 (0x2U)&CDIF_PSCR_PRSC_DIV8 (0x3U)'CDIF_PSCR_PRSC_DIV16 (0x4U)(CDIF_PSCR_PRSC_DIV32 (0x5U))CDIF_PSCR_PRSC_DIV64 (0x6U)*CDIF_PSCR_PRSC_DIV128 (0x7U)`U ..\Drivers\..\Core\Include\fm33a0xxev_cdif.hFM33A0XXEV.h¼
..\Drivers\fm33a0xxev_cdif.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMõö÷__INCLUDEALL_H__     
     
  !"#$ ÌÂ ..\Core\..\Drivers\fm33a0xxev_include_all.hfm33a0xxev_aes.hfm33a0xxev_adc.hfm33a0xxev_bstim.hfm33a0xxev_comp.hfm33a0xxev_rmu.hfm33a0xxev_crc.hfm33a0xxev_lcd.hfm33a0xxev_dma.hfm33a0xxev_gpio.hfm33a0xxev_i2c.hfm33a0xxev_iwdt.hfm33a0xxev_lpuart.hfm33a0xxev_flash.hfm33a0xxev_pmu.hfm33a0xxev_cmu.hfm33a0xxev_rtc.hfm33a0xxev_dbg.hfm33a0xxev_spi.hfm33a0xxev_rng.hfm33a0xxev_u7816.hfm33a0xxev_uart.hfm33a0xxev_lptim.hfm33a0xxev_wwdt.hfm33a0xxev_svd.hfm33a0xxev_pae.hfm33a0xxev_hash.hfm33a0xxev_qspi.hfm33a0xxev_bt.hfm33a0xxev_et.hfm33a0xxev_vrtc.hfm33a0xxev_cdif.hÀ
..\Core\fm33a0xxev_include_all.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMùúû__string_h __ARMCLIB_VERSION 5060037_ARMABI __declspec(__nothrow)__STRING_DECLS __CLIBNS$__CLIBNS 7NULL8NULL 0XM D:\Keil5\ARM\ARMCC\Bin\..\include\string.hstdio.h¤D:\Keil5\ARM\ARMCC\Bin\..\include\string.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]unsigned intPsize_t5ýþÿBIT0 0x00000001BIT1 0x00000002BIT2 0x00000004BIT3 0x00000008BIT4 0x00000010BIT5 0x00000020    BIT6 0x00000040
BIT7 0x00000080BIT8 0x00000100BIT9 0x00000200 BIT10 0x00000400BIT11 0x00000800BIT12 0x00001000BIT13 0x00002000BIT14 0x00004000BIT15 0x00008000BIT16 0x00010000BIT17 0x00020000BIT18 0x00040000BIT19 0x00080000BIT20 0x00100000BIT21 0x00200000BIT22 0x00400000BIT23 0x00800000BIT24 0x01000000BIT25 0x02000000BIT26 0x04000000BIT27 0x08000000BIT28 0x10000000 BIT29 0x20000000!BIT30 0x40000000"BIT31 0x80000000#BITNO 0x00000000%B0000_0000 0x00&B0000_0001 0x01'B0000_0010 0x02(B0000_0011 0x03)B0000_0100 0x04*B0000_0101 0x05+B0000_0110 0x06,B0000_0111 0x07-B0000_1000 0x08.B0000_1001 0x09/B0000_1010 0x0A0B0000_1011 0x0B1B0000_1100 0x0C2B0000_1101 0x0D3B0000_1110 0x0E4B0000_1111 0x0F6B0001_0000 0x107B0001_0001 0x118B0001_0010 0x129B0001_0011 0x13:B0001_0100 0x14;B0001_0101 0x15<B0001_0110 0x16=B0001_0111 0x17>B0001_1000 0x18?B0001_1001 0x19@B0001_1010 0x1AAB0001_1011 0x1BBB0001_1100 0x1CCB0001_1101 0x1DDB0001_1110 0x1EEB0001_1111 0x1FGB0010_0000 0x20HB0010_0001 0x21IB0010_0010 0x22JB0010_0011 0x23KB0010_0100 0x24LB0010_0101 0x25MB0010_0110 0x26NB0010_0111 0x27OB0010_1000 0x28PB0010_1001 0x29QB0010_1010 0x2ARB0010_1011 0x2BSB0010_1100 0x2CTB0010_1101 0x2DUB0010_1110 0x2EVB0010_1111 0x2FXB0011_0000 0x30YB0011_0001 0x31ZB0011_0010 0x32[B0011_0011 0x33\B0011_0100 0x34]B0011_0101 0x35^B0011_0110 0x36_B0011_0111 0x37`B0011_1000 0x38aB0011_1001 0x39bB0011_1010 0x3AcB0011_1011 0x3BdB0011_1100 0x3CeB0011_1101 0x3DfB0011_1110 0x3EgB0011_1111 0x3FiB0100_0000 0x40jB0100_0001 0x41kB0100_0010 0x42lB0100_0011 0x43mB0100_0100 0x44nB0100_0101 0x45oB0100_0110 0x46pB0100_0111 0x47qB0100_1000 0x48rB0100_1001 0x49sB0100_1010 0x4AtB0100_1011 0x4BuB0100_1100 0x4CvB0100_1101 0x4DwB0100_1110 0x4ExB0100_1111 0x4FzB0101_0000 0x50{B0101_0001 0x51|B0101_0010 0x52}B0101_0011 0x53~B0101_0100 0x54B0101_0101 0x55B0101_0110 0x56B0101_0111 0x57B0101_1000 0x58B0101_1001 0x59B0101_1010 0x5AB0101_1011 0x5BB0101_1100 0x5CB0101_1101 0x5DB0101_1110 0x5EB0101_1111 0x5FB0110_0000 0x60B0110_0001 0x61B0110_0010 0x62B0110_0011 0x63B0110_0100 0x64B0110_0101 0x65B0110_0110 0x66B0110_0111 0x67B0110_1000 0x68B0110_1001 0x69B0110_1010 0x6AB0110_1011 0x6BB0110_1100 0x6CB0110_1101 0x6DB0110_1110 0x6EB0110_1111 0x6FB0111_0000 0x70B0111_0001 0x71B0111_0010 0x72B0111_0011 0x73 B0111_0100 0x74¡B0111_0101 0x75¢B0111_0110 0x76£B0111_0111 0x77¤B0111_1000 0x78¥B0111_1001 0x79¦B0111_1010 0x7A§B0111_1011 0x7B¨B0111_1100 0x7C©B0111_1101 0x7DªB0111_1110 0x7E«B0111_1111 0x7FB1000_0000 0x80®B1000_0001 0x81¯B1000_0010 0x82°B1000_0011 0x83±B1000_0100 0x84²B1000_0101 0x85³B1000_0110 0x86´B1000_0111 0x87µB1000_1000 0x88¶B1000_1001 0x89·B1000_1010 0x8A¸B1000_1011 0x8B¹B1000_1100 0x8CºB1000_1101 0x8D»B1000_1110 0x8E¼B1000_1111 0x8F¾B1001_0000 0x90¿B1001_0001 0x91ÀB1001_0010 0x92ÁB1001_0011 0x93ÂB1001_0100 0x94ÃB1001_0101 0x95ÄB1001_0110 0x96ÅB1001_0111 0x97ÆB1001_1000 0x98ÇB1001_1001 0x99ÈB1001_1010 0x9AÉB1001_1011 0x9BÊB1001_1100 0x9CËB1001_1101 0x9DÌB1001_1110 0x9EÍB1001_1111 0x9FÏB1010_0000 0xA0ÐB1010_0001 0xA1ÑB1010_0010 0xA2ÒB1010_0011 0xA3ÓB1010_0100 0xA4ÔB1010_0101 0xA5ÕB1010_0110 0xA6ÖB1010_0111 0xA7×B1010_1000 0xA8ØB1010_1001 0xA9ÙB1010_1010 0xAAÚB1010_1011 0xABÛB1010_1100 0xACÜB1010_1101 0xADÝB1010_1110 0xAEÞB1010_1111 0xAFàB1011_0000 0xB0áB1011_0001 0xB1âB1011_0010 0xB2ãB1011_0011 0xB3äB1011_0100 0xB4åB1011_0101 0xB5æB1011_0110 0xB6çB1011_0111 0xB7èB1011_1000 0xB8éB1011_1001 0xB9êB1011_1010 0xBAëB1011_1011 0xBBìB1011_1100 0xBCíB1011_1101 0xBDîB1011_1110 0xBEïB1011_1111 0xBFñB1100_0000 0xC0òB1100_0001 0xC1óB1100_0010 0xC2ôB1100_0011 0xC3õB1100_0100 0xC4öB1100_0101 0xC5÷B1100_0110 0xC6øB1100_0111 0xC7ùB1100_1000 0xC8úB1100_1001 0xC9ûB1100_1010 0xCAüB1100_1011 0xCBýB1100_1100 0xCCþB1100_1101 0xCDÿB1100_1110 0xCEB1100_1111 0xCFB1101_0000 0xD0B1101_0001 0xD1B1101_0010 0xD2B1101_0011 0xD3B1101_0100 0xD4B1101_0101 0xD5B1101_0110 0xD6B1101_0111 0xD7B1101_1000 0xD8B1101_1001 0xD9B1101_1010 0xDAB1101_1011 0xDBB1101_1100 0xDCB1101_1101 0xDDB1101_1110 0xDEB1101_1111 0xDFB1110_0000 0xE0B1110_0001 0xE1B1110_0010 0xE2B1110_0011 0xE3B1110_0100 0xE4B1110_0101 0xE5B1110_0110 0xE6B1110_0111 0xE7B1110_1000 0xE8B1110_1001 0xE9B1110_1010 0xEAB1110_1011 0xEBB1110_1100 0xEC B1110_1101 0xED¡B1110_1110 0xEE¢B1110_1111 0xEF¤B1111_0000 0xF0¥B1111_0001 0xF1¦B1111_0010 0xF2§B1111_0011 0xF3¨B1111_0100 0xF4©B1111_0101 0xF5ªB1111_0110 0xF6«B1111_0111 0xF7¬B1111_1000 0xF8B1111_1001 0xF9®B1111_1010 0xFA¯B1111_1011 0xFB°B1111_1100 0xFC±B1111_1101 0xFD²B1111_1110 0xFE³B1111_1111 0xFF4* ..\Core\bintohex.h´
..\Core\bintohex.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM__DEFINEALL_H__ RCHFCLKCFG 8clkmode 1SYSCLKdef CMU_RCHFCR_FSEL_8MHZ5uint08 uint8_t6uint8 uint8_t8uint16 uint16_t9uint32 uint32_t:int08 int8_t;int16 int16_t<int32 int32_tCIN_NORMAL 0DIN_PULLUP 1IOUT_PUSHPULL 0JOUT_OPENDRAIN 1QALTFUN_NORMAL 0RALTFUN_OPENDRAIN 1SALTFUN_PULLUP 2TALTFUN_OPENDRAIN_PULLUP 3XYZ[\]^_    ý ..\Core\..\Core\Include\D:\Keil5\ARM\ARMCC\Bin\..\include\..\Hardware\CLOCK\..\Hardware\DELAY\define_all.hFM33A0XXEV.hfm33a0xxev_include_all.hstdio.hstdint.hstring.hbintohex.huser_init.hdelay.h
..\Core\define_all.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMunsigned charSÜB08¶Bit!PB08_BitÇ-SUCCESS_0ERROR_1PErrorStatus_STM32ë3*!bit0¶#!bit1¶#!bit2¶#!bit3¶#!bit4¶#!bit5¶#!bit6¶#!bit7¶#__USER_INIT_H__ XN ..\Hardware\CLOCK\..\Core\user_init.hdefine_all.hÀ
..\Hardware\CLOCK\user_init.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM    
_DELAY_H_ SYSTICK_CLOCK_SOURCE_SCLK 0xFFFFFF3FSYSTICK_CLOCK_SOURCE_LSCLK 0xFFFFFF7FSYSTICK_CLOCK_SOURCE_RFU 0xFFFFFFBF    SYSTICK_CLOCK_SOURCE_SYSCLK 0xFFFFFFFFSYSTICK_CLOCK_SOURCE_U_SCLK 0x00000000SYSTICK_CLOCK_SOURCE_U_LSCLK 0x00000040 SYSTICK_CLOCK_SOURCE_U_RFU 0x00000080SYSTICK_CLOCK_SOURCE_U_SYSCLK 0x000000C0SYSCLOCK_U 12000000\Q ..\Hardware\DELAY\..\Drivers\delay.hfm33a0xxev_cmu.hà
..\Hardware\DELAY\delay.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMintNÉ»"ÂPConditionHookÉ __READDEVICEDATA_H SIZHUMODBUS1 0x0101 SIZHUMODBUS2 0x0102SIZHUMODBUSV2_0 0x0104TIANXINCUSTOM 0x0200TIANXINMODBUS 0x0201TIANXINMODBUSA4 0x0202TIANXINMODBUSA6 0x0203TIANXINMODBUSA3 0x0204TIANXINMODBUSTFC 0x0205TIANXINMODBUSTUA 0x0206TIANXINMODBUSTUFC 0x0207TIANXINMODBUSTUF 0x0208EKMODBUS 0x0300EKMODBUS_M_SONIC 0x0301 CANGNANCUSTOM 0x0400!CANGNANMODBUSV2_0 0x0401"CANGNANMODBUSV3_1 0x0402#CANGNANMODBUSV1_3 0x0403%XINKECUSTOM 0x0500&XINKEMODBUS1 0x0501'XINKEMODBUS2 0x0502)SICK500MODBUS 0x0600*SICK_X_C 0x0601+SICK_X_P 0x0602-ASMODBUS 0x0701.AS100MODBUS 0x07020CDLC_LC_MODBUS_V2_8 0x08012YUSHUNMODBUS 0x09014CHUANGSHENG_MODBUS 0x10016AEROSPACE_POWER 0x11017AEROSPACE_POWER_NO_TP 0x11029SINOTOMODBUS 0x1201;SIARGO_MODBUS 0x1301<DEWEN_IGSM_MODBUS 0x1401=DEWEN_PTZ_BOX_5_0 0x1402?HADE_MODBUS 0x1501@HADE_MODBUS_RTU1 0x1502AHADE_MODBUS_RTU2 0x1503CANJUN_MODBUSV1_0 0x1601EYINGYUNCUSTOM 0X1700FYINGYUN_MODBUS 0X1701HSIDASIYI_MODBUS 0x1801IZHENLANMODBUS 0X1901JZHONGHEWEISI_MODBUS 0X2001LTIANJIN_WU_JICHAUNG_CUSTOM 0X2201NLIQING_LQUA_MODBUS 0X2301PAIKE_AKCL_2S_MODBUS 0X2401TREPEATNUM 3UREPEATUNIT 3VBEATTIME 60WMODBUS_WAIT 0X05XMODBUS_TX 0X06ZLLJRXDBOUND 0XFF\P ..\Pre_Drivers\..\Core\ReadDeviceData.hdefine_all.h
..\Pre_Drivers\ReadDeviceData.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMunsigned charPFRAMErg*®HandleStepÁ#RepeadNumÁ#RepeadTimeÁ#dataAddressV#PMODBUS_LLJßp*Þ8u16MeterTypeCode#u8BaudRateCode#u8RS485Parity#u8EXPVoltageCode#u8LowPowerAlarmLine#u8slaveAddress#Vbt_Flag#decoding_Type#u8deviceAdress#    u32VTAddr#u32VbTAddr#u32VbT2Addr#u32PMESAddr#u32TMESAddr#u32QAddr# u32QbAddr#$u32P_Bar#(u32FlowData#,VT_permission#0VbT_permission#1Q_permission#2Qb_permission#3TEMP_permission#4PRES_permission#5PPARM_ACCESS@*ÿÁÿUartBuffw#ÁÿHandBuff#WritePtrÁ#HandlePtrÁ#TempPtrÁ#NewLenÁ#DataLenÁ#__math_h __ARMCLIB_VERSION 5060037 __LONGLONG long long,__USE_C99_MATH 10_ARMABI __declspec(__nothrow)4_ARMABI_SOFTFP __declspec(__nothrow) __attribute__((__pcs__("aapcs")))5__HAVE_LONGDOUBLE 17_ARMABI_PURE __declspec(__nothrow) __attribute__((const));_ARMABI_FPEXCEPT _ARMABI __attribute__((const))B_ARMABI_INLINE static __inlineC_ARMABI_INLINE_DEF static __inlineO_SOFTFP __attribute__((__pcs__("aapcs")))h__FLT(x) (*(unsigned *)&(x))m__HI(x) (*(1 + (unsigned *)&(x)))n__LO(x) (*(unsigned *)&(x))r__MATH_DECLS Ý__CLIBNSä__CLIBNS é__has_builtin(x) 0öHUGE_VALF ((float)__INFINITY__)÷HUGE_VALL ((long double)__INFINITY__)øINFINITY ((float)__INFINITY__)ùNAN (__ESCAPE__(0f_7FC00000))üMATH_ERRNO 1ýMATH_ERREXCEPT 2HUGE_VAL ((double)__INFINITY__)Ëfpclassify(x) ((sizeof(x) == sizeof(float)) ? __ARM_fpclassifyf(x) : __ARM_fpclassify(x))ÑFP_ZERO (0)ÒFP_SUBNORMAL (4)ÓFP_NORMAL (5)ÔFP_INFINITE (3)ÕFP_NAN (7)ôFP_ILOGB0 (-0x7fffffff)õFP_ILOGBNAN ( 0x80000000)÷isfinite(x) ((sizeof(x) == sizeof(float)) ? __ARM_isfinitef(x) : __ARM_isfinite(x))ÿisgreater(x,y) (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) ? ((__ARM_fcmp4((x), (y)) & 0xf0000000) == 0x20000000) : ((__ARM_dcmp4((x), (y)) & 0xf0000000) == 0x20000000))isgreaterequal(x,y) (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) ? ((__ARM_fcmp4((x), (y)) & 0x30000000) == 0x20000000) : ((__ARM_dcmp4((x), (y)) & 0x30000000) == 0x20000000))isinf(x) ((sizeof(x) == sizeof(float)) ? __ARM_isinff(x) : __ARM_isinf(x))isless(x,y) (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) ? ((__ARM_fcmp4((x), (y)) & 0xf0000000) == 0x80000000) : ((__ARM_dcmp4((x), (y)) & 0xf0000000) == 0x80000000))¥islessequal(x,y) (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) ? ((__ARM_fcmp4((x), (y)) & 0xc0000000) != 0) : ((__ARM_dcmp4((x), (y)) & 0xc0000000) != 0))¯islessgreater(x,y) (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) ? __ARM_islessgreaterf((x), (y)) : __ARM_islessgreater((x), (y)))¹isnan(x) ((sizeof(x) == sizeof(float)) ? __ARM_isnanf(x) : __ARM_isnan(x))Áisnormal(x) ((sizeof(x) == sizeof(float)) ? __ARM_isnormalf(x) : __ARM_isnormal(x))Éisunordered(x,y) (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) ? ((__ARM_fcmp4((x), (y)) & 0x10000000) == 0x10000000) : ((__ARM_dcmp4((x), (y)) & 0x10000000) == 0x10000000))¥signbit(x) ((sizeof(x) == sizeof(float)) ? __ARM_signbitf(x) : __ARM_signbit(x))Ê_ARMDEFLD1(f) _ARMABI long double f ## l(long double )Í_ARMDEFLD1P(f,T) _ARMABI long double f ## l(long double , T )Ð_ARMDEFLD2(f) _ARMABI long double f ## l(long double , long double )ì_ARMDEFLD1í_ARMDEFLD1Pî_ARMDEFLD2¦
__LONGLONGL@ D:\Keil5\ARM\ARMCC\Bin\..\include\math.hÌD:\Keil5\ARM\ARMCC\Bin\..\include\math.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]floatdoubleintunsigned intlong doublelonglong longcharPfloat_tîPdouble_tïqmath_errhandlingý;Ê'__ARM_isfinitef$__xa__result;û'__ARM_isfinite$__xa__result;ª'__ARM_isinff$__xa__result;Ø'__ARM_isinf$__xa__result;¥'__ARM_islessgreaterf$__x$__ya__result\__f ;åª'__ARM_islessgreater$__x$__ya__result\__f ;´'__ARM_isnanf$__xa__result;Ë¸'__ARM_isnan$__xa__result\__xf ;À'__ARM_isnormalf$__xa__result\__xe ;ÀÅ'__ARM_isnormal$__xa__result\__xe ;ñÍ'__ARM_signbitf$__xa__result;¡Ñ'__ARM_signbit$__xa__result;Éò_sqrt$__xa__result;ò÷_sqrtf$__xa__result;¥¯$copysign$__x$__ya__result;Ù·#copysignf$__x$__ya__result;    ±#fabsf$__fa__result;¸    ¦$fmal°$°__x$°__y$°__za__result°;á    µlrintl¿$°__xa__result¿;
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Ç#llroundlÇ$°__xa__resultÇ;Í)nanl°$__ta__result°Ô";ÉÞremquol°$°__x$°__y$É__qa__result°"#Ðmath_errhandling__ADC_H const_adc_Slope (*((uint16_t *)(0x1FFFFA88)))const_adc_Offset (*((int16_t *)(0x1FFFFA8A)))const_T_30 *(uint16_t *)0x1FFFFA92const_T_30_14BIT *(uint16_t *)0x1FFFFB54AD_ALKA_BAT_REF_VOL 3.3AD_ALKA_BAT_CH 12AD_ALKA_BAT_CNT 26ALKA_VOL_COE 3.5AD_LITH_BAT_REF_VOL 3.3AD_LITH_BAT_CH 5AD_LITH_BAT_CNT 26LITH_VOL_COE 4.3PF ..\Pre_Drivers\..\Core\1ADC.hdefine_all.h 
..\Pre_Drivers\1ADC.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM)ad_data_getlÒ1ad_get_address_pÇ#ad_buffer_cnt#dad_ch#hPad_data_s·$__PARA_H FIRMWARE_VER_1 0x0000    FIRMWARE_VER_2 0x0102
FIRMWARE_VER_3 0x0407__UPPER_DATA_ALTER(__LAST__,__NOW__) ((__LAST__ != __NOW__) ? SET : RESET)READSUCCESSFULLYTIMES 3READFAILEDTIMES 200PULSE_MODE 0x01RS485_MODE 0x02RS485_AND_PULSE_MODE 0x03ACTIVE 1NOACTIVE 0HOST_COMPUTER_DATA_INDEX 3FLOW_LOW_PWR_ALARM_CODE 0x0101 FLOW_UNDER_VOLTAGE_ALARM_CODE 0x0102!FLOW_PWR_DOWN_ALARM_CODE 0x0103"ALKA_PWR_DOWN_ALARM_CODE 0x0104#LITH_PWR_DOWN_ALARM_CODE 0x0105$EXTERNAL_PWR_ACCESS_ALARM_CODE 0x0106%EXTERNAL_PWR_DOWN_ALARM_CODE 0x0107&ALKA_PWR_LOW_ALARM_CODE 0x0108'LITH_PWR_LOW_ALARM_CODE 0x0109)PULSE_LINE_DISCONNECTED_ALARM_CODE 0x0201*FORCED_TO_CLOSE_VALVE_ALARM_CODE 0x0202+VALVE_OPEN_ALARM_CODE 0x0203,VALVE_ABNORMAL_ALARM_CODE 0x0204-VALVE_FORCE_OPEN_ALARM_CODE 0x0205.PULSE_LINE_MISMATCH_ALARM_CODE 0xfff1/GAS_LEAK_ALARM_CODE 0x02081RS485_READ_FLOW_FAILED_ALARM_CODE 0x03012RS485_READ_ABNORMAL_SMALL_READING_CODE 0x03024TEMPERATURE_ABNORMAL_ALARM_CODE 0x04015PRESSURE_ABNORMAL_ALARM_CODE 0x04027AMOUNT_SMALL_ALARM_CODE 0x05018AMOUNT_ARREARS_ALARM_CODE 0x05029AMOUNT_OVERDRAFT_ALARM_CODE 0x0503;E2RW_READ_ABNORMAL_ALARM_CODE 0x0701<E2RW_WRITE_ABNORMAL_ALARM_CODE 0x0702>CAP_OPEN_ALARM_CODE 0x0802DDeviceAddress_Addr 0x0004ETyf_Addr 0x0012FTy_Addr 0x0014GTyp_Addr 0x0016HTp_Addr 0x0018JTime1_Flag_Addr 0x001CKSendTiming_Hour_Addr 0x001DLSendTiming_Min_Addr 0x001EMTime2_Flag_Addr 0x001FNSendTiming_Hour2_Addr 0x0020OSendTiming_Min2_Addr 0x0021PGPRS_RestartTime_Addr 0x0022QIP_Addr 0x0028SNumDataStored_Addr 0x0037TDataStoredFlag_Addr 0x003CVKVER_ADDR 62WKEY_ADDR 64YREALTIME_CUMULATIVE_GAS_USAGE_ADDR 80ZREALTIME_CUMULATIVE_FEE_USAGE_ADDR 88[REALTIME_BALANCE_ADDR 96^DATA_OBTAIN_TYPE_ADDR 104_PULSE_COE_ADDR 108`BILLING_TYPE_ADDR 112aSINGLE_BILLING_FEE_ADDR 113bSTEP_BILLING_FIRST_ADDR 117cSTEP_BILLING_FEE_FIRST_ADDR 121dSTEP_BILLING_SECOND_ADDR 125eSTEP_BILLING_FEE_SECOND_ADDR 129fSTEP_BILLING_THIRD_ADDR 133gSTEP_BILLING_FEE_THIRD_ADDR 137hBALANCE_INSUF_ALARM_AMOUNT_ADDR 141iCREDITS_ADDR 145kMETER_TYPE_CODE_ADDR 149mPULSE_WITDH_ADDR 151oACCOUNT_STATUS_ADDR 155qBAUD_RATE_CODE_ADDR 156rRS485_PARITY_ADDR 157sEXP_VOLTAGE_CODE_ADDR 158tLOW_POWER_ALARM_LINE_ADDR 159uSLAVE_ADDRESS_ADDR 160wSHOW_BALANCE_FLAG_ADDR 161xSHOW_PRICE_FLAG_ADDR 162zLCD_LOGO_ADDR 169{LCD_FLAG_ADDR 170|LOGO_DISPLAY_FLAG_ADDR 171}OPEN_VALVE_AUTHORIZE_FLAG_ADDR 172~OPEN_VALVE_AUTHORIZE_TIME_CNT_ADDRA 173VALVE_STATE_ADDR 177VALVE_TYPE_ADDR 178DeviceserialNum1_ADDR 200DeviceserialNum2_ADDR 202DeviceserialNum3_ADDR 204DeviceserialNum4_ADDR 206HardwareVerSn1_ADDR 208HardwareVerSn2_ADDR 210HardwareVerSn3_ADDR 212FirmwareVerSn1_ADDR 214FirmwareVerSn2_ADDR 216FirmwareVerSn3_ADDR 218FirmwareCRC_ADDR 220FirmwareDateyear_ADDR 222FirmwareDatemonth_ADDR 224FirmwareDateday_ADDR 226EquipmentCaliberAndModel_ADDR 228RS485_SETTLEMENT_FLAG_ADDR 299DATA_READABLE_FLAG_ADDR 300SCACC_BIL_ADDR 301BALANCE_BIL_ADDR 305GAS_USAGE_BIL_ADDR 313FEE_USAGE_BIL_ADDR 321TIME_BIL_ADDR 329¢REALTIME_CUMULATIVE_GAS_USAGE_B_ADDR 350£REALTIME_CUMULATIVE_FEE_USAGE_B_ADDR 358¤REALTIME_BALANCE_B_ADDR 366¦E2RW_READ_ABNORMAL_FLAG_ADDR 375§E2RW_WRITE_ABNORMAL_FLAG_ADDR 376©VALVE_OPEN_TIMES_ADDR 925ªVALVE_CLOSE_TIMES_ADDR 927¬REALTIME_CUMULATIVE_GAS_USAGE_C_ADDR 970REALTIME_CUMULATIVE_FEE_USAGE_C_ADDR 978®REALTIME_BALANCE_C_ADDR 986°NumStoredLength 750±WCACC_addr 0x03E8²SCACC_addr 0x1068³PRE_addr 0x1CE8´TEM_addr 0x2968µWCINS_addr 0x35E8¶SCINS_addr 0x4268·SCCor_addr 0x4EE8¹YEAR_addr 0x5B68ºMONTH_addr 0x5E88»DAY_addr 0x61A8¼HOUR_addr 0x64C8½MIN_addr 0x67E8¾SEC_addr 0x6B08ÀBAT_LITH_addr 0x6E28ÂBAT_ALKA_addr 0x6E2CÃBAT_EX_addr 0x6E30ÅCUMULATIVE_GAS_USAGE_ADDR 31400ÆCUMULATIVE_FEE_USAGE_ADDR 37400ÇBALANCE_ADDR 43400ÊCURRENT_BIL_RECORD_NUM_ADDR 49990ËBIL_RECORD_FULL_FLAG_ADDR 49992ÌFIRST_BIL_RECORD_ADDR 50000ÎBIL_RECORD_LENGTH 100ÏBIL_RECORD_NUM 100ÒCURRENT_ALARM_RECORD_NUM_ADDR 60000ÓALARM_RECORD_FULL_FLAG_ADDR 60002ÔFIRST_ALARM_RECORD_ADDR 60004ÖALARM_RECORD_LENGTH 9×ALARM_RECORD_NUM 1000ÚCUMULANTS_MODIFY_RECORD_NUM_ADDR 70000ÛCUMULANTS_MODIFY_RECORD_FULL_FLAG_ADDR 70002ÜFIRST_CUMULANTS_MODIFY_RECORD_ADDR 70004ÞCUMULANTS_MODIFY_RECORD_LENGTH 50ßCUMULANTS_MODIFY_RECORD_NUM 50áMODBUS_SLAVE_ADDR 75000äBALANCE_SAVE_TYPE_ADDR 75002 VALVE_ABNORMAL_THRESHOLD 3\P ..\Pre_Drivers\..\Core\para.hdefine_all.h1ADC.h
..\Pre_Drivers\para.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMfloatdoubleintcharPLLJ_DATAù*ÿ Tyf8#Tf8#Typ8#Tp8#sampling_TimeV#time1_flag8#sendTiming_hour8#sendTiming_min8#time2_flag8#    sendTiming_hour28#
sendTiming_min28#GPRS_RESTARTTIME8#real_sendTiming_hour8# real_sendTiming_min8#real_sendTiming_day8#RTC_sendTiming_hour8#RTC_sendTiming_min8#RTC_sendTiming_day8#AccountStatus8#TestStatus8#Hour_Updata_flag8#Key_Power_Det8#Logo_Display_Flag8#Sample_Min_Time#Sample_Interval#Send_Interval#show_balance_flag#show_price_flag#PDEVICE_PARMê¬*Ialarm_l8#u16AlarmStoreNumV#u8AlarmStoreFullFlag8#alarm_Sample8#alarm_PRE8#alarm_TEM8#alarm_FlowPowerLOW8#alarm_FlowUnderPower8#alarm_FlowPowerDOWN8#    alarm_AlkaPowerDOWN8#
alarm_AlkaPowerLOW8#alarm_LithPowerDOWN8#alarm_LithPowerLOW8# alarm_EXPowerIN8#alarm_EXPowerRemove8#alarm_Pulse_Broken8#alarm_Pulse_Dismatch8#alarm_Valve_close8#alarm_Valve_open8#alarm_Valve_Abnormal8#alarm_Gas_Leak8#alarm_Gas_Leak_time8#alarm_Balance_Small8#alarm_Balance_08#alarm_Credits_08#alarm_Credits_0TimesV#alarm_E2RW_read_abnormal8#alarm_E2RW_write_abnormal8#alarm_Cap_OPEN8#alarm_Valve_Force_Open8#fTempratureLowLimit·# fTempratureHighLimit·#$fPressureLowLimit·#(fPressureHighLimit·#,u8ReadfailedTimes8#0u8ReadSuccessfullyTimes8#1alarm_Send_failed_time8#2Data_Send_failed_time8#3alarm_Valve_Abnormal_time8#4alarm_RS485_Abnormal_Small_Reading8#5u8PulseBrokenTimes8#6alarm_FlowPowerLOW_time8#7alarm_AlkaPowerLow_LCDFLAG8#8alarm_LithPowerLow_LCDFLAG8#9alarm_AlkaPowerDOWN_LCDFLAG8#:alarm_LithPowerDOWN_LCDFLAG8#;alarm_Pulse_Broken_LCDFLAG8#<alarm_Pulse_Dismatch_LCDFLAG8#=alarm_Gas_Leak_LCDFLAG8#>alarm_Sample_LCDFLAG8#?alarm_PRE_LCDFLAG8#@alarm_TEM_LCDFLAG8#Aalarm_Balance_Small_LCDFLAG8#Balarm_RS485Cardinalityfree_LCDFLAG8#Calarm_E2RW_read_abnormal_FLAG8#Dalarm_E2RW_write_abnormal_FLAG8#Ealarm_RS485_Abnormal_Small_Reading_FLAG8#Falarm_Cap_OPEN_LCDFALG8#Galarm_FlowPowerLOW_FLAG8#HPSYSTEM_ALARMø*«u16BilRecordNUMV#u8BilStoreFullFlag8#u16CumulantsRecordNUMV#u8CumulantsStoreFullFlag8#PSYSTEM_RECORD°
)Ôparameter_bil5cDataObtainType#u8PulseWidth#fPulseCoefficient·#cBillingType#fSingleBillingFee·#fStepBilling_First·#fStepBillingFee_First·#fStepBilling_Second·#fStepBillingFee_Second·#fStepBilling_Third·#fStepBillingFee_Third·#s32RechargeAmountÊ##dRechargeAmountÀ#'iBalanceInsufAlarmAmountV#/fCredits·#1PPARAMETER_BILA)ïvalve_abnormal_paravalveCloseFirstCumÀ#valveCloseFirstFlag#valveCloseNextCumÀ#    valveCloseNextFlag#PVALVE_ABNORMAL_PARAê©*ßVhardwareVerSn #ºVfirmwareVer¯ #firmwareCRCV#firmwareVerDate_yearV#firmwareVerDate_monthV#firmwareVerDate_dayV#EquipmentCaliberAndModel8#PdeviceSerialNum_t º*«slave_time_flag#slave_addr#PMODBUS_DEV_PARAyÀt_qregDevSerialNumÃqTime_For_valve_openVqTime_For_wakeupVqLCD_sleepTimeVqLCD_flag8qLOGO_Flag8qk_indexfqflag8qbegin8qLPM3_FLAG8qnumÊqsleepTimeÊqtotal_dataGroupNum8qyushu8qFirstTimeRunFlag8íÑqDebugãqdevice_Parmqparameter_bilÔqsystem_alarm
qsystem_record+qRS485_statusqBT_statustqad_data_gmtÙqLLJ_data_gqPower_ON_cntqPower_ON_flagt«qmodbus_dev_paraÃqvalve_abnormal_para_go )&LLJ_dataPyearV#month8#date8#hour8#min8#sec8#Lith_Battery_V·#Alka_Battery_V·#EX_Battery_V·#Meter_Battery_V·#MeterBatVoltagePercent#SC_Accumulation·#WC_Accumulation·#SC_Accumulation_longf# WC_Accumulation_longf#$SC_Accumulation_doubleÀ#(WC_Accumulation_doubleÀ#0SC_Weight_Factor#8WC_Weight_Factor#:Temperature·#<Pressure·#@SC_instant·#DWC_instant·#HKB_battery_Q·#LÐÇregDevSerialNumÝTime_For_valve_openùTime_For_wakeupLCD_sleepTime'LCD_flag8LOGO_FlagJk_indexZflaggbeginuLPM3_FLAGnumsleepTime¡total_dataGroupNum¼yushuÊFirstTimeRunFlagíDebugùdevice_Parmparameter_bilsystem_alarm2system_recordFRS485_status[BT_statussad_data_gLLJ_data_gPower_ON_cntPower_ON_flagÇmodbus_dev_paraÝvalve_abnormal_para_g !_SPI_H_ SPI0_PORT GPIOF    SPI0_MOSI_PIN GPIO_Pin_12
SPI0_MISO_PIN GPIO_Pin_13SPI0_SCK_PIN GPIO_Pin_14 SPI0_CS_PORT GPIOESPI0_CS1_PIN GPIO_Pin_8SPI0_CS2_PIN GPIO_Pin_6PF ..\Hardware\SPI\..\Core\spi.hdefine_all.h¸
..\Hardware\SPI\spi.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM#$%&_E2P_H_ EEPROM_PHYS_SIZE (256 * 1024)
EEPROM_CFG_BLOCK_SIZE 4096EEPROM_CFG_BLOCK_CNT (EEPROM_PHYS_SIZE / EEPROM_CFG_BLOCK_SIZE)EEPROM_PHYS_START_ADDR 0FM_WREN 0x06FM_WRDI 0x04FM_RDSR 0x05FM_WRSR 0x01FM_READ 0x03FM_FSTRD 0x0bFM_WRITE 0x02FM_SLEEP 0xb9FM_RDID 0x9fE2P_PWR_PORT GPIOFE2P_PWR_PIN GPIO_Pin_15 E2P_CS1_PORT SPI0_CS_PORT!E2P_CS1_PIN SPI0_CS1_PIN$E2P_CS2_PORT SPI0_CS_PORT%E2P_CS2_PIN SPI0_CS2_PIN(E2P_PWR_ON GPIO_ResetBits(E2P_PWR_PORT,E2P_PWR_PIN))E2P_PWR_OFF GPIO_SetBits(E2P_PWR_PORT,E2P_PWR_PIN)+E2P_CS1_L GPIO_ResetBits(E2P_CS1_PORT,E2P_CS1_PIN),E2P_CS1_H GPIO_SetBits(E2P_CS1_PORT,E2P_CS1_PIN).E2P_CS2_L GPIO_ResetBits(E2P_CS2_PORT,E2P_CS2_PIN)/E2P_CS2_H GPIO_SetBits(E2P_CS2_PORT,E2P_CS2_PIN)<FM_ReadWriteByte(dat) SpiWriteAndRead(dat)l` ..\Function\E2P\..\Core\..\Hardware\SPI\e2p.hdefine_all.hspi.h
..\Function\E2P\e2p.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMdoublefloatPdouble_unñESüfloÁò8dataçPfloat_unÛKS¯uiof¥8dataPu32_unRSàusoVÖ8dataKPu16_un=X*Ätest_u88#test_u16V#test_u32f#test_fÁ#test_d·#PE2P_TEST_DATA_Tnaqe2p_test_data_gÄSdou·8dataý"Ûe2p_test_data_g()*+__EX_RTC_H_ RX8025_ADDR_READ 0x65RX8025_ADDR_WRITE 0x64TH ..\Pre_Drivers\..\Core\ex_rtc.hdefine_all.h
..\Pre_Drivers\ex_rtc.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM*hour#min#sec#month#date#week#year#Pcalendar_obj¹*yearN8#monthN8#dateN8#hourN8#minN8#secN8#PNETTIME3qcalendarqnet_now_timeqSending_flag8qLast_Send_D8qLast_Send_H8qLast_Send_M8qLast_Sample_D8qLast_Sample_H8qLast_Sample_M8qNext_real_Sample_D8qNext_real_Sample_H8qNext_real_Sample_M8qNext_Sample_D8qNext_Sample_H8qNext_Sample_M8qRTC_corqRTC_Setting_Flag? calendar¯net_now_timeÂSending_flag×Last_Send_DëLast_Send_HÿLast_Send_MLast_Sample_D)Last_Sample_H?Last_Sample_MUNext_real_Sample_DpNext_real_Sample_HNext_real_Sample_M¦Next_Sample_D¼Next_Sample_HÒNext_Sample_MèRTC_corøRTC_Setting_Flag-./__DATA_WRITE_LOCAL_H DeviceAddress_Addr 0x0004    Tyf_Addr 0x0012
Ty_Addr 0x0014Typ_Addr 0x0016Tp_Addr 0x0018Time1_Flag_Addr 0x001CSendTiming_Hour_Addr 0x001DSendTiming_Min_Addr 0x001ETime2_Flag_Addr 0x001FSendTiming_Hour2_Addr 0x0020SendTiming_Min2_Addr 0x0021GPRS_RestartTime_Addr 0x0022IP_Addr 0x0028NumDataStored_Addr 0x0037DataStoredFlag_Addr 0x003CKVER_ADDR 62KEY_ADDR 64REALTIME_CUMULATIVE_GAS_USAGE_ADDR 80REALTIME_CUMULATIVE_FEE_USAGE_ADDR 88REALTIME_BALANCE_ADDR 96"DATA_OBTAIN_TYPE_ADDR 104#PULSE_COE_ADDR 108$BILLING_TYPE_ADDR 112%SINGLE_BILLING_FEE_ADDR 113&STEP_BILLING_FIRST_ADDR 117'STEP_BILLING_FEE_FIRST_ADDR 121(STEP_BILLING_SECOND_ADDR 125)STEP_BILLING_FEE_SECOND_ADDR 129*STEP_BILLING_THIRD_ADDR 133+STEP_BILLING_FEE_THIRD_ADDR 137,BALANCE_INSUF_ALARM_AMOUNT_ADDR 141-CREDITS_ADDR 145/METER_TYPE_CODE_ADDR 1491PULSE_WITDH_ADDR 1513ACCOUNT_STATUS_ADDR 1555BAUD_RATE_CODE_ADDR 1566RS485_PARITY_ADDR 1577EXP_VOLTAGE_CODE_ADDR 1588LOW_POWER_ALARM_LINE_ADDR 1599SLAVE_ADDRESS_ADDR 160;SHOW_BALANCE_FLAG_ADDR 161<SHOW_PRICE_FLAG_ADDR 162>LCD_LOGO_ADDR 169?LCD_FLAG_ADDR 170@LOGO_DISPLAY_FLAG_ADDR 171AOPEN_VALVE_AUTHORIZE_FLAG_ADDR 172BOPEN_VALVE_AUTHORIZE_TIME_CNT_ADDRA 173CVALVE_STATE_ADDR 177DVALVE_TYPE_ADDR 178FDeviceserialNum1_ADDR 200GDeviceserialNum2_ADDR 202HDeviceserialNum3_ADDR 204IDeviceserialNum4_ADDR 206KHardwareVerSn1_ADDR 208LHardwareVerSn2_ADDR 210MHardwareVerSn3_ADDR 212OFirmwareVerSn1_ADDR 214PFirmwareVerSn2_ADDR 216QFirmwareVerSn3_ADDR 218SFirmwareCRC_ADDR 220UFirmwareDateyear_ADDR 222VFirmwareDatemonth_ADDR 224WFirmwareDateday_ADDR 226XEquipmentCaliberAndModel_ADDR 228\RS485_SETTLEMENT_FLAG_ADDR 299]DATA_READABLE_FLAG_ADDR 300^SCACC_BIL_ADDR 301_BALANCE_BIL_ADDR 305`GAS_USAGE_BIL_ADDR 313aFEE_USAGE_BIL_ADDR 321cTIME_BIL_ADDR 329fREALTIME_CUMULATIVE_GAS_USAGE_B_ADDR 350gREALTIME_CUMULATIVE_FEE_USAGE_B_ADDR 358hREALTIME_BALANCE_B_ADDR 366jE2RW_READ_ABNORMAL_FLAG_ADDR 375kE2RW_WRITE_ABNORMAL_FLAG_ADDR 376mVALVE_OPEN_TIMES_ADDR 925nVALVE_CLOSE_TIMES_ADDR 927pREALTIME_CUMULATIVE_GAS_USAGE_C_ADDR 970qREALTIME_CUMULATIVE_FEE_USAGE_C_ADDR 978rREALTIME_BALANCE_C_ADDR 986tNumStoredLength 750uWCACC_addr 0x03E8vSCACC_addr 0x1068wPRE_addr 0x1CE8xTEM_addr 0x2968yWCINS_addr 0x35E8zSCINS_addr 0x4268{SCCor_addr 0x4EE8}YEAR_addr 0x5B68~MONTH_addr 0x5E88DAY_addr 0x61A8HOUR_addr 0x64C8MIN_addr 0x67E8SEC_addr 0x6B08BAT_LITH_addr 0x6E28BAT_ALKA_addr 0x6E2CBAT_EX_addr 0x6E30CUMULATIVE_GAS_USAGE_ADDR 31400CUMULATIVE_FEE_USAGE_ADDR 37400BALANCE_ADDR 43400CURRENT_BIL_RECORD_NUM_ADDR 49990BIL_RECORD_FULL_FLAG_ADDR 49992FIRST_BIL_RECORD_ADDR 50000BIL_RECORD_LENGTH 100BIL_RECORD_NUM 100CURRENT_ALARM_RECORD_NUM_ADDR 60000ALARM_RECORD_FULL_FLAG_ADDR 60002FIRST_ALARM_RECORD_ADDR 60004ALARM_RECORD_LENGTH 9ALARM_RECORD_NUM 1000CUMULANTS_MODIFY_RECORD_NUM_ADDR 70000CUMULANTS_MODIFY_RECORD_FULL_FLAG_ADDR 70002 FIRST_CUMULANTS_MODIFY_RECORD_ADDR 70004¢CUMULANTS_MODIFY_RECORD_LENGTH 50£CUMULANTS_MODIFY_RECORD_NUM 50¥MODBUS_SLAVE_ADDR 75000¨BALANCE_SAVE_TYPE_ADDR 75002LC ..\Pre_Drivers\data_write_local.hpara.hÄ
..\Pre_Drivers\data_write_local.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM1234__GPRS_H VAR_RESET_PASSWORD 7654321UARTGPRSNUM USART3GPRS 0X01SMS 0X02GPRSALIVE 0GPRSNONE 1NOMARL_DATA_GPRS 0X01NOMARL_HEART_BEAT 0X02DEVICE_WARNING 0X03LINKRXDBOUND 0XFFGSM_DATA 0X12RESTARTTIME 300!SYS_WAIT 0X00"SYS_OPEN 0X01#SYS_DATA 0X03$SYS_RESTART 0X04%SYS_WAIT_SIM_OPEN 0X05(dormancy_awaken 0x00)RTC_awaken 0x01*Key_awaken 0x02+Alarm_awaken 0x030PROTOCOL_VERSION 0x322CAMMAND_FLAG_DATAUP 0x84603CAMMAND_FLAG_SET_PARA_DEV 0xA4604CAMMAND_FLAG_READ_PARA_DEV 0xA4615CAMMAND_FLAG_SET_PARA_BIL 0xA4626CAMMAND_FLAG_READ_PARA_BIL 0xA4637CAMMAND_FLAG_SET_TIME 0xA4648CAMMAND_FLAG_MODIFY_KEY 0xA4659CAMMAND_FLAG_VALVE_CONTROL 0xA466:CAMMAND_FLAG_ACCOUNT_STATUS 0xA467;CAMMAND_FLAG_RECHARGE 0xA468<CAMMAND_FLAG_IP_PORT 0xA469=CAMMAND_FLAG_CLEAR_ABNORMAL 0xA46A@CAMMAND_FLAG_ALARM 0x8461ACAMMAND_FLAG_END 0xA450CCONTROL_CODE_DATAUP_UP 0x85DCONTROL_CODE_DATAUP_DOWN 0x05ECONTROL_CODE_SET_PARA_DEV_UP 0x84FCONTROL_CODE_SET_PARA_DEV_DOWN 0x04GCONTROL_CODE_READ_PARA_DEV_UP 0x81HCONTROL_CODE_READ_PARA_DEV_DOWN 0x01ICONTROL_CODE_SET_PARA_BIL_UP 0x84JCONTROL_CODE_SET_PARA_BIL_DOWN 0x04KCONTROL_CODE_READ_PARA_BIL_UP 0x81LCONTROL_CODE_READ_PARA_BIL_DOWN 0x01MCONTROL_CODE_SET_TIME_UP 0x84NCONTROL_CODE_SET_TIME_DOWN 0x04OCONTROL_CODE_VALVE_CONTROL_UP 0x84PCONTROL_CODE_VALVE_CONTROL_DOWN 0x04QCONTROL_CODE_ACCOUNT_STATUS_UP 0x84RCONTROL_CODE_ACCOUNT_STATUS_DOWN 0x04SCONTROL_CODE_RECHARGE_UP 0x84TCONTROL_CODE_RECHARGE_DOWN 0x04UCONTROL_CODE_IP_PORT_UP 0x84VCONTROL_CODE_IP_PORT_DOWN 0x04WCONTROL_CODE_CLEAR_ABNORMAL_UP 0x84XCONTROL_CODE_CLEAR_ABNORMAL_DOWN 0x04[CONTROL_CODE_MODIFY_KEY_UP 0x84\CONTROL_CODE_MODIFY_KEY_DOWN 0x04]CONTROL_CODE_ALARM_UP 0x85^CONTROL_CODE_ALARM_DOWN 0x05_CONTROL_CODE_END_UP 0x81`CONTROL_CODE_END_DOWN 0x01bFIRST_DATA_SHIFT 27dDATA_PACKET_HEADEA_LENGTH 31eDATA_PACKET_DATA_LENGTH 80gFRAME_DATA_MAX 4PG ..\Pre_Drivers\..\Core\1gprs.hdefine_all.hø
 
..\Pre_Drivers\1gprs.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMunsigned charunsigned shortcharfloatPGPRS_PARAMETER1    qPGPRS_SEND_DATAh    PSTRLINK:
*+RebootNum¸#NetLinkFlag¸#HandleStep¸#RepeadNum¸#ED_RepeadNum¸#RepeadTime¸#CmdType¸#netgrade¸#netrate¸#BeatTimeÉ#    WaitTimeÉ#ð¸ServerIPç# ¸ServerPort#¤¸APN#ConnectNum¸#%Net_info¸#&RestartTimeÉ#'send_finish_ok¸#)ReceivedInstructionFlag¸#*PVARIABLE(¨*¬
:Framestart_symbolÛ#Ó8DeviceAddressÈ#Datastart_symbolÛ#    Control_codeÛ#
Data_lengthV#Systemclock_year8# Systemclock_month8#Systemclock_day8#Systemclock_hour8#Systemclock_min8#Systemclock_sec8#Protocol_version8#Cammand_flagV#frameSeqV#totalTSeqV#KVerÛ#Signal_intensity8#ÇÛmoduleSeq>#Send_type8#0Power_type8#1Data_Acq_type8#2Billing_type8#3AccountStatus_g8#4Reserved18#5Reserved28#6Reserved38#7Valve_Status8#8dataGroup_Num8#9PGPRS_PROTOCOL_HEADER«Ê*ÖRSample_year8#Sample_month8#Sample_day8#Sample_hour8#Sample_min8#Sample_sec8#fBalance_xsV#fBalance_zsf#fGasUsageTotal_xsV#fGasUsageTotal_zsf#fGasFeeUsageTotal_xsV#fGasFeeUsageTotal_zsf#SC_Accumulation_xsV#SC_Accumulation_zsf#WC_Accumulation_xsV#WC_Accumulation_zsf# SC_instant_xsV#$SC_instant_zsf#&WC_instant_xsV#*WC_instant_zsf#,Temperatureã#0Pressureã#4Lith_battery_V_xs8#8Lith_battery_V_zs8#9Alka_battery_V_xs8#:Alka_battery_V_zs8#;EX_battery_V_xs8#<EX_battery_V_zs8#=reservation1v#>reservation2v#Freservation3V#NCSÛ#PFrameend_symbolÛ#QPGPRS_DATA_PACKAGEIóqLinkDlgqVariaDlgqgprs_protocol_header,qgprs_data_packageVqCS_addrVqGPRSbeginflag8qawaken_flag8qGPRS_sendFlag88ÖqGPRS_SEND_BUFF    )ègprs_parameterÏipD    #port#*ºdata_send_in_one_min#data_send_mode#data_send_date#data_send_hour#data_send_min#data_send_sec#data_send_min_interval#data_send_frame#*ùÉ¸ÿUartBuff?
#ã¸ÿHandBuffY
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CallNumt
#WritePtr¸#HandlePtr¸#TempPtr¸#NewLen¸#DataLen¸#Gprs_Finish_Flag¸#©ü
pLinkDlg~VariaDlggprs_protocol_header¨gprs_data_packageÀCS_addrÐGPRSbeginflagæawaken_flagúGPRS_sendFlag    GPRS_SEND_BUFF6789__BILLING_H BALANCE_UP_LIMIT 999999999BALANCE_LOWER_LIMIT (-999999999)
GAS_USAGE_UP_LIMIT 4000000000GAS_USAGE_LOWER_LIMIT (-9999999999) FEE_USAGE_UP_LIMIT 4000000000FEE_USAGE_LOWER_LIMIT (-9999999999)TJ ..\Pre_Drivers\..\Core\1billing.hdefine_all.h
..\Pre_Drivers\1billing.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMdoublePSETTLEMENT_PARAò#qSettlement_ParaÅ)Settlement_Para0fCurrentGasUsage»#fCumulativeGasUsage»#fCumulativeFeeUsage»#fBalance»#u32PulseCounting_last# u32PulseCounting#$SettlementStorageFlag#(RS485SettlementFlag#)RS485SettlementINGFlag#*RS485BilDataReadableFlag#+" ÜSettlement_Para;<=>__VALVECONTROL_H SZV101_VALVE 1SZV102_VALVE 2    SZV103_VALVE 3VALVE_TYPE SZV102_VALVEVALVE_OPEN_TIME_LIMIT 350XO ..\Pre_Drivers\..\Core\1ValveControl.hdefine_all.hh
..\Pre_Drivers\1ValveControl.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMunsigned charqOpenValveFLAGÀqOpenValveAuthorizeFLAGÀqOpenValveAuthorizeTimeCntqValve_control_parmPqValveOpenTimesqValveCloseTimesqValve_Force_Open_FlagqBat_Lith_statusqBat_Alka_status*ÐValve_Type#OpenValveTime#CloseValveTime#CurrentState#CurrentState0Time#ValveHaveClosedTime#PVALVE_CONTROL_PARMºÙlÑOpenValveFLAGåOpenValveAuthorizeFLAGOpenValveAuthorizeTimeCnt$Valve_control_parm=ValveOpenTimesTValveCloseTimeslValve_Force_Open_FlagBat_Lith_status¢Bat_Alka_status@AB__assert_h _ARMABI_NORETURN __declspec(__nothrow) __declspec(__noreturn)__ARMCLIB_VERSION 5060037!__ARM_PROMISE __promise#__CLIBNS)__CLIBNS Hassert(e) ((e) ? (void)0 : __CLIBNS __aeabi_assert(#e, __FILE__, __LINE__), (__ARM_PROMISE)((e)?1:0))J__promise(e) assert(e)LB D:\Keil5\ARM\ARMCC\Bin\..\include\assert.hD:\Keil5\ARM\ARMCC\Bin\..\include\assert.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]DEF __inttypes_h __ARMCLIB_VERSION 5060037_ARMABI __declspec(__nothrow)_ARMABI_PURE __declspec(__nothrow) __attribute__((const))__PRISCN64 "ll"__PRISCNPTR %PRId8 "d"&PRId16 "d"'PRId32 "d"(PRId64 __PRISCN64 "d")PRIdLEAST8 "d"*PRIdLEAST16 "d"+PRIdLEAST32 "d",PRIdLEAST64 __PRISCN64 "d"-PRIdFAST8 "d".PRIdFAST16 "d"/PRIdFAST32 "d"0PRIdFAST64 __PRISCN64 "d"1PRIdMAX "jd"2PRIdPTR __PRISCNPTR "d"4PRIi8 "i"5PRIi16 "i"6PRIi32 "i"7PRIi64 __PRISCN64 "i"8PRIiLEAST8 "i"9PRIiLEAST16 "i":PRIiLEAST32 "i";PRIiLEAST64 __PRISCN64 "i"<PRIiFAST8 "i"=PRIiFAST16 "i">PRIiFAST32 "i"?PRIiFAST64 __PRISCN64 "i"@PRIiMAX "ji"APRIiPTR __PRISCNPTR "i"CPRIo8 "o"DPRIo16 "o"EPRIo32 "o"FPRIo64 __PRISCN64 "o"GPRIoLEAST8 "o"HPRIoLEAST16 "o"IPRIoLEAST32 "o"JPRIoLEAST64 __PRISCN64 "o"KPRIoFAST8 "o"LPRIoFAST16 "o"MPRIoFAST32 "o"NPRIoFAST64 __PRISCN64 "o"OPRIoMAX "jo"PPRIoPTR __PRISCNPTR "o"RPRIu8 "d"SPRIu16 "d"TPRIu32 "u"UPRIu64 __PRISCN64 "u"VPRIuLEAST8 "d"WPRIuLEAST16 "d"XPRIuLEAST32 "u"YPRIuLEAST64 __PRISCN64 "u"ZPRIuFAST8 "u"[PRIuFAST16 "u"\PRIuFAST32 "u"]PRIuFAST64 __PRISCN64 "u"^PRIuMAX "ju"_PRIuPTR __PRISCNPTR "u"aPRIx8 "x"bPRIx16 "x"cPRIx32 "x"dPRIx64 __PRISCN64 "x"ePRIxLEAST8 "x"fPRIxLEAST16 "x"gPRIxLEAST32 "x"hPRIxLEAST64 __PRISCN64 "x"iPRIxFAST8 "x"jPRIxFAST16 "x"kPRIxFAST32 "x"lPRIxFAST64 __PRISCN64 "x"mPRIxMAX "jx"nPRIxPTR __PRISCNPTR "x"pPRIX8 "X"qPRIX16 "X"rPRIX32 "X"sPRIX64 __PRISCN64 "X"tPRIXLEAST8 "X"uPRIXLEAST16 "X"vPRIXLEAST32 "X"wPRIXLEAST64 __PRISCN64 "X"xPRIXFAST8 "X"yPRIXFAST16 "X"zPRIXFAST32 "X"{PRIXFAST64 __PRISCN64 "X"|PRIXMAX "jX"}PRIXPTR __PRISCNPTR "X"SCNd8 "hhd"SCNd16 "hd"SCNd32 "d"SCNd64 __PRISCN64 "d"SCNdLEAST8 "hhd"SCNdLEAST16 "hd"SCNdLEAST32 "d"SCNdLEAST64 __PRISCN64 "d"SCNdFAST8 "d"SCNdFAST16 "d"SCNdFAST32 "d"SCNdFAST64 __PRISCN64 "d"SCNdMAX "jd"SCNdPTR __PRISCNPTR "d"SCNi8 "hhd"SCNi16 "hi"SCNi32 "i"SCNi64 __PRISCN64 "i"SCNiLEAST8 "hhi"SCNiLEAST16 "hi"SCNiLEAST32 "i"SCNiLEAST64 __PRISCN64 "i"SCNiFAST8 "i"SCNiFAST16 "i"SCNiFAST32 "i"SCNiFAST64 __PRISCN64 "i"SCNiMAX "ji"SCNiPTR __PRISCNPTR "i"SCNo8 "hho"SCNo16 "ho"SCNo32 "o" SCNo64 __PRISCN64 "o"¡SCNoLEAST8 "hho"¢SCNoLEAST16 "ho"£SCNoLEAST32 "o"¤SCNoLEAST64 __PRISCN64 "o"¥SCNoFAST8 "o"¦SCNoFAST16 "o"§SCNoFAST32 "o"¨SCNoFAST64 __PRISCN64 "o"©SCNoMAX "jo"ªSCNoPTR __PRISCNPTR "o"¬SCNu8 "hhu"SCNu16 "hu"®SCNu32 "u"¯SCNu64 __PRISCN64 "u"°SCNuLEAST8 "hhu"±SCNuLEAST16 "hu"²SCNuLEAST32 "u"³SCNuLEAST64 __PRISCN64 "u"´SCNuFAST8 "u"µSCNuFAST16 "u"¶SCNuFAST32 "u"·SCNuFAST64 __PRISCN64 "u"¸SCNuMAX "ju"¹SCNuPTR __PRISCNPTR "u"»SCNx8 "hhx"¼SCNx16 "hx"½SCNx32 "x"¾SCNx64 __PRISCN64 "x"¿SCNxLEAST8 "hhx"ÀSCNxLEAST16 "hx"ÁSCNxLEAST32 "x"ÂSCNxLEAST64 __PRISCN64 "x"ÃSCNxFAST8 "x"ÄSCNxFAST16 "x"ÅSCNxFAST32 "x"ÆSCNxFAST64 __PRISCN64 "x"ÇSCNxMAX "jx"ÈSCNxPTR __PRISCNPTR "x"\P D:\Keil5\ARM\ARMCC\Bin\..\include\inttypes.hstdint.hèD:\Keil5\ARM\ARMCC\Bin\..\include\inttypes.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]unsigned shortPwchar_tÒ)Öimaxdiv_tquot#rem#Pimaxdiv_t¬Þ2HIJ_PORT_H INLINE inlinePR_BEGIN_EXTERN_C extern "C" {PR_END_EXTERN_C }!ENTER_CRITICAL_SECTION() __set_PRIMASK(1)"EXIT_CRITICAL_SECTION() __set_PRIMASK(0)0TRUE 14FALSE 0| ..\Soft\D:\Keil5\ARM\ARMCC\Bin\..\include\..\Core\port.hassert.hinttypes.hdefine_all.h,
..\Soft\port.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMunsigned charcharPBOOL8$PUCHAR°&PCHARÁ'PUSHORTV)PSHORT*PULONGf,PLONG-LMN_MB_CRC_H !<1 ..\Soft\mbcrc.hport.h°
..\Soft\mbcrc.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMPQR__DEVICEGPIOINIT_H FM25V02_CS_LOW(__CS_TYPE__) do { if (__CS_TYPE__ == CS_1) { FM25V02_CS1_L; FM25V02_CS2_H; } else { FM25V02_CS2_L; FM25V02_CS1_H; } } while (0)FM25V02_CS_HIGH do { FM25V02_CS1_H; FM25V02_CS2_H; } while (0)!Fram_Flash_SPI_SCL_PIN_NUM GPIO_Pin_7"Fram_Flash_SPI_SCL_GROUP GPIOC$Fram_Flash_SPI_MISO_PIN_NUM GPIO_Pin_8%Fram_Flash_SPI_MISO_PIN_GROUP GPIOC'Fram_Flash_SPI_MOSI_PIN_NUM GPIO_Pin_9(Fram_Flash_SPI_MOSI_PIN_GROUP GPIOC*FRAM_CS1_NUM GPIO_Pin_6+FRAM_CS1_GROUP GPIOC,FM25V02_CS1_H GPIO_SetBits(FRAM_CS1_GROUP, FRAM_CS1_NUM)-FM25V02_CS1_L GPIO_ResetBits(FRAM_CS1_GROUP, FRAM_CS1_NUM)/FRAM_CS2_NUM GPIO_Pin_140FRAM_CS2_GROUP GPIOC1FM25V02_CS2_H GPIO_SetBits(FRAM_CS2_GROUP, FRAM_CS2_NUM)2FM25V02_CS2_L GPIO_ResetBits(FRAM_CS2_GROUP, FRAM_CS2_NUM)4E2P_VCC_EN_NUM GPIO_Pin_115E2P_VCC_EN_GROUP GPIOC6E2P_VCC_ON GPIO_ResetBits(E2P_VCC_EN_GROUP, E2P_VCC_EN_NUM)7E2P_VCC_OFF GPIO_SetBits(E2P_VCC_EN_GROUP, E2P_VCC_EN_NUM):LCD_POWER_CON_NUM GPIO_Pin_0;LCD_POWER_CON_GROUP GPIOF<LCD_Power_ON GPIO_SetBits(LCD_POWER_CON_GROUP, LCD_POWER_CON_NUM)=LCD_Power_OFF GPIO_ResetBits(LCD_POWER_CON_GROUP, LCD_POWER_CON_NUM)@LCD_SDA_PIN_NUM GPIO_Pin_3ALCD_SDA_PIN_GROUP GPIODBLCD_SDA_H GPIO_SetBits(LCD_SDA_PIN_GROUP, LCD_SDA_PIN_NUM)CLCD_SDA_L GPIO_ResetBits(LCD_SDA_PIN_GROUP, LCD_SDA_PIN_NUM)ELCD_SCL_PIN_NUM GPIO_Pin_2FLCD_SCL_PIN_GROUP GPIODGLCD_SCL_H GPIO_SetBits(LCD_SCL_PIN_GROUP, LCD_SCL_PIN_NUM)HLCD_SCL_L GPIO_ResetBits(LCD_SCL_PIN_GROUP, LCD_SCL_PIN_NUM)JLCD_SCL_READ GPIO_ReadInputDataBit(LCD_SCL_PIN_GROUP, LCD_SCL_PIN_NUM)KLCD_SDA_READ GPIO_ReadInputDataBit(LCD_SDA_PIN_GROUP, LCD_SDA_PIN_NUM)MLCD_RD_CLK_PIN_NUM GPIO_Pin_5NLCD_RD_CLK_PIN_GROUP GPIODOLCD_CS_PIN_NUM GPIO_Pin_4PLCD_CS_PIN_GROUP GPIODSPOWER_EX_EN_PIN_NUM GPIO_Pin_13TPOWER_EX_EN_PIN_GROUP GPIOBUpowerEX_ON GPIO_SetBits(POWER_EX_EN_PIN_GROUP, POWER_EX_EN_PIN_NUM)VpowerEX_OFF GPIO_ResetBits(POWER_EX_EN_PIN_GROUP, POWER_EX_EN_PIN_NUM)XPOWER_9V_EN_PIN_NUM GPIO_Pin_14YPOWER_9V_EN_PIN_GROUP GPIOBZpower9V_ON GPIO_SetBits(POWER_9V_EN_PIN_GROUP, POWER_9V_EN_PIN_NUM)[power9V_OFF GPIO_ResetBits(POWER_9V_EN_PIN_GROUP, POWER_9V_EN_PIN_NUM)]POWER_12V_EN_PIN_NUM GPIO_Pin_15^POWER_12V_EN_PIN_GROUP GPIOB_power12V_ON GPIO_SetBits(POWER_12V_EN_PIN_GROUP, POWER_12V_EN_PIN_NUM)`power12V_OFF GPIO_ResetBits(POWER_12V_EN_PIN_GROUP, POWER_12V_EN_PIN_NUM)bOUTPUT1_EN_PIN_NUM GPIO_Pin_11cOUTPUT1_EN_PIN_GROUP GPIOBdOUTPUT1_EN_ON GPIO_SetBits(OUTPUT1_EN_PIN_GROUP, OUTPUT1_EN_PIN_NUM)eOUTPUT1_EN_OFF GPIO_ResetBits(OUTPUT1_EN_PIN_GROUP, OUTPUT1_EN_PIN_NUM)gOUTPUT2_EN_PIN_NUM GPIO_Pin_12hOUTPUT2_EN_PIN_GROUP GPIOBiOUTPUT2_EN_ON GPIO_SetBits(OUTPUT2_EN_PIN_GROUP, OUTPUT2_EN_PIN_NUM)jOUTPUT2_EN_OFF GPIO_ResetBits(OUTPUT2_EN_PIN_GROUP, OUTPUT2_EN_PIN_NUM)mRS485_SYNC_PIN_NUM GPIO_Pin_2nRS485_SYNC_PIN_GROUP GPIOEoRS485_SYNC_READ GPIO_ReadInputDataBit(RS485_SYNC_PIN_GROUP, RS485_SYNC_PIN_NUM)qLOW_PWR_INT_PIN_NUM GPIO_Pin_2rLOW_PWR_INT_PIN_GROUP GPIOBsLOW_PWR_READ GPIO_ReadInputDataBit(LOW_PWR_INT_PIN_GROUP, LOW_PWR_INT_PIN_NUM)uUNDER_PWR_INT_PIN_NUM GPIO_Pin_3vUNDER_PWR_INT_PIN_GROUP GPIOBwUNDER_PWR_READ GPIO_ReadInputDataBit(UNDER_PWR_INT_PIN_GROUP, UNDER_PWR_INT_PIN_NUM)yALARM_LINE_PIN_NUM GPIO_Pin_13zALARM_LINE_PIN_GROUP GPIOA{ALARM_LINE_READ GPIO_ReadInputDataBit(ALARM_LINE_PIN_GROUP, ALARM_LINE_PIN_NUM)}LITH_BAT_LOW_PWR_PIN_NUM GPIO_Pin_0~LITH_BAT_LOW_PWR_PIN_GROUP GPIODLITH_BAT_LOW_PWR_PIN_READ GPIO_ReadInputDataBit(LITH_BAT_LOW_PWR_PIN_GROUP, LITH_BAT_LOW_PWR_PIN_NUM)ALKA_BAT_M_PIN_NUM GPIO_Pin_0ALKA_BAT_M_PIN_GROUP GPIOHLITH_BAT_M_PIN_NUM GPIO_Pin_6LITH_BAT_M_PIN_GROUP GPIOFALKA_TEST_EN_PIN_NUM GPIO_Pin_4ALKA_TEST_EN_PIN_GROUP GPIOFALKA_TEST_ON GPIO_SetBits(ALKA_TEST_EN_PIN_GROUP, ALKA_TEST_EN_PIN_NUM)ALKA_TEST_OFF GPIO_ResetBits(ALKA_TEST_EN_PIN_GROUP, ALKA_TEST_EN_PIN_NUM)LITH_TEST_EN_PIN_NUM GPIO_Pin_3LITH_TEST_EN_PIN_GROUP GPIOFLITH_TEST_ON GPIO_SetBits(LITH_TEST_EN_PIN_GROUP, LITH_TEST_EN_PIN_NUM)LITH_TEST_OFF GPIO_ResetBits(LITH_TEST_EN_PIN_GROUP, LITH_TEST_EN_PIN_NUM)HWID0_PIN_NUM GPIO_Pin_5HWID0_PIN_GROUP GPIOFHWID0_READ GPIO_ReadInputDataBit(HWID0_PIN_GROUP, HWID0_PIN_NUM)HWID0_H GPIO_SetBits(HWID0_PIN_GROUP, HWID0_PIN_NUM)HWID0_L GPIO_ResetBits(HWID0_PIN_GROUP, HWID0_PIN_NUM)EX_PWR_EN_PIN_NUM GPIO_Pin_3EX_PWR_EN_PIN_GROUP GPIOGEX_PWR_EN_H GPIO_SetBits(EX_PWR_EN_PIN_GROUP, EX_PWR_EN_PIN_NUM)EX_PWR_EN_L GPIO_ResetBits(EX_PWR_EN_PIN_GROUP, EX_PWR_EN_PIN_NUM)EX_PWR_EN_READ GPIO_ReadInputDataBit(EX_PWR_EN_PIN_GROUP, EX_PWR_EN_PIN_NUM)LIMIT_TRIG_PIN_NUM GPIO_Pin_13LIMIT_TRIG_PIN_GROUP GPIOCLIMIT_TRIG_READ GPIO_ReadInputDataBit(LIMIT_TRIG_PIN_GROUP, LIMIT_TRIG_PIN_NUM)¢KEY1_PIN_NUM GPIO_Pin_9£KEY1_PIN_GROUP GPIOE¥KEY2_PIN_NUM GPIO_Pin_15¦KEY2_PIN_GROUP GPIOF¨KEY3_PIN_NUM GPIO_Pin_14©KEY3_PIN_GROUP GPIOF«KEY1_PRESS GPIO_ReadInputDataBit(KEY1_PIN_GROUP, KEY1_PIN_NUM)¬KEY2_PRESS GPIO_ReadInputDataBit(KEY2_PIN_GROUP, KEY2_PIN_NUM)KEY3_PRESS GPIO_ReadInputDataBit(KEY3_PIN_GROUP, KEY3_PIN_NUM)°RS485_RE_EN_PIN_NUM GPIO_Pin_14±RS485_RE_EN_PIN_GROUP GPIOA²RS485_RE_H GPIO_SetBits(RS485_RE_EN_PIN_GROUP, RS485_RE_EN_PIN_NUM)³RS485_RE_L GPIO_ResetBits(RS485_RE_EN_PIN_GROUP, RS485_RE_EN_PIN_NUM)µRS485_TXD_EN_PIN_NUM GPIO_Pin_1¶RS485_TXD_EN_PIN_GROUP GPIOB·RS485_RXD_EN_PIN_NUM GPIO_Pin_0¸RS485_RXD_EN_PIN_GROUP GPIOBºRS485_POWER_EN_PIN_NUM GPIO_Pin_15»RS485_POWER_EN_PIN_GROUP GPIOA¼RS485_POWER_ON GPIO_SetBits(RS485_POWER_EN_PIN_GROUP, RS485_POWER_EN_PIN_NUM)½RS485_POWER_OFF GPIO_ResetBits(RS485_POWER_EN_PIN_GROUP, RS485_POWER_EN_PIN_NUM)ÀGPRSRS232_TXD_EN_PIN_NUM GPIO_Pin_4ÁGPRSRS232_TXD_EN_PIN_GROUP GPIOEÂGPRSRS232_RXD_EN_PIN_NUM GPIO_Pin_3ÃGPRSRS232_RXD_EN_PIN_GROUP GPIOEÆUTRXD_RE_EN_PIN_NUM GPIO_Pin_10ÇUTXRD_RE_EN_PIN_GROUP GPIOAÈUTRXD_RE_H GPIO_SetBits(UTXRD_RE_EN_PIN_GROUP, UTRXD_RE_EN_PIN_NUM)ÉUTRXD_RE_L GPIO_ResetBits(UTXRD_RE_EN_PIN_GROUP, UTRXD_RE_EN_PIN_NUM)ËUTXD_EN_PIN_NUM GPIO_Pin_9ÌUTXD_EN_PIN_GROUP GPIOAÍURXD_EN_PIN_NUM GPIO_Pin_8ÎURXD_EN_PIN_GROUP GPIOAÑMotor_A_PIN_NUM GPIO_Pin_8ÒMotor_A_PIN_GROUP GPIOBÓMotor_A_EN_H GPIO_SetBits(Motor_A_PIN_GROUP, Motor_A_PIN_NUM)ÔMotor_A_EN_L GPIO_ResetBits(Motor_A_PIN_GROUP, Motor_A_PIN_NUM)ÖMotor_B_PIN_NUM GPIO_Pin_9×Motor_B_PIN_GROUP GPIOBØMotor_B_EN_H GPIO_SetBits(Motor_B_PIN_GROUP, Motor_B_PIN_NUM)ÙMotor_B_EN_L GPIO_ResetBits(Motor_B_PIN_GROUP, Motor_B_PIN_NUM)ÛMotor_OP_PIN_NUM GPIO_Pin_6ÜMotor_OP_PIN_GROUP GPIOBÝMotor_OP_PIN_READ GPIO_ReadInputDataBit(Motor_OP_PIN_GROUP, Motor_OP_PIN_NUM)ßMotor_CL_PIN_NUM GPIO_Pin_7àMotor_CL_PIN_GROUP GPIOBáMotor_CL_PIN_READ GPIO_ReadInputDataBit(Motor_CL_PIN_GROUP, Motor_CL_PIN_NUM)äRTC_SDA_PIN_NUM GPIO_Pin_3åRTC_SDA_PIN_GROUP GPIODæRTC_CLK_PIN_NUM GPIO_Pin_2çRTC_CLK_PIN_GROUP GPIODéRTC_INT_PIN_NUM GPIO_Pin_6êRTC_INT_PIN_GROUP GPIODíLOWPLUSE_PIN_NUM GPIO_Pin_3îLOWPLUSE_PIN_GROUP GPIOHïPULSE_LINE_READ GPIOH_ReadInputDataBit(LOWPLUSE_PIN_NUM)òGPIO_GPRS_POWER_PIN_NUM GPIO_Pin_7óGPIO_GPRS_POWER_PIN_GROUP GPIOEôGPRS_POWER_ON GPIO_SetBits(GPIO_GPRS_POWER_PIN_GROUP, GPIO_GPRS_POWER_PIN_NUM)õGPRS_POWER_OFF GPIO_ResetBits(GPIO_GPRS_POWER_PIN_GROUP, GPIO_GPRS_POWER_PIN_NUM)÷GPRS_PWR_EN_PIN_NUM GPIO_Pin_6øGPRS_PWR_EN_PIN_GROUP GPIOEùGPRS_POWER_EN_H GPIO_SetBits(GPRS_PWR_EN_PIN_GROUP, GPRS_PWR_EN_PIN_NUM)úGPRS_POWER_EN_L GPIO_ResetBits(GPRS_PWR_EN_PIN_GROUP, GPRS_PWR_EN_PIN_NUM)ýUNCAP_INT_PIN_NUM GPIO_Pin_1þUNCAP_INT_PIN_GROUP GPIODÿUNCAP_INT_READ GPIO_ReadInputDataBit(UNCAP_INT_PIN_GROUP, UNCAP_INT_PIN_NUM)UNCAP_INT_L GPIO_ResetBits(UNCAP_INT_PIN_GROUP, UNCAP_INT_PIN_NUM)FORCE_OPEN_INT_PIN_NUM GPIO_Pin_12FORCE_OPEN_INT_PIN_GROUP GPIOCFORCE_OPEN_INT_READ GPIO_ReadInputDataBit(FORCE_OPEN_INT_PIN_GROUP, FORCE_OPEN_INT_PIN_NUM)BORROW_PWR_EN_PIN_NUM GPIO_Pin_2BORROW_PWR_EN_PIN_NUM_GROUP GPIOGBORROW_PWR_EN_PIN_H GPIO_SetBits(BORROW_PWR_EN_PIN_NUM_GROUP, BORROW_PWR_EN_PIN_NUM)BORROW_PWR_EN_NUM_L GPIO_ResetBits(BORROW_PWR_EN_PIN_NUM_GROUP, BORROW_PWR_EN_PIN_NUM)\P ..\Pre_Drivers\..\Core\devicegpioinit.hdefine_all.hè
..\Pre_Drivers\devicegpioinit.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMÖCS_1CS_2PCS_TYPED_TÁ
TUV__RS485_H PG ..\Pre_Drivers\..\Core\rs485.hdefine_all.h¸
..\Pre_Drivers\rs485.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMXYZ_powermanage_H HIGH 1LOW 0POWER_EXTERN 1POWER_BAT 0ALKA_V_THRESHOLD1UP 6.8ALKA_V_THRESHOLD1DOWN 5.5LITH_V_LOW_ALARM 5.5LITH_V_DOWN_VALVE_CLOSE 5.0ALKA_V_LOW_ALARM 5.4ALKA_V_DOWN_VALVE_CLOSE 5.0XN ..\Pre_Drivers\..\Core\1powermanage.hdefine_all.hÀ
..\Pre_Drivers\1powermanage.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM\]^        
 
  H> ..\Pre_Drivers\D:\Keil5\ARM\ARMCC\Bin\..\include\..\Function\E2P\..\Soft\..\Pre_Drivers\ReadDeviceData.cReadDeviceData.hmath.hpara.he2p.hex_rtc.hdata_write_local.h1gprs.h1billing.h1ValveControl.hmbcrc.hdevicegpioinit.hrs485.h1powermanage.hx
..\Pre_Drivers\ReadDeviceData.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM_Complex long_double_Complex double_Complex floatuvoidunsigned charunsigned shortfloatintdouble)Ü__va_list__ap\#"þP__builtin_va_listA`!/!I$>%%%%    %C
%C%% %%%C%C&I(( 1111 I8     I  I8    4! I8     "I#7I$I%I&I    'I(I)*+,-./404142434445.:;9?I6.:;9?7.:;9G8.:;9?I 9.:;9? :.:;9G ;.:;9?I<.:;9?=.:;9G>.:;9?I@?.:;9?@@.:;9G@A.:;9?I@
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K.1L.<4I?M.<4?NIOPI:;9QI4RSTUVW1X4I    ,Y4I    Z4I[4I,\4I]4I    4^4I    ,4_4I4`4I,4a4I4b41    ,c41d41,e41f1g1hI    iIjIkI    4lI    ,4mI4n1    o1p4I    ?q4I?<r4I,s4It5Iu;v=w%x<%Component: ARM Compiler 5.06 update 6 (build 750) Tool: armlink [4d35ed]armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=9931,9931,6642 --cpu=Cortex-M0 --fpu=SoftVFP --output=.\objects\readdevicedata.o --vfemode=force
Input Comments:p31a4-3Component: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]armasm --debug --diag_suppress=9931,9931,1602,1073 --cpu=Cortex-M0 --fpu=SoftVFP --apcs=/interwork/interwork --no_divide readdevicedata.oComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]ArmCC --c99 --split_sections --debug -c --gnu -o.\objects\readdevicedata.o --depend=.\objects\readdevicedata.d --cpu=Cortex-M0 --apcs=interwork -O0 --diag_suppress=9931 -I..\Core -I..\Drivers -I..\Core\Include -I..\Hardware -I.\RTE\Device -I..\Hardware\CLOCK -I..\Hardware\DELAY -I..\Hardware\GPIO -I..\Hardware\UART -I..\Hardware\TIM -I..\Function\KEY -I..\Hardware\EXTI -I..\Hardware\RTC -I..\Hardware\ADC -I..\Hardware\I2C -I..\Function\LCD -I..\Function\EXTERN_RTC -I..\Hardware\SPI -I..\Function\GPRS -I..\Function\HARDWARE_WATCHDOG -I..\Function\IR_NEC -I..\Function\MEASURE_INTERACTION -I..\Function\POWER_MANAGE -I..\Function\STORAGE -I..\Function\UPPER_COMPUTER -I..\Function\VALVE -I..\Soft -I..\MultiButton -I..\USMART -I..\Hardware\DMA -I..\Hardware\ON_CHIP_FLASH -I..\Hardware\SVD -I..\Function\OFF_CHIP_FLASH -I..\Hardware\CRC -I..\Function\BOOTLOADER_IAP -I..\Hardware\COMP -I..\Function\E2P -I..\CmBackTrace -I..\Pre_Drivers -I..\Pre_Drivers -I..\Function\PROJECT_TETS -I.\RTE\_UFG220_FM33A0_MainSystem -ID:\Keil5\ARM\PACK\ARM\CMSIS\5.3.0\CMSIS\Include -ID:\Keil5\ARM\PACK\Keil\FM33A0XXEV_DFP\0.0.4\Device\Include -D__MICROLIB -D__UVISION_VERSION=525 -D_RTE_ -D__VTOR_PRESENT --omf_browse=.\objects\readdevicedata.crf ..\Pre_Drivers\ReadDeviceData.ccMcMcMcMcM`McM,`M,cMt`MlcM´`Mz cM`MìcM`McM,`M®cM`M>cM    `M"    cM
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Õ³Z·|ÕÕµÕÒÕòÕÕ¸Y¼ÕNÕfÕÕÕ´ÕËÕâÕúÕÕ+ÕHÕ`!LÁÕÎÕ¨¬PÐÕùÕÕÕ%Õ©N¹h½)°´Q·\»¹^½.ARM.attributes.strtab.shstrtab.rel.debug_pubnames.rel.debug_frame.rel.debug_line.rel.debug_info.reli.Temperature_alarm.reli.Read485_process.reli.Pressure_alarm.reli.Parameter_assignment.reli.PULSE_Recording.reli.Modbus_RS485B.reli.LLJ_sendFrame.reli.LLJ_ModbusHandle_SIZHUV2_0.reli.LLJ_ModbusHandle_CRCData.reli.LLJ_ModbusHandle.reli.Analysis_Float48.reli.Analysis_Float.symtab.comment.arm_vfe_header__ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000__ARM_grp.ReadDeviceData.c.2_ME0000_NL3pXWtQuz0_300000__ARM_grp.1powermanage.h.2_Uz0000_vSamYc4k5o2_300000__ARM_grp.rs485.h.2_Us0000_3$Cs1gcuNt3_300000__ARM_grp.devicegpioinit.h.2_0w4000_64Z46PStLCa_300000__ARM_grp.mbcrc.h.2_8s0000_udjUqJW6TU5_300000__ARM_grp.port.h.2_Em1000_cWymiH7cCq9_b00000__ARM_grp.inttypes.h.2_YM2000_HBynUsOMdLa_800000__ARM_grp.assert.h.2_oA0000_EVegbDxopI6_300000__ARM_grp.1ValveControl.h.2_NL2000_a5DINTTQpWf_B00000__ARM_grp.1billing.h.2_GK2000_cmOxbPQKCb2_p00000__ARM_grp.1gprs.h.2_B95000_i_AeRhQ$890_j20000__ARM_grp.data_write_local.h.2_I32000_1VLSL0PLXId_300000__ARM_grp.ex_rtc.h.2_DP2000_DSa9_1ND590_510000__ARM_grp.e2p.h.2_Wb3000_h$Rdq_Blhv7_v00000__ARM_grp.spi.h.2_gy0000_s_nnifot9te_300000__ARM_grp.para.h.2_Ez8000_khDVHof8zWa_t40000__ARM_grp.1ADC.h.2_Qp1000_8FudzCBNeP8_900000__ARM_grp.math.h.2_bA3000_jfXlNmluFrf_700000__ARM_grp.ReadDeviceData.h.2_s22000_kYPOqAyPDy8_v00000__ARM_grp.delay.h.2_EE0000_7GGSWSTJWL4_300000__ARM_grp.user_init.h.2_ot0000_jZWuqvPHwt6_300000__ARM_grp.define_all.h.2_kN0000_fD9tyG24Hn2_300000__ARM_grp.bintohex.h.2_Y33000_duI5XZW3h40_300000__ARM_grp.string.h.2_kw0000_aP4aobzpRT7_300000__ARM_grp.fm33a0xxev_include_all.h.2_UQ0000_xxdaGLUj6Cf_300000__ARM_grp.fm33a0xxev_cdif.h.2_kJ0000_JQTXKb9R3mc_300000__ARM_grp.fm33a0xxev_vrtc.h.2_YK1000_bGKK6ktMN$f_300000__ARM_grp.fm33a0xxev_et.h.2_4h3000_57B3Rgey0je_300000__ARM_grp.fm33a0xxev_bt.h.2_kV3000_MyPILKKQ6H1_300000__ARM_grp.fm33a0xxev_qspi.h.2_Qr4000_J7HoI7y0B84_g00000__ARM_grp.fm33a0xxev_hash.h.2_kO0000_KuZ300H4_80_300000__ARM_grp.fm33a0xxev_pae.h.2_sJ3000_RoohqLgJd45_300000__ARM_grp.fm33a0xxev_svd.h.2_YX4000_B$e1cGixg00_i00000__ARM_grp.fm33a0xxev_wwdt.h.2_4H0000_TVah5VHd$Wd_300000__ARM_grp.fm33a0xxev_lptim.h.2_8q4000_BFHTRuxu1ie_300000__ARM_grp.fm33a0xxev_uart.h.2_s_5000_gGxJA_bT3g3_r00000__ARM_grp.fm33a0xxev_u7816.h.2_sD5000_T7w3HnfvCn7_w00000__ARM_grp.fm33a0xxev_rng.h.2_IJ0000_vzTWbGvNuZe_300000__ARM_grp.fm33a0xxev_spi.h.2_AU2000_7eFMvsSXzw0_300000__ARM_grp.fm33a0xxev_dbg.h.2_4f1000_pVDK34opiR1_300000__ARM_grp.fm33a0xxev_rtc.h.2_sS3000_IylpavQ6INd_g00000__ARM_grp.fm33a0xxev_cmu.h.2_Ekb000_qHj10Bv8MJ6_v00000__ARM_grp.fm33a0xxev_pmu.h.2_Af5000_lOjh94cQJQf_g00000__ARM_grp.fm33a0xxev_flash.h.2_0_1000_TO3GMzQCtL1_300000__ARM_grp.fm33a0xxev_lpuart.h.2_oE2000_Ig0fu_ljcn3_300000__ARM_grp.fm33a0xxev_iwdt.h.2_4L0000_LcDBel0usy8_300000__ARM_grp.fm33a0xxev_i2c.h.2_IS1000_g4ErNZQBGwd_300000__ARM_grp.fm33a0xxev_gpio.h.2_815000_upDQZZvAzia_700000__ARM_grp.fm33a0xxev_dma.h.2_ks8000_OrTMHX6QIe0_p00000__ARM_grp.fm33a0xxev_lcd.h.2_Y$4000_kUmWRnNV3_4_300000__ARM_grp.fm33a0xxev_crc.h.2_8C4000_La7VPM3Tip8_k00000__ARM_grp.fm33a0xxev_rmu.h.2_4L2000_C$q$9vNhOp0_300000__ARM_grp.fm33a0xxev_comp.h.2_k_2000_e5VaGx8gTre_300000__ARM_grp.fm33a0xxev_bstim.h.2_g$0000_A3CHw2qJcga_300000__ARM_grp.fm33a0xxev_adc.h.2_Yh2000_DMQIo6NAW82_300000__ARM_grp.fm33a0xxev_aes.h.2_4p5000_ig0fpeqfTIb_l00000__ARM_grp.system_FM33A0XXEV.h.2_qK2000_3p2q1l7JLmc_f00000__ARM_grp.FM33A0XXEV.h.2_0U4000_APjZ6EN_n61_800000__ARM_grp.stdio.h.2_UP1000_6McqO1w0lYe_f00000__ARM_grp.core_cm0plus.h.2_oo7000_NmZU1Rz5UO8_W00000__ARM_grp.core_cmfunc.h.2_4o1000_5BOwGSyN3D1_z00000__ARM_grp.core_cminstr.h.2_gq1000_Kwrp1OO1xx3_b00000__ARM_grp.stdint.h.2_QG1000_h7K9OtBs0h1_300000.debug_abbrev__ARM_asm.debug_abbrev.1.debug_macinfo.debug_loc.data.bss.revsh_text.rev16_textLib$$Request$$armlibusMBCRC16system_alarmpowparameter_bildelay_mscalendarawaken_flagarraya_2_arrayb__aeabi_uread4__aeabi_ui2f__aeabi_ui2d__aeabi_memclr4__aeabi_i2f__aeabi_i2d__aeabi_fdiv__aeabi_f2uiz__aeabi_f2d__aeabi_drsub__aeabi_dmul__aeabi_ddiv__aeabi_dadd__aeabi_d2uiz__aeabi_d2f__aeabi_cfrcmple__aeabi_cfcmple__aeabi_cdrcmpleSettlement_ParaRS485_Usart_InitRS485_Send_DataRS485_GPIO_InitRS485SettlementPOWER_EX_GPIO_InitOUTPUT_EN_GPIO_InitLLJ_data_gIWDT_ClrGet_TimeGPRS_sendFlagGPIO_SetBitsGPIO_ResetBitsGPIO_ReadInputDataBitFirstTimeRunFlagFM25V02_data_write_uint32_WRCheckFM25V02_data_write_uint32FM25V02_data_write_uint16FM25V02_data_write_floatFM25V02_data_write_doubleFM25V02_data_writeEXPower_ControlBat_Alka_status__ARM_grp..debug_pubnames$system_FM33A0XXEV.h$.2_qK2000_3p2q1l7JLmc_f00000__ARM_grp..debug_pubnames$stdio.h$.2_UP1000_6McqO1w0lYe_f00000__ARM_grp..debug_pubnames$para.h$.2_Ez8000_khDVHof8zWa_t40000__ARM_grp..debug_pubnames$math.h$.2_bA3000_jfXlNmluFrf_700000__ARM_grp..debug_pubnames$ex_rtc.h$.2_DP2000_DSa9_1ND590_510000__ARM_grp..debug_pubnames$e2p.h$.2_Wb3000_h$Rdq_Blhv7_v00000__ARM_grp..debug_pubnames$1gprs.h$.2_B95000_i_AeRhQ$890_j20000__ARM_grp..debug_pubnames$1billing.h$.2_GK2000_cmOxbPQKCb2_p00000__ARM_grp..debug_pubnames$1ValveControl.h$.2_NL2000_a5DINTTQpWf_B00000__ARM_grp..debug_macinfo$user_init.h$.2_ot0000_jZWuqvPHwt6_300000__ARM_grp..debug_macinfo$system_FM33A0XXEV.h$.2_qK2000_3p2q1l7JLmc_f00000__ARM_grp..debug_macinfo$string.h$.2_kw0000_aP4aobzpRT7_300000__ARM_grp..debug_macinfo$stdio.h$.2_UP1000_6McqO1w0lYe_f00000__ARM_grp..debug_macinfo$stdint.h$.2_QG1000_h7K9OtBs0h1_300000__ARM_grp..debug_macinfo$spi.h$.2_gy0000_s_nnifot9te_300000__ARM_grp..debug_macinfo$rs485.h$.2_Us0000_3$Cs1gcuNt3_300000__ARM_grp..debug_macinfo$port.h$.2_Em1000_cWymiH7cCq9_b00000__ARM_grp..debug_macinfo$para.h$.2_Ez8000_khDVHof8zWa_t40000__ARM_grp..debug_macinfo$mbcrc.h$.2_8s0000_udjUqJW6TU5_300000__ARM_grp..debug_macinfo$math.h$.2_bA3000_jfXlNmluFrf_700000__ARM_grp..debug_macinfo$inttypes.h$.2_YM2000_HBynUsOMdLa_800000__ARM_grp..debug_macinfo$fm33a0xxev_wwdt.h$.2_4H0000_TVah5VHd$Wd_300000__ARM_grp..debug_macinfo$fm33a0xxev_vrtc.h$.2_YK1000_bGKK6ktMN$f_300000__ARM_grp..debug_macinfo$fm33a0xxev_uart.h$.2_s_5000_gGxJA_bT3g3_r00000__ARM_grp..debug_macinfo$fm33a0xxev_u7816.h$.2_sD5000_T7w3HnfvCn7_w00000__ARM_grp..debug_macinfo$fm33a0xxev_svd.h$.2_YX4000_B$e1cGixg00_i00000__ARM_grp..debug_macinfo$fm33a0xxev_spi.h$.2_AU2000_7eFMvsSXzw0_300000__ARM_grp..debug_macinfo$fm33a0xxev_rtc.h$.2_sS3000_IylpavQ6INd_g00000__ARM_grp..debug_macinfo$fm33a0xxev_rng.h$.2_IJ0000_vzTWbGvNuZe_300000__ARM_grp..debug_macinfo$fm33a0xxev_rmu.h$.2_4L2000_C$q$9vNhOp0_300000__ARM_grp..debug_macinfo$fm33a0xxev_qspi.h$.2_Qr4000_J7HoI7y0B84_g00000__ARM_grp..debug_macinfo$fm33a0xxev_pmu.h$.2_Af5000_lOjh94cQJQf_g00000__ARM_grp..debug_macinfo$fm33a0xxev_pae.h$.2_sJ3000_RoohqLgJd45_300000__ARM_grp..debug_macinfo$fm33a0xxev_lpuart.h$.2_oE2000_Ig0fu_ljcn3_300000__ARM_grp..debug_macinfo$fm33a0xxev_lptim.h$.2_8q4000_BFHTRuxu1ie_300000__ARM_grp..debug_macinfo$fm33a0xxev_lcd.h$.2_Y$4000_kUmWRnNV3_4_300000__ARM_grp..debug_macinfo$fm33a0xxev_iwdt.h$.2_4L0000_LcDBel0usy8_300000__ARM_grp..debug_macinfo$fm33a0xxev_include_all.h$.2_UQ0000_xxdaGLUj6Cf_300000__ARM_grp..debug_macinfo$fm33a0xxev_i2c.h$.2_IS1000_g4ErNZQBGwd_300000__ARM_grp..debug_macinfo$fm33a0xxev_hash.h$.2_kO0000_KuZ300H4_80_300000__ARM_grp..debug_macinfo$fm33a0xxev_gpio.h$.2_815000_upDQZZvAzia_700000__ARM_grp..debug_macinfo$fm33a0xxev_flash.h$.2_0_1000_TO3GMzQCtL1_300000__ARM_grp..debug_macinfo$fm33a0xxev_et.h$.2_4h3000_57B3Rgey0je_300000__ARM_grp..debug_macinfo$fm33a0xxev_dma.h$.2_ks8000_OrTMHX6QIe0_p00000__ARM_grp..debug_macinfo$fm33a0xxev_dbg.h$.2_4f1000_pVDK34opiR1_300000__ARM_grp..debug_macinfo$fm33a0xxev_crc.h$.2_8C4000_La7VPM3Tip8_k00000__ARM_grp..debug_macinfo$fm33a0xxev_comp.h$.2_k_2000_e5VaGx8gTre_300000__ARM_grp..debug_macinfo$fm33a0xxev_cmu.h$.2_Ekb000_qHj10Bv8MJ6_v00000__ARM_grp..debug_macinfo$fm33a0xxev_cdif.h$.2_kJ0000_JQTXKb9R3mc_300000__ARM_grp..debug_macinfo$fm33a0xxev_bt.h$.2_kV3000_MyPILKKQ6H1_300000__ARM_grp..debug_macinfo$fm33a0xxev_bstim.h$.2_g$0000_A3CHw2qJcga_300000__ARM_grp..debug_macinfo$fm33a0xxev_aes.h$.2_4p5000_ig0fpeqfTIb_l00000__ARM_grp..debug_macinfo$fm33a0xxev_adc.h$.2_Yh2000_DMQIo6NAW82_300000__ARM_grp..debug_macinfo$ex_rtc.h$.2_DP2000_DSa9_1ND590_510000__ARM_grp..debug_macinfo$e2p.h$.2_Wb3000_h$Rdq_Blhv7_v00000__ARM_grp..debug_macinfo$devicegpioinit.h$.2_0w4000_64Z46PStLCa_300000__ARM_grp..debug_macinfo$delay.h$.2_EE0000_7GGSWSTJWL4_300000__ARM_grp..debug_macinfo$define_all.h$.2_kN0000_fD9tyG24Hn2_300000__ARM_grp..debug_macinfo$data_write_local.h$.2_I32000_1VLSL0PLXId_300000__ARM_grp..debug_macinfo$core_cminstr.h$.2_gq1000_Kwrp1OO1xx3_b00000__ARM_grp..debug_macinfo$core_cmfunc.h$.2_4o1000_5BOwGSyN3D1_z00000__ARM_grp..debug_macinfo$core_cm0plus.h$.2_oo7000_NmZU1Rz5UO8_W00000__ARM_grp..debug_macinfo$bintohex.h$.2_Y33000_duI5XZW3h40_300000__ARM_grp..debug_macinfo$assert.h$.2_oA0000_EVegbDxopI6_300000__ARM_grp..debug_macinfo$ReadDeviceData.h$.2_s22000_kYPOqAyPDy8_v00000__ARM_grp..debug_macinfo$ReadDeviceData.c$.2_ME0000_NL3pXWtQuz0_300000__ARM_grp..debug_macinfo$FM33A0XXEV.h$.2_0U4000_APjZ6EN_n61_800000__ARM_grp..debug_macinfo$1powermanage.h$.2_Uz0000_vSamYc4k5o2_300000__ARM_grp..debug_macinfo$1gprs.h$.2_B95000_i_AeRhQ$890_j20000__ARM_grp..debug_macinfo$1billing.h$.2_GK2000_cmOxbPQKCb2_p00000__ARM_grp..debug_macinfo$1ValveControl.h$.2_NL2000_a5DINTTQpWf_B00000__ARM_grp..debug_macinfo$1ADC.h$.2_Qp1000_8FudzCBNeP8_900000__ARM_grp..debug_line$user_init.h$.2_ot0000_jZWuqvPHwt6_300000__ARM_grp..debug_line$system_FM33A0XXEV.h$.2_qK2000_3p2q1l7JLmc_f00000__ARM_grp..debug_line$string.h$.2_kw0000_aP4aobzpRT7_300000__ARM_grp..debug_line$stdio.h$.2_UP1000_6McqO1w0lYe_f00000__ARM_grp..debug_line$stdint.h$.2_QG1000_h7K9OtBs0h1_300000__ARM_grp..debug_line$spi.h$.2_gy0000_s_nnifot9te_300000__ARM_grp..debug_line$rs485.h$.2_Us0000_3$Cs1gcuNt3_300000__ARM_grp..debug_line$port.h$.2_Em1000_cWymiH7cCq9_b00000__ARM_grp..debug_line$para.h$.2_Ez8000_khDVHof8zWa_t40000__ARM_grp..debug_line$mbcrc.h$.2_8s0000_udjUqJW6TU5_300000__ARM_grp..debug_line$math.h$.2_bA3000_jfXlNmluFrf_700000__ARM_grp..debug_line$inttypes.h$.2_YM2000_HBynUsOMdLa_800000__ARM_grp..debug_line$fm33a0xxev_wwdt.h$.2_4H0000_TVah5VHd$Wd_300000__ARM_grp..debug_line$fm33a0xxev_vrtc.h$.2_YK1000_bGKK6ktMN$f_300000__ARM_grp..debug_line$fm33a0xxev_uart.h$.2_s_5000_gGxJA_bT3g3_r00000__ARM_grp..debug_line$fm33a0xxev_u7816.h$.2_sD5000_T7w3HnfvCn7_w00000__ARM_grp..debug_line$fm33a0xxev_svd.h$.2_YX4000_B$e1cGixg00_i00000__ARM_grp..debug_line$fm33a0xxev_spi.h$.2_AU2000_7eFMvsSXzw0_300000__ARM_grp..debug_line$fm33a0xxev_rtc.h$.2_sS3000_IylpavQ6INd_g00000__ARM_grp..debug_line$fm33a0xxev_rng.h$.2_IJ0000_vzTWbGvNuZe_300000__ARM_grp..debug_line$fm33a0xxev_rmu.h$.2_4L2000_C$q$9vNhOp0_300000__ARM_grp..debug_line$fm33a0xxev_qspi.h$.2_Qr4000_J7HoI7y0B84_g00000__ARM_grp..debug_line$fm33a0xxev_pmu.h$.2_Af5000_lOjh94cQJQf_g00000__ARM_grp..debug_line$fm33a0xxev_pae.h$.2_sJ3000_RoohqLgJd45_300000__ARM_grp..debug_line$fm33a0xxev_lpuart.h$.2_oE2000_Ig0fu_ljcn3_300000__ARM_grp..debug_line$fm33a0xxev_lptim.h$.2_8q4000_BFHTRuxu1ie_300000__ARM_grp..debug_line$fm33a0xxev_lcd.h$.2_Y$4000_kUmWRnNV3_4_300000__ARM_grp..debug_line$fm33a0xxev_iwdt.h$.2_4L0000_LcDBel0usy8_300000__ARM_grp..debug_line$fm33a0xxev_include_all.h$.2_UQ0000_xxdaGLUj6Cf_300000__ARM_grp..debug_line$fm33a0xxev_i2c.h$.2_IS1000_g4ErNZQBGwd_300000__ARM_grp..debug_line$fm33a0xxev_hash.h$.2_kO0000_KuZ300H4_80_300000__ARM_grp..debug_line$fm33a0xxev_gpio.h$.2_815000_upDQZZvAzia_700000__ARM_grp..debug_line$fm33a0xxev_flash.h$.2_0_1000_TO3GMzQCtL1_300000__ARM_grp..debug_line$fm33a0xxev_et.h$.2_4h3000_57B3Rgey0je_300000__ARM_grp..debug_line$fm33a0xxev_dma.h$.2_ks8000_OrTMHX6QIe0_p00000__ARM_grp..debug_line$fm33a0xxev_dbg.h$.2_4f1000_pVDK34opiR1_300000__ARM_grp..debug_line$fm33a0xxev_crc.h$.2_8C4000_La7VPM3Tip8_k00000__ARM_grp..debug_line$fm33a0xxev_comp.h$.2_k_2000_e5VaGx8gTre_300000__ARM_grp..debug_line$fm33a0xxev_cmu.h$.2_Ekb000_qHj10Bv8MJ6_v00000__ARM_grp..debug_line$fm33a0xxev_cdif.h$.2_kJ0000_JQTXKb9R3mc_300000__ARM_grp..debug_line$fm33a0xxev_bt.h$.2_kV3000_MyPILKKQ6H1_300000__ARM_grp..debug_line$fm33a0xxev_bstim.h$.2_g$0000_A3CHw2qJcga_300000__ARM_grp..debug_line$fm33a0xxev_aes.h$.2_4p5000_ig0fpeqfTIb_l00000__ARM_grp..debug_line$fm33a0xxev_adc.h$.2_Yh2000_DMQIo6NAW82_300000__ARM_grp..debug_line$ex_rtc.h$.2_DP2000_DSa9_1ND590_510000__ARM_grp..debug_line$e2p.h$.2_Wb3000_h$Rdq_Blhv7_v00000__ARM_grp..debug_line$devicegpioinit.h$.2_0w4000_64Z46PStLCa_300000__ARM_grp..debug_line$delay.h$.2_EE0000_7GGSWSTJWL4_300000__ARM_grp..debug_line$define_all.h$.2_kN0000_fD9tyG24Hn2_300000__ARM_grp..debug_line$data_write_local.h$.2_I32000_1VLSL0PLXId_300000__ARM_grp..debug_line$core_cminstr.h$.2_gq1000_Kwrp1OO1xx3_b00000__ARM_grp..debug_line$core_cmfunc.h$.2_4o1000_5BOwGSyN3D1_z00000__ARM_grp..debug_line$core_cm0plus.h$.2_oo7000_NmZU1Rz5UO8_W00000__ARM_grp..debug_line$bintohex.h$.2_Y33000_duI5XZW3h40_300000__ARM_grp..debug_line$assert.h$.2_oA0000_EVegbDxopI6_300000__ARM_grp..debug_line$ReadDeviceData.h$.2_s22000_kYPOqAyPDy8_v00000__ARM_grp..debug_line$ReadDeviceData.c$.2_ME0000_NL3pXWtQuz0_300000__ARM_grp..debug_line$FM33A0XXEV.h$.2_0U4000_APjZ6EN_n61_800000__ARM_grp..debug_line$1powermanage.h$.2_Uz0000_vSamYc4k5o2_300000__ARM_grp..debug_line$1gprs.h$.2_B95000_i_AeRhQ$890_j20000__ARM_grp..debug_line$1billing.h$.2_GK2000_cmOxbPQKCb2_p00000__ARM_grp..debug_line$1ValveControl.h$.2_NL2000_a5DINTTQpWf_B00000__ARM_grp..debug_line$1ADC.h$.2_Qp1000_8FudzCBNeP8_900000__ARM_grp.user_init.h.2_ot0000_jZWuqvPHwt6_300000__ARM_grp.system_FM33A0XXEV.h.2_qK2000_3p2q1l7JLmc_f00000__ARM_grp.string.h.2_kw0000_aP4aobzpRT7_300000__ARM_grp.stdio.h.2_UP1000_6McqO1w0lYe_f00000__ARM_grp.stdint.h.2_QG1000_h7K9OtBs0h1_300000__ARM_grp.spi.h.2_gy0000_s_nnifot9te_300000__ARM_grp.rs485.h.2_Us0000_3$Cs1gcuNt3_300000__ARM_grp.port.h.2_Em1000_cWymiH7cCq9_b00000__ARM_grp.para.h.2_Ez8000_khDVHof8zWa_t40000__ARM_grp.mbcrc.h.2_8s0000_udjUqJW6TU5_300000__ARM_grp.math.h.2_bA3000_jfXlNmluFrf_700000__ARM_grp.inttypes.h.2_YM2000_HBynUsOMdLa_800000__ARM_grp.fm33a0xxev_wwdt.h.2_4H0000_TVah5VHd$Wd_300000__ARM_grp.fm33a0xxev_vrtc.h.2_YK1000_bGKK6ktMN$f_300000__ARM_grp.fm33a0xxev_uart.h.2_s_5000_gGxJA_bT3g3_r00000__ARM_grp.fm33a0xxev_u7816.h.2_sD5000_T7w3HnfvCn7_w00000__ARM_grp.fm33a0xxev_svd.h.2_YX4000_B$e1cGixg00_i00000__ARM_grp.fm33a0xxev_spi.h.2_AU2000_7eFMvsSXzw0_300000__ARM_grp.fm33a0xxev_rtc.h.2_sS3000_IylpavQ6INd_g00000__ARM_grp.fm33a0xxev_rng.h.2_IJ0000_vzTWbGvNuZe_300000__ARM_grp.fm33a0xxev_rmu.h.2_4L2000_C$q$9vNhOp0_300000__ARM_grp.fm33a0xxev_qspi.h.2_Qr4000_J7HoI7y0B84_g00000__ARM_grp.fm33a0xxev_pmu.h.2_Af5000_lOjh94cQJQf_g00000__ARM_grp.fm33a0xxev_pae.h.2_sJ3000_RoohqLgJd45_300000__ARM_grp.fm33a0xxev_lpuart.h.2_oE2000_Ig0fu_ljcn3_300000__ARM_grp.fm33a0xxev_lptim.h.2_8q4000_BFHTRuxu1ie_300000__ARM_grp.fm33a0xxev_lcd.h.2_Y$4000_kUmWRnNV3_4_300000__ARM_grp.fm33a0xxev_iwdt.h.2_4L0000_LcDBel0usy8_300000__ARM_grp.fm33a0xxev_include_all.h.2_UQ0000_xxdaGLUj6Cf_300000__ARM_grp.fm33a0xxev_i2c.h.2_IS1000_g4ErNZQBGwd_300000__ARM_grp.fm33a0xxev_hash.h.2_kO0000_KuZ300H4_80_300000__ARM_grp.fm33a0xxev_gpio.h.2_815000_upDQZZvAzia_700000__ARM_grp.fm33a0xxev_flash.h.2_0_1000_TO3GMzQCtL1_300000__ARM_grp.fm33a0xxev_et.h.2_4h3000_57B3Rgey0je_300000__ARM_grp.fm33a0xxev_dma.h.2_ks8000_OrTMHX6QIe0_p00000__ARM_grp.fm33a0xxev_dbg.h.2_4f1000_pVDK34opiR1_300000__ARM_grp.fm33a0xxev_crc.h.2_8C4000_La7VPM3Tip8_k00000__ARM_grp.fm33a0xxev_comp.h.2_k_2000_e5VaGx8gTre_300000__ARM_grp.fm33a0xxev_cmu.h.2_Ekb000_qHj10Bv8MJ6_v00000__ARM_grp.fm33a0xxev_cdif.h.2_kJ0000_JQTXKb9R3mc_300000__ARM_grp.fm33a0xxev_bt.h.2_kV3000_MyPILKKQ6H1_300000__ARM_grp.fm33a0xxev_bstim.h.2_g$0000_A3CHw2qJcga_300000__ARM_grp.fm33a0xxev_aes.h.2_4p5000_ig0fpeqfTIb_l00000__ARM_grp.fm33a0xxev_adc.h.2_Yh2000_DMQIo6NAW82_300000__ARM_grp.ex_rtc.h.2_DP2000_DSa9_1ND590_510000__ARM_grp.e2p.h.2_Wb3000_h$Rdq_Blhv7_v00000__ARM_grp.devicegpioinit.h.2_0w4000_64Z46PStLCa_300000__ARM_grp.delay.h.2_EE0000_7GGSWSTJWL4_300000__ARM_grp.define_all.h.2_kN0000_fD9tyG24Hn2_300000__ARM_grp.data_write_local.h.2_I32000_1VLSL0PLXId_300000__ARM_grp.core_cminstr.h.2_gq1000_Kwrp1OO1xx3_b00000__ARM_grp.core_cmfunc.h.2_4o1000_5BOwGSyN3D1_z00000__ARM_grp.core_cm0plus.h.2_oo7000_NmZU1Rz5UO8_W00000__ARM_grp.bintohex.h.2_Y33000_duI5XZW3h40_300000__ARM_grp.assert.h.2_oA0000_EVegbDxopI6_300000__ARM_grp.ReadDeviceData.h.2_s22000_kYPOqAyPDy8_v00000__ARM_grp.ReadDeviceData.c.2_ME0000_NL3pXWtQuz0_300000__ARM_grp.FM33A0XXEV.h.2_0U4000_APjZ6EN_n61_800000__ARM_grp.1powermanage.h.2_Uz0000_vSamYc4k5o2_300000__ARM_grp.1gprs.h.2_B95000_i_AeRhQ$890_j20000__ARM_grp.1billing.h.2_GK2000_cmOxbPQKCb2_p00000__ARM_grp.1ValveControl.h.2_NL2000_a5DINTTQpWf_B00000__ARM_grp.1ADC.h.2_Qp1000_8FudzCBNeP8_900000__ARM_grp..debug_info$user_init.h$.2_ot0000_jZWuqvPHwt6_300000__ARM_grp..debug_info$system_FM33A0XXEV.h$.2_qK2000_3p2q1l7JLmc_f00000__ARM_grp..debug_info$string.h$.2_kw0000_aP4aobzpRT7_300000__ARM_grp..debug_info$stdio.h$.2_UP1000_6McqO1w0lYe_f00000__ARM_grp..debug_info$stdint.h$.2_QG1000_h7K9OtBs0h1_300000__ARM_grp..debug_info$spi.h$.2_gy0000_s_nnifot9te_300000__ARM_grp..debug_info$rs485.h$.2_Us0000_3$Cs1gcuNt3_300000__ARM_grp..debug_info$port.h$.2_Em1000_cWymiH7cCq9_b00000__ARM_grp..debug_info$para.h$.2_Ez8000_khDVHof8zWa_t40000__ARM_grp..debug_info$mbcrc.h$.2_8s0000_udjUqJW6TU5_300000__ARM_grp..debug_info$math.h$.2_bA3000_jfXlNmluFrf_700000__ARM_grp..debug_info$inttypes.h$.2_YM2000_HBynUsOMdLa_800000__ARM_grp..debug_info$fm33a0xxev_wwdt.h$.2_4H0000_TVah5VHd$Wd_300000__ARM_grp..debug_info$fm33a0xxev_vrtc.h$.2_YK1000_bGKK6ktMN$f_300000__ARM_grp..debug_info$fm33a0xxev_uart.h$.2_s_5000_gGxJA_bT3g3_r00000__ARM_grp..debug_info$fm33a0xxev_u7816.h$.2_sD5000_T7w3HnfvCn7_w00000__ARM_grp..debug_info$fm33a0xxev_svd.h$.2_YX4000_B$e1cGixg00_i00000__ARM_grp..debug_info$fm33a0xxev_spi.h$.2_AU2000_7eFMvsSXzw0_300000__ARM_grp..debug_info$fm33a0xxev_rtc.h$.2_sS3000_IylpavQ6INd_g00000__ARM_grp..debug_info$fm33a0xxev_rng.h$.2_IJ0000_vzTWbGvNuZe_300000__ARM_grp..debug_info$fm33a0xxev_rmu.h$.2_4L2000_C$q$9vNhOp0_300000__ARM_grp..debug_info$fm33a0xxev_qspi.h$.2_Qr4000_J7HoI7y0B84_g00000__ARM_grp..debug_info$fm33a0xxev_pmu.h$.2_Af5000_lOjh94cQJQf_g00000__ARM_grp..debug_info$fm33a0xxev_pae.h$.2_sJ3000_RoohqLgJd45_300000__ARM_grp..debug_info$fm33a0xxev_lpuart.h$.2_oE2000_Ig0fu_ljcn3_300000__ARM_grp..debug_info$fm33a0xxev_lptim.h$.2_8q4000_BFHTRuxu1ie_300000__ARM_grp..debug_info$fm33a0xxev_lcd.h$.2_Y$4000_kUmWRnNV3_4_300000__ARM_grp..debug_info$fm33a0xxev_iwdt.h$.2_4L0000_LcDBel0usy8_300000__ARM_grp..debug_info$fm33a0xxev_include_all.h$.2_UQ0000_xxdaGLUj6Cf_300000__ARM_grp..debug_info$fm33a0xxev_i2c.h$.2_IS1000_g4ErNZQBGwd_300000__ARM_grp..debug_info$fm33a0xxev_hash.h$.2_kO0000_KuZ300H4_80_300000__ARM_grp..debug_info$fm33a0xxev_gpio.h$.2_815000_upDQZZvAzia_700000__ARM_grp..debug_info$fm33a0xxev_flash.h$.2_0_1000_TO3GMzQCtL1_300000__ARM_grp..debug_info$fm33a0xxev_et.h$.2_4h3000_57B3Rgey0je_300000__ARM_grp..debug_info$fm33a0xxev_dma.h$.2_ks8000_OrTMHX6QIe0_p00000__ARM_grp..debug_info$fm33a0xxev_dbg.h$.2_4f1000_pVDK34opiR1_300000__ARM_grp..debug_info$fm33a0xxev_crc.h$.2_8C4000_La7VPM3Tip8_k00000__ARM_grp..debug_info$fm33a0xxev_comp.h$.2_k_2000_e5VaGx8gTre_300000__ARM_grp..debug_info$fm33a0xxev_cmu.h$.2_Ekb000_qHj10Bv8MJ6_v00000__ARM_grp..debug_info$fm33a0xxev_cdif.h$.2_kJ0000_JQTXKb9R3mc_300000__ARM_grp..debug_info$fm33a0xxev_bt.h$.2_kV3000_MyPILKKQ6H1_300000__ARM_grp..debug_info$fm33a0xxev_bstim.h$.2_g$0000_A3CHw2qJcga_300000__ARM_grp..debug_info$fm33a0xxev_aes.h$.2_4p5000_ig0fpeqfTIb_l00000__ARM_grp..debug_info$fm33a0xxev_adc.h$.2_Yh2000_DMQIo6NAW82_300000__ARM_grp..debug_info$ex_rtc.h$.2_DP2000_DSa9_1ND590_510000__ARM_grp..debug_info$e2p.h$.2_Wb3000_h$Rdq_Blhv7_v00000__ARM_grp..debug_info$devicegpioinit.h$.2_0w4000_64Z46PStLCa_300000__ARM_grp..debug_info$delay.h$.2_EE0000_7GGSWSTJWL4_300000__ARM_grp..debug_info$define_all.h$.2_kN0000_fD9tyG24Hn2_300000__ARM_grp..debug_info$data_write_local.h$.2_I32000_1VLSL0PLXId_300000__ARM_grp..debug_info$core_cminstr.h$.2_gq1000_Kwrp1OO1xx3_b00000__ARM_grp..debug_info$core_cmfunc.h$.2_4o1000_5BOwGSyN3D1_z00000__ARM_grp..debug_info$core_cm0plus.h$.2_oo7000_NmZU1Rz5UO8_W00000__ARM_grp..debug_info$bintohex.h$.2_Y33000_duI5XZW3h40_300000__ARM_grp..debug_info$assert.h$.2_oA0000_EVegbDxopI6_300000__ARM_grp..debug_info$ReadDeviceData.h$.2_s22000_kYPOqAyPDy8_v00000__ARM_grp..debug_info$ReadDeviceData.c$.2_ME0000_NL3pXWtQuz0_300000__ARM_grp..debug_info$FM33A0XXEV.h$.2_0U4000_APjZ6EN_n61_800000__ARM_grp..debug_info$1powermanage.h$.2_Uz0000_vSamYc4k5o2_300000__ARM_grp..debug_info$1gprs.h$.2_B95000_i_AeRhQ$890_j20000__ARM_grp..debug_info$1billing.h$.2_GK2000_cmOxbPQKCb2_p00000__ARM_grp..debug_info$1ValveControl.h$.2_NL2000_a5DINTTQpWf_B00000__ARM_grp..debug_info$1ADC.h$.2_Qp1000_8FudzCBNeP8_900000__ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000BeginflagDataStoredFlagNumDataStoredNOW_Data_DDRLast_Data_DDRddr_index_2ModbusDlgparmAccessLLJ_Msg__asm___16_ReadDeviceData_c_ef47cb5f____REVSH__asm___16_ReadDeviceData_c_ef47cb5f____REV16__ARM_asm.debug_abbrev.1__ARM_grp_.debug_pubnames$94__ARM_grp_.debug_pubnames$87__ARM_grp_.debug_pubnames$80__ARM_grp_.debug_pubnames$73__ARM_grp_.debug_pubnames$66__ARM_grp_.debug_pubnames$59__ARM_grp_.debug_pubnames$52__ARM_grp_.debug_pubnames$45__ARM_grp_.debug_pubnames$38__ARM_grp_.debug_pubnames$31__ARM_grp_.debug_pubnames$24__ARM_grp_.debug_pubnames$17__ARM_grp_.debug_pubnames$10__ARM_grp_.debug_macinfo$4__ARM_grp_.debug_loc$96__ARM_grp_.debug_loc$89__ARM_grp_.debug_loc$82__ARM_grp_.debug_loc$75__ARM_grp_.debug_loc$68__ARM_grp_.debug_loc$61__ARM_grp_.debug_loc$54__ARM_grp_.debug_loc$47__ARM_grp_.debug_loc$40__ARM_grp_.debug_loc$33__ARM_grp_.debug_loc$26__ARM_grp_.debug_loc$19__ARM_grp_.debug_line$92__ARM_grp_.debug_line$85__ARM_grp_.debug_line$78__ARM_grp_.debug_line$71__ARM_grp_.debug_line$64__ARM_grp_.debug_line$57__ARM_grp_.debug_line$50__ARM_grp_.debug_line$43__ARM_grp_.debug_line$36__ARM_grp_.debug_line$29__ARM_grp_.debug_line$22__ARM_grp_.debug_line$15__ARM_grp_.debug_line$1__ARM_grp_.debug_info$93__ARM_grp_.debug_info$86__ARM_grp_.debug_info$79__ARM_grp_.debug_info$72__ARM_grp_.debug_info$65__ARM_grp_.debug_info$58__ARM_grp_.debug_info$51__ARM_grp_.debug_info$44__ARM_grp_.debug_info$37__ARM_grp_.debug_info$30__ARM_grp_.debug_info$23__ARM_grp_.debug_info$16__ARM_grp_.debug_info$9__ARM_grp_.debug_info$2__ARM_grp_.debug_frame$97__ARM_grp_.debug_frame$90__ARM_grp_.debug_frame$83__ARM_grp_.debug_frame$76__ARM_grp_.debug_frame$69__ARM_grp_.debug_frame$62__ARM_grp_.debug_frame$55__ARM_grp_.debug_frame$48__ARM_grp_.debug_frame$41__ARM_grp_.debug_frame$34__ARM_grp_.debug_frame$27__ARM_grp_.debug_frame$20.data.bssi.Temperature_alarmi.Read485_processi.Pressure_alarmi.Parameter_assignmenti.PULSE_Recordingi.Modbus_RS485Bi.LLJ_sendFramei.LLJ_ModbusHandle_SIZHUV2_0i.LLJ_ModbusHandle_CRCDatai.LLJ_ModbusHandlei.Analysis_Float48BuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$~SHL$OSPACE$EBA8$REQ8$PRES8$EABIv2i.Analysis_FloatBuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$~SHL$OSPACE$EBA8$PRES8$EABIv2..\Pre_Drivers\ReadDeviceData.c.revsh_text.rev16_text..\\Pre_Drivers\\ReadDeviceData.c$d.realdata$d$tATaeabiCortex-M0         
 C2.09ARM
.4"8v<¼_øH  )$$ÔôøHà@xÊ¸ä¯Tð@0lÌ @"@"\"L#T\r#Lr$T;Æ$D;
%D;N%L;%H;â%H;*&L;v&T;Ê&L;'P;f'P;¶'<;ò'L;>(H;(L\Ò(Ä\)\2+X\,\-\.Ð\f0\ú2Ø\Ò4\b6\î7ô\â8$\:,\2;ìL<DLb<Læ<¬L=°LB>LÎC°L~EL~FLGlLzG@LºHÐLJÐLZLÔ.M|ªM4ÞM4N|N<ÊN`*Ox¢O6PJP\¦P\Q ý"Q4'VV¡'÷V$'W%'@W('hW''W1'ÀW/'ïW%'X'';X+'fX$'X&'°X&äØXcÖàX §YcýYL¬aP\üa8r4ecæýDeLàfD\$g>,hcåý<hLThD\h    lcäý,l<Lh\´Û ´cýÈHLP\`¸'p¨ cßýØLp£l\Ü£°n »cý »xL½\¬½à'¾&7 ´¾cîýÄ¾$LèÊd\LËx ÄÌcíýÔÌ¨L|Ûd\àÛÀÇ Ücïý°ÜPLád\dáÄ(âcóý8â4Llöd\ÐöÀX÷cý ÷LLì    d\P
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