ELF ( |D 4 ( @ºpGÀºpG ..\\Function\\HARDWARE_WATCHDOG\\hardware_watchdog.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM __asm___19_hardware_watchdog_c____REV16 P 9 ..\\Core\\Include\\ core_cminstr.h ..\\Function\\HARDWARE_WATCHDOG\\hardware_watchdog.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM __asm___19_hardware_watchdog_c____REVSH P 9 ..\\Core\\Include\\ core_cminstr.h 0 ÿÿÿÿarmcc+ |
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..\Function\HARDWARE_WATCHDOG\hardware_watchdog.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM T H ..\Function\HARDWARE_WATCHDOG\hardware_watchdog.c __DATE__ "Jun 11 2024" __TIME__ "13:38:12" __STDC__ 1 __STDC_VERSION__ 199901L __STDC_HOSTED__ 1 __STDC_ISO_10646__ 200607 __EDG__ 1 __EDG_VERSION__ 407 __EDG_SIZE_TYPE__ unsigned int __EDG_PTRDIFF_TYPE__ int __GNUC__ 4 __GNUC_STDC_INLINE__ 1 __GNUC_MINOR__ 7 __GNUC_PATCHLEVEL__ 0 __VERSION__ "4.7 (EDG gcc mode)" __CHAR16_TYPE__ unsigned short __CHAR32_TYPE__ unsigned int __USER_LABEL_PREFIX__ __CHAR_UNSIGNED__ 1 __WCHAR_UNSIGNED__ 1 __SIZE_TYPE__ unsigned int __PTRDIFF_TYPE__ int __WCHAR_TYPE__ unsigned short __WINT_TYPE__ unsigned short __INTMAX_TYPE__ long long __UINTMAX_TYPE__ unsigned long long __sizeof_int 4 __sizeof_long 4 __sizeof_ptr 4 __ARMCC_VERSION 5060750 __TARGET_CPU_CORTEX_M0 1 __TARGET_FPU_SOFTVFP 1 __TARGET_FPU_SOFTVFP 1 __MICROLIB 1 __UVISION_VERSION 525 _RTE_ 1 __VTOR_PRESENT 1 __CC_ARM 1 __arm 1 __arm__ 1 __TARGET_ARCH_6S_M 1 __TARGET_ARCH_ARM 0 __TARGET_ARCH_THUMB 3 __TARGET_ARCH_A64 0 __TARGET_ARCH_AARCH32 1 __TARGET_PROFILE_M 1 __TARGET_FEATURE_HALFWORD 1 __TARGET_FEATURE_THUMB 1 __TARGET_FEATURE_DMB 1 __TARGET_FEATURE_EXTENSION_REGISTER_COUNT 0 __APCS_INTERWORK 1 __thumb 1 __thumb__ 1 __t32__ 1 __OPTIMISE_SPACE 1 __OPTIMIZE_SIZE__ 1 __OPTIMISE_LEVEL 0 __SOFTFP__ 1 % . __stdint_h __ARMCLIB_VERSION 5060037 __INT64 __int64 __INT64_C_SUFFIX__ ll __PASTE2(x,y) x ## y __PASTE(x,y) __PASTE2(x, y) __INT64_C(x) __ESCAPE__(__PASTE(x, __INT64_C_SUFFIX__)) __UINT64_C(x) __ESCAPE__(__PASTE(x ## u, __INT64_C_SUFFIX__)) __LONGLONG long long #__STDINT_DECLS %__CLIBNS ,__CLIBNS yINT8_MIN -128 zINT16_MIN -32768 {INT32_MIN (~0x7fffffff) |INT64_MIN __INT64_C(~0x7fffffffffffffff) INT8_MAX 127 INT16_MAX 32767 INT32_MAX 2147483647 INT64_MAX __INT64_C(9223372036854775807)
UINT8_MAX 255 UINT16_MAX 65535 UINT32_MAX 4294967295u UINT64_MAX __UINT64_C(18446744073709551615) INT_LEAST8_MIN -128 INT_LEAST16_MIN -32768 INT_LEAST32_MIN (~0x7fffffff) INT_LEAST64_MIN __INT64_C(~0x7fffffffffffffff) INT_LEAST8_MAX 127 INT_LEAST16_MAX 32767 INT_LEAST32_MAX 2147483647 INT_LEAST64_MAX __INT64_C(9223372036854775807) UINT_LEAST8_MAX 255 UINT_LEAST16_MAX 65535 UINT_LEAST32_MAX 4294967295u UINT_LEAST64_MAX __UINT64_C(18446744073709551615) ¡INT_FAST8_MIN (~0x7fffffff) ¢INT_FAST16_MIN (~0x7fffffff) £INT_FAST32_MIN (~0x7fffffff) ¤INT_FAST64_MIN __INT64_C(~0x7fffffffffffffff) §INT_FAST8_MAX 2147483647 ¨INT_FAST16_MAX 2147483647 ©INT_FAST32_MAX 2147483647 ªINT_FAST64_MAX __INT64_C(9223372036854775807) UINT_FAST8_MAX 4294967295u ®UINT_FAST16_MAX 4294967295u ¯UINT_FAST32_MAX 4294967295u °UINT_FAST64_MAX __UINT64_C(18446744073709551615) ¸INTPTR_MIN INT32_MIN ¿INTPTR_MAX INT32_MAX ÆUINTPTR_MAX UINT32_MAX ÌINTMAX_MIN __ESCAPE__(~0x7fffffffffffffffll) ÏINTMAX_MAX __ESCAPE__(9223372036854775807ll) ÒUINTMAX_MAX __ESCAPE__(18446744073709551615ull) ÛPTRDIFF_MIN INT32_MIN ÜPTRDIFF_MAX INT32_MAX àSIG_ATOMIC_MIN (~0x7fffffff) áSIG_ATOMIC_MAX 2147483647 çSIZE_MAX UINT32_MAX íWCHAR_MIN îWCHAR_MAX ôWCHAR_MIN 0 õWCHAR_MAX 65535 ùWINT_MIN (~0x7fffffff) úWINT_MAX 2147483647 INT8_C(x) (x) INT16_C(x) (x) INT32_C(x) (x) INT64_C(x) __INT64_C(x) UINT8_C(x) (x ## u) UINT16_C(x) (x ## u) UINT32_C(x) (x ## u) UINT64_C(x) __UINT64_C(x) INTMAX_C(x) __ESCAPE__(x ## ll) UINTMAX_C(x) __ESCAPE__(x ## ull) ¸__INT64 ¹__LONGLONG L B D:\Keil5\ARM\ARMCC\Bin\..\include\ stdint.h 4 D:\Keil5\ARM\ARMCC\Bin\..\include\stdint.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] signed char short int long long unsigned char unsigned short unsigned int unsigned long long Pint8_t 8 Pint16_t 9 Pint32_t : Pint64_t § ; Puint8_t ´ > Puint8_t ´ > Puint16_t Å ? Puint32_t × @ Puint64_t ç A Pu32 fCPu16 VDPu8 8EPint_least8_t M Pint_least16_t N Pint_least32_t O Pint_least64_t § P Puint_least8_t ´ S Puint_least16_t Å T Puint_least32_t × U Puint_least64_t ç V Pint_fast8_t [ Pint_fast16_t \ Pint_fast32_t ] Pint_fast64_t § ^ Puint_fast8_t × a Puint_fast16_t × b Puint_fast32_t × c Puint_fast64_t ç d Pintptr_t k Puintptr_t × l Pintmax_t § p!Puintmax_t ç q! '__CORE_CMINSTR_H <__NOP __nop D__WFI __wfi L__WFE __wfe S__SEV __sev \__ISB() do { __schedule_barrier(); __isb(0xF); __schedule_barrier(); } while (0) g__DSB() do { __schedule_barrier(); __dsb(0xF); __schedule_barrier(); } while (0) r__DMB() do { __schedule_barrier(); __dmb(0xF); __schedule_barrier(); } while (0) __REV __rev ©__ROR __ror ´__BKPT(value) __breakpoint(value) Ú__CLZ __clz @ 6 ..\Core\Include\ core_cminstr.h
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..\Core\Include\core_cminstr.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM ;Á9__RBIT f $f value a__result f \result f \s '__CORE_CMFUNC_H @ 5 ..\Core\Include\ core_cmfunc.h
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..\Core\Include\core_cmfunc.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM ;ÿ@__get_CONTROL f a__result f Y__regControl f P <¸M__set_CONTROL $f control Y__regControl f P ;òZ__get_IPSR f a__result f Y__regIPSR f P ;¬g__get_APSR f a__result f Y__regAPSR f P ;æt__get_xPSR f a__result f Y__regXPSR f P ;¯__get_PSP f a__result f Y__regProcessStackPointer f P <ø__set_PSP $f topOfProcStack Y__regProcessStackPointer f P ;¾__get_MSP f a__result f Y__regMainStackPointer f P <¨__set_MSP $f topOfMainStack Y__regMainStackPointer f P ;ŵ__get_PRIMASK f a__result f Y__regPriMask f P <ÿÂ__set_PRIMASK $f priMask Y__regPriMask f P __CORE_CM0PLUS_H_GENERIC "@__CM0PLUS_CMSIS_VERSION_MAIN ( 5U) A__CM0PLUS_CMSIS_VERSION_SUB ( 0U) B__CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | __CM0PLUS_CMSIS_VERSION_SUB ) E__CORTEX_M (0U) Q__ASM __asm R__INLINE __inline S__STATIC_INLINE static __inline T__NO_RETURN __declspec(noreturn) U__USED __attribute__((used)) V__WEAK __attribute__((weak)) W__UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) __FPU_USED 0U ÆÇÒ__CORE_CM0PLUS_H_DEPENDANT ÿ__I volatile const __O volatile __IO volatile
__IM volatile const __OM volatile __IOM volatile ³APSR_N_Pos 31U ´APSR_N_Msk (1UL << APSR_N_Pos) ¶APSR_Z_Pos 30U ·APSR_Z_Msk (1UL << APSR_Z_Pos) ¹APSR_C_Pos 29U ºAPSR_C_Msk (1UL << APSR_C_Pos) ¼APSR_V_Pos 28U ½APSR_V_Msk (1UL << APSR_V_Pos) ÎIPSR_ISR_Pos 0U ÏIPSR_ISR_Msk (0x1FFUL ) æxPSR_N_Pos 31U çxPSR_N_Msk (1UL << xPSR_N_Pos) éxPSR_Z_Pos 30U êxPSR_Z_Msk (1UL << xPSR_Z_Pos) ìxPSR_C_Pos 29U íxPSR_C_Msk (1UL << xPSR_C_Pos) ïxPSR_V_Pos 28U ðxPSR_V_Msk (1UL << xPSR_V_Pos) òxPSR_T_Pos 24U óxPSR_T_Msk (1UL << xPSR_T_Pos) õxPSR_ISR_Pos 0U öxPSR_ISR_Msk (0x1FFUL ) CONTROL_SPSEL_Pos 1U CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) CONTROL_nPRIV_Pos 0U CONTROL_nPRIV_Msk (1UL ) ÈSCB_CPUID_IMPLEMENTER_Pos 24U ÉSCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) ËSCB_CPUID_VARIANT_Pos 20U ÌSCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) ÎSCB_CPUID_ARCHITECTURE_Pos 16U ÏSCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) ÑSCB_CPUID_PARTNO_Pos 4U ÒSCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) ÔSCB_CPUID_REVISION_Pos 0U ÕSCB_CPUID_REVISION_Msk (0xFUL ) ØSCB_ICSR_NMIPENDSET_Pos 31U ÙSCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) ÛSCB_ICSR_PENDSVSET_Pos 28U ÜSCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) ÞSCB_ICSR_PENDSVCLR_Pos 27U ßSCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) áSCB_ICSR_PENDSTSET_Pos 26U âSCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) äSCB_ICSR_PENDSTCLR_Pos 25U åSCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) çSCB_ICSR_ISRPREEMPT_Pos 23U èSCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) êSCB_ICSR_ISRPENDING_Pos 22U ëSCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) íSCB_ICSR_VECTPENDING_Pos 12U îSCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) ðSCB_ICSR_VECTACTIVE_Pos 0U ñSCB_ICSR_VECTACTIVE_Msk (0x1FFUL ) õSCB_VTOR_TBLOFF_Pos 8U öSCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) úSCB_AIRCR_VECTKEY_Pos 16U ûSCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) ýSCB_AIRCR_VECTKEYSTAT_Pos 16U þSCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) SCB_AIRCR_ENDIANESS_Pos 15U SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) SCB_AIRCR_SYSRESETREQ_Pos 2U SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) SCB_AIRCR_VECTCLRACTIVE_Pos 1U SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) SCB_SCR_SEVONPEND_Pos 4U SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) SCB_SCR_SLEEPDEEP_Pos 2U SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) SCB_SCR_SLEEPONEXIT_Pos 1U SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) SCB_CCR_STKALIGN_Pos 9U SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) SCB_CCR_UNALIGN_TRP_Pos 3U SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) SCB_SHCSR_SVCALLPENDED_Pos 15U SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) ´SysTick_CTRL_COUNTFLAG_Pos 16U µSysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) ·SysTick_CTRL_CLKSOURCE_Pos 2U ¸SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) ºSysTick_CTRL_TICKINT_Pos 1U »SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) ½SysTick_CTRL_ENABLE_Pos 0U ¾SysTick_CTRL_ENABLE_Msk (1UL ) ÁSysTick_LOAD_RELOAD_Pos 0U ÂSysTick_LOAD_RELOAD_Msk (0xFFFFFFUL ) ÅSysTick_VAL_CURRENT_Pos 0U ÆSysTick_VAL_CURRENT_Msk (0xFFFFFFUL ) ÉSysTick_CALIB_NOREF_Pos 31U ÊSysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) ÌSysTick_CALIB_SKEW_Pos 30U ÍSysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) ÏSysTick_CALIB_TENMS_Pos 0U ÐSysTick_CALIB_TENMS_Msk (0xFFFFFFUL ) éMPU_TYPE_IREGION_Pos 16U êMPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) ìMPU_TYPE_DREGION_Pos 8U íMPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) ïMPU_TYPE_SEPARATE_Pos 0U ðMPU_TYPE_SEPARATE_Msk (1UL ) óMPU_CTRL_PRIVDEFENA_Pos 2U ôMPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) öMPU_CTRL_HFNMIENA_Pos 1U ÷MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) ùMPU_CTRL_ENABLE_Pos 0U úMPU_CTRL_ENABLE_Msk (1UL ) ýMPU_RNR_REGION_Pos 0U þMPU_RNR_REGION_Msk (0xFFUL ) MPU_RBAR_ADDR_Pos 8U MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) MPU_RBAR_VALID_Pos 4U
MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) MPU_RBAR_REGION_Pos 0U MPU_RBAR_REGION_Msk (0xFUL ) MPU_RASR_ATTRS_Pos 16U MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) MPU_RASR_XN_Pos 28U MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) MPU_RASR_AP_Pos 24U MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) MPU_RASR_TEX_Pos 19U MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) MPU_RASR_S_Pos 18U MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) MPU_RASR_C_Pos 17U MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) MPU_RASR_B_Pos 16U MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) MPU_RASR_SRD_Pos 8U ¡MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) £MPU_RASR_SIZE_Pos 1U ¤MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) ¦MPU_RASR_ENABLE_Pos 0U §MPU_RASR_ENABLE_Msk (1UL ) Ä_VAL2FLD(field,value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) Ì_FLD2VAL(field,value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) ÙSCS_BASE (0xE000E000UL) ÚSysTick_BASE (SCS_BASE + 0x0010UL) ÛNVIC_BASE (SCS_BASE + 0x0100UL) ÜSCB_BASE (SCS_BASE + 0x0D00UL) ÞSCB ((SCB_Type *) SCB_BASE ) ßSysTick ((SysTick_Type *) SysTick_BASE ) àNVIC ((NVIC_Type *) NVIC_BASE ) ãMPU_BASE (SCS_BASE + 0x0D90UL) äMPU ((MPU_Type *) MPU_BASE ) _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) ..\Core\Include\ D:\Keil5\ARM\ARMCC\Bin\..\include\ core_cm0plus.h stdint.h core_cminstr.h core_cmfunc.h °
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..\Core\Include\core_cm0plus.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM *!_reserved0 f # !V f # !C f # !Z f # !N f # S§ b À w f PAPSR_Type °*å!ISR f # !_reserved0 f # Sø b 9 w f PIPSR_Type eË*!ISR f # !_reserved0 f # !T f # !_reserved1 f # !V f # !C f # !Z f # !N f # S¦ b w f PxPSR_Type ã*ø!nPRIV f # !SPSEL f # !_reserved1 f # S b 8 w f PCONTROL_Type x
* ® ISER ¥# Åf RESERVED0 º#ß ICER Ö#÷f RSERVED1 ì# ISPR #©f RESERVED2 #Ä ICPR ;#Üf RESERVED3 Q#ùf ? RESERVED4 n# IP # tf PNVIC_Type §*¹( CPUID ?# ICSR # VTOR # AIRCR # SCR # CCR # RESERVED1 f # SHP # SHCSR #$ f t9PSCB_Type ¸Å* CTRL # LOAD # VAL # CALIB ?# PSysTick_Type T±*Þ TYPE ?# CTRL # RNR # RBAR # RASR # PMPU_Type æ<
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NVIC_EnableIRQ $( IRQn <¶
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NVIC_DisableIRQ $( IRQn ;ò
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NVIC_GetPendingIRQ f $( IRQn a__result f < ÀNVIC_SetPendingIRQ $( IRQn <Â ÏNVIC_ClearPendingIRQ $( IRQn <ö áNVIC_SetPriority $( IRQn $f priority ;° ùNVIC_GetPriority f $( IRQn a__result f <Ê NVIC_SystemReset ;÷ ¬SCB_GetFPUType f a__result f ;° ËSysTick_Config f $f ticks a__result f ! " __stdio_h __ARMCLIB_VERSION 5060037 "_ARMABI __declspec(__nothrow) %__STDIO_DECLS '__CLIBNS -__CLIBNS <NULL =NULL 0 g_SYS_OPEN 16 ¥stdin (&__CLIBNS __stdin) §stdout (&__CLIBNS __stdout) ©stderr (&__CLIBNS __stderr) ¬_IOFBF 0x100 _IOLBF 0x200 ®_IONBF 0x400 ±BUFSIZ (512) ³FOPEN_MAX _SYS_OPEN ¹FILENAME_MAX 256 ¾L_tmpnam FILENAME_MAX ÄTMP_MAX 256 ÌEOF (-1) ÒSEEK_SET 0 ÓSEEK_CUR 1 ÔSEEK_END 2 Ú_IOBIN 0x04 Ü__STDIN_BUFSIZ (64) Ý__STDOUT_BUFSIZ (64) Þ__STDERR_BUFSIZ (16) ¿getchar() getc(stdin) àputchar(c) putc(c, stdout) L A D:\Keil5\ARM\ARMCC\Bin\..\include\ stdio.h ´ D:\Keil5\ARM\ARMCC\Bin\..\include\stdio.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] unsigned int unsigned long long Psize_t 5P__va_list F *ó __state1 # __state2 # )¦__fpos_t_struct __pos # __mbstate Î # Pfpos_t ó a-__FILE PFILE 4lq__stdin <q__stdout <q__stderr <"<q__aeabi_stdin tq__aeabi_stdout tq__aeabi_stderr t l ¸ H __stdin V __stdout e __stderr x __aeabi_stdin __aeabi_stdout ¡ __aeabi_stderr $ % & $FM33A0XXEV_H .__RCHF_INITIAL_CLOCK (8000000) /__RCMF_CLOCK (2000000) 0__RCLP_CLOCK (32000) 1__XTLF_CLOCK (32768) n__CM0_REV 0x0100 o__MPU_PRESENT 1 p__VTOR_PRESENT 1 q__NVIC_PRIO_BITS 2 r__Vendor_SysTickConfig 0 uv¿FLASH_BASE (( uint32_t)0x00000000) ÀSRAM_BASE (( uint32_t)0x20000000) ÁPERIPH_BASE (( uint32_t)0x40000000) ÊPMU_BASE (PERIPH_BASE +0x00002000) ËDBG_BASE (PERIPH_BASE +0x00000000) ÌFLS_BASE (PERIPH_BASE +0x00001000) ÍRMU_BASE (PERIPH_BASE +0x00002800) ÎIWDT_BASE (PERIPH_BASE +0x00011400) ÏWWDT_BASE (PERIPH_BASE +0x00011800) ÐCMU_BASE (PERIPH_BASE +0x00002400) ÑCDIF_BASE (PERIPH_BASE +0x0001E000) ÒVRTC_BASE (PERIPH_BASE +0x0001F800) ÓSVD_BASE (PERIPH_BASE +0x00012800) ÔAES_BASE (PERIPH_BASE +0x00013800) ÕPAE_BASE (PERIPH_BASE +0x00001400) ÖHASH_BASE (PERIPH_BASE +0x00001800) ×RNG_BASE (PERIPH_BASE +0x00013C00) ØCOMP_BASE (PERIPH_BASE +0x00015400) ÙI2C0_BASE (PERIPH_BASE +0x00012400) ÚI2C1_BASE (PERIPH_BASE +0x00015000) ÛUARTIR_BASE (PERIPH_BASE +0x00017C00) ÜUART0_BASE (PERIPH_BASE +0x00012000) ÝUART1_BASE (PERIPH_BASE +0x00016800) ÞUART2_BASE (PERIPH_BASE +0x00016C00) ßUART3_BASE (PERIPH_BASE +0x00017000) àUART4_BASE (PERIPH_BASE +0x00017400) áUART5_BASE (PERIPH_BASE +0x00017800) âLPUART0_BASE (PERIPH_BASE +0x00014000) ãLPUART1_BASE (PERIPH_BASE +0x00014400) äSPI0_BASE (PERIPH_BASE +0x00010400) åSPI1_BASE (PERIPH_BASE +0x00010800) æSPI2_BASE (PERIPH_BASE +0x00014800) çSPI3_BASE (PERIPH_BASE +0x00014C00) èSPI4_BASE (PERIPH_BASE +0x00016400) éU7816_BASE (PERIPH_BASE +0x00011C00) êQSPI_BASE (PERIPH_BASE +0x00000800) ëDMA_BASE (PERIPH_BASE +0x00000400) ìCRC_BASE (PERIPH_BASE +0x00010000) íBT1_BASE (PERIPH_BASE +0x00013000) îBT2_BASE (PERIPH_BASE +0x00013044) ïET1_BASE (PERIPH_BASE +0x00013090) ðET2_BASE (PERIPH_BASE +0x000130B0) ñET3_BASE (PERIPH_BASE +0x000130D0) òET4_BASE (PERIPH_BASE +0x000130F0) óETCNT_BASE (PERIPH_BASE +0x00013110) ôBSTIM_BASE (PERIPH_BASE +0x00016000) õLPTIM_BASE (PERIPH_BASE +0x00013400) öRTC_BASE (PERIPH_BASE +0x00011000) ÷LCD_BASE (PERIPH_BASE +0x00010C00) øADC_BASE (PERIPH_BASE +0x0001FA00) ùCIC_BASE (PERIPH_BASE +0x00015C00) úGPIOA_BASE (PERIPH_BASE +0x00000C00) ûGPIOB_BASE (PERIPH_BASE +0x00000C40) üGPIOC_BASE (PERIPH_BASE +0x00000C80) ýGPIOD_BASE (PERIPH_BASE +0x00000CC0) þGPIOE_BASE (PERIPH_BASE +0x00000D00) ÿGPIOF_BASE (PERIPH_BASE +0x00000D40) GPIOG_BASE (PERIPH_BASE +0x00000D80) GPIOH_BASE (PERIPH_BASE +0x0001FC00) GPIO_BASE (PERIPH_BASE +0x00000DC0) PMU ((PMU_Type *) PMU_BASE ) DBG ((DBG_Type *) DBG_BASE ) FLS ((FLS_Type *) FLS_BASE ) RMU ((RMU_Type *) RMU_BASE ) IWDT ((IWDT_Type *) IWDT_BASE ) WWDT ((WWDT_Type *) WWDT_BASE ) CMU ((CMU_Type *) CMU_BASE ) CDIF ((CDIF_Type *) CDIF_BASE ) VRTC ((VRTC_Type *) VRTC_BASE ) SVD ((SVD_Type *) SVD_BASE ) AES ((AES_Type *) AES_BASE ) PAE ((PAE_Type *) PAE_BASE ) HASH ((HASH_Type *) HASH_BASE ) RNG ((RNG_Type *) RNG_BASE ) COMP ((COMP_Type *) COMP_BASE ) I2C0 ((I2C_Type *) I2C0_BASE ) I2C1 ((I2C_Type *) I2C1_BASE ) UARTIR ((UARTIR_Type *) UARTIR_BASE ) UART0 ((UART_Type *) UART0_BASE ) UART1 ((UART_Type *) UART1_BASE ) UART2 ((UART_Type *) UART2_BASE ) UART3 ((UART_Type *) UART3_BASE ) UART4 ((UART_Type *) UART4_BASE ) UART5 ((UART_Type *) UART5_BASE ) LPUART0 ((LPUART_Type *) LPUART0_BASE ) ¡LPUART1 ((LPUART_Type *) LPUART1_BASE ) ¢SPI0 ((SPI_Type *) SPI0_BASE ) £SPI1 ((SPI_Type *) SPI1_BASE ) ¤SPI2 ((SPI_Type *) SPI2_BASE ) ¥SPI3 ((SPI_Type *) SPI3_BASE ) ¦SPI4 ((SPI_Type *) SPI4_BASE ) §U7816 ((U7816_Type *) U7816_BASE ) ¨QSPI ((QSPI_Type *) QSPI_BASE ) ©DMA ((DMA_Type *) DMA_BASE ) ªCRC ((CRC_Type *) CRC_BASE ) «BT1 ((BT_Type *) BT1_BASE ) ¬BT2 ((BT_Type *) BT2_BASE ) ET1 ((ET_Type *) ET1_BASE ) ®ET2 ((ET_Type *) ET2_BASE ) ¯ET3 ((ET_Type *) ET3_BASE ) °ET4 ((ET_Type *) ET4_BASE ) ±ETCNT ((ETCNT_Type *) ETCNT_BASE ) ²BSTIM ((BSTIM_Type *) BSTIM_BASE ) ³LPTIM ((LPTIM_Type *) LPTIM_BASE ) ´RTC ((RTC_Type *) RTC_BASE ) µLCD ((LCD_Type *) LCD_BASE ) ¶ADC ((ADC_Type *) ADC_BASE ) ·CIC ((CIC_Type *) CIC_BASE ) ¸GPIOA ((GPIO_Type *) GPIOA_BASE ) ¹GPIOB ((GPIO_Type *) GPIOB_BASE ) ºGPIOC ((GPIO_Type *) GPIOC_BASE ) »GPIOD ((GPIO_Type *) GPIOD_BASE ) ¼GPIOE ((GPIO_Type *) GPIOE_BASE ) ½GPIOF ((GPIO_Type *) GPIOF_BASE ) ¾GPIOG ((GPIO_Type *) GPIOG_BASE ) ¿GPIOH ((GPIOH_Type *) GPIOH_BASE ) ÀGPIO ((GPIO_COMMON_Type *) GPIO_BASE ) h ] ..\Core\Include\ FM33A0XXEV.h core_cm0plus.h system_FM33A0XXEV.h ¬
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..\Core\Include\FM33A0XXEV.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM ÓRESET SET PFlagStatus ¾ *(PITStatus ¾ *4DISABLE ENABLE PFunState õ +/´FAIL PASS PErrorStatus ,'¨Reset_IRQn qNMI_IRQn rHardFault_IRQn sSVC_IRQn {PendSV_IRQn ~SysTick_IRQn WWDT_IRQn SVD_IRQn RTC_IRQn FLASH_IRQn CMU_IRQn ADC_IRQn SPI0_IRQn SPI1_IRQn SPI2_IRQn UART0_IRQn UART1_IRQn
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UART2_IRQn UART3_IRQn UART4_IRQn UART5_IRQn U7816_IRQn LPUART0_IRQn I2Cx_IRQn RSV_IRQn CRYPTO_IRQn LPTIM_IRQn DMA_IRQn WKUPx_IRQn COMP_IRQn BTx_IRQn QSPI_IRQn ETx_IRQn BSTIM_IRQn SPI3_IRQn SPI4_IRQn GPIO_IRQn LPUART1_IRQn PIRQn_Type Gb*ö CR v# WKTR v# WKFR v# IER v# ISR v# tf PPMU_Type 9*´ RSV1 v# CR v# HDFR v# PDBG_Type ¨* X RDCR v# PFCR v# OPTBR #÷v RSV1 î# EPCR v# KEY v# IER v# ISR v# ¹v RSV2 0#$ ACLOCK1 v#H ACLOCK2 v#L ACLOCK3 v#P ACLOCK4 v#T f tPFLS_Type ž*
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$ PDRCR v# BORCR v# RSTCFGR v# SOFTRST v# RSR v# PRSTEN v# AHBRST v# APBRST1 v# APBRST2 v# PRMU_Type Ð*Ù
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SERV v# CFGR v# CNTR # PIWDT_Type 0Ü*´ CR v# CFGR v# CNTR # IER v# ISR v# PSCR # PWWDT_Type kë* 8 SYSCLKCR v# RCHFCR v# RCHFTR v# PLLLCR v# PLLHCR v# XTHFCR v# IER v# ISR v# PCLKCR1 v# PCLKCR2 v#$ PCLKCR3 v#( PCLKCR4 v#, OPCCR1 v#0 OPCCR2 v#4 PCMU_Type Æ*» CR v# PSCR v# PCDIF_Type *Õ0 PDRCR v# ç v RSV1 Þ# RCMFCR v# RCLPCR v# RCLPTR v# XTLFCR v# ADCCR v#$ LFDIER v#( LFDISR v#, PVRTC_Type Í*£ CFGR v# CR v# IER v# ISR v# VSR v# PSVD_Type g¬*§T CR v# IER v# ISR v# DIR v# DOR # KEY0 v# KEY1 v# KEY2 v# KEY3 v# KEY4 v#$ KEY5 v#( KEY6 v#, KEY7 v#0 IVR0 v#4 IVR1 v#8 IVR2 v#< IVR3 v#@ H0 v#D H1 v#H H2 v#L H3 v#P PAES_Type ´Ê* CSR v# MLR v# MPR v# M0CFG v# M1CFG v# M2CFG v# M3CFG v# WORD v# PPAE_Type ¸Û*Ê CSR v# DTR v# PHASH_Type / æ*À CR v# DOR #þv RSV1 u # SR v# CRC_CR v# CRC_DIR v# CRC_SR v# PRNG_Type \ ö* CR1 v# CR2 v# ICR v# ISR v# PCR v# PCOMP_Type Ñ *$ CFGR v# CR v# IER v# ISR v# SR v# BRG v# BUF v# TIMING v# TO v# PI2C_Type
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*¨ CR v# PUARTIR_Type
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* CSR v# IER v# ISR v# TODR v# RXBUF # TXBUF v# BGR v# PUART_Type ¼
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°*û CSR v# IER v# ISR v# BMR v# RXBUF v# TXBUF v# DMR v# PLPUART_Type % À*å CR1 v# CR2 v# CR3 v# IER v# ISR v# TXBUF v# RXBUF # PSPI_Type Ð*â$ CR v# FFR v# EGTR v# PSC v# BGR v# RXBUF # TXBUF v# IER v# ISR v# PU7816_Type ö â*0 CR v# CFG v# SR v# DATALEN v# CCR v# ADDR v# ABR v# DR v# SMSK v# SMAT v#$ PITV v#( TO v#, PQSPI_Type u ÷*õ ¸ GCR v# CH0CR v# CH0MAR v# CH1CR v# CH1MAR v# CH2CR v# CH2MAR v# CH3CR v# CH3MAR v# CH4CR v#$ CH4MAR v#( CH5CR v#, CH5MAR v#0 CH6CR v#4 CH6MAR v#8 CH7CR v#< CH7MAR v#@ CH8CR v#D CH8MAR v#H CH9CR v#L CH9MAR v#P CH10CR v#T CH10MAR v#X CH11CR v#\ CH11FAR v#` CH11RAR v#d ISR v#h v$ RSV1 #l CH0CSR v# CH0MASR v# CH1CSR v# CH1MASR v# CH2CSR v# CH2MASR v# CH3CSR v# CH3MASR v# CH4CSR v# CH4MASR v#¤ CH5CSR v#¨ CH5MASR v#¬ CH6CSR v#° CH6MASR v#´ PDMA_Type ª*× DR v# CR v# LFSR v# XOR v# ¾ v RSV1 µ# POLY v# PCRC_Type ¹*¾!D CR1 v# CR2 v# CFGR1 v# CFGR2 v# PRES v# LOADCR v# CNTL # CNTH # PRESET v# LOADL v#$ LOADH v#( CMPL v#, CMPH v#0 OUTCNT v#4 OCR v#8 IER v#< ISR v#@ PBT_Type èÓ*°" CR v# INSR v# PSCR1 v# PSCR2 v# IVR v# CMPR v# IER v# ISR v# PET_Type Îä*õ" CNT1 v# CNT2 v# CNT3 v# CNT4 v# PETCNT_Type @ï*$0 CR1 v# CR2 v# RSV1 v# IER v# ISR v# EGR v#Ø#v RSV2 Ï# CNTR v#$ PSCR v#( ARR v#, PBSTIM_Type *«%0 CFGR v# CNTR # CCSR v# ARR v# IER v# ISR v# CR v# RSV1 v# CCR1 v# CCR2 v#$ CCR3 v#( CCR4 v#, PLPTIM_Type *ø' WER v# IER v# ISR v# BCDSEC v# BCDMIN v# BCDHOUR v# BCDDATE v# BCDWEEK v# BCDMONTH v# BCDYEAR v#$ ALARM v#( TMSEL v#, ADJUST v#0 ADSIGN v#4 VCAL v#8 MSCNT v#< CALSTEP v#@ ADCNT #D SSR #H SSA v#L DTR v#Pá'v RSV1 Ø#T CR v#| PRTC_Type ¾¶*¿*` CR v# TEST v# FCR v# FLKT v# RSV1 v# IER v# ISR v#å(v RSV2 \# DATA0 v#$ DATA1 v#( DATA2 v#, DATA3 v#0 DATA4 v#4 DATA5 v#8 DATA6 v#< DATA7 v#@ DATA8 v#D DATA9 v#Hü)v RSV3 ó#L COMEN v#P SEGEN0 v#T SEGEN1 v#X BSTCR v#\ PLCD_Type Õ*+ CR v# TRIM v# DR # ISR v# CFGR v# PADC_Type Pã*×+ DR # OS v# USDR # CR v# ISR v# PCIC_Type ñ*ë,, INEN v# PUEN v# ODEN v# FCR v# DO v# DSET v# DRST v# DIN # DFS v# RSV v#$ ANEN v#( PGPIO_Type è
*º- INEN v# PUEN v# FCR v# DO v# DIN v# PGPIOH_Type }*/Ä EXTISEL0 v# EXTISEL1 v# EXTIEDS0 v# EXTIEDS1 v# EXTIDF v# EXTIISR v# EXTIDI #Æ.v RSV1 =# FOUTSEL v#@ IOMCR v#D÷.v= RSV2 n#H PINWKEN v#À PGPIO_COMMON_Type ͦ ( ) * + (SYSTEM_FM33A0XXEV_H 234O__SYSTEM_CLOCK (8000000) PDELAY_US (__SYSTEM_CLOCK/1000000) QDELAY_MS (__SYSTEM_CLOCK/1000) TDo_DelayStart() { uint32_t LastTick = SysTick->VAL; do { WWhile_DelayMsEnd(Count) }while(((LastTick - SysTick->VAL)&0xFFFFFF)<DELAY_MS*Count); } ZWhile_DelayUsEnd(Count) }while(((LastTick - SysTick->VAL)&0xFFFFFF)<DELAY_US*Count); }
..\Core\Include\ D:\Keil5\ARM\ARMCC\Bin\..\include\ system_FM33A0XXEV.h stdint.h stdio.h FM33A0XXEV.h Ü
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..\Core\Include\system_FM33A0XXEV.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM qSystemCoreClock f " à Å SystemCoreClock - . / __FM33A0XXEV_AES_H )AES_CR_KEYLEN_Pos 13 /AES_CR_KEYLEN_Msk (0x3U << AES_CR_KEYLEN_Pos) 0AES_CR_KEYLEN_128BIT (0x0U << AES_CR_KEYLEN_Pos) 1AES_CR_KEYLEN_192BIT (0x1U << AES_CR_KEYLEN_Pos) 2AES_CR_KEYLEN_256BIT (0x2U << AES_CR_KEYLEN_Pos) 3AES_CR_KEYLEN_ (0x3U << AES_CR_KEYLEN_Pos) 5AES_CR_DMAOEN_Pos 12 :AES_CR_DMAOEN_Msk (0x1U << AES_CR_DMAOEN_Pos) =AES_CR_DMAIEN_Pos 11 BAES_CR_DMAIEN_Msk (0x1U << AES_CR_DMAIEN_Pos) EAES_CR_CHMOD_Pos 5 KAES_CR_CHMOD_Msk (0x3U << AES_CR_CHMOD_Pos) LAES_CR_CHMOD_ECB (0x0U << AES_CR_CHMOD_Pos) MAES_CR_CHMOD_CBC (0x1U << AES_CR_CHMOD_Pos) NAES_CR_CHMOD_CTR (0x2U << AES_CR_CHMOD_Pos) OAES_CR_CHMOD_MULTH (0x3U << AES_CR_CHMOD_Pos) QAES_CR_MODE_Pos 3 XAES_CR_MODE_Msk (0x3U << AES_CR_MODE_Pos) YAES_CR_MODE_ENCRYPT (0x0U << AES_CR_MODE_Pos) ZAES_CR_MODE_KEYEXP (0x1U << AES_CR_MODE_Pos) [AES_CR_MODE_DECRYPT (0x2U << AES_CR_MODE_Pos) \AES_CR_MODE_KEYEXPDECRYPT (0x3U << AES_CR_MODE_Pos) ^AES_CR_DATATYP_Pos 1 dAES_CR_DATATYP_Msk (0x3U << AES_CR_DATATYP_Pos) eAES_CR_DATATYP_32BITNOEX (0x0U << AES_CR_DATATYP_Pos) fAES_CR_DATATYP_16BITEX (0x1U << AES_CR_DATATYP_Pos) gAES_CR_DATATYP_8BITEX (0x2U << AES_CR_DATATYP_Pos) hAES_CR_DATATYP_1BITEX (0x3U << AES_CR_DATATYP_Pos) jAES_CR_EN_Pos 0 oAES_CR_EN_Msk (0x1U << AES_CR_EN_Pos) sAES_IER_WRERR_IE_Pos 2 tAES_IER_WRERR_IE_Msk (0x1U << AES_IER_WRERR_IE_Pos) vAES_IER_RDERR_IE_Pos 1 wAES_IER_RDERR_IE_Msk (0x1U << AES_IER_RDERR_IE_Pos) yAES_IER_CCF_IE_Pos 0 zAES_IER_CCF_IE_Msk (0x1U << AES_IER_CCF_IE_Pos) |AES_DIR_DIN_Pos 0 AES_DIR_DIN_Msk (0xffffffffU << AES_DIR_DIN_Pos) AES_DOR_DOUT_Pos 0 AES_DOR_DOUT_Msk (0xffffffffU << AES_DOR_DOUT_Pos) AES_KEY0_KEYx_Pos 0 AES_KEY0_KEYx_Msk (0xffffffffU << AES_KEY0_KEYx_Pos) AES_KEY1_KEYx_Pos 0 AES_KEY1_KEYx_Msk (0xffffffffU << AES_KEY1_KEYx_Pos) AES_KEY2_KEYx_Pos 0 AES_KEY2_KEYx_Msk (0xffffffffU << AES_KEY2_KEYx_Pos) AES_KEY3_KEYx_Pos 0 AES_KEY3_KEYx_Msk (0xffffffffU << AES_KEY3_KEYx_Pos) AES_KEY4_KEYx_Pos 0 AES_KEY4_KEYx_Msk (0xffffffffU << AES_KEY4_KEYx_Pos) AES_KEY5_KEYx_Pos 0 AES_KEY5_KEYx_Msk (0xffffffffU << AES_KEY5_KEYx_Pos) ¢AES_KEY6_KEYx_Pos 0 ¤AES_KEY6_KEYx_Msk (0xffffffffU << AES_KEY6_KEYx_Pos) ¦AES_KEY7_KEYx_Pos 0 ¨AES_KEY7_KEYx_Msk (0xffffffffU << AES_KEY7_KEYx_Pos) ªAES_IVR0_IVRx_Pos 0 ¬AES_IVR0_IVRx_Msk (0xffffffffU << AES_IVR0_IVRx_Pos) ®AES_IVR1_IVRx_Pos 0 °AES_IVR1_IVRx_Msk (0xffffffffU << AES_IVR1_IVRx_Pos) ²AES_IVR2_IVRx_Pos 0 ´AES_IVR2_IVRx_Msk (0xffffffffU << AES_IVR2_IVRx_Pos) ¶AES_IVR3_IVRx_Pos 0 ¸AES_IVR3_IVRx_Msk (0xffffffffU << AES_IVR3_IVRx_Pos) ºAES_H0_Hx_Pos 0 ¼AES_H0_Hx_Msk (0xffffffffU << AES_H0_Hx_Pos) ¾AES_H1_Hx_Pos 0 ÀAES_H1_Hx_Msk (0xffffffffU << AES_H1_Hx_Pos) ÂAES_H2_Hx_Pos 0 ÄAES_H2_Hx_Msk (0xffffffffU << AES_H2_Hx_Pos) ÆAES_H3_Hx_Pos 0 ÈAES_H3_Hx_Msk (0xffffffffU << AES_H3_Hx_Pos) ÊAES_ISR_WRERR_Pos 2 ËAES_ISR_WRERR_Msk (0x1U << AES_ISR_WRERR_Pos) ÍAES_ISR_RDERR_Pos 1 ÎAES_ISR_RDERR_Msk (0x1U << AES_ISR_RDERR_Pos) ÐAES_ISR_CCF_Pos 0 ÓAES_ISR_CCF_Msk (0x1U << AES_ISR_CCF_Pos) ` T ..\Drivers\ ..\Core\Include\ fm33a0xxev_aes.h FM33A0XXEV.h t
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..\Drivers\fm33a0xxev_aes.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM *Þ KEYLEN f # CHMOD f # MODE f # DATATYP f # DMAOEN # DMAIEN # WERRIE # RERRIE # CCFIE # AESEN # PAES_InitTypeDef ½ ' 1 2 3 __FM33A0XXEV_ADC_H ADC_CR_ADC_IE_Pos 7 ADC_CR_ADC_IE_Msk (0x1U << ADC_CR_ADC_IE_Pos) ADC_CR_ACC_IE_Pos 6 ADC_CR_ACC_IE_Msk (0x1U << ADC_CR_ACC_IE_Pos) ADC_CR_HPEN_Pos 3 "ADC_CR_HPEN_Msk (0x1U << ADC_CR_HPEN_Pos) #ADC_CR_HPEN_1MHZ (0x0U << ADC_CR_HPEN_Pos) $ADC_CR_HPEN_2MHZ (0x1U << ADC_CR_HPEN_Pos) &ADC_CR_MODE_Pos 2 )ADC_CR_MODE_Msk (0x1U << ADC_CR_MODE_Pos) *ADC_CR_MODE_INNER (0x0U << ADC_CR_MODE_Pos) +ADC_CR_MODE_EXTERNAL (0x1U << ADC_CR_MODE_Pos) -ADC_CR_RSTCTRL_EN_Pos 1 0ADC_CR_RSTCTRL_EN_Msk (0x1U << ADC_CR_RSTCTRL_EN_Pos) 4ADC_CR_EN_Pos 0 9ADC_CR_EN_Msk (0x1U << ADC_CR_EN_Pos) >ADC_TRIM_ADC_TRIM_Pos 0 AADC_TRIM_ADC_TRIM_Msk (0x7ffU << ADC_TRIM_ADC_TRIM_Pos) CADC_DR_ADC_DATA_Pos 0 FADC_DR_ADC_DATA_Msk (0xffffU << ADC_DR_ADC_DATA_Pos) HADC_ISR_INIT_RDY_Pos 9 MADC_ISR_INIT_RDY_Msk (0x1U << ADC_ISR_INIT_RDY_Pos) OADC_ISR_ACC_IF_Pos 8 PADC_ISR_ACC_IF_Msk (0x1U << ADC_ISR_ACC_IF_Pos) RADC_ISR_ADC_DONE_Pos 1 TADC_ISR_ADC_DONE_Msk (0x1U << ADC_ISR_ADC_DONE_Pos) VADC_ISR_ADC_IF_Pos 0 WADC_ISR_ADC_IF_Msk (0x1U << ADC_ISR_ADC_IF_Pos) YADC_CFGR_ACC_PERIOD_Pos 16 `ADC_CFGR_ACC_PERIOD_Msk (0x7U << ADC_CFGR_ACC_PERIOD_Pos) aADC_CFGR_ACC_PERIOD_10BITS (0x0U << ADC_CFGR_ACC_PERIOD_Pos) bADC_CFGR_ACC_PERIOD_11BITS (0x1U << ADC_CFGR_ACC_PERIOD_Pos) cADC_CFGR_ACC_PERIOD_12BITS (0x2U << ADC_CFGR_ACC_PERIOD_Pos) dADC_CFGR_ACC_PERIOD_13BITS (0x3U << ADC_CFGR_ACC_PERIOD_Pos) eADC_CFGR_ACC_PERIOD_14BITS (0x4U << ADC_CFGR_ACC_PERIOD_Pos) gADC_CFGR_RST_CTRL_DELAY_Pos 8 lADC_CFGR_RST_CTRL_DELAY_Msk (0xffU << ADC_CFGR_RST_CTRL_DELAY_Pos) nADC_CFGR_BUFEN_Pos 5 oADC_CFGR_BUFEN_Msk (0x1U << ADC_CFGR_BUFEN_Pos) qADC_CFGR_BUFSEL_Pos 0 ADC_CFGR_BUFSEL_Msk (0xfU << ADC_CFGR_BUFSEL_Pos) ADC_CFGR_BUFSEL_ADC_IN1 (0x1U << ADC_CFGR_BUFSEL_Pos) ADC_CFGR_BUFSEL_ADC_IN2 (0x2U << ADC_CFGR_BUFSEL_Pos)
ADC_CFGR_BUFSEL_ADC_IN3 (0x3U << ADC_CFGR_BUFSEL_Pos) ADC_CFGR_BUFSEL_ADC_IN4 (0x4U << ADC_CFGR_BUFSEL_Pos) ADC_CFGR_BUFSEL_ADC_IN5 (0x5U << ADC_CFGR_BUFSEL_Pos) ADC_CFGR_BUFSEL_ADC_IN6 (0x6U << ADC_CFGR_BUFSEL_Pos) ADC_CFGR_BUFSEL_ADC_IN7 (0x7U << ADC_CFGR_BUFSEL_Pos) ADC_CFGR_BUFSEL_ADC_IN8 (0x8U << ADC_CFGR_BUFSEL_Pos) ADC_CFGR_BUFSEL_ADC_IN9 (0x9U << ADC_CFGR_BUFSEL_Pos) ADC_CFGR_BUFSEL_ADC_IN10 (0xaU << ADC_CFGR_BUFSEL_Pos) ADC_CFGR_BUFSEL_ADC_IN11 (0xbU << ADC_CFGR_BUFSEL_Pos) ADC_CFGR_BUFSEL_ADC_IN12 (0xcU << ADC_CFGR_BUFSEL_Pos) ADC_CFGR_BUFSEL_VBAT (0xeU << ADC_CFGR_BUFSEL_Pos) ADC_CFGR_BUFSEL_TS (0xfU << ADC_CFGR_BUFSEL_Pos) CIC_DR_ADC_CIC_DATA_Pos 0 CIC_DR_ADC_CIC_DATA_Msk (0xffffffU << CIC_DR_ADC_CIC_DATA_Pos) CIC_OS_ADC_CIC_OS_Pos 0 CIC_OS_ADC_CIC_OS_Msk (0xffffffU << CIC_OS_ADC_CIC_OS_Pos) CIC_USDR_ADC_CIC_USDR_Pos 0 CIC_USDR_ADC_CIC_USDR_Msk (0xffffffU << CIC_USDR_ADC_CIC_USDR_Pos) CIC_CR_CIC_EN_Pos 31 CIC_CR_CIC_EN_Msk (0x1U << CIC_CR_CIC_EN_Pos) ¢CIC_CR_NS_DISC_Pos 8 ¥CIC_CR_NS_DISC_Msk (0xffU << CIC_CR_NS_DISC_Pos) §CIC_CR_OVR_IE_Pos 7 ªCIC_CR_OVR_IE_Msk (0x1U << CIC_CR_OVR_IE_Pos) ®CIC_CR_CIC_IE_Pos 6 ±CIC_CR_CIC_IE_Msk (0x1U << CIC_CR_CIC_IE_Pos) µCIC_CR_TRUNC_Pos 3 ·CIC_CR_TRUNC_Msk (0x7U << CIC_CR_TRUNC_Pos) ¹CIC_CR_OSR_Pos 0 ÂCIC_CR_OSR_Msk (0x7U << CIC_CR_OSR_Pos) ÃCIC_CR_OSR_X8 (0x0U << CIC_CR_OSR_Pos) ÄCIC_CR_OSR_X16 (0x1U << CIC_CR_OSR_Pos) ÅCIC_CR_OSR_X32 (0x2U << CIC_CR_OSR_Pos) ÆCIC_CR_OSR_X64 (0x3U << CIC_CR_OSR_Pos) ÇCIC_CR_OSR_X128 (0x4U << CIC_CR_OSR_Pos) ÈCIC_CR_OSR_X256 (0x5U << CIC_CR_OSR_Pos) ÉCIC_CR_OSR_X512 (0x6U << CIC_CR_OSR_Pos) ÊCIC_CR_OSR_X1024 (0x7U << CIC_CR_OSR_Pos) ÌCIC_ISR_CIC_OVR_Pos 1 ÍCIC_ISR_CIC_OVR_Msk (0x1U << CIC_ISR_CIC_OVR_Pos) ÏCIC_ISR_CIC_IF_Pos 0 ÐCIC_ISR_CIC_IF_Msk (0x1U << CIC_ISR_CIC_IF_Pos) ` T ..\Drivers\ ..\Core\Include\ fm33a0xxev_adc.h FM33A0XXEV.h ¼
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..\Drivers\fm33a0xxev_adc.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM 5 6 7 __FM33A0XXEV_BSTIM_H BSTIM_CR1_ARPE_Pos 7 BSTIM_CR1_ARPE_Msk (0x1U << BSTIM_CR1_ARPE_Pos) BSTIM_CR1_OPM_Pos 3 #BSTIM_CR1_OPM_Msk (0x1U << BSTIM_CR1_OPM_Pos) $BSTIM_CR1_OPM_CONTINUE (0x0U << BSTIM_CR1_OPM_Pos) %BSTIM_CR1_OPM_STOP (0x1U << BSTIM_CR1_OPM_Pos) 'BSTIM_CR1_URS_Pos 2 -BSTIM_CR1_URS_Msk (0x1U << BSTIM_CR1_URS_Pos) .BSTIM_CR1_URS_ALL (0x0U << BSTIM_CR1_URS_Pos) /BSTIM_CR1_URS_COUNT (0x1U << BSTIM_CR1_URS_Pos) 1BSTIM_CR1_UDIS_Pos 1 7BSTIM_CR1_UDIS_Msk (0x1U << BSTIM_CR1_UDIS_Pos) ;BSTIM_CR1_CEN_Pos 0 ?BSTIM_CR1_CEN_Msk (0x1U << BSTIM_CR1_CEN_Pos) DBSTIM_CR2_MMS_Pos 4 KBSTIM_CR2_MMS_Msk (0x7U << BSTIM_CR2_MMS_Pos) MBSTIM_IER_UIE_Pos 0 PBSTIM_IER_UIE_Msk (0x1U << BSTIM_IER_UIE_Pos) TBSTIM_ISR_UIF_Pos 0 YBSTIM_ISR_UIF_Msk (0x1U << BSTIM_ISR_UIF_Pos) [BSTIM_EGR_UG_Pos 0 ]BSTIM_EGR_UG_Msk (0x1U << BSTIM_EGR_UG_Pos) _BSTIM_CNTR_CNT_Pos 0 `BSTIM_CNTR_CNT_Msk (0xffffffffU << BSTIM_CNTR_CNT_Pos) bBSTIM_PSCR_PSC_Pos 0 eBSTIM_PSCR_PSC_Msk (0xffffffffU << BSTIM_PSCR_PSC_Pos) gBSTIM_ARR_ARR_Pos 0 iBSTIM_ARR_ARR_Msk (0xffffffffU << BSTIM_ARR_ARR_Pos) ` V ..\Drivers\ ..\Core\Include\ fm33a0xxev_bstim.h FM33A0XXEV.h À
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..\Drivers\fm33a0xxev_bstim.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM 9 : ; __FM33A0XXEV_COMP_H COMP_CR1_DFLEN_Pos 19 COMP_CR1_DFLEN_Msk (0x1fU << COMP_CR1_DFLEN_Pos) COMP_CR1_DFLEN_X3 (0x2U << COMP_CR1_DFLEN_Pos) COMP_CR1_DFLEN_X32 (0x1fU << COMP_CR1_DFLEN_Pos) !COMP_CR1_WINMODE_Pos 18 $COMP_CR1_WINMODE_Msk (0x1U << COMP_CR1_WINMODE_Pos) (COMP_CR1_POLAR_Pos 17 +COMP_CR1_POLAR_Msk (0x1U << COMP_CR1_POLAR_Pos) ,COMP_CR1_POLAR_POS (0x0U << COMP_CR1_POLAR_Pos) -COMP_CR1_POLAR_NEG (0x1U << COMP_CR1_POLAR_Pos) /COMP_CR1_DFEN_Pos 16 2COMP_CR1_DFEN_Msk (0x1U << COMP_CR1_DFEN_Pos) 6COMP_CR1_CMP1OR_Pos 9 7COMP_CR1_CMP1OR_Msk (0x1U << COMP_CR1_CMP1OR_Pos) 9COMP_CR1_CMP1OF_Pos 8 :COMP_CR1_CMP1OF_Msk (0x1U << COMP_CR1_CMP1OF_Pos) <COMP_CR1_V1NSEL_Pos 4 ECOMP_CR1_V1NSEL_Msk (0x7U << COMP_CR1_V1NSEL_Pos) FCOMP_CR1_V1NSEL_COMP1_INN1 (0x0U << COMP_CR1_V1NSEL_Pos) GCOMP_CR1_V1NSEL_COMP1_INN2 (0x1U << COMP_CR1_V1NSEL_Pos) HCOMP_CR1_V1NSEL_VREF (0x2U << COMP_CR1_V1NSEL_Pos) ICOMP_CR1_V1NSEL_3_4_VREF (0x3U << COMP_CR1_V1NSEL_Pos) JCOMP_CR1_V1NSEL_1_2_VREF (0x4U << COMP_CR1_V1NSEL_Pos) KCOMP_CR1_V1NSEL_1_4_VREF (0x5U << COMP_CR1_V1NSEL_Pos) LCOMP_CR1_V1NSEL_1_8_VREF (0x6U << COMP_CR1_V1NSEL_Pos) NCOMP_CR1_V1PSEL_Pos 1 SCOMP_CR1_V1PSEL_Msk (0x3U << COMP_CR1_V1PSEL_Pos) TCOMP_CR1_V1PSEL_COMP1_INP1 (0x0U << COMP_CR1_V1PSEL_Pos) UCOMP_CR1_V1PSEL_COMP1_INP2 (0x1U << COMP_CR1_V1PSEL_Pos) VCOMP_CR1_V1PSEL_COMP1_INP3 (0x2U << COMP_CR1_V1PSEL_Pos) WCOMP_CR1_V1PSEL_COMP1_INP4 (0x3U << COMP_CR1_V1PSEL_Pos) YCOMP_CR1_CMP1EN_Pos 0 \COMP_CR1_CMP1EN_Msk (0x1U << COMP_CR1_CMP1EN_Pos) `COMP_CR2_DFLEN_Pos 19 dCOMP_CR2_DFLEN_Msk (0x1fU << COMP_CR2_DFLEN_Pos) eCOMP_CR2_DFLEN_X3 (0x2U << COMP_CR2_DFLEN_Pos) fCOMP_CR2_DFLEN_X32 (0x1fU << COMP_CR2_DFLEN_Pos) hCOMP_CR2_WINMODE_Pos 18 kCOMP_CR2_WINMODE_Msk (0x1U << COMP_CR2_WINMODE_Pos) oCOMP_CR2_POLAR_Pos 17 rCOMP_CR2_POLAR_Msk (0x1U << COMP_CR2_POLAR_Pos) sCOMP_CR2_POLAR_POS (0x0U << COMP_CR2_POLAR_Pos) tCOMP_CR2_POLAR_NEG (0x1U << COMP_CR2_POLAR_Pos) vCOMP_CR2_DFEN_Pos 16 yCOMP_CR2_DFEN_Msk (0x1U << COMP_CR2_DFEN_Pos) }COMP_CR2_CMP2OR_Pos 9 ~COMP_CR2_CMP2OR_Msk (0x1U << COMP_CR2_CMP2OR_Pos) COMP_CR2_CMP2OF_Pos 8 COMP_CR2_CMP2OF_Msk (0x1U << COMP_CR2_CMP2OF_Pos) COMP_CR2_V2NSEL_Pos 4 COMP_CR2_V2NSEL_Msk (0x7U << COMP_CR2_V2NSEL_Pos) COMP_CR2_V2NSEL_COMP2_INN1 (0x0U << COMP_CR2_V2NSEL_Pos) COMP_CR2_V2NSEL_COMP2_INN2 (0x1U << COMP_CR2_V2NSEL_Pos) COMP_CR2_V2NSEL_VREF (0x2U << COMP_CR2_V2NSEL_Pos) COMP_CR2_V2NSEL_3_4_VREF (0x3U << COMP_CR2_V2NSEL_Pos) COMP_CR2_V2NSEL_1_2_VREF (0x4U << COMP_CR2_V2NSEL_Pos) COMP_CR2_V2NSEL_1_4_VREF (0x5U << COMP_CR2_V2NSEL_Pos) COMP_CR2_V2NSEL_1_8_VREF (0x6U << COMP_CR2_V2NSEL_Pos) COMP_CR2_V2NSEL_REFIN (0x7U << COMP_CR2_V2NSEL_Pos) COMP_CR2_V2PSEL_Pos 1 COMP_CR2_V2PSEL_Msk (0x7U << COMP_CR2_V2PSEL_Pos) COMP_CR2_V2PSEL_COMP2_INP1 (0x0U << COMP_CR2_V2PSEL_Pos) COMP_CR2_V2PSEL_COMP2_INP2 (0x1U << COMP_CR2_V2PSEL_Pos) ¡COMP_CR2_V2PSEL_COMP1_INP1 (0x2U << COMP_CR2_V2PSEL_Pos) ¢COMP_CR2_V2PSEL_COMP1_INP2 (0x3U << COMP_CR2_V2PSEL_Pos) £COMP_CR2_V2PSEL_AVREF (0x4U << COMP_CR2_V2PSEL_Pos) ¤COMP_CR2_V2PSEL_VDD15 (0x5U << COMP_CR2_V2PSEL_Pos) ¦COMP_CR2_CMP2EN_Pos 0 ©COMP_CR2_CMP2EN_Msk (0x1U << COMP_CR2_CMP2EN_Pos) COMP_ICR_OOW_IE_Pos 9 ®COMP_ICR_OOW_IE_Msk (0x1U << COMP_ICR_OOW_IE_Pos) °COMP_ICR_WIN_IE_Pos 8 ±COMP_ICR_WIN_IE_Msk (0x1U << COMP_ICR_WIN_IE_Pos) ³COMP_ICR_BUFBYP_Pos 7 ¶COMP_ICR_BUFBYP_Msk (0x1U << COMP_ICR_BUFBYP_Pos) ¸COMP_ICR_BUF_OFF_Pos 6 »COMP_ICR_BUF_OFF_Msk (0x1U << COMP_ICR_BUF_OFF_Pos) ½COMP_ICR_CMP2SEL_Pos 4 ÁCOMP_ICR_CMP2SEL_Msk (0x3U << COMP_ICR_CMP2SEL_Pos) ÂCOMP_ICR_CMP2SEL_BOTH (0x0U << COMP_ICR_CMP2SEL_Pos) ÃCOMP_ICR_CMP2SEL_RISING (0x1U << COMP_ICR_CMP2SEL_Pos) ÄCOMP_ICR_CMP2SEL_FALLING (0x2U << COMP_ICR_CMP2SEL_Pos) ÆCOMP_ICR_CMP1SEL_Pos 2 ÊCOMP_ICR_CMP1SEL_Msk (0x3U << COMP_ICR_CMP1SEL_Pos) ËCOMP_ICR_CMP1SEL_BOTH (0x0U << COMP_ICR_CMP1SEL_Pos) ÌCOMP_ICR_CMP1SEL_RISING (0x1U << COMP_ICR_CMP1SEL_Pos) ÍCOMP_ICR_CMP1SEL_FALLING (0x2U << COMP_ICR_CMP1SEL_Pos) ÏCOMP_ICR_CMP2IE_Pos 1 ÐCOMP_ICR_CMP2IE_Msk (0x1U << COMP_ICR_CMP2IE_Pos) ÒCOMP_ICR_CMP1IE_Pos 0 ÓCOMP_ICR_CMP1IE_Msk (0x1U << COMP_ICR_CMP1IE_Pos) ÕCOMP_ISR_OOW_IF_Pos 3 ÖCOMP_ISR_OOW_IF_Msk (0x1U << COMP_ISR_OOW_IF_Pos) ØCOMP_ISR_WIN_IF_Pos 2 ÙCOMP_ISR_WIN_IF_Msk (0x1U << COMP_ISR_WIN_IF_Pos) ÛCOMP_ISR_CMP2IF_Pos 1 ÜCOMP_ISR_CMP2IF_Msk (0x1U << COMP_ISR_CMP2IF_Pos) ÞCOMP_ISR_CMP1IF_Pos 0 ßCOMP_ISR_CMP1IF_Msk (0x1U << COMP_ISR_CMP1IF_Pos) áCOMP_PCR_HSCMPBUF_EN_Pos 2 äCOMP_PCR_HSCMPBUF_EN_Msk (0x1U << COMP_PCR_HSCMPBUF_EN_Pos) åCOMP_PCR_HSCMPBUF_EN_SLOW (0x0U << COMP_PCR_HSCMPBUF_EN_Pos) æCOMP_PCR_HSCMPBUF_EN_FAST (0x1U << COMP_PCR_HSCMPBUF_EN_Pos) èCOMP_PCR_HSCMP2_EN_Pos 1 ëCOMP_PCR_HSCMP2_EN_Msk (0x1U << COMP_PCR_HSCMP2_EN_Pos) ìCOMP_PCR_HSCMP2_EN_SLOW (0x0U << COMP_PCR_HSCMP2_EN_Pos) íCOMP_PCR_HSCMP2_EN_FAST (0x1U << COMP_PCR_HSCMP2_EN_Pos) ïCOMP_PCR_HSCMP1_EN_Pos 0 òCOMP_PCR_HSCMP1_EN_Msk (0x1U << COMP_PCR_HSCMP1_EN_Pos) óCOMP_PCR_HSCMP1_EN_SLOW (0x0U << COMP_PCR_HSCMP1_EN_Pos) ôCOMP_PCR_HSCMP1_EN_FAST (0x1U << COMP_PCR_HSCMP1_EN_Pos) ` U ..\Drivers\ ..\Core\Include\ fm33a0xxev_comp.h FM33A0XXEV.h ¼
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..\Drivers\fm33a0xxev_comp.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM = > ? __FM33A0XXEV_RMU_H RMU_PDRCR_PDRCFG_Pos 1 RMU_PDRCR_PDRCFG_Msk (0x3U << RMU_PDRCR_PDRCFG_Pos) RMU_PDRCR_PDRCFG_1P5V (0x0U << RMU_PDRCR_PDRCFG_Pos) RMU_PDRCR_PDRCFG_1P25V (0x1U << RMU_PDRCR_PDRCFG_Pos) RMU_PDRCR_PDRCFG_1P35V (0x2U << RMU_PDRCR_PDRCFG_Pos) RMU_PDRCR_PDRCFG_1P4V (0x3U << RMU_PDRCR_PDRCFG_Pos) RMU_PDRCR_PDREN_Pos 0 !RMU_PDRCR_PDREN_Msk (0x1U << RMU_PDRCR_PDREN_Pos) %RMU_BORCR_BOR_PDRCFG_Pos 1 &RMU_BORCR_BOR_PDRCFG_Msk (0x3U << RMU_BORCR_BOR_PDRCFG_Pos) 'RMU_BORCR_BOR_PDRCFG_1P7V (0x0U << RMU_BORCR_BOR_PDRCFG_Pos) (RMU_BORCR_BOR_PDRCFG_1P6V (0x1U << RMU_BORCR_BOR_PDRCFG_Pos) )RMU_BORCR_BOR_PDRCFG_1P65V (0x2U << RMU_BORCR_BOR_PDRCFG_Pos) *RMU_BORCR_BOR_PDRCFG_1P75V (0x3U << RMU_BORCR_BOR_PDRCFG_Pos) ,RMU_BORCR_OFF_BOR_Pos 0 -RMU_BORCR_OFF_BOR_Msk (0x1U << RMU_BORCR_OFF_BOR_Pos) 1RMU_RSTCFGR_LKUPRST_EN_Pos 1 2RMU_RSTCFGR_LKUPRST_EN_Msk (0x1U << RMU_RSTCFGR_LKUPRST_EN_Pos) 6RMU_SOFTRST_SOFTRST_Pos 0 7RMU_SOFTRST_SOFTRST_Msk (0xffffffffU << RMU_SOFTRST_SOFTRST_Pos) 9RMU_RSR_NRSTN_FLAG_Pos 11 :RMU_RSR_NRSTN_FLAG_Msk (0x1U << RMU_RSR_NRSTN_FLAG_Pos) <RMU_RSR_TESTN_FLAG_Pos 10 =RMU_RSR_TESTN_FLAG_Msk (0x1U << RMU_RSR_TESTN_FLAG_Pos) ?RMU_RSR_PORN_FLAG_Pos 9 @RMU_RSR_PORN_FLAG_Msk (0x1U << RMU_RSR_PORN_FLAG_Pos) BRMU_RSR_PDRN_FLAG_Pos 8 CRMU_RSR_PDRN_FLAG_Msk (0x1U << RMU_RSR_PDRN_FLAG_Pos) ERMU_RSR_SOFTN_FLAG_Pos 5 FRMU_RSR_SOFTN_FLAG_Msk (0x1U << RMU_RSR_SOFTN_FLAG_Pos) HRMU_RSR_IWDTN_FLAG_Pos 4 IRMU_RSR_IWDTN_FLAG_Msk (0x1U << RMU_RSR_IWDTN_FLAG_Pos) KRMU_RSR_WWDTN_FLAG_Pos 2 LRMU_RSR_WWDTN_FLAG_Msk (0x1U << RMU_RSR_WWDTN_FLAG_Pos) NRMU_RSR_LKUPN_FLAG_Pos 1 ORMU_RSR_LKUPN_FLAG_Msk (0x1U << RMU_RSR_LKUPN_FLAG_Pos) QRMU_RSR_NVICN_FLAG_Pos 0 RRMU_RSR_NVICN_FLAG_Msk (0x1U << RMU_RSR_NVICN_FLAG_Pos) TRMU_PRSTEN_PERHRSTEN_Pos 0 URMU_PRSTEN_PERHRSTEN_Msk (0xffffffffU << RMU_PRSTEN_PERHRSTEN_Pos) WRMU_AHBRST_HASHRST_Pos 2 XRMU_AHBRST_HASHRST_Msk (0x1U << RMU_AHBRST_HASHRST_Pos) \RMU_AHBRST_PAERST_Pos 1 ]RMU_AHBRST_PAERST_Msk (0x1U << RMU_AHBRST_PAERST_Pos) aRMU_AHBRST_DMARST_Pos 0 bRMU_AHBRST_DMARST_Msk (0x1U << RMU_AHBRST_DMARST_Pos) fRMU_APBRST1_UART5RST_Pos 31 gRMU_APBRST1_UART5RST_Msk (0x1U << RMU_APBRST1_UART5RST_Pos) kRMU_APBRST1_UART4RST_Pos 30 lRMU_APBRST1_UART4RST_Msk (0x1U << RMU_APBRST1_UART4RST_Pos) pRMU_APBRST1_UART3RST_Pos 29 qRMU_APBRST1_UART3RST_Msk (0x1U << RMU_APBRST1_UART3RST_Pos) uRMU_APBRST1_UART2RST_Pos 28 vRMU_APBRST1_UART2RST_Msk (0x1U << RMU_APBRST1_UART2RST_Pos) zRMU_APBRST1_TIMARST_Pos 23 {RMU_APBRST1_TIMARST_Msk (0x1U << RMU_APBRST1_TIMARST_Pos) RMU_APBRST1_LCDRST_Pos 16 RMU_APBRST1_LCDRST_Msk (0x1U << RMU_APBRST1_LCDRST_Pos) RMU_APBRST1_U7816RST_Pos 14
RMU_APBRST1_U7816RST_Msk (0x1U << RMU_APBRST1_U7816RST_Pos) RMU_APBRST1_SPI4RST_Pos 12 RMU_APBRST1_SPI4RST_Msk (0x1U << RMU_APBRST1_SPI4RST_Pos) RMU_APBRST1_SPI3RST_Pos 11 RMU_APBRST1_SPI3RST_Msk (0x1U << RMU_APBRST1_SPI3RST_Pos) RMU_APBRST1_SPI2RST_Pos 10 RMU_APBRST1_SPI2RST_Msk (0x1U << RMU_APBRST1_SPI2RST_Pos) RMU_APBRST1_LPUART0RST_Pos 6 RMU_APBRST1_LPUART0RST_Msk (0x1U << RMU_APBRST1_LPUART0RST_Pos) RMU_APBRST1_I2C1RST_Pos 3 RMU_APBRST1_I2C1RST_Msk (0x1U << RMU_APBRST1_I2C1RST_Pos) ¢RMU_APBRST1_LPTRST_Pos 0 £RMU_APBRST1_LPTRST_Msk (0x1U << RMU_APBRST1_LPTRST_Pos) §RMU_APBRST2_UART1RST_Pos 31 ¨RMU_APBRST2_UART1RST_Msk (0x1U << RMU_APBRST2_UART1RST_Pos) ¬RMU_APBRST2_UART0RST_Pos 30 RMU_APBRST2_UART0RST_Msk (0x1U << RMU_APBRST2_UART0RST_Pos) ±RMU_APBRST2_UARTIRRST_Pos 29 ²RMU_APBRST2_UARTIRRST_Msk (0x1U << RMU_APBRST2_UARTIRRST_Pos) ¶RMU_APBRST2_BSTRST_Pos 28 ·RMU_APBRST2_BSTRST_Msk (0x1U << RMU_APBRST2_BSTRST_Pos) »RMU_APBRST2_CICRST_Pos 24 ¼RMU_APBRST2_CICRST_Msk (0x1U << RMU_APBRST2_CICRST_Pos) ÀRMU_APBRST2_ADCRST_Pos 23 ÁRMU_APBRST2_ADCRST_Msk (0x1U << RMU_APBRST2_ADCRST_Pos) ÅRMU_APBRST2_AESRST_Pos 18 ÆRMU_APBRST2_AESRST_Msk (0x1U << RMU_APBRST2_AESRST_Pos) ÊRMU_APBRST2_CRCRST_Pos 17 ËRMU_APBRST2_CRCRST_Msk (0x1U << RMU_APBRST2_CRCRST_Pos) ÏRMU_APBRST2_RNGRST_Pos 16 ÐRMU_APBRST2_RNGRST_Msk (0x1U << RMU_APBRST2_RNGRST_Pos) ÔRMU_APBRST2_SPI1RST_Pos 9 ÕRMU_APBRST2_SPI1RST_Msk (0x1U << RMU_APBRST2_SPI1RST_Pos) ÙRMU_APBRST2_SPI0RST_Pos 8 ÚRMU_APBRST2_SPI0RST_Msk (0x1U << RMU_APBRST2_SPI0RST_Pos) ÞRMU_APBRST2_LPUART1RST_Pos 7 ßRMU_APBRST2_LPUART1RST_Msk (0x1U << RMU_APBRST2_LPUART1RST_Pos) ãRMU_APBRST2_I2C0RST_Pos 4 äRMU_APBRST2_I2C0RST_Msk (0x1U << RMU_APBRST2_I2C0RST_Pos) èRMU_APBRST2_SVDRST_Pos 1 éRMU_APBRST2_SVDRST_Msk (0x1U << RMU_APBRST2_SVDRST_Pos) íRMU_APBRST2_COMPRST_Pos 0 îRMU_APBRST2_COMPRST_Msk (0x1U << RMU_APBRST2_COMPRST_Pos) ` T ..\Drivers\ ..\Core\Include\ fm33a0xxev_rmu.h FM33A0XXEV.h ¼
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..\Drivers\fm33a0xxev_rmu.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM A B C __FM33A0XXEV_CRC_H &CRC_DR_DR_Pos 0 )CRC_DR_DR_Msk (0xffffffffU << CRC_DR_DR_Pos) +CRC_CR_OPWD_Pos 9 .CRC_CR_OPWD_Msk (0x1U << CRC_CR_OPWD_Pos) /CRC_CR_OPWD_BYTE (0x0U << CRC_CR_OPWD_Pos) 0CRC_CR_OPWD_WORD (0x1U << CRC_CR_OPWD_Pos) 2CRC_CR_PARA_Pos 8 5CRC_CR_PARA_Msk (0x1U << CRC_CR_PARA_Pos) 6CRC_CR_PARA_SERIAL (0x0U << CRC_CR_PARA_Pos) 7CRC_CR_PARA_PARALLEL (0x1U << CRC_CR_PARA_Pos) 9CRC_CR_RFLTIN_Pos 6 ACRC_CR_RFLTIN_Msk (0x3U << CRC_CR_RFLTIN_Pos) BCRC_CR_RFLTIN_NONE (0x0U << CRC_CR_RFLTIN_Pos) CCRC_CR_RFLTIN_BYTE (0x1U << CRC_CR_RFLTIN_Pos) DCRC_CR_RFLTIN_HALFWORD (0x2U << CRC_CR_RFLTIN_Pos) ECRC_CR_RFLTIN_WORD (0x3U << CRC_CR_RFLTIN_Pos) GCRC_CR_RFLTO_Pos 5 LCRC_CR_RFLTO_Msk (0x1U << CRC_CR_RFLTO_Pos) MCRC_CR_RFLTO_NON (0x0U << CRC_CR_RFLTO_Pos) NCRC_CR_RFLTO_BYTE (0x1U << CRC_CR_RFLTO_Pos) PCRC_CR_RES_Pos 4 SCRC_CR_RES_Msk (0x1U << CRC_CR_RES_Pos) UCRC_CR_BUSY_Pos 3 XCRC_CR_BUSY_Msk (0x1U << CRC_CR_BUSY_Pos) ZCRC_CR_XOR_Pos 2 ]CRC_CR_XOR_Msk (0x1U << CRC_CR_XOR_Pos) aCRC_CR_SEL_Pos 0 fCRC_CR_SEL_Msk (0x3U << CRC_CR_SEL_Pos) gCRC_CR_SEL_CRC32 (0x0U << CRC_CR_SEL_Pos) hCRC_CR_SEL_CRC16 (0x1U << CRC_CR_SEL_Pos) iCRC_CR_SEL_CRC8 (0x2U << CRC_CR_SEL_Pos) jCRC_CR_SEL_CRC7 (0x3U << CRC_CR_SEL_Pos) lCRC_LFSR_LFSR_Pos 0 nCRC_LFSR_LFSR_Msk (0xffffffffU << CRC_LFSR_LFSR_Pos) pCRC_XOR_XOR_Pos 0 rCRC_XOR_XOR_Msk (0xffffffffU << CRC_XOR_XOR_Pos) tCRC_POLY_POLY_Pos 0 uCRC_POLY_POLY_Msk (0xffffffffU << CRC_POLY_POLY_Pos) ` T ..\Drivers\ ..\Core\Include\ fm33a0xxev_crc.h FM33A0XXEV.h `
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..\Drivers\fm33a0xxev_crc.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM *Ê$ CRCSEL f # OPWD f # PARA f # RFLTIN f # RFLTO f # XOR # CRC_XOR f # CRCPOLY f # LFSR f # PCRC_InitTypeDef ½ $ E F G __FM33A0XXEV_LCD_H LCD_CR_SCSEL_Pos 20 "LCD_CR_SCSEL_Msk (0x7U << LCD_CR_SCSEL_Pos) #LCD_CR_SCSEL_LSCLK_COM (0x0U << LCD_CR_SCSEL_Pos) $LCD_CR_SCSEL_LSCLK_8 (0x1U << LCD_CR_SCSEL_Pos) %LCD_CR_SCSEL_LSCLK_16 (0x2U << LCD_CR_SCSEL_Pos) &LCD_CR_SCSEL_LSCLK_32 (0x3U << LCD_CR_SCSEL_Pos) 'LCD_CR_SCSEL_LSCLK_64 (0x4U << LCD_CR_SCSEL_Pos) (LCD_CR_SCSEL_LSCLK_128 (0x5U << LCD_CR_SCSEL_Pos) )LCD_CR_SCSEL_LSCLK_256 (0x6U << LCD_CR_SCSEL_Pos) *LCD_CR_SCSEL_LSCLK_512 (0x7U << LCD_CR_SCSEL_Pos) ,LCD_CR_SC_CTRL_Pos 18 1LCD_CR_SC_CTRL_Msk (0x3U << LCD_CR_SC_CTRL_Pos) 2LCD_CR_SC_CTRL_S0 (0x0U << LCD_CR_SC_CTRL_Pos) 3LCD_CR_SC_CTRL_S1 (0x1U << LCD_CR_SC_CTRL_Pos) 4LCD_CR_SC_CTRL_S2 (0x2U << LCD_CR_SC_CTRL_Pos) 5LCD_CR_SC_CTRL_S3 (0x3U << LCD_CR_SC_CTRL_Pos) 8LCD_CR_IC_CTRL_Pos 16 =LCD_CR_IC_CTRL_Msk (0x3U << LCD_CR_IC_CTRL_Pos) >LCD_CR_IC_CTRL_L3 (0x0U << LCD_CR_IC_CTRL_Pos) ?LCD_CR_IC_CTRL_L2 (0x1U << LCD_CR_IC_CTRL_Pos) @LCD_CR_IC_CTRL_L1 (0x2U << LCD_CR_IC_CTRL_Pos) ALCD_CR_IC_CTRL_L0 (0x3U << LCD_CR_IC_CTRL_Pos) CLCD_CR_ENMODE_Pos 15 FLCD_CR_ENMODE_Msk (0x1U << LCD_CR_ENMODE_Pos) GLCD_CR_ENMODE_EXTERNALCAP (0x0U << LCD_CR_ENMODE_Pos) HLCD_CR_ENMODE_INNERRESISTER (0x1U << LCD_CR_ENMODE_Pos) JLCD_CR_FLICK_Pos 14 MLCD_CR_FLICK_Msk (0x1U << LCD_CR_FLICK_Pos) QLCD_CR_BIAS_Pos 8 RLCD_CR_BIAS_Msk (0xfU << LCD_CR_BIAS_Pos) TLCD_CR_BIASMD_Pos 5 WLCD_CR_BIASMD_Msk (0x1U << LCD_CR_BIASMD_Pos) XLCD_CR_BIASMD_3BIAS (0x1U << LCD_CR_BIASMD_Pos) YLCD_CR_BIASMD_4BIAS (0x0U << LCD_CR_BIASMD_Pos) [LCD_CR_ANTIPOLAR_Pos 4 ^LCD_CR_ANTIPOLAR_Msk (0x1U << LCD_CR_ANTIPOLAR_Pos) _LCD_CR_ANTIPOLAR_GND (0x1U << LCD_CR_ANTIPOLAR_Pos) `LCD_CR_ANTIPOLAR_FLOAT (0x0U << LCD_CR_ANTIPOLAR_Pos) bLCD_CR_WFT_Pos 3 eLCD_CR_WFT_Msk (0x1U << LCD_CR_WFT_Pos) fLCD_CR_WFT_BTYPE (0x1U << LCD_CR_WFT_Pos) gLCD_CR_WFT_ATYPE (0x0U << LCD_CR_WFT_Pos) iLCD_CR_LMUX_Pos 1 mLCD_CR_LMUX_Msk (0x3U << LCD_CR_LMUX_Pos) nLCD_CR_LMUX_4COM (0x0U << LCD_CR_LMUX_Pos) oLCD_CR_LMUX_6COM (0x1U << LCD_CR_LMUX_Pos) pLCD_CR_LMUX_8COM (0x2U << LCD_CR_LMUX_Pos) sLCD_CR_EN_Pos 0 vLCD_CR_EN_Msk (0x1U << LCD_CR_EN_Pos) zLCD_TEST_LCCTRL_Pos 7 |LCD_TEST_LCCTRL_Msk (0x1U << LCD_TEST_LCCTRL_Pos) }LCD_TEST_LCCTRL_LOW (0x0U << LCD_TEST_LCCTRL_Pos) ~LCD_TEST_LCCTRL_HIGH (0x1U << LCD_TEST_LCCTRL_Pos) LCD_TEST_TESTEN_Pos 0 LCD_TEST_TESTEN_Msk (0x1U << LCD_TEST_TESTEN_Pos) LCD_FCR_DF_Pos 0 LCD_FCR_DF_Msk (0xffU << LCD_FCR_DF_Pos) LCD_FLKT_TOFF_Pos 8 LCD_FLKT_TOFF_Msk (0xffU << LCD_FLKT_TOFF_Pos) LCD_FLKT_TON_Pos 0 LCD_FLKT_TON_Msk (0xffU << LCD_FLKT_TON_Pos) LCD_IER_DONIE_Pos 1 LCD_IER_DONIE_Msk (0x1U << LCD_IER_DONIE_Pos) LCD_IER_DOFFIE_Pos 0 LCD_IER_DOFFIE_Msk (0x1U << LCD_IER_DOFFIE_Pos) LCD_ISR_DONIF_Pos 1 ¢LCD_ISR_DONIF_Msk (0x1U << LCD_ISR_DONIF_Pos) ¤LCD_ISR_DOFFIF_Pos 0 ¦LCD_ISR_DOFFIF_Msk (0x1U << LCD_ISR_DOFFIF_Pos) ¨LCD_BSTCR_OSC_CFG_Pos 12 ©LCD_BSTCR_OSC_CFG_Msk (0xfU << LCD_BSTCR_OSC_CFG_Pos) «LCD_BSTCR_BUF_OFF_Pos 9 ¬LCD_BSTCR_BUF_OFF_Msk (0x1U << LCD_BSTCR_BUF_OFF_Pos) ®LCD_BSTCR_BUFBYP_Pos 8 ¯LCD_BSTCR_BUFBYP_Msk (0x1U << LCD_BSTCR_BUFBYP_Pos) ±LCD_BSTCR_VLCDPD_Pos 7 ²LCD_BSTCR_VLCDPD_Msk (0x1U << LCD_BSTCR_VLCDPD_Pos) ´LCD_BSTCR_VLCDCFG_Pos 2 µLCD_BSTCR_VLCDCFG_Msk (0x1fU << LCD_BSTCR_VLCDCFG_Pos) ¶LCD_BSTCR_VLCDCFG_2_4V (0x0U << LCD_BSTCR_VLCDCFG_Pos) ·LCD_BSTCR_VLCDCFG_2_6V (0x1U << LCD_BSTCR_VLCDCFG_Pos) ¸LCD_BSTCR_VLCDCFG_2_8V (0x2U << LCD_BSTCR_VLCDCFG_Pos) ¹LCD_BSTCR_VLCDCFG_3_0V (0x3U << LCD_BSTCR_VLCDCFG_Pos) ºLCD_BSTCR_VLCDCFG_3_2V (0x4U << LCD_BSTCR_VLCDCFG_Pos) »LCD_BSTCR_VLCDCFG_3_4V (0x5U << LCD_BSTCR_VLCDCFG_Pos) ¼LCD_BSTCR_VLCDCFG_3_6V (0x6U << LCD_BSTCR_VLCDCFG_Pos) ½LCD_BSTCR_VLCDCFG_3_8V (0x7U << LCD_BSTCR_VLCDCFG_Pos) ¾LCD_BSTCR_VLCDCFG_4_0V (0x8U << LCD_BSTCR_VLCDCFG_Pos) ¿LCD_BSTCR_VLCDCFG_4_2V (0x9U << LCD_BSTCR_VLCDCFG_Pos) ÀLCD_BSTCR_VLCDCFG_4_4V (0xaU << LCD_BSTCR_VLCDCFG_Pos) ÁLCD_BSTCR_VLCDCFG_4_6V (0xbU << LCD_BSTCR_VLCDCFG_Pos) ÂLCD_BSTCR_VLCDCFG_4_8V (0xcU << LCD_BSTCR_VLCDCFG_Pos) ÃLCD_BSTCR_VLCDCFG_5_0V (0xdU << LCD_BSTCR_VLCDCFG_Pos) ÄLCD_BSTCR_VLCDCFG_5_2V (0xeU << LCD_BSTCR_VLCDCFG_Pos) ÅLCD_BSTCR_VLCDCFG_5_4V (0xfU << LCD_BSTCR_VLCDCFG_Pos) ÇLCD_BSTCR_BOOST_TEN_Pos 1 ÈLCD_BSTCR_BOOST_TEN_Msk (0x1U << LCD_BSTCR_BOOST_TEN_Pos) ÊLCD_BSTCR_BOOST_EN_Pos 0 ËLCD_BSTCR_BOOST_EN_Msk (0x1U << LCD_BSTCR_BOOST_EN_Pos) ÍLCD_COM_EN_COMEN_Pos 0 ÎLCD_COM_EN_COMEN_Msk (0xfU << LCD_COM_EN_COMEN_Pos) ÐLCD_SEG_EN0_SEGENx_Pos 0 ÑLCD_SEG_EN0_SEGENx_Msk (0xffffffffU << LCD_SEG_EN0_SEGENx_Pos) ÓLCD_SEG_EN1_SEGENx_Pos 0 ÔLCD_SEG_EN1_SEGENx_Msk (0xfffU << LCD_SEG_EN1_SEGENx_Pos) ÖLCD_COM_EN_COMEN3_Pos 3 ×LCD_COM_EN_COMEN3_Msk (0x1U << LCD_COM_EN_COMEN3_Pos) ÙLCD_COM_EN_COMEN2_Pos 2 ÚLCD_COM_EN_COMEN2_Msk (0x1U << LCD_COM_EN_COMEN2_Pos) ÜLCD_COM_EN_COMEN1_Pos 1 ÝLCD_COM_EN_COMEN1_Msk (0x1U << LCD_COM_EN_COMEN1_Pos) ßLCD_COM_EN_COMEN0_Pos 0 àLCD_COM_EN_COMEN0_Msk (0x1U << LCD_COM_EN_COMEN0_Pos) âLCD_SEG_EN0_SEGEN31_Pos 31 ãLCD_SEG_EN0_SEGEN31_Msk (0x1U << LCD_SEG_EN0_SEGEN31_Pos) åLCD_SEG_EN0_SEGEN30_Pos 30 æLCD_SEG_EN0_SEGEN30_Msk (0x1U << LCD_SEG_EN0_SEGEN30_Pos) èLCD_SEG_EN0_SEGEN29_Pos 29 éLCD_SEG_EN0_SEGEN29_Msk (0x1U << LCD_SEG_EN0_SEGEN29_Pos) ëLCD_SEG_EN0_SEGEN28_Pos 28 ìLCD_SEG_EN0_SEGEN28_Msk (0x1U << LCD_SEG_EN0_SEGEN28_Pos) îLCD_SEG_EN0_SEGEN27_Pos 27 ïLCD_SEG_EN0_SEGEN27_Msk (0x1U << LCD_SEG_EN0_SEGEN27_Pos) ñLCD_SEG_EN0_SEGEN26_Pos 26 òLCD_SEG_EN0_SEGEN26_Msk (0x1U << LCD_SEG_EN0_SEGEN26_Pos) ôLCD_SEG_EN0_SEGEN25_Pos 25 õLCD_SEG_EN0_SEGEN25_Msk (0x1U << LCD_SEG_EN0_SEGEN25_Pos) ÷LCD_SEG_EN0_SEGEN24_Pos 24 øLCD_SEG_EN0_SEGEN24_Msk (0x1U << LCD_SEG_EN0_SEGEN24_Pos) úLCD_SEG_EN0_SEGEN23_Pos 23 ûLCD_SEG_EN0_SEGEN23_Msk (0x1U << LCD_SEG_EN0_SEGEN23_Pos) ýLCD_SEG_EN0_SEGEN22_Pos 22 þLCD_SEG_EN0_SEGEN22_Msk (0x1U << LCD_SEG_EN0_SEGEN22_Pos) LCD_SEG_EN0_SEGEN21_Pos 21 LCD_SEG_EN0_SEGEN21_Msk (0x1U << LCD_SEG_EN0_SEGEN21_Pos) LCD_SEG_EN0_SEGEN20_Pos 20 LCD_SEG_EN0_SEGEN20_Msk (0x1U << LCD_SEG_EN0_SEGEN20_Pos) LCD_SEG_EN0_SEGEN19_Pos 19 LCD_SEG_EN0_SEGEN19_Msk (0x1U << LCD_SEG_EN0_SEGEN19_Pos) LCD_SEG_EN0_SEGEN18_Pos 18 LCD_SEG_EN0_SEGEN18_Msk (0x1U << LCD_SEG_EN0_SEGEN18_Pos) LCD_SEG_EN0_SEGEN17_Pos 17 LCD_SEG_EN0_SEGEN17_Msk (0x1U << LCD_SEG_EN0_SEGEN17_Pos) LCD_SEG_EN0_SEGEN16_Pos 16 LCD_SEG_EN0_SEGEN16_Msk (0x1U << LCD_SEG_EN0_SEGEN16_Pos) LCD_SEG_EN0_SEGEN15_Pos 15 LCD_SEG_EN0_SEGEN15_Msk (0x1U << LCD_SEG_EN0_SEGEN15_Pos) LCD_SEG_EN0_SEGEN14_Pos 14 LCD_SEG_EN0_SEGEN14_Msk (0x1U << LCD_SEG_EN0_SEGEN14_Pos) LCD_SEG_EN0_SEGEN13_Pos 13 LCD_SEG_EN0_SEGEN13_Msk (0x1U << LCD_SEG_EN0_SEGEN13_Pos) LCD_SEG_EN0_SEGEN12_Pos 12 LCD_SEG_EN0_SEGEN12_Msk (0x1U << LCD_SEG_EN0_SEGEN12_Pos) LCD_SEG_EN0_SEGEN11_Pos 11 LCD_SEG_EN0_SEGEN11_Msk (0x1U << LCD_SEG_EN0_SEGEN11_Pos) ¡LCD_SEG_EN0_SEGEN10_Pos 10 ¢LCD_SEG_EN0_SEGEN10_Msk (0x1U << LCD_SEG_EN0_SEGEN10_Pos) ¤LCD_SEG_EN0_SEGEN9_Pos 9 ¥LCD_SEG_EN0_SEGEN9_Msk (0x1U << LCD_SEG_EN0_SEGEN9_Pos) §LCD_SEG_EN0_SEGEN8_Pos 8 ¨LCD_SEG_EN0_SEGEN8_Msk (0x1U << LCD_SEG_EN0_SEGEN8_Pos) ªLCD_SEG_EN0_SEGEN7_Pos 7 «LCD_SEG_EN0_SEGEN7_Msk (0x1U << LCD_SEG_EN0_SEGEN7_Pos) LCD_SEG_EN0_SEGEN6_Pos 6 ®LCD_SEG_EN0_SEGEN6_Msk (0x1U << LCD_SEG_EN0_SEGEN6_Pos) °LCD_SEG_EN0_SEGEN5_Pos 5 ±LCD_SEG_EN0_SEGEN5_Msk (0x1U << LCD_SEG_EN0_SEGEN5_Pos) ³LCD_SEG_EN0_SEGEN4_Pos 4 ´LCD_SEG_EN0_SEGEN4_Msk (0x1U << LCD_SEG_EN0_SEGEN4_Pos) ¶LCD_SEG_EN0_SEGEN3_Pos 3 ·LCD_SEG_EN0_SEGEN3_Msk (0x1U << LCD_SEG_EN0_SEGEN3_Pos) ¹LCD_SEG_EN0_SEGEN2_Pos 2 ºLCD_SEG_EN0_SEGEN2_Msk (0x1U << LCD_SEG_EN0_SEGEN2_Pos) ¼LCD_SEG_EN0_SEGEN1_Pos 1 ½LCD_SEG_EN0_SEGEN1_Msk (0x1U << LCD_SEG_EN0_SEGEN1_Pos) ¿LCD_SEG_EN0_SEGEN0_Pos 0 ÀLCD_SEG_EN0_SEGEN0_Msk (0x1U << LCD_SEG_EN0_SEGEN0_Pos) ÂLCD_SEG_EN1_SEGEN43_Pos 11 ÃLCD_SEG_EN1_SEGEN43_Msk (0x1U << LCD_SEG_EN1_SEGEN43_Pos) ÅLCD_SEG_EN1_SEGEN42_Pos 10 ÆLCD_SEG_EN1_SEGEN42_Msk (0x1U << LCD_SEG_EN1_SEGEN42_Pos) ÈLCD_SEG_EN1_SEGEN41_Pos 9 ÉLCD_SEG_EN1_SEGEN41_Msk (0x1U << LCD_SEG_EN1_SEGEN41_Pos) ËLCD_SEG_EN1_SEGEN40_Pos 8 ÌLCD_SEG_EN1_SEGEN40_Msk (0x1U << LCD_SEG_EN1_SEGEN40_Pos) ÎLCD_SEG_EN1_SEGEN39_Pos 7 ÏLCD_SEG_EN1_SEGEN39_Msk (0x1U << LCD_SEG_EN1_SEGEN39_Pos) ÑLCD_SEG_EN1_SEGEN38_Pos 6 ÒLCD_SEG_EN1_SEGEN38_Msk (0x1U << LCD_SEG_EN1_SEGEN38_Pos) ÔLCD_SEG_EN1_SEGEN37_Pos 5 ÕLCD_SEG_EN1_SEGEN37_Msk (0x1U << LCD_SEG_EN1_SEGEN37_Pos) ×LCD_SEG_EN1_SEGEN36_Pos 4 ØLCD_SEG_EN1_SEGEN36_Msk (0x1U << LCD_SEG_EN1_SEGEN36_Pos) ÚLCD_SEG_EN1_SEGEN35_Pos 3 ÛLCD_SEG_EN1_SEGEN35_Msk (0x1U << LCD_SEG_EN1_SEGEN35_Pos) ÝLCD_SEG_EN1_SEGEN34_Pos 2 ÞLCD_SEG_EN1_SEGEN34_Msk (0x1U << LCD_SEG_EN1_SEGEN34_Pos) àLCD_SEG_EN1_SEGEN33_Pos 1 áLCD_SEG_EN1_SEGEN33_Msk (0x1U << LCD_SEG_EN1_SEGEN33_Pos) ãLCD_SEG_EN1_SEGEN32_Pos 0 äLCD_SEG_EN1_SEGEN32_Msk (0x1U << LCD_SEG_EN1_SEGEN32_Pos) æLCD_SEG_EN1_COMEN7_Pos 11 çLCD_SEG_EN1_COMEN7_Msk (0x1U << LCD_SEG_EN1_COMEN7_Pos) éLCD_SEG_EN1_COMEN6_Pos 10 êLCD_SEG_EN1_COMEN6_Msk (0x1U << LCD_SEG_EN1_COMEN6_Pos) ìLCD_SEG_EN1_COMEN5_Pos 9 íLCD_SEG_EN1_COMEN5_Msk (0x1U << LCD_SEG_EN1_COMEN5_Pos) ïLCD_SEG_EN1_COMEN4_Pos 8 ðLCD_SEG_EN1_COMEN4_Msk (0x1U << LCD_SEG_EN1_COMEN4_Pos) ` T ..\Drivers\ ..\Core\Include\ fm33a0xxev_lcd.h FM33A0XXEV.h ¼
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..\Drivers\fm33a0xxev_lcd.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM I J K __FM33A0XXEV_DMA_H 2DMA_GCR_DMA_ADDRERR_EN_Pos 1 5DMA_GCR_DMA_ADDRERR_EN_Msk (0x1U << DMA_GCR_DMA_ADDRERR_EN_Pos) 7DMA_GCR_DMAEN_Pos 0 :DMA_GCR_DMAEN_Msk (0x1U << DMA_GCR_DMAEN_Pos) <DMA_CHxCR_CHxTSIZE_Pos 16 =DMA_CHxCR_CHxTSIZE_Msk (0x1fffU << DMA_CHxCR_CHxTSIZE_Pos) ?DMA_CHxCR_CHxPRI_Pos 12 DDMA_CHxCR_CHxPRI_Msk (0x3U << DMA_CHxCR_CHxPRI_Pos) EDMA_CHxCR_CHxPRI_LOW (0x0U << DMA_CHxCR_CHxPRI_Pos) FDMA_CHxCR_CHxPRI_MEDIUM (0x1U << DMA_CHxCR_CHxPRI_Pos) GDMA_CHxCR_CHxPRI_HIGH (0x2U << DMA_CHxCR_CHxPRI_Pos) HDMA_CHxCR_CHxPRI_VERY_HIGH (0x3U << DMA_CHxCR_CHxPRI_Pos) JDMA_CHxCR_CHxINC_Pos 11 MDMA_CHxCR_CHxINC_Msk (0x1U << DMA_CHxCR_CHxINC_Pos) NDMA_CHxCR_CHxINC_INCREASE (0x1U << DMA_CHxCR_CHxINC_Pos) ODMA_CHxCR_CHxINC_DECREASE (0x0U << DMA_CHxCR_CHxINC_Pos) QDMA_CHxCR_CHxSSEL_Pos 8 SDMA_CHxCR_CHxSSEL_Msk (0x7U << DMA_CHxCR_CHxSSEL_Pos) UDMA_CHxCR_CH0SSEL_ADC (0x0U << DMA_CHxCR_CHxSSEL_Pos) VDMA_CHxCR_CH0SSEL_SPI3_RX (0x1U << DMA_CHxCR_CHxSSEL_Pos) WDMA_CHxCR_CH0SSEL_LPUART0_RX (0x2U << DMA_CHxCR_CHxSSEL_Pos) XDMA_CHxCR_CH0SSEL_LPUART1_RX (0x3U << DMA_CHxCR_CHxSSEL_Pos) YDMA_CHxCR_CH0SSEL_UART2_RX (0x4U << DMA_CHxCR_CHxSSEL_Pos) ZDMA_CHxCR_CH0SSEL_UART4_RX (0x5U << DMA_CHxCR_CHxSSEL_Pos) [DMA_CHxCR_CH0SSEL_AES_IN (0x6U << DMA_CHxCR_CHxSSEL_Pos) \DMA_CHxCR_CH0SSEL_QSPI (0x7U << DMA_CHxCR_CHxSSEL_Pos) ^DMA_CHxCR_CH1SSEL_ADC (0x0U << DMA_CHxCR_CHxSSEL_Pos) _DMA_CHxCR_CH1SSEL_SPI0_RX (0x1U << DMA_CHxCR_CHxSSEL_Pos) `DMA_CHxCR_CH1SSEL_SPI2_RX (0x2U << DMA_CHxCR_CHxSSEL_Pos) aDMA_CHxCR_CH1SSEL_SPI3_TX (0x3U << DMA_CHxCR_CHxSSEL_Pos) bDMA_CHxCR_CH1SSEL_UART0_RX (0x4U << DMA_CHxCR_CHxSSEL_Pos) cDMA_CHxCR_CH1SSEL_UART2_TX (0x5U << DMA_CHxCR_CHxSSEL_Pos) dDMA_CHxCR_CH1SSEL_UART3_RX (0x6U << DMA_CHxCR_CHxSSEL_Pos) eDMA_CHxCR_CH1SSEL_U7816_RX (0x7U << DMA_CHxCR_CHxSSEL_Pos) gDMA_CHxCR_CH2SSEL_SPI0_TX (0x0U << DMA_CHxCR_CHxSSEL_Pos) hDMA_CHxCR_CH2SSEL_SPI2_TX (0x1U << DMA_CHxCR_CHxSSEL_Pos) iDMA_CHxCR_CH2SSEL_SPI4_RX (0x2U << DMA_CHxCR_CHxSSEL_Pos) jDMA_CHxCR_CH2SSEL_UART0_TX (0x3U << DMA_CHxCR_CHxSSEL_Pos) kDMA_CHxCR_CH2SSEL_UART3_TX (0x4U << DMA_CHxCR_CHxSSEL_Pos) lDMA_CHxCR_CH2SSEL_UART5_RX (0x5U << DMA_CHxCR_CHxSSEL_Pos) mDMA_CHxCR_CH2SSEL_U7816_TX (0x6U << DMA_CHxCR_CHxSSEL_Pos) nDMA_CHxCR_CH2SSEL_AES_OUT (0x7U << DMA_CHxCR_CHxSSEL_Pos) pDMA_CHxCR_CH3SSEL_SPI1_RX (0x0U << DMA_CHxCR_CHxSSEL_Pos) qDMA_CHxCR_CH3SSEL_SPI4_TX (0x1U << DMA_CHxCR_CHxSSEL_Pos) rDMA_CHxCR_CH3SSEL_LPUART0_RX (0x2U << DMA_CHxCR_CHxSSEL_Pos) sDMA_CHxCR_CH3SSEL_UART1_RX (0x3U << DMA_CHxCR_CHxSSEL_Pos) tDMA_CHxCR_CH3SSEL_UART4_RX (0x4U << DMA_CHxCR_CHxSSEL_Pos) uDMA_CHxCR_CH3SSEL_UART5_TX (0x5U << DMA_CHxCR_CHxSSEL_Pos) vDMA_CHxCR_CH3SSEL_I2C0_TX (0x6U << DMA_CHxCR_CHxSSEL_Pos) wDMA_CHxCR_CH3SSEL_AES_IN (0x7U << DMA_CHxCR_CHxSSEL_Pos) yDMA_CHxCR_CH4SSEL_SPI1_TX (0x0U << DMA_CHxCR_CHxSSEL_Pos) zDMA_CHxCR_CH4SSEL_SPI3_RX (0x1U << DMA_CHxCR_CHxSSEL_Pos) {DMA_CHxCR_CH4SSEL_LPUART0_TX (0x2U << DMA_CHxCR_CHxSSEL_Pos) |DMA_CHxCR_CH4SSEL_UART1_TX (0x3U << DMA_CHxCR_CHxSSEL_Pos) }DMA_CHxCR_CH4SSEL_UART2_RX (0x4U << DMA_CHxCR_CHxSSEL_Pos) ~DMA_CHxCR_CH4SSEL_UART4_TX (0x5U << DMA_CHxCR_CHxSSEL_Pos) DMA_CHxCR_CH4SSEL_I2C0_RX (0x6U << DMA_CHxCR_CHxSSEL_Pos) DMA_CHxCR_CH4SSEL_AES_OUT (0x7U << DMA_CHxCR_CHxSSEL_Pos) DMA_CHxCR_CH5SSEL_SPI0_RX (0x0U << DMA_CHxCR_CHxSSEL_Pos) DMA_CHxCR_CH5SSEL_SPI2_RX (0x1U << DMA_CHxCR_CHxSSEL_Pos) DMA_CHxCR_CH5SSEL_LPUART1_RX (0x2U << DMA_CHxCR_CHxSSEL_Pos)
DMA_CHxCR_CH5SSEL_UART1_RX (0x3U << DMA_CHxCR_CHxSSEL_Pos) DMA_CHxCR_CH5SSEL_UART2_TX (0x4U << DMA_CHxCR_CHxSSEL_Pos) DMA_CHxCR_CH5SSEL_UART3_RX (0x5U << DMA_CHxCR_CHxSSEL_Pos) DMA_CHxCR_CH5SSEL_UART5_RX (0x6U << DMA_CHxCR_CHxSSEL_Pos) DMA_CHxCR_CH5SSEL_I2C1_TX (0x7U << DMA_CHxCR_CHxSSEL_Pos) DMA_CHxCR_CH6SSEL_SPI0_TX (0x0U << DMA_CHxCR_CHxSSEL_Pos) DMA_CHxCR_CH6SSEL_SPI2_TX (0x1U << DMA_CHxCR_CHxSSEL_Pos) DMA_CHxCR_CH6SSEL_LPUART1_TX (0x2U << DMA_CHxCR_CHxSSEL_Pos) DMA_CHxCR_CH6SSEL_UART1_TX (0x3U << DMA_CHxCR_CHxSSEL_Pos) DMA_CHxCR_CH6SSEL_UART3_TX (0x4U << DMA_CHxCR_CHxSSEL_Pos) DMA_CHxCR_CH6SSEL_UART5_TX (0x5U << DMA_CHxCR_CHxSSEL_Pos) DMA_CHxCR_CH6SSEL_I2C1_RX (0x6U << DMA_CHxCR_CHxSSEL_Pos) DMA_CHxCR_CH6SSEL_CRC (0x7U << DMA_CHxCR_CHxSSEL_Pos) DMA_CHxCR_CH7SSEL_ADC (0x0U << DMA_CHxCR_CHxSSEL_Pos) DMA_CHxCR_CH7SSEL_SPI1_RX (0x1U << DMA_CHxCR_CHxSSEL_Pos) DMA_CHxCR_CH7SSEL_SPI3_RX (0x2U << DMA_CHxCR_CHxSSEL_Pos) DMA_CHxCR_CH7SSEL_LPUART0_RX (0x3U << DMA_CHxCR_CHxSSEL_Pos) DMA_CHxCR_CH7SSEL_UART0_RX (0x4U << DMA_CHxCR_CHxSSEL_Pos) DMA_CHxCR_CH7SSEL_UART2_RX (0x5U << DMA_CHxCR_CHxSSEL_Pos) DMA_CHxCR_CH7SSEL_UART4_RX (0x6U << DMA_CHxCR_CHxSSEL_Pos) DMA_CHxCR_CH7SSEL_QSPI (0x7U << DMA_CHxCR_CHxSSEL_Pos) DMA_CHxCR_CH8SSEL_ADC (0x0U << DMA_CHxCR_CHxSSEL_Pos) DMA_CHxCR_CH8SSEL_SPI1_TX (0x1U << DMA_CHxCR_CHxSSEL_Pos) DMA_CHxCR_CH8SSEL_SPI2_RX (0x2U << DMA_CHxCR_CHxSSEL_Pos) DMA_CHxCR_CH8SSEL_SPI3_TX (0x3U << DMA_CHxCR_CHxSSEL_Pos) ¡DMA_CHxCR_CH8SSEL_LPUART0_TX (0x4U << DMA_CHxCR_CHxSSEL_Pos) ¢DMA_CHxCR_CH8SSEL_UART0_TX (0x5U << DMA_CHxCR_CHxSSEL_Pos) £DMA_CHxCR_CH8SSEL_UART2_TX (0x6U << DMA_CHxCR_CHxSSEL_Pos) ¤DMA_CHxCR_CH8SSEL_UART4_TX (0x7U << DMA_CHxCR_CHxSSEL_Pos) ¦DMA_CHxCR_CH9SSEL_SPI0_RX (0x0U << DMA_CHxCR_CHxSSEL_Pos) §DMA_CHxCR_CH9SSEL_SPI2_TX (0x1U << DMA_CHxCR_CHxSSEL_Pos) ¨DMA_CHxCR_CH9SSEL_SPI4_RX (0x2U << DMA_CHxCR_CHxSSEL_Pos) ©DMA_CHxCR_CH9SSEL_LPUART1_RX (0x3U << DMA_CHxCR_CHxSSEL_Pos) ªDMA_CHxCR_CH9SSEL_UART1_RX (0x4U << DMA_CHxCR_CHxSSEL_Pos) «DMA_CHxCR_CH9SSEL_UART3_RX (0x5U << DMA_CHxCR_CHxSSEL_Pos) ¬DMA_CHxCR_CH9SSEL_UART5_RX (0x6U << DMA_CHxCR_CHxSSEL_Pos) DMA_CHxCR_CH9SSEL_I2C0_TX (0x7U << DMA_CHxCR_CHxSSEL_Pos) ¯DMA_CHxCR_CH10SSEL_SPI0_TX (0x0U << DMA_CHxCR_CHxSSEL_Pos) °DMA_CHxCR_CH10SSEL_SPI4_TX (0x1U << DMA_CHxCR_CHxSSEL_Pos) ±DMA_CHxCR_CH10SSEL_LPUART1_TX (0x2U << DMA_CHxCR_CHxSSEL_Pos) ²DMA_CHxCR_CH10SSEL_UART1_TX (0x3U << DMA_CHxCR_CHxSSEL_Pos) ³DMA_CHxCR_CH10SSEL_UART3_TX (0x4U << DMA_CHxCR_CHxSSEL_Pos) ´DMA_CHxCR_CH10SSEL_UART5_TX (0x5U << DMA_CHxCR_CHxSSEL_Pos) µDMA_CHxCR_CH10SSEL_I2C0_RX (0x6U << DMA_CHxCR_CHxSSEL_Pos) ¶DMA_CHxCR_CH10SSEL_CRC (0x7U << DMA_CHxCR_CHxSSEL_Pos) ¸DMA_CHxCR_CIRC_UPD_Pos 7 ¼DMA_CHxCR_CIRC_UPD_Msk (0x1U << DMA_CHxCR_CIRC_UPD_Pos) ÁDMA_CHxCR_DIR_Pos 6 ÄDMA_CHxCR_DIR_Msk (0x1U << DMA_CHxCR_DIR_Pos) ÅDMA_CHxCR_DIR_TO_RAM (0x0U << DMA_CHxCR_DIR_Pos) ÆDMA_CHxCR_DIR_TO_PER (0x1U << DMA_CHxCR_DIR_Pos) ÈDMA_CHxCR_BDW_Pos 4 ÍDMA_CHxCR_BDW_Msk (0x3U << DMA_CHxCR_BDW_Pos) ÎDMA_CHxCR_BDW_8BITS (0x0U << DMA_CHxCR_BDW_Pos) ÏDMA_CHxCR_BDW_16BITS (0x1U << DMA_CHxCR_BDW_Pos) ÐDMA_CHxCR_BDW_32BITS (0x2U << DMA_CHxCR_BDW_Pos) ÒDMA_CHxCR_CIRC_Pos 3 ÕDMA_CHxCR_CIRC_Msk (0x1U << DMA_CHxCR_CIRC_Pos) ÙDMA_CHxCR_CHxFTIE_Pos 2 ÜDMA_CHxCR_CHxFTIE_Msk (0x1U << DMA_CHxCR_CHxFTIE_Pos) àDMA_CHxCR_CHxHTIE_Pos 1 ãDMA_CHxCR_CHxHTIE_Msk (0x1U << DMA_CHxCR_CHxHTIE_Pos) çDMA_CHxCR_ChxEN_Pos 0 êDMA_CHxCR_ChxEN_Msk (0x1U << DMA_CHxCR_ChxEN_Pos) îDMA_CHxMAR_CHxMEMAD_Pos 0 ôDMA_CHxMAR_CHxMEMAD_Msk (0xffffffffU << DMA_CHxMAR_CHxMEMAD_Pos) öDMA_CH11CR_CH11TSIZE_Pos 16 ÷DMA_CH11CR_CH11TSIZE_Msk (0x1fffU << DMA_CH11CR_CH11TSIZE_Pos) ùDMA_CH11CR_CH11PRI_Pos 12 þDMA_CH11CR_CH11PRI_Msk (0x3U << DMA_CH11CR_CH11PRI_Pos) ÿDMA_CH11CR_CH11PRI_LOW (0x0U << DMA_CH11CR_CH11PRI_Pos) DMA_CH11CR_CH11PRI_MEDIUM (0x1U << DMA_CH11CR_CH11PRI_Pos) DMA_CH11CR_CH11PRI_HIGH (0x2U << DMA_CH11CR_CH11PRI_Pos) DMA_CH11CR_CH11PRI_VERY_HIGH (0x3U << DMA_CH11CR_CH11PRI_Pos) DMA_CH11CR_CH11DIR_Pos 10 DMA_CH11CR_CH11DIR_Msk (0x1U << DMA_CH11CR_CH11DIR_Pos) DMA_CH11CR_CH11DIR_TO_RAM (0x1U << DMA_CH11CR_CH11DIR_Pos) DMA_CH11CR_CH11DIR_TO_FLASH (0x0U << DMA_CH11CR_CH11DIR_Pos) DMA_CH11CR_CH11RI_Pos 9 DMA_CH11CR_CH11RI_Msk (0x1U << DMA_CH11CR_CH11RI_Pos) DMA_CH11CR_CH11RI_INCREASE (0x1U << DMA_CH11CR_CH11RI_Pos) DMA_CH11CR_CH11RI_DECREASE (0x0U << DMA_CH11CR_CH11RI_Pos) DMA_CH11CR_CH11FI_Pos 8 DMA_CH11CR_CH11FI_Msk (0x1U << DMA_CH11CR_CH11FI_Pos) DMA_CH11CR_CH11FI_INCREASE (0x1U << DMA_CH11CR_CH11FI_Pos) DMA_CH11CR_CH11FI_DECREASE (0x0U << DMA_CH11CR_CH11FI_Pos) DMA_CH11CR_CH11FTIE_Pos 2 DMA_CH11CR_CH11FTIE_Msk (0x1U << DMA_CH11CR_CH11FTIE_Pos) DMA_CH11CR_CH11HTIE_Pos 1 £DMA_CH11CR_CH11HTIE_Msk (0x1U << DMA_CH11CR_CH11HTIE_Pos) §DMA_CH11CR_CH11EN_Pos 0 ªDMA_CH11CR_CH11EN_Msk (0x1U << DMA_CH11CR_CH11EN_Pos) ®DMA_CH11FAR_CH11FLSAD_Pos 0 ±DMA_CH11FAR_CH11FLSAD_Msk (0x7fffU << DMA_CH11FAR_CH11FLSAD_Pos) ³DMA_CH11RAR_CH7RAMAD_Pos 0 µDMA_CH11RAR_CH7RAMAD_Msk (0x7fffU << DMA_CH11RAR_CH7RAMAD_Pos) ·DMA_ISR_DMA_ADDRERR_Pos 28 ¸DMA_ISR_DMA_ADDRERR_Msk (0x1U << DMA_ISR_DMA_ADDRERR_Pos) ºDMA_ISR_DMACHFT_Pos 16 ½DMA_ISR_DMACHFT_Msk (0xfffU << DMA_ISR_DMACHFT_Pos) ¿DMA_ISR_DMACHHT_Pos 0 ÀDMA_ISR_DMACHHT_Msk (0xfffU << DMA_ISR_DMACHHT_Pos) ÂDMA_CHxCSR_CHxTSIZE_SDW_Pos 16 ÃDMA_CHxCSR_CHxTSIZE_SDW_Msk (0x1fffU << DMA_CHxCSR_CHxTSIZE_SDW_Pos) ÅDMA_CHxCSR_CHxINC_SDW_Pos 11 ÆDMA_CHxCSR_CHxINC_SDW_Msk (0x1U << DMA_CHxCSR_CHxINC_SDW_Pos) ÈDMA_CHxMASR_CHxMAD_SDW_Pos 0 ÊDMA_CHxMASR_CHxMAD_SDW_Msk (0xffffffffU << DMA_CHxMASR_CHxMAD_SDW_Pos) ` T ..\Drivers\ ..\Core\Include\ fm33a0xxev_dma.h FM33A0XXEV.h l
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..\Drivers\fm33a0xxev_dma.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM ÈDMA_CH0 DMA_CH1 DMA_CH2 DMA_CH3 DMA_CH4 DMA_CH5 DMA_CH6 DMA_CH7 DMA_CH8 DMA_CH9 DMA_CH10
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DMA_CH11 PDMA_CH_Type ½ *Õ0 CHx H# CHxTSIZE f # CHxPRI f # CHxINC f # CHxSSEL f # CHxDIR f # CHxBDW f # CHxCICR # CHxFTIE # CHxHTIE # CHxEN # CHxRAMAD f # CH11RI f #$ CH11FI f #( CH11FLSAD f #, PDMA_InitTypeDef [0 M N O __FM33A0XXEV_GPIO_H cIS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET)) lIS_GPIO_INTERRUPT_TRIGER_EDGE(EDGE) (((EDGE) == EXTI_RISING) || ((EDGE) == EXTI_FALLING)|| ((EDGE) == EXTI_BOTH)|| ((EDGE) == EXTIDISABLE)) }IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || ((PERIPH) == GPIOB) || ((PERIPH) == GPIOC) || ((PERIPH) == GPIOD) || ((PERIPH) == GPIOE) || ((PERIPH) == GPIOF) || ((PERIPH) == GPIOG))
IS_GPIO_HD_PERIPH(PERIPH) ((PERIPH) == GPIOH) GPIO_Pin_0 ((uint32_t)0x00000001) GPIO_Pin_1 ((uint32_t)0x00000002) GPIO_Pin_2 ((uint32_t)0x00000004) GPIO_Pin_3 ((uint32_t)0x00000008) GPIO_Pin_4 ((uint32_t)0x00000010) GPIO_Pin_5 ((uint32_t)0x00000020) GPIO_Pin_6 ((uint32_t)0x00000040) GPIO_Pin_7 ((uint32_t)0x00000080) GPIO_Pin_8 ((uint32_t)0x00000100) GPIO_Pin_9 ((uint32_t)0x00000200) GPIO_Pin_10 ((uint32_t)0x00000400) GPIO_Pin_11 ((uint32_t)0x00000800) GPIO_Pin_12 ((uint32_t)0x00001000) GPIO_Pin_13 ((uint32_t)0x00002000) GPIO_Pin_14 ((uint32_t)0x00004000) GPIO_Pin_15 ((uint32_t)0x00008000) GPIO_Pin_All ((uint16_t)0xFFFF) IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00)) IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || ((PIN) == GPIO_Pin_1) || ((PIN) == GPIO_Pin_2) || ((PIN) == GPIO_Pin_3) || ((PIN) == GPIO_Pin_4) || ((PIN) == GPIO_Pin_5) || ((PIN) == GPIO_Pin_6) || ((PIN) == GPIO_Pin_7) || ((PIN) == GPIO_Pin_8) || ((PIN) == GPIO_Pin_9) || ((PIN) == GPIO_Pin_10) || ((PIN) == GPIO_Pin_11) || ((PIN) == GPIO_Pin_12) || ((PIN) == GPIO_Pin_13) || ((PIN) == GPIO_Pin_14) || ((PIN) == GPIO_Pin_15)) ¯IS_GET_GPIOH_PIN(PIN) (((PIN) == GPIO_Pin_0) || ((PIN) == GPIO_Pin_1) || ((PIN) == GPIO_Pin_2) || ((PIN) == GPIO_Pin_3)) ·PINWKEN_PD6 7 ¸PINWKEN_PE9 6 ¹PINWKEN_PE2 5 ºPINWKEN_PA13 4 »PINWKEN_PG7 3 ¼PINWKEN_PC13 2 ½PINWKEN_PB0 1 ¾PINWKEN_PF5 0 ÁGPIOx_INEN_INEN_Pos 0 ÂGPIOx_INEN_INEN_Msk (0xffffU << GPIOx_INEN_INEN_Pos) ÈGPIOx_PUEN_PUEN_Pos 0 ÉGPIOx_PUEN_PUEN_Msk (0xffffU << GPIOx_PUEN_PUEN_Pos) ÏGPIOx_ODEN_ODEN_Pos 0 ÐGPIOx_ODEN_ODEN_Msk (0xffffU << GPIOx_ODEN_ODEN_Pos) ÖGPIOx_FCR_Px15FCR_Pos 30 ×GPIOx_FCR_Px15FCR_Msk (0x03U << GPIOx_FCR_Px15FCR_Pos) ÝGPIOx_FCR_Px14FCR_Pos 28 ÞGPIOx_FCR_Px14FCR_Msk (0x03U << GPIOx_FCR_Px14FCR_Pos) äGPIOx_FCR_Px13FCR_Pos 26 åGPIOx_FCR_Px13FCR_Msk (0x03U << GPIOx_FCR_Px13FCR_Pos) ëGPIOx_FCR_Px12FCR_Pos 24 ìGPIOx_FCR_Px12FCR_Msk (0x03U << GPIOx_FCR_Px12FCR_Pos) òGPIOx_FCR_Px11FCR_Pos 22 óGPIOx_FCR_Px11FCR_Msk (0x03U << GPIOx_FCR_Px11FCR_Pos) ùGPIOx_FCR_Px10FCR_Pos 20 úGPIOx_FCR_Px10FCR_Msk (0x03U << GPIOx_FCR_Px10FCR_Pos) GPIOx_FCR_Px9FCR_Pos 18 GPIOx_FCR_Px9FCR_Msk (0x03U << GPIOx_FCR_Px9FCR_Pos) GPIOx_FCR_Px8FCR_Pos 16 GPIOx_FCR_Px8FCR_Msk (0x03U << GPIOx_FCR_Px8FCR_Pos) GPIOx_FCR_Px7FCR_Pos 14 GPIOx_FCR_Px7FCR_Msk (0x03U << GPIOx_FCR_Px7FCR_Pos) GPIOx_FCR_Px6FCR_Pos 12 GPIOx_FCR_Px6FCR_Msk (0x03U << GPIOx_FCR_Px6FCR_Pos) GPIOx_FCR_Px5FCR_Pos 10 GPIOx_FCR_Px5FCR_Msk (0x03U << GPIOx_FCR_Px5FCR_Pos) £GPIOx_FCR_Px4FCR_Pos 8 ¤GPIOx_FCR_Px4FCR_Msk (0x03U << GPIOx_FCR_Px4FCR_Pos) ªGPIOx_FCR_Px3FCR_Pos 6 «GPIOx_FCR_Px3FCR_Msk (0x03U << GPIOx_FCR_Px3FCR_Pos) ±GPIOx_FCR_Px2FCR_Pos 4 ²GPIOx_FCR_Px2FCR_Msk (0x03U << GPIOx_FCR_Px2FCR_Pos) ¸GPIOx_FCR_Px1FCR_Pos 2 ¹GPIOx_FCR_Px1FCR_Msk (0x03U << GPIOx_FCR_Px1FCR_Pos) ¿GPIOx_FCR_Px0FCR_Pos 0 ÀGPIOx_FCR_Px0FCR_Msk (0x03U << GPIOx_FCR_Px0FCR_Pos) ÈGPIOx_DO_DO_Pos 0 ÉGPIOx_DO_DO_Msk (0xffffU << GPIOx_DO_DO_Pos) ÍGPIOx_DSET_DSET_Pos 0 ÎGPIOx_DSET_DSET_Msk (0xffffU << GPIOx_DSET_DSET_Pos) ÔGPIOx_DRST_DRESET_Pos 0 ÕGPIOx_DRST_DRESET_Msk (0xffffU << GPIOx_DRST_DRESET_Pos) ÛGPIOx_DIN_DIN_Pos 0 ÜGPIOx_DIN_DIN_Msk (0xffffU << GPIOx_DIN_DIN_Pos) âGPIOx_DFS_DFS_Pos 0 ãGPIOx_DFS_DFS_Msk (0xffffU << GPIOx_DFS_DFS_Pos) éGPIOx_ANEN_ANEN_Pos 0 êGPIOx_ANEN_ANEN_Msk (0xffffU << GPIOx_ANEN_ANEN_Pos) öGPIO_FOUTSEL_FOUT1SEL_Pos 8 ÷GPIO_FOUTSEL_FOUT1SEL_Msk (0x1fU << GPIO_FOUTSEL_FOUT1SEL_Pos) øGPIO_FOUTSEL_FOUT1SEL_XTLF (0x0U << GPIO_FOUTSEL_FOUT1SEL_Pos) ùGPIO_FOUTSEL_FOUT1SEL_RCLP (0x1U << GPIO_FOUTSEL_FOUT1SEL_Pos) úGPIO_FOUTSEL_FOUT1SEL_RCHFD64 (0x2U << GPIO_FOUTSEL_FOUT1SEL_Pos) ûGPIO_FOUTSEL_FOUT1SEL_LSCLK (0x3U << GPIO_FOUTSEL_FOUT1SEL_Pos) üGPIO_FOUTSEL_FOUT1SEL_AHBCLKD64 (0x4U << GPIO_FOUTSEL_FOUT1SEL_Pos) ýGPIO_FOUTSEL_FOUT1SEL_RTC_TM (0x5U << GPIO_FOUTSEL_FOUT1SEL_Pos) þGPIO_FOUTSEL_FOUT1SEL_PLLHD64 (0x6U << GPIO_FOUTSEL_FOUT1SEL_Pos) ÿGPIO_FOUTSEL_FOUT1SEL_RTCCLK64Hz (0x7U << GPIO_FOUTSEL_FOUT1SEL_Pos) GPIO_FOUTSEL_FOUT1SEL_APBCLKD64 (0x8U << GPIO_FOUTSEL_FOUT1SEL_Pos) GPIO_FOUTSEL_FOUT1SEL_PLL_L (0x9U << GPIO_FOUTSEL_FOUT1SEL_Pos) GPIO_FOUTSEL_FOUT1SEL_RCMF (0xAU << GPIO_FOUTSEL_FOUT1SEL_Pos) GPIO_FOUTSEL_FOUT1SEL_RCHF (0xBU << GPIO_FOUTSEL_FOUT1SEL_Pos) GPIO_FOUTSEL_FOUT1SEL_XTHFD64 (0xCU << GPIO_FOUTSEL_FOUT1SEL_Pos)
GPIO_FOUTSEL_FOUT1SEL_ADCCLK (0xDU << GPIO_FOUTSEL_FOUT1SEL_Pos) GPIO_FOUTSEL_FOUT1SEL_PLL_H (0xEU << GPIO_FOUTSEL_FOUT1SEL_Pos) GPIO_FOUTSEL_FOUT1SEL_BOOST_FLAG (0x10U << GPIO_FOUTSEL_FOUT1SEL_Pos) GPIO_FOUTSEL_FOUT1SEL_AUTOTRIM_OUTPUT (0x11U << GPIO_FOUTSEL_FOUT1SEL_Pos) GPIO_FOUTSEL_FOUT0SEL_Pos 0 GPIO_FOUTSEL_FOUT0SEL_Msk (0x1fU << GPIO_FOUTSEL_FOUT0SEL_Pos) GPIO_FOUTSEL_FOUT0SEL_XTLF (0x0U << GPIO_FOUTSEL_FOUT0SEL_Pos) GPIO_FOUTSEL_FOUT0SEL_RCLP (0x1U << GPIO_FOUTSEL_FOUT0SEL_Pos) GPIO_FOUTSEL_FOUT0SEL_RCHFD64 (0x2U << GPIO_FOUTSEL_FOUT0SEL_Pos) GPIO_FOUTSEL_FOUT0SEL_LSCLK (0x3U << GPIO_FOUTSEL_FOUT0SEL_Pos) GPIO_FOUTSEL_FOUT0SEL_AHBCLKD64 (0x4U << GPIO_FOUTSEL_FOUT0SEL_Pos) GPIO_FOUTSEL_FOUT0SEL_RTC_TM (0x5U << GPIO_FOUTSEL_FOUT0SEL_Pos) GPIO_FOUTSEL_FOUT0SEL_PLLHD64 (0x6U << GPIO_FOUTSEL_FOUT0SEL_Pos) GPIO_FOUTSEL_FOUT0SEL_RTCCLK64Hz (0x7U << GPIO_FOUTSEL_FOUT0SEL_Pos) GPIO_FOUTSEL_FOUT0SEL_APBCLKD64 (0x8U << GPIO_FOUTSEL_FOUT0SEL_Pos) GPIO_FOUTSEL_FOUT0SEL_PLL_L (0x9U << GPIO_FOUTSEL_FOUT0SEL_Pos) GPIO_FOUTSEL_FOUT0SEL_RCMF (0xAU << GPIO_FOUTSEL_FOUT0SEL_Pos) GPIO_FOUTSEL_FOUT0SEL_RCHF (0xBU << GPIO_FOUTSEL_FOUT0SEL_Pos) GPIO_FOUTSEL_FOUT0SEL_XTHFD64 (0xCU << GPIO_FOUTSEL_FOUT0SEL_Pos) GPIO_FOUTSEL_FOUT0SEL_ADCCLK (0xDU << GPIO_FOUTSEL_FOUT0SEL_Pos) GPIO_FOUTSEL_FOUT0SEL_PLL_H (0xEU << GPIO_FOUTSEL_FOUT0SEL_Pos) GPIO_FOUTSEL_FOUT0SEL_BOOST_FLAG (0x10U << GPIO_FOUTSEL_FOUT0SEL_Pos) GPIO_IOMCR_IOMUXSEL_Pos 1 GPIO_IOMCR_IOMUXSEL_Msk (0x3U << GPIO_IOMCR_IOMUXSEL_Pos) GPIO_IOMCR_IOMUXSEL_PD6 (0x0U << GPIO_IOMCR_IOMUXSEL_Pos) ¡GPIO_IOMCR_IOMUXSEL_PD7 (0x1U << GPIO_IOMCR_IOMUXSEL_Pos) ¢GPIO_IOMCR_IOMUXSEL_PG2 (0x2U << GPIO_IOMCR_IOMUXSEL_Pos) £GPIO_IOMCR_IOMUXSEL_PG3 (0x3U << GPIO_IOMCR_IOMUXSEL_Pos) ¥GPIO_IOMCR_IOMUXEN_Pos 0 ¦GPIO_IOMCR_IOMCUEN_Msk (0x1U << GPIO_IOMCR_IOMUXEN_Pos) ¨GPIO_PINWKEN_WKISEL_Pos 31 ©GPIO_PINWKEN_WKISEL_Msk (0x1U << GPIO_PINWKEN_WKISEL_Pos) ªGPIO_PINWKEN_WKISEL_NMI (0x0U << GPIO_PINWKEN_WKISEL_Pos) «GPIO_PINWKEN_WKISEL_46 (0x1U << GPIO_PINWKEN_WKISEL_Pos) GPIO_PINWKEN_PINWKSEL_Pos 8 ®GPIO_PINWKEN_PINWKSEL_Msk (0xffffU << GPIO_PINWKEN_PINWKSEL_Pos) ¯GPIO_PINWKEN_PINWKSEL_FALLING 0 °GPIO_PINWKEN_PINWKSEL_RISING 1 ±GPIO_PINWKEN_PINWKSEL_BOTH 2 ³GPIO_PINWKEN_PINWKEN_Pos 0 ´GPIO_PINWKEN_PINWKEN_Msk (0xffU << GPIO_PINWKEN_PINWKEN_Pos) ¸GPIOH_DO_PHDO_Pos 0 ¹GPIOH_DO_PHDO_Msk (0xfU << GPIOH_DO_PHDO_Pos) ¼GPIOH_DIN_PHDIN_Pos 0 ½GPIOH_DIN_PHDIN_Msk (0xfU << GPIOH_DIN_PHDIN_Pos) ` U ..\Drivers\ ..\Core\Include\ fm33a0xxev_gpio.h FM33A0XXEV.h $
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..\Drivers\fm33a0xxev_gpio.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM GPIO_FCR_IN GPIO_FCR_OUT GPIO_FCR_DIG GPIO_FCR_ANA PGPIO_FCR_TypeDef ¾ ¼GPIO_OD_Dis GPIO_OD_En PGPIO_ODEN_TypeDef )÷GPIO_PU_Dis GPIO_PU_En PGPIO_PUEN_TypeDef U2²GPIO_IN_Dis GPIO_IN_En PGPIO_INEN_TypeDef ;íGPIO_HD_Dis GPIO_HD_En PGPIO_HD_TypeDef ËDªGPIO_ANEN_Dis GPIO_ANEN_En PGPIO_ANEN_TypeDef M* Pin f # PxFCR # PxODEN <# PxPUEN w# PxINEN ²# PGPIO_InitTypeDef CYÁBit_RESET Bit_SET PBitAction ¤bEXTI_RISING EXTI_FALLING EXTI_BOTH EXTIDISABLE PGPIOExtiEdge Òk Q R S __FM33A0XXEV_I2C_H I2C_SEND_STARTBIT(I2Cx) I2Cx_CR_SEN_Setable(I2Cx,ENABLE) I2C_SEND_RESTARTBIT(I2Cx) I2Cx_CR_RSEN_Setable(I2Cx,ENABLE) I2C_SEND_STOPBIT(I2Cx) I2Cx_CR_PEN_Setable(I2Cx,ENABLE) I2C_SEND_ACK_0(I2Cx) I2Cx_SR_ACKMO_Set(I2Cx,I2Cx_SR_ACKMO_RESET) I2C_SEND_ACK_1(I2Cx) I2Cx_SR_ACKMO_Set(I2Cx,I2Cx_SR_ACKMO_SET) !I2Cx_CFGR_AUTOEND_Pos 17 $I2Cx_CFGR_AUTOEND_Msk (0x1U << I2Cx_CFGR_AUTOEND_Pos) %I2Cx_CFGR_AUTOEND_AUTO (0x1U << I2Cx_CFGR_AUTOEND_Pos) &I2Cx_CFGR_AUTOEND_MANUAL (0x0U << I2Cx_CFGR_AUTOEND_Pos) (I2Cx_CFGR_MSP_DMAEN_Pos 16 +I2Cx_CFGR_MSP_DMAEN_Msk (0x1U << I2Cx_CFGR_MSP_DMAEN_Pos) /I2Cx_CFGR_TOEN_Pos 1 2I2Cx_CFGR_TOEN_Msk (0x1U << I2Cx_CFGR_TOEN_Pos) 3I2Cx_CFGR_TOEN_ENABLE (0x1U << I2Cx_CFGR_TOEN_Pos) 4I2Cx_CFGR_TOEN_DISABLE (0x0U << I2Cx_CFGR_TOEN_Pos) 6I2Cx_CFGR_MSPEN_Pos 0 7I2Cx_CFGR_MSPEN_Msk (0x1U << I2Cx_CFGR_MSPEN_Pos) 9I2Cx_CR_RCEN_Pos 3 <I2Cx_CR_RCEN_Msk (0x1U << I2Cx_CR_RCEN_Pos) >I2Cx_CR_PEN_Pos 2 ?I2Cx_CR_PEN_Msk (0x1U << I2Cx_CR_PEN_Pos) AI2Cx_CR_RSEN_Pos 1 BI2Cx_CR_RSEN_Msk (0x1U << I2Cx_CR_RSEN_Pos) DI2Cx_CR_SEN_Pos 0 EI2Cx_CR_SEN_Msk (0x1U << I2Cx_CR_SEN_Pos) GI2Cx_IER_WCOLE_Pos 6 JI2Cx_IER_WCOLE_Msk (0x1U << I2Cx_IER_WCOLE_Pos) NI2Cx_IER_TOE_Pos 5 QI2Cx_IER_TOE_Msk (0x1U << I2Cx_IER_TOE_Pos) SI2Cx_IER_SE_Pos 4 VI2Cx_IER_SE_Msk (0x1U << I2Cx_IER_SE_Pos) ZI2Cx_IER_PE_Pos 3 ]I2Cx_IER_PE_Msk (0x1U << I2Cx_IER_PE_Pos) aI2Cx_IER_NACKE_Pos 2 dI2Cx_IER_NACKE_Msk (0x1U << I2Cx_IER_NACKE_Pos) hI2Cx_IER_TXIE_Pos 1 kI2Cx_IER_TXIE_Msk (0x1U << I2Cx_IER_TXIE_Pos) oI2Cx_IER_RXIE_Pos 0 rI2Cx_IER_RXIE_Msk (0x1U << I2Cx_IER_RXIE_Pos) vI2Cx_ISR_WCOL_Pos 6 zI2Cx_ISR_WCOL_Msk (0x1U << I2Cx_ISR_WCOL_Pos) |I2Cx_ISR_TO_Pos 5 }I2Cx_ISR_TO_Msk (0x1U << I2Cx_ISR_TO_Pos) I2Cx_ISR_S_Pos 4 I2Cx_ISR_S_Msk (0x1U << I2Cx_ISR_S_Pos) I2Cx_ISR_P_Pos 3 I2Cx_ISR_P_Msk (0x1U << I2Cx_ISR_P_Pos) I2Cx_ISR_ACKSTA_Pos 2 I2Cx_ISR_ACKSTA_Msk (0x1U << I2Cx_ISR_ACKSTA_Pos) I2Cx_ISR_TXIF_Pos 1 I2Cx_ISR_TXIF_Msk (0x1U << I2Cx_ISR_TXIF_Pos) I2Cx_ISR_RXIF_Pos 0 I2Cx_ISR_RXIF_Msk (0x1U << I2Cx_ISR_RXIF_Pos) I2Cx_SR_BUSY_Pos 5 I2Cx_SR_BUSY_Msk (0x1U << I2Cx_SR_BUSY_Pos) I2Cx_SR_RW_Pos 4 I2Cx_SR_RW_Msk (0x1U << I2Cx_SR_RW_Pos) I2Cx_SR_BF_Pos 2 ¤I2Cx_SR_BF_Msk (0x1U << I2Cx_SR_BF_Pos) ¦I2Cx_SR_ACKMO_Pos 0 ¬I2Cx_SR_ACKMO_Msk (0x1U << I2Cx_SR_ACKMO_Pos) I2Cx_SR_ACKMO_RESET (0x0U << I2Cx_SR_ACKMO_Pos) ®I2Cx_SR_ACKMO_SET (0x1U << I2Cx_SR_ACKMO_Pos) °I2Cx_BRG_MSPBRGH_Pos 16 ±I2Cx_BRG_MSPBRGH_Msk (0x1ffU << I2Cx_BRG_MSPBRGH_Pos) ³I2Cx_BRG_MSPBRGL_Pos 0 ´I2Cx_BRG_MSPBRGL_Msk (0x1ffU << I2Cx_BRG_MSPBRGL_Pos) ¶I2Cx_BUF_WR_Pos 0 ·I2Cx_BUF_WR_Msk (0xffU << I2Cx_BUF_WR_Pos) ¹I2Cx_TIMING_SDAHD_Pos 0 »I2Cx_TIMING_SDAHD_Msk (0x1ffU << I2Cx_TIMING_SDAHD_Pos) ½I2Cx_TO_TIMEOUT_Pos 0 ¿I2Cx_TO_TIMEOUT_Msk (0xfffU << I2Cx_TO_TIMEOUT_Pos) ` T ..\Drivers\ ..\Core\Include\ fm33a0xxev_i2c.h FM33A0XXEV.h ¼
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..\Drivers\fm33a0xxev_i2c.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM U V W __FM33A0XXEV_IWDT_H IWDT_SERV_IWDTSERV_KEY 0x12345A5AU IWDT_SERV_IWDTSERV_Pos 0 IWDT_SERV_IWDTSERV_Msk (0xffffffffU << IWDT_SERV_IWDTSERV_Pos) IWDT_CFGR_IWDTOVP_Pos 0 "IWDT_CFGR_IWDTOVP_Msk (0x7U << IWDT_CFGR_IWDTOVP_Pos) #IWDT_IWDTOVP_125MS (0x0U << IWDT_CFGR_IWDTOVP_Pos) $IWDT_IWDTOVP_500MS (0x1U << IWDT_CFGR_IWDTOVP_Pos) %IWDT_IWDTOVP_2S (0x2U << IWDT_CFGR_IWDTOVP_Pos) &IWDT_IWDTOVP_8S (0x3U << IWDT_CFGR_IWDTOVP_Pos) (IWDT_IWDTOVP_4096S (0x4U << IWDT_CFGR_IWDTOVP_Pos) *IWDT_CNTR_IWDTCNT_Pos 0 +IWDT_CNTR_IWDTCNT_Msk (0xfffffU << IWDT_CNTR_IWDTCNT_Pos) ` U ..\Drivers\ ..\Core\Include\ fm33a0xxev_iwdt.h FM33A0XXEV.h ¼
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..\Drivers\fm33a0xxev_iwdt.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM Y Z [ __FM33A0XXEV_LPUART_H LPUARTx_MCTL_FOR9600 (0x00000552<<16) LPUARTx_MCTL_FOR4800 (0x00001EFB<<16) LPUARTx_MCTL_FOR2400 (0x000016DB<<16) LPUARTx_MCTL_FOR1200 (0x00000492<<16) LPUARTx_MCTL_FOR600 (0x000016D6<<16) LPUARTx_MCTL_FOR300 (0x00000842<<16) LPUARTx_CSR_BUSY_Pos 24 #LPUARTx_CSR_BUSY_Msk (0x1U << LPUARTx_CSR_BUSY_Pos) %LPUARTx_CSR_WKBYTECFG_Pos 19 (LPUARTx_CSR_WKBYTECFG_Msk (0x1U << LPUARTx_CSR_WKBYTECFG_Pos) *LPUARTx_CSR_RXEV_Pos 16 0LPUARTx_CSR_RXEV_Msk (0x3U << LPUARTx_CSR_RXEV_Pos) 1LPUARTx_CSR_RXEV_START (0x0U << LPUARTx_CSR_RXEV_Pos) 2LPUARTx_CSR_RXEV_1BYTE (0x1U << LPUARTx_CSR_RXEV_Pos) 3LPUARTx_CSR_RXEV_MATCH (0x2U << LPUARTx_CSR_RXEV_Pos) 4LPUARTx_CSR_RXEV_FALLING (0x3U << LPUARTx_CSR_RXEV_Pos) 6LPUARTx_CSR_IOSWAP_Pos 11 9LPUARTx_CSR_IOSWAP_Msk (0x1U << LPUARTx_CSR_IOSWAP_Pos) :LPUARTx_CSR_IOSWAP_DEFUALT (0x0U << LPUARTx_CSR_IOSWAP_Pos) ;LPUARTx_CSR_IOSWAP_SWAP (0x1U << LPUARTx_CSR_IOSWAP_Pos) >LPUARTx_CSR_DMATXIFCFG_Pos 10 ALPUARTx_CSR_DMATXIFCFG_Msk (0x1U << LPUARTx_CSR_DMATXIFCFG_Pos) ELPUARTx_CSR_BITORD_Pos 9 HLPUARTx_CSR_BITORD_Msk (0x1U << LPUARTx_CSR_BITORD_Pos) ILPUARTx_CSR_BITORD_LSB (0x0U << LPUARTx_CSR_BITORD_Pos) JLPUARTx_CSR_BITORD_MSB (0x1U << LPUARTx_CSR_BITORD_Pos) LLPUARTx_CSR_STOPCFG_Pos 8 OLPUARTx_CSR_STOPCFG_Msk (0x1U << LPUARTx_CSR_STOPCFG_Pos) PLPUARTx_CSR_STOPCFG_1STOP (0x0U << LPUARTx_CSR_STOPCFG_Pos) QLPUARTx_CSR_STOPCFG_2STOP (0x1U << LPUARTx_CSR_STOPCFG_Pos) SLPUARTx_CSR_PDSEL_Pos 6 YLPUARTx_CSR_PDSEL_Msk (0x3U << LPUARTx_CSR_PDSEL_Pos) ZLPUARTx_CSR_PDSEL_7BITS (0x0U << LPUARTx_CSR_PDSEL_Pos) [LPUARTx_CSR_PDSEL_8BITS (0x1U << LPUARTx_CSR_PDSEL_Pos) \LPUARTx_CSR_PDSEL_9BITS (0x2U << LPUARTx_CSR_PDSEL_Pos) ]LPUARTx_CSR_PDSEL_6BITS (0x3U << LPUARTx_CSR_PDSEL_Pos) _LPUARTx_CSR_PARITY_Pos 4 dLPUARTx_CSR_PARITY_Msk (0x3U << LPUARTx_CSR_PARITY_Pos) eLPUARTx_CSR_PARITY_NON (0x0U << LPUARTx_CSR_PARITY_Pos) fLPUARTx_CSR_PARITY_EVEN (0x1U << LPUARTx_CSR_PARITY_Pos) gLPUARTx_CSR_PARITY_ODD (0x2U << LPUARTx_CSR_PARITY_Pos) iLPUARTx_CSR_RXPOL_Pos 3 lLPUARTx_CSR_RXPOL_Msk (0x1U << LPUARTx_CSR_RXPOL_Pos) mLPUARTx_CSR_RXPOL_POS (0x0U << LPUARTx_CSR_RXPOL_Pos) nLPUARTx_CSR_RXPOL_NEG (0x1U << LPUARTx_CSR_RXPOL_Pos) pLPUARTx_CSR_TXPOL_Pos 2 sLPUARTx_CSR_TXPOL_Msk (0x1U << LPUARTx_CSR_TXPOL_Pos) tLPUARTx_CSR_TXPOL_POS (0x0U << LPUARTx_CSR_TXPOL_Pos) uLPUARTx_CSR_TXPOL_NEG (0x1U << LPUARTx_CSR_TXPOL_Pos) wLPUARTx_CSR_RXEN_Pos 1 xLPUARTx_CSR_RXEN_Msk (0x1U << LPUARTx_CSR_RXEN_Pos) zLPUARTx_CSR_TXEN_Pos 0 {LPUARTx_CSR_TXEN_Msk (0x1U << LPUARTx_CSR_TXEN_Pos) }LPUARTx_IER_RXEV_IE_Pos 12 ~LPUARTx_IER_RXEV_IE_Msk (0x1U << LPUARTx_IER_RXEV_IE_Pos) LPUARTx_IER_RXERR_IE_Pos 10 LPUARTx_IER_RXERR_IE_Msk (0x1U << LPUARTx_IER_RXERR_IE_Pos) LPUARTx_IER_RXBF_IE_Pos 8 LPUARTx_IER_RXBF_IE_Msk (0x1U << LPUARTx_IER_RXBF_IE_Pos) LPUARTx_IER_TXBE_IE_Pos 1 LPUARTx_IER_TXBE_IE_Msk (0x1U << LPUARTx_IER_TXBE_IE_Pos) LPUARTx_IER_TXSE_IE_Pos 0 LPUARTx_IER_TXSE_IE_Msk (0x1U << LPUARTx_IER_TXSE_IE_Pos) LPUARTx_ISR_RXEVF_Pos 24 LPUARTx_ISR_RXEVF_Msk (0x1U << LPUARTx_ISR_RXEVF_Pos) LPUARTx_ISR_TXOV_Pos 19 LPUARTx_ISR_TXOV_Msk (0x1U << LPUARTx_ISR_TXOV_Pos) LPUARTx_ISR_PERR_Pos 18 LPUARTx_ISR_PERR_Msk (0x1U << LPUARTx_ISR_PERR_Pos) LPUARTx_ISR_FERR_Pos 17 LPUARTx_ISR_FERR_Msk (0x1U << LPUARTx_ISR_FERR_Pos) LPUARTx_ISR_OERR_Pos 16 LPUARTx_ISR_OERR_Msk (0x1U << LPUARTx_ISR_OERR_Pos) LPUARTx_ISR_RXBF_Pos 8 LPUARTx_ISR_RXBF_Msk (0x1U << LPUARTx_ISR_RXBF_Pos) LPUARTx_ISR_TXBE_Pos 1 ¡LPUARTx_ISR_TXBE_Msk (0x1U << LPUARTx_ISR_TXBE_Pos) £LPUARTx_ISR_TXSE_Pos 0 ¤LPUARTx_ISR_TXSE_Msk (0x1U << LPUARTx_ISR_TXSE_Pos) ¦LPUARTx_BMR_MCTL_Pos 16 §LPUARTx_BMR_MCTL_Msk (0x1fffU << LPUARTx_BMR_MCTL_Pos) ©LPUARTx_BMR_BAUD_Pos 0 °LPUARTx_BMR_BAUD_Msk (0x7U << LPUARTx_BMR_BAUD_Pos) ±LPUARTx_BMR_BAUD_9600 (0x0U << LPUARTx_BMR_BAUD_Pos) ²LPUARTx_BMR_BAUD_4800 (0x1U << LPUARTx_BMR_BAUD_Pos) ³LPUARTx_BMR_BAUD_2400 (0x2U << LPUARTx_BMR_BAUD_Pos) ´LPUARTx_BMR_BAUD_1200 (0x3U << LPUARTx_BMR_BAUD_Pos) µLPUARTx_BMR_BAUD_600 (0x4U << LPUARTx_BMR_BAUD_Pos) ¶LPUARTx_BMR_BAUD_300 (0x5U << LPUARTx_BMR_BAUD_Pos) ¸LPUARTx_RXBUF_RXBUF_Pos 0 ¹LPUARTx_RXBUF_RXBUF_Msk (0x1ffU << LPUARTx_RXBUF_RXBUF_Pos) »LPUARTx_TXBUF_TXBUF_Pos 0 ¼LPUARTx_TXBUF_TXBUF_Msk (0x1ffU << LPUARTx_TXBUF_TXBUF_Pos) ¾LPUARTx_DMR_MATD_Pos 0 ÀLPUARTx_DMR_MATD_Msk (0x1ffU << LPUARTx_DMR_MATD_Pos) ` W ..\Drivers\ ..\Core\Include\ fm33a0xxev_lpuart.h FM33A0XXEV.h À
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..\Drivers\fm33a0xxev_lpuart.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM ] ^ _ __FM33A0XXEV_FLASH_H FLS_RDCR_WAIT_Pos 0 FLS_RDCR_WAIT_Msk (0x3U << FLS_RDCR_WAIT_Pos) FLS_RDCR_WAIT_0CYCLE (0x0U << FLS_RDCR_WAIT_Pos) FLS_RDCR_WAIT_1CYCLE (0x1U << FLS_RDCR_WAIT_Pos) !FLS_RDCR_WAIT_2CYCLE (0x2U << FLS_RDCR_WAIT_Pos) #FLS_PFCR_PRFTEN_Pos 0 &FLS_PFCR_PRFTEN_Msk (0x1U << FLS_PFCR_PRFTEN_Pos) *FLS_OPTBR_DBGCFGEN_Pos 31 +FLS_OPTBR_DBGCFGEN_Msk (0x1U << FLS_OPTBR_DBGCFGEN_Pos) -FLS_OPTBR_IF2LOCK_Pos 18 0FLS_OPTBR_IF2LOCK_Msk (0x1U << FLS_OPTBR_IF2LOCK_Pos) 2FLS_OPTBR_IF1LOCK_Pos 17 5FLS_OPTBR_IF1LOCK_Msk (0x1U << FLS_OPTBR_IF1LOCK_Pos) 7FLS_OPTBR_DFLSEN_Pos 10 :FLS_OPTBR_DFLSEN_Msk (0x1U << FLS_OPTBR_DFLSEN_Pos) >FLS_OPTBR_BTSEN_Pos 8 AFLS_OPTBR_BTSEN_Msk (0x3U << FLS_OPTBR_BTSEN_Pos) GFLS_OPTBR_ACLOCKEN_Pos 4 JFLS_OPTBR_ACLOCKEN_Msk (0x3U << FLS_OPTBR_ACLOCKEN_Pos) PFLS_OPTBR_DBRDPEN_Pos 0 SFLS_OPTBR_DBRDPEN_Msk (0xfU << FLS_OPTBR_DBRDPEN_Pos) YFLS_OPTBR_LOCK1_Pos 0 ZFLS_OPTBR_LOCK1_Msk (0xffffffffU << FLS_OPTBR_LOCK1_Pos) \FLS_OPTBR_LOCK2_Pos 0 ]FLS_OPTBR_LOCK2_Msk (0xffffffffU << FLS_OPTBR_LOCK2_Pos) _FLS_OPTBR_LOCK3_Pos 0 `FLS_OPTBR_LOCK3_Msk (0xffffffffU << FLS_OPTBR_LOCK3_Pos) bFLS_OPTBR_LOCK4_Pos 0 cFLS_OPTBR_LOCK4_Msk (0xffffffffU << FLS_OPTBR_LOCK4_Pos) eFLS_EPCR_ERTYPE_Pos 8 iFLS_EPCR_ERTYPE_Msk (0x3U << FLS_EPCR_ERTYPE_Pos) jFLS_EPCR_ERTYPE_PAGE (0x0U << FLS_EPCR_ERTYPE_Pos) kFLS_EPCR_ERTYPE_SECTOR (0x1U << FLS_EPCR_ERTYPE_Pos) lFLS_EPCR_ERTYPE_CHIP_ERASE (0x2U << FLS_EPCR_ERTYPE_Pos) nFLS_EPCR_PREQ_Pos 1 pFLS_EPCR_PREQ_Msk (0x1U << FLS_EPCR_PREQ_Pos) rFLS_EPCR_EREQ_Pos 0 tFLS_EPCR_EREQ_Msk (0x1U << FLS_EPCR_EREQ_Pos) vFLS_KEY_KEY_Pos 0 wFLS_KEY_KEY_Msk (0xffffffffU << FLS_KEY_KEY_Pos) yFLS_IER_OTPIE_Pos 11 zFLS_IER_OTPIE_Msk (0x1U << FLS_IER_OTPIE_Pos) |FLS_IER_AUTHIE_Pos 10 }FLS_IER_AUTHIE_Msk (0x1U << FLS_IER_AUTHIE_Pos) FLS_IER_KEYIE_Pos 9 FLS_IER_KEYIE_Msk (0x1U << FLS_IER_KEYIE_Pos) FLS_IER_CKIE_Pos 8 FLS_IER_CKIE_Msk (0x1U << FLS_IER_CKIE_Pos)
FLS_IER_PRDIE_Pos 1 FLS_IER_PRDIE_Msk (0x1U << FLS_IER_PRDIE_Pos) FLS_IER_ERDIE_Pos 0 FLS_IER_ERDIE_Msk (0x1U << FLS_IER_ERDIE_Pos) FLS_ISR_KEYSTA_Pos 17 FLS_ISR_KEYSTA_Msk (0x7U << FLS_ISR_KEYSTA_Pos) FLS_ISR_KEYSTA_KEY_NONE_PROTECT (0x0U << FLS_ISR_KEYSTA_Pos) FLS_ISR_KEYSTA_CHIP_ERASE (0x1U << FLS_ISR_KEYSTA_Pos) FLS_ISR_KEYSTA_SECTOR_ERASE (0x2U << FLS_ISR_KEYSTA_Pos) FLS_ISR_KEYSTA_PROGRAM (0x3U << FLS_ISR_KEYSTA_Pos) FLS_ISR_KEYSTA_KEY_ERR_PROTECT (0x4U << FLS_ISR_KEYSTA_Pos) FLS_ISR_BTSF_Pos 16 FLS_ISR_BTSF_Msk (0x1U << FLS_ISR_BTSF_Pos) FLS_ISR_BTSF_START_0000H (0x0U << FLS_ISR_BTSF_Pos) FLS_ISR_BTSF_START_2000H (0x1U << FLS_ISR_BTSF_Pos) FLS_ISR_OTPERR_Pos 11 £FLS_ISR_OTPERR_Msk (0x1U << FLS_ISR_OTPERR_Pos) ¥FLS_ISR_AUTHERR_Pos 10 ¨FLS_ISR_AUTHERR_Msk (0x1U << FLS_ISR_AUTHERR_Pos) ªFLS_ISR_KEYERR_Pos 9 «FLS_ISR_KEYERR_Msk (0x1U << FLS_ISR_KEYERR_Pos) FLS_ISR_CKERR_Pos 8 ®FLS_ISR_CKERR_Msk (0x1U << FLS_ISR_CKERR_Pos) °FLS_ISR_PRD_Pos 1 ±FLS_ISR_PRD_Msk (0x1U << FLS_ISR_PRD_Pos) ³FLS_ISR_ERD_Pos 0 ´FLS_ISR_ERD_Msk (0x1U << FLS_ISR_ERD_Pos) ` V ..\Drivers\ ..\Core\Include\ fm33a0xxev_flash.h FM33A0XXEV.h À
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..\Drivers\fm33a0xxev_flash.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM a b c __FM33A0XXEV_PMU_H PMU_CR_LDO15EN_Pos 17 #PMU_CR_LDO15EN_Msk (0x1U << PMU_CR_LDO15EN_Pos) %PMU_CR_LDO15EN_B_Pos 16 &PMU_CR_LDO15EN_B_Msk (0x1U << PMU_CR_LDO15EN_B_Pos) (PMU_CR_WKFSEL_Pos 10 -PMU_CR_WKFSEL_Msk (0x3U << PMU_CR_WKFSEL_Pos) .PMU_CR_WKFSEL_RCHF_8M (0x0U << PMU_CR_WKFSEL_Pos) /PMU_CR_WKFSEL_RCHF_16M (0x1U << PMU_CR_WKFSEL_Pos) 0PMU_CR_WKFSEL_RCHF_24M (0x2U << PMU_CR_WKFSEL_Pos) 1PMU_CR_WKFSEL_RCHF_32M (0x3U << PMU_CR_WKFSEL_Pos) 3PMU_CR_SLPDP_Pos 9 8PMU_CR_SLPDP_Msk (0x1U << PMU_CR_SLPDP_Pos) 9PMU_CR_SLPDP_DEEPSLEEP (0x1U << PMU_CR_SLPDP_Pos) :PMU_CR_SLPDP_SLEEP (0x0U << PMU_CR_SLPDP_Pos) <PMU_CR_CVS_Pos 8 @PMU_CR_CVS_Msk (0x1U << PMU_CR_CVS_Pos) APMU_CR_CVS_DISABLE (0x0U << PMU_CR_CVS_Pos) BPMU_CR_CVS_ENABLE (0x1U << PMU_CR_CVS_Pos) DPMU_CR_PMOD_Pos 0 IPMU_CR_PMOD_Msk (0x3U << PMU_CR_PMOD_Pos) JPMU_CR_PMOD_ACTIVE (0x0U << PMU_CR_PMOD_Pos) KPMU_CR_PMOD_LPRUN (0x1U << PMU_CR_PMOD_Pos) LPMU_CR_PMOD_SLEEP (0x2U << PMU_CR_PMOD_Pos) NPMU_WKTR_STPCLR_Pos 2 QPMU_WKTR_STPCLR_Msk (0x1U << PMU_WKTR_STPCLR_Pos) RPMU_WKTR_STPCLR_SYN (0x0U << PMU_WKTR_STPCLR_Pos) SPMU_WKTR_STPCLR_ASY (0x1U << PMU_WKTR_STPCLR_Pos) UPMU_WKTR_T1A_Pos 0 [PMU_WKTR_T1A_Msk (0x3U << PMU_WKTR_T1A_Pos) \PMU_WKTR_T1A_0US (0x0U << PMU_WKTR_T1A_Pos) ]PMU_WKTR_T1A_2US (0x1U << PMU_WKTR_T1A_Pos) ^PMU_WKTR_T1A_4US (0x2U << PMU_WKTR_T1A_Pos) _PMU_WKTR_T1A_8US (0x3U << PMU_WKTR_T1A_Pos) aPMU_WKFR_ADCWKF_Pos 31 bPMU_WKFR_ADCWKF_Msk (0x1U << PMU_WKFR_ADCWKF_Pos) dPMU_WKFR_RTCWKF_Pos 28 ePMU_WKFR_RTCWKF_Msk (0x1U << PMU_WKFR_RTCWKF_Pos) gPMU_WKFR_SVDWKF_Pos 27 hPMU_WKFR_SVDWKF_Msk (0x1U << PMU_WKFR_SVDWKF_Pos) jPMU_WKFR_LFDETWKF_Pos 26 kPMU_WKFR_LFDETWKF_Msk (0x1U << PMU_WKFR_LFDETWKF_Pos) mPMU_WKFR_IOWKF_Pos 24 nPMU_WKFR_IOWKF_Msk (0x1U << PMU_WKFR_IOWKF_Pos) pPMU_WKFR_LPU1WKF_Pos 21 qPMU_WKFR_LPU1WKF_Msk (0x1U << PMU_WKFR_LPU1WKF_Pos) sPMU_WKFR_LPU0WKF_Pos 20 tPMU_WKFR_LPU0WKF_Msk (0x1U << PMU_WKFR_LPU0WKF_Pos) vPMU_WKFR_COMP_OOWF_Pos 19 wPMU_WKFR_COMP_OOWF_Msk (0x1U << PMU_WKFR_COMP_OOWF_Pos) yPMU_WKFR_COMP_WINF_Pos 18 zPMU_WKFR_COMP_WINF_Msk (0x1U << PMU_WKFR_COMP_WINF_Pos) |PMU_WKFR_COMP2WKF_Pos 17 }PMU_WKFR_COMP2WKF_Msk (0x1U << PMU_WKFR_COMP2WKF_Pos) PMU_WKFR_COMP1WKF_Pos 16 PMU_WKFR_COMP1WKF_Msk (0x1U << PMU_WKFR_COMP1WKF_Pos) PMU_WKFR_LPTWKF_Pos 10 PMU_WKFR_LPTWKF_Msk (0x1U << PMU_WKFR_LPTWKF_Pos)
PMU_WKFR_BSTWKF_Pos 9 PMU_WKFR_BSTWKF_Msk (0x1U << PMU_WKFR_BSTWKF_Pos) PMU_WKFR_DBGWKF_Pos 8 PMU_WKFR_DBGWKF_Msk (0x1U << PMU_WKFR_DBGWKF_Pos) PMU_IER_SLPEIE_Pos 1 PMU_IER_SLPEIE_Msk (0x1U << PMU_IER_SLPEIE_Pos) PMU_IER_RTCEIE_Pos 0 PMU_IER_RTCEIE_Msk (0x1U << PMU_IER_RTCEIE_Pos) PMU_ISR_SLPEIF_Pos 1 PMU_ISR_SLPEIF_Msk (0x1U << PMU_ISR_SLPEIF_Pos) PMU_ISR_RTCEIF_Pos 0 ¢PMU_ISR_RTCEIF_Msk (0x1U << PMU_ISR_RTCEIF_Pos) ` T ..\Drivers\ ..\Core\Include\ fm33a0xxev_pmu.h FM33A0XXEV.h $
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..\Drivers\fm33a0xxev_pmu.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM * PMOD f # SLPDP f # CVS # SCR f # TIA f # PPMU_SleepCfg_InitTypeDef ½ e f g __FM33A0XXEV_CMU_H HXVAR(object,addr) (*((object *) (addr))) const_rchf_Trim8 HXVAR( uint32_t, 0x1FFFFB40 ) const_rchf_Trim16 HXVAR( uint32_t, 0x1FFFFB3C ) const_rchf_Trim24 HXVAR( uint32_t, 0x1FFFFB38 ) const_rchf_Trim32 HXVAR( uint32_t, 0x1FFFFB34) !__XTHF_CLOCK (12000000) RCMU_SYSCLKCR_SLP_ENEXTI_Pos 25 SCMU_SYSCLKCR_SLP_ENEXTI_Msk (0x1U << CMU_SYSCLKCR_SLP_ENEXTI_Pos) UCMU_SYSCLKCR_APBPRES_Pos 16 [CMU_SYSCLKCR_APBPRES_Msk (0x7U << CMU_SYSCLKCR_APBPRES_Pos) \CMU_SYSCLKCR_APBPRES_DIV1 (0x0U << CMU_SYSCLKCR_APBPRES_Pos) ]CMU_SYSCLKCR_APBPRES_DIV2 (0x4U << CMU_SYSCLKCR_APBPRES_Pos) ^CMU_SYSCLKCR_APBPRES_DIV4 (0x5U << CMU_SYSCLKCR_APBPRES_Pos) _CMU_SYSCLKCR_APBPRES_DIV8 (0x6U << CMU_SYSCLKCR_APBPRES_Pos) `CMU_SYSCLKCR_APBPRES_DIV16 (0x7U << CMU_SYSCLKCR_APBPRES_Pos) bCMU_SYSCLKCR_AHBPRES_Pos 8 hCMU_SYSCLKCR_AHBPRES_Msk (0x7U << CMU_SYSCLKCR_AHBPRES_Pos) iCMU_SYSCLKCR_AHBPRES_DIV1 (0x0U << CMU_SYSCLKCR_AHBPRES_Pos) jCMU_SYSCLKCR_AHBPRES_DIV2 (0x4U << CMU_SYSCLKCR_AHBPRES_Pos) kCMU_SYSCLKCR_AHBPRES_DIV4 (0x5U << CMU_SYSCLKCR_AHBPRES_Pos) lCMU_SYSCLKCR_AHBPRES_DIV8 (0x6U << CMU_SYSCLKCR_AHBPRES_Pos) mCMU_SYSCLKCR_AHBPRES_DIV16 (0x7U << CMU_SYSCLKCR_AHBPRES_Pos) oCMU_SYSCLKCR_STCLKSEL_Pos 6 tCMU_SYSCLKCR_STCLKSEL_Msk (0x3U << CMU_SYSCLKCR_STCLKSEL_Pos) uCMU_SYSCLKCR_STCLKSEL_SCLK (0x0U << CMU_SYSCLKCR_STCLKSEL_Pos) vCMU_SYSCLKCR_STCLKSEL_LSCLK (0x1U << CMU_SYSCLKCR_STCLKSEL_Pos) wCMU_SYSCLKCR_STCLKSEL_RC4M (0x2U << CMU_SYSCLKCR_STCLKSEL_Pos) xCMU_SYSCLKCR_STCLKSEL_SYSCLK (0x3U << CMU_SYSCLKCR_STCLKSEL_Pos) zCMU_SYSCLKCR_SYSCLKSEL_Pos 0 {CMU_SYSCLKCR_SYSCLKSEL_Msk (0x7U << CMU_SYSCLKCR_SYSCLKSEL_Pos) |CMU_SYSCLKCR_SYSCLKSEL_RCHF (0x0U << CMU_SYSCLKCR_SYSCLKSEL_Pos) }CMU_SYSCLKCR_SYSCLKSEL_XTHF (0x1U << CMU_SYSCLKCR_SYSCLKSEL_Pos) ~CMU_SYSCLKCR_SYSCLKSEL_PLL_H (0x2U << CMU_SYSCLKCR_SYSCLKSEL_Pos) CMU_SYSCLKCR_SYSCLKSEL_LSCLK (0x3U << CMU_SYSCLKCR_SYSCLKSEL_Pos) CMU_RCHFCR_FSEL_Pos 16 CMU_RCHFCR_FSEL_Msk (0xfU << CMU_RCHFCR_FSEL_Pos) CMU_RCHFCR_FSEL_8MHZ (0x0U << CMU_RCHFCR_FSEL_Pos) CMU_RCHFCR_FSEL_16MHZ (0x1U << CMU_RCHFCR_FSEL_Pos) CMU_RCHFCR_FSEL_24MHZ (0x2U << CMU_RCHFCR_FSEL_Pos) CMU_RCHFCR_FSEL_32MHZ (0x3U << CMU_RCHFCR_FSEL_Pos) CMU_RCHFCR_RCHFEN_Pos 0 CMU_RCHFCR_RCHFEN_Msk (0x1U << CMU_RCHFCR_RCHFEN_Pos) CMU_RCHFTR_RCHFTRIM_Pos 0 CMU_RCHFTR_RCHFTRIM_Msk (0xffU << CMU_RCHFTR_RCHFTRIM_Pos) CMU_PLLLCR_PLLDB_Pos 16 CMU_PLLLCR_PLLDB_Msk (0x3ffU << CMU_PLLLCR_PLLDB_Pos) CMU_PLLLCR_LOCKED_Pos 7 CMU_PLLLCR_LOCKED_Msk (0x1U << CMU_PLLLCR_LOCKED_Pos) CMU_PLLLCR_PLLEN_Pos 0 £CMU_PLLLCR_PLLEN_Msk (0x1U << CMU_PLLLCR_PLLEN_Pos) ¥CMU_PLLHCR_PLLHDB_Pos 16 ¨CMU_PLLHCR_PLLHDB_Msk (0x3ffU << CMU_PLLHCR_PLLHDB_Pos) ©CMU_PLLHCR_PLLHDB_X32 (0x1fU << CMU_PLLHCR_PLLHDB_Pos) ªCMU_PLLHCR_PLLHDB_X48 (0x2fU << CMU_PLLHCR_PLLHDB_Pos) «CMU_PLLHCR_PLLHDB_X64 (0x3fU << CMU_PLLHCR_PLLHDB_Pos) CMU_PLLHCR_LOCKED_Pos 7 °CMU_PLLHCR_LOCKED_Msk (0x1U << CMU_PLLHCR_LOCKED_Pos) ²CMU_PLLHCR_REFPRSC_Pos 4 »CMU_PLLHCR_REFPRSC_Msk (0x7U << CMU_PLLHCR_REFPRSC_Pos) ¼CMU_PLLHCR_REFPRSC_DIV1 (0x0U << CMU_PLLHCR_REFPRSC_Pos) ½CMU_PLLHCR_REFPRSC_DIV2 (0x1U << CMU_PLLHCR_REFPRSC_Pos) ¾CMU_PLLHCR_REFPRSC_DIV4 (0x2U << CMU_PLLHCR_REFPRSC_Pos) ¿CMU_PLLHCR_REFPRSC_DIV8 (0x3U << CMU_PLLHCR_REFPRSC_Pos) ÀCMU_PLLHCR_REFPRSC_DIV12 (0x4U << CMU_PLLHCR_REFPRSC_Pos) ÁCMU_PLLHCR_REFPRSC_DIV16 (0x5U << CMU_PLLHCR_REFPRSC_Pos) ÂCMU_PLLHCR_REFPRSC_DIV24 (0x6U << CMU_PLLHCR_REFPRSC_Pos) ÃCMU_PLLHCR_REFPRSC_DIV32 (0x7U << CMU_PLLHCR_REFPRSC_Pos) ÅCMU_PLLHCR_OSEL_Pos 3 ÈCMU_PLLHCR_OSEL_Msk (0x1U << CMU_PLLHCR_OSEL_Pos) ÉCMU_PLLHCR_OSEL_X1 (0x0U << CMU_PLLHCR_OSEL_Pos) ÊCMU_PLLHCR_OSEL_X2 (0x1U << CMU_PLLHCR_OSEL_Pos) ÌCMU_PLLHCR_INSEL_Pos 1 ÏCMU_PLLHCR_INSEL_Msk (0x1U << CMU_PLLHCR_INSEL_Pos) ÐCMU_PLLHCR_INSEL_RCHF (0x0U << CMU_PLLHCR_INSEL_Pos) ÑCMU_PLLHCR_INSEL_XTHF (0x1U << CMU_PLLHCR_INSEL_Pos) ÓCMU_PLLHCR_EN_Pos 0 ÖCMU_PLLHCR_EN_Msk (0x1U << CMU_PLLHCR_EN_Pos) ØCMU_XTHFCR_XTHF_CFG_Pos 8 ÛCMU_XTHFCR_XTHF_CFG_Msk (0x7U << CMU_XTHFCR_XTHF_CFG_Pos) ÜCMU_XTHFCR_XTHF_CFG_MIN (0x0U << CMU_XTHFCR_XTHF_CFG_Pos) ÝCMU_XTHFCR_XTHF_CFG_MAX (0x7U << CMU_XTHFCR_XTHF_CFG_Pos) ßCMU_XTHFCR_XTHFEN_Pos 0 âCMU_XTHFCR_XTHFEN_Msk (0x1U << CMU_XTHFCR_XTHFEN_Pos) æCMU_IER_SYSCSE_IE_Pos 1 çCMU_IER_SYSCSE_IE_Msk (0x1U << CMU_IER_SYSCSE_IE_Pos) éCMU_IER_HFDET_IE_Pos 0 êCMU_IER_HFDET_IE_Msk (0x1U << CMU_IER_HFDET_IE_Pos) íCMU_ISR_HFDETO_Pos 8 ðCMU_ISR_HFDETO_Msk (0x1U << CMU_ISR_HFDETO_Pos) òCMU_ISR_SYSCSE_IF_Pos 1 óCMU_ISR_SYSCSE_IF_Msk (0x1U << CMU_ISR_SYSCSE_IF_Pos) õCMU_ISR_HFDET_IF_Pos 0 öCMU_ISR_HFDET_IF_Msk (0x1U << CMU_ISR_HFDET_IF_Pos) øCMU_PCLKCR1_COMP_PCE_Pos 9 ùCMU_PCLKCR1_COMP_PCE_Msk (0x1U << CMU_PCLKCR1_COMP_PCE_Pos) ûCMU_PCLKCR1_SVD_PCE_Pos 8 üCMU_PCLKCR1_SVD_PCE_Msk (0x1U << CMU_PCLKCR1_SVD_PCE_Pos) þCMU_PCLKCR1_PAD_PCE_Pos 7 ÿCMU_PCLKCR1_PAD_PCE_Msk (0x1U << CMU_PCLKCR1_PAD_PCE_Pos) CMU_PCLKCR1_ANAC_PCE_Pos 6 CMU_PCLKCR1_ANAC_PCE_Msk (0x1U << CMU_PCLKCR1_ANAC_PCE_Pos)
CMU_PCLKCR1_IWDT_PCE_Pos 5 CMU_PCLKCR1_IWDT_PCE_Msk (0x1U << CMU_PCLKCR1_IWDT_PCE_Pos) CMU_PCLKCR1_SCU_PCE_Pos 4 CMU_PCLKCR1_SCU_PCE_Msk (0x1U << CMU_PCLKCR1_SCU_PCE_Pos) CMU_PCLKCR1_PMU_PCE_Pos 3 CMU_PCLKCR1_PMU_PCE_Msk (0x1U << CMU_PCLKCR1_PMU_PCE_Pos) CMU_PCLKCR1_RTC_PCE_Pos 2 CMU_PCLKCR1_RTC_PCE_Msk (0x1U << CMU_PCLKCR1_RTC_PCE_Pos) CMU_PCLKCR1_LPT_PCE_Pos 0 CMU_PCLKCR1_LPT_PCE_Msk (0x1U << CMU_PCLKCR1_LPT_PCE_Pos) CMU_PCLKCR2_PAE_PCE_Pos 17 CMU_PCLKCR2_PAE_PCE_Msk (0x1U << CMU_PCLKCR2_PAE_PCE_Pos) CMU_PCLKCR2_SHA_PCE_Pos 16 CMU_PCLKCR2_SHA_PCE_Msk (0x1U << CMU_PCLKCR2_SHA_PCE_Pos) CMU_PCLKCR2_CIC_PCE_Pos 8 CMU_PCLKCR2_CIC_PCE_Msk (0x1U << CMU_PCLKCR2_CIC_PCE_Pos) CMU_PCLKCR2_WWDT_PCE_Pos 7 CMU_PCLKCR2_WWDT_PCE_Msk (0x1U << CMU_PCLKCR2_WWDT_PCE_Pos) CMU_PCLKCR2_RAMBIST_PCE_Pos 6 ¡CMU_PCLKCR2_RAMBIST_PCE_Msk (0x1U << CMU_PCLKCR2_RAMBIST_PCE_Pos) £CMU_PCLKCR2_NVM_PCE_Pos 5 ¤CMU_PCLKCR2_NVM_PCE_Msk (0x1U << CMU_PCLKCR2_NVM_PCE_Pos) ¦CMU_PCLKCR2_DMA_PCE_Pos 4 §CMU_PCLKCR2_DMA_PCE_Msk (0x1U << CMU_PCLKCR2_DMA_PCE_Pos) ©CMU_PCLKCR2_LCD_PCE_Pos 3 ªCMU_PCLKCR2_LCD_PCE_Msk (0x1U << CMU_PCLKCR2_LCD_PCE_Pos) ¬CMU_PCLKCR2_AES_PCE_Pos 2 CMU_PCLKCR2_AES_PCE_Msk (0x1U << CMU_PCLKCR2_AES_PCE_Pos) ¯CMU_PCLKCR2_TRNG_PCE_Pos 1 °CMU_PCLKCR2_TRNG_PCE_Msk (0x1U << CMU_PCLKCR2_TRNG_PCE_Pos) ²CMU_PCLKCR2_CRC_PCE_Pos 0 ³CMU_PCLKCR2_CRC_PCE_Msk (0x1U << CMU_PCLKCR2_CRC_PCE_Pos) µCMU_PCLKCR3_I2C1_PCE_Pos 25 ¶CMU_PCLKCR3_I2C1_PCE_Msk (0x1U << CMU_PCLKCR3_I2C1_PCE_Pos) ¸CMU_PCLKCR3_I2C0_PCE_Pos 24 ¹CMU_PCLKCR3_I2C0_PCE_Msk (0x1U << CMU_PCLKCR3_I2C0_PCE_Pos) »CMU_PCLKCR3_LPUART1_PCE_Pos 18 ¼CMU_PCLKCR3_LPUART1_PCE_Msk (0x1U << CMU_PCLKCR3_LPUART1_PCE_Pos) ¾CMU_PCLKCR3_U7816_PCE_Pos 16 ¿CMU_PCLKCR3_U7816_PCE_Msk (0x1U << CMU_PCLKCR3_U7816_PCE_Pos) ÁCMU_PCLKCR3_LPUART0_PCE_Pos 15 ÂCMU_PCLKCR3_LPUART0_PCE_Msk (0x1U << CMU_PCLKCR3_LPUART0_PCE_Pos) ÄCMU_PCLKCR3_UICR_PCE_Pos 14 ÅCMU_PCLKCR3_UICR_PCE_Msk (0x1U << CMU_PCLKCR3_UICR_PCE_Pos) ÇCMU_PCLKCR3_UART5_PCE_Pos 13 ÈCMU_PCLKCR3_UART5_PCE_Msk (0x1U << CMU_PCLKCR3_UART5_PCE_Pos) ÊCMU_PCLKCR3_UART4_PCE_Pos 12 ËCMU_PCLKCR3_UART4_PCE_Msk (0x1U << CMU_PCLKCR3_UART4_PCE_Pos) ÍCMU_PCLKCR3_UART3_PCE_Pos 11 ÎCMU_PCLKCR3_UART3_PCE_Msk (0x1U << CMU_PCLKCR3_UART3_PCE_Pos) ÐCMU_PCLKCR3_UART2_PCE_Pos 10 ÑCMU_PCLKCR3_UART2_PCE_Msk (0x1U << CMU_PCLKCR3_UART2_PCE_Pos) ÓCMU_PCLKCR3_UART1_PCE_Pos 9 ÔCMU_PCLKCR3_UART1_PCE_Msk (0x1U << CMU_PCLKCR3_UART1_PCE_Pos) ÖCMU_PCLKCR3_UART0_PCE_Pos 8 ×CMU_PCLKCR3_UART0_PCE_Msk (0x1U << CMU_PCLKCR3_UART0_PCE_Pos) ÙCMU_PCLKCR3_QSPI_PCE_Pos 7 ÚCMU_PCLKCR3_QSPI_PCE_Msk (0x1U << CMU_PCLKCR3_QSPI_PCE_Pos) ÜCMU_PCLKCR3_SPI4_PCE_Pos 4 ÝCMU_PCLKCR3_SPI4_PCE_Msk (0x1U << CMU_PCLKCR3_SPI4_PCE_Pos) ßCMU_PCLKCR3_SPI3_PCE_Pos 3 àCMU_PCLKCR3_SPI3_PCE_Msk (0x1U << CMU_PCLKCR3_SPI3_PCE_Pos) âCMU_PCLKCR3_SPI2_PCE_Pos 2 ãCMU_PCLKCR3_SPI2_PCE_Msk (0x1U << CMU_PCLKCR3_SPI2_PCE_Pos) åCMU_PCLKCR3_SPI1_PCE_Pos 1 æCMU_PCLKCR3_SPI1_PCE_Msk (0x1U << CMU_PCLKCR3_SPI1_PCE_Pos) èCMU_PCLKCR3_SPI0_PCE_Pos 0 éCMU_PCLKCR3_SPI0_PCE_Msk (0x1U << CMU_PCLKCR3_SPI0_PCE_Pos) ëCMU_PCLKCR4_ET4_PCE_Pos 6 ìCMU_PCLKCR4_ET4_PCE_Msk (0x1U << CMU_PCLKCR4_ET4_PCE_Pos) îCMU_PCLKCR4_ET3_PCE_Pos 5 ïCMU_PCLKCR4_ET3_PCE_Msk (0x1U << CMU_PCLKCR4_ET3_PCE_Pos) ñCMU_PCLKCR4_ET2_PCE_Pos 4 òCMU_PCLKCR4_ET2_PCE_Msk (0x1U << CMU_PCLKCR4_ET2_PCE_Pos) ôCMU_PCLKCR4_ET1_PCE_Pos 3 õCMU_PCLKCR4_ET1_PCE_Msk (0x1U << CMU_PCLKCR4_ET1_PCE_Pos) ÷CMU_PCLKCR4_BT2_PCE_Pos 2 øCMU_PCLKCR4_BT2_PCE_Msk (0x1U << CMU_PCLKCR4_BT2_PCE_Pos) úCMU_PCLKCR4_BT1_PCE_Pos 1 ûCMU_PCLKCR4_BT1_PCE_Msk (0x1U << CMU_PCLKCR4_BT1_PCE_Pos) ýCMU_PCLKCR4_BSTIM_PCE_Pos 0 þCMU_PCLKCR4_BSTIM_PCE_Msk (0x1U << CMU_PCLKCR4_BSTIM_PCE_Pos) CMU_OPCCR1_EXTICKE_Pos 31 CMU_OPCCR1_EXTICKE_Msk (0x1U << CMU_OPCCR1_EXTICKE_Pos) CMU_OPCCR1_EXTICKSEL_Pos 30 CMU_OPCCR1_EXTICKSEL_Msk (0x1U << CMU_OPCCR1_EXTICKSEL_Pos)
CMU_OPCCR1_EXTICKSEL_LSCLK (0x1U << CMU_OPCCR1_EXTICKSEL_Pos) CMU_OPCCR1_EXTICKSEL_HCLK (0x0U << CMU_OPCCR1_EXTICKSEL_Pos) CMU_OPCCR1_LPUART1CKE_Pos 29 CMU_OPCCR1_LPUART1CKE_Msk (0x1U << CMU_OPCCR1_LPUART1CKE_Pos) CMU_OPCCR1_LPUART0CKE_Pos 28 CMU_OPCCR1_LPUART0CKE_Msk (0x1U << CMU_OPCCR1_LPUART0CKE_Pos) CMU_OPCCR1_LPUART1CKS_Pos 26 CMU_OPCCR1_LPUART1CKS_Msk (0x3U << CMU_OPCCR1_LPUART1CKS_Pos) CMU_OPCCR1_LPUART1CKS_LSCLK (0x0U << CMU_OPCCR1_LPUART1CKS_Pos) CMU_OPCCR1_LPUART1CKS_RCHF (0x1U << CMU_OPCCR1_LPUART1CKS_Pos) CMU_OPCCR1_LPUART0CKS_Pos 24 CMU_OPCCR1_LPUART0CKS_Msk (0x3U << CMU_OPCCR1_LPUART0CKS_Pos) CMU_OPCCR1_LPUART0CKS_LSCLK (0x0U << CMU_OPCCR1_LPUART0CKS_Pos) CMU_OPCCR1_LPUART0CKS_RCHF (0x1U << CMU_OPCCR1_LPUART0CKS_Pos) CMU_OPCCR1_I2C1CKE_Pos 21 ¡CMU_OPCCR1_I2C1CKE_Msk (0x1U << CMU_OPCCR1_I2C1CKE_Pos) £CMU_OPCCR1_I2C0CKE_Pos 20 ¤CMU_OPCCR1_I2C0CKE_Msk (0x1U << CMU_OPCCR1_I2C0CKE_Pos) ¦CMU_OPCCR1_I2C1CKS_Pos 18 «CMU_OPCCR1_I2C1CKS_Msk (0x3U << CMU_OPCCR1_I2C1CKS_Pos) ¬CMU_OPCCR1_I2C1CKS_APBCLK (0x0U << CMU_OPCCR1_I2C1CKS_Pos) CMU_OPCCR1_I2C1CKS_RCHF (0x1U << CMU_OPCCR1_I2C1CKS_Pos) ®CMU_OPCCR1_I2C1CKS_SYSCLK (0x2U << CMU_OPCCR1_I2C1CKS_Pos) °CMU_OPCCR1_I2C0CKS_Pos 16 µCMU_OPCCR1_I2C0CKS_Msk (0x3U << CMU_OPCCR1_I2C0CKS_Pos) ¶CMU_OPCCR1_I2C0CKS_APBCLK (0x0U << CMU_OPCCR1_I2C0CKS_Pos) ·CMU_OPCCR1_I2C0CKS_RCHF (0x1U << CMU_OPCCR1_I2C0CKS_Pos) ¸CMU_OPCCR1_I2C0CKS_SYSCLK (0x2U << CMU_OPCCR1_I2C0CKS_Pos) ºCMU_OPCCR1_UART1CKE_Pos 9 »CMU_OPCCR1_UART1CKE_Msk (0x1U << CMU_OPCCR1_UART1CKE_Pos) ½CMU_OPCCR1_UART0CKE_Pos 8 ¾CMU_OPCCR1_UART0CKE_Msk (0x1U << CMU_OPCCR1_UART0CKE_Pos) ÀCMU_OPCCR1_UART1CKS_Pos 2 ÅCMU_OPCCR1_UART1CKS_Msk (0x3U << CMU_OPCCR1_UART1CKS_Pos) ÆCMU_OPCCR1_UART1CKS_APBCLK (0x0U << CMU_OPCCR1_UART1CKS_Pos) ÇCMU_OPCCR1_UART1CKS_RCHF (0x1U << CMU_OPCCR1_UART1CKS_Pos) ÈCMU_OPCCR1_UART1CKS_SYSCLK (0x2U << CMU_OPCCR1_UART1CKS_Pos) ÊCMU_OPCCR1_UART0CKS_Pos 0 ÏCMU_OPCCR1_UART0CKS_Msk (0x3U << CMU_OPCCR1_UART0CKS_Pos) ÐCMU_OPCCR1_UART0CKS_APBCLK (0x0U << CMU_OPCCR1_UART0CKS_Pos) ÑCMU_OPCCR1_UART0CKS_RCHF (0x1U << CMU_OPCCR1_UART0CKS_Pos) ÒCMU_OPCCR1_UART0CKS_SYSCLK (0x2U << CMU_OPCCR1_UART0CKS_Pos) ÔCMU_OPCCR2_RNGPRSC_Pos 28 ÜCMU_OPCCR2_RNGPRSC_Msk (0x7U << CMU_OPCCR2_RNGPRSC_Pos) ÝCMU_OPCCR2_RNGPRSC_DIV1 (0x0U << CMU_OPCCR2_RNGPRSC_Pos) ÞCMU_OPCCR2_RNGPRSC_DIV2 (0x1U << CMU_OPCCR2_RNGPRSC_Pos) ßCMU_OPCCR2_RNGPRSC_DIV4 (0x2U << CMU_OPCCR2_RNGPRSC_Pos) àCMU_OPCCR2_RNGPRSC_DIV8 (0x3U << CMU_OPCCR2_RNGPRSC_Pos) áCMU_OPCCR2_RNGPRSC_DIV16 (0x4U << CMU_OPCCR2_RNGPRSC_Pos) âCMU_OPCCR2_RNGPRSC_DIV32 (0x5U << CMU_OPCCR2_RNGPRSC_Pos) äCMU_OPCCR2_NVMCKE_Pos 22 åCMU_OPCCR2_NVMCKE_Msk (0x1U << CMU_OPCCR2_NVMCKE_Pos) çCMU_OPCCR2_RNGCKE_Pos 21 èCMU_OPCCR2_RNGCKE_Msk (0x1U << CMU_OPCCR2_RNGCKE_Pos) êCMU_OPCCR2_LPTCKE_Pos 12 ëCMU_OPCCR2_LPTCKE_Msk (0x1U << CMU_OPCCR2_LPTCKE_Pos) íCMU_OPCCR2_LPTCKS_Pos 8 òCMU_OPCCR2_LPTCKS_Msk (0x3U << CMU_OPCCR2_LPTCKS_Pos) óCMU_OPCCR2_LPTCKS_APBCLK (0x0U << CMU_OPCCR2_LPTCKS_Pos) ôCMU_OPCCR2_LPTCKS_LSCLK (0x1U << CMU_OPCCR2_LPTCKS_Pos) õCMU_OPCCR2_LPTCKS_RCLP (0x2U << CMU_OPCCR2_LPTCKS_Pos) öCMU_OPCCR2_LPTCKS_PLL_L (0x3U << CMU_OPCCR2_LPTCKS_Pos) øCMU_OPCCR2_BSTCKE_Pos 4 ùCMU_OPCCR2_BSTCKE_Msk (0x1U << CMU_OPCCR2_BSTCKE_Pos) ûCMU_OPCCR2_BSTCKS_Pos 0 CMU_OPCCR2_BSTCKS_Msk (0x3U << CMU_OPCCR2_BSTCKS_Pos) CMU_OPCCR2_BSTCKS_APBCLK (0x0U << CMU_OPCCR2_BSTCKS_Pos) CMU_OPCCR2_BSTCKS_LSCLK (0x1U << CMU_OPCCR2_BSTCKS_Pos) CMU_OPCCR2_BSTCKS_RCLP (0x2U << CMU_OPCCR2_BSTCKS_Pos) CMU_OPCCR2_BSTCKS_SYSCLK (0x3U << CMU_OPCCR2_BSTCKS_Pos) £COMPCLK (0x01000000 + CMU_PCLKCR1_COMP_PCE_Pos) ¤SVDCLK (0x01000000 + CMU_PCLKCR1_SVD_PCE_Pos) ¥PADCLK (0x01000000 + CMU_PCLKCR1_PAD_PCE_Pos) ¦ANACCLK (0x01000000 + CMU_PCLKCR1_ANAC_PCE_Pos) §IWDTCLK (0x01000000 + CMU_PCLKCR1_IWDT_PCE_Pos) ¨SCUCLK (0x01000000 + CMU_PCLKCR1_SCU_PCE_Pos) ©PMUCLK (0x01000000 + CMU_PCLKCR1_PMU_PCE_Pos) ªRTCCLK (0x01000000 + CMU_PCLKCR1_RTC_PCE_Pos) «LPTCLK (0x01000000 + CMU_PCLKCR1_LPT_PCE_Pos) ®PAECLK (0x02000000 + CMU_PCLKCR2_PAE_PCE_Pos) ¯SHACLK (0x02000000 + CMU_PCLKCR2_SHA_PCE_Pos) °CICCLK (0x02000000 + CMU_PCLKCR2_CIC_PCE_Pos) ±WWDTCLK (0x02000000 + CMU_PCLKCR2_WWDT_PCE_Pos) ²RAMBISTCLK (0x02000000 + CMU_PCLKCR2_RAMBIST_PCE_Pos) ³FLASHCLK (0x02000000 + CMU_PCLKCR2_NVM_PCE_Pos) ´DMACLK (0x02000000 + CMU_PCLKCR2_DMA_PCE_Pos) µLCDCLK (0x02000000 + CMU_PCLKCR2_LCD_PCE_Pos) ¶AESCLK (0x02000000 + CMU_PCLKCR2_AES_PCE_Pos) ·TRNGCLK (0x02000000 + CMU_PCLKCR2_TRNG_PCE_Pos) ¸CRCCLK (0x02000000 + CMU_PCLKCR2_CRC_PCE_Pos) ºI2C1CLK (0x03000000 + CMU_PCLKCR3_I2C1_PCE_Pos) »I2C0CLK (0x03000000 + CMU_PCLKCR3_I2C0_PCE_Pos) ¼LPUART1CLK (0x03000000 + CMU_PCLKCR3_LPUART1_PCE_Pos) ½U7816CLK (0x03000000 + CMU_PCLKCR3_U7816_PCE_Pos) ¾LPUART0CLK (0x03000000 + CMU_PCLKCR3_LPUART0_PCE_Pos) ¿UARTIRCLK (0x03000000 + CMU_PCLKCR3_UICR_PCE_Pos) ÀUART5CLK (0x03000000 + CMU_PCLKCR3_UART5_PCE_Pos) ÁUART4CLK (0x03000000 + CMU_PCLKCR3_UART4_PCE_Pos) ÂUART3CLK (0x03000000 + CMU_PCLKCR3_UART3_PCE_Pos) ÃUART2CLK (0x03000000 + CMU_PCLKCR3_UART2_PCE_Pos) ÄUART1CLK (0x03000000 + CMU_PCLKCR3_UART1_PCE_Pos) ÅUART0CLK (0x03000000 + CMU_PCLKCR3_UART0_PCE_Pos) ÆQSPICLK (0x03000000 + CMU_PCLKCR3_QSPI_PCE_Pos) ÇSPI4CLK (0x03000000 + CMU_PCLKCR3_SPI4_PCE_Pos) ÈSPI3CLK (0x03000000 + CMU_PCLKCR3_SPI3_PCE_Pos) ÉSPI2CLK (0x03000000 + CMU_PCLKCR3_SPI2_PCE_Pos) ÊSPI1CLK (0x03000000 + CMU_PCLKCR3_SPI1_PCE_Pos) ËSPI0CLK (0x03000000 + CMU_PCLKCR3_SPI0_PCE_Pos) ÎET4CLK (0x04000000 + CMU_PCLKCR4_ET4_PCE_Pos) ÏET3CLK (0x04000000 + CMU_PCLKCR4_ET3_PCE_Pos) ÐET2CLK (0x04000000 + CMU_PCLKCR4_ET2_PCE_Pos) ÑET1CLK (0x04000000 + CMU_PCLKCR4_ET1_PCE_Pos) ÒBT2CLK (0x04000000 + CMU_PCLKCR4_BT2_PCE_Pos) ÓBT1CLK (0x04000000 + CMU_PCLKCR4_BT1_PCE_Pos) ÔBSTIMCLK (0x04000000 + CMU_PCLKCR4_BSTIM_PCE_Pos) ` T ..\Drivers\ ..\Core\Include\ fm33a0xxev_cmu.h FM33A0XXEV.h ð
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..\Drivers\fm33a0xxev_cmu.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM *à FSEL f # RCHFEN # PCMU_RCHF_InitTypeDef ½ )*¢ PLLLDB f # PLLL_EN # PCMU_PLL_L_InitTypeDef ü /* PLLHDB f # REFPRSC f # PLLH_OSEL f # PLLH_INSEL f # PLLH_EN # PCMU_PLL_H_InitTypeDef ?9* SYSCLKSEL f # AHBPRES f # APBPRES f # SLP_ENEXTI # PCMU_SYSCLK_InitTypeDef ºC*Û SYSCLK_Frequency f # AHBCLK_Frequency f # APBCLK_Frequency f # RCHF_Frequency f # PLL_H_Frequency f # XTHF_Frequency f # LSCLK_Frequency f # PCMU_ClocksType &N i j k __FM33A0XXEV_RTC_H /RTC_WRITE_ENABLE ((uint32_t)0xACACACAC) 0RTC_WRITE_DISABLE ((uint32_t)0x55AA55AA) 2RTC_WER_RTCWE_Pos 0 4RTC_WER_RTCWE_Msk (0x1U << RTC_WER_RTCWE_Pos) 6RTC_IER_ADJ_IE_Pos 12 9RTC_IER_ADJ_IE_Msk (0x1U << RTC_IER_ADJ_IE_Pos) =RTC_IER_ALARM_IE_Pos 11 @RTC_IER_ALARM_IE_Msk (0x1U << RTC_IER_ALARM_IE_Pos) DRTC_IER_1KHZ_IE_Pos 10 GRTC_IER_1KHZ_IE_Msk (0x1U << RTC_IER_1KHZ_IE_Pos) KRTC_IER_256HZ_IE_Pos 9 NRTC_IER_256HZ_IE_Msk (0x1U << RTC_IER_256HZ_IE_Pos) RRTC_IER_64HZ_IE_Pos 8 URTC_IER_64HZ_IE_Msk (0x1U << RTC_IER_64HZ_IE_Pos) YRTC_IER_16HZ_IE_Pos 7 \RTC_IER_16HZ_IE_Msk (0x1U << RTC_IER_16HZ_IE_Pos) `RTC_IER_8HZ_IE_Pos 6 cRTC_IER_8HZ_IE_Msk (0x1U << RTC_IER_8HZ_IE_Pos) gRTC_IER_4HZ_IE_Pos 5 jRTC_IER_4HZ_IE_Msk (0x1U << RTC_IER_4HZ_IE_Pos) nRTC_IER_2HZ_IE_Pos 4 qRTC_IER_2HZ_IE_Msk (0x1U << RTC_IER_2HZ_IE_Pos) uRTC_IER_SEC_IE_Pos 3 xRTC_IER_SEC_IE_Msk (0x1U << RTC_IER_SEC_IE_Pos) |RTC_IER_MIN_IE_Pos 2 RTC_IER_MIN_IE_Msk (0x1U << RTC_IER_MIN_IE_Pos) RTC_IER_HOUR_IE_Pos 1 RTC_IER_HOUR_IE_Msk (0x1U << RTC_IER_HOUR_IE_Pos) RTC_IER_DATE_IE_Pos 0 RTC_IER_DATE_IE_Msk (0x1U << RTC_IER_DATE_IE_Pos) RTC_ISR_ADJ_IF_Pos 12 RTC_ISR_ADJ_IF_Msk (0x1U << RTC_ISR_ADJ_IF_Pos) RTC_ISR_ALARM_IF_Pos 11 RTC_ISR_ALARM_IF_Msk (0x1U << RTC_ISR_ALARM_IF_Pos) RTC_ISR_1KHZ_IF_Pos 10 RTC_ISR_1KHZ_IF_Msk (0x1U << RTC_ISR_1KHZ_IF_Pos) RTC_ISR_256HZ_IF_Pos 9 £RTC_ISR_256HZ_IF_Msk (0x1U << RTC_ISR_256HZ_IF_Pos) ¦RTC_ISR_64HZ_IF_Pos 8 ©RTC_ISR_64HZ_IF_Msk (0x1U << RTC_ISR_64HZ_IF_Pos) ¬RTC_ISR_16HZ_IF_Pos 7 ¯RTC_ISR_16HZ_IF_Msk (0x1U << RTC_ISR_16HZ_IF_Pos) ±RTC_ISR_8HZ_IF_Pos 6 ´RTC_ISR_8HZ_IF_Msk (0x1U << RTC_ISR_8HZ_IF_Pos) ¶RTC_ISR_4HZ_IF_Pos 5 ¹RTC_ISR_4HZ_IF_Msk (0x1U << RTC_ISR_4HZ_IF_Pos) »RTC_ISR_2HZ_IF_Pos 4 ¾RTC_ISR_2HZ_IF_Msk (0x1U << RTC_ISR_2HZ_IF_Pos) ÀRTC_ISR_SEC_IF_Pos 3 ÃRTC_ISR_SEC_IF_Msk (0x1U << RTC_ISR_SEC_IF_Pos) ÅRTC_ISR_MIN_IF_Pos 2 ÈRTC_ISR_MIN_IF_Msk (0x1U << RTC_ISR_MIN_IF_Pos) ÊRTC_ISR_HOUR_IF_Pos 1 ÍRTC_ISR_HOUR_IF_Msk (0x1U << RTC_ISR_HOUR_IF_Pos) ÏRTC_ISR_DATE_IF_Pos 0 ÒRTC_ISR_DATE_IF_Msk (0x1U << RTC_ISR_DATE_IF_Pos) ÔRTC_BCDSEC_BCDSEC_Pos 0 ÕRTC_BCDSEC_BCDSEC_Msk (0x7fU << RTC_BCDSEC_BCDSEC_Pos) ×RTC_BCDMIN_BCDMIN_Pos 0 ØRTC_BCDMIN_BCDMIN_Msk (0x7fU << RTC_BCDMIN_BCDMIN_Pos) ÚRTC_BCDHOUR_BCDHOUR_Pos 0 ÛRTC_BCDHOUR_BCDHOUR_Msk (0x3fU << RTC_BCDHOUR_BCDHOUR_Pos) ÝRTC_BCDDATE_BCDDATE_Pos 0 ÞRTC_BCDDATE_BCDDATE_Msk (0x3fU << RTC_BCDDATE_BCDDATE_Pos) àRTC_BCDWEEK_BCDWEEK_Pos 0 áRTC_BCDWEEK_BCDWEEK_Msk (0x7U << RTC_BCDWEEK_BCDWEEK_Pos) ãRTC_BCDMONTH_BCDMONTH_Pos 0 äRTC_BCDMONTH_BCDMONTH_Msk (0x1fU << RTC_BCDMONTH_BCDMONTH_Pos) æRTC_BCDYEAR_BCDYEAR_Pos 0 çRTC_BCDYEAR_BCDYEAR_Msk (0xffU << RTC_BCDYEAR_BCDYEAR_Pos) éRTC_ALARM_ALMEN_Pos 31 ìRTC_ALARM_ALMEN_Msk (0x1U << RTC_ALARM_ALMEN_Pos) ðRTC_ALARM_ALARMHOUR_Pos 16 ñRTC_ALARM_ALARMHOUR_Msk (0x3fU << RTC_ALARM_ALARMHOUR_Pos) óRTC_ALARM_ALARMMIN_Pos 8 ôRTC_ALARM_ALARMMIN_Msk (0x7fU << RTC_ALARM_ALARMMIN_Pos) öRTC_ALARM_ALARMSEC_Pos 0 ÷RTC_ALARM_ALARMSEC_Msk (0x7fU << RTC_ALARM_ALARMSEC_Pos) ùRTC_TMSEL_FSEL_Pos 0 RTC_TMSEL_FSEL_Msk (0xfU << RTC_TMSEL_FSEL_Pos) RTC_TMSEL_FSEL_PLL1HZ (0x0U << RTC_TMSEL_FSEL_Pos) RTC_TMSEL_FSEL_PLLD1HZ (0x1U << RTC_TMSEL_FSEL_Pos) RTC_TMSEL_FSEL_SECOND (0x2U << RTC_TMSEL_FSEL_Pos) RTC_TMSEL_FSEL_MINUTE (0x3U << RTC_TMSEL_FSEL_Pos) RTC_TMSEL_FSEL_HOUR (0x4U << RTC_TMSEL_FSEL_Pos) RTC_TMSEL_FSEL_DAY (0x5U << RTC_TMSEL_FSEL_Pos) RTC_TMSEL_FSEL_ALARM (0x6U << RTC_TMSEL_FSEL_Pos) RTC_TMSEL_FSEL_256S (0x7U << RTC_TMSEL_FSEL_Pos) RTC_TMSEL_FSEL_PLLD1HZREV (0x8U << RTC_TMSEL_FSEL_Pos) RTC_TMSEL_FSEL_SECONDREV (0x9U << RTC_TMSEL_FSEL_Pos) RTC_TMSEL_FSEL_MINUTEREV (0xaU << RTC_TMSEL_FSEL_Pos) RTC_TMSEL_FSEL_HOURREV (0xbU << RTC_TMSEL_FSEL_Pos) RTC_TMSEL_FSEL_DAYREV (0xcU << RTC_TMSEL_FSEL_Pos) RTC_TMSEL_FSEL_ALARMREV (0xdU << RTC_TMSEL_FSEL_Pos) RTC_TMSEL_FSEL_PLL1HZREV (0xeU << RTC_TMSEL_FSEL_Pos) RTC_TMSEL_FSEL_SECONDRUN (0xfU << RTC_TMSEL_FSEL_Pos) RTC_ADJUST_ADJUST_Pos 0 ¡RTC_ADJUST_ADJUST_Msk (0x1fffU << RTC_ADJUST_ADJUST_Pos) £RTC_ADSIGN_ADSIGN_Pos 0 ¦RTC_ADSIGN_ADSIGN_Msk (0x1U << RTC_ADSIGN_ADSIGN_Pos) §RTC_ADSIGN_ADSIGN_INCREASE (0x0U << RTC_ADSIGN_ADSIGN_Pos) ¨RTC_ADSIGN_ADSIGN_DECREASE (0x1U << RTC_ADSIGN_ADSIGN_Pos) ªRTC_VCAL_PR1SEN_Pos 0 RTC_VCAL_PR1SEN_Msk (0x1U << RTC_VCAL_PR1SEN_Pos) ±RTC_MSCNT_MSCNT_Pos 0 µRTC_MSCNT_MSCNT_Msk (0xffU << RTC_MSCNT_MSCNT_Pos) ·RTC_CALSTEP_CALSTEP_Pos 0 »RTC_CALSTEP_CALSTEP_Msk (0x1U << RTC_CALSTEP_CALSTEP_Pos) ¼RTC_CALSTEP_CALSTEP_006PPM (0x2U << RTC_CALSTEP_CALSTEP_Pos) ½RTC_CALSTEP_CALSTEP_0119PPM (0x1U << RTC_CALSTEP_CALSTEP_Pos) ¾RTC_CALSTEP_CALSTEP_0238PPM (0x0U << RTC_CALSTEP_CALSTEP_Pos) ÀRTC_ADCNT_ADJCNT_Pos 0 ÁRTC_ADCNT_ADJCNT_Msk (0x1ffU << RTC_ADCNT_ADJCNT_Pos) ÃRTC_SSR_SSR_Pos 0 ÅRTC_SSR_SSR_Msk (0x3fU << RTC_SSR_SSR_Pos) ÇRTC_SSA_SSAEN_Pos 7 ÊRTC_SSA_SSAEN_Msk (0x1U << RTC_SSA_SSAEN_Pos) ÎRTC_SSA_SS_ALARM_Pos 0 ÐRTC_SSA_SS_ALARM_Msk (0x3fU << RTC_SSA_SS_ALARM_Pos) ÒRTC_DTR_DUTY_Pos 0 ÓRTC_DTR_DUTY_Msk (0x1ffffffU << RTC_DTR_DUTY_Pos) ÕRTC_CR_RTC_EN_Pos 0 ÚRTC_CR_RTC_EN_Msk (0x1U << RTC_CR_RTC_EN_Pos) ` T ..\Drivers\ ..\Core\Include\ fm33a0xxev_rtc.h FM33A0XXEV.h °
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..\Drivers\fm33a0xxev_rtc.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM *© Year 8 # Month 8 # Date 8 # Hour 8 # Minute 8 # Second 8 # Week 8 # PRTC_TimeDateTypeDef ½ #PRTC_StampTmieTypeDef ½ #* Hour 8 # Minute 8 # Second 8 # PRTC_AlarmTmieTypeDef `+ m n o __FM33A0XXEV_DBG_H DBG_CR_DBG_LPT_STOP_Pos 15 DBG_CR_DBG_LPT_STOP_Msk (0x1U << DBG_CR_DBG_LPT_STOP_Pos) DBG_CR_DBG_BST_STOP_Pos 14 #DBG_CR_DBG_BST_STOP_Msk (0x1U << DBG_CR_DBG_BST_STOP_Pos) 'DBG_CR_DBG_ET4_STOP_Pos 13 *DBG_CR_DBG_ET4_STOP_Msk (0x1U << DBG_CR_DBG_ET4_STOP_Pos) .DBG_CR_DBG_ET3_STOP_Pos 12 1DBG_CR_DBG_ET3_STOP_Msk (0x1U << DBG_CR_DBG_ET3_STOP_Pos) 5DBG_CR_DBG_ET2_STOP_Pos 11 8DBG_CR_DBG_ET2_STOP_Msk (0x1U << DBG_CR_DBG_ET2_STOP_Pos) <DBG_CR_DBG_ET1_STOP_Pos 10 ?DBG_CR_DBG_ET1_STOP_Msk (0x1U << DBG_CR_DBG_ET1_STOP_Pos) CDBG_CR_DBG_BT2_STOP_Pos 9 FDBG_CR_DBG_BT2_STOP_Msk (0x1U << DBG_CR_DBG_BT2_STOP_Pos) JDBG_CR_DBG_BT1_STOP_Pos 8 MDBG_CR_DBG_BT1_STOP_Msk (0x1U << DBG_CR_DBG_BT1_STOP_Pos) QDBG_CR_DBG_WWDT_STOP_Pos 1 TDBG_CR_DBG_WWDT_STOP_Msk (0x1U << DBG_CR_DBG_WWDT_STOP_Pos) XDBG_CR_DBG_IWDT_STOP_Pos 0 [DBG_CR_DBG_IWDT_STOP_Msk (0x1U << DBG_CR_DBG_IWDT_STOP_Pos) _DBG_HDFR_DABORT_ADDR_FLAG_Pos 6 bDBG_HDFR_DABORT_ADDR_FLAG_Msk (0x1U << DBG_HDFR_DABORT_ADDR_FLAG_Pos) dDBG_HDFR_DABORT_RESP_FLAG_Pos 5 gDBG_HDFR_DABORT_RESP_FLAG_Msk (0x1U << DBG_HDFR_DABORT_RESP_FLAG_Pos) iDBG_HDFR_SVCUNDEF_FLAG_Pos 4 nDBG_HDFR_SVCUNDEF_FLAG_Msk (0x1U << DBG_HDFR_SVCUNDEF_FLAG_Pos) pDBG_HDFR_BKPT_FLAG_Pos 3 sDBG_HDFR_BKPT_FLAG_Msk (0x1U << DBG_HDFR_BKPT_FLAG_Pos) uDBG_HDFR_TBIT_FLAG_Pos 2 xDBG_HDFR_TBIT_FLAG_Msk (0x1U << DBG_HDFR_TBIT_FLAG_Pos) zDBG_HDFR_SPECIAL_OP_FLAG_Pos 1 }DBG_HDFR_SPECIAL_OP_FLAG_Msk (0x1U << DBG_HDFR_SPECIAL_OP_FLAG_Pos) DBG_HDFR_HDF_REQUEST_FLAG_Pos 0 DBG_HDFR_HDF_REQUEST_FLAG_Msk (0x1U << DBG_HDFR_HDF_REQUEST_FLAG_Pos) ` T ..\Drivers\ ..\Core\Include\ fm33a0xxev_dbg.h FM33A0XXEV.h ¼
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..\Drivers\fm33a0xxev_dbg.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM q r s __FM33A0XXEV_SPI_H SPIx_CR1_IOSWAP_Pos 11 SPIx_CR1_IOSWAP_Msk (0x1U << SPIx_CR1_IOSWAP_Pos) SPIx_CR1_IOSWAP_DEFAULT (0x0U << SPIx_CR1_IOSWAP_Pos) SPIx_CR1_IOSWAP_EXCHANGE (0x1U << SPIx_CR1_IOSWAP_Pos) "SPIx_CR1_MSPA_Pos 10 %SPIx_CR1_MSPA_Msk (0x1U << SPIx_CR1_MSPA_Pos) &SPIx_CR1_MSPA_DELAY (0x1U << SPIx_CR1_MSPA_Pos) 'SPIx_CR1_MSPA_NORMAL (0x0U << SPIx_CR1_MSPA_Pos) )SPIx_CR1_SSPA_Pos 9 ,SPIx_CR1_SSPA_Msk (0x1U << SPIx_CR1_SSPA_Pos) -SPIx_CR1_SSPA_EARLY (0x1U << SPIx_CR1_SSPA_Pos) .SPIx_CR1_SSPA_NORMAL (0x0U << SPIx_CR1_SSPA_Pos) 0SPIx_CR1_MM_Pos 8 1SPIx_CR1_MM_Msk (0x1U << SPIx_CR1_MM_Pos) 2SPIx_CR1_MM_MASTER (0x1U << SPIx_CR1_MM_Pos) 3SPIx_CR1_MM_SLAVE (0x0U << SPIx_CR1_MM_Pos) 5SPIx_CR1_WAIT_Pos 6 6SPIx_CR1_WAIT_Msk (0x3U << SPIx_CR1_WAIT_Pos) 7SPIx_CR1_WAIT_1WAIT (0x0U << SPIx_CR1_WAIT_Pos) 8SPIx_CR1_WAIT_2WAIT (0x1U << SPIx_CR1_WAIT_Pos) 9SPIx_CR1_WAIT_3WAIT (0x2U << SPIx_CR1_WAIT_Pos) :SPIx_CR1_WAIT_4WAIT (0x3U << SPIx_CR1_WAIT_Pos) <SPIx_CR1_BAUD_Pos 3 =SPIx_CR1_BAUD_Msk (0x7U << SPIx_CR1_BAUD_Pos) >SPIx_CR1_BAUD_DIV2 (0x0U << SPIx_CR1_BAUD_Pos) ?SPIx_CR1_BAUD_DIV4 (0x1U << SPIx_CR1_BAUD_Pos) @SPIx_CR1_BAUD_DIV8 (0x2U << SPIx_CR1_BAUD_Pos) ASPIx_CR1_BAUD_DIV16 (0x3U << SPIx_CR1_BAUD_Pos) BSPIx_CR1_BAUD_DIV32 (0x4U << SPIx_CR1_BAUD_Pos) CSPIx_CR1_BAUD_DIV64 (0x5U << SPIx_CR1_BAUD_Pos) DSPIx_CR1_BAUD_DIV128 (0x6U << SPIx_CR1_BAUD_Pos) ESPIx_CR1_BAUD_DIV256 (0x7U << SPIx_CR1_BAUD_Pos) GSPIx_CR1_LSBF_Pos 2 HSPIx_CR1_LSBF_Msk (0x1U << SPIx_CR1_LSBF_Pos) ISPIx_CR1_LSBF_MSB (0x0U << SPIx_CR1_LSBF_Pos) JSPIx_CR1_LSBF_LSB (0x1U << SPIx_CR1_LSBF_Pos) LSPIx_CR1_CPHOL_Pos 1 MSPIx_CR1_CPHOL_Msk (0x1U << SPIx_CR1_CPHOL_Pos) NSPIx_CR1_CPHOL_LOW (0x0U << SPIx_CR1_CPHOL_Pos) OSPIx_CR1_CPHOL_HIGH (0x1U << SPIx_CR1_CPHOL_Pos) QSPIx_CR1_CPHA_Pos 0 RSPIx_CR1_CPHA_Msk (0x1U << SPIx_CR1_CPHA_Pos) SSPIx_CR1_CPHA_1CLOCK (0x0U << SPIx_CR1_CPHA_Pos) TSPIx_CR1_CPHA_2CLOCK (0x1U << SPIx_CR1_CPHA_Pos) VSPIx_CR2_DUMMY_EN_Pos 15 ZSPIx_CR2_DUMMY_EN_Msk (0x1U << SPIx_CR2_DUMMY_EN_Pos) ^SPIx_CR2_RXO_Pos 11 aSPIx_CR2_RXO_Msk (0x1U << SPIx_CR2_RXO_Pos) eSPIx_CR2_DLEN_Pos 9 jSPIx_CR2_DLEN_Msk (0x3U << SPIx_CR2_DLEN_Pos) kSPIx_CR2_DLEN_8BIT (0x0U << SPIx_CR2_DLEN_Pos) lSPIx_CR2_DLEN_16BIT (0x1U << SPIx_CR2_DLEN_Pos) mSPIx_CR2_DLEN_24BIT (0x2U << SPIx_CR2_DLEN_Pos) nSPIx_CR2_DLEN_32BIT (0x3U << SPIx_CR2_DLEN_Pos) pSPIx_CR2_HALFDUPLEX_Pos 8 sSPIx_CR2_HALFDUPLEX_Msk (0x1U << SPIx_CR2_HALFDUPLEX_Pos) tSPIx_CR2_HALFDUPLEX_SPI (0x0U << SPIx_CR2_HALFDUPLEX_Pos) uSPIx_CR2_HALFDUPLEX_DCN (0x1U << SPIx_CR2_HALFDUPLEX_Pos) wSPIx_CR2_HD_RW_Pos 7 zSPIx_CR2_HD_RW_Msk (0x1U << SPIx_CR2_HD_RW_Pos) {SPIx_CR2_HD_RW_WRITE (0x0U << SPIx_CR2_HD_RW_Pos) |SPIx_CR2_HD_RW_READ (0x1U << SPIx_CR2_HD_RW_Pos) ~SPIx_CR2_CMD8b_Pos 6 SPIx_CR2_CMD8b_Msk (0x1U << SPIx_CR2_CMD8b_Pos) SPIx_CR2_CMD8b_8BIT (0x1U << SPIx_CR2_CMD8b_Pos) SPIx_CR2_CMD8b_DLEN (0x0U << SPIx_CR2_CMD8b_Pos)
SPIx_CR2_SSNM_Pos 5 SPIx_CR2_SSNM_Msk (0x1U << SPIx_CR2_SSNM_Pos) SPIx_CR2_SSNM_HIGH (0x1U << SPIx_CR2_SSNM_Pos) SPIx_CR2_SSNM_LOW (0x0U << SPIx_CR2_SSNM_Pos) SPIx_CR2_TXO_AC_Pos 4 SPIx_CR2_TXO_AC_Msk (0x1U << SPIx_CR2_TXO_AC_Pos) SPIx_CR2_TXO_Pos 3 SPIx_CR2_TXO_Msk (0x1U << SPIx_CR2_TXO_Pos) SPIx_CR2_SSN_Pos 2 SPIx_CR2_SSN_Msk (0x1U << SPIx_CR2_SSN_Pos) SPIx_CR2_SSN_LOW (0x0U << SPIx_CR2_SSN_Pos) SPIx_CR2_SSN_HIGH (0x1U << SPIx_CR2_SSN_Pos) SPIx_CR2_SSNSEN_Pos 1 SPIx_CR2_SSNSEN_Msk (0x1U << SPIx_CR2_SSNSEN_Pos) £SPIx_CR2_SPIEN_Pos 0 ¤SPIx_CR2_SPIEN_Msk (0x1U << SPIx_CR2_SPIEN_Pos) ¦SPIx_CR3_TXBFC_Pos 3 §SPIx_CR3_TXBFC_Msk (0x1U << SPIx_CR3_TXBFC_Pos) ©SPIx_CR3_RXBFC_Pos 2 ªSPIx_CR3_RXBFC_Msk (0x1U << SPIx_CR3_RXBFC_Pos) ¬SPIx_CR3_MERRC_Pos 1 SPIx_CR3_MERRC_Msk (0x1U << SPIx_CR3_MERRC_Pos) ¯SPIx_CR3_SERRC_Pos 0 °SPIx_CR3_SERRC_Msk (0x1U << SPIx_CR3_SERRC_Pos) ²SPIx_IER_ERRIE_Pos 2 ³SPIx_IER_ERRIE_Msk (0x1U << SPIx_IER_ERRIE_Pos) µSPIx_IER_TXIE_Pos 1 ¶SPIx_IER_TXIE_Msk (0x1U << SPIx_IER_TXIE_Pos) ¸SPIx_IER_RXIE_Pos 0 ¹SPIx_IER_RXIE_Msk (0x1U << SPIx_IER_RXIE_Pos) »SPIx_ISR_DCN_TX_Pos 12 ¿SPIx_ISR_DCN_TX_Msk (0x1U << SPIx_ISR_DCN_TX_Pos) ÀSPIx_ISR_DCN_TX_COMMAND (0x0U << SPIx_ISR_DCN_TX_Pos) ÁSPIx_ISR_DCN_TX_DATA (0x1U << SPIx_ISR_DCN_TX_Pos) ÃSPIx_ISR_RXCOL_Pos 10 ÄSPIx_ISR_RXCOL_Msk (0x1U << SPIx_ISR_RXCOL_Pos) ÆSPIx_ISR_TXCOL_Pos 9 ÇSPIx_ISR_TXCOL_Msk (0x1U << SPIx_ISR_TXCOL_Pos) ÉSPIx_ISR_BUSY_Pos 8 ÌSPIx_ISR_BUSY_Msk (0x1U << SPIx_ISR_BUSY_Pos) ÎSPIx_ISR_MERR_Pos 6 ÐSPIx_ISR_MERR_Msk (0x1U << SPIx_ISR_MERR_Pos) ÒSPIx_ISR_SERR_Pos 5 ÔSPIx_ISR_SERR_Msk (0x1U << SPIx_ISR_SERR_Pos) ÖSPIx_ISR_TXBE_Pos 1 ÙSPIx_ISR_TXBE_Msk (0x1U << SPIx_ISR_TXBE_Pos) ÛSPIx_ISR_RXBF_Pos 0 ÞSPIx_ISR_RXBF_Msk (0x1U << SPIx_ISR_RXBF_Pos) àSPIx_TXBUF_TXBUF_Pos 0 áSPIx_TXBUF_TXBUF_Msk (0xffffffffU << SPIx_TXBUF_TXBUF_Pos) ãSPIx_RXBUF_RXBUF_Pos 0 äSPIx_RXBUF_RXBUF_Msk (0xffffffffU << SPIx_RXBUF_RXBUF_Pos) ` T ..\Drivers\ ..\Core\Include\ fm33a0xxev_spi.h FM33A0XXEV.h ¼
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..\Drivers\fm33a0xxev_spi.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM u v w __FM33A0XXEV_RNG_H RNG_CR_EN_Pos 0 RNG_CR_EN_Msk (0x1U << RNG_CR_EN_Pos) RNG_DOR_OUT_Pos 0 "RNG_DOR_OUT_Msk (0xffffffffU << RNG_DOR_OUT_Pos) $RNG_SR_LFSREN_Pos 1 (RNG_SR_LFSREN_Msk (0x1U << RNG_SR_LFSREN_Pos) -RNG_SR_RNF_Pos 0 0RNG_SR_RNF_Msk (0x1U << RNG_SR_RNF_Pos) 2RNG_CRC_CR_CRCEN_Pos 0 5RNG_CRC_CR_CRCEN_Msk (0x1U << RNG_CRC_CR_CRCEN_Pos) 9RNG_CRC_DIR_CRCIN_Pos 0 :RNG_CRC_DIR_CRCIN_Msk (0xffffffffU << RNG_CRC_DIR_CRCIN_Pos) <RNG_CRC_SR_CRCDONE_Pos 0 ?RNG_CRC_SR_CRCDONE_Msk (0x1U << RNG_CRC_SR_CRCDONE_Pos) ` T ..\Drivers\ ..\Core\Include\ fm33a0xxev_rng.h FM33A0XXEV.h ¼
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..\Drivers\fm33a0xxev_rng.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM y z { __FM33A0XXEV_U7816_H 7U7816_CR_TXEN_Pos 5 8U7816_CR_TXEN_Msk (0x1U << U7816_CR_TXEN_Pos) :U7816_CR_RXEN_Pos 4 ;U7816_CR_RXEN_Msk (0x1U << U7816_CR_RXEN_Pos) =U7816_CR_CKOEN_Pos 3 >U7816_CR_CKOEN_Msk (0x1U << U7816_CR_CKOEN_Pos) @U7816_CR_HPUAT_Pos 2 AU7816_CR_HPUAT_Msk (0x1U << U7816_CR_HPUAT_Pos) CU7816_CR_HPUEN_Pos 1 DU7816_CR_HPUEN_Msk (0x1U << U7816_CR_HPUEN_Pos) FU7816_FFR_SFREN_Pos 11 GU7816_FFR_SFREN_Msk (0x1U << U7816_FFR_SFREN_Pos) HU7816_FFR_SFREN_3ETU (0x1U << U7816_FFR_SFREN_Pos) IU7816_FFR_SFREN_2ETU (0x0U << U7816_FFR_SFREN_Pos) KU7816_FFR_ERSW_Pos 9 LU7816_FFR_ERSW_Msk (0x3U << U7816_FFR_ERSW_Pos) MU7816_FFR_ERSW_1ETU (0x0U << U7816_FFR_ERSW_Pos) NU7816_FFR_ERSW_1P5ETU (0x1U << U7816_FFR_ERSW_Pos) OU7816_FFR_ERSW_2ETU (0x2U << U7816_FFR_ERSW_Pos) QU7816_FFR_ERSGD_Pos 8 SU7816_FFR_ERSGD_Msk (0x1U << U7816_FFR_ERSGD_Pos) TU7816_FFR_ERSGD_1ETU (0x1U << U7816_FFR_ERSGD_Pos) UU7816_FFR_ERSGD_2ETU (0x0U << U7816_FFR_ERSGD_Pos) WU7816_FFR_BGTEN_Pos 7 XU7816_FFR_BGTEN_Msk (0x1U << U7816_FFR_BGTEN_Pos) ZU7816_FFR_REP_T_Pos 6 [U7816_FFR_REP_T_Msk (0x1U << U7816_FFR_REP_T_Pos) \U7816_FFR_REP_T_1TIMES (0x0U << U7816_FFR_REP_T_Pos) ]U7816_FFR_REP_T_3TIMES (0x1U << U7816_FFR_REP_T_Pos) _U7816_FFR_PAR_Pos 4 `U7816_FFR_PAR_Msk (0x3U << U7816_FFR_PAR_Pos) aU7816_FFR_PAR_EVEN (0x0U << U7816_FFR_PAR_Pos) bU7816_FFR_PAR_ODD (0x1U << U7816_FFR_PAR_Pos) cU7816_FFR_PAR_1ALAWAYS (0x2U << U7816_FFR_PAR_Pos) dU7816_FFR_PAR_NON (0x3U << U7816_FFR_PAR_Pos) fU7816_FFR_RFREN_Pos 3 gU7816_FFR_RFREN_Msk (0x1U << U7816_FFR_RFREN_Pos) hU7816_FFR_RFREN_1ETU (0x1U << U7816_FFR_RFREN_Pos) iU7816_FFR_RFREN_2ETU (0x0U << U7816_FFR_RFREN_Pos) kU7816_FFR_TREPEN_Pos 2 lU7816_FFR_TREPEN_Msk (0x1U << U7816_FFR_TREPEN_Pos) nU7816_FFR_RREPEN_Pos 1 oU7816_FFR_RREPEN_Msk (0x1U << U7816_FFR_RREPEN_Pos) qU7816_FFR_DICONV_Pos 0 rU7816_FFR_DICONV_Msk (0x1U << U7816_FFR_DICONV_Pos) sU7816_FFR_DICONV_FORWARD (0x0U << U7816_FFR_DICONV_Pos) tU7816_FFR_DICONV_REVERSE (0x1U << U7816_FFR_DICONV_Pos) vU7816_EGTR_TXEGT_Pos 0 xU7816_EGTR_TXEGT_Msk (0xffU << U7816_EGTR_TXEGT_Pos) zU7816_PSC_CLKDIV_Pos 0 {U7816_PSC_CLKDIV_Msk (0x1fU << U7816_PSC_CLKDIV_Pos) }U7816_BGR_PDIV_Pos 0 U7816_BGR_PDIV_Msk (0xfffU << U7816_BGR_PDIV_Pos) U7816_RXBUF_RXBUF_Pos 0 U7816_RXBUF_RXBUF_Msk (0xffU << U7816_RXBUF_RXBUF_Pos)
U7816_TXBUF_TXBUF_Pos 0 U7816_TXBUF_TXBUF_Msk (0xffU << U7816_TXBUF_TXBUF_Pos) U7816_IER_RXIE_Pos 2 U7816_IER_RXIE_Msk (0x1U << U7816_IER_RXIE_Pos) U7816_IER_TXIE_Pos 1 U7816_IER_TXIE_Msk (0x1U << U7816_IER_TXIE_Pos) U7816_IER_LSIE_Pos 0 U7816_IER_LSIE_Msk (0x1U << U7816_IER_LSIE_Pos) U7816_ISR_WAIT_RPT_Pos 18 U7816_ISR_WAIT_RPT_Msk (0x1U << U7816_ISR_WAIT_RPT_Pos) U7816_ISR_TXBUSY_Pos 17 U7816_ISR_TXBUSY_Msk (0x1U << U7816_ISR_TXBUSY_Pos) U7816_ISR_RXBUSY_Pos 16 U7816_ISR_RXBUSY_Msk (0x1U << U7816_ISR_RXBUSY_Pos) U7816_ISR_TPARERR_Pos 11 U7816_ISR_TPARERR_Msk (0x1U << U7816_ISR_TPARERR_Pos) U7816_ISR_RPARERR_Pos 10 U7816_ISR_RPARERR_Msk (0x1U << U7816_ISR_RPARERR_Pos) U7816_ISR_FRERR_Pos 9 ¡U7816_ISR_FRERR_Msk (0x1U << U7816_ISR_FRERR_Pos) £U7816_ISR_OVERR_Pos 8 ¤U7816_ISR_OVERR_Msk (0x1U << U7816_ISR_OVERR_Pos) ¦U7816_ISR_RXIF_Pos 2 §U7816_ISR_RXIF_Msk (0x1U << U7816_ISR_RXIF_Pos) ©U7816_ISR_TXIF_Pos 1 ªU7816_ISR_TXIF_Msk (0x1U << U7816_ISR_TXIF_Pos) ¬U7816_ISR_ERRIF_Pos 0 U7816_ISR_ERRIF_Msk (0x1U << U7816_ISR_ERRIF_Pos) ` V ..\Drivers\ ..\Core\Include\ fm33a0xxev_u7816.h FM33A0XXEV.h
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..\Drivers\fm33a0xxev_u7816.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM *ú8 TXEN # RXEN # CKOEN # HPUAT # HPUEN # ERSW f # ERSGD f # BGTEN # REP_T f # PAR f # SFREN f # RFREN f # TREPEN #$ RREPEN #% DICONV #& TXEGT f #( CLKDIV f #, PDIV f #0 RXIE #4 TXIE #5 LSIE #6 PU7816_InitTypeDef ¿ 4 } ~ __FM33A0XXEV_UART_H OUARTIR_CR_IRFLAG_Pos 15 RUARTIR_CR_IRFLAG_Msk (0x1U << UARTIR_CR_IRFLAG_Pos) SUARTIR_CR_IRFLAG_POSITIVE (0x0U << UARTIR_CR_IRFLAG_Pos) TUARTIR_CR_IRFLAG_NEGTIVE (0x1U << UARTIR_CR_IRFLAG_Pos) VUARTIR_CR_TH_Pos 11 WUARTIR_CR_TH_Msk (0xfU << UARTIR_CR_TH_Pos) YUARTIR_CR_TZBRG_Pos 0 ZUARTIR_CR_TZBRG_Msk (0x7ffU << UARTIR_CR_TZBRG_Pos) \UARTx_CSR_BUSY_Pos 24 _UARTx_CSR_BUSY_Msk (0x1U << UARTx_CSR_BUSY_Pos) aUARTx_CSR_TXIREN_Pos 17 dUARTx_CSR_TXIREN_Msk (0x1U << UARTx_CSR_TXIREN_Pos) hUARTx_CSR_RXTOEN_Pos 16 kUARTx_CSR_RXTOEN_Msk (0x1U << UARTx_CSR_RXTOEN_Pos) oUARTx_CSR_IOSWAP_Pos 12 rUARTx_CSR_IOSWAP_Msk (0x1U << UARTx_CSR_IOSWAP_Pos) sUARTx_CSR_IOSWAP_DEFAULT (0x0U << UARTx_CSR_IOSWAP_Pos) tUARTx_CSR_IOSWAP_EXCHANGE (0x1U << UARTx_CSR_IOSWAP_Pos) vUARTx_CSR_DMATXIFCFG_Pos 10 yUARTx_CSR_DMATXIFCFG_Msk (0x1U << UARTx_CSR_DMATXIFCFG_Pos) }UARTx_CSR_BITORD_Pos 9 UARTx_CSR_BITORD_Msk (0x1U << UARTx_CSR_BITORD_Pos) UARTx_CSR_BITORD_LSB (0x0U << UARTx_CSR_BITORD_Pos) UARTx_CSR_BITORD_MSB (0x1U << UARTx_CSR_BITORD_Pos) UARTx_CSR_STOPCFG_Pos 8 UARTx_CSR_STOPCFG_Msk (0x1U << UARTx_CSR_STOPCFG_Pos) UARTx_CSR_STOPCFG_1STOPBIT (0x0U << UARTx_CSR_STOPCFG_Pos) UARTx_CSR_STOPCFG_2STOPBIT (0x1U << UARTx_CSR_STOPCFG_Pos) UARTx_CSR_PDSEL_Pos 6 UARTx_CSR_PDSEL_Msk (0x3U << UARTx_CSR_PDSEL_Pos) UARTx_CSR_PDSEL_7BIT (0x0U << UARTx_CSR_PDSEL_Pos) UARTx_CSR_PDSEL_8BIT (0x1U << UARTx_CSR_PDSEL_Pos) UARTx_CSR_PDSEL_9BIT (0x2U << UARTx_CSR_PDSEL_Pos) UARTx_CSR_PDSEL_6BIT (0x3U << UARTx_CSR_PDSEL_Pos) UARTx_CSR_PARITY_Pos 4 UARTx_CSR_PARITY_Msk (0x3U << UARTx_CSR_PARITY_Pos) UARTx_CSR_PARITY_NONE (0x0U << UARTx_CSR_PARITY_Pos) UARTx_CSR_PARITY_EVEN (0x1U << UARTx_CSR_PARITY_Pos) UARTx_CSR_PARITY_ODD (0x2U << UARTx_CSR_PARITY_Pos) UARTx_CSR_RXPOL_Pos 3 £UARTx_CSR_RXPOL_Msk (0x1U << UARTx_CSR_RXPOL_Pos) ¤UARTx_CSR_RXPOL_POSITIVE (0x0U << UARTx_CSR_RXPOL_Pos) ¥UARTx_CSR_RXPOL_NEGTIVE (0x1U << UARTx_CSR_RXPOL_Pos) §UARTx_CSR_TXPOL_Pos 2 ªUARTx_CSR_TXPOL_Msk (0x1U << UARTx_CSR_TXPOL_Pos) «UARTx_CSR_TXPOL_POSITIVE (0x0U << UARTx_CSR_TXPOL_Pos) ¬UARTx_CSR_TXPOL_NEGTIVE (0x1U << UARTx_CSR_TXPOL_Pos) ®UARTx_CSR_RXEN_Pos 1 ¯UARTx_CSR_RXEN_Msk (0x1U << UARTx_CSR_RXEN_Pos) °UARTx_CSR_RXEN_DISBALE (0x0U << UARTx_CSR_RXEN_Pos) ±UARTx_CSR_RXEN_ENABLE (0x1U << UARTx_CSR_RXEN_Pos) ³UARTx_CSR_TXEN_Pos 0 ´UARTx_CSR_TXEN_Msk (0x1U << UARTx_CSR_TXEN_Pos) µUARTx_CSR_TXEN_DISBALE (0x0U << UARTx_CSR_TXEN_Pos) ¶UARTx_CSR_TXEN_ENABLE (0x1U << UARTx_CSR_TXEN_Pos) ¸UARTx_IER_RXTO_IE_Pos 11 ºUARTx_IER_RXTO_IE_Msk (0x1U << UARTx_IER_RXTO_IE_Pos) ¼UARTx_IER_RXERR_IE_Pos 10 ½UARTx_IER_RXERR_IE_Msk (0x1U << UARTx_IER_RXERR_IE_Pos) ¿UARTx_IER_RXBF_IE_Pos 8 ÀUARTx_IER_RXBF_IE_Msk (0x1U << UARTx_IER_RXBF_IE_Pos) ÂUARTx_IER_NEWUP_IE_Pos 7 ÃUARTx_IER_NEWUP_IE_Msk (0x1U << UARTx_IER_NEWUP_IE_Pos) ÅUARTx_IER_TXBE_IE_Pos 1 ÆUARTx_IER_TXBE_IE_Msk (0x1U << UARTx_IER_TXBE_IE_Pos) ÈUARTx_IER_TXSE_IE_Pos 0 ÉUARTx_IER_TXSE_IE_Msk (0x1U << UARTx_IER_TXSE_IE_Pos) ËUARTx_ISR_PERR_Pos 18 ÌUARTx_ISR_PERR_Msk (0x1U << UARTx_ISR_PERR_Pos) ÎUARTx_ISR_FERR_Pos 17 ÏUARTx_ISR_FERR_Msk (0x1U << UARTx_ISR_FERR_Pos) ÑUARTx_ISR_OERR_Pos 16 ÓUARTx_ISR_OERR_Msk (0x1U << UARTx_ISR_OERR_Pos) ÕUARTx_ISR_RXTO_Pos 11 ×UARTx_ISR_RXTO_Msk (0x1U << UARTx_ISR_RXTO_Pos) ÙUARTx_ISR_RXBF_Pos 8 ÚUARTx_ISR_RXBF_Msk (0x1U << UARTx_ISR_RXBF_Pos) ÜUARTx_ISR_TXBE_Pos 1 ÝUARTx_ISR_TXBE_Msk (0x1U << UARTx_ISR_TXBE_Pos) ßUARTx_ISR_TXSE_Pos 0 àUARTx_ISR_TXSE_Msk (0x1U << UARTx_ISR_TXSE_Pos) âUARTx_TODR_TXDLY_LEN_Pos 8 ãUARTx_TODR_TXDLY_LEN_Msk (0xffU << UARTx_TODR_TXDLY_LEN_Pos) åUARTx_TODR_RXTO_LEN_Pos 0 æUARTx_TODR_RXTO_LEN_Msk (0xffU << UARTx_TODR_RXTO_LEN_Pos) èUARTx_RXBUF_RXBUF_Pos 0 éUARTx_RXBUF_RXBUF_Msk (0x1ffU << UARTx_RXBUF_RXBUF_Pos) ëUARTx_TXBUF_TXBUF_Pos 0 ìUARTx_TXBUF_TXBUF_Msk (0x1ffU << UARTx_TXBUF_TXBUF_Pos) îUARTx_BRG_SPBRG_Pos 0 ïUARTx_BRG_SPBRG_Msk (0xffffU << UARTx_BRG_SPBRG_Pos) t i ..\Drivers\ ..\Core\Include\ fm33a0xxev_uart.h FM33A0XXEV.h fm33a0xxev_CMU.h
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..\Drivers\fm33a0xxev_uart.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM ÕRxInt TxInt PUART_IntTypeDef ¾ ¢Seven7Bit Eight8Bit Nine9Bit Six6Bit PUART_DataBitTypeDef ì %ÙNONE EVEN ODD PUART_ParityBitTypeDef =,OneBit TwoBit PUART_StopBitTypeDef v2* BaudRate f # DataBit "# ParityBit Y# StopBit # ClockSrc f # PUART_SInitTypeDef ª;*þ RXBF_IE # TXBE_IE # TXSE_IE # SPBRG f # PDSEL f # PARITY f # RXTO_IE # ERRIE # RXEN # STOPSEL f # TXEN # IREN # RXDFLAG # TXDFLAG # PUART_InitTypeDef M __FM33A0XXEV_LPTIM_H LPTIM_CFGR_ETR_AFEN_Pos 24 LPTIM_CFGR_ETR_AFEN_Msk (0x1U << LPTIM_CFGR_ETR_AFEN_Pos) LPTIM_CFGR_PSCSEL_Pos 14 #LPTIM_CFGR_PSCSEL_Msk (0x1U << LPTIM_CFGR_PSCSEL_Pos) $LPTIM_CFGR_PSCSEL_CLKSEL (0x0U << LPTIM_CFGR_PSCSEL_Pos) %LPTIM_CFGR_PSCSEL_LPTETRF (0x1U << LPTIM_CFGR_PSCSEL_Pos) 'LPTIM_CFGR_DIVSEL_Pos 10 0LPTIM_CFGR_DIVSEL_Msk (0x7U << LPTIM_CFGR_DIVSEL_Pos) 1LPTIM_CFGR_DIVSEL_DIV1 (0x0U << LPTIM_CFGR_DIVSEL_Pos) 2LPTIM_CFGR_DIVSEL_DIV2 (0x1U << LPTIM_CFGR_DIVSEL_Pos) 3LPTIM_CFGR_DIVSEL_DIV4 (0x2U << LPTIM_CFGR_DIVSEL_Pos) 4LPTIM_CFGR_DIVSEL_DIV8 (0x3U << LPTIM_CFGR_DIVSEL_Pos) 5LPTIM_CFGR_DIVSEL_DIV16 (0x4U << LPTIM_CFGR_DIVSEL_Pos) 6LPTIM_CFGR_DIVSEL_DIV32 (0x5U << LPTIM_CFGR_DIVSEL_Pos) 7LPTIM_CFGR_DIVSEL_DIV64 (0x6U << LPTIM_CFGR_DIVSEL_Pos) 8LPTIM_CFGR_DIVSEL_DIV128 (0x7U << LPTIM_CFGR_DIVSEL_Pos) :LPTIM_CFGR_EDGESEL_Pos 7 =LPTIM_CFGR_EDGESEL_Msk (0x1U << LPTIM_CFGR_EDGESEL_Pos) >LPTIM_CFGR_EDGESEL_RISING (0x0U << LPTIM_CFGR_EDGESEL_Pos) ?LPTIM_CFGR_EDGESEL_FALLING (0x1U << LPTIM_CFGR_EDGESEL_Pos) ALPTIM_CFGR_TRIGCFG_Pos 5 ELPTIM_CFGR_TRIGCFG_Msk (0x3U << LPTIM_CFGR_TRIGCFG_Pos) FLPTIM_CFGR_TRIGCFG_RISING (0x0U << LPTIM_CFGR_TRIGCFG_Pos) GLPTIM_CFGR_TRIGCFG_FALLING (0x1U << LPTIM_CFGR_TRIGCFG_Pos) HLPTIM_CFGR_TRIGCFG_EXTERNAL (0x2U << LPTIM_CFGR_TRIGCFG_Pos) JLPTIM_CFGR_ONST_Pos 2 MLPTIM_CFGR_ONST_Msk (0x1U << LPTIM_CFGR_ONST_Pos) NLPTIM_CFGR_ONST_CONTINUE (0x0U << LPTIM_CFGR_ONST_Pos) OLPTIM_CFGR_ONST_SINGLE (0x1U << LPTIM_CFGR_ONST_Pos) QLPTIM_CFGR_TMODE_Pos 0 VLPTIM_CFGR_TMODE_Msk (0x3U << LPTIM_CFGR_TMODE_Pos) WLPTIM_CFGR_TMODE_COUNTER (0x0U << LPTIM_CFGR_TMODE_Pos) XLPTIM_CFGR_TMODE_PULSE (0x1U << LPTIM_CFGR_TMODE_Pos) YLPTIM_CFGR_TMODE_ASY (0x2U << LPTIM_CFGR_TMODE_Pos) ZLPTIM_CFGR_TMODE_TIMEOUT (0x3U << LPTIM_CFGR_TMODE_Pos) \LPTIM_CNTR_CNT32_Pos 0 ]LPTIM_CNTR_CNT32_Msk (0xffffffffU << LPTIM_CNTR_CNT32_Pos) _LPTIM_CCSR_CAP1SSEL_Pos 24 dLPTIM_CCSR_CAP1SSEL_Msk (0x3U << LPTIM_CCSR_CAP1SSEL_Pos) eLPTIM_CCSR_CAP1SSEL_LPT_CH1 (0x0U << LPTIM_CCSR_CAP1SSEL_Pos) fLPTIM_CCSR_CAP1SSEL_XTLF (0x1U << LPTIM_CCSR_CAP1SSEL_Pos) gLPTIM_CCSR_CAP1SSEL_RCLP (0x2U << LPTIM_CCSR_CAP1SSEL_Pos) hLPTIM_CCSR_CAP1SSEL_RCMF (0x3U << LPTIM_CCSR_CAP1SSEL_Pos) jLPTIM_CCSR_CAP4EDGE_Pos 23 mLPTIM_CCSR_CAP4EDGE_Msk (0x1U << LPTIM_CCSR_CAP4EDGE_Pos) nLPTIM_CCSR_CAP4EDGE_RISING (0x0U << LPTIM_CCSR_CAP4EDGE_Pos) oLPTIM_CCSR_CAP4EDGE_FALLING (0x1U << LPTIM_CCSR_CAP4EDGE_Pos) qLPTIM_CCSR_CAP3EDGE_Pos 22 rLPTIM_CCSR_CAP3EDGE_Msk (0x1U << LPTIM_CCSR_CAP3EDGE_Pos) sLPTIM_CCSR_CAP3EDGE_RISING (0x0U << LPTIM_CCSR_CAP3EDGE_Pos) tLPTIM_CCSR_CAP3EDGE_FALLING (0x1U << LPTIM_CCSR_CAP3EDGE_Pos) vLPTIM_CCSR_CAP2EDGE_Pos 21 wLPTIM_CCSR_CAP2EDGE_Msk (0x1U << LPTIM_CCSR_CAP2EDGE_Pos) xLPTIM_CCSR_CAP2EDGE_RISING (0x0U << LPTIM_CCSR_CAP2EDGE_Pos) yLPTIM_CCSR_CAP2EDGE_FALLING (0x1U << LPTIM_CCSR_CAP2EDGE_Pos) {LPTIM_CCSR_CAP1EDGE_Pos 20 |LPTIM_CCSR_CAP1EDGE_Msk (0x1U << LPTIM_CCSR_CAP1EDGE_Pos) }LPTIM_CCSR_CAP1EDGE_RISING (0x0U << LPTIM_CCSR_CAP1EDGE_Pos) ~LPTIM_CCSR_CAP1EDGE_FALLING (0x1U << LPTIM_CCSR_CAP1EDGE_Pos) LPTIM_CCSR_POLAR4_Pos 19 LPTIM_CCSR_POLAR4_Msk (0x1U << LPTIM_CCSR_POLAR4_Pos) LPTIM_CCSR_POLAR4_POS (0x0U << LPTIM_CCSR_POLAR4_Pos)
LPTIM_CCSR_POLAR4_NEG (0x1U << LPTIM_CCSR_POLAR4_Pos) LPTIM_CCSR_POLAR3_Pos 18 LPTIM_CCSR_POLAR3_Msk (0x1U << LPTIM_CCSR_POLAR3_Pos) LPTIM_CCSR_POLAR3_POS (0x0U << LPTIM_CCSR_POLAR3_Pos) LPTIM_CCSR_POLAR3_NEG (0x1U << LPTIM_CCSR_POLAR3_Pos) LPTIM_CCSR_POLAR2_Pos 17 LPTIM_CCSR_POLAR2_Msk (0x1U << LPTIM_CCSR_POLAR2_Pos) LPTIM_CCSR_POLAR2_POS (0x0U << LPTIM_CCSR_POLAR2_Pos) LPTIM_CCSR_POLAR2_NEG (0x1U << LPTIM_CCSR_POLAR2_Pos) LPTIM_CCSR_POLAR1_Pos 16 LPTIM_CCSR_POLAR1_Msk (0x1U << LPTIM_CCSR_POLAR1_Pos) LPTIM_CCSR_POLAR1_POS (0x0U << LPTIM_CCSR_POLAR1_Pos) LPTIM_CCSR_POLAR1_NEG (0x1U << LPTIM_CCSR_POLAR1_Pos) LPTIM_CCSR_CAPCFG4_Pos 14 LPTIM_CCSR_CAPCFG4_Msk (0x3U << LPTIM_CCSR_CAPCFG4_Pos) LPTIM_CCSR_CAPCFG4_RISING (0x0U << LPTIM_CCSR_CAPCFG4_Pos) LPTIM_CCSR_CAPCFG4_FALLING (0x1U << LPTIM_CCSR_CAPCFG4_Pos) LPTIM_CCSR_CAPCFG4_BOTH (0x2U << LPTIM_CCSR_CAPCFG4_Pos) LPTIM_CCSR_CAPCFG3_Pos 12 ¡LPTIM_CCSR_CAPCFG3_Msk (0x3U << LPTIM_CCSR_CAPCFG3_Pos) ¢LPTIM_CCSR_CAPCFG3_RISING (0x0U << LPTIM_CCSR_CAPCFG3_Pos) £LPTIM_CCSR_CAPCFG3_FALLING (0x1U << LPTIM_CCSR_CAPCFG3_Pos) ¤LPTIM_CCSR_CAPCFG3_BOTH (0x2U << LPTIM_CCSR_CAPCFG3_Pos) ¦LPTIM_CCSR_CAPCFG2_Pos 10 §LPTIM_CCSR_CAPCFG2_Msk (0x3U << LPTIM_CCSR_CAPCFG2_Pos) ¨LPTIM_CCSR_CAPCFG2_RISING (0x0U << LPTIM_CCSR_CAPCFG2_Pos) ©LPTIM_CCSR_CAPCFG2_FALLING (0x1U << LPTIM_CCSR_CAPCFG2_Pos) ªLPTIM_CCSR_CAPCFG2_BOTH (0x2U << LPTIM_CCSR_CAPCFG2_Pos) ¬LPTIM_CCSR_CAPCFG1_Pos 8 LPTIM_CCSR_CAPCFG1_Msk (0x3U << LPTIM_CCSR_CAPCFG1_Pos) ®LPTIM_CCSR_CAPCFG1_RISING (0x0U << LPTIM_CCSR_CAPCFG1_Pos) ¯LPTIM_CCSR_CAPCFG1_FALLING (0x1U << LPTIM_CCSR_CAPCFG1_Pos) °LPTIM_CCSR_CAPCFG1_BOTH (0x2U << LPTIM_CCSR_CAPCFG1_Pos) ²LPTIM_CCSR_CC4S_Pos 6 ¶LPTIM_CCSR_CC4S_Msk (0x3U << LPTIM_CCSR_CC4S_Pos) ·LPTIM_CCSR_CC4S_NON (0x0U << LPTIM_CCSR_CC4S_Pos) ¸LPTIM_CCSR_CC4S_LPT_CH4_IN (0x1U << LPTIM_CCSR_CC4S_Pos) ¹LPTIM_CCSR_CC4S_LPT_CH4_OUT (0x2U << LPTIM_CCSR_CC4S_Pos) »LPTIM_CCSR_CC3S_Pos 4 ¼LPTIM_CCSR_CC3S_Msk (0x3U << LPTIM_CCSR_CC3S_Pos) ½LPTIM_CCSR_CC3S_NON (0x0U << LPTIM_CCSR_CC3S_Pos) ¾LPTIM_CCSR_CC3S_LPT_CH3_IN (0x1U << LPTIM_CCSR_CC3S_Pos) ¿LPTIM_CCSR_CC3S_LPT_CH3_OUT (0x2U << LPTIM_CCSR_CC3S_Pos) ÁLPTIM_CCSR_CC2S_Pos 2 ÂLPTIM_CCSR_CC2S_Msk (0x3U << LPTIM_CCSR_CC2S_Pos) ÃLPTIM_CCSR_CC2S_NON (0x0U << LPTIM_CCSR_CC2S_Pos) ÄLPTIM_CCSR_CC2S_LPT_CH2_IN (0x1U << LPTIM_CCSR_CC2S_Pos) ÅLPTIM_CCSR_CC2S_LPT_CH2_OUT (0x2U << LPTIM_CCSR_CC2S_Pos) ÇLPTIM_CCSR_CC1S_Pos 0 ÈLPTIM_CCSR_CC1S_Msk (0x3U << LPTIM_CCSR_CC1S_Pos) ÉLPTIM_CCSR_CC1S_NON (0x0U << LPTIM_CCSR_CC1S_Pos) ÊLPTIM_CCSR_CC1S_LPT_CH1_IN (0x1U << LPTIM_CCSR_CC1S_Pos) ËLPTIM_CCSR_CC1S_LPT_CH1_OUT (0x2U << LPTIM_CCSR_CC1S_Pos) ÍLPTIM_ARR_ARR_Pos 0 ÏLPTIM_ARR_ARR_Msk (0xffffffffU << LPTIM_ARR_ARR_Pos) ÑLPTIM_IER_OVR4IE_Pos 11 ÔLPTIM_IER_OVR4IE_Msk (0x1U << LPTIM_IER_OVR4IE_Pos) ØLPTIM_IER_OVR3IE_Pos 10 ÛLPTIM_IER_OVR3IE_Msk (0x1U << LPTIM_IER_OVR3IE_Pos) ßLPTIM_IER_OVR2IE_Pos 9 âLPTIM_IER_OVR2IE_Msk (0x1U << LPTIM_IER_OVR2IE_Pos) æLPTIM_IER_OVR1IE_Pos 8 éLPTIM_IER_OVR1IE_Msk (0x1U << LPTIM_IER_OVR1IE_Pos) íLPTIM_IER_TRIGIE_Pos 7 ðLPTIM_IER_TRIGIE_Msk (0x1U << LPTIM_IER_TRIGIE_Pos) ôLPTIM_IER_OVIE_Pos 6 ÷LPTIM_IER_OVIE_Msk (0x1U << LPTIM_IER_OVIE_Pos) ûLPTIM_IER_CC4IE_Pos 3 þLPTIM_IER_CC4IE_Msk (0x1U << LPTIM_IER_CC4IE_Pos) LPTIM_IER_CC3IE_Pos 2
LPTIM_IER_CC3IE_Msk (0x1U << LPTIM_IER_CC3IE_Pos) LPTIM_IER_CC2IE_Pos 1 LPTIM_IER_CC2IE_Msk (0x1U << LPTIM_IER_CC2IE_Pos) LPTIM_IER_CC1IE_Pos 0 LPTIM_IER_CC1IE_Msk (0x1U << LPTIM_IER_CC1IE_Pos) LPTIM_ISR_CAP4OVR_Pos 11 LPTIM_ISR_CAP4OVR_Msk (0x1U << LPTIM_ISR_CAP4OVR_Pos) LPTIM_ISR_CAP3OVR_Pos 10 LPTIM_ISR_CAP3OVR_Msk (0x1U << LPTIM_ISR_CAP3OVR_Pos) LPTIM_ISR_CAP2OVR_Pos 9 LPTIM_ISR_CAP2OVR_Msk (0x1U << LPTIM_ISR_CAP2OVR_Pos) LPTIM_ISR_CAP1OVR_Pos 8 ¡LPTIM_ISR_CAP1OVR_Msk (0x1U << LPTIM_ISR_CAP1OVR_Pos) £LPTIM_ISR_TRIGIF_Pos 7 ¤LPTIM_ISR_TRIGIF_Msk (0x1U << LPTIM_ISR_TRIGIF_Pos) ¦LPTIM_ISR_OVIF_Pos 6 §LPTIM_ISR_OVIF_Msk (0x1U << LPTIM_ISR_OVIF_Pos) ©LPTIM_ISR_CC4IF_Pos 3 ªLPTIM_ISR_CC4IF_Msk (0x1U << LPTIM_ISR_CC4IF_Pos) ¬LPTIM_ISR_CC3IF_Pos 2 LPTIM_ISR_CC3IF_Msk (0x1U << LPTIM_ISR_CC3IF_Pos) ¯LPTIM_ISR_CC2IF_Pos 1 °LPTIM_ISR_CC2IF_Msk (0x1U << LPTIM_ISR_CC2IF_Pos) ²LPTIM_ISR_CC1IF_Pos 0 ³LPTIM_ISR_CC1IF_Msk (0x1U << LPTIM_ISR_CC1IF_Pos) µLPTIM_CR_EN_Pos 0 ¸LPTIM_CR_EN_Msk (0x1U << LPTIM_CR_EN_Pos) ¼LPTIM_CCR1_CCR1_Pos 0 ½LPTIM_CCR1_CCR1_Msk (0xffffffffU << LPTIM_CCR1_CCR1_Pos) ¿LPTIM_CCR2_CCR2_Pos 0 ÀLPTIM_CCR2_CCR2_Msk (0xffffffffU << LPTIM_CCR2_CCR2_Pos) ÂLPTIM_CCR3_CCR3_Pos 0 ÃLPTIM_CCR3_CCR3_Msk (0xffffffffU << LPTIM_CCR3_CCR3_Pos) ÅLPTIM_CCR4_CCR4_Pos 0 ÆLPTIM_CCR4_CCR4_Msk (0xffffffffU << LPTIM_CCR4_CCR4_Pos) ` V ..\Drivers\ ..\Core\Include\ fm33a0xxev_lptim.h FM33A0XXEV.h À
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..\Drivers\fm33a0xxev_lptim.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM
__FM33A0XXEV_WWDT_H WWDT_CR_CON_Pos 0 WWDT_CR_CON_Msk (0xffU << WWDT_CR_CON_Pos) WWDT_CFGR_CFG_Pos 0 &WWDT_CFGR_CFG_Msk (0x7U << WWDT_CFGR_CFG_Pos) (WWDT_CNTR_CNT_Pos 0 )WWDT_CNTR_CNT_Msk (0x3ffU << WWDT_CNTR_CNT_Pos) +WWDT_IER_IE_Pos 0 .WWDT_IER_IE_Msk (0x1U << WWDT_IER_IE_Pos) 2WWDT_ISR_NOVF_Pos 0 6WWDT_ISR_NOVF_Msk (0x1U << WWDT_ISR_NOVF_Pos) 8WWDT_PSCR_DIV_CNT_Pos 0 9WWDT_PSCR_DIV_CNT_Msk (0xfffU << WWDT_PSCR_DIV_CNT_Pos) ` U ..\Drivers\ ..\Core\Include\ fm33a0xxev_wwdt.h FM33A0XXEV.h ¼
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..\Drivers\fm33a0xxev_wwdt.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM __FM33A0XXEV_SVD_H %SVD_CFGR_LVL_Pos 4 'SVD_CFGR_LVL_Msk (0xfU << SVD_CFGR_LVL_Pos) (SVD_CFGR_LVL_1P800V (0x0U << SVD_CFGR_LVL_Pos) )SVD_CFGR_LVL_2P014V (0x1U << SVD_CFGR_LVL_Pos) *SVD_CFGR_LVL_2P229V (0x2U << SVD_CFGR_LVL_Pos) +SVD_CFGR_LVL_2P443V (0x3U << SVD_CFGR_LVL_Pos) ,SVD_CFGR_LVL_2P657V (0x4U << SVD_CFGR_LVL_Pos) -SVD_CFGR_LVL_2P871V (0x5U << SVD_CFGR_LVL_Pos) .SVD_CFGR_LVL_3P086V (0x6U << SVD_CFGR_LVL_Pos) /SVD_CFGR_LVL_3P300V (0x7U << SVD_CFGR_LVL_Pos) 0SVD_CFGR_LVL_3P514V (0x8U << SVD_CFGR_LVL_Pos) 1SVD_CFGR_LVL_3P729V (0x9U << SVD_CFGR_LVL_Pos) 2SVD_CFGR_LVL_3P943V (0xaU << SVD_CFGR_LVL_Pos) 3SVD_CFGR_LVL_4P157V (0xbU << SVD_CFGR_LVL_Pos) 4SVD_CFGR_LVL_4P371V (0xcU << SVD_CFGR_LVL_Pos) 5SVD_CFGR_LVL_4P586V (0xdU << SVD_CFGR_LVL_Pos) 6SVD_CFGR_LVL_4P800V (0xeU << SVD_CFGR_LVL_Pos) 7SVD_CFGR_LVL_SVS (0xfU << SVD_CFGR_LVL_Pos) 9SVD_CFGR_DFEN_Pos 3 =SVD_CFGR_DFEN_Msk (0x1U << SVD_CFGR_DFEN_Pos) ASVD_CFGR_MOD_Pos 2 FSVD_CFGR_MOD_Msk (0x1U << SVD_CFGR_MOD_Pos) GSVD_CFGR_MOD_INTERVAL (0x1U << SVD_CFGR_MOD_Pos) HSVD_CFGR_MOD_ALWAYSON (0x0U << SVD_CFGR_MOD_Pos) JSVD_CFGR_ITVL_Pos 0 OSVD_CFGR_ITVL_Msk (0x3U << SVD_CFGR_ITVL_Pos) PSVD_CFGR_ITVL_62P5MS (0x0U << SVD_CFGR_ITVL_Pos) QSVD_CFGR_ITVL_256MS (0x1U << SVD_CFGR_ITVL_Pos) RSVD_CFGR_ITVL_1S (0x2U << SVD_CFGR_ITVL_Pos) SSVD_CFGR_ITVL_4S (0x3U << SVD_CFGR_ITVL_Pos) XSVD_CR_TE_Pos 8 YSVD_CR_TE_Msk (0x1U << SVD_CR_TE_Pos) [SVD_CR_SVSEN_Pos 1 `SVD_CR_SVSEN_Msk (0x1U << SVD_CR_SVSEN_Pos) dSVD_CR_SVDEN_Pos 0 eSVD_CR_SVDEN_Msk (0x1U << SVD_CR_SVDEN_Pos) gSVD_IER_PFIE_Pos 1 hSVD_IER_PFIE_Msk (0x1U << SVD_IER_PFIE_Pos) jSVD_IER_PRIE_Pos 0 kSVD_IER_PRIE_Msk (0x1U << SVD_IER_PRIE_Pos) mSVD_ISR_SVDO_Pos 8 pSVD_ISR_SVDO_Msk (0x1U << SVD_ISR_SVDO_Pos) rSVD_ISR_SVDR_Pos 7 tSVD_ISR_SVDR_Msk (0x1U << SVD_ISR_SVDR_Pos) vSVD_ISR_PFF_Pos 1 wSVD_ISR_PFF_Msk (0x1U << SVD_ISR_PFF_Pos) ySVD_ISR_PRF_Pos 0 zSVD_ISR_PRF_Msk (0x1U << SVD_ISR_PRF_Pos) |SVD_VSR_V1P0EN_Pos 2 SVD_VSR_V1P0EN_Msk (0x1U << SVD_VSR_V1P0EN_Pos) SVD_VSR_V0P95EN_Pos 1 SVD_VSR_V0P95EN_Msk (0x1U << SVD_VSR_V0P95EN_Pos) SVD_VSR_V0P9EN_Pos 0 SVD_VSR_V0P9EN_Msk (0x1U << SVD_VSR_V0P9EN_Pos) ` T ..\Drivers\ ..\Core\Include\ fm33a0xxev_svd.h FM33A0XXEV.h D
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..\Drivers\fm33a0xxev_svd.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM *¬ SVDMOD f # SVDITVL f # SVDLVL f # DFEN # PFIE # PRIE # SVDEN # PSVD_InitTypeDef ½ # __FM33A0XXEV_PAE_H ECC_STD_DBL 0x00 ECC_STD_ADD 0x01 ECC_ALG1_DBLADD 0x02 ECC_ALG2_ECDBL 0x03 ECC_ALG2_ECADDDBL 0x04 ECC_ALG2_YRECOVER 0x05 'PAE_CSR_DATA_TYPE_Pos 8 -PAE_CSR_DATA_TYPE_Msk (0x3U << PAE_CSR_DATA_TYPE_Pos) .PAE_CSR_DATA_TYPE_NONE (0x0U << PAE_CSR_DATA_TYPE_Pos) /PAE_CSR_DATA_TYPE_HALFWORD (0x1U << PAE_CSR_DATA_TYPE_Pos) 0PAE_CSR_DATA_TYPE_BYTE (0x2U << PAE_CSR_DATA_TYPE_Pos) 1PAE_CSR_DATA_TYPE_BIT (0x3U << PAE_CSR_DATA_TYPE_Pos) 3PAE_CSR_START_Pos 7 4PAE_CSR_START_Msk (0x1U << PAE_CSR_START_Pos) 6PAE_CSR_RUN_MODE_Pos 4 ;PAE_CSR_RUN_MODE_Msk (0x3U << PAE_CSR_RUN_MODE_Pos) <PAE_CSR_RUN_MODE_MOD (0x0U << PAE_CSR_RUN_MODE_Pos) =PAE_CSR_RUN_MODE_DOT (0x1U << PAE_CSR_RUN_MODE_Pos) >PAE_CSR_RUN_MODE_RSA (0x2U << PAE_CSR_RUN_MODE_Pos) ?PAE_CSR_RUN_MODE_ECC (0x3U << PAE_CSR_RUN_MODE_Pos) APAE_CSR_SOFT_RST_Pos 3 CPAE_CSR_SOFT_RST_Msk (0x1U << PAE_CSR_SOFT_RST_Pos) FPAE_CSR_PAEIE_Pos 2 IPAE_CSR_PAEIE_Msk (0x1U << PAE_CSR_PAEIE_Pos) JPAE_CSR_PAEIE_ENABLE (0x1U << PAE_CSR_PAEIE_Pos) KPAE_CSR_PAEIE_DISABLE (0x0U << PAE_CSR_PAEIE_Pos) MPAE_CSR_PAEIF_Pos 1 NPAE_CSR_PAEIF_Msk (0x1U << PAE_CSR_PAEIF_Pos) PPAE_CSR_BUSY_Pos 0 SPAE_CSR_BUSY_Msk (0x1U << PAE_CSR_BUSY_Pos) UPAE_MLR_PAE_MLR_Pos 0 YPAE_MLR_PAE_MLR_Msk (0x3fU << PAE_MLR_PAE_MLR_Pos) [PAE_MPR_PAE_MPR_Pos 0 \PAE_MPR_PAE_MPR_Msk (0xffffffffU << PAE_MPR_PAE_MPR_Pos) ^PAE_M0CFG_BLKCFG_Pos 15 aPAE_M0CFG_BLKCFG_Msk (0x1U << PAE_M0CFG_BLKCFG_Pos) bPAE_M0CFG_BLKCFG_16BLOCK (0x1U << PAE_M0CFG_BLKCFG_Pos) cPAE_M0CFG_BLKCFG_4BLOCK (0x0U << PAE_M0CFG_BLKCFG_Pos) ePAE_M0CFG_INS_M0_Pos 12 jPAE_M0CFG_INS_M0_Msk (0x3U << PAE_M0CFG_INS_M0_Pos) kPAE_M0CFG_INS_M0_MUL (0x0U << PAE_M0CFG_INS_M0_Pos) lPAE_M0CFG_INS_M0_ADD (0x1U << PAE_M0CFG_INS_M0_Pos) mPAE_M0CFG_INS_M0_SUB (0x3U << PAE_M0CFG_INS_M0_Pos) oPAE_M0CFG_RES_BLK_Pos 8 rPAE_M0CFG_RES_BLK_Msk (0xfU << PAE_M0CFG_RES_BLK_Pos) sPAE_M0CFG_RES_BLK_BLOCK0 (0x0U << PAE_M0CFG_RES_BLK_Pos) tPAE_M0CFG_RES_BLK_BLOCK1 (0x1U << PAE_M0CFG_RES_BLK_Pos) uPAE_M0CFG_RES_BLK_BLOCK2 (0x2U << PAE_M0CFG_RES_BLK_Pos) vPAE_M0CFG_RES_BLK_BLOCK3 (0x3U << PAE_M0CFG_RES_BLK_Pos) wPAE_M0CFG_RES_BLK_BLOCK4 (0x4U << PAE_M0CFG_RES_BLK_Pos) xPAE_M0CFG_RES_BLK_BLOCK5 (0x5U << PAE_M0CFG_RES_BLK_Pos) yPAE_M0CFG_RES_BLK_BLOCK6 (0x6U << PAE_M0CFG_RES_BLK_Pos) zPAE_M0CFG_RES_BLK_BLOCK7 (0x7U << PAE_M0CFG_RES_BLK_Pos) {PAE_M0CFG_RES_BLK_BLOCK8 (0x8U << PAE_M0CFG_RES_BLK_Pos) |PAE_M0CFG_RES_BLK_BLOCK9 (0x9U << PAE_M0CFG_RES_BLK_Pos) }PAE_M0CFG_RES_BLK_BLOCK10 (0xAU << PAE_M0CFG_RES_BLK_Pos) ~PAE_M0CFG_RES_BLK_BLOCK11 (0xBU << PAE_M0CFG_RES_BLK_Pos) PAE_M0CFG_RES_BLK_BLOCK12 (0xCU << PAE_M0CFG_RES_BLK_Pos) PAE_M0CFG_RES_BLK_BLOCK13 (0xDU << PAE_M0CFG_RES_BLK_Pos) PAE_M0CFG_RES_BLK_BLOCK14 (0xEU << PAE_M0CFG_RES_BLK_Pos) PAE_M0CFG_RES_BLK_BLOCK15 (0xFU << PAE_M0CFG_RES_BLK_Pos) PAE_M0CFG_OP1_BLK_Pos 4 PAE_M0CFG_OP1_BLK_Msk (0xfU << PAE_M0CFG_OP1_BLK_Pos) PAE_M0CFG_OP1_BLK_BLOCK0 (0x0U << PAE_M0CFG_OP1_BLK_Pos) PAE_M0CFG_OP1_BLK_BLOCK1 (0x1U << PAE_M0CFG_OP1_BLK_Pos) PAE_M0CFG_OP1_BLK_BLOCK2 (0x2U << PAE_M0CFG_OP1_BLK_Pos) PAE_M0CFG_OP1_BLK_BLOCK3 (0x3U << PAE_M0CFG_OP1_BLK_Pos) PAE_M0CFG_OP1_BLK_BLOCK4 (0x4U << PAE_M0CFG_OP1_BLK_Pos) PAE_M0CFG_OP1_BLK_BLOCK5 (0x5U << PAE_M0CFG_OP1_BLK_Pos) PAE_M0CFG_OP1_BLK_BLOCK6 (0x6U << PAE_M0CFG_OP1_BLK_Pos) PAE_M0CFG_OP1_BLK_BLOCK7 (0x7U << PAE_M0CFG_OP1_BLK_Pos) PAE_M0CFG_OP1_BLK_BLOCK8 (0x8U << PAE_M0CFG_OP1_BLK_Pos) PAE_M0CFG_OP1_BLK_BLOCK9 (0x9U << PAE_M0CFG_OP1_BLK_Pos) PAE_M0CFG_OP1_BLK_BLOCK10 (0xAU << PAE_M0CFG_OP1_BLK_Pos) PAE_M0CFG_OP1_BLK_BLOCK11 (0xBU << PAE_M0CFG_OP1_BLK_Pos) PAE_M0CFG_OP1_BLK_BLOCK12 (0xCU << PAE_M0CFG_OP1_BLK_Pos) PAE_M0CFG_OP1_BLK_BLOCK13 (0xDU << PAE_M0CFG_OP1_BLK_Pos) PAE_M0CFG_OP1_BLK_BLOCK14 (0xEU << PAE_M0CFG_OP1_BLK_Pos) PAE_M0CFG_OP1_BLK_BLOCK15 (0xFU << PAE_M0CFG_OP1_BLK_Pos) ¡PAE_M0CFG_OP2_BLK_Pos 0 ¤PAE_M0CFG_OP2_BLK_Msk (0xfU << PAE_M0CFG_OP2_BLK_Pos) ¥PAE_M0CFG_OP2_BLK_BLOCK0 (0x0U << PAE_M0CFG_OP2_BLK_Pos) ¦PAE_M0CFG_OP2_BLK_BLOCK1 (0x1U << PAE_M0CFG_OP2_BLK_Pos) §PAE_M0CFG_OP2_BLK_BLOCK2 (0x2U << PAE_M0CFG_OP2_BLK_Pos) ¨PAE_M0CFG_OP2_BLK_BLOCK3 (0x3U << PAE_M0CFG_OP2_BLK_Pos) ©PAE_M0CFG_OP2_BLK_BLOCK4 (0x4U << PAE_M0CFG_OP2_BLK_Pos) ªPAE_M0CFG_OP2_BLK_BLOCK5 (0x5U << PAE_M0CFG_OP2_BLK_Pos) «PAE_M0CFG_OP2_BLK_BLOCK6 (0x6U << PAE_M0CFG_OP2_BLK_Pos) ¬PAE_M0CFG_OP2_BLK_BLOCK7 (0x7U << PAE_M0CFG_OP2_BLK_Pos) PAE_M0CFG_OP2_BLK_BLOCK8 (0x8U << PAE_M0CFG_OP2_BLK_Pos) ®PAE_M0CFG_OP2_BLK_BLOCK9 (0x9U << PAE_M0CFG_OP2_BLK_Pos) ¯PAE_M0CFG_OP2_BLK_BLOCK10 (0xAU << PAE_M0CFG_OP2_BLK_Pos) °PAE_M0CFG_OP2_BLK_BLOCK11 (0xBU << PAE_M0CFG_OP2_BLK_Pos) ±PAE_M0CFG_OP2_BLK_BLOCK12 (0xCU << PAE_M0CFG_OP2_BLK_Pos) ²PAE_M0CFG_OP2_BLK_BLOCK13 (0xDU << PAE_M0CFG_OP2_BLK_Pos) ³PAE_M0CFG_OP2_BLK_BLOCK14 (0xEU << PAE_M0CFG_OP2_BLK_Pos) ´PAE_M0CFG_OP2_BLK_BLOCK15 (0xFU << PAE_M0CFG_OP2_BLK_Pos) ·PAE_M1CFG_INS_M1_Pos 4 ÀPAE_M1CFG_INS_M1_Msk (0x7U << PAE_M1CFG_INS_M1_Pos) ÁPAE_M1CFG_INS_M1_JACOBIN (0x0U << PAE_M1CFG_INS_M1_Pos) ÂPAE_M1CFG_INS_M1_MIXADD (0x1U << PAE_M1CFG_INS_M1_Pos) ÃPAE_M1CFG_INS_M1_ECDBL (0x3U << PAE_M1CFG_INS_M1_Pos) ÄPAE_M1CFG_INS_M1_ECADDDBL (0x4U << PAE_M1CFG_INS_M1_Pos) ÅPAE_M1CFG_INS_M1_ECYRECOVER (0x5U << PAE_M1CFG_INS_M1_Pos) ÇPAE_M1CFG_AEN3_M1_Pos 1 ÊPAE_M1CFG_AEN3_M1_Msk (0x1U << PAE_M1CFG_AEN3_M1_Pos) ËPAE_M1CFG_AEN3_M1_NE3 (0x1U << PAE_M1CFG_AEN3_M1_Pos) ÌPAE_M1CFG_AEN3_M1_EQ3 (0x0U << PAE_M1CFG_AEN3_M1_Pos) ÎPAE_M1CFG_BIT_VALUE_M1_Pos 0 ÑPAE_M1CFG_BIT_VALUE_M1_Msk (0x1U << PAE_M1CFG_BIT_VALUE_M1_Pos) ÒPAE_M1CFG_BIT_VALUE_M1_VALUE1 (0x1U << PAE_M1CFG_BIT_VALUE_M1_Pos) ÓPAE_M1CFG_BIT_VALUE_M1_VALUE0 (0x0U << PAE_M1CFG_BIT_VALUE_M1_Pos) ÕPAE_M2CFG_ALWAYS_MULT_Pos 4 ØPAE_M2CFG_ALWAYS_MULT_Msk (0x1U << PAE_M2CFG_ALWAYS_MULT_Pos) ÙPAE_M2CFG_ALWAYS_MULT_ALWAYS (0x1U << PAE_M2CFG_ALWAYS_MULT_Pos) ÚPAE_M2CFG_ALWAYS_MULT_NONE (0x0U << PAE_M2CFG_ALWAYS_MULT_Pos) ÜPAE_M2CFG_FBO_M2_Pos 0 ßPAE_M2CFG_FBO_M2_Msk (0x1U << PAE_M2CFG_FBO_M2_Pos) àPAE_M2CFG_FBO_M2_FB1 (0x1U << PAE_M2CFG_FBO_M2_Pos) áPAE_M2CFG_FBO_M2_NFB1 (0x0U << PAE_M2CFG_FBO_M2_Pos) ãPAE_M3CFG_AEN3_M3_Pos 4 æPAE_M3CFG_AEN3_M3_Msk (0x1U << PAE_M3CFG_AEN3_M3_Pos) çPAE_M3CFG_AEN3_M3_EQ3 (0x1U << PAE_M3CFG_AEN3_M3_Pos) èPAE_M3CFG_AEN3_M3_NE3 (0x0U << PAE_M3CFG_AEN3_M3_Pos) êPAE_M3CFG_FBO_M3_Pos 0 íPAE_M3CFG_FBO_M3_Msk (0x1U << PAE_M3CFG_FBO_M3_Pos) îPAE_M3CFG_FBO_M3_FB1 (0x1U << PAE_M3CFG_FBO_M3_Pos) ïPAE_M3CFG_FBO_M3_NFB1 (0x0U << PAE_M3CFG_FBO_M3_Pos) ñPAE_WORD_PAE_WORD_Pos 0 òPAE_WORD_PAE_WORD_Msk (0xffffffffU << PAE_WORD_PAE_WORD_Pos) ` T ..\Drivers\ ..\Core\Include\ fm33a0xxev_pae.h FM33A0XXEV.h ¼
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..\Drivers\fm33a0xxev_pae.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM __FM33A0XXEV_HASH_H HASH_CSR_START_Pos 7 HASH_CSR_START_Msk (0x1U << HASH_CSR_START_Pos) HASH_CSR_BUSY_Pos 6 HASH_CSR_BUSY_Msk (0x1U << HASH_CSR_BUSY_Pos) HASH_CSR_HASHSEL_Pos 1 HASH_CSR_HASHSEL_Msk (0x1U << HASH_CSR_HASHSEL_Pos) !HASH_CSR_HASHSEL_SHA256 (0x0U << HASH_CSR_HASHSEL_Pos) "HASH_CSR_HASHSEL_SHA1 (0x1U << HASH_CSR_HASHSEL_Pos) $HASH_DTR_DATA_TYPE_Pos 0 +HASH_DTR_DATA_TYPE_Msk (0x3U << HASH_DTR_DATA_TYPE_Pos) ,HASH_DTR_DATA_TYPE_NONE (0x0U << HASH_DTR_DATA_TYPE_Pos) -HASH_DTR_DATA_TYPE_HALFWORD (0x1U << HASH_DTR_DATA_TYPE_Pos) .HASH_DTR_DATA_TYPE_BYTE (0x2U << HASH_DTR_DATA_TYPE_Pos) /HASH_DTR_DATA_TYPE_BIT (0x3U << HASH_DTR_DATA_TYPE_Pos) ` U ..\Drivers\ ..\Core\Include\ fm33a0xxev_hash.h FM33A0XXEV.h ¼
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..\Drivers\fm33a0xxev_hash.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM __FM33A0XXEV_QSPI_H )QSPI_CR_PRESCALER_Pos 24 *QSPI_CR_PRESCALER_Msk (0xffU << QSPI_CR_PRESCALER_Pos) ,QSPI_CR_PMM_Pos 23 /QSPI_CR_PMM_Msk (0x1U << QSPI_CR_PMM_Pos) 0QSPI_CR_PMM_AND (0x0U << QSPI_CR_PMM_Pos) 1QSPI_CR_PMM_OR (0x1U << QSPI_CR_PMM_Pos) 3QSPI_CR_TOIE_Pos 20 6QSPI_CR_TOIE_Msk (0x1U << QSPI_CR_TOIE_Pos) :QSPI_CR_SMIE_Pos 19 =QSPI_CR_SMIE_Msk (0x1U << QSPI_CR_SMIE_Pos) AQSPI_CR_FTIE_Pos 18 DQSPI_CR_FTIE_Msk (0x1U << QSPI_CR_FTIE_Pos) HQSPI_CR_TCIE_Pos 17 KQSPI_CR_TCIE_Msk (0x1U << QSPI_CR_TCIE_Pos) OQSPI_CR_TEIE_Pos 16 RQSPI_CR_TEIE_Msk (0x1U << QSPI_CR_TEIE_Pos) VQSPI_CR_FIFOTHR_Pos 8 aQSPI_CR_FIFOTHR_Msk (0xfU << QSPI_CR_FIFOTHR_Pos) bQSPI_CR_FIFOTHR_1 (0x0U << QSPI_CR_FIFOTHR_Pos) cQSPI_CR_FIFOTHR_2 (0x1U << QSPI_CR_FIFOTHR_Pos) dQSPI_CR_FIFOTHR_3 (0x2U << QSPI_CR_FIFOTHR_Pos) eQSPI_CR_FIFOTHR_4 (0x3U << QSPI_CR_FIFOTHR_Pos) fQSPI_CR_FIFOTHR_5 (0x4U << QSPI_CR_FIFOTHR_Pos) gQSPI_CR_FIFOTHR_6 (0x5U << QSPI_CR_FIFOTHR_Pos) hQSPI_CR_FIFOTHR_7 (0x6U << QSPI_CR_FIFOTHR_Pos) iQSPI_CR_FIFOTHR_8 (0x7U << QSPI_CR_FIFOTHR_Pos) jQSPI_CR_FIFOTHR_9 (0x8U << QSPI_CR_FIFOTHR_Pos) kQSPI_CR_FIFOTHR_10 (0x9U << QSPI_CR_FIFOTHR_Pos) lQSPI_CR_FIFOTHR_11 (0x10U << QSPI_CR_FIFOTHR_Pos) mQSPI_CR_FIFOTHR_12 (0x11U << QSPI_CR_FIFOTHR_Pos) nQSPI_CR_FIFOTHR_13 (0x12U << QSPI_CR_FIFOTHR_Pos) oQSPI_CR_FIFOTHR_14 (0x13U << QSPI_CR_FIFOTHR_Pos) pQSPI_CR_FIFOTHR_15 (0x14U << QSPI_CR_FIFOTHR_Pos) qQSPI_CR_FIFOTHR_16 (0x15U << QSPI_CR_FIFOTHR_Pos) sQSPI_CR_SSHFT_Pos 4 vQSPI_CR_SSHFT_Msk (0x1U << QSPI_CR_SSHFT_Pos) zQSPI_CR_TCEN_Pos 3 ~QSPI_CR_TCEN_Msk (0x1U << QSPI_CR_TCEN_Pos) QSPI_CR_DMAEN_Pos 2
QSPI_CR_DMAEN_Msk (0x1U << QSPI_CR_DMAEN_Pos) QSPI_CR_ABORT_Pos 1 QSPI_CR_ABORT_Msk (0x1U << QSPI_CR_ABORT_Pos) QSPI_CR_EN_Pos 0 QSPI_CR_EN_Msk (0x1U << QSPI_CR_EN_Pos) QSPI_CFG_CSHT_Pos 8 QSPI_CFG_CSHT_Msk (0x7U << QSPI_CFG_CSHT_Pos) QSPI_CFG_CSHT_1CYCLE (0x0U << QSPI_CFG_CSHT_Pos) QSPI_CFG_CSHT_2CYCLES (0x1U << QSPI_CFG_CSHT_Pos) QSPI_CFG_CSHT_3CYCLES (0x2U << QSPI_CFG_CSHT_Pos) QSPI_CFG_CSHT_4CYCLES (0x3U << QSPI_CFG_CSHT_Pos) QSPI_CFG_CSHT_5CYCLES (0x4U << QSPI_CFG_CSHT_Pos) QSPI_CFG_CSHT_6CYCLES (0x5U << QSPI_CFG_CSHT_Pos) QSPI_CFG_CSHT_7CYCLES (0x6U << QSPI_CFG_CSHT_Pos) QSPI_CFG_CSHT_8CYCLES (0x7U << QSPI_CFG_CSHT_Pos) ¢QSPI_CFG_CKMODE_Pos 0 ¥QSPI_CFG_CKMODE_Msk (0x1U << QSPI_CFG_CKMODE_Pos) ¦QSPI_CFG_CKMODE_MODE0 (0x0U << QSPI_CFG_CKMODE_Pos) §QSPI_CFG_CKMODE_MODE3 (0x1U << QSPI_CFG_CKMODE_Pos) ©QSPI_SR_FIFOLVL_Pos 8 ¬QSPI_SR_FIFOLVL_Msk (0x1fU << QSPI_SR_FIFOLVL_Pos) ®QSPI_SR_BUSY_Pos 5 ¯QSPI_SR_BUSY_Msk (0x1U << QSPI_SR_BUSY_Pos) ±QSPI_SR_TOF_Pos 4 ²QSPI_SR_TOF_Msk (0x1U << QSPI_SR_TOF_Pos) ´QSPI_SR_SMF_Pos 3 µQSPI_SR_SMF_Msk (0x1U << QSPI_SR_SMF_Pos) ·QSPI_SR_FTF_Pos 2 ¹QSPI_SR_FTF_Msk (0x1U << QSPI_SR_FTF_Pos) »QSPI_SR_TCF_Pos 1 ¼QSPI_SR_TCF_Msk (0x1U << QSPI_SR_TCF_Pos) ¾QSPI_DATALEN_QSPI_DATALEN_Pos 0 ¿QSPI_DATALEN_QSPI_DATALEN_Msk (0xffffffffU << QSPI_DATALEN_QSPI_DATALEN_Pos) ÁQSPI_CCR_CRM_Pos 28 ÄQSPI_CCR_CRM_Msk (0x1U << QSPI_CCR_CRM_Pos) ÅQSPI_CCR_CRM_ALWAYS (0x0U << QSPI_CCR_CRM_Pos) ÆQSPI_CCR_CRM_ONLY (0x1U << QSPI_CCR_CRM_Pos) ÈQSPI_CCR_OPMODE_Pos 26 ÍQSPI_CCR_OPMODE_Msk (0x3U << QSPI_CCR_OPMODE_Pos) ÎQSPI_CCR_OPMODE_WRITE (0x0U << QSPI_CCR_OPMODE_Pos) ÏQSPI_CCR_OPMODE_READ (0x1U << QSPI_CCR_OPMODE_Pos) ÐQSPI_CCR_OPMODE_QUERY (0x2U << QSPI_CCR_OPMODE_Pos) ÑQSPI_CCR_OPMODE_MAP (0x3U << QSPI_CCR_OPMODE_Pos) ÓQSPI_CCR_DMODE_Pos 24 ØQSPI_CCR_DMODE_Msk (0x3U << QSPI_CCR_DMODE_Pos) ÙQSPI_CCR_DMODE_NONE (0x0U << QSPI_CCR_DMODE_Pos) ÚQSPI_CCR_DMODE_SINGLE (0x1U << QSPI_CCR_DMODE_Pos) ÛQSPI_CCR_DMODE_DOUBLE (0x2U << QSPI_CCR_DMODE_Pos) ÜQSPI_CCR_DMODE_FOUR (0x3U << QSPI_CCR_DMODE_Pos) ÞQSPI_CCR_DUMCYC_Pos 18 ßQSPI_CCR_DUMCYC_Msk (0x1fU << QSPI_CCR_DUMCYC_Pos) áQSPI_CCR_ABSIZE_Pos 16 æQSPI_CCR_ABSIZE_Msk (0x3U << QSPI_CCR_ABSIZE_Pos) çQSPI_CCR_ABSIZE_8BITS (0x0U << QSPI_CCR_ABSIZE_Pos) èQSPI_CCR_ABSIZE_16BITS (0x1U << QSPI_CCR_ABSIZE_Pos) éQSPI_CCR_ABSIZE_24BITS (0x2U << QSPI_CCR_ABSIZE_Pos) êQSPI_CCR_ABSIZE_32BITS (0x3U << QSPI_CCR_ABSIZE_Pos) ìQSPI_CCR_ABMODE_Pos 14 ñQSPI_CCR_ABMODE_Msk (0x3U << QSPI_CCR_ABMODE_Pos) òQSPI_CCR_ABMODE_NONE (0x0U << QSPI_CCR_ABMODE_Pos) óQSPI_CCR_ABMODE_SINGLE (0x1U << QSPI_CCR_ABMODE_Pos) ôQSPI_CCR_ABMODE_DOUBLE (0x2U << QSPI_CCR_ABMODE_Pos) õQSPI_CCR_ABMODE_FOUR (0x3U << QSPI_CCR_ABMODE_Pos) ÷QSPI_CCR_ADSIZE_Pos 12 üQSPI_CCR_ADSIZE_Msk (0x3U << QSPI_CCR_ADSIZE_Pos) ýQSPI_CCR_ADSIZE_8BITS (0x0U << QSPI_CCR_ADSIZE_Pos) þQSPI_CCR_ADSIZE_16BITS (0x1U << QSPI_CCR_ADSIZE_Pos) ÿQSPI_CCR_ADSIZE_24BITS (0x2U << QSPI_CCR_ADSIZE_Pos) QSPI_CCR_ADSIZE_32BITS (0x3U << QSPI_CCR_ADSIZE_Pos) QSPI_CCR_ADMODE_Pos 10 QSPI_CCR_ADMODE_Msk (0x3U << QSPI_CCR_ADMODE_Pos) QSPI_CCR_ADMODE_NONE (0x0U << QSPI_CCR_ADMODE_Pos) QSPI_CCR_ADMODE_SINGLE (0x1U << QSPI_CCR_ADMODE_Pos) QSPI_CCR_ADMODE_DOUBLE (0x2U << QSPI_CCR_ADMODE_Pos) QSPI_CCR_ADMODE_FOUR (0x3U << QSPI_CCR_ADMODE_Pos) QSPI_CCR_IMODE_Pos 8 QSPI_CCR_IMODE_Msk (0x3U << QSPI_CCR_IMODE_Pos) QSPI_CCR_IMODE_NONE (0x0U << QSPI_CCR_IMODE_Pos) QSPI_CCR_IMODE_SINGLE (0x1U << QSPI_CCR_IMODE_Pos) QSPI_CCR_IMODE_DOUBLE (0x2U << QSPI_CCR_IMODE_Pos) QSPI_CCR_IMODE_FOUR (0x3U << QSPI_CCR_IMODE_Pos) QSPI_CCR_INSTRUCTION_Pos 0 QSPI_CCR_INSTRUCTION_Msk (0xffU << QSPI_CCR_INSTRUCTION_Pos) QSPI_ADDR_QSPI_ADDR_Pos 0 QSPI_ADDR_QSPI_ADDR_Msk (0xffffffffU << QSPI_ADDR_QSPI_ADDR_Pos) QSPI_ABR_QSPI_ABR_Pos 0 QSPI_ABR_QSPI_ABR_Msk (0xffffffffU << QSPI_ABR_QSPI_ABR_Pos) ¡QSPI_DR_QSPI_DATA_Pos 0 ¥QSPI_DR_QSPI_DATA_Msk (0xffffffffU << QSPI_DR_QSPI_DATA_Pos) §QSPI_SMSK_QSPI_SMSK_Pos 0 ¨QSPI_SMSK_QSPI_SMSK_Msk (0xffffffffU << QSPI_SMSK_QSPI_SMSK_Pos) ªQSPI_SMAT_QSPI_SMAT_Pos 0 ¬QSPI_SMAT_QSPI_SMAT_Msk (0xffffffffU << QSPI_SMAT_QSPI_SMAT_Pos) ®QSPI_PITV_QSPI_PITV_Pos 0 ¯QSPI_PITV_QSPI_PITV_Msk (0xffffU << QSPI_PITV_QSPI_PITV_Pos) ±QSPI_TO_QSPI_TO_Pos 0 ³QSPI_TO_QSPI_TO_Msk (0xffffU << QSPI_TO_QSPI_TO_Pos) µQSPI_CCR_DUMCYC_SET(value) ((value << QSPI_CCR_DUMCYC_Pos) & QSPI_CCR_DUMCYC_Msk) ¶QSPI_CCR_DUMCYC_GET(value) ((value >> QSPI_CCR_DUMCYC_Pos) & QSPI_CCR_DUMCYC_Msk) ·QSPI_CCR_INSTRUCTION_SET(value) ((value << QSPI_CCR_INSTRUCTION_Pos) & QSPI_CCR_INSTRUCTION_Msk) ¸QSPI_CCR_INSTRUCTION_GET(value) ((value >> QSPI_CCR_INSTRUCTION_Pos) & QSPI_CCR_INSTRUCTION_Msk) ` U ..\Drivers\ ..\Core\Include\ fm33a0xxev_qspi.h FM33A0XXEV.h ¸
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..\Drivers\fm33a0xxev_qspi.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM * ( Instruction f # Address f # AlternateByte f # AddressSize f # AlternateByteSize f # DummyCycles f # InstructionMode f # AddressMode f # AlternateByteMode f # DataMode f #$ PQSPI_CmdTypeDef ¾ ' __FM33A0XXEV_BT_H BTx_CR1_CHEN_Pos 7 BTx_CR1_CHEN_Msk (0x1U << BTx_CR1_CHEN_Pos) BTx_CR1_CLEN_Pos 6 BTx_CR1_CLEN_Msk (0x1U << BTx_CR1_CLEN_Pos) $BTx_CR1_MODE_Pos 5 'BTx_CR1_MODE_Msk (0x1U << BTx_CR1_MODE_Pos) (BTx_CR1_MODE_CAPTURE (0x1U << BTx_CR1_MODE_Pos) )BTx_CR1_MODE_COUNTER (0x0U << BTx_CR1_MODE_Pos) +BTx_CR1_EDGESEL_Pos 4 /BTx_CR1_EDGESEL_Msk (0x1U << BTx_CR1_EDGESEL_Pos) 0BTx_CR1_EDGESEL_FALLING (0x1U << BTx_CR1_EDGESEL_Pos) 1BTx_CR1_EDGESEL_RISING (0x0U << BTx_CR1_EDGESEL_Pos) 3BTx_CR1_CAPMOD_Pos 3 6BTx_CR1_CAPMOD_Msk (0x1U << BTx_CR1_CAPMOD_Pos) 7BTx_CR1_CAPMOD_PULSE (0x1U << BTx_CR1_CAPMOD_Pos) 8BTx_CR1_CAPMOD_CYCLE (0x0U << BTx_CR1_CAPMOD_Pos) :BTx_CR1_CAPCLR_Pos 2 =BTx_CR1_CAPCLR_Msk (0x1U << BTx_CR1_CAPCLR_Pos) ABTx_CR1_CAPONCE_Pos 1 DBTx_CR1_CAPONCE_Msk (0x1U << BTx_CR1_CAPONCE_Pos) EBTx_CR1_CAPONCE_SINGLE (0x1U << BTx_CR1_CAPONCE_Pos) FBTx_CR1_CAPONCE_CONTINUE (0x0U << BTx_CR1_CAPONCE_Pos) HBTx_CR1_PWM_Pos 0 KBTx_CR1_PWM_Msk (0x1U << BTx_CR1_PWM_Pos) OBTx_CR2_SIG2SEL_Pos 7 RBTx_CR2_SIG2SEL_Msk (0x1U << BTx_CR2_SIG2SEL_Pos) SBTx_CR2_SIG2SEL_GROUP2 (0x1U << BTx_CR2_SIG2SEL_Pos) TBTx_CR2_SIG2SEL_GROUP1 (0x0U << BTx_CR2_SIG2SEL_Pos) VBTx_CR2_SIG1SEL_Pos 6 YBTx_CR2_SIG1SEL_Msk (0x1U << BTx_CR2_SIG1SEL_Pos) ZBTx_CR2_SIG1SEL_GROUP1 (0x1U << BTx_CR2_SIG1SEL_Pos) [BTx_CR2_SIG1SEL_GROUP2 (0x0U << BTx_CR2_SIG1SEL_Pos) ]BTx_CR2_CNTHSEL_Pos 4 aBTx_CR2_CNTHSEL_Msk (0x3U << BTx_CR2_CNTHSEL_Pos) bBTx_CR2_CNTHSEL_COUNTER (0x0U << BTx_CR2_CNTHSEL_Pos) cBTx_CR2_CNTHSEL_CAPTURE (0x1U << BTx_CR2_CNTHSEL_Pos) dBTx_CR2_CNTHSEL_INNER (0x2U << BTx_CR2_CNTHSEL_Pos) fBTx_CR2_DIREN_Pos 3 iBTx_CR2_DIREN_Msk (0x1U << BTx_CR2_DIREN_Pos) mBTx_CR2_STDIR_Pos 2 oBTx_CR2_STDIR_Msk (0x1U << BTx_CR2_STDIR_Pos) rBTx_CR2_SRCSEL_Pos 1 uBTx_CR2_SRCSEL_Msk (0x1U << BTx_CR2_SRCSEL_Pos) xBTx_CR2_DIRPO_Pos 0 {BTx_CR2_DIRPO_Msk (0x1U << BTx_CR2_DIRPO_Pos) |BTx_CR2_DIRPO_REVERSE (0x1U << BTx_CR2_DIRPO_Pos) }BTx_CR2_DIRPO_NON (0x0U << BTx_CR2_DIRPO_Pos) BTx_CFGR1_RTCSEL2_Pos 6 BTx_CFGR1_RTCSEL2_Msk (0x3U << BTx_CFGR1_RTCSEL2_Pos)
BTx_CFGR1_RTCSEL2_32768HZ (0x0U << BTx_CFGR1_RTCSEL2_Pos) BTx_CFGR1_RTCSEL2_RTC_SEC (0x1U << BTx_CFGR1_RTCSEL2_Pos) BTx_CFGR1_RTCSEL2_RTC_MIN (0x2U << BTx_CFGR1_RTCSEL2_Pos) BTx_CFGR1_RTCSEL1_Pos 4 BTx_CFGR1_RTCSEL1_Msk (0x3U << BTx_CFGR1_RTCSEL1_Pos) BTx_CFGR1_RTCSEL1_32768HZ (0x0U << BTx_CFGR1_RTCSEL1_Pos) BTx_CFGR1_RTCSEL1_RTC_SEC (0x1U << BTx_CFGR1_RTCSEL1_Pos) BTx_CFGR1_RTCSEL1_RTC_MIN (0x2U << BTx_CFGR1_RTCSEL1_Pos) BTx_CFGR1_GRP2SEL_Pos 2 BTx_CFGR1_GRP2SEL_Msk (0x3U << BTx_CFGR1_GRP2SEL_Pos) BTx_CFGR1_GRP2SEL_APBCLK (0x0U << BTx_CFGR1_GRP2SEL_Pos) BTx_CFGR1_GRP2SEL_RTCOUT2 (0x1U << BTx_CFGR1_GRP2SEL_Pos) BTx_CFGR1_GRP2SEL_IN_SIG2 (0x2U << BTx_CFGR1_GRP2SEL_Pos) BTx_CFGR1_GRP2SEL_EX_SIG2 (0x3U << BTx_CFGR1_GRP2SEL_Pos) BTx_CFGR1_GRP1SEL_Pos 0 ¥BTx_CFGR1_GRP1SEL_Msk (0x3U << BTx_CFGR1_GRP1SEL_Pos) ¦BTx_CFGR1_GRP1SEL_APBCLK (0x0U << BTx_CFGR1_GRP1SEL_Pos) §BTx_CFGR1_GRP1SEL_RTCOUT1 (0x1U << BTx_CFGR1_GRP1SEL_Pos) ¨BTx_CFGR1_GRP1SEL_IN_SIG1 (0x2U << BTx_CFGR1_GRP1SEL_Pos) ©BTx_CFGR1_GRP1SEL_EX_SIG1 (0x3U << BTx_CFGR1_GRP1SEL_Pos) «BTx_CFGR2_EXSEL2_Pos 6 °BTx_CFGR2_EXSEL2_Msk (0x3U << BTx_CFGR2_EXSEL2_Pos) ±BTx_CFGR2_EXSEL2_IN0 (0x0U << BTx_CFGR2_EXSEL2_Pos) ²BTx_CFGR2_EXSEL2_IN1 (0x1U << BTx_CFGR2_EXSEL2_Pos) ³BTx_CFGR2_EXSEL2_IN2 (0x2U << BTx_CFGR2_EXSEL2_Pos) ´BTx_CFGR2_EXSEL2_IN3 (0x3U << BTx_CFGR2_EXSEL2_Pos) ¶BTx_CFGR2_EXSEL1_Pos 4 »BTx_CFGR2_EXSEL1_Msk (0x3U << BTx_CFGR2_EXSEL1_Pos) ¼BTx_CFGR2_EXSEL1_IN0 (0x0U << BTx_CFGR2_EXSEL1_Pos) ½BTx_CFGR2_EXSEL1_IN1 (0x1U << BTx_CFGR2_EXSEL1_Pos) ¾BTx_CFGR2_EXSEL1_IN2 (0x2U << BTx_CFGR2_EXSEL1_Pos) ¿BTx_CFGR2_EXSEL1_IN3 (0x3U << BTx_CFGR2_EXSEL1_Pos) ÁBTx_CFGR2_INSEL2_Pos 2 ÆBTx_CFGR2_INSEL2_Msk (0x3U << BTx_CFGR2_INSEL2_Pos) ÇBTx_CFGR2_INSEL2_RX3 (0x0U << BTx_CFGR2_INSEL2_Pos) ÈBTx_CFGR2_INSEL2_RX4 (0x1U << BTx_CFGR2_INSEL2_Pos) ÉBTx_CFGR2_INSEL2_RX5 (0x2U << BTx_CFGR2_INSEL2_Pos) ÊBTx_CFGR2_INSEL2_RCLP (0x3U << BTx_CFGR2_INSEL2_Pos) ÌBTx_CFGR2_INSEL1_Pos 0 ÑBTx_CFGR2_INSEL1_Msk (0x3U << BTx_CFGR2_INSEL1_Pos) ÒBTx_CFGR2_INSEL1_RX0 (0x0U << BTx_CFGR2_INSEL1_Pos) ÓBTx_CFGR2_INSEL1_RX1 (0x1U << BTx_CFGR2_INSEL1_Pos) ÔBTx_CFGR2_INSEL1_RX2 (0x2U << BTx_CFGR2_INSEL1_Pos) ÕBTx_CFGR2_INSEL1_RCLP (0x3U << BTx_CFGR2_INSEL1_Pos) ×BTx_PRES_PRESCALE_Pos 0 ÙBTx_PRES_PRESCALE_Msk (0xffU << BTx_PRES_PRESCALE_Pos) ÛBTx_LOADCR_LHEN_Pos 4 ÝBTx_LOADCR_LHEN_Msk (0x1U << BTx_LOADCR_LHEN_Pos) ßBTx_LOADCR_LLEN_Pos 0 áBTx_LOADCR_LLEN_Msk (0x1U << BTx_LOADCR_LLEN_Pos) ãBTx_CNTL_CNTL_Pos 0 åBTx_CNTL_CNTL_Msk (0xffU << BTx_CNTL_CNTL_Pos) çBTx_CNTH_CNTH_Pos 0 éBTx_CNTH_CNTH_Msk (0xffU << BTx_CNTH_CNTH_Pos) ëBTx_PRESET_PRESETH_Pos 8 íBTx_PRESET_PRESETH_Msk (0xffU << BTx_PRESET_PRESETH_Pos) ïBTx_PRESET_PRESETL_Pos 0 ñBTx_PRESET_PRESETL_Msk (0xffU << BTx_PRESET_PRESETL_Pos) óBTx_LOADL_LOADL_Pos 0 õBTx_LOADL_LOADL_Msk (0xffU << BTx_LOADL_LOADL_Pos) ÷BTx_LOADH_LOADH_Pos 0 ùBTx_LOADH_LOADH_Msk (0xffU << BTx_LOADH_LOADH_Pos) ûBTx_CMPL_CMPL_Pos 0 ýBTx_CMPL_CMPL_Msk (0xffU << BTx_CMPL_CMPL_Pos) ÿBTx_CMPH_CMPH_Pos 0 BTx_CMPH_CMPH_Msk (0xffU << BTx_CMPH_CMPH_Pos) BTx_OUTCNT_OUTCNT_Pos 0
BTx_OUTCNT_OUTCNT_Msk (0xfffU << BTx_OUTCNT_OUTCNT_Pos) BTx_OCR_OUTCLR_Pos 5 BTx_OCR_OUTCLR_Msk (0x1U << BTx_OCR_OUTCLR_Pos) BTx_OCR_OUTCLR_INVALID (0x0U << BTx_OCR_OUTCLR_Pos) BTx_OCR_OUTCLR_CLEAR (0x1U << BTx_OCR_OUTCLR_Pos) BTx_OCR_OUTINV_Pos 4 BTx_OCR_OUTINV_Msk (0x1U << BTx_OCR_OUTINV_Pos) BTx_OCR_OUTINV_NORMAL (0x0U << BTx_OCR_OUTINV_Pos) BTx_OCR_OUTINV_REVERSE (0x1U << BTx_OCR_OUTINV_Pos) BTx_OCR_OUTMOD_Pos 3 BTx_OCR_OUTMOD_Msk (0x1U << BTx_OCR_OUTMOD_Pos) BTx_OCR_OUTMOD_PULSE_SHIFT (0x0U << BTx_OCR_OUTMOD_Pos) BTx_OCR_OUTMOD_NEG (0x1U << BTx_OCR_OUTMOD_Pos) BTx_OCR_OUTSEL_Pos 0 BTx_OCR_OUTSEL_Msk (0x7U << BTx_OCR_OUTSEL_Pos) BTx_OCR_OUTSEL_HIGH (0x0U << BTx_OCR_OUTSEL_Pos) BTx_OCR_OUTSEL_LOW (0x1U << BTx_OCR_OUTSEL_Pos) BTx_OCR_OUTSEL_GROUP1 (0x2U << BTx_OCR_OUTSEL_Pos) BTx_OCR_OUTSEL_GROUP2 (0x3U << BTx_OCR_OUTSEL_Pos) BTx_OCR_OUTSEL_PWM (0x4U << BTx_OCR_OUTSEL_Pos) BTx_IER_CMPHIE_Pos 4 ¡BTx_IER_CMPHIE_Msk (0x1U << BTx_IER_CMPHIE_Pos) £BTx_IER_CMPLIE_Pos 3 ¦BTx_IER_CMPLIE_Msk (0x1U << BTx_IER_CMPLIE_Pos) ¨BTx_IER_OVHIE_Pos 2 «BTx_IER_OVHIE_Msk (0x1U << BTx_IER_OVHIE_Pos) BTx_IER_OVLIE_Pos 1 °BTx_IER_OVLIE_Msk (0x1U << BTx_IER_OVLIE_Pos) ²BTx_IER_CAPIE_Pos 0 µBTx_IER_CAPIE_Msk (0x1U << BTx_IER_CAPIE_Pos) ·BTx_ISR_EDGESTA_Pos 5 ºBTx_ISR_EDGESTA_Msk (0x1U << BTx_ISR_EDGESTA_Pos) ¼BTx_ISR_CMPHIF_Pos 4 ¿BTx_ISR_CMPHIF_Msk (0x1U << BTx_ISR_CMPHIF_Pos) ÁBTx_ISR_CMPLIF_Pos 3 ÄBTx_ISR_CMPLIF_Msk (0x1U << BTx_ISR_CMPLIF_Pos) ÆBTx_ISR_OVHIF_Pos 2 ÉBTx_ISR_OVHIF_Msk (0x1U << BTx_ISR_OVHIF_Pos) ËBTx_ISR_OVLIF_Pos 1 ÎBTx_ISR_OVLIF_Msk (0x1U << BTx_ISR_OVLIF_Pos) ÐBTx_ISR_CAPIF_Pos 0 ÓBTx_ISR_CAPIF_Msk (0x1U << BTx_ISR_CAPIF_Pos) \ S ..\Drivers\ ..\Core\Include\ fm33a0xxev_bt.h FM33A0XXEV.h ¼
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..\Drivers\fm33a0xxev_bt.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM __FM33A0XXEV_ET_H ETx_CR_OPOL_Pos 10 ETx_CR_OPOL_Msk (0x1U << ETx_CR_OPOL_Pos) ETx_CR_OPOL_NORMAL (0x0U << ETx_CR_OPOL_Pos) ETx_CR_OPOL_REVERSE (0x1U << ETx_CR_OPOL_Pos) ETx_CR_EXFLT_Pos 9 #ETx_CR_EXFLT_Msk (0x1U << ETx_CR_EXFLT_Pos) $ETx_CR_EXFLT_OPEN (0x1U << ETx_CR_EXFLT_Pos) %ETx_CR_EXFLT_CLOSE (0x0U << ETx_CR_EXFLT_Pos) 'ETx_CR_PWM_Pos 8 *ETx_CR_PWM_Msk (0x1U << ETx_CR_PWM_Pos) ,ETx_CR_CEN_Pos 7 /ETx_CR_CEN_Msk (0x1U << ETx_CR_CEN_Pos) 1ETx_CR_MOD_Pos 6 4ETx_CR_MOD_Msk (0x1U << ETx_CR_MOD_Pos) 5ETx_CR_MOD_CAPTURE (0x1U << ETx_CR_MOD_Pos) 6ETx_CR_MOD_COUNTER (0x0U << ETx_CR_MOD_Pos) 8ETx_CR_CASEN_Pos 5 ;ETx_CR_CASEN_Msk (0x1U << ETx_CR_CASEN_Pos) <ETx_CR_CASEN_32BITS (0x1U << ETx_CR_CASEN_Pos) =ETx_CR_CASEN_16BITS (0x0U << ETx_CR_CASEN_Pos) ?ETx_CR_EDGESEL_Pos 4 CETx_CR_EDGESEL_Msk (0x1U << ETx_CR_EDGESEL_Pos) DETx_CR_EDGESEL_FALLING (0x1U << ETx_CR_EDGESEL_Pos) EETx_CR_EDGESEL_RISING (0x0U << ETx_CR_EDGESEL_Pos) GETx_CR_CAPMOD_Pos 3 JETx_CR_CAPMOD_Msk (0x1U << ETx_CR_CAPMOD_Pos) KETx_CR_CAPMOD_PULSE (0x1U << ETx_CR_CAPMOD_Pos) LETx_CR_CAPMOD_CYCLE (0x0U << ETx_CR_CAPMOD_Pos) NETx_CR_CAPCLR_Pos 2 QETx_CR_CAPCLR_Msk (0x1U << ETx_CR_CAPCLR_Pos) TETx_CR_CAPONCE_Pos 1 WETx_CR_CAPONCE_Msk (0x1U << ETx_CR_CAPONCE_Pos) XETx_CR_CAPONCE_SINGLE (0x1U << ETx_CR_CAPONCE_Pos) YETx_CR_CAPONCE_CONTINUE (0x0U << ETx_CR_CAPONCE_Pos) [ETx_CR_CAPEDGE_Pos 0 ^ETx_CR_CAPEDGE_Msk (0x1U << ETx_CR_CAPEDGE_Pos) _ETx_CR_CAPEDGE_FALLING (0x1U << ETx_CR_CAPEDGE_Pos) `ETx_CR_CAPEDGE_RISING (0x0U << ETx_CR_CAPEDGE_Pos) bETx_INSR_SIG2SEL_Pos 7 eETx_INSR_SIG2SEL_Msk (0x1U << ETx_INSR_SIG2SEL_Pos) fETx_INSR_SIG2SEL_GROUP1 (0x1U << ETx_INSR_SIG2SEL_Pos) gETx_INSR_SIG2SEL_GROUP2 (0x0U << ETx_INSR_SIG2SEL_Pos) iETx_INSR_SIG1SEL_Pos 6 lETx_INSR_SIG1SEL_Msk (0x1U << ETx_INSR_SIG1SEL_Pos) mETx_INSR_SIG1SEL_GROUP2 (0x1U << ETx_INSR_SIG1SEL_Pos) nETx_INSR_SIG1SEL_GROUP1 (0x0U << ETx_INSR_SIG1SEL_Pos) pETx_INSR_GRP2SEL_Pos 2 ETx_INSR_GRP2SEL_Msk (0x7U << ETx_INSR_GRP2SEL_Pos) ETx_INSR_GRP2SEL_ET1_UART0_RX (0x0U << ETx_INSR_GRP2SEL_Pos) ETx_INSR_GRP2SEL_ET1_UART1_RX (0x1U << ETx_INSR_GRP2SEL_Pos) ETx_INSR_GRP2SEL_ET1_XTLF (0x2U << ETx_INSR_GRP2SEL_Pos) ETx_INSR_GRP2SEL_ET1_IN1 (0x3U << ETx_INSR_GRP2SEL_Pos) ETx_INSR_GRP2SEL_ET1_IN2 (0x4U << ETx_INSR_GRP2SEL_Pos) ETx_INSR_GRP2SEL_ET1_CMP1O (0x5U << ETx_INSR_GRP2SEL_Pos) ETx_INSR_GRP2SEL_ET1_CMP2O (0x6U << ETx_INSR_GRP2SEL_Pos) ETx_INSR_GRP2SEL_ET1_RCMF (0x7U << ETx_INSR_GRP2SEL_Pos) ETx_INSR_GRP2SEL_ET2_UART2_RX (0x0U << ETx_INSR_GRP2SEL_Pos) ETx_INSR_GRP2SEL_ET2_UART3_RX (0x1U << ETx_INSR_GRP2SEL_Pos) ETx_INSR_GRP2SEL_ET2_XTLF (0x2U << ETx_INSR_GRP2SEL_Pos) ETx_INSR_GRP2SEL_ET2_IN1 (0x3U << ETx_INSR_GRP2SEL_Pos) ETx_INSR_GRP2SEL_ET2_IN2 (0x4U << ETx_INSR_GRP2SEL_Pos) ¡ETx_INSR_GRP2SEL_ET2_CMP1O (0x5U << ETx_INSR_GRP2SEL_Pos) ¢ETx_INSR_GRP2SEL_ET2_CMP2O (0x6U << ETx_INSR_GRP2SEL_Pos) £ETx_INSR_GRP2SEL_ET2_RCMF (0x7U << ETx_INSR_GRP2SEL_Pos) ¤ETx_INSR_GRP2SEL_ET3_IN1 (0x0U << ETx_INSR_GRP2SEL_Pos) ¥ETx_INSR_GRP2SEL_ET3_XTLF (0x1U << ETx_INSR_GRP2SEL_Pos) ¦ETx_INSR_GRP2SEL_ET3_UART4_RX (0x2U << ETx_INSR_GRP2SEL_Pos) §ETx_INSR_GRP2SEL_ET3_UART5_RX (0x3U << ETx_INSR_GRP2SEL_Pos) ¨ETx_INSR_GRP2SEL_ET3_RTCSEC (0x4U << ETx_INSR_GRP2SEL_Pos) ©ETx_INSR_GRP2SEL_ET4_IN (0x0U << ETx_INSR_GRP2SEL_Pos) ªETx_INSR_GRP2SEL_ET4_XTLF (0x1U << ETx_INSR_GRP2SEL_Pos) «ETx_INSR_GRP2SEL_ET4_UART_RX2 (0x2U << ETx_INSR_GRP2SEL_Pos) ¬ETx_INSR_GRP2SEL_ET4_UART_RX0 (0x3U << ETx_INSR_GRP2SEL_Pos) ETx_INSR_GRP2SEL_ET4_CMP1O (0x4U << ETx_INSR_GRP2SEL_Pos) ®ETx_INSR_GRP2SEL_ET4_CMP2O (0x5U << ETx_INSR_GRP2SEL_Pos) ¯ETx_INSR_GRP2SEL_ET4_RTCSEC (0x6U << ETx_INSR_GRP2SEL_Pos) °ETx_INSR_GRP2SEL_ET4_RCMF (0x7U << ETx_INSR_GRP2SEL_Pos) ²ETx_INSR_GRP1SEL_Pos 0 ÇETx_INSR_GRP1SEL_Msk (0x3U << ETx_INSR_GRP1SEL_Pos) ÈETx_INSR_GRP1SEL_ET1_APBCLK (0x0U << ETx_INSR_GRP1SEL_Pos) ÉETx_INSR_GRP1SEL_ET1_XTLF (0x1U << ETx_INSR_GRP1SEL_Pos) ÊETx_INSR_GRP1SEL_ET1_RCLP (0x2U << ETx_INSR_GRP1SEL_Pos) ËETx_INSR_GRP1SEL_ET1_IN0 (0x3U << ETx_INSR_GRP1SEL_Pos) ÌETx_INSR_GRP1SEL_ET2_APBCLK (0x0U << ETx_INSR_GRP1SEL_Pos) ÍETx_INSR_GRP1SEL_ET2_XTLF (0x1U << ETx_INSR_GRP1SEL_Pos) ÎETx_INSR_GRP1SEL_ET2_RCLP (0x2U << ETx_INSR_GRP1SEL_Pos) ÏETx_INSR_GRP1SEL_ET2_IN0 (0x3U << ETx_INSR_GRP1SEL_Pos) ÐETx_INSR_GRP1SEL_ET3_APBCLK (0x0U << ETx_INSR_GRP1SEL_Pos) ÑETx_INSR_GRP1SEL_ET3_IN0 (0x1U << ETx_INSR_GRP1SEL_Pos) ÒETx_INSR_GRP1SEL_ET3_RTCSEC (0x2U << ETx_INSR_GRP1SEL_Pos) ÓETx_INSR_GRP1SEL_ET3_RCLP (0x3U << ETx_INSR_GRP1SEL_Pos) ÔETx_INSR_GRP1SEL_ET4_APBCLK (0x0U << ETx_INSR_GRP1SEL_Pos) ÕETx_INSR_GRP1SEL_ET4_IN0 (0x1U << ETx_INSR_GRP1SEL_Pos) ÖETx_INSR_GRP1SEL_ET4_RTC64HZ (0x2U << ETx_INSR_GRP1SEL_Pos) ×ETx_INSR_GRP1SEL_ET4_RCMF (0x3U << ETx_INSR_GRP1SEL_Pos) ÙETx_PSCR1_PRESCALE1_Pos 0 ÛETx_PSCR1_PRESCALE1_Msk (0xffU << ETx_PSCR1_PRESCALE1_Pos) ÝETx_PSCR2_PRESCALE2_Pos 0 ßETx_PSCR2_PRESCALE2_Msk (0xffU << ETx_PSCR2_PRESCALE2_Pos) áETx_IVR_INITVALUE_Pos 0 âETx_IVR_INITVALUE_Msk (0xffffU << ETx_IVR_INITVALUE_Pos) äETx_CMPR_CMP_Pos 0 æETx_CMPR_CMP_Msk (0xffffU << ETx_CMPR_CMP_Pos) èETx_IER_CMPIE_Pos 2 ëETx_IER_CMPIE_Msk (0x1U << ETx_IER_CMPIE_Pos) íETx_IER_CAPIE_Pos 1 ðETx_IER_CAPIE_Msk (0x1U << ETx_IER_CAPIE_Pos) òETx_IER_OVIE_Pos 0 õETx_IER_OVIE_Msk (0x1U << ETx_IER_OVIE_Pos) ÷ETx_ISR_CMPIF_Pos 3 úETx_ISR_CMPIF_Msk (0x1U << ETx_ISR_CMPIF_Pos) üETx_ISR_EDGESTA_Pos 2 ÿETx_ISR_EDGESTA_Msk (0x1U << ETx_ISR_EDGESTA_Pos) ETx_ISR_CAPIF_Pos 1 ETx_ISR_CAPIF_Msk (0x1U << ETx_ISR_CAPIF_Pos) ETx_ISR_OVIF_Pos 0 ETx_ISR_OVIF_Msk (0x1U << ETx_ISR_OVIF_Pos) ETCNTx_CNT_Pos 0 ETCNTx_CNT_Msk (0xffffU << ETCNTx_CNT_Pos) \ S ..\Drivers\ ..\Core\Include\ fm33a0xxev_et.h FM33A0XXEV.h ¼
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..\Drivers\fm33a0xxev_et.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM ¡ ¢ £ __FM33A0XXEV_VRTC_H HXVAR(object,addr) (*((object *) (addr))) const_rcmf_Trim HXVAR( uint32_t, 0x1FFFFB44 ) const_rclp_Trim HXVAR( uint32_t, 0x1FFFFB20 ) VRTC_PDRCR_CFG_Pos 0 VRTC_PDRCR_CFG_Msk (0x1U << VRTC_PDRCR_CFG_Pos) "VRTC_RCMFCR_EN_Msk (0x1U << VRTC_RCMFCR_EN_Pos) &VRTC_RCMFCR_EN_Pos 7 *VRTC_RCMFCR_EN_Msk (0x1U << VRTC_RCMFCR_EN_Pos) .VRTC_RCMFCR_TRIM_Pos 0 /VRTC_RCMFCR_TRIM_Msk (0x3fU << VRTC_RCMFCR_TRIM_Pos) 1VRTC_RCLPCR_CHOPEN_Pos 1 2VRTC_RCLPCR_CHOPEN_Msk (0x1U << VRTC_RCLPCR_CHOPEN_Pos) 4VRTC_RCLPCR_RCLP_OFF_Pos 0 8VRTC_RCLPCR_RCLP_OFF_Msk (0x1U << VRTC_RCLPCR_RCLP_OFF_Pos) <VRTC_RCLPTR_RCLP_TRIM_Pos 0 ?VRTC_RCLPTR_RCLP_TRIM_Msk (0xffU << VRTC_RCLPTR_RCLP_TRIM_Pos) AVRTC_XTLFCR_XTLFIPW_Pos 0 BVRTC_XTLFCR_XTLFIPW_Msk (0xfU << VRTC_XTLFCR_XTLFIPW_Pos) CVRTC_XTLFCR_XTLFIPW_850NA (0x0U << VRTC_XTLFCR_XTLFIPW_Pos) DVRTC_XTLFCR_XTLFIPW_800NA (0x1U << VRTC_XTLFCR_XTLFIPW_Pos) EVRTC_XTLFCR_XTLFIPW_750NA (0x2U << VRTC_XTLFCR_XTLFIPW_Pos) FVRTC_XTLFCR_XTLFIPW_700NA (0x3U << VRTC_XTLFCR_XTLFIPW_Pos) GVRTC_XTLFCR_XTLFIPW_650NA (0x4U << VRTC_XTLFCR_XTLFIPW_Pos) HVRTC_XTLFCR_XTLFIPW_600NA (0x5U << VRTC_XTLFCR_XTLFIPW_Pos) IVRTC_XTLFCR_XTLFIPW_550NA (0x6U << VRTC_XTLFCR_XTLFIPW_Pos) JVRTC_XTLFCR_XTLFIPW_500NA (0x7U << VRTC_XTLFCR_XTLFIPW_Pos) KVRTC_XTLFCR_XTLFIPW_450NA (0x8U << VRTC_XTLFCR_XTLFIPW_Pos) LVRTC_XTLFCR_XTLFIPW_400NA (0x9U << VRTC_XTLFCR_XTLFIPW_Pos) MVRTC_XTLFCR_XTLFIPW_350NA (0xaU << VRTC_XTLFCR_XTLFIPW_Pos) NVRTC_XTLFCR_XTLFIPW_300NA (0xbU << VRTC_XTLFCR_XTLFIPW_Pos) OVRTC_XTLFCR_XTLFIPW_250NA (0xcU << VRTC_XTLFCR_XTLFIPW_Pos) PVRTC_XTLFCR_XTLFIPW_200NA (0xdU << VRTC_XTLFCR_XTLFIPW_Pos) QVRTC_XTLFCR_XTLFIPW_150NA (0xeU << VRTC_XTLFCR_XTLFIPW_Pos) RVRTC_XTLFCR_XTLFIPW_100NA (0xfU << VRTC_XTLFCR_XTLFIPW_Pos) TVRTC_ADCCR_CKS_Pos 1 ]VRTC_ADCCR_CKS_Msk (0x7U << VRTC_ADCCR_CKS_Pos) ^VRTC_ADCCR_CKS_RCMF (0x0U << VRTC_ADCCR_CKS_Pos) _VRTC_ADCCR_CKS_RCMF_2 (0x1U << VRTC_ADCCR_CKS_Pos) `VRTC_ADCCR_CKS_RCMF_4 (0x2U << VRTC_ADCCR_CKS_Pos) aVRTC_ADCCR_CKS_RCMF_8 (0x3U << VRTC_ADCCR_CKS_Pos) bVRTC_ADCCR_CKS_RCMF_16 (0x4U << VRTC_ADCCR_CKS_Pos) cVRTC_ADCCR_CKS_RCMF_32 (0x5U << VRTC_ADCCR_CKS_Pos) dVRTC_ADCCR_CKS_RCLP (0x6U << VRTC_ADCCR_CKS_Pos) eVRTC_ADCCR_CKS_XTLF (0x7U << VRTC_ADCCR_CKS_Pos) gVRTC_ADCCR_CKE_Pos 0 jVRTC_ADCCR_CKE_Msk (0x1U << VRTC_ADCCR_CKE_Pos) nVRTC_LFDIER_LFDET_IE_Pos 0 oVRTC_LFDIER_LFDET_IE_Msk (0x1U << VRTC_LFDIER_LFDET_IE_Pos) qVRTC_LFDISR_LFDETO_Pos 1 tVRTC_LFDISR_LFDETO_Msk (0x1U << VRTC_LFDISR_LFDETO_Pos) vVRTC_LFDISR_LFDET_IF_Pos 0 wVRTC_LFDISR_LFDET_IF_Msk (0x1U << VRTC_LFDISR_LFDET_IF_Pos) ` U ..\Drivers\ ..\Core\Include\ fm33a0xxev_vrtc.h FM33A0XXEV.h ¼
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..\Drivers\fm33a0xxev_vrtc.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM ¥ ¦ § __FM33A0XXEV_CDIF_H CDIF_CR_INTF_EN_Pos 0 CDIF_CR_INTF_EN_Msk (0xfU << CDIF_CR_INTF_EN_Pos) CDIF_CR_INTF_EN_ENABLE (0xAU << CDIF_CR_INTF_EN_Pos) CDIF_CR_INTF_EN_DISABLE (0x5U << CDIF_CR_INTF_EN_Pos) !CDIF_PSCR_PRSC_Pos 0 "CDIF_PSCR_PRSC_Msk (0x7U << CDIF_PSCR_PRSC_Pos) #CDIF_PSCR_PRSC_DIV1 (0x0U) $CDIF_PSCR_PRSC_DIV2 (0x1U) %CDIF_PSCR_PRSC_DIV4 (0x2U) &CDIF_PSCR_PRSC_DIV8 (0x3U) 'CDIF_PSCR_PRSC_DIV16 (0x4U) (CDIF_PSCR_PRSC_DIV32 (0x5U) )CDIF_PSCR_PRSC_DIV64 (0x6U) *CDIF_PSCR_PRSC_DIV128 (0x7U) ` U ..\Drivers\ ..\Core\Include\ fm33a0xxev_cdif.h FM33A0XXEV.h ¼
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..\Drivers\fm33a0xxev_cdif.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM © ª « __INCLUDEALL_H__
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! " # $ Ì Â ..\Core\ ..\Drivers\ fm33a0xxev_include_all.h fm33a0xxev_aes.h fm33a0xxev_adc.h fm33a0xxev_bstim.h fm33a0xxev_comp.h fm33a0xxev_rmu.h fm33a0xxev_crc.h fm33a0xxev_lcd.h fm33a0xxev_dma.h fm33a0xxev_gpio.h fm33a0xxev_i2c.h fm33a0xxev_iwdt.h fm33a0xxev_lpuart.h fm33a0xxev_flash.h fm33a0xxev_pmu.h fm33a0xxev_cmu.h fm33a0xxev_rtc.h fm33a0xxev_dbg.h fm33a0xxev_spi.h fm33a0xxev_rng.h fm33a0xxev_u7816.h fm33a0xxev_uart.h fm33a0xxev_lptim.h fm33a0xxev_wwdt.h fm33a0xxev_svd.h fm33a0xxev_pae.h fm33a0xxev_hash.h fm33a0xxev_qspi.h fm33a0xxev_bt.h fm33a0xxev_et.h fm33a0xxev_vrtc.h fm33a0xxev_cdif.h À
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..\Core\fm33a0xxev_include_all.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM ® ¯ __string_h __ARMCLIB_VERSION 5060037 _ARMABI __declspec(__nothrow) __STRING_DECLS __CLIBNS $__CLIBNS 7NULL 8NULL 0 X M D:\Keil5\ARM\ARMCC\Bin\..\include\ string.h stdio.h ¤ D:\Keil5\ARM\ARMCC\Bin\..\include\string.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] unsigned int Psize_t 5 ± ² ³ BIT0 0x00000001 BIT1 0x00000002 BIT2 0x00000004 BIT3 0x00000008 BIT4 0x00000010 BIT5 0x00000020 BIT6 0x00000040
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BIT7 0x00000080 BIT8 0x00000100 BIT9 0x00000200 BIT10 0x00000400 BIT11 0x00000800 BIT12 0x00001000 BIT13 0x00002000 BIT14 0x00004000 BIT15 0x00008000 BIT16 0x00010000 BIT17 0x00020000 BIT18 0x00040000 BIT19 0x00080000 BIT20 0x00100000 BIT21 0x00200000 BIT22 0x00400000 BIT23 0x00800000 BIT24 0x01000000 BIT25 0x02000000 BIT26 0x04000000 BIT27 0x08000000 BIT28 0x10000000 BIT29 0x20000000 !BIT30 0x40000000 "BIT31 0x80000000 #BITNO 0x00000000 %B0000_0000 0x00 &B0000_0001 0x01 'B0000_0010 0x02 (B0000_0011 0x03 )B0000_0100 0x04 *B0000_0101 0x05 +B0000_0110 0x06 ,B0000_0111 0x07 -B0000_1000 0x08 .B0000_1001 0x09 /B0000_1010 0x0A 0B0000_1011 0x0B 1B0000_1100 0x0C 2B0000_1101 0x0D 3B0000_1110 0x0E 4B0000_1111 0x0F 6B0001_0000 0x10 7B0001_0001 0x11 8B0001_0010 0x12 9B0001_0011 0x13 :B0001_0100 0x14 ;B0001_0101 0x15 <B0001_0110 0x16 =B0001_0111 0x17 >B0001_1000 0x18 ?B0001_1001 0x19 @B0001_1010 0x1A AB0001_1011 0x1B BB0001_1100 0x1C CB0001_1101 0x1D DB0001_1110 0x1E EB0001_1111 0x1F GB0010_0000 0x20 HB0010_0001 0x21 IB0010_0010 0x22 JB0010_0011 0x23 KB0010_0100 0x24 LB0010_0101 0x25 MB0010_0110 0x26 NB0010_0111 0x27 OB0010_1000 0x28 PB0010_1001 0x29 QB0010_1010 0x2A RB0010_1011 0x2B SB0010_1100 0x2C TB0010_1101 0x2D UB0010_1110 0x2E VB0010_1111 0x2F XB0011_0000 0x30 YB0011_0001 0x31 ZB0011_0010 0x32 [B0011_0011 0x33 \B0011_0100 0x34 ]B0011_0101 0x35 ^B0011_0110 0x36 _B0011_0111 0x37 `B0011_1000 0x38 aB0011_1001 0x39 bB0011_1010 0x3A cB0011_1011 0x3B dB0011_1100 0x3C eB0011_1101 0x3D fB0011_1110 0x3E gB0011_1111 0x3F iB0100_0000 0x40 jB0100_0001 0x41 kB0100_0010 0x42 lB0100_0011 0x43 mB0100_0100 0x44 nB0100_0101 0x45 oB0100_0110 0x46 pB0100_0111 0x47 qB0100_1000 0x48 rB0100_1001 0x49 sB0100_1010 0x4A tB0100_1011 0x4B uB0100_1100 0x4C vB0100_1101 0x4D wB0100_1110 0x4E xB0100_1111 0x4F zB0101_0000 0x50 {B0101_0001 0x51 |B0101_0010 0x52 }B0101_0011 0x53 ~B0101_0100 0x54 B0101_0101 0x55 B0101_0110 0x56 B0101_0111 0x57 B0101_1000 0x58 B0101_1001 0x59 B0101_1010 0x5A
B0101_1011 0x5B B0101_1100 0x5C B0101_1101 0x5D B0101_1110 0x5E B0101_1111 0x5F B0110_0000 0x60 B0110_0001 0x61 B0110_0010 0x62 B0110_0011 0x63 B0110_0100 0x64 B0110_0101 0x65 B0110_0110 0x66 B0110_0111 0x67 B0110_1000 0x68 B0110_1001 0x69 B0110_1010 0x6A B0110_1011 0x6B B0110_1100 0x6C B0110_1101 0x6D B0110_1110 0x6E B0110_1111 0x6F B0111_0000 0x70 B0111_0001 0x71 B0111_0010 0x72 B0111_0011 0x73 B0111_0100 0x74 ¡B0111_0101 0x75 ¢B0111_0110 0x76 £B0111_0111 0x77 ¤B0111_1000 0x78 ¥B0111_1001 0x79 ¦B0111_1010 0x7A §B0111_1011 0x7B ¨B0111_1100 0x7C ©B0111_1101 0x7D ªB0111_1110 0x7E «B0111_1111 0x7F B1000_0000 0x80 ®B1000_0001 0x81 ¯B1000_0010 0x82 °B1000_0011 0x83 ±B1000_0100 0x84 ²B1000_0101 0x85 ³B1000_0110 0x86 ´B1000_0111 0x87 µB1000_1000 0x88 ¶B1000_1001 0x89 ·B1000_1010 0x8A ¸B1000_1011 0x8B ¹B1000_1100 0x8C ºB1000_1101 0x8D »B1000_1110 0x8E ¼B1000_1111 0x8F ¾B1001_0000 0x90 ¿B1001_0001 0x91 ÀB1001_0010 0x92 ÁB1001_0011 0x93 ÂB1001_0100 0x94 ÃB1001_0101 0x95 ÄB1001_0110 0x96 ÅB1001_0111 0x97 ÆB1001_1000 0x98 ÇB1001_1001 0x99 ÈB1001_1010 0x9A ÉB1001_1011 0x9B ÊB1001_1100 0x9C ËB1001_1101 0x9D ÌB1001_1110 0x9E ÍB1001_1111 0x9F ÏB1010_0000 0xA0 ÐB1010_0001 0xA1 ÑB1010_0010 0xA2 ÒB1010_0011 0xA3 ÓB1010_0100 0xA4 ÔB1010_0101 0xA5 ÕB1010_0110 0xA6 ÖB1010_0111 0xA7 ×B1010_1000 0xA8 ØB1010_1001 0xA9 ÙB1010_1010 0xAA ÚB1010_1011 0xAB ÛB1010_1100 0xAC ÜB1010_1101 0xAD ÝB1010_1110 0xAE ÞB1010_1111 0xAF àB1011_0000 0xB0 áB1011_0001 0xB1 âB1011_0010 0xB2 ãB1011_0011 0xB3 äB1011_0100 0xB4 åB1011_0101 0xB5 æB1011_0110 0xB6 çB1011_0111 0xB7 èB1011_1000 0xB8 éB1011_1001 0xB9 êB1011_1010 0xBA ëB1011_1011 0xBB ìB1011_1100 0xBC íB1011_1101 0xBD îB1011_1110 0xBE ïB1011_1111 0xBF ñB1100_0000 0xC0 òB1100_0001 0xC1 óB1100_0010 0xC2 ôB1100_0011 0xC3 õB1100_0100 0xC4 öB1100_0101 0xC5 ÷B1100_0110 0xC6 øB1100_0111 0xC7 ùB1100_1000 0xC8 úB1100_1001 0xC9 ûB1100_1010 0xCA üB1100_1011 0xCB ýB1100_1100 0xCC þB1100_1101 0xCD ÿB1100_1110 0xCE B1100_1111 0xCF B1101_0000 0xD0 B1101_0001 0xD1 B1101_0010 0xD2
B1101_0011 0xD3 B1101_0100 0xD4 B1101_0101 0xD5 B1101_0110 0xD6 B1101_0111 0xD7 B1101_1000 0xD8 B1101_1001 0xD9 B1101_1010 0xDA B1101_1011 0xDB B1101_1100 0xDC B1101_1101 0xDD B1101_1110 0xDE B1101_1111 0xDF B1110_0000 0xE0 B1110_0001 0xE1 B1110_0010 0xE2 B1110_0011 0xE3 B1110_0100 0xE4 B1110_0101 0xE5 B1110_0110 0xE6 B1110_0111 0xE7 B1110_1000 0xE8 B1110_1001 0xE9 B1110_1010 0xEA B1110_1011 0xEB B1110_1100 0xEC B1110_1101 0xED ¡B1110_1110 0xEE ¢B1110_1111 0xEF ¤B1111_0000 0xF0 ¥B1111_0001 0xF1 ¦B1111_0010 0xF2 §B1111_0011 0xF3 ¨B1111_0100 0xF4 ©B1111_0101 0xF5 ªB1111_0110 0xF6 «B1111_0111 0xF7 ¬B1111_1000 0xF8 B1111_1001 0xF9 ®B1111_1010 0xFA ¯B1111_1011 0xFB °B1111_1100 0xFC ±B1111_1101 0xFD ²B1111_1110 0xFE ³B1111_1111 0xFF 4 * ..\Core\ bintohex.h ´
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..\Core\bintohex.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM µ ¶ · __DEFINEALL_H__ RCHFCLKCFG 8 clkmode 1 SYSCLKdef CMU_RCHFCR_FSEL_8MHZ 5uint08 uint8_t 6uint8 uint8_t 8uint16 uint16_t 9uint32 uint32_t :int08 int8_t ;int16 int16_t <int32 int32_t CIN_NORMAL 0 DIN_PULLUP 1 IOUT_PUSHPULL 0 JOUT_OPENDRAIN 1 QALTFUN_NORMAL 0 RALTFUN_OPENDRAIN 1 SALTFUN_PULLUP 2 TALTFUN_OPENDRAIN_PULLUP 3 XYZ[\]^_ ý ..\Core\ ..\Core\Include\ D:\Keil5\ARM\ARMCC\Bin\..\include\ ..\Hardware\CLOCK\ ..\Hardware\DELAY\ define_all.h FM33A0XXEV.h fm33a0xxev_include_all.h stdio.h stdint.h string.h bintohex.h user_init.h delay.h
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..\Core\define_all.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM unsigned char SÜ B08 ¶ Bit ! PB08_Bit Ç -SUCCESS_0 ERROR_1 PErrorStatus_STM32 ë 3*!bit0 ¶ # !bit1 ¶ # !bit2 ¶ # !bit3 ¶ # !bit4 ¶ # !bit5 ¶ # !bit6 ¶ # !bit7 ¶ # ¹ º » __USER_INIT_H__ X N ..\Hardware\CLOCK\ ..\Core\ user_init.h define_all.h À
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..\Hardware\CLOCK\user_init.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM ½ ¾ ¿ _DELAY_H_ SYSTICK_CLOCK_SOURCE_SCLK 0xFFFFFF3F SYSTICK_CLOCK_SOURCE_LSCLK 0xFFFFFF7F SYSTICK_CLOCK_SOURCE_RFU 0xFFFFFFBF SYSTICK_CLOCK_SOURCE_SYSCLK 0xFFFFFFFF SYSTICK_CLOCK_SOURCE_U_SCLK 0x00000000 SYSTICK_CLOCK_SOURCE_U_LSCLK 0x00000040 SYSTICK_CLOCK_SOURCE_U_RFU 0x00000080 SYSTICK_CLOCK_SOURCE_U_SYSCLK 0x000000C0 SYSCLOCK_U 12000000 \ Q ..\Hardware\DELAY\ ..\Drivers\ delay.h fm33a0xxev_cmu.h à
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..\Hardware\DELAY\delay.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM int NÉ» "Â PConditionHook É Á Â Ã _MAIN_H_ OS_YEAR ((((__DATE__[7] - '0') * 10 + (__DATE__[8] - '0')) * 10 + (__DATE__[9] - '0')) * 10 + (__DATE__[10] - '0'))
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OS_MONTH (__DATE__[2] == 'n' ? (__DATE__[1] == 'a' ? 1 : 6) : __DATE__[2] == 'b' ? 2 : __DATE__[2] == 'r' ? (__DATE__[0] == 'M' ? 3 : 4) : __DATE__[2] == 'y' ? 5 : __DATE__[2] == 'l' ? 7 : __DATE__[2] == 'g' ? 8 : __DATE__[2] == 'p' ? 9 : __DATE__[2] == 't' ? 10 : __DATE__[2] == 'v' ? 11 : 12) OS_DAY ((__DATE__[4] == ' ' ? 0 : __DATE__[4] - '0') * 10 + (__DATE__[5] - '0')) OS_HOUR ((__TIME__[0] - '0') * 10 + (__TIME__[1] - '0')) OS_MINUTE ((__TIME__[3] - '0') * 10 + (__TIME__[4] - '0')) OS_SENCOND ((__TIME__[6] - '0') * 10 + (__TIME__[7] - '0')) "FW_VER_RESERVE 0x00 &FW_VER_MAIN 0x01 *FW_VER_MINOR 0x02 .FW_VER_REVISE 0x03 2HARDWARE_VERSION "02154.0203.3" :FIRMWARE_VERSION "1.3.0.0" HRS232_PRINTF WLCD_NEW \SYS_MODE_DEFAULT 8 `SYS_LCD_DISPLAY_MODE_DEFAULT 0 dSOFT_OR_HARD 0 iGET_FLOW_DATA_PERIOD_TIME 10 nSYS_WAKE_UP_TIME 30 sDISPLAY_PARA_TIME 300 xGPRS_TIMEOUT 120 }GPRS_RECONNECTION_INTERVAL_TIME 10 UC_ACTIVE_TIME 600 SET_PARA_MODE_TIMEOUT 10 CAL_MODE_TIMEOUT 20 CAL_MODE_FORCE_TIME 480 GPRS_PROTOCOL_SELECT 1 GPRS_HISTORY_OR_REAL_DATA 1 KEY_VERSION 0x80 ¡NB_OR_4G_FLAG 0 ¥APN_SET_FLAG 0 ©IP_OR_YUMING_FLAG 0 ®AUTO_CALI_TIME_SEC_MAX 300 ±STANDARD_PRESSURE 101.325f ´STANDARD_TEMPERATURE 293.15f ¸CAL_TEST ¾FIRMWARE_VER_1 0x0000 ¿FIRMWARE_VER_2 0x0102 ÀFIRMWARE_VER_3 0x0407 @ 6 ..\Core\ main.h define_all.h °
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..\Core\main.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM Å Æ Ç _HARDWARE_WATCHDOG_H_ x l ..\Function\HARDWARE_WATCHDOG\ ..\Core\ hardware_watchdog.h define_all.h main.h Ô
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..\Function\HARDWARE_WATCHDOG\hardware_watchdog.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM É Ê Ë ~ ..\Function\HARDWARE_WATCHDOG\ ..\Function\HARDWARE_WATCHDOG\hardware_watchdog.c hardware_watchdog.h L
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..\Function\HARDWARE_WATCHDOG\hardware_watchdog.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM _Complex long_double _Complex double _Complex float uvoid )±__va_list __ap 1# "P__builtin_va_list Í ! / ! I $ > % % % % %C
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%C % % % % %C %C & I ( ( 1 1 1 1 I8 I I8 4 ! I8 " I #7 I $ I % I & I ' I ( I ) * + , - . /4 04 14 24 3 4 4 4 5.:;9? I 6.:;9? 7.:;9G 8.:;9? I 9.:;9? :.:;9G ;.:;9? I <.:;9? =.:;9G >.:;9? I@ ?.:;9? @ @.:;9G@ A.:;9? I@
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K.1 L.< 4 I? M.< 4 ? NI O P I:;9 Q I4 R S T U V W 1 X4 I , Y4 I Z4 I [4 I, \4 I ]4 I 4 ^4 I ,4 _4 I4 `4 I,4 a4 I4 b4 1 , c4 1 d4 1, e4 1 f 1 g 1 h I i I j I k I 4 l I ,4 m I4 n 1 o 1 p4 I ? q4 I? < r4 I , s4 I t5 I u; v= w% x<% Component: ARM Compiler 5.06 update 6 (build 750) Tool: armlink [4d35ed] armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=9931,9931,6642 --cpu=Cortex-M0 --fpu=SoftVFP --output=.\objects\hardware_watchdog.o --vfemode=force
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Input Comments: p23a8-3 Component: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec] armasm --debug --diag_suppress=9931,9931,1602,1073 --cpu=Cortex-M0 --fpu=SoftVFP --apcs=/interwork/interwork --no_divide hardware_watchdog.o Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] ArmCC --c99 --split_sections --debug -c --gnu -o.\objects\hardware_watchdog.o --depend=.\objects\hardware_watchdog.d --cpu=Cortex-M0 --apcs=interwork -O0 --diag_suppress=9931 -I..\Core -I..\Drivers -I..\Core\Include -I..\Hardware -I.\RTE\Device -I..\Hardware\CLOCK -I..\Hardware\DELAY -I..\Hardware\GPIO -I..\Hardware\UART -I..\Hardware\TIM -I..\Function\KEY -I..\Hardware\EXTI -I..\Hardware\RTC -I..\Hardware\ADC -I..\Hardware\I2C -I..\Function\LCD -I..\Function\EXTERN_RTC -I..\Hardware\SPI -I..\Function\GPRS -I..\Function\HARDWARE_WATCHDOG -I..\Function\IR_NEC -I..\Function\MEASURE_INTERACTION -I..\Function\POWER_MANAGE -I..\Function\STORAGE -I..\Function\UPPER_COMPUTER -I..\Function\VALVE -I..\Soft -I..\MultiButton -I..\USMART -I..\Hardware\DMA -I..\Hardware\ON_CHIP_FLASH -I..\Hardware\SVD -I..\Function\OFF_CHIP_FLASH -I..\Hardware\CRC -I..\Function\BOOTLOADER_IAP -I..\Hardware\COMP -I..\Function\E2P -I..\CmBackTrace -I..\Pre_Drivers -I..\Pre_Drivers -I..\Function\PROJECT_TETS -I.\RTE\_UFG220_FM33A0_MainSystem -ID:\Keil5\ARM\PACK\ARM\CMSIS\5.3.0\CMSIS\Include -ID:\Keil5\ARM\PACK\Keil\FM33A0XXEV_DFP\0.0.4\Device\Include -D__MICROLIB -D__UVISION_VERSION=525 -D_RTE_ -D__VTOR_PRESENT --omf_browse=.\objects\hardware_watchdog.crf ..\Function\HARDWARE_WATCHDOG\hardware_watchdog.c 2 2 2 Î Ô1 ñÿÈ1 ¼1 T T D D 1 ñÿr1 Z1
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¶ È º ¶ ® º º ¹ ¾ Ï ¬ ¤ ° u ® ¨ ² y · Ñ » ¢ ³ © · z ¨ Ì ¬ Ë Ë Ï Ë Ê Ï .ARM.attributes .strtab .shstrtab .rel.debug_pubnames .rel.debug_frame .rel.debug_line .rel.debug_info .symtab .comment .arm_vfe_header __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000 __ARM_grp.hardware_watchdog.c.2_Aw0000_dyonvSirEse_300000 __ARM_grp.hardware_watchdog.h.2_4v0000_BaVexAWvF24_300000 __ARM_grp.main.h.2_ga1000_6c0asbwEXV7_300000 __ARM_grp.delay.h.2_EE0000_7GGSWSTJWL4_300000 __ARM_grp.user_init.h.2_ot0000_jZWuqvPHwt6_300000 __ARM_grp.define_all.h.2_kN0000_fD9tyG24Hn2_300000 __ARM_grp.bintohex.h.2_Y33000_duI5XZW3h40_300000 __ARM_grp.string.h.2_kw0000_aP4aobzpRT7_300000 __ARM_grp.fm33a0xxev_include_all.h.2_UQ0000_xxdaGLUj6Cf_300000 __ARM_grp.fm33a0xxev_cdif.h.2_kJ0000_JQTXKb9R3mc_300000 __ARM_grp.fm33a0xxev_vrtc.h.2_YK1000_bGKK6ktMN$f_300000 __ARM_grp.fm33a0xxev_et.h.2_4h3000_57B3Rgey0je_300000 __ARM_grp.fm33a0xxev_bt.h.2_kV3000_MyPILKKQ6H1_300000 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