1.Fixed communication failure between MCU and wireless module 2.Fix the wro...

wujiazhi

2024-06-11 65062d0d5b21f838aa0043a15ce54cfab8d72c43

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öSCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)
úSCB_AIRCR_VECTKEY_Pos 16U
ûSCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
ýSCB_AIRCR_VECTKEYSTAT_Pos 16U
þSCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
€SCB_AIRCR_ENDIANESS_Pos 15U
SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
ƒSCB_AIRCR_SYSRESETREQ_Pos 2U
„SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
†SCB_AIRCR_VECTCLRACTIVE_Pos 1U
‡SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
ŠSCB_SCR_SEVONPEND_Pos 4U
‹SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
SCB_SCR_SLEEPDEEP_Pos 2U
ŽSCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
SCB_SCR_SLEEPONEXIT_Pos 1U
‘SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
”SCB_CCR_STKALIGN_Pos 9U
•SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)
—SCB_CCR_UNALIGN_TRP_Pos 3U
˜SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
›SCB_SHCSR_SVCALLPENDED_Pos 15U
œSCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
´SysTick_CTRL_COUNTFLAG_Pos 16U
µSysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
·SysTick_CTRL_CLKSOURCE_Pos 2U
¸SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
ºSysTick_CTRL_TICKINT_Pos 1U
»SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
½SysTick_CTRL_ENABLE_Pos 0U
¾SysTick_CTRL_ENABLE_Msk (1UL )
ÁSysTick_LOAD_RELOAD_Pos 0U
ÂSysTick_LOAD_RELOAD_Msk (0xFFFFFFUL )
ÅSysTick_VAL_CURRENT_Pos 0U
ÆSysTick_VAL_CURRENT_Msk (0xFFFFFFUL )
ÉSysTick_CALIB_NOREF_Pos 31U
ÊSysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)
ÌSysTick_CALIB_SKEW_Pos 30U
ÍSysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)
ÏSysTick_CALIB_TENMS_Pos 0U
ÐSysTick_CALIB_TENMS_Msk (0xFFFFFFUL )
éMPU_TYPE_IREGION_Pos 16U
êMPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
ìMPU_TYPE_DREGION_Pos 8U
íMPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
ïMPU_TYPE_SEPARATE_Pos 0U
ðMPU_TYPE_SEPARATE_Msk (1UL )
óMPU_CTRL_PRIVDEFENA_Pos 2U
ôMPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
öMPU_CTRL_HFNMIENA_Pos 1U
÷MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
ùMPU_CTRL_ENABLE_Pos 0U
úMPU_CTRL_ENABLE_Msk (1UL )
ýMPU_RNR_REGION_Pos 0U
þMPU_RNR_REGION_Msk (0xFFUL )
MPU_RBAR_ADDR_Pos 8U
‚MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)
„MPU_RBAR_VALID_Pos 4U
…MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos)
‡MPU_RBAR_REGION_Pos 0U
ˆMPU_RBAR_REGION_Msk (0xFUL )
‹MPU_RASR_ATTRS_Pos 16U
ŒMPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos)
ŽMPU_RASR_XN_Pos 28U
MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos)
‘MPU_RASR_AP_Pos 24U
’MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos)
”MPU_RASR_TEX_Pos 19U
•MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos)
—MPU_RASR_S_Pos 18U
˜MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos)
šMPU_RASR_C_Pos 17U
›MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos)
MPU_RASR_B_Pos 16U
žMPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos)
 MPU_RASR_SRD_Pos 8U
¡MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos)
£MPU_RASR_SIZE_Pos 1U
¤MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos)
¦MPU_RASR_ENABLE_Pos 0U
§MPU_RASR_ENABLE_Msk (1UL )
Ä_VAL2FLD(field,value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
Ì_FLD2VAL(field,value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
ÙSCS_BASE (0xE000E000UL)
ÚSysTick_BASE (SCS_BASE + 0x0010UL)
ÛNVIC_BASE (SCS_BASE + 0x0100UL)
ÜSCB_BASE (SCS_BASE + 0x0D00UL)
ÞSCB ((SCB_Type *) SCB_BASE )
ßSysTick ((SysTick_Type *) SysTick_BASE )
àNVIC ((NVIC_Type *) NVIC_BASE )
ãMPU_BASE (SCS_BASE + 0x0D90UL)
äMPU ((MPU_Type *) MPU_BASE )
‚_BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
ƒ_SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
„_IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )”ˆ
 




..\Core\Include\D:\Keil5\ARM\ARMCC\Bin\..\include\core_cm0plus.h
stdint.hcore_cminstr.h
core_cmfunc.h


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..\Core\Include\core_cm0plus.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM*”!_reserved0f
#!Vf
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Å*‰    CTRL #LOAD #VAL #CALIB?#PSysTick_TypeT
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NVIC_EnableIRQ$(IRQn<¶

œNVIC_DisableIRQ$(IRQn;ò

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ÏNVIC_ClearPendingIRQ$(IRQn<ö
áNVIC_SetPriority$(IRQn$f
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ùNVIC_GetPriorityf
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__stdio_h 
__ARMCLIB_VERSION 5060037
"_ARMABI __declspec(__nothrow)
%__STDIO_DECLS '__CLIBNS
-__CLIBNS <NULL
=NULL 0
g_SYS_OPEN 16
¥
stdin (&__CLIBNS __stdin)
§
stdout (&__CLIBNS __stdout)
©
stderr (&__CLIBNS __stderr)
¬
_IOFBF 0x100
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_IOLBF 0x200
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_IONBF 0x400
±
BUFSIZ (512)
³
FOPEN_MAX _SYS_OPEN
¹
FILENAME_MAX 256
¾
L_tmpnam FILENAME_MAX
Ä
TMP_MAX 256
Ì
EOF (-1)
Ò
SEEK_SET 0
Ó
SEEK_CUR 1
Ô
SEEK_END 2
Ú
_IOBIN 0x04
Ü
__STDIN_BUFSIZ (64)
Ý
__STDOUT_BUFSIZ (64)
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__STDERR_BUFSIZ (16)
¿getchar() getc(stdin)
àputchar(c) putc(c, stdout)LA
 




D:\Keil5\ARM\ARMCC\Bin\..\include\stdio.h


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D:\Keil5\ARM\ARMCC\Bin\..\include\stdio.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]unsigned intunsigned long longPsize_t‡
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$FM33A0XXEV_H 
.__RCHF_INITIAL_CLOCK (8000000)
/__RCMF_CLOCK (2000000)
0__RCLP_CLOCK (32000)
1__XTLF_CLOCK (32768)
n__CM0_REV 0x0100
o__MPU_PRESENT 1
p__VTOR_PRESENT 1
q__NVIC_PRIO_BITS 2
r__Vendor_SysTickConfig 0uv
¿FLASH_BASE (( uint32_t)0x00000000)
ÀSRAM_BASE (( uint32_t)0x20000000)
ÁPERIPH_BASE (( uint32_t)0x40000000)
ÊPMU_BASE (PERIPH_BASE +0x00002000)
ËDBG_BASE (PERIPH_BASE +0x00000000)
ÌFLS_BASE (PERIPH_BASE +0x00001000)
ÍRMU_BASE (PERIPH_BASE +0x00002800)
ÎIWDT_BASE (PERIPH_BASE +0x00011400)
ÏWWDT_BASE (PERIPH_BASE +0x00011800)
ÐCMU_BASE (PERIPH_BASE +0x00002400)
ÑCDIF_BASE (PERIPH_BASE +0x0001E000)
ÒVRTC_BASE (PERIPH_BASE +0x0001F800)
ÓSVD_BASE (PERIPH_BASE +0x00012800)
ÔAES_BASE (PERIPH_BASE +0x00013800)
ÕPAE_BASE (PERIPH_BASE +0x00001400)
ÖHASH_BASE (PERIPH_BASE +0x00001800)
×RNG_BASE (PERIPH_BASE +0x00013C00)
ØCOMP_BASE (PERIPH_BASE +0x00015400)
ÙI2C0_BASE (PERIPH_BASE +0x00012400)
ÚI2C1_BASE (PERIPH_BASE +0x00015000)
ÛUARTIR_BASE (PERIPH_BASE +0x00017C00)
ÜUART0_BASE (PERIPH_BASE +0x00012000)
ÝUART1_BASE (PERIPH_BASE +0x00016800)
ÞUART2_BASE (PERIPH_BASE +0x00016C00)
ßUART3_BASE (PERIPH_BASE +0x00017000)
àUART4_BASE (PERIPH_BASE +0x00017400)
áUART5_BASE (PERIPH_BASE +0x00017800)
âLPUART0_BASE (PERIPH_BASE +0x00014000)
ãLPUART1_BASE (PERIPH_BASE +0x00014400)
äSPI0_BASE (PERIPH_BASE +0x00010400)
åSPI1_BASE (PERIPH_BASE +0x00010800)
æSPI2_BASE (PERIPH_BASE +0x00014800)
çSPI3_BASE (PERIPH_BASE +0x00014C00)
èSPI4_BASE (PERIPH_BASE +0x00016400)
éU7816_BASE (PERIPH_BASE +0x00011C00)
êQSPI_BASE (PERIPH_BASE +0x00000800)
ëDMA_BASE (PERIPH_BASE +0x00000400)
ìCRC_BASE (PERIPH_BASE +0x00010000)
íBT1_BASE (PERIPH_BASE +0x00013000)
îBT2_BASE (PERIPH_BASE +0x00013044)
ïET1_BASE (PERIPH_BASE +0x00013090)
ðET2_BASE (PERIPH_BASE +0x000130B0)
ñET3_BASE (PERIPH_BASE +0x000130D0)
òET4_BASE (PERIPH_BASE +0x000130F0)
óETCNT_BASE (PERIPH_BASE +0x00013110)
ôBSTIM_BASE (PERIPH_BASE +0x00016000)
õLPTIM_BASE (PERIPH_BASE +0x00013400)
öRTC_BASE (PERIPH_BASE +0x00011000)
÷LCD_BASE (PERIPH_BASE +0x00010C00)
øADC_BASE (PERIPH_BASE +0x0001FA00)
ùCIC_BASE (PERIPH_BASE +0x00015C00)
úGPIOA_BASE (PERIPH_BASE +0x00000C00)
ûGPIOB_BASE (PERIPH_BASE +0x00000C40)
üGPIOC_BASE (PERIPH_BASE +0x00000C80)
ýGPIOD_BASE (PERIPH_BASE +0x00000CC0)
þGPIOE_BASE (PERIPH_BASE +0x00000D00)
ÿGPIOF_BASE (PERIPH_BASE +0x00000D40)
€GPIOG_BASE (PERIPH_BASE +0x00000D80)
GPIOH_BASE (PERIPH_BASE +0x0001FC00)
‚GPIO_BASE (PERIPH_BASE +0x00000DC0)
ˆPMU ((PMU_Type *) PMU_BASE )
‰DBG ((DBG_Type *) DBG_BASE )
ŠFLS ((FLS_Type *) FLS_BASE )
‹RMU ((RMU_Type *) RMU_BASE )
ŒIWDT ((IWDT_Type *) IWDT_BASE )
WWDT ((WWDT_Type *) WWDT_BASE )
ŽCMU ((CMU_Type *) CMU_BASE )
CDIF ((CDIF_Type *) CDIF_BASE )
VRTC ((VRTC_Type *) VRTC_BASE )
‘SVD ((SVD_Type *) SVD_BASE )
’AES ((AES_Type *) AES_BASE )
“PAE ((PAE_Type *) PAE_BASE )
”HASH ((HASH_Type *) HASH_BASE )
•RNG ((RNG_Type *) RNG_BASE )
–COMP ((COMP_Type *) COMP_BASE )
—I2C0 ((I2C_Type *) I2C0_BASE )
˜I2C1 ((I2C_Type *) I2C1_BASE )
™UARTIR ((UARTIR_Type *) UARTIR_BASE )
šUART0 ((UART_Type *) UART0_BASE )
›UART1 ((UART_Type *) UART1_BASE )
œUART2 ((UART_Type *) UART2_BASE )
UART3 ((UART_Type *) UART3_BASE )
žUART4 ((UART_Type *) UART4_BASE )
ŸUART5 ((UART_Type *) UART5_BASE )
 LPUART0 ((LPUART_Type *) LPUART0_BASE )
¡LPUART1 ((LPUART_Type *) LPUART1_BASE )
¢SPI0 ((SPI_Type *) SPI0_BASE )
£SPI1 ((SPI_Type *) SPI1_BASE )
¤SPI2 ((SPI_Type *) SPI2_BASE )
¥SPI3 ((SPI_Type *) SPI3_BASE )
¦SPI4 ((SPI_Type *) SPI4_BASE )
§U7816 ((U7816_Type *) U7816_BASE )
¨QSPI ((QSPI_Type *) QSPI_BASE )
©DMA ((DMA_Type *) DMA_BASE )
ªCRC ((CRC_Type *) CRC_BASE )
«BT1 ((BT_Type *) BT1_BASE )
¬BT2 ((BT_Type *) BT2_BASE )
­ET1 ((ET_Type *) ET1_BASE )
®ET2 ((ET_Type *) ET2_BASE )
¯ET3 ((ET_Type *) ET3_BASE )
°ET4 ((ET_Type *) ET4_BASE )
±ETCNT ((ETCNT_Type *) ETCNT_BASE )
²BSTIM ((BSTIM_Type *) BSTIM_BASE )
³LPTIM ((LPTIM_Type *) LPTIM_BASE )
´RTC ((RTC_Type *) RTC_BASE )
µLCD ((LCD_Type *) LCD_BASE )
¶ADC ((ADC_Type *) ADC_BASE )
·CIC ((CIC_Type *) CIC_BASE )
¸GPIOA ((GPIO_Type *) GPIOA_BASE )
¹GPIOB ((GPIO_Type *) GPIOB_BASE )
ºGPIOC ((GPIO_Type *) GPIOC_BASE )
»GPIOD ((GPIO_Type *) GPIOD_BASE )
¼GPIOE ((GPIO_Type *) GPIOE_BASE )
½GPIOF ((GPIO_Type *) GPIOF_BASE )
¾GPIOG ((GPIO_Type *) GPIOG_BASE )
¿GPIOH ((GPIOH_Type *) GPIOH_BASE )
ÀGPIO ((GPIO_COMMON_Type *) GPIO_BASE )h]
 




..\Core\Include\FM33A0XXEV.h
core_cm0plus.h
system_FM33A0XXEV.h


¬
..\Core\Include\FM33A0XXEV.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMÓ

RESETSET
PFlagStatus¾
*(PITStatus¾
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PFunStateõ
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Reset_IRQnqNMI_IRQnrHardFault_IRQnsSVC_IRQn{PendSV_IRQn~SysTick_IRQnWWDT_IRQnSVD_IRQn
RTC_IRQnFLASH_IRQnCMU_IRQnADC_IRQnSPI0_IRQnSPI1_IRQnSPI2_IRQnUART0_IRQn    UART1_IRQn
UART2_IRQnUART3_IRQnUART4_IRQn UART5_IRQnU7816_IRQnLPUART0_IRQnI2Cx_IRQnRSV_IRQnCRYPTO_IRQnLPTIM_IRQnDMA_IRQnWKUPx_IRQnCOMP_IRQnBTx_IRQnQSPI_IRQnETx_IRQnBSTIM_IRQnSPI3_IRQnSPI4_IRQnGPIO_IRQnLPUART1_IRQnPIRQn_TypeG

b*öCRv#WKTRv#WKFRv#IERv#ISRv#tf
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RSV20#$ACLOCK1v#HACLOCK2v#LACLOCK3v#PACLOCK4v#Tf
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¾
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$PDRCRv#BORCRv#RSTCFGRv#SOFTRSTv#RSRv#PRSTENv#AHBRSTv#APBRST1v#APBRST2v# PRMU_Type
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ë
* 8SYSCLKCRv#RCHFCRv#RCHFTRv#PLLLCRv#PLLHCRv#XTHFCRv#IERv#ISRv#PCLKCR1v# PCLKCR2v#$PCLKCR3v#(PCLKCR4v#,OPCCR1v#0OPCCR2v#4PCMU_TypeÆ
‚*» CRv#PSCRv#PCDIF_Type 
Œ*Õ0PDRCRv#ç v
RSV1Þ#RCMFCRv#RCLPCRv#RCLPTRv#XTLFCRv# ADCCRv#$LFDIERv#(LFDISRv#,PVRTC_TypeÍ
ž*£CFGRv#CRv#IERv#ISRv#VSRv#PSVD_Typeg
¬*§TCRv#IERv#ISRv#DIRv#DORˆ#KEY0v#KEY1v#KEY2v#KEY3v# KEY4v#$KEY5v#(KEY6v#,KEY7v#0IVR0v#4IVR1v#8IVR2v#<IVR3v#@H0v#DH1v#HH2v#LH3v#PPAES_Type´
Ê*ž CSRv#MLRv#MPRv#M0CFGv#M1CFGv#M2CFGv#M3CFGv#WORDv#PPAE_Type¸
Û*ÊCSRv#DTRv#PHASH_Type/    
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ö*CR1v#CR2v#ICRv#ISRv#PCRv#PCOMP_TypeÑ    
„*ˆ$CFGRv#CRv#IERv#ISRv#SRv#BRGv#BUFv#TIMINGv#TOv# PI2C_Type

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Ð*â$CRv#FFRv#EGTRv#PSCv#BGRv#RXBUFˆ#TXBUFv#IERv#ISRv# PU7816_Typeö
â*‚0CRv#CFGv#SRv#DATALENv#CCRv#ADDRv#ABRv#DRv#SMSKv# SMATv#$PITVv#(TOv#,PQSPI_Typeu
÷*õ¸GCRv#CH0CRv#CH0MARv#CH1CRv#CH1MARv#CH2CRv#CH2MARv#CH3CRv#CH3MARv# CH4CRv#$CH4MARv#(CH5CRv#,CH5MARv#0CH6CRv#4CH6MARv#8CH7CRv#<CH7MARv#@CH8CRv#DCH8MARv#HCH9CRv#LCH9MARv#PCH10CRv#TCH10MARv#XCH11CRv#\CH11FARv#`CH11RARv#dISRv#hv
$RSV1†#lCH0CSRv#€CH0MASRv#„CH1CSRv#ˆCH1MASRv#ŒCH2CSRv#CH2MASRv#”CH3CSRv#˜CH3MASRv#œCH4CSRv# CH4MASRv#¤CH5CSRv#¨CH5MASRv#¬CH6CSRv#°CH6MASRv#´PDMA_Type 
ª*× DRv#CRv#LFSRv#XORv#¾v
RSV1µ#POLYv#PCRC_Type†
¹*¾!DCR1v#CR2v#CFGR1v#CFGR2v#PRESv#LOADCRv#CNTLˆ#CNTHˆ#PRESETv# LOADLv#$LOADHv#(CMPLv#,CMPHv#0OUTCNTv#4OCRv#8IERv#<ISRv#@PBT_Typeè
Ó*°" CRv#INSRv#PSCR1v#PSCR2v#IVRv#CMPRv#IERv#ISRv#PET_TypeÎ
ä*õ"CNT1v#CNT2v#CNT3v#CNT4v#PETCNT_Type@
ï*ˆ$0CR1v#CR2v#RSV1v#IERv#ISRv#EGRv#Ø#v
RSV2Ï#CNTRv#$PSCRv#(ARRv#,PBSTIM_Typeˆ
*«%0CFGRv#CNTRˆ#CCSRv#ARRv#IERv#ISRv#CRv#RSV1v#CCR1v# CCR2v#$CCR3v#(CCR4v#,PLPTIM_Type
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WERv#IERv#ISRv#BCDSECv#BCDMINv#BCDHOURv#BCDDATEv#BCDWEEKv#BCDMONTHv# BCDYEARv#$ALARMv#(TMSELv#,ADJUSTv#0ADSIGNv#4VCALv#8MSCNTv#<CALSTEPv#@ADCNTˆ#DSSRˆ#HSSAv#LDTRv#Pá'v
    RSV1Ø#TCRv#|PRTC_Type¾
¶*¿*`CRv#TESTv#FCRv#FLKTv#RSV1v#IERv#ISRv#å(v

RSV2\#DATA0v#$DATA1v#(DATA2v#,DATA3v#0DATA4v#4DATA5v#8DATA6v#<DATA7v#@DATA8v#DDATA9v#Hü)v
RSV3ó#LCOMENv#PSEGEN0v#TSEGEN1v#XBSTCRv#\PLCD_Type    
Õ*Œ+CRv#TRIMv#DRˆ#ISRv#CFGRv#PADC_TypeP
ã*×+DRˆ#OSv#USDRˆ#CRv#ISRv#PCIC_Type
ñ*ë,,INENv#PUENv#ODENv#FCRv#DOv#DSETv#DRSTv#DINˆ#DFSv# RSVv#$ANENv#(PGPIO_Typeè
…*º-INENv#PUENv#FCRv#DOv#DINv#PGPIOH_Type}
’*”/ÄEXTISEL0v#EXTISEL1v#EXTIEDS0v#EXTIEDS1v#EXTIDFv#EXTIISRv#EXTIDIˆ#Æ.v
RSV1=#FOUTSELv#@IOMCRv#D÷.v
=RSV2n#HPINWKENv#ÀPGPIO_COMMON_TypeÍ
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(SYSTEM_FM33A0XXEV_H 234
O__SYSTEM_CLOCK (8000000)
PDELAY_US (__SYSTEM_CLOCK/1000000)
QDELAY_MS (__SYSTEM_CLOCK/1000)
TDo_DelayStart() { uint32_t LastTick = SysTick->VAL; do {
WWhile_DelayMsEnd(Count) }while(((LastTick - SysTick->VAL)&0xFFFFFF)<DELAY_MS*Count); }
ZWhile_DelayUsEnd(Count) }while(((LastTick - SysTick->VAL)&0xFFFFFF)<DELAY_US*Count); }…
 




..\Core\Include\D:\Keil5\ARM\ARMCC\Bin\..\include\system_FM33A0XXEV.h
stdint.hstdio.hFM33A0XXEV.h


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..\Core\Include\system_FM33A0XXEV.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMqSystemCoreClockf


"àÅSystemCoreClock
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‘
’


__FM33A0XXEV_AES_H 
)AES_CR_KEYLEN_Pos 13
/AES_CR_KEYLEN_Msk (0x3U << AES_CR_KEYLEN_Pos)
0AES_CR_KEYLEN_128BIT (0x0U << AES_CR_KEYLEN_Pos)
1AES_CR_KEYLEN_192BIT (0x1U << AES_CR_KEYLEN_Pos)
2AES_CR_KEYLEN_256BIT (0x2U << AES_CR_KEYLEN_Pos)
3AES_CR_KEYLEN_ (0x3U << AES_CR_KEYLEN_Pos)
5AES_CR_DMAOEN_Pos 12
:AES_CR_DMAOEN_Msk (0x1U << AES_CR_DMAOEN_Pos)
=AES_CR_DMAIEN_Pos 11
BAES_CR_DMAIEN_Msk (0x1U << AES_CR_DMAIEN_Pos)
EAES_CR_CHMOD_Pos 5
KAES_CR_CHMOD_Msk (0x3U << AES_CR_CHMOD_Pos)
LAES_CR_CHMOD_ECB (0x0U << AES_CR_CHMOD_Pos)
MAES_CR_CHMOD_CBC (0x1U << AES_CR_CHMOD_Pos)
NAES_CR_CHMOD_CTR (0x2U << AES_CR_CHMOD_Pos)
OAES_CR_CHMOD_MULTH (0x3U << AES_CR_CHMOD_Pos)
QAES_CR_MODE_Pos 3
XAES_CR_MODE_Msk (0x3U << AES_CR_MODE_Pos)
YAES_CR_MODE_ENCRYPT (0x0U << AES_CR_MODE_Pos)
ZAES_CR_MODE_KEYEXP (0x1U << AES_CR_MODE_Pos)
[AES_CR_MODE_DECRYPT (0x2U << AES_CR_MODE_Pos)
\AES_CR_MODE_KEYEXPDECRYPT (0x3U << AES_CR_MODE_Pos)
^AES_CR_DATATYP_Pos 1
dAES_CR_DATATYP_Msk (0x3U << AES_CR_DATATYP_Pos)
eAES_CR_DATATYP_32BITNOEX (0x0U << AES_CR_DATATYP_Pos)
fAES_CR_DATATYP_16BITEX (0x1U << AES_CR_DATATYP_Pos)
gAES_CR_DATATYP_8BITEX (0x2U << AES_CR_DATATYP_Pos)
hAES_CR_DATATYP_1BITEX (0x3U << AES_CR_DATATYP_Pos)
jAES_CR_EN_Pos 0
oAES_CR_EN_Msk (0x1U << AES_CR_EN_Pos)
sAES_IER_WRERR_IE_Pos 2
tAES_IER_WRERR_IE_Msk (0x1U << AES_IER_WRERR_IE_Pos)
vAES_IER_RDERR_IE_Pos 1
wAES_IER_RDERR_IE_Msk (0x1U << AES_IER_RDERR_IE_Pos)
yAES_IER_CCF_IE_Pos 0
zAES_IER_CCF_IE_Msk (0x1U << AES_IER_CCF_IE_Pos)
|AES_DIR_DIN_Pos 0

AES_DIR_DIN_Msk (0xffffffffU << AES_DIR_DIN_Pos)
ƒ
AES_DOR_DOUT_Pos 0
ˆ
AES_DOR_DOUT_Msk (0xffffffffU << AES_DOR_DOUT_Pos)
Š
AES_KEY0_KEYx_Pos 0
Œ
AES_KEY0_KEYx_Msk (0xffffffffU << AES_KEY0_KEYx_Pos)
Ž
AES_KEY1_KEYx_Pos 0

AES_KEY1_KEYx_Msk (0xffffffffU << AES_KEY1_KEYx_Pos)
’
AES_KEY2_KEYx_Pos 0
”
AES_KEY2_KEYx_Msk (0xffffffffU << AES_KEY2_KEYx_Pos)
–
AES_KEY3_KEYx_Pos 0
˜
AES_KEY3_KEYx_Msk (0xffffffffU << AES_KEY3_KEYx_Pos)
š
AES_KEY4_KEYx_Pos 0
œ
AES_KEY4_KEYx_Msk (0xffffffffU << AES_KEY4_KEYx_Pos)
ž
AES_KEY5_KEYx_Pos 0
 
AES_KEY5_KEYx_Msk (0xffffffffU << AES_KEY5_KEYx_Pos)
¢
AES_KEY6_KEYx_Pos 0
¤
AES_KEY6_KEYx_Msk (0xffffffffU << AES_KEY6_KEYx_Pos)
¦
AES_KEY7_KEYx_Pos 0
¨
AES_KEY7_KEYx_Msk (0xffffffffU << AES_KEY7_KEYx_Pos)
ª
AES_IVR0_IVRx_Pos 0
¬
AES_IVR0_IVRx_Msk (0xffffffffU << AES_IVR0_IVRx_Pos)
®
AES_IVR1_IVRx_Pos 0
°
AES_IVR1_IVRx_Msk (0xffffffffU << AES_IVR1_IVRx_Pos)
²
AES_IVR2_IVRx_Pos 0
´
AES_IVR2_IVRx_Msk (0xffffffffU << AES_IVR2_IVRx_Pos)
¶
AES_IVR3_IVRx_Pos 0
¸
AES_IVR3_IVRx_Msk (0xffffffffU << AES_IVR3_IVRx_Pos)
º
AES_H0_Hx_Pos 0
¼
AES_H0_Hx_Msk (0xffffffffU << AES_H0_Hx_Pos)
¾
AES_H1_Hx_Pos 0
À
AES_H1_Hx_Msk (0xffffffffU << AES_H1_Hx_Pos)
Â
AES_H2_Hx_Pos 0
Ä
AES_H2_Hx_Msk (0xffffffffU << AES_H2_Hx_Pos)
Æ
AES_H3_Hx_Pos 0
È
AES_H3_Hx_Msk (0xffffffffU << AES_H3_Hx_Pos)
Ê
AES_ISR_WRERR_Pos 2
Ë
AES_ISR_WRERR_Msk (0x1U << AES_ISR_WRERR_Pos)
Í
AES_ISR_RDERR_Pos 1
Î
AES_ISR_RDERR_Msk (0x1U << AES_ISR_RDERR_Pos)
Ð
AES_ISR_CCF_Pos 0
Ó
AES_ISR_CCF_Msk (0x1U << AES_ISR_CCF_Pos)`T
 




..\Drivers\..\Core\Include\fm33a0xxev_aes.h
FM33A0XXEV.h

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..\Drivers\fm33a0xxev_aes.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM*ÞKEYLENf
#CHMODf
#MODEf
#DATATYPf
#DMAOEN
#DMAIEN
#WERRIE
#RERRIE
#CCFIE
#AESEN
#PAES_InitTypeDef½
'
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•
–


__FM33A0XXEV_ADC_H 
ADC_CR_ADC_IE_Pos 7
ADC_CR_ADC_IE_Msk (0x1U << ADC_CR_ADC_IE_Pos)
ADC_CR_ACC_IE_Pos 6
ADC_CR_ACC_IE_Msk (0x1U << ADC_CR_ACC_IE_Pos)
ADC_CR_HPEN_Pos 3
"ADC_CR_HPEN_Msk (0x1U << ADC_CR_HPEN_Pos)
#ADC_CR_HPEN_1MHZ (0x0U << ADC_CR_HPEN_Pos)
$ADC_CR_HPEN_2MHZ (0x1U << ADC_CR_HPEN_Pos)
&ADC_CR_MODE_Pos 2
)ADC_CR_MODE_Msk (0x1U << ADC_CR_MODE_Pos)
*ADC_CR_MODE_INNER (0x0U << ADC_CR_MODE_Pos)
+ADC_CR_MODE_EXTERNAL (0x1U << ADC_CR_MODE_Pos)
-ADC_CR_RSTCTRL_EN_Pos 1
0ADC_CR_RSTCTRL_EN_Msk (0x1U << ADC_CR_RSTCTRL_EN_Pos)
4ADC_CR_EN_Pos 0
9ADC_CR_EN_Msk (0x1U << ADC_CR_EN_Pos)
>ADC_TRIM_ADC_TRIM_Pos 0
AADC_TRIM_ADC_TRIM_Msk (0x7ffU << ADC_TRIM_ADC_TRIM_Pos)
CADC_DR_ADC_DATA_Pos 0
FADC_DR_ADC_DATA_Msk (0xffffU << ADC_DR_ADC_DATA_Pos)
HADC_ISR_INIT_RDY_Pos 9
MADC_ISR_INIT_RDY_Msk (0x1U << ADC_ISR_INIT_RDY_Pos)
OADC_ISR_ACC_IF_Pos 8
PADC_ISR_ACC_IF_Msk (0x1U << ADC_ISR_ACC_IF_Pos)
RADC_ISR_ADC_DONE_Pos 1
TADC_ISR_ADC_DONE_Msk (0x1U << ADC_ISR_ADC_DONE_Pos)
VADC_ISR_ADC_IF_Pos 0
WADC_ISR_ADC_IF_Msk (0x1U << ADC_ISR_ADC_IF_Pos)
YADC_CFGR_ACC_PERIOD_Pos 16
`ADC_CFGR_ACC_PERIOD_Msk (0x7U << ADC_CFGR_ACC_PERIOD_Pos)
aADC_CFGR_ACC_PERIOD_10BITS (0x0U << ADC_CFGR_ACC_PERIOD_Pos)
bADC_CFGR_ACC_PERIOD_11BITS (0x1U << ADC_CFGR_ACC_PERIOD_Pos)
cADC_CFGR_ACC_PERIOD_12BITS (0x2U << ADC_CFGR_ACC_PERIOD_Pos)
dADC_CFGR_ACC_PERIOD_13BITS (0x3U << ADC_CFGR_ACC_PERIOD_Pos)
eADC_CFGR_ACC_PERIOD_14BITS (0x4U << ADC_CFGR_ACC_PERIOD_Pos)
gADC_CFGR_RST_CTRL_DELAY_Pos 8
lADC_CFGR_RST_CTRL_DELAY_Msk (0xffU << ADC_CFGR_RST_CTRL_DELAY_Pos)
nADC_CFGR_BUFEN_Pos 5
oADC_CFGR_BUFEN_Msk (0x1U << ADC_CFGR_BUFEN_Pos)
qADC_CFGR_BUFSEL_Pos 0
‚
ADC_CFGR_BUFSEL_Msk (0xfU << ADC_CFGR_BUFSEL_Pos)
ƒ
ADC_CFGR_BUFSEL_ADC_IN1 (0x1U << ADC_CFGR_BUFSEL_Pos)
„
ADC_CFGR_BUFSEL_ADC_IN2 (0x2U << ADC_CFGR_BUFSEL_Pos)
…
ADC_CFGR_BUFSEL_ADC_IN3 (0x3U << ADC_CFGR_BUFSEL_Pos)
†
ADC_CFGR_BUFSEL_ADC_IN4 (0x4U << ADC_CFGR_BUFSEL_Pos)
‡
ADC_CFGR_BUFSEL_ADC_IN5 (0x5U << ADC_CFGR_BUFSEL_Pos)
ˆ
ADC_CFGR_BUFSEL_ADC_IN6 (0x6U << ADC_CFGR_BUFSEL_Pos)
‰
ADC_CFGR_BUFSEL_ADC_IN7 (0x7U << ADC_CFGR_BUFSEL_Pos)
Š
ADC_CFGR_BUFSEL_ADC_IN8 (0x8U << ADC_CFGR_BUFSEL_Pos)
‹
ADC_CFGR_BUFSEL_ADC_IN9 (0x9U << ADC_CFGR_BUFSEL_Pos)
Œ
ADC_CFGR_BUFSEL_ADC_IN10 (0xaU << ADC_CFGR_BUFSEL_Pos)

ADC_CFGR_BUFSEL_ADC_IN11 (0xbU << ADC_CFGR_BUFSEL_Pos)
Ž
ADC_CFGR_BUFSEL_ADC_IN12 (0xcU << ADC_CFGR_BUFSEL_Pos)

ADC_CFGR_BUFSEL_VBAT (0xeU << ADC_CFGR_BUFSEL_Pos)

ADC_CFGR_BUFSEL_TS (0xfU << ADC_CFGR_BUFSEL_Pos)
’
CIC_DR_ADC_CIC_DATA_Pos 0
“
CIC_DR_ADC_CIC_DATA_Msk (0xffffffU << CIC_DR_ADC_CIC_DATA_Pos)
•
CIC_OS_ADC_CIC_OS_Pos 0
–
CIC_OS_ADC_CIC_OS_Msk (0xffffffU << CIC_OS_ADC_CIC_OS_Pos)
˜
CIC_USDR_ADC_CIC_USDR_Pos 0
™
CIC_USDR_ADC_CIC_USDR_Msk (0xffffffU << CIC_USDR_ADC_CIC_USDR_Pos)
›
CIC_CR_CIC_EN_Pos 31
ž
CIC_CR_CIC_EN_Msk (0x1U << CIC_CR_CIC_EN_Pos)
¢
CIC_CR_NS_DISC_Pos 8
¥
CIC_CR_NS_DISC_Msk (0xffU << CIC_CR_NS_DISC_Pos)
§
CIC_CR_OVR_IE_Pos 7
ª
CIC_CR_OVR_IE_Msk (0x1U << CIC_CR_OVR_IE_Pos)
®
CIC_CR_CIC_IE_Pos 6
±
CIC_CR_CIC_IE_Msk (0x1U << CIC_CR_CIC_IE_Pos)
µ
CIC_CR_TRUNC_Pos 3
·
CIC_CR_TRUNC_Msk (0x7U << CIC_CR_TRUNC_Pos)
¹
CIC_CR_OSR_Pos 0
Â
CIC_CR_OSR_Msk (0x7U << CIC_CR_OSR_Pos)
Ã
CIC_CR_OSR_X8 (0x0U << CIC_CR_OSR_Pos)
Ä
CIC_CR_OSR_X16 (0x1U << CIC_CR_OSR_Pos)
Å
CIC_CR_OSR_X32 (0x2U << CIC_CR_OSR_Pos)
Æ
CIC_CR_OSR_X64 (0x3U << CIC_CR_OSR_Pos)
Ç
CIC_CR_OSR_X128 (0x4U << CIC_CR_OSR_Pos)
È
CIC_CR_OSR_X256 (0x5U << CIC_CR_OSR_Pos)
É
CIC_CR_OSR_X512 (0x6U << CIC_CR_OSR_Pos)
Ê
CIC_CR_OSR_X1024 (0x7U << CIC_CR_OSR_Pos)
Ì
CIC_ISR_CIC_OVR_Pos 1
Í
CIC_ISR_CIC_OVR_Msk (0x1U << CIC_ISR_CIC_OVR_Pos)
Ï
CIC_ISR_CIC_IF_Pos 0
Ð
CIC_ISR_CIC_IF_Msk (0x1U << CIC_ISR_CIC_IF_Pos)`T
 




..\Drivers\..\Core\Include\fm33a0xxev_adc.h
FM33A0XXEV.h

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..\Drivers\fm33a0xxev_adc.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM
˜
™
š
›


_UPPER_COMPUTER_H_ 
UC_RANDOM_CREATED (rand() % 100) << 8 | (rand() % 100)
UC_PROTOCOL_HEAD_LENGTH (sizeof(struct uc_protocol_head) - sizeof(struct uc_log_time_data_field))
 UC_PROTOCOL_VER 0x0001
UC_PASSWORD UC_PROTOCOL_VER
UC_RECV_LEN_MAX 1024
UC_CMD_LOGIN 0x11
UC_CMD_EXIT 0x12
UC_CMD_WRITE 0x42
UC_CMD_READ 0x52
UC_CMD_GET_LOG_RECENT 0x82
UC_CMD_GET_LOG_TIME 0x83
UC_CMD_IAP 0x99fghÔÉ
 




..\Function\UPPER_COMPUTER\..\Core\..\Soft\upper_computer.h
define_all.hsundry.hupper_computer_rw_api.h
upper_computer_read_log_api.h
upper_computer_iap_api.h


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..\Function\UPPER_COMPUTER\upper_computer.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM
UC_UNKNOWNUC_OK
UC_PLANT_NUM_ERRUC_PASSWORD_ERRPUC_LOGIN_STATUSÍ
#êUC_GENERALUC_IDEA_CREATED4UC_ENNE#UC_GOLD_CARDV4PUC_PLANT_NUM'

+)ªuc_log_time_data_fieldlog_table_idV
#º8

log_start_time_bcd¯
#ß8

log_end_time_bcdÔ
#log_num_limitV
#log_continue_flag8
#)uc_protocol_headframe_start_code8
#uc_type8
#
uc_admin8
#plant_numberV
#protocol_verV
#random_numberV
#cmd_code8
#    data_field_lengthV
#
uc_log_time_data_field_s~
#SÆ€ž8

ÿuc_recv_bufuc_protocol_head_s*PUC_RECV_DATA_UNION_T 
E*±ƒuc_recv_buf_unionF#uc_recv_lengthV
#€uc_recv_flagÓ#‚PUC_RECV_PARA_Tb
Mt8
quc_return_flag_gÇ

quc_recv_para_g±

6üÍuc_return_flag_gäuc_recv_para_g
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ž
Ÿ


__FM33A0XXEV_BSTIM_H 
BSTIM_CR1_ARPE_Pos 7
BSTIM_CR1_ARPE_Msk (0x1U << BSTIM_CR1_ARPE_Pos)
 BSTIM_CR1_OPM_Pos 3
#BSTIM_CR1_OPM_Msk (0x1U << BSTIM_CR1_OPM_Pos)
$BSTIM_CR1_OPM_CONTINUE (0x0U << BSTIM_CR1_OPM_Pos)
%BSTIM_CR1_OPM_STOP (0x1U << BSTIM_CR1_OPM_Pos)
'BSTIM_CR1_URS_Pos 2
-BSTIM_CR1_URS_Msk (0x1U << BSTIM_CR1_URS_Pos)
.BSTIM_CR1_URS_ALL (0x0U << BSTIM_CR1_URS_Pos)
/BSTIM_CR1_URS_COUNT (0x1U << BSTIM_CR1_URS_Pos)
1BSTIM_CR1_UDIS_Pos 1
7BSTIM_CR1_UDIS_Msk (0x1U << BSTIM_CR1_UDIS_Pos)
;BSTIM_CR1_CEN_Pos 0
?BSTIM_CR1_CEN_Msk (0x1U << BSTIM_CR1_CEN_Pos)
DBSTIM_CR2_MMS_Pos 4
KBSTIM_CR2_MMS_Msk (0x7U << BSTIM_CR2_MMS_Pos)
MBSTIM_IER_UIE_Pos 0
PBSTIM_IER_UIE_Msk (0x1U << BSTIM_IER_UIE_Pos)
TBSTIM_ISR_UIF_Pos 0
YBSTIM_ISR_UIF_Msk (0x1U << BSTIM_ISR_UIF_Pos)
[BSTIM_EGR_UG_Pos 0
]BSTIM_EGR_UG_Msk (0x1U << BSTIM_EGR_UG_Pos)
_BSTIM_CNTR_CNT_Pos 0
`BSTIM_CNTR_CNT_Msk (0xffffffffU << BSTIM_CNTR_CNT_Pos)
bBSTIM_PSCR_PSC_Pos 0
eBSTIM_PSCR_PSC_Msk (0xffffffffU << BSTIM_PSCR_PSC_Pos)
gBSTIM_ARR_ARR_Pos 0
iBSTIM_ARR_ARR_Msk (0xffffffffU << BSTIM_ARR_ARR_Pos)`V
 




..\Drivers\..\Core\Include\fm33a0xxev_bstim.h
FM33A0XXEV.h

À
..\Drivers\fm33a0xxev_bstim.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM
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__FM33A0XXEV_COMP_H 
COMP_CR1_DFLEN_Pos 19
COMP_CR1_DFLEN_Msk (0x1fU << COMP_CR1_DFLEN_Pos)
COMP_CR1_DFLEN_X3 (0x2U << COMP_CR1_DFLEN_Pos)
COMP_CR1_DFLEN_X32 (0x1fU << COMP_CR1_DFLEN_Pos)
!COMP_CR1_WINMODE_Pos 18
$COMP_CR1_WINMODE_Msk (0x1U << COMP_CR1_WINMODE_Pos)
(COMP_CR1_POLAR_Pos 17
+COMP_CR1_POLAR_Msk (0x1U << COMP_CR1_POLAR_Pos)
,COMP_CR1_POLAR_POS (0x0U << COMP_CR1_POLAR_Pos)
-COMP_CR1_POLAR_NEG (0x1U << COMP_CR1_POLAR_Pos)
/COMP_CR1_DFEN_Pos 16
2COMP_CR1_DFEN_Msk (0x1U << COMP_CR1_DFEN_Pos)
6COMP_CR1_CMP1OR_Pos 9
7COMP_CR1_CMP1OR_Msk (0x1U << COMP_CR1_CMP1OR_Pos)
9COMP_CR1_CMP1OF_Pos 8
:COMP_CR1_CMP1OF_Msk (0x1U << COMP_CR1_CMP1OF_Pos)
<COMP_CR1_V1NSEL_Pos 4
ECOMP_CR1_V1NSEL_Msk (0x7U << COMP_CR1_V1NSEL_Pos)
FCOMP_CR1_V1NSEL_COMP1_INN1 (0x0U << COMP_CR1_V1NSEL_Pos)
GCOMP_CR1_V1NSEL_COMP1_INN2 (0x1U << COMP_CR1_V1NSEL_Pos)
HCOMP_CR1_V1NSEL_VREF (0x2U << COMP_CR1_V1NSEL_Pos)
ICOMP_CR1_V1NSEL_3_4_VREF (0x3U << COMP_CR1_V1NSEL_Pos)
JCOMP_CR1_V1NSEL_1_2_VREF (0x4U << COMP_CR1_V1NSEL_Pos)
KCOMP_CR1_V1NSEL_1_4_VREF (0x5U << COMP_CR1_V1NSEL_Pos)
LCOMP_CR1_V1NSEL_1_8_VREF (0x6U << COMP_CR1_V1NSEL_Pos)
NCOMP_CR1_V1PSEL_Pos 1
SCOMP_CR1_V1PSEL_Msk (0x3U << COMP_CR1_V1PSEL_Pos)
TCOMP_CR1_V1PSEL_COMP1_INP1 (0x0U << COMP_CR1_V1PSEL_Pos)
UCOMP_CR1_V1PSEL_COMP1_INP2 (0x1U << COMP_CR1_V1PSEL_Pos)
VCOMP_CR1_V1PSEL_COMP1_INP3 (0x2U << COMP_CR1_V1PSEL_Pos)
WCOMP_CR1_V1PSEL_COMP1_INP4 (0x3U << COMP_CR1_V1PSEL_Pos)
YCOMP_CR1_CMP1EN_Pos 0
\COMP_CR1_CMP1EN_Msk (0x1U << COMP_CR1_CMP1EN_Pos)
`COMP_CR2_DFLEN_Pos 19
dCOMP_CR2_DFLEN_Msk (0x1fU << COMP_CR2_DFLEN_Pos)
eCOMP_CR2_DFLEN_X3 (0x2U << COMP_CR2_DFLEN_Pos)
fCOMP_CR2_DFLEN_X32 (0x1fU << COMP_CR2_DFLEN_Pos)
hCOMP_CR2_WINMODE_Pos 18
kCOMP_CR2_WINMODE_Msk (0x1U << COMP_CR2_WINMODE_Pos)
oCOMP_CR2_POLAR_Pos 17
rCOMP_CR2_POLAR_Msk (0x1U << COMP_CR2_POLAR_Pos)
sCOMP_CR2_POLAR_POS (0x0U << COMP_CR2_POLAR_Pos)
tCOMP_CR2_POLAR_NEG (0x1U << COMP_CR2_POLAR_Pos)
vCOMP_CR2_DFEN_Pos 16
yCOMP_CR2_DFEN_Msk (0x1U << COMP_CR2_DFEN_Pos)
}COMP_CR2_CMP2OR_Pos 9
~COMP_CR2_CMP2OR_Msk (0x1U << COMP_CR2_CMP2OR_Pos)
€
COMP_CR2_CMP2OF_Pos 8

COMP_CR2_CMP2OF_Msk (0x1U << COMP_CR2_CMP2OF_Pos)
ƒ
COMP_CR2_V2NSEL_Pos 4
Œ
COMP_CR2_V2NSEL_Msk (0x7U << COMP_CR2_V2NSEL_Pos)

COMP_CR2_V2NSEL_COMP2_INN1 (0x0U << COMP_CR2_V2NSEL_Pos)
Ž
COMP_CR2_V2NSEL_COMP2_INN2 (0x1U << COMP_CR2_V2NSEL_Pos)

COMP_CR2_V2NSEL_VREF (0x2U << COMP_CR2_V2NSEL_Pos)

COMP_CR2_V2NSEL_3_4_VREF (0x3U << COMP_CR2_V2NSEL_Pos)
‘
COMP_CR2_V2NSEL_1_2_VREF (0x4U << COMP_CR2_V2NSEL_Pos)
’
COMP_CR2_V2NSEL_1_4_VREF (0x5U << COMP_CR2_V2NSEL_Pos)
“
COMP_CR2_V2NSEL_1_8_VREF (0x6U << COMP_CR2_V2NSEL_Pos)
”
COMP_CR2_V2NSEL_REFIN (0x7U << COMP_CR2_V2NSEL_Pos)
–
COMP_CR2_V2PSEL_Pos 1
ž
COMP_CR2_V2PSEL_Msk (0x7U << COMP_CR2_V2PSEL_Pos)
Ÿ
COMP_CR2_V2PSEL_COMP2_INP1 (0x0U << COMP_CR2_V2PSEL_Pos)
 
COMP_CR2_V2PSEL_COMP2_INP2 (0x1U << COMP_CR2_V2PSEL_Pos)
¡
COMP_CR2_V2PSEL_COMP1_INP1 (0x2U << COMP_CR2_V2PSEL_Pos)
¢
COMP_CR2_V2PSEL_COMP1_INP2 (0x3U << COMP_CR2_V2PSEL_Pos)
£
COMP_CR2_V2PSEL_AVREF (0x4U << COMP_CR2_V2PSEL_Pos)
¤
COMP_CR2_V2PSEL_VDD15 (0x5U << COMP_CR2_V2PSEL_Pos)
¦
COMP_CR2_CMP2EN_Pos 0
©
COMP_CR2_CMP2EN_Msk (0x1U << COMP_CR2_CMP2EN_Pos)
­
COMP_ICR_OOW_IE_Pos 9
®
COMP_ICR_OOW_IE_Msk (0x1U << COMP_ICR_OOW_IE_Pos)
°
COMP_ICR_WIN_IE_Pos 8
±
COMP_ICR_WIN_IE_Msk (0x1U << COMP_ICR_WIN_IE_Pos)
³
COMP_ICR_BUFBYP_Pos 7
¶
COMP_ICR_BUFBYP_Msk (0x1U << COMP_ICR_BUFBYP_Pos)
¸
COMP_ICR_BUF_OFF_Pos 6
»
COMP_ICR_BUF_OFF_Msk (0x1U << COMP_ICR_BUF_OFF_Pos)
½
COMP_ICR_CMP2SEL_Pos 4
Á
COMP_ICR_CMP2SEL_Msk (0x3U << COMP_ICR_CMP2SEL_Pos)
Â
COMP_ICR_CMP2SEL_BOTH (0x0U << COMP_ICR_CMP2SEL_Pos)
Ã
COMP_ICR_CMP2SEL_RISING (0x1U << COMP_ICR_CMP2SEL_Pos)
Ä
COMP_ICR_CMP2SEL_FALLING (0x2U << COMP_ICR_CMP2SEL_Pos)
Æ
COMP_ICR_CMP1SEL_Pos 2
Ê
COMP_ICR_CMP1SEL_Msk (0x3U << COMP_ICR_CMP1SEL_Pos)
Ë
COMP_ICR_CMP1SEL_BOTH (0x0U << COMP_ICR_CMP1SEL_Pos)
Ì
COMP_ICR_CMP1SEL_RISING (0x1U << COMP_ICR_CMP1SEL_Pos)
Í
COMP_ICR_CMP1SEL_FALLING (0x2U << COMP_ICR_CMP1SEL_Pos)
Ï
COMP_ICR_CMP2IE_Pos 1
Ð
COMP_ICR_CMP2IE_Msk (0x1U << COMP_ICR_CMP2IE_Pos)
Ò
COMP_ICR_CMP1IE_Pos 0
Ó
COMP_ICR_CMP1IE_Msk (0x1U << COMP_ICR_CMP1IE_Pos)
Õ
COMP_ISR_OOW_IF_Pos 3
Ö
COMP_ISR_OOW_IF_Msk (0x1U << COMP_ISR_OOW_IF_Pos)
Ø
COMP_ISR_WIN_IF_Pos 2
Ù
COMP_ISR_WIN_IF_Msk (0x1U << COMP_ISR_WIN_IF_Pos)
Û
COMP_ISR_CMP2IF_Pos 1
Ü
COMP_ISR_CMP2IF_Msk (0x1U << COMP_ISR_CMP2IF_Pos)
Þ
COMP_ISR_CMP1IF_Pos 0
ß
COMP_ISR_CMP1IF_Msk (0x1U << COMP_ISR_CMP1IF_Pos)
á
COMP_PCR_HSCMPBUF_EN_Pos 2
ä
COMP_PCR_HSCMPBUF_EN_Msk (0x1U << COMP_PCR_HSCMPBUF_EN_Pos)
å
COMP_PCR_HSCMPBUF_EN_SLOW (0x0U << COMP_PCR_HSCMPBUF_EN_Pos)
æ
COMP_PCR_HSCMPBUF_EN_FAST (0x1U << COMP_PCR_HSCMPBUF_EN_Pos)
è
COMP_PCR_HSCMP2_EN_Pos 1
ë
COMP_PCR_HSCMP2_EN_Msk (0x1U << COMP_PCR_HSCMP2_EN_Pos)
ì
COMP_PCR_HSCMP2_EN_SLOW (0x0U << COMP_PCR_HSCMP2_EN_Pos)
í
COMP_PCR_HSCMP2_EN_FAST (0x1U << COMP_PCR_HSCMP2_EN_Pos)
ï
COMP_PCR_HSCMP1_EN_Pos 0
ò
COMP_PCR_HSCMP1_EN_Msk (0x1U << COMP_PCR_HSCMP1_EN_Pos)
ó
COMP_PCR_HSCMP1_EN_SLOW (0x0U << COMP_PCR_HSCMP1_EN_Pos)
ô
COMP_PCR_HSCMP1_EN_FAST (0x1U << COMP_PCR_HSCMP1_EN_Pos)`U
 




..\Drivers\..\Core\Include\fm33a0xxev_comp.h
FM33A0XXEV.h

¼
..\Drivers\fm33a0xxev_comp.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM
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¦
§


__FM33A0XXEV_RMU_H 
RMU_PDRCR_PDRCFG_Pos 1
RMU_PDRCR_PDRCFG_Msk (0x3U << RMU_PDRCR_PDRCFG_Pos)
RMU_PDRCR_PDRCFG_1P5V (0x0U << RMU_PDRCR_PDRCFG_Pos)
RMU_PDRCR_PDRCFG_1P25V (0x1U << RMU_PDRCR_PDRCFG_Pos)
RMU_PDRCR_PDRCFG_1P35V (0x2U << RMU_PDRCR_PDRCFG_Pos)
RMU_PDRCR_PDRCFG_1P4V (0x3U << RMU_PDRCR_PDRCFG_Pos)
 RMU_PDRCR_PDREN_Pos 0
!RMU_PDRCR_PDREN_Msk (0x1U << RMU_PDRCR_PDREN_Pos)
%RMU_BORCR_BOR_PDRCFG_Pos 1
&RMU_BORCR_BOR_PDRCFG_Msk (0x3U << RMU_BORCR_BOR_PDRCFG_Pos)
'RMU_BORCR_BOR_PDRCFG_1P7V (0x0U << RMU_BORCR_BOR_PDRCFG_Pos)
(RMU_BORCR_BOR_PDRCFG_1P6V (0x1U << RMU_BORCR_BOR_PDRCFG_Pos)
)RMU_BORCR_BOR_PDRCFG_1P65V (0x2U << RMU_BORCR_BOR_PDRCFG_Pos)
*RMU_BORCR_BOR_PDRCFG_1P75V (0x3U << RMU_BORCR_BOR_PDRCFG_Pos)
,RMU_BORCR_OFF_BOR_Pos 0
-RMU_BORCR_OFF_BOR_Msk (0x1U << RMU_BORCR_OFF_BOR_Pos)
1RMU_RSTCFGR_LKUPRST_EN_Pos 1
2RMU_RSTCFGR_LKUPRST_EN_Msk (0x1U << RMU_RSTCFGR_LKUPRST_EN_Pos)
6RMU_SOFTRST_SOFTRST_Pos 0
7RMU_SOFTRST_SOFTRST_Msk (0xffffffffU << RMU_SOFTRST_SOFTRST_Pos)
9RMU_RSR_NRSTN_FLAG_Pos 11
:RMU_RSR_NRSTN_FLAG_Msk (0x1U << RMU_RSR_NRSTN_FLAG_Pos)
<RMU_RSR_TESTN_FLAG_Pos 10
=RMU_RSR_TESTN_FLAG_Msk (0x1U << RMU_RSR_TESTN_FLAG_Pos)
?RMU_RSR_PORN_FLAG_Pos 9
@RMU_RSR_PORN_FLAG_Msk (0x1U << RMU_RSR_PORN_FLAG_Pos)
BRMU_RSR_PDRN_FLAG_Pos 8
CRMU_RSR_PDRN_FLAG_Msk (0x1U << RMU_RSR_PDRN_FLAG_Pos)
ERMU_RSR_SOFTN_FLAG_Pos 5
FRMU_RSR_SOFTN_FLAG_Msk (0x1U << RMU_RSR_SOFTN_FLAG_Pos)
HRMU_RSR_IWDTN_FLAG_Pos 4
IRMU_RSR_IWDTN_FLAG_Msk (0x1U << RMU_RSR_IWDTN_FLAG_Pos)
KRMU_RSR_WWDTN_FLAG_Pos 2
LRMU_RSR_WWDTN_FLAG_Msk (0x1U << RMU_RSR_WWDTN_FLAG_Pos)
NRMU_RSR_LKUPN_FLAG_Pos 1
ORMU_RSR_LKUPN_FLAG_Msk (0x1U << RMU_RSR_LKUPN_FLAG_Pos)
QRMU_RSR_NVICN_FLAG_Pos 0
RRMU_RSR_NVICN_FLAG_Msk (0x1U << RMU_RSR_NVICN_FLAG_Pos)
TRMU_PRSTEN_PERHRSTEN_Pos 0
URMU_PRSTEN_PERHRSTEN_Msk (0xffffffffU << RMU_PRSTEN_PERHRSTEN_Pos)
WRMU_AHBRST_HASHRST_Pos 2
XRMU_AHBRST_HASHRST_Msk (0x1U << RMU_AHBRST_HASHRST_Pos)
\RMU_AHBRST_PAERST_Pos 1
]RMU_AHBRST_PAERST_Msk (0x1U << RMU_AHBRST_PAERST_Pos)
aRMU_AHBRST_DMARST_Pos 0
bRMU_AHBRST_DMARST_Msk (0x1U << RMU_AHBRST_DMARST_Pos)
fRMU_APBRST1_UART5RST_Pos 31
gRMU_APBRST1_UART5RST_Msk (0x1U << RMU_APBRST1_UART5RST_Pos)
kRMU_APBRST1_UART4RST_Pos 30
lRMU_APBRST1_UART4RST_Msk (0x1U << RMU_APBRST1_UART4RST_Pos)
pRMU_APBRST1_UART3RST_Pos 29
qRMU_APBRST1_UART3RST_Msk (0x1U << RMU_APBRST1_UART3RST_Pos)
uRMU_APBRST1_UART2RST_Pos 28
vRMU_APBRST1_UART2RST_Msk (0x1U << RMU_APBRST1_UART2RST_Pos)
zRMU_APBRST1_TIMARST_Pos 23
{RMU_APBRST1_TIMARST_Msk (0x1U << RMU_APBRST1_TIMARST_Pos)
RMU_APBRST1_LCDRST_Pos 16
€
RMU_APBRST1_LCDRST_Msk (0x1U << RMU_APBRST1_LCDRST_Pos)
„
RMU_APBRST1_U7816RST_Pos 14
…
RMU_APBRST1_U7816RST_Msk (0x1U << RMU_APBRST1_U7816RST_Pos)
‰
RMU_APBRST1_SPI4RST_Pos 12
Š
RMU_APBRST1_SPI4RST_Msk (0x1U << RMU_APBRST1_SPI4RST_Pos)
Ž
RMU_APBRST1_SPI3RST_Pos 11

RMU_APBRST1_SPI3RST_Msk (0x1U << RMU_APBRST1_SPI3RST_Pos)
“
RMU_APBRST1_SPI2RST_Pos 10
”
RMU_APBRST1_SPI2RST_Msk (0x1U << RMU_APBRST1_SPI2RST_Pos)
˜
RMU_APBRST1_LPUART0RST_Pos 6
™
RMU_APBRST1_LPUART0RST_Msk (0x1U << RMU_APBRST1_LPUART0RST_Pos)

RMU_APBRST1_I2C1RST_Pos 3
ž
RMU_APBRST1_I2C1RST_Msk (0x1U << RMU_APBRST1_I2C1RST_Pos)
¢
RMU_APBRST1_LPTRST_Pos 0
£
RMU_APBRST1_LPTRST_Msk (0x1U << RMU_APBRST1_LPTRST_Pos)
§
RMU_APBRST2_UART1RST_Pos 31
¨
RMU_APBRST2_UART1RST_Msk (0x1U << RMU_APBRST2_UART1RST_Pos)
¬
RMU_APBRST2_UART0RST_Pos 30
­
RMU_APBRST2_UART0RST_Msk (0x1U << RMU_APBRST2_UART0RST_Pos)
±
RMU_APBRST2_UARTIRRST_Pos 29
²
RMU_APBRST2_UARTIRRST_Msk (0x1U << RMU_APBRST2_UARTIRRST_Pos)
¶
RMU_APBRST2_BSTRST_Pos 28
·
RMU_APBRST2_BSTRST_Msk (0x1U << RMU_APBRST2_BSTRST_Pos)
»
RMU_APBRST2_CICRST_Pos 24
¼
RMU_APBRST2_CICRST_Msk (0x1U << RMU_APBRST2_CICRST_Pos)
À
RMU_APBRST2_ADCRST_Pos 23
Á
RMU_APBRST2_ADCRST_Msk (0x1U << RMU_APBRST2_ADCRST_Pos)
Å
RMU_APBRST2_AESRST_Pos 18
Æ
RMU_APBRST2_AESRST_Msk (0x1U << RMU_APBRST2_AESRST_Pos)
Ê
RMU_APBRST2_CRCRST_Pos 17
Ë
RMU_APBRST2_CRCRST_Msk (0x1U << RMU_APBRST2_CRCRST_Pos)
Ï
RMU_APBRST2_RNGRST_Pos 16
Ð
RMU_APBRST2_RNGRST_Msk (0x1U << RMU_APBRST2_RNGRST_Pos)
Ô
RMU_APBRST2_SPI1RST_Pos 9
Õ
RMU_APBRST2_SPI1RST_Msk (0x1U << RMU_APBRST2_SPI1RST_Pos)
Ù
RMU_APBRST2_SPI0RST_Pos 8
Ú
RMU_APBRST2_SPI0RST_Msk (0x1U << RMU_APBRST2_SPI0RST_Pos)
Þ
RMU_APBRST2_LPUART1RST_Pos 7
ß
RMU_APBRST2_LPUART1RST_Msk (0x1U << RMU_APBRST2_LPUART1RST_Pos)
ã
RMU_APBRST2_I2C0RST_Pos 4
ä
RMU_APBRST2_I2C0RST_Msk (0x1U << RMU_APBRST2_I2C0RST_Pos)
è
RMU_APBRST2_SVDRST_Pos 1
é
RMU_APBRST2_SVDRST_Msk (0x1U << RMU_APBRST2_SVDRST_Pos)
í
RMU_APBRST2_COMPRST_Pos 0
î
RMU_APBRST2_COMPRST_Msk (0x1U << RMU_APBRST2_COMPRST_Pos)`T
 




..\Drivers\..\Core\Include\fm33a0xxev_rmu.h
FM33A0XXEV.h

¼
..\Drivers\fm33a0xxev_rmu.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM
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«


__FM33A0XXEV_CRC_H 
&CRC_DR_DR_Pos 0
)CRC_DR_DR_Msk (0xffffffffU << CRC_DR_DR_Pos)
+CRC_CR_OPWD_Pos 9
.CRC_CR_OPWD_Msk (0x1U << CRC_CR_OPWD_Pos)
/CRC_CR_OPWD_BYTE (0x0U << CRC_CR_OPWD_Pos)
0CRC_CR_OPWD_WORD (0x1U << CRC_CR_OPWD_Pos)
2CRC_CR_PARA_Pos 8
5CRC_CR_PARA_Msk (0x1U << CRC_CR_PARA_Pos)
6CRC_CR_PARA_SERIAL (0x0U << CRC_CR_PARA_Pos)
7CRC_CR_PARA_PARALLEL (0x1U << CRC_CR_PARA_Pos)
9CRC_CR_RFLTIN_Pos 6
ACRC_CR_RFLTIN_Msk (0x3U << CRC_CR_RFLTIN_Pos)
BCRC_CR_RFLTIN_NONE (0x0U << CRC_CR_RFLTIN_Pos)
CCRC_CR_RFLTIN_BYTE (0x1U << CRC_CR_RFLTIN_Pos)
DCRC_CR_RFLTIN_HALFWORD (0x2U << CRC_CR_RFLTIN_Pos)
ECRC_CR_RFLTIN_WORD (0x3U << CRC_CR_RFLTIN_Pos)
GCRC_CR_RFLTO_Pos 5
LCRC_CR_RFLTO_Msk (0x1U << CRC_CR_RFLTO_Pos)
MCRC_CR_RFLTO_NON (0x0U << CRC_CR_RFLTO_Pos)
NCRC_CR_RFLTO_BYTE (0x1U << CRC_CR_RFLTO_Pos)
PCRC_CR_RES_Pos 4
SCRC_CR_RES_Msk (0x1U << CRC_CR_RES_Pos)
UCRC_CR_BUSY_Pos 3
XCRC_CR_BUSY_Msk (0x1U << CRC_CR_BUSY_Pos)
ZCRC_CR_XOR_Pos 2
]CRC_CR_XOR_Msk (0x1U << CRC_CR_XOR_Pos)
aCRC_CR_SEL_Pos 0
fCRC_CR_SEL_Msk (0x3U << CRC_CR_SEL_Pos)
gCRC_CR_SEL_CRC32 (0x0U << CRC_CR_SEL_Pos)
hCRC_CR_SEL_CRC16 (0x1U << CRC_CR_SEL_Pos)
iCRC_CR_SEL_CRC8 (0x2U << CRC_CR_SEL_Pos)
jCRC_CR_SEL_CRC7 (0x3U << CRC_CR_SEL_Pos)
lCRC_LFSR_LFSR_Pos 0
nCRC_LFSR_LFSR_Msk (0xffffffffU << CRC_LFSR_LFSR_Pos)
pCRC_XOR_XOR_Pos 0
rCRC_XOR_XOR_Msk (0xffffffffU << CRC_XOR_XOR_Pos)
tCRC_POLY_POLY_Pos 0
uCRC_POLY_POLY_Msk (0xffffffffU << CRC_POLY_POLY_Pos)`T
 




..\Drivers\..\Core\Include\fm33a0xxev_crc.h
FM33A0XXEV.h

`

..\Drivers\fm33a0xxev_crc.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM*Ê$CRCSELf
#OPWDf
#PARAf
#RFLTINf
#RFLTOf
#XOR
#CRC_XORf
#CRCPOLYf
#LFSRf
# PCRC_InitTypeDef½
$
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®
¯


__FM33A0XXEV_LCD_H 
LCD_CR_SCSEL_Pos 20
"LCD_CR_SCSEL_Msk (0x7U << LCD_CR_SCSEL_Pos)
#LCD_CR_SCSEL_LSCLK_COM (0x0U << LCD_CR_SCSEL_Pos)
$LCD_CR_SCSEL_LSCLK_8 (0x1U << LCD_CR_SCSEL_Pos)
%LCD_CR_SCSEL_LSCLK_16 (0x2U << LCD_CR_SCSEL_Pos)
&LCD_CR_SCSEL_LSCLK_32 (0x3U << LCD_CR_SCSEL_Pos)
'LCD_CR_SCSEL_LSCLK_64 (0x4U << LCD_CR_SCSEL_Pos)
(LCD_CR_SCSEL_LSCLK_128 (0x5U << LCD_CR_SCSEL_Pos)
)LCD_CR_SCSEL_LSCLK_256 (0x6U << LCD_CR_SCSEL_Pos)
*LCD_CR_SCSEL_LSCLK_512 (0x7U << LCD_CR_SCSEL_Pos)
,LCD_CR_SC_CTRL_Pos 18
1LCD_CR_SC_CTRL_Msk (0x3U << LCD_CR_SC_CTRL_Pos)
2LCD_CR_SC_CTRL_S0 (0x0U << LCD_CR_SC_CTRL_Pos)
3LCD_CR_SC_CTRL_S1 (0x1U << LCD_CR_SC_CTRL_Pos)
4LCD_CR_SC_CTRL_S2 (0x2U << LCD_CR_SC_CTRL_Pos)
5LCD_CR_SC_CTRL_S3 (0x3U << LCD_CR_SC_CTRL_Pos)
8LCD_CR_IC_CTRL_Pos 16
=LCD_CR_IC_CTRL_Msk (0x3U << LCD_CR_IC_CTRL_Pos)
>LCD_CR_IC_CTRL_L3 (0x0U << LCD_CR_IC_CTRL_Pos)
?LCD_CR_IC_CTRL_L2 (0x1U << LCD_CR_IC_CTRL_Pos)
@LCD_CR_IC_CTRL_L1 (0x2U << LCD_CR_IC_CTRL_Pos)
ALCD_CR_IC_CTRL_L0 (0x3U << LCD_CR_IC_CTRL_Pos)
CLCD_CR_ENMODE_Pos 15
FLCD_CR_ENMODE_Msk (0x1U << LCD_CR_ENMODE_Pos)
GLCD_CR_ENMODE_EXTERNALCAP (0x0U << LCD_CR_ENMODE_Pos)
HLCD_CR_ENMODE_INNERRESISTER (0x1U << LCD_CR_ENMODE_Pos)
JLCD_CR_FLICK_Pos 14
MLCD_CR_FLICK_Msk (0x1U << LCD_CR_FLICK_Pos)
QLCD_CR_BIAS_Pos 8
RLCD_CR_BIAS_Msk (0xfU << LCD_CR_BIAS_Pos)
TLCD_CR_BIASMD_Pos 5
WLCD_CR_BIASMD_Msk (0x1U << LCD_CR_BIASMD_Pos)
XLCD_CR_BIASMD_3BIAS (0x1U << LCD_CR_BIASMD_Pos)
YLCD_CR_BIASMD_4BIAS (0x0U << LCD_CR_BIASMD_Pos)
[LCD_CR_ANTIPOLAR_Pos 4
^LCD_CR_ANTIPOLAR_Msk (0x1U << LCD_CR_ANTIPOLAR_Pos)
_LCD_CR_ANTIPOLAR_GND (0x1U << LCD_CR_ANTIPOLAR_Pos)
`LCD_CR_ANTIPOLAR_FLOAT (0x0U << LCD_CR_ANTIPOLAR_Pos)
bLCD_CR_WFT_Pos 3
eLCD_CR_WFT_Msk (0x1U << LCD_CR_WFT_Pos)
fLCD_CR_WFT_BTYPE (0x1U << LCD_CR_WFT_Pos)
gLCD_CR_WFT_ATYPE (0x0U << LCD_CR_WFT_Pos)
iLCD_CR_LMUX_Pos 1
mLCD_CR_LMUX_Msk (0x3U << LCD_CR_LMUX_Pos)
nLCD_CR_LMUX_4COM (0x0U << LCD_CR_LMUX_Pos)
oLCD_CR_LMUX_6COM (0x1U << LCD_CR_LMUX_Pos)
pLCD_CR_LMUX_8COM (0x2U << LCD_CR_LMUX_Pos)
sLCD_CR_EN_Pos 0
vLCD_CR_EN_Msk (0x1U << LCD_CR_EN_Pos)
zLCD_TEST_LCCTRL_Pos 7
|LCD_TEST_LCCTRL_Msk (0x1U << LCD_TEST_LCCTRL_Pos)
}LCD_TEST_LCCTRL_LOW (0x0U << LCD_TEST_LCCTRL_Pos)
~LCD_TEST_LCCTRL_HIGH (0x1U << LCD_TEST_LCCTRL_Pos)
€
LCD_TEST_TESTEN_Pos 0
ƒ
LCD_TEST_TESTEN_Msk (0x1U << LCD_TEST_TESTEN_Pos)
‡
LCD_FCR_DF_Pos 0
ˆ
LCD_FCR_DF_Msk (0xffU << LCD_FCR_DF_Pos)
Š
LCD_FLKT_TOFF_Pos 8
Œ
LCD_FLKT_TOFF_Msk (0xffU << LCD_FLKT_TOFF_Pos)
Ž
LCD_FLKT_TON_Pos 0

LCD_FLKT_TON_Msk (0xffU << LCD_FLKT_TON_Pos)
’
LCD_IER_DONIE_Pos 1
•
LCD_IER_DONIE_Msk (0x1U << LCD_IER_DONIE_Pos)
™
LCD_IER_DOFFIE_Pos 0
œ
LCD_IER_DOFFIE_Msk (0x1U << LCD_IER_DOFFIE_Pos)
 
LCD_ISR_DONIF_Pos 1
¢
LCD_ISR_DONIF_Msk (0x1U << LCD_ISR_DONIF_Pos)
¤
LCD_ISR_DOFFIF_Pos 0
¦
LCD_ISR_DOFFIF_Msk (0x1U << LCD_ISR_DOFFIF_Pos)
¨
LCD_BSTCR_OSC_CFG_Pos 12
©
LCD_BSTCR_OSC_CFG_Msk (0xfU << LCD_BSTCR_OSC_CFG_Pos)
«
LCD_BSTCR_BUF_OFF_Pos 9
¬
LCD_BSTCR_BUF_OFF_Msk (0x1U << LCD_BSTCR_BUF_OFF_Pos)
®
LCD_BSTCR_BUFBYP_Pos 8
¯
LCD_BSTCR_BUFBYP_Msk (0x1U << LCD_BSTCR_BUFBYP_Pos)
±
LCD_BSTCR_VLCDPD_Pos 7
²
LCD_BSTCR_VLCDPD_Msk (0x1U << LCD_BSTCR_VLCDPD_Pos)
´
LCD_BSTCR_VLCDCFG_Pos 2
µ
LCD_BSTCR_VLCDCFG_Msk (0x1fU << LCD_BSTCR_VLCDCFG_Pos)
¶
LCD_BSTCR_VLCDCFG_2_4V (0x0U << LCD_BSTCR_VLCDCFG_Pos)
·
LCD_BSTCR_VLCDCFG_2_6V (0x1U << LCD_BSTCR_VLCDCFG_Pos)
¸
LCD_BSTCR_VLCDCFG_2_8V (0x2U << LCD_BSTCR_VLCDCFG_Pos)
¹
LCD_BSTCR_VLCDCFG_3_0V (0x3U << LCD_BSTCR_VLCDCFG_Pos)
º
LCD_BSTCR_VLCDCFG_3_2V (0x4U << LCD_BSTCR_VLCDCFG_Pos)
»
LCD_BSTCR_VLCDCFG_3_4V (0x5U << LCD_BSTCR_VLCDCFG_Pos)
¼
LCD_BSTCR_VLCDCFG_3_6V (0x6U << LCD_BSTCR_VLCDCFG_Pos)
½
LCD_BSTCR_VLCDCFG_3_8V (0x7U << LCD_BSTCR_VLCDCFG_Pos)
¾
LCD_BSTCR_VLCDCFG_4_0V (0x8U << LCD_BSTCR_VLCDCFG_Pos)
¿
LCD_BSTCR_VLCDCFG_4_2V (0x9U << LCD_BSTCR_VLCDCFG_Pos)
À
LCD_BSTCR_VLCDCFG_4_4V (0xaU << LCD_BSTCR_VLCDCFG_Pos)
Á
LCD_BSTCR_VLCDCFG_4_6V (0xbU << LCD_BSTCR_VLCDCFG_Pos)
Â
LCD_BSTCR_VLCDCFG_4_8V (0xcU << LCD_BSTCR_VLCDCFG_Pos)
Ã
LCD_BSTCR_VLCDCFG_5_0V (0xdU << LCD_BSTCR_VLCDCFG_Pos)
Ä
LCD_BSTCR_VLCDCFG_5_2V (0xeU << LCD_BSTCR_VLCDCFG_Pos)
Å
LCD_BSTCR_VLCDCFG_5_4V (0xfU << LCD_BSTCR_VLCDCFG_Pos)
Ç
LCD_BSTCR_BOOST_TEN_Pos 1
È
LCD_BSTCR_BOOST_TEN_Msk (0x1U << LCD_BSTCR_BOOST_TEN_Pos)
Ê
LCD_BSTCR_BOOST_EN_Pos 0
Ë
LCD_BSTCR_BOOST_EN_Msk (0x1U << LCD_BSTCR_BOOST_EN_Pos)
Í
LCD_COM_EN_COMEN_Pos 0
Î
LCD_COM_EN_COMEN_Msk (0xfU << LCD_COM_EN_COMEN_Pos)
Ð
LCD_SEG_EN0_SEGENx_Pos 0
Ñ
LCD_SEG_EN0_SEGENx_Msk (0xffffffffU << LCD_SEG_EN0_SEGENx_Pos)
Ó
LCD_SEG_EN1_SEGENx_Pos 0
Ô
LCD_SEG_EN1_SEGENx_Msk (0xfffU << LCD_SEG_EN1_SEGENx_Pos)
Ö
LCD_COM_EN_COMEN3_Pos 3
×
LCD_COM_EN_COMEN3_Msk (0x1U << LCD_COM_EN_COMEN3_Pos)
Ù
LCD_COM_EN_COMEN2_Pos 2
Ú
LCD_COM_EN_COMEN2_Msk (0x1U << LCD_COM_EN_COMEN2_Pos)
Ü
LCD_COM_EN_COMEN1_Pos 1
Ý
LCD_COM_EN_COMEN1_Msk (0x1U << LCD_COM_EN_COMEN1_Pos)
ß
LCD_COM_EN_COMEN0_Pos 0
à
LCD_COM_EN_COMEN0_Msk (0x1U << LCD_COM_EN_COMEN0_Pos)
â
LCD_SEG_EN0_SEGEN31_Pos 31
ã
LCD_SEG_EN0_SEGEN31_Msk (0x1U << LCD_SEG_EN0_SEGEN31_Pos)
å
LCD_SEG_EN0_SEGEN30_Pos 30
æ
LCD_SEG_EN0_SEGEN30_Msk (0x1U << LCD_SEG_EN0_SEGEN30_Pos)
è
LCD_SEG_EN0_SEGEN29_Pos 29
é
LCD_SEG_EN0_SEGEN29_Msk (0x1U << LCD_SEG_EN0_SEGEN29_Pos)
ë
LCD_SEG_EN0_SEGEN28_Pos 28
ì
LCD_SEG_EN0_SEGEN28_Msk (0x1U << LCD_SEG_EN0_SEGEN28_Pos)
î
LCD_SEG_EN0_SEGEN27_Pos 27
ï
LCD_SEG_EN0_SEGEN27_Msk (0x1U << LCD_SEG_EN0_SEGEN27_Pos)
ñ
LCD_SEG_EN0_SEGEN26_Pos 26
ò
LCD_SEG_EN0_SEGEN26_Msk (0x1U << LCD_SEG_EN0_SEGEN26_Pos)
ô
LCD_SEG_EN0_SEGEN25_Pos 25
õ
LCD_SEG_EN0_SEGEN25_Msk (0x1U << LCD_SEG_EN0_SEGEN25_Pos)
÷
LCD_SEG_EN0_SEGEN24_Pos 24
ø
LCD_SEG_EN0_SEGEN24_Msk (0x1U << LCD_SEG_EN0_SEGEN24_Pos)
ú
LCD_SEG_EN0_SEGEN23_Pos 23
û
LCD_SEG_EN0_SEGEN23_Msk (0x1U << LCD_SEG_EN0_SEGEN23_Pos)
ý
LCD_SEG_EN0_SEGEN22_Pos 22
þ
LCD_SEG_EN0_SEGEN22_Msk (0x1U << LCD_SEG_EN0_SEGEN22_Pos)
€LCD_SEG_EN0_SEGEN21_Pos 21
LCD_SEG_EN0_SEGEN21_Msk (0x1U << LCD_SEG_EN0_SEGEN21_Pos)
ƒLCD_SEG_EN0_SEGEN20_Pos 20
„LCD_SEG_EN0_SEGEN20_Msk (0x1U << LCD_SEG_EN0_SEGEN20_Pos)
†LCD_SEG_EN0_SEGEN19_Pos 19
‡LCD_SEG_EN0_SEGEN19_Msk (0x1U << LCD_SEG_EN0_SEGEN19_Pos)
‰LCD_SEG_EN0_SEGEN18_Pos 18
ŠLCD_SEG_EN0_SEGEN18_Msk (0x1U << LCD_SEG_EN0_SEGEN18_Pos)
ŒLCD_SEG_EN0_SEGEN17_Pos 17
LCD_SEG_EN0_SEGEN17_Msk (0x1U << LCD_SEG_EN0_SEGEN17_Pos)
LCD_SEG_EN0_SEGEN16_Pos 16
LCD_SEG_EN0_SEGEN16_Msk (0x1U << LCD_SEG_EN0_SEGEN16_Pos)
’LCD_SEG_EN0_SEGEN15_Pos 15
“LCD_SEG_EN0_SEGEN15_Msk (0x1U << LCD_SEG_EN0_SEGEN15_Pos)
•LCD_SEG_EN0_SEGEN14_Pos 14
–LCD_SEG_EN0_SEGEN14_Msk (0x1U << LCD_SEG_EN0_SEGEN14_Pos)
˜LCD_SEG_EN0_SEGEN13_Pos 13
™LCD_SEG_EN0_SEGEN13_Msk (0x1U << LCD_SEG_EN0_SEGEN13_Pos)
›LCD_SEG_EN0_SEGEN12_Pos 12
œLCD_SEG_EN0_SEGEN12_Msk (0x1U << LCD_SEG_EN0_SEGEN12_Pos)
žLCD_SEG_EN0_SEGEN11_Pos 11
ŸLCD_SEG_EN0_SEGEN11_Msk (0x1U << LCD_SEG_EN0_SEGEN11_Pos)
¡LCD_SEG_EN0_SEGEN10_Pos 10
¢LCD_SEG_EN0_SEGEN10_Msk (0x1U << LCD_SEG_EN0_SEGEN10_Pos)
¤LCD_SEG_EN0_SEGEN9_Pos 9
¥LCD_SEG_EN0_SEGEN9_Msk (0x1U << LCD_SEG_EN0_SEGEN9_Pos)
§LCD_SEG_EN0_SEGEN8_Pos 8
¨LCD_SEG_EN0_SEGEN8_Msk (0x1U << LCD_SEG_EN0_SEGEN8_Pos)
ªLCD_SEG_EN0_SEGEN7_Pos 7
«LCD_SEG_EN0_SEGEN7_Msk (0x1U << LCD_SEG_EN0_SEGEN7_Pos)
­LCD_SEG_EN0_SEGEN6_Pos 6
®LCD_SEG_EN0_SEGEN6_Msk (0x1U << LCD_SEG_EN0_SEGEN6_Pos)
°LCD_SEG_EN0_SEGEN5_Pos 5
±LCD_SEG_EN0_SEGEN5_Msk (0x1U << LCD_SEG_EN0_SEGEN5_Pos)
³LCD_SEG_EN0_SEGEN4_Pos 4
´LCD_SEG_EN0_SEGEN4_Msk (0x1U << LCD_SEG_EN0_SEGEN4_Pos)
¶LCD_SEG_EN0_SEGEN3_Pos 3
·LCD_SEG_EN0_SEGEN3_Msk (0x1U << LCD_SEG_EN0_SEGEN3_Pos)
¹LCD_SEG_EN0_SEGEN2_Pos 2
ºLCD_SEG_EN0_SEGEN2_Msk (0x1U << LCD_SEG_EN0_SEGEN2_Pos)
¼LCD_SEG_EN0_SEGEN1_Pos 1
½LCD_SEG_EN0_SEGEN1_Msk (0x1U << LCD_SEG_EN0_SEGEN1_Pos)
¿LCD_SEG_EN0_SEGEN0_Pos 0
ÀLCD_SEG_EN0_SEGEN0_Msk (0x1U << LCD_SEG_EN0_SEGEN0_Pos)
ÂLCD_SEG_EN1_SEGEN43_Pos 11
ÃLCD_SEG_EN1_SEGEN43_Msk (0x1U << LCD_SEG_EN1_SEGEN43_Pos)
ÅLCD_SEG_EN1_SEGEN42_Pos 10
ÆLCD_SEG_EN1_SEGEN42_Msk (0x1U << LCD_SEG_EN1_SEGEN42_Pos)
ÈLCD_SEG_EN1_SEGEN41_Pos 9
ÉLCD_SEG_EN1_SEGEN41_Msk (0x1U << LCD_SEG_EN1_SEGEN41_Pos)
ËLCD_SEG_EN1_SEGEN40_Pos 8
ÌLCD_SEG_EN1_SEGEN40_Msk (0x1U << LCD_SEG_EN1_SEGEN40_Pos)
ÎLCD_SEG_EN1_SEGEN39_Pos 7
ÏLCD_SEG_EN1_SEGEN39_Msk (0x1U << LCD_SEG_EN1_SEGEN39_Pos)
ÑLCD_SEG_EN1_SEGEN38_Pos 6
ÒLCD_SEG_EN1_SEGEN38_Msk (0x1U << LCD_SEG_EN1_SEGEN38_Pos)
ÔLCD_SEG_EN1_SEGEN37_Pos 5
ÕLCD_SEG_EN1_SEGEN37_Msk (0x1U << LCD_SEG_EN1_SEGEN37_Pos)
×LCD_SEG_EN1_SEGEN36_Pos 4
ØLCD_SEG_EN1_SEGEN36_Msk (0x1U << LCD_SEG_EN1_SEGEN36_Pos)
ÚLCD_SEG_EN1_SEGEN35_Pos 3
ÛLCD_SEG_EN1_SEGEN35_Msk (0x1U << LCD_SEG_EN1_SEGEN35_Pos)
ÝLCD_SEG_EN1_SEGEN34_Pos 2
ÞLCD_SEG_EN1_SEGEN34_Msk (0x1U << LCD_SEG_EN1_SEGEN34_Pos)
àLCD_SEG_EN1_SEGEN33_Pos 1
áLCD_SEG_EN1_SEGEN33_Msk (0x1U << LCD_SEG_EN1_SEGEN33_Pos)
ãLCD_SEG_EN1_SEGEN32_Pos 0
äLCD_SEG_EN1_SEGEN32_Msk (0x1U << LCD_SEG_EN1_SEGEN32_Pos)
æLCD_SEG_EN1_COMEN7_Pos 11
çLCD_SEG_EN1_COMEN7_Msk (0x1U << LCD_SEG_EN1_COMEN7_Pos)
éLCD_SEG_EN1_COMEN6_Pos 10
êLCD_SEG_EN1_COMEN6_Msk (0x1U << LCD_SEG_EN1_COMEN6_Pos)
ìLCD_SEG_EN1_COMEN5_Pos 9
íLCD_SEG_EN1_COMEN5_Msk (0x1U << LCD_SEG_EN1_COMEN5_Pos)
ïLCD_SEG_EN1_COMEN4_Pos 8
ðLCD_SEG_EN1_COMEN4_Msk (0x1U << LCD_SEG_EN1_COMEN4_Pos)`T
 




..\Drivers\..\Core\Include\fm33a0xxev_lcd.h
FM33A0XXEV.h

¼
..\Drivers\fm33a0xxev_lcd.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM
±
²
³


__FM33A0XXEV_DMA_H 
2DMA_GCR_DMA_ADDRERR_EN_Pos 1
5DMA_GCR_DMA_ADDRERR_EN_Msk (0x1U << DMA_GCR_DMA_ADDRERR_EN_Pos)
7DMA_GCR_DMAEN_Pos 0
:DMA_GCR_DMAEN_Msk (0x1U << DMA_GCR_DMAEN_Pos)
<DMA_CHxCR_CHxTSIZE_Pos 16
=DMA_CHxCR_CHxTSIZE_Msk (0x1fffU << DMA_CHxCR_CHxTSIZE_Pos)
?DMA_CHxCR_CHxPRI_Pos 12
DDMA_CHxCR_CHxPRI_Msk (0x3U << DMA_CHxCR_CHxPRI_Pos)
EDMA_CHxCR_CHxPRI_LOW (0x0U << DMA_CHxCR_CHxPRI_Pos)
FDMA_CHxCR_CHxPRI_MEDIUM (0x1U << DMA_CHxCR_CHxPRI_Pos)
GDMA_CHxCR_CHxPRI_HIGH (0x2U << DMA_CHxCR_CHxPRI_Pos)
HDMA_CHxCR_CHxPRI_VERY_HIGH (0x3U << DMA_CHxCR_CHxPRI_Pos)
JDMA_CHxCR_CHxINC_Pos 11
MDMA_CHxCR_CHxINC_Msk (0x1U << DMA_CHxCR_CHxINC_Pos)
NDMA_CHxCR_CHxINC_INCREASE (0x1U << DMA_CHxCR_CHxINC_Pos)
ODMA_CHxCR_CHxINC_DECREASE (0x0U << DMA_CHxCR_CHxINC_Pos)
QDMA_CHxCR_CHxSSEL_Pos 8
SDMA_CHxCR_CHxSSEL_Msk (0x7U << DMA_CHxCR_CHxSSEL_Pos)
UDMA_CHxCR_CH0SSEL_ADC (0x0U << DMA_CHxCR_CHxSSEL_Pos)
VDMA_CHxCR_CH0SSEL_SPI3_RX (0x1U << DMA_CHxCR_CHxSSEL_Pos)
WDMA_CHxCR_CH0SSEL_LPUART0_RX (0x2U << DMA_CHxCR_CHxSSEL_Pos)
XDMA_CHxCR_CH0SSEL_LPUART1_RX (0x3U << DMA_CHxCR_CHxSSEL_Pos)
YDMA_CHxCR_CH0SSEL_UART2_RX (0x4U << DMA_CHxCR_CHxSSEL_Pos)
ZDMA_CHxCR_CH0SSEL_UART4_RX (0x5U << DMA_CHxCR_CHxSSEL_Pos)
[DMA_CHxCR_CH0SSEL_AES_IN (0x6U << DMA_CHxCR_CHxSSEL_Pos)
\DMA_CHxCR_CH0SSEL_QSPI (0x7U << DMA_CHxCR_CHxSSEL_Pos)
^DMA_CHxCR_CH1SSEL_ADC (0x0U << DMA_CHxCR_CHxSSEL_Pos)
_DMA_CHxCR_CH1SSEL_SPI0_RX (0x1U << DMA_CHxCR_CHxSSEL_Pos)
`DMA_CHxCR_CH1SSEL_SPI2_RX (0x2U << DMA_CHxCR_CHxSSEL_Pos)
aDMA_CHxCR_CH1SSEL_SPI3_TX (0x3U << DMA_CHxCR_CHxSSEL_Pos)
bDMA_CHxCR_CH1SSEL_UART0_RX (0x4U << DMA_CHxCR_CHxSSEL_Pos)
cDMA_CHxCR_CH1SSEL_UART2_TX (0x5U << DMA_CHxCR_CHxSSEL_Pos)
dDMA_CHxCR_CH1SSEL_UART3_RX (0x6U << DMA_CHxCR_CHxSSEL_Pos)
eDMA_CHxCR_CH1SSEL_U7816_RX (0x7U << DMA_CHxCR_CHxSSEL_Pos)
gDMA_CHxCR_CH2SSEL_SPI0_TX (0x0U << DMA_CHxCR_CHxSSEL_Pos)
hDMA_CHxCR_CH2SSEL_SPI2_TX (0x1U << DMA_CHxCR_CHxSSEL_Pos)
iDMA_CHxCR_CH2SSEL_SPI4_RX (0x2U << DMA_CHxCR_CHxSSEL_Pos)
jDMA_CHxCR_CH2SSEL_UART0_TX (0x3U << DMA_CHxCR_CHxSSEL_Pos)
kDMA_CHxCR_CH2SSEL_UART3_TX (0x4U << DMA_CHxCR_CHxSSEL_Pos)
lDMA_CHxCR_CH2SSEL_UART5_RX (0x5U << DMA_CHxCR_CHxSSEL_Pos)
mDMA_CHxCR_CH2SSEL_U7816_TX (0x6U << DMA_CHxCR_CHxSSEL_Pos)
nDMA_CHxCR_CH2SSEL_AES_OUT (0x7U << DMA_CHxCR_CHxSSEL_Pos)
pDMA_CHxCR_CH3SSEL_SPI1_RX (0x0U << DMA_CHxCR_CHxSSEL_Pos)
qDMA_CHxCR_CH3SSEL_SPI4_TX (0x1U << DMA_CHxCR_CHxSSEL_Pos)
rDMA_CHxCR_CH3SSEL_LPUART0_RX (0x2U << DMA_CHxCR_CHxSSEL_Pos)
sDMA_CHxCR_CH3SSEL_UART1_RX (0x3U << DMA_CHxCR_CHxSSEL_Pos)
tDMA_CHxCR_CH3SSEL_UART4_RX (0x4U << DMA_CHxCR_CHxSSEL_Pos)
uDMA_CHxCR_CH3SSEL_UART5_TX (0x5U << DMA_CHxCR_CHxSSEL_Pos)
vDMA_CHxCR_CH3SSEL_I2C0_TX (0x6U << DMA_CHxCR_CHxSSEL_Pos)
wDMA_CHxCR_CH3SSEL_AES_IN (0x7U << DMA_CHxCR_CHxSSEL_Pos)
yDMA_CHxCR_CH4SSEL_SPI1_TX (0x0U << DMA_CHxCR_CHxSSEL_Pos)
zDMA_CHxCR_CH4SSEL_SPI3_RX (0x1U << DMA_CHxCR_CHxSSEL_Pos)
{DMA_CHxCR_CH4SSEL_LPUART0_TX (0x2U << DMA_CHxCR_CHxSSEL_Pos)
|DMA_CHxCR_CH4SSEL_UART1_TX (0x3U << DMA_CHxCR_CHxSSEL_Pos)
}DMA_CHxCR_CH4SSEL_UART2_RX (0x4U << DMA_CHxCR_CHxSSEL_Pos)
~DMA_CHxCR_CH4SSEL_UART4_TX (0x5U << DMA_CHxCR_CHxSSEL_Pos)
DMA_CHxCR_CH4SSEL_I2C0_RX (0x6U << DMA_CHxCR_CHxSSEL_Pos)
€
DMA_CHxCR_CH4SSEL_AES_OUT (0x7U << DMA_CHxCR_CHxSSEL_Pos)
‚
DMA_CHxCR_CH5SSEL_SPI0_RX (0x0U << DMA_CHxCR_CHxSSEL_Pos)
ƒ
DMA_CHxCR_CH5SSEL_SPI2_RX (0x1U << DMA_CHxCR_CHxSSEL_Pos)
„
DMA_CHxCR_CH5SSEL_LPUART1_RX (0x2U << DMA_CHxCR_CHxSSEL_Pos)
…
DMA_CHxCR_CH5SSEL_UART1_RX (0x3U << DMA_CHxCR_CHxSSEL_Pos)
†
DMA_CHxCR_CH5SSEL_UART2_TX (0x4U << DMA_CHxCR_CHxSSEL_Pos)
‡
DMA_CHxCR_CH5SSEL_UART3_RX (0x5U << DMA_CHxCR_CHxSSEL_Pos)
ˆ
DMA_CHxCR_CH5SSEL_UART5_RX (0x6U << DMA_CHxCR_CHxSSEL_Pos)
‰
DMA_CHxCR_CH5SSEL_I2C1_TX (0x7U << DMA_CHxCR_CHxSSEL_Pos)
‹
DMA_CHxCR_CH6SSEL_SPI0_TX (0x0U << DMA_CHxCR_CHxSSEL_Pos)
Œ
DMA_CHxCR_CH6SSEL_SPI2_TX (0x1U << DMA_CHxCR_CHxSSEL_Pos)

DMA_CHxCR_CH6SSEL_LPUART1_TX (0x2U << DMA_CHxCR_CHxSSEL_Pos)
Ž
DMA_CHxCR_CH6SSEL_UART1_TX (0x3U << DMA_CHxCR_CHxSSEL_Pos)

DMA_CHxCR_CH6SSEL_UART3_TX (0x4U << DMA_CHxCR_CHxSSEL_Pos)

DMA_CHxCR_CH6SSEL_UART5_TX (0x5U << DMA_CHxCR_CHxSSEL_Pos)
‘
DMA_CHxCR_CH6SSEL_I2C1_RX (0x6U << DMA_CHxCR_CHxSSEL_Pos)
’
DMA_CHxCR_CH6SSEL_CRC (0x7U << DMA_CHxCR_CHxSSEL_Pos)
”
DMA_CHxCR_CH7SSEL_ADC (0x0U << DMA_CHxCR_CHxSSEL_Pos)
•
DMA_CHxCR_CH7SSEL_SPI1_RX (0x1U << DMA_CHxCR_CHxSSEL_Pos)
–
DMA_CHxCR_CH7SSEL_SPI3_RX (0x2U << DMA_CHxCR_CHxSSEL_Pos)
—
DMA_CHxCR_CH7SSEL_LPUART0_RX (0x3U << DMA_CHxCR_CHxSSEL_Pos)
˜
DMA_CHxCR_CH7SSEL_UART0_RX (0x4U << DMA_CHxCR_CHxSSEL_Pos)
™
DMA_CHxCR_CH7SSEL_UART2_RX (0x5U << DMA_CHxCR_CHxSSEL_Pos)
š
DMA_CHxCR_CH7SSEL_UART4_RX (0x6U << DMA_CHxCR_CHxSSEL_Pos)
›
DMA_CHxCR_CH7SSEL_QSPI (0x7U << DMA_CHxCR_CHxSSEL_Pos)

DMA_CHxCR_CH8SSEL_ADC (0x0U << DMA_CHxCR_CHxSSEL_Pos)
ž
DMA_CHxCR_CH8SSEL_SPI1_TX (0x1U << DMA_CHxCR_CHxSSEL_Pos)
Ÿ
DMA_CHxCR_CH8SSEL_SPI2_RX (0x2U << DMA_CHxCR_CHxSSEL_Pos)
 
DMA_CHxCR_CH8SSEL_SPI3_TX (0x3U << DMA_CHxCR_CHxSSEL_Pos)
¡
DMA_CHxCR_CH8SSEL_LPUART0_TX (0x4U << DMA_CHxCR_CHxSSEL_Pos)
¢
DMA_CHxCR_CH8SSEL_UART0_TX (0x5U << DMA_CHxCR_CHxSSEL_Pos)
£
DMA_CHxCR_CH8SSEL_UART2_TX (0x6U << DMA_CHxCR_CHxSSEL_Pos)
¤
DMA_CHxCR_CH8SSEL_UART4_TX (0x7U << DMA_CHxCR_CHxSSEL_Pos)
¦
DMA_CHxCR_CH9SSEL_SPI0_RX (0x0U << DMA_CHxCR_CHxSSEL_Pos)
§
DMA_CHxCR_CH9SSEL_SPI2_TX (0x1U << DMA_CHxCR_CHxSSEL_Pos)
¨
DMA_CHxCR_CH9SSEL_SPI4_RX (0x2U << DMA_CHxCR_CHxSSEL_Pos)
©
DMA_CHxCR_CH9SSEL_LPUART1_RX (0x3U << DMA_CHxCR_CHxSSEL_Pos)
ª
DMA_CHxCR_CH9SSEL_UART1_RX (0x4U << DMA_CHxCR_CHxSSEL_Pos)
«
DMA_CHxCR_CH9SSEL_UART3_RX (0x5U << DMA_CHxCR_CHxSSEL_Pos)
¬
DMA_CHxCR_CH9SSEL_UART5_RX (0x6U << DMA_CHxCR_CHxSSEL_Pos)
­
DMA_CHxCR_CH9SSEL_I2C0_TX (0x7U << DMA_CHxCR_CHxSSEL_Pos)
¯
DMA_CHxCR_CH10SSEL_SPI0_TX (0x0U << DMA_CHxCR_CHxSSEL_Pos)
°
DMA_CHxCR_CH10SSEL_SPI4_TX (0x1U << DMA_CHxCR_CHxSSEL_Pos)
±
DMA_CHxCR_CH10SSEL_LPUART1_TX (0x2U << DMA_CHxCR_CHxSSEL_Pos)
²
DMA_CHxCR_CH10SSEL_UART1_TX (0x3U << DMA_CHxCR_CHxSSEL_Pos)
³
DMA_CHxCR_CH10SSEL_UART3_TX (0x4U << DMA_CHxCR_CHxSSEL_Pos)
´
DMA_CHxCR_CH10SSEL_UART5_TX (0x5U << DMA_CHxCR_CHxSSEL_Pos)
µ
DMA_CHxCR_CH10SSEL_I2C0_RX (0x6U << DMA_CHxCR_CHxSSEL_Pos)
¶
DMA_CHxCR_CH10SSEL_CRC (0x7U << DMA_CHxCR_CHxSSEL_Pos)
¸
DMA_CHxCR_CIRC_UPD_Pos 7
¼
DMA_CHxCR_CIRC_UPD_Msk (0x1U << DMA_CHxCR_CIRC_UPD_Pos)
Á
DMA_CHxCR_DIR_Pos 6
Ä
DMA_CHxCR_DIR_Msk (0x1U << DMA_CHxCR_DIR_Pos)
Å
DMA_CHxCR_DIR_TO_RAM (0x0U << DMA_CHxCR_DIR_Pos)
Æ
DMA_CHxCR_DIR_TO_PER (0x1U << DMA_CHxCR_DIR_Pos)
È
DMA_CHxCR_BDW_Pos 4
Í
DMA_CHxCR_BDW_Msk (0x3U << DMA_CHxCR_BDW_Pos)
Î
DMA_CHxCR_BDW_8BITS (0x0U << DMA_CHxCR_BDW_Pos)
Ï
DMA_CHxCR_BDW_16BITS (0x1U << DMA_CHxCR_BDW_Pos)
Ð
DMA_CHxCR_BDW_32BITS (0x2U << DMA_CHxCR_BDW_Pos)
Ò
DMA_CHxCR_CIRC_Pos 3
Õ
DMA_CHxCR_CIRC_Msk (0x1U << DMA_CHxCR_CIRC_Pos)
Ù
DMA_CHxCR_CHxFTIE_Pos 2
Ü
DMA_CHxCR_CHxFTIE_Msk (0x1U << DMA_CHxCR_CHxFTIE_Pos)
à
DMA_CHxCR_CHxHTIE_Pos 1
ã
DMA_CHxCR_CHxHTIE_Msk (0x1U << DMA_CHxCR_CHxHTIE_Pos)
ç
DMA_CHxCR_ChxEN_Pos 0
ê
DMA_CHxCR_ChxEN_Msk (0x1U << DMA_CHxCR_ChxEN_Pos)
î
DMA_CHxMAR_CHxMEMAD_Pos 0
ô
DMA_CHxMAR_CHxMEMAD_Msk (0xffffffffU << DMA_CHxMAR_CHxMEMAD_Pos)
ö
DMA_CH11CR_CH11TSIZE_Pos 16
÷
DMA_CH11CR_CH11TSIZE_Msk (0x1fffU << DMA_CH11CR_CH11TSIZE_Pos)
ù
DMA_CH11CR_CH11PRI_Pos 12
þ
DMA_CH11CR_CH11PRI_Msk (0x3U << DMA_CH11CR_CH11PRI_Pos)
ÿ
DMA_CH11CR_CH11PRI_LOW (0x0U << DMA_CH11CR_CH11PRI_Pos)
€DMA_CH11CR_CH11PRI_MEDIUM (0x1U << DMA_CH11CR_CH11PRI_Pos)
DMA_CH11CR_CH11PRI_HIGH (0x2U << DMA_CH11CR_CH11PRI_Pos)
‚DMA_CH11CR_CH11PRI_VERY_HIGH (0x3U << DMA_CH11CR_CH11PRI_Pos)
„DMA_CH11CR_CH11DIR_Pos 10
‡DMA_CH11CR_CH11DIR_Msk (0x1U << DMA_CH11CR_CH11DIR_Pos)
ˆDMA_CH11CR_CH11DIR_TO_RAM (0x1U << DMA_CH11CR_CH11DIR_Pos)
‰DMA_CH11CR_CH11DIR_TO_FLASH (0x0U << DMA_CH11CR_CH11DIR_Pos)
‹DMA_CH11CR_CH11RI_Pos 9
ŽDMA_CH11CR_CH11RI_Msk (0x1U << DMA_CH11CR_CH11RI_Pos)
DMA_CH11CR_CH11RI_INCREASE (0x1U << DMA_CH11CR_CH11RI_Pos)
DMA_CH11CR_CH11RI_DECREASE (0x0U << DMA_CH11CR_CH11RI_Pos)
’DMA_CH11CR_CH11FI_Pos 8
•DMA_CH11CR_CH11FI_Msk (0x1U << DMA_CH11CR_CH11FI_Pos)
–DMA_CH11CR_CH11FI_INCREASE (0x1U << DMA_CH11CR_CH11FI_Pos)
—DMA_CH11CR_CH11FI_DECREASE (0x0U << DMA_CH11CR_CH11FI_Pos)
™DMA_CH11CR_CH11FTIE_Pos 2
œDMA_CH11CR_CH11FTIE_Msk (0x1U << DMA_CH11CR_CH11FTIE_Pos)
 DMA_CH11CR_CH11HTIE_Pos 1
£DMA_CH11CR_CH11HTIE_Msk (0x1U << DMA_CH11CR_CH11HTIE_Pos)
§DMA_CH11CR_CH11EN_Pos 0
ªDMA_CH11CR_CH11EN_Msk (0x1U << DMA_CH11CR_CH11EN_Pos)
®DMA_CH11FAR_CH11FLSAD_Pos 0
±DMA_CH11FAR_CH11FLSAD_Msk (0x7fffU << DMA_CH11FAR_CH11FLSAD_Pos)
³DMA_CH11RAR_CH7RAMAD_Pos 0
µDMA_CH11RAR_CH7RAMAD_Msk (0x7fffU << DMA_CH11RAR_CH7RAMAD_Pos)
·DMA_ISR_DMA_ADDRERR_Pos 28
¸DMA_ISR_DMA_ADDRERR_Msk (0x1U << DMA_ISR_DMA_ADDRERR_Pos)
ºDMA_ISR_DMACHFT_Pos 16
½DMA_ISR_DMACHFT_Msk (0xfffU << DMA_ISR_DMACHFT_Pos)
¿DMA_ISR_DMACHHT_Pos 0
ÀDMA_ISR_DMACHHT_Msk (0xfffU << DMA_ISR_DMACHHT_Pos)
ÂDMA_CHxCSR_CHxTSIZE_SDW_Pos 16
ÃDMA_CHxCSR_CHxTSIZE_SDW_Msk (0x1fffU << DMA_CHxCSR_CHxTSIZE_SDW_Pos)
ÅDMA_CHxCSR_CHxINC_SDW_Pos 11
ÆDMA_CHxCSR_CHxINC_SDW_Msk (0x1U << DMA_CHxCSR_CHxINC_SDW_Pos)
ÈDMA_CHxMASR_CHxMAD_SDW_Pos 0
ÊDMA_CHxMASR_CHxMAD_SDW_Msk (0xffffffffU << DMA_CHxMASR_CHxMAD_SDW_Pos)`T
 




..\Drivers\..\Core\Include\fm33a0xxev_dma.h
FM33A0XXEV.h

l
..\Drivers\fm33a0xxev_dma.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMÈ
DMA_CH0DMA_CH1
DMA_CH2DMA_CH3DMA_CH4DMA_CH5DMA_CH6DMA_CH7DMA_CH8DMA_CH9    DMA_CH10
DMA_CH11PDMA_CH_Type½
*Õ0CHxH
#CHxTSIZEf
#CHxPRIf
#CHxINCf
#CHxSSELf
#CHxDIRf
#CHxBDWf
#CHxCICR
#CHxFTIE
#CHxHTIE
#CHxEN
#CHxRAMADf
# CH11RIf
#$CH11FIf
#(CH11FLSADf
#,PDMA_InitTypeDef[

0
µ
¶
·


__FM33A0XXEV_GPIO_H 
cIS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
lIS_GPIO_INTERRUPT_TRIGER_EDGE(EDGE) (((EDGE) == EXTI_RISING) || ((EDGE) == EXTI_FALLING)|| ((EDGE) == EXTI_BOTH)|| ((EDGE) == EXTIDISABLE))
}IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || ((PERIPH) == GPIOB) || ((PERIPH) == GPIOC) || ((PERIPH) == GPIOD) || ((PERIPH) == GPIOE) || ((PERIPH) == GPIOF) || ((PERIPH) == GPIOG))
…
IS_GPIO_HD_PERIPH(PERIPH) ((PERIPH) == GPIOH)
‰
GPIO_Pin_0 ((uint32_t)0x00000001)
Š
GPIO_Pin_1 ((uint32_t)0x00000002)
‹
GPIO_Pin_2 ((uint32_t)0x00000004)
Œ
GPIO_Pin_3 ((uint32_t)0x00000008)

GPIO_Pin_4 ((uint32_t)0x00000010)
Ž
GPIO_Pin_5 ((uint32_t)0x00000020)

GPIO_Pin_6 ((uint32_t)0x00000040)

GPIO_Pin_7 ((uint32_t)0x00000080)
‘
GPIO_Pin_8 ((uint32_t)0x00000100)
’
GPIO_Pin_9 ((uint32_t)0x00000200)
“
GPIO_Pin_10 ((uint32_t)0x00000400)
”
GPIO_Pin_11 ((uint32_t)0x00000800)
•
GPIO_Pin_12 ((uint32_t)0x00001000)
–
GPIO_Pin_13 ((uint32_t)0x00002000)
—
GPIO_Pin_14 ((uint32_t)0x00004000)
˜
GPIO_Pin_15 ((uint32_t)0x00008000)
™
GPIO_Pin_All ((uint16_t)0xFFFF)
›
IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00))
œ
IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || ((PIN) == GPIO_Pin_1) || ((PIN) == GPIO_Pin_2) || ((PIN) == GPIO_Pin_3) || ((PIN) == GPIO_Pin_4) || ((PIN) == GPIO_Pin_5) || ((PIN) == GPIO_Pin_6) || ((PIN) == GPIO_Pin_7) || ((PIN) == GPIO_Pin_8) || ((PIN) == GPIO_Pin_9) || ((PIN) == GPIO_Pin_10) || ((PIN) == GPIO_Pin_11) || ((PIN) == GPIO_Pin_12) || ((PIN) == GPIO_Pin_13) || ((PIN) == GPIO_Pin_14) || ((PIN) == GPIO_Pin_15))
¯
IS_GET_GPIOH_PIN(PIN) (((PIN) == GPIO_Pin_0) || ((PIN) == GPIO_Pin_1) || ((PIN) == GPIO_Pin_2) || ((PIN) == GPIO_Pin_3))
·
PINWKEN_PD6 7
¸
PINWKEN_PE9 6
¹
PINWKEN_PE2 5
º
PINWKEN_PA13 4
»
PINWKEN_PG7 3
¼
PINWKEN_PC13 2
½
PINWKEN_PB0 1
¾
PINWKEN_PF5 0
Á
GPIOx_INEN_INEN_Pos 0
Â
GPIOx_INEN_INEN_Msk (0xffffU << GPIOx_INEN_INEN_Pos)
È
GPIOx_PUEN_PUEN_Pos 0
É
GPIOx_PUEN_PUEN_Msk (0xffffU << GPIOx_PUEN_PUEN_Pos)
Ï
GPIOx_ODEN_ODEN_Pos 0
Ð
GPIOx_ODEN_ODEN_Msk (0xffffU << GPIOx_ODEN_ODEN_Pos)
Ö
GPIOx_FCR_Px15FCR_Pos 30
×
GPIOx_FCR_Px15FCR_Msk (0x03U << GPIOx_FCR_Px15FCR_Pos)
Ý
GPIOx_FCR_Px14FCR_Pos 28
Þ
GPIOx_FCR_Px14FCR_Msk (0x03U << GPIOx_FCR_Px14FCR_Pos)
ä
GPIOx_FCR_Px13FCR_Pos 26
å
GPIOx_FCR_Px13FCR_Msk (0x03U << GPIOx_FCR_Px13FCR_Pos)
ë
GPIOx_FCR_Px12FCR_Pos 24
ì
GPIOx_FCR_Px12FCR_Msk (0x03U << GPIOx_FCR_Px12FCR_Pos)
ò
GPIOx_FCR_Px11FCR_Pos 22
ó
GPIOx_FCR_Px11FCR_Msk (0x03U << GPIOx_FCR_Px11FCR_Pos)
ù
GPIOx_FCR_Px10FCR_Pos 20
ú
GPIOx_FCR_Px10FCR_Msk (0x03U << GPIOx_FCR_Px10FCR_Pos)
€GPIOx_FCR_Px9FCR_Pos 18
GPIOx_FCR_Px9FCR_Msk (0x03U << GPIOx_FCR_Px9FCR_Pos)
‡GPIOx_FCR_Px8FCR_Pos 16
ˆGPIOx_FCR_Px8FCR_Msk (0x03U << GPIOx_FCR_Px8FCR_Pos)
ŽGPIOx_FCR_Px7FCR_Pos 14
GPIOx_FCR_Px7FCR_Msk (0x03U << GPIOx_FCR_Px7FCR_Pos)
•GPIOx_FCR_Px6FCR_Pos 12
–GPIOx_FCR_Px6FCR_Msk (0x03U << GPIOx_FCR_Px6FCR_Pos)
œGPIOx_FCR_Px5FCR_Pos 10
GPIOx_FCR_Px5FCR_Msk (0x03U << GPIOx_FCR_Px5FCR_Pos)
£GPIOx_FCR_Px4FCR_Pos 8
¤GPIOx_FCR_Px4FCR_Msk (0x03U << GPIOx_FCR_Px4FCR_Pos)
ªGPIOx_FCR_Px3FCR_Pos 6
«GPIOx_FCR_Px3FCR_Msk (0x03U << GPIOx_FCR_Px3FCR_Pos)
±GPIOx_FCR_Px2FCR_Pos 4
²GPIOx_FCR_Px2FCR_Msk (0x03U << GPIOx_FCR_Px2FCR_Pos)
¸GPIOx_FCR_Px1FCR_Pos 2
¹GPIOx_FCR_Px1FCR_Msk (0x03U << GPIOx_FCR_Px1FCR_Pos)
¿GPIOx_FCR_Px0FCR_Pos 0
ÀGPIOx_FCR_Px0FCR_Msk (0x03U << GPIOx_FCR_Px0FCR_Pos)
ÈGPIOx_DO_DO_Pos 0
ÉGPIOx_DO_DO_Msk (0xffffU << GPIOx_DO_DO_Pos)
ÍGPIOx_DSET_DSET_Pos 0
ÎGPIOx_DSET_DSET_Msk (0xffffU << GPIOx_DSET_DSET_Pos)
ÔGPIOx_DRST_DRESET_Pos 0
ÕGPIOx_DRST_DRESET_Msk (0xffffU << GPIOx_DRST_DRESET_Pos)
ÛGPIOx_DIN_DIN_Pos 0
ÜGPIOx_DIN_DIN_Msk (0xffffU << GPIOx_DIN_DIN_Pos)
âGPIOx_DFS_DFS_Pos 0
ãGPIOx_DFS_DFS_Msk (0xffffU << GPIOx_DFS_DFS_Pos)
éGPIOx_ANEN_ANEN_Pos 0
êGPIOx_ANEN_ANEN_Msk (0xffffU << GPIOx_ANEN_ANEN_Pos)
öGPIO_FOUTSEL_FOUT1SEL_Pos 8
÷GPIO_FOUTSEL_FOUT1SEL_Msk (0x1fU << GPIO_FOUTSEL_FOUT1SEL_Pos)
øGPIO_FOUTSEL_FOUT1SEL_XTLF (0x0U << GPIO_FOUTSEL_FOUT1SEL_Pos)
ùGPIO_FOUTSEL_FOUT1SEL_RCLP (0x1U << GPIO_FOUTSEL_FOUT1SEL_Pos)
úGPIO_FOUTSEL_FOUT1SEL_RCHFD64 (0x2U << GPIO_FOUTSEL_FOUT1SEL_Pos)
ûGPIO_FOUTSEL_FOUT1SEL_LSCLK (0x3U << GPIO_FOUTSEL_FOUT1SEL_Pos)
üGPIO_FOUTSEL_FOUT1SEL_AHBCLKD64 (0x4U << GPIO_FOUTSEL_FOUT1SEL_Pos)
ýGPIO_FOUTSEL_FOUT1SEL_RTC_TM (0x5U << GPIO_FOUTSEL_FOUT1SEL_Pos)
þGPIO_FOUTSEL_FOUT1SEL_PLLHD64 (0x6U << GPIO_FOUTSEL_FOUT1SEL_Pos)
ÿGPIO_FOUTSEL_FOUT1SEL_RTCCLK64Hz (0x7U << GPIO_FOUTSEL_FOUT1SEL_Pos)
€GPIO_FOUTSEL_FOUT1SEL_APBCLKD64 (0x8U << GPIO_FOUTSEL_FOUT1SEL_Pos)
GPIO_FOUTSEL_FOUT1SEL_PLL_L (0x9U << GPIO_FOUTSEL_FOUT1SEL_Pos)
‚GPIO_FOUTSEL_FOUT1SEL_RCMF (0xAU << GPIO_FOUTSEL_FOUT1SEL_Pos)
ƒGPIO_FOUTSEL_FOUT1SEL_RCHF (0xBU << GPIO_FOUTSEL_FOUT1SEL_Pos)
„GPIO_FOUTSEL_FOUT1SEL_XTHFD64 (0xCU << GPIO_FOUTSEL_FOUT1SEL_Pos)
…GPIO_FOUTSEL_FOUT1SEL_ADCCLK (0xDU << GPIO_FOUTSEL_FOUT1SEL_Pos)
†GPIO_FOUTSEL_FOUT1SEL_PLL_H (0xEU << GPIO_FOUTSEL_FOUT1SEL_Pos)
‡GPIO_FOUTSEL_FOUT1SEL_BOOST_FLAG (0x10U << GPIO_FOUTSEL_FOUT1SEL_Pos)
ˆGPIO_FOUTSEL_FOUT1SEL_AUTOTRIM_OUTPUT (0x11U << GPIO_FOUTSEL_FOUT1SEL_Pos)
‹GPIO_FOUTSEL_FOUT0SEL_Pos 0
ŒGPIO_FOUTSEL_FOUT0SEL_Msk (0x1fU << GPIO_FOUTSEL_FOUT0SEL_Pos)
GPIO_FOUTSEL_FOUT0SEL_XTLF (0x0U << GPIO_FOUTSEL_FOUT0SEL_Pos)
ŽGPIO_FOUTSEL_FOUT0SEL_RCLP (0x1U << GPIO_FOUTSEL_FOUT0SEL_Pos)
GPIO_FOUTSEL_FOUT0SEL_RCHFD64 (0x2U << GPIO_FOUTSEL_FOUT0SEL_Pos)
GPIO_FOUTSEL_FOUT0SEL_LSCLK (0x3U << GPIO_FOUTSEL_FOUT0SEL_Pos)
‘GPIO_FOUTSEL_FOUT0SEL_AHBCLKD64 (0x4U << GPIO_FOUTSEL_FOUT0SEL_Pos)
’GPIO_FOUTSEL_FOUT0SEL_RTC_TM (0x5U << GPIO_FOUTSEL_FOUT0SEL_Pos)
“GPIO_FOUTSEL_FOUT0SEL_PLLHD64 (0x6U << GPIO_FOUTSEL_FOUT0SEL_Pos)
”GPIO_FOUTSEL_FOUT0SEL_RTCCLK64Hz (0x7U << GPIO_FOUTSEL_FOUT0SEL_Pos)
•GPIO_FOUTSEL_FOUT0SEL_APBCLKD64 (0x8U << GPIO_FOUTSEL_FOUT0SEL_Pos)
–GPIO_FOUTSEL_FOUT0SEL_PLL_L (0x9U << GPIO_FOUTSEL_FOUT0SEL_Pos)
—GPIO_FOUTSEL_FOUT0SEL_RCMF (0xAU << GPIO_FOUTSEL_FOUT0SEL_Pos)
˜GPIO_FOUTSEL_FOUT0SEL_RCHF (0xBU << GPIO_FOUTSEL_FOUT0SEL_Pos)
™GPIO_FOUTSEL_FOUT0SEL_XTHFD64 (0xCU << GPIO_FOUTSEL_FOUT0SEL_Pos)
šGPIO_FOUTSEL_FOUT0SEL_ADCCLK (0xDU << GPIO_FOUTSEL_FOUT0SEL_Pos)
›GPIO_FOUTSEL_FOUT0SEL_PLL_H (0xEU << GPIO_FOUTSEL_FOUT0SEL_Pos)
œGPIO_FOUTSEL_FOUT0SEL_BOOST_FLAG (0x10U << GPIO_FOUTSEL_FOUT0SEL_Pos)
žGPIO_IOMCR_IOMUXSEL_Pos 1
ŸGPIO_IOMCR_IOMUXSEL_Msk (0x3U << GPIO_IOMCR_IOMUXSEL_Pos)
 GPIO_IOMCR_IOMUXSEL_PD6 (0x0U << GPIO_IOMCR_IOMUXSEL_Pos)
¡GPIO_IOMCR_IOMUXSEL_PD7 (0x1U << GPIO_IOMCR_IOMUXSEL_Pos)
¢GPIO_IOMCR_IOMUXSEL_PG2 (0x2U << GPIO_IOMCR_IOMUXSEL_Pos)
£GPIO_IOMCR_IOMUXSEL_PG3 (0x3U << GPIO_IOMCR_IOMUXSEL_Pos)
¥GPIO_IOMCR_IOMUXEN_Pos 0
¦GPIO_IOMCR_IOMCUEN_Msk (0x1U << GPIO_IOMCR_IOMUXEN_Pos)
¨GPIO_PINWKEN_WKISEL_Pos 31
©GPIO_PINWKEN_WKISEL_Msk (0x1U << GPIO_PINWKEN_WKISEL_Pos)
ªGPIO_PINWKEN_WKISEL_NMI (0x0U << GPIO_PINWKEN_WKISEL_Pos)
«GPIO_PINWKEN_WKISEL_46 (0x1U << GPIO_PINWKEN_WKISEL_Pos)
­GPIO_PINWKEN_PINWKSEL_Pos 8
®GPIO_PINWKEN_PINWKSEL_Msk (0xffffU << GPIO_PINWKEN_PINWKSEL_Pos)
¯GPIO_PINWKEN_PINWKSEL_FALLING 0
°GPIO_PINWKEN_PINWKSEL_RISING 1
±GPIO_PINWKEN_PINWKSEL_BOTH 2
³GPIO_PINWKEN_PINWKEN_Pos 0
´GPIO_PINWKEN_PINWKEN_Msk (0xffU << GPIO_PINWKEN_PINWKEN_Pos)
¸GPIOH_DO_PHDO_Pos 0
¹GPIOH_DO_PHDO_Msk (0xfU << GPIOH_DO_PHDO_Pos)
¼GPIOH_DIN_PHDIN_Pos 0
½GPIOH_DIN_PHDIN_Msk (0xfU << GPIOH_DIN_PHDIN_Pos)`U
 




..\Drivers\..\Core\Include\fm33a0xxev_gpio.h
FM33A0XXEV.h

$
..\Drivers\fm33a0xxev_gpio.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM‚
GPIO_FCR_INGPIO_FCR_OUT
GPIO_FCR_DIGGPIO_FCR_ANAPGPIO_FCR_TypeDef¾
 ¼
GPIO_OD_DisGPIO_OD_En
PGPIO_ODEN_TypeDef

)÷
GPIO_PU_DisGPIO_PU_En
PGPIO_PUEN_TypeDefU

2²
GPIO_IN_DisGPIO_IN_En
PGPIO_INEN_TypeDef

;í
GPIO_HD_DisGPIO_HD_En
PGPIO_HD_TypeDefË

Dª
GPIO_ANEN_DisGPIO_ANEN_En
PGPIO_ANEN_TypeDef
M*ŒPinf
#PxFCR
#PxODEN<
#PxPUENw
#PxINEN²
#PGPIO_InitTypeDefC
YÁ
Bit_RESETBit_SET
PBitAction¤
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EXTI_RISINGEXTI_FALLING
EXTI_BOTHEXTIDISABLEPGPIOExtiEdgeÒ
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¹
º
»


__FM33A0XXEV_I2C_H 
I2C_SEND_STARTBIT(I2Cx) I2Cx_CR_SEN_Setable(I2Cx,ENABLE)
I2C_SEND_RESTARTBIT(I2Cx) I2Cx_CR_RSEN_Setable(I2Cx,ENABLE)
I2C_SEND_STOPBIT(I2Cx) I2Cx_CR_PEN_Setable(I2Cx,ENABLE)
I2C_SEND_ACK_0(I2Cx) I2Cx_SR_ACKMO_Set(I2Cx,I2Cx_SR_ACKMO_RESET)
I2C_SEND_ACK_1(I2Cx) I2Cx_SR_ACKMO_Set(I2Cx,I2Cx_SR_ACKMO_SET)
!I2Cx_CFGR_AUTOEND_Pos 17
$I2Cx_CFGR_AUTOEND_Msk (0x1U << I2Cx_CFGR_AUTOEND_Pos)
%I2Cx_CFGR_AUTOEND_AUTO (0x1U << I2Cx_CFGR_AUTOEND_Pos)
&I2Cx_CFGR_AUTOEND_MANUAL (0x0U << I2Cx_CFGR_AUTOEND_Pos)
(I2Cx_CFGR_MSP_DMAEN_Pos 16
+I2Cx_CFGR_MSP_DMAEN_Msk (0x1U << I2Cx_CFGR_MSP_DMAEN_Pos)
/I2Cx_CFGR_TOEN_Pos 1
2I2Cx_CFGR_TOEN_Msk (0x1U << I2Cx_CFGR_TOEN_Pos)
3I2Cx_CFGR_TOEN_ENABLE (0x1U << I2Cx_CFGR_TOEN_Pos)
4I2Cx_CFGR_TOEN_DISABLE (0x0U << I2Cx_CFGR_TOEN_Pos)
6I2Cx_CFGR_MSPEN_Pos 0
7I2Cx_CFGR_MSPEN_Msk (0x1U << I2Cx_CFGR_MSPEN_Pos)
9I2Cx_CR_RCEN_Pos 3
<I2Cx_CR_RCEN_Msk (0x1U << I2Cx_CR_RCEN_Pos)
>I2Cx_CR_PEN_Pos 2
?I2Cx_CR_PEN_Msk (0x1U << I2Cx_CR_PEN_Pos)
AI2Cx_CR_RSEN_Pos 1
BI2Cx_CR_RSEN_Msk (0x1U << I2Cx_CR_RSEN_Pos)
DI2Cx_CR_SEN_Pos 0
EI2Cx_CR_SEN_Msk (0x1U << I2Cx_CR_SEN_Pos)
GI2Cx_IER_WCOLE_Pos 6
JI2Cx_IER_WCOLE_Msk (0x1U << I2Cx_IER_WCOLE_Pos)
NI2Cx_IER_TOE_Pos 5
QI2Cx_IER_TOE_Msk (0x1U << I2Cx_IER_TOE_Pos)
SI2Cx_IER_SE_Pos 4
VI2Cx_IER_SE_Msk (0x1U << I2Cx_IER_SE_Pos)
ZI2Cx_IER_PE_Pos 3
]I2Cx_IER_PE_Msk (0x1U << I2Cx_IER_PE_Pos)
aI2Cx_IER_NACKE_Pos 2
dI2Cx_IER_NACKE_Msk (0x1U << I2Cx_IER_NACKE_Pos)
hI2Cx_IER_TXIE_Pos 1
kI2Cx_IER_TXIE_Msk (0x1U << I2Cx_IER_TXIE_Pos)
oI2Cx_IER_RXIE_Pos 0
rI2Cx_IER_RXIE_Msk (0x1U << I2Cx_IER_RXIE_Pos)
vI2Cx_ISR_WCOL_Pos 6
zI2Cx_ISR_WCOL_Msk (0x1U << I2Cx_ISR_WCOL_Pos)
|I2Cx_ISR_TO_Pos 5
}I2Cx_ISR_TO_Msk (0x1U << I2Cx_ISR_TO_Pos)
€
I2Cx_ISR_S_Pos 4
‚
I2Cx_ISR_S_Msk (0x1U << I2Cx_ISR_S_Pos)
„
I2Cx_ISR_P_Pos 3
†
I2Cx_ISR_P_Msk (0x1U << I2Cx_ISR_P_Pos)
ˆ
I2Cx_ISR_ACKSTA_Pos 2
‹
I2Cx_ISR_ACKSTA_Msk (0x1U << I2Cx_ISR_ACKSTA_Pos)

I2Cx_ISR_TXIF_Pos 1
Ž
I2Cx_ISR_TXIF_Msk (0x1U << I2Cx_ISR_TXIF_Pos)

I2Cx_ISR_RXIF_Pos 0
‘
I2Cx_ISR_RXIF_Msk (0x1U << I2Cx_ISR_RXIF_Pos)
“
I2Cx_SR_BUSY_Pos 5
–
I2Cx_SR_BUSY_Msk (0x1U << I2Cx_SR_BUSY_Pos)
˜
I2Cx_SR_RW_Pos 4
›
I2Cx_SR_RW_Msk (0x1U << I2Cx_SR_RW_Pos)

I2Cx_SR_BF_Pos 2
¤
I2Cx_SR_BF_Msk (0x1U << I2Cx_SR_BF_Pos)
¦
I2Cx_SR_ACKMO_Pos 0
¬
I2Cx_SR_ACKMO_Msk (0x1U << I2Cx_SR_ACKMO_Pos)
­
I2Cx_SR_ACKMO_RESET (0x0U << I2Cx_SR_ACKMO_Pos)
®
I2Cx_SR_ACKMO_SET (0x1U << I2Cx_SR_ACKMO_Pos)
°
I2Cx_BRG_MSPBRGH_Pos 16
±
I2Cx_BRG_MSPBRGH_Msk (0x1ffU << I2Cx_BRG_MSPBRGH_Pos)
³
I2Cx_BRG_MSPBRGL_Pos 0
´
I2Cx_BRG_MSPBRGL_Msk (0x1ffU << I2Cx_BRG_MSPBRGL_Pos)
¶
I2Cx_BUF_WR_Pos 0
·
I2Cx_BUF_WR_Msk (0xffU << I2Cx_BUF_WR_Pos)
¹
I2Cx_TIMING_SDAHD_Pos 0
»
I2Cx_TIMING_SDAHD_Msk (0x1ffU << I2Cx_TIMING_SDAHD_Pos)
½
I2Cx_TO_TIMEOUT_Pos 0
¿
I2Cx_TO_TIMEOUT_Msk (0xfffU << I2Cx_TO_TIMEOUT_Pos)`T
 




..\Drivers\..\Core\Include\fm33a0xxev_i2c.h
FM33A0XXEV.h

¼
..\Drivers\fm33a0xxev_i2c.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM
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__FM33A0XXEV_IWDT_H 
IWDT_SERV_IWDTSERV_KEY 0x12345A5AU
IWDT_SERV_IWDTSERV_Pos 0
IWDT_SERV_IWDTSERV_Msk (0xffffffffU << IWDT_SERV_IWDTSERV_Pos)
IWDT_CFGR_IWDTOVP_Pos 0
"IWDT_CFGR_IWDTOVP_Msk (0x7U << IWDT_CFGR_IWDTOVP_Pos)
#IWDT_IWDTOVP_125MS (0x0U << IWDT_CFGR_IWDTOVP_Pos)
$IWDT_IWDTOVP_500MS (0x1U << IWDT_CFGR_IWDTOVP_Pos)
%IWDT_IWDTOVP_2S (0x2U << IWDT_CFGR_IWDTOVP_Pos)
&IWDT_IWDTOVP_8S (0x3U << IWDT_CFGR_IWDTOVP_Pos)
(IWDT_IWDTOVP_4096S (0x4U << IWDT_CFGR_IWDTOVP_Pos)
*IWDT_CNTR_IWDTCNT_Pos 0
+IWDT_CNTR_IWDTCNT_Msk (0xfffffU << IWDT_CNTR_IWDTCNT_Pos)`U
 




..\Drivers\..\Core\Include\fm33a0xxev_iwdt.h
FM33A0XXEV.h

¼
..\Drivers\fm33a0xxev_iwdt.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM
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__FM33A0XXEV_LPUART_H 
LPUARTx_MCTL_FOR9600 (0x00000552<<16)
LPUARTx_MCTL_FOR4800 (0x00001EFB<<16)
LPUARTx_MCTL_FOR2400 (0x000016DB<<16)
LPUARTx_MCTL_FOR1200 (0x00000492<<16)
LPUARTx_MCTL_FOR600 (0x000016D6<<16)
LPUARTx_MCTL_FOR300 (0x00000842<<16)
 LPUARTx_CSR_BUSY_Pos 24
#LPUARTx_CSR_BUSY_Msk (0x1U << LPUARTx_CSR_BUSY_Pos)
%LPUARTx_CSR_WKBYTECFG_Pos 19
(LPUARTx_CSR_WKBYTECFG_Msk (0x1U << LPUARTx_CSR_WKBYTECFG_Pos)
*LPUARTx_CSR_RXEV_Pos 16
0LPUARTx_CSR_RXEV_Msk (0x3U << LPUARTx_CSR_RXEV_Pos)
1LPUARTx_CSR_RXEV_START (0x0U << LPUARTx_CSR_RXEV_Pos)
2LPUARTx_CSR_RXEV_1BYTE (0x1U << LPUARTx_CSR_RXEV_Pos)
3LPUARTx_CSR_RXEV_MATCH (0x2U << LPUARTx_CSR_RXEV_Pos)
4LPUARTx_CSR_RXEV_FALLING (0x3U << LPUARTx_CSR_RXEV_Pos)
6LPUARTx_CSR_IOSWAP_Pos 11
9LPUARTx_CSR_IOSWAP_Msk (0x1U << LPUARTx_CSR_IOSWAP_Pos)
:LPUARTx_CSR_IOSWAP_DEFUALT (0x0U << LPUARTx_CSR_IOSWAP_Pos)
;LPUARTx_CSR_IOSWAP_SWAP (0x1U << LPUARTx_CSR_IOSWAP_Pos)
>LPUARTx_CSR_DMATXIFCFG_Pos 10
ALPUARTx_CSR_DMATXIFCFG_Msk (0x1U << LPUARTx_CSR_DMATXIFCFG_Pos)
ELPUARTx_CSR_BITORD_Pos 9
HLPUARTx_CSR_BITORD_Msk (0x1U << LPUARTx_CSR_BITORD_Pos)
ILPUARTx_CSR_BITORD_LSB (0x0U << LPUARTx_CSR_BITORD_Pos)
JLPUARTx_CSR_BITORD_MSB (0x1U << LPUARTx_CSR_BITORD_Pos)
LLPUARTx_CSR_STOPCFG_Pos 8
OLPUARTx_CSR_STOPCFG_Msk (0x1U << LPUARTx_CSR_STOPCFG_Pos)
PLPUARTx_CSR_STOPCFG_1STOP (0x0U << LPUARTx_CSR_STOPCFG_Pos)
QLPUARTx_CSR_STOPCFG_2STOP (0x1U << LPUARTx_CSR_STOPCFG_Pos)
SLPUARTx_CSR_PDSEL_Pos 6
YLPUARTx_CSR_PDSEL_Msk (0x3U << LPUARTx_CSR_PDSEL_Pos)
ZLPUARTx_CSR_PDSEL_7BITS (0x0U << LPUARTx_CSR_PDSEL_Pos)
[LPUARTx_CSR_PDSEL_8BITS (0x1U << LPUARTx_CSR_PDSEL_Pos)
\LPUARTx_CSR_PDSEL_9BITS (0x2U << LPUARTx_CSR_PDSEL_Pos)
]LPUARTx_CSR_PDSEL_6BITS (0x3U << LPUARTx_CSR_PDSEL_Pos)
_LPUARTx_CSR_PARITY_Pos 4
dLPUARTx_CSR_PARITY_Msk (0x3U << LPUARTx_CSR_PARITY_Pos)
eLPUARTx_CSR_PARITY_NON (0x0U << LPUARTx_CSR_PARITY_Pos)
fLPUARTx_CSR_PARITY_EVEN (0x1U << LPUARTx_CSR_PARITY_Pos)
gLPUARTx_CSR_PARITY_ODD (0x2U << LPUARTx_CSR_PARITY_Pos)
iLPUARTx_CSR_RXPOL_Pos 3
lLPUARTx_CSR_RXPOL_Msk (0x1U << LPUARTx_CSR_RXPOL_Pos)
mLPUARTx_CSR_RXPOL_POS (0x0U << LPUARTx_CSR_RXPOL_Pos)
nLPUARTx_CSR_RXPOL_NEG (0x1U << LPUARTx_CSR_RXPOL_Pos)
pLPUARTx_CSR_TXPOL_Pos 2
sLPUARTx_CSR_TXPOL_Msk (0x1U << LPUARTx_CSR_TXPOL_Pos)
tLPUARTx_CSR_TXPOL_POS (0x0U << LPUARTx_CSR_TXPOL_Pos)
uLPUARTx_CSR_TXPOL_NEG (0x1U << LPUARTx_CSR_TXPOL_Pos)
wLPUARTx_CSR_RXEN_Pos 1
xLPUARTx_CSR_RXEN_Msk (0x1U << LPUARTx_CSR_RXEN_Pos)
zLPUARTx_CSR_TXEN_Pos 0
{LPUARTx_CSR_TXEN_Msk (0x1U << LPUARTx_CSR_TXEN_Pos)
}LPUARTx_IER_RXEV_IE_Pos 12
~LPUARTx_IER_RXEV_IE_Msk (0x1U << LPUARTx_IER_RXEV_IE_Pos)
€
LPUARTx_IER_RXERR_IE_Pos 10

LPUARTx_IER_RXERR_IE_Msk (0x1U << LPUARTx_IER_RXERR_IE_Pos)
ƒ
LPUARTx_IER_RXBF_IE_Pos 8
„
LPUARTx_IER_RXBF_IE_Msk (0x1U << LPUARTx_IER_RXBF_IE_Pos)
†
LPUARTx_IER_TXBE_IE_Pos 1
‡
LPUARTx_IER_TXBE_IE_Msk (0x1U << LPUARTx_IER_TXBE_IE_Pos)
‰
LPUARTx_IER_TXSE_IE_Pos 0
Š
LPUARTx_IER_TXSE_IE_Msk (0x1U << LPUARTx_IER_TXSE_IE_Pos)
Œ
LPUARTx_ISR_RXEVF_Pos 24
Ž
LPUARTx_ISR_RXEVF_Msk (0x1U << LPUARTx_ISR_RXEVF_Pos)

LPUARTx_ISR_TXOV_Pos 19
’
LPUARTx_ISR_TXOV_Msk (0x1U << LPUARTx_ISR_TXOV_Pos)
”
LPUARTx_ISR_PERR_Pos 18
•
LPUARTx_ISR_PERR_Msk (0x1U << LPUARTx_ISR_PERR_Pos)
—
LPUARTx_ISR_FERR_Pos 17
˜
LPUARTx_ISR_FERR_Msk (0x1U << LPUARTx_ISR_FERR_Pos)
š
LPUARTx_ISR_OERR_Pos 16
›
LPUARTx_ISR_OERR_Msk (0x1U << LPUARTx_ISR_OERR_Pos)

LPUARTx_ISR_RXBF_Pos 8
ž
LPUARTx_ISR_RXBF_Msk (0x1U << LPUARTx_ISR_RXBF_Pos)
 
LPUARTx_ISR_TXBE_Pos 1
¡
LPUARTx_ISR_TXBE_Msk (0x1U << LPUARTx_ISR_TXBE_Pos)
£
LPUARTx_ISR_TXSE_Pos 0
¤
LPUARTx_ISR_TXSE_Msk (0x1U << LPUARTx_ISR_TXSE_Pos)
¦
LPUARTx_BMR_MCTL_Pos 16
§
LPUARTx_BMR_MCTL_Msk (0x1fffU << LPUARTx_BMR_MCTL_Pos)
©
LPUARTx_BMR_BAUD_Pos 0
°
LPUARTx_BMR_BAUD_Msk (0x7U << LPUARTx_BMR_BAUD_Pos)
±
LPUARTx_BMR_BAUD_9600 (0x0U << LPUARTx_BMR_BAUD_Pos)
²
LPUARTx_BMR_BAUD_4800 (0x1U << LPUARTx_BMR_BAUD_Pos)
³
LPUARTx_BMR_BAUD_2400 (0x2U << LPUARTx_BMR_BAUD_Pos)
´
LPUARTx_BMR_BAUD_1200 (0x3U << LPUARTx_BMR_BAUD_Pos)
µ
LPUARTx_BMR_BAUD_600 (0x4U << LPUARTx_BMR_BAUD_Pos)
¶
LPUARTx_BMR_BAUD_300 (0x5U << LPUARTx_BMR_BAUD_Pos)
¸
LPUARTx_RXBUF_RXBUF_Pos 0
¹
LPUARTx_RXBUF_RXBUF_Msk (0x1ffU << LPUARTx_RXBUF_RXBUF_Pos)
»
LPUARTx_TXBUF_TXBUF_Pos 0
¼
LPUARTx_TXBUF_TXBUF_Msk (0x1ffU << LPUARTx_TXBUF_TXBUF_Pos)
¾
LPUARTx_DMR_MATD_Pos 0
À
LPUARTx_DMR_MATD_Msk (0x1ffU << LPUARTx_DMR_MATD_Pos)`W
 




..\Drivers\..\Core\Include\fm33a0xxev_lpuart.h
FM33A0XXEV.h

À
..\Drivers\fm33a0xxev_lpuart.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM
Å
Æ
Ç


__FM33A0XXEV_FLASH_H 
FLS_RDCR_WAIT_Pos 0
FLS_RDCR_WAIT_Msk (0x3U << FLS_RDCR_WAIT_Pos)
FLS_RDCR_WAIT_0CYCLE (0x0U << FLS_RDCR_WAIT_Pos)
 FLS_RDCR_WAIT_1CYCLE (0x1U << FLS_RDCR_WAIT_Pos)
!FLS_RDCR_WAIT_2CYCLE (0x2U << FLS_RDCR_WAIT_Pos)
#FLS_PFCR_PRFTEN_Pos 0
&FLS_PFCR_PRFTEN_Msk (0x1U << FLS_PFCR_PRFTEN_Pos)
*FLS_OPTBR_DBGCFGEN_Pos 31
+FLS_OPTBR_DBGCFGEN_Msk (0x1U << FLS_OPTBR_DBGCFGEN_Pos)
-FLS_OPTBR_IF2LOCK_Pos 18
0FLS_OPTBR_IF2LOCK_Msk (0x1U << FLS_OPTBR_IF2LOCK_Pos)
2FLS_OPTBR_IF1LOCK_Pos 17
5FLS_OPTBR_IF1LOCK_Msk (0x1U << FLS_OPTBR_IF1LOCK_Pos)
7FLS_OPTBR_DFLSEN_Pos 10
:FLS_OPTBR_DFLSEN_Msk (0x1U << FLS_OPTBR_DFLSEN_Pos)
>FLS_OPTBR_BTSEN_Pos 8
AFLS_OPTBR_BTSEN_Msk (0x3U << FLS_OPTBR_BTSEN_Pos)
GFLS_OPTBR_ACLOCKEN_Pos 4
JFLS_OPTBR_ACLOCKEN_Msk (0x3U << FLS_OPTBR_ACLOCKEN_Pos)
PFLS_OPTBR_DBRDPEN_Pos 0
SFLS_OPTBR_DBRDPEN_Msk (0xfU << FLS_OPTBR_DBRDPEN_Pos)
YFLS_OPTBR_LOCK1_Pos 0
ZFLS_OPTBR_LOCK1_Msk (0xffffffffU << FLS_OPTBR_LOCK1_Pos)
\FLS_OPTBR_LOCK2_Pos 0
]FLS_OPTBR_LOCK2_Msk (0xffffffffU << FLS_OPTBR_LOCK2_Pos)
_FLS_OPTBR_LOCK3_Pos 0
`FLS_OPTBR_LOCK3_Msk (0xffffffffU << FLS_OPTBR_LOCK3_Pos)
bFLS_OPTBR_LOCK4_Pos 0
cFLS_OPTBR_LOCK4_Msk (0xffffffffU << FLS_OPTBR_LOCK4_Pos)
eFLS_EPCR_ERTYPE_Pos 8
iFLS_EPCR_ERTYPE_Msk (0x3U << FLS_EPCR_ERTYPE_Pos)
jFLS_EPCR_ERTYPE_PAGE (0x0U << FLS_EPCR_ERTYPE_Pos)
kFLS_EPCR_ERTYPE_SECTOR (0x1U << FLS_EPCR_ERTYPE_Pos)
lFLS_EPCR_ERTYPE_CHIP_ERASE (0x2U << FLS_EPCR_ERTYPE_Pos)
nFLS_EPCR_PREQ_Pos 1
pFLS_EPCR_PREQ_Msk (0x1U << FLS_EPCR_PREQ_Pos)
rFLS_EPCR_EREQ_Pos 0
tFLS_EPCR_EREQ_Msk (0x1U << FLS_EPCR_EREQ_Pos)
vFLS_KEY_KEY_Pos 0
wFLS_KEY_KEY_Msk (0xffffffffU << FLS_KEY_KEY_Pos)
yFLS_IER_OTPIE_Pos 11
zFLS_IER_OTPIE_Msk (0x1U << FLS_IER_OTPIE_Pos)
|FLS_IER_AUTHIE_Pos 10
}FLS_IER_AUTHIE_Msk (0x1U << FLS_IER_AUTHIE_Pos)
FLS_IER_KEYIE_Pos 9
€
FLS_IER_KEYIE_Msk (0x1U << FLS_IER_KEYIE_Pos)
‚
FLS_IER_CKIE_Pos 8
ƒ
FLS_IER_CKIE_Msk (0x1U << FLS_IER_CKIE_Pos)
…
FLS_IER_PRDIE_Pos 1
†
FLS_IER_PRDIE_Msk (0x1U << FLS_IER_PRDIE_Pos)
ˆ
FLS_IER_ERDIE_Pos 0
‰
FLS_IER_ERDIE_Msk (0x1U << FLS_IER_ERDIE_Pos)
‹
FLS_ISR_KEYSTA_Pos 17
’
FLS_ISR_KEYSTA_Msk (0x7U << FLS_ISR_KEYSTA_Pos)
“
FLS_ISR_KEYSTA_KEY_NONE_PROTECT (0x0U << FLS_ISR_KEYSTA_Pos)
”
FLS_ISR_KEYSTA_CHIP_ERASE (0x1U << FLS_ISR_KEYSTA_Pos)
•
FLS_ISR_KEYSTA_SECTOR_ERASE (0x2U << FLS_ISR_KEYSTA_Pos)
–
FLS_ISR_KEYSTA_PROGRAM (0x3U << FLS_ISR_KEYSTA_Pos)
—
FLS_ISR_KEYSTA_KEY_ERR_PROTECT (0x4U << FLS_ISR_KEYSTA_Pos)
™
FLS_ISR_BTSF_Pos 16
œ
FLS_ISR_BTSF_Msk (0x1U << FLS_ISR_BTSF_Pos)

FLS_ISR_BTSF_START_0000H (0x0U << FLS_ISR_BTSF_Pos)
ž
FLS_ISR_BTSF_START_2000H (0x1U << FLS_ISR_BTSF_Pos)
 
FLS_ISR_OTPERR_Pos 11
£
FLS_ISR_OTPERR_Msk (0x1U << FLS_ISR_OTPERR_Pos)
¥
FLS_ISR_AUTHERR_Pos 10
¨
FLS_ISR_AUTHERR_Msk (0x1U << FLS_ISR_AUTHERR_Pos)
ª
FLS_ISR_KEYERR_Pos 9
«
FLS_ISR_KEYERR_Msk (0x1U << FLS_ISR_KEYERR_Pos)
­
FLS_ISR_CKERR_Pos 8
®
FLS_ISR_CKERR_Msk (0x1U << FLS_ISR_CKERR_Pos)
°
FLS_ISR_PRD_Pos 1
±
FLS_ISR_PRD_Msk (0x1U << FLS_ISR_PRD_Pos)
³
FLS_ISR_ERD_Pos 0
´
FLS_ISR_ERD_Msk (0x1U << FLS_ISR_ERD_Pos)`V
 




..\Drivers\..\Core\Include\fm33a0xxev_flash.h
FM33A0XXEV.h

À
..\Drivers\fm33a0xxev_flash.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM
É
Ê
Ë


__FM33A0XXEV_PMU_H 
 PMU_CR_LDO15EN_Pos 17
#PMU_CR_LDO15EN_Msk (0x1U << PMU_CR_LDO15EN_Pos)
%PMU_CR_LDO15EN_B_Pos 16
&PMU_CR_LDO15EN_B_Msk (0x1U << PMU_CR_LDO15EN_B_Pos)
(PMU_CR_WKFSEL_Pos 10
-PMU_CR_WKFSEL_Msk (0x3U << PMU_CR_WKFSEL_Pos)
.PMU_CR_WKFSEL_RCHF_8M (0x0U << PMU_CR_WKFSEL_Pos)
/PMU_CR_WKFSEL_RCHF_16M (0x1U << PMU_CR_WKFSEL_Pos)
0PMU_CR_WKFSEL_RCHF_24M (0x2U << PMU_CR_WKFSEL_Pos)
1PMU_CR_WKFSEL_RCHF_32M (0x3U << PMU_CR_WKFSEL_Pos)
3PMU_CR_SLPDP_Pos 9
8PMU_CR_SLPDP_Msk (0x1U << PMU_CR_SLPDP_Pos)
9PMU_CR_SLPDP_DEEPSLEEP (0x1U << PMU_CR_SLPDP_Pos)
:PMU_CR_SLPDP_SLEEP (0x0U << PMU_CR_SLPDP_Pos)
<PMU_CR_CVS_Pos 8
@PMU_CR_CVS_Msk (0x1U << PMU_CR_CVS_Pos)
APMU_CR_CVS_DISABLE (0x0U << PMU_CR_CVS_Pos)
BPMU_CR_CVS_ENABLE (0x1U << PMU_CR_CVS_Pos)
DPMU_CR_PMOD_Pos 0
IPMU_CR_PMOD_Msk (0x3U << PMU_CR_PMOD_Pos)
JPMU_CR_PMOD_ACTIVE (0x0U << PMU_CR_PMOD_Pos)
KPMU_CR_PMOD_LPRUN (0x1U << PMU_CR_PMOD_Pos)
LPMU_CR_PMOD_SLEEP (0x2U << PMU_CR_PMOD_Pos)
NPMU_WKTR_STPCLR_Pos 2
QPMU_WKTR_STPCLR_Msk (0x1U << PMU_WKTR_STPCLR_Pos)
RPMU_WKTR_STPCLR_SYN (0x0U << PMU_WKTR_STPCLR_Pos)
SPMU_WKTR_STPCLR_ASY (0x1U << PMU_WKTR_STPCLR_Pos)
UPMU_WKTR_T1A_Pos 0
[PMU_WKTR_T1A_Msk (0x3U << PMU_WKTR_T1A_Pos)
\PMU_WKTR_T1A_0US (0x0U << PMU_WKTR_T1A_Pos)
]PMU_WKTR_T1A_2US (0x1U << PMU_WKTR_T1A_Pos)
^PMU_WKTR_T1A_4US (0x2U << PMU_WKTR_T1A_Pos)
_PMU_WKTR_T1A_8US (0x3U << PMU_WKTR_T1A_Pos)
aPMU_WKFR_ADCWKF_Pos 31
bPMU_WKFR_ADCWKF_Msk (0x1U << PMU_WKFR_ADCWKF_Pos)
dPMU_WKFR_RTCWKF_Pos 28
ePMU_WKFR_RTCWKF_Msk (0x1U << PMU_WKFR_RTCWKF_Pos)
gPMU_WKFR_SVDWKF_Pos 27
hPMU_WKFR_SVDWKF_Msk (0x1U << PMU_WKFR_SVDWKF_Pos)
jPMU_WKFR_LFDETWKF_Pos 26
kPMU_WKFR_LFDETWKF_Msk (0x1U << PMU_WKFR_LFDETWKF_Pos)
mPMU_WKFR_IOWKF_Pos 24
nPMU_WKFR_IOWKF_Msk (0x1U << PMU_WKFR_IOWKF_Pos)
pPMU_WKFR_LPU1WKF_Pos 21
qPMU_WKFR_LPU1WKF_Msk (0x1U << PMU_WKFR_LPU1WKF_Pos)
sPMU_WKFR_LPU0WKF_Pos 20
tPMU_WKFR_LPU0WKF_Msk (0x1U << PMU_WKFR_LPU0WKF_Pos)
vPMU_WKFR_COMP_OOWF_Pos 19
wPMU_WKFR_COMP_OOWF_Msk (0x1U << PMU_WKFR_COMP_OOWF_Pos)
yPMU_WKFR_COMP_WINF_Pos 18
zPMU_WKFR_COMP_WINF_Msk (0x1U << PMU_WKFR_COMP_WINF_Pos)
|PMU_WKFR_COMP2WKF_Pos 17
}PMU_WKFR_COMP2WKF_Msk (0x1U << PMU_WKFR_COMP2WKF_Pos)
PMU_WKFR_COMP1WKF_Pos 16
€
PMU_WKFR_COMP1WKF_Msk (0x1U << PMU_WKFR_COMP1WKF_Pos)
‚
PMU_WKFR_LPTWKF_Pos 10
ƒ
PMU_WKFR_LPTWKF_Msk (0x1U << PMU_WKFR_LPTWKF_Pos)
…
PMU_WKFR_BSTWKF_Pos 9
†
PMU_WKFR_BSTWKF_Msk (0x1U << PMU_WKFR_BSTWKF_Pos)
ˆ
PMU_WKFR_DBGWKF_Pos 8
‰
PMU_WKFR_DBGWKF_Msk (0x1U << PMU_WKFR_DBGWKF_Pos)
Œ
PMU_IER_SLPEIE_Pos 1

PMU_IER_SLPEIE_Msk (0x1U << PMU_IER_SLPEIE_Pos)
“
PMU_IER_RTCEIE_Pos 0
–
PMU_IER_RTCEIE_Msk (0x1U << PMU_IER_RTCEIE_Pos)
š
PMU_ISR_SLPEIF_Pos 1

PMU_ISR_SLPEIF_Msk (0x1U << PMU_ISR_SLPEIF_Pos)
Ÿ
PMU_ISR_RTCEIF_Pos 0
¢
PMU_ISR_RTCEIF_Msk (0x1U << PMU_ISR_RTCEIF_Pos)`T
 




..\Drivers\..\Core\Include\fm33a0xxev_pmu.h
FM33A0XXEV.h

$

..\Drivers\fm33a0xxev_pmu.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM*†PMODf
#SLPDPf
#CVS
#SCRf
#TIAf
#PPMU_SleepCfg_InitTypeDef½

Í
Î
Ï


__FM33A0XXEV_CMU_H 
HXVAR(object,addr) (*((object *) (addr)))
const_rchf_Trim8 HXVAR( uint32_t, 0x1FFFFB40 )
const_rchf_Trim16 HXVAR( uint32_t, 0x1FFFFB3C )
const_rchf_Trim24 HXVAR( uint32_t, 0x1FFFFB38 )
const_rchf_Trim32 HXVAR( uint32_t, 0x1FFFFB34)
!__XTHF_CLOCK (12000000)
RCMU_SYSCLKCR_SLP_ENEXTI_Pos 25
SCMU_SYSCLKCR_SLP_ENEXTI_Msk (0x1U << CMU_SYSCLKCR_SLP_ENEXTI_Pos)
UCMU_SYSCLKCR_APBPRES_Pos 16
[CMU_SYSCLKCR_APBPRES_Msk (0x7U << CMU_SYSCLKCR_APBPRES_Pos)
\CMU_SYSCLKCR_APBPRES_DIV1 (0x0U << CMU_SYSCLKCR_APBPRES_Pos)
]CMU_SYSCLKCR_APBPRES_DIV2 (0x4U << CMU_SYSCLKCR_APBPRES_Pos)
^CMU_SYSCLKCR_APBPRES_DIV4 (0x5U << CMU_SYSCLKCR_APBPRES_Pos)
_CMU_SYSCLKCR_APBPRES_DIV8 (0x6U << CMU_SYSCLKCR_APBPRES_Pos)
`CMU_SYSCLKCR_APBPRES_DIV16 (0x7U << CMU_SYSCLKCR_APBPRES_Pos)
bCMU_SYSCLKCR_AHBPRES_Pos 8
hCMU_SYSCLKCR_AHBPRES_Msk (0x7U << CMU_SYSCLKCR_AHBPRES_Pos)
iCMU_SYSCLKCR_AHBPRES_DIV1 (0x0U << CMU_SYSCLKCR_AHBPRES_Pos)
jCMU_SYSCLKCR_AHBPRES_DIV2 (0x4U << CMU_SYSCLKCR_AHBPRES_Pos)
kCMU_SYSCLKCR_AHBPRES_DIV4 (0x5U << CMU_SYSCLKCR_AHBPRES_Pos)
lCMU_SYSCLKCR_AHBPRES_DIV8 (0x6U << CMU_SYSCLKCR_AHBPRES_Pos)
mCMU_SYSCLKCR_AHBPRES_DIV16 (0x7U << CMU_SYSCLKCR_AHBPRES_Pos)
oCMU_SYSCLKCR_STCLKSEL_Pos 6
tCMU_SYSCLKCR_STCLKSEL_Msk (0x3U << CMU_SYSCLKCR_STCLKSEL_Pos)
uCMU_SYSCLKCR_STCLKSEL_SCLK (0x0U << CMU_SYSCLKCR_STCLKSEL_Pos)
vCMU_SYSCLKCR_STCLKSEL_LSCLK (0x1U << CMU_SYSCLKCR_STCLKSEL_Pos)
wCMU_SYSCLKCR_STCLKSEL_RC4M (0x2U << CMU_SYSCLKCR_STCLKSEL_Pos)
xCMU_SYSCLKCR_STCLKSEL_SYSCLK (0x3U << CMU_SYSCLKCR_STCLKSEL_Pos)
zCMU_SYSCLKCR_SYSCLKSEL_Pos 0
{CMU_SYSCLKCR_SYSCLKSEL_Msk (0x7U << CMU_SYSCLKCR_SYSCLKSEL_Pos)
|CMU_SYSCLKCR_SYSCLKSEL_RCHF (0x0U << CMU_SYSCLKCR_SYSCLKSEL_Pos)
}CMU_SYSCLKCR_SYSCLKSEL_XTHF (0x1U << CMU_SYSCLKCR_SYSCLKSEL_Pos)
~CMU_SYSCLKCR_SYSCLKSEL_PLL_H (0x2U << CMU_SYSCLKCR_SYSCLKSEL_Pos)
CMU_SYSCLKCR_SYSCLKSEL_LSCLK (0x3U << CMU_SYSCLKCR_SYSCLKSEL_Pos)

CMU_RCHFCR_FSEL_Pos 16
ˆ
CMU_RCHFCR_FSEL_Msk (0xfU << CMU_RCHFCR_FSEL_Pos)
‰
CMU_RCHFCR_FSEL_8MHZ (0x0U << CMU_RCHFCR_FSEL_Pos)
Š
CMU_RCHFCR_FSEL_16MHZ (0x1U << CMU_RCHFCR_FSEL_Pos)
‹
CMU_RCHFCR_FSEL_24MHZ (0x2U << CMU_RCHFCR_FSEL_Pos)
Œ
CMU_RCHFCR_FSEL_32MHZ (0x3U << CMU_RCHFCR_FSEL_Pos)
Ž
CMU_RCHFCR_RCHFEN_Pos 0
‘
CMU_RCHFCR_RCHFEN_Msk (0x1U << CMU_RCHFCR_RCHFEN_Pos)
•
CMU_RCHFTR_RCHFTRIM_Pos 0
˜
CMU_RCHFTR_RCHFTRIM_Msk (0xffU << CMU_RCHFTR_RCHFTRIM_Pos)
š
CMU_PLLLCR_PLLDB_Pos 16
›
CMU_PLLLCR_PLLDB_Msk (0x3ffU << CMU_PLLLCR_PLLDB_Pos)

CMU_PLLLCR_LOCKED_Pos 7
ž
CMU_PLLLCR_LOCKED_Msk (0x1U << CMU_PLLLCR_LOCKED_Pos)
 
CMU_PLLLCR_PLLEN_Pos 0
£
CMU_PLLLCR_PLLEN_Msk (0x1U << CMU_PLLLCR_PLLEN_Pos)
¥
CMU_PLLHCR_PLLHDB_Pos 16
¨
CMU_PLLHCR_PLLHDB_Msk (0x3ffU << CMU_PLLHCR_PLLHDB_Pos)
©
CMU_PLLHCR_PLLHDB_X32 (0x1fU << CMU_PLLHCR_PLLHDB_Pos)
ª
CMU_PLLHCR_PLLHDB_X48 (0x2fU << CMU_PLLHCR_PLLHDB_Pos)
«
CMU_PLLHCR_PLLHDB_X64 (0x3fU << CMU_PLLHCR_PLLHDB_Pos)
­
CMU_PLLHCR_LOCKED_Pos 7
°
CMU_PLLHCR_LOCKED_Msk (0x1U << CMU_PLLHCR_LOCKED_Pos)
²
CMU_PLLHCR_REFPRSC_Pos 4
»
CMU_PLLHCR_REFPRSC_Msk (0x7U << CMU_PLLHCR_REFPRSC_Pos)
¼
CMU_PLLHCR_REFPRSC_DIV1 (0x0U << CMU_PLLHCR_REFPRSC_Pos)
½
CMU_PLLHCR_REFPRSC_DIV2 (0x1U << CMU_PLLHCR_REFPRSC_Pos)
¾
CMU_PLLHCR_REFPRSC_DIV4 (0x2U << CMU_PLLHCR_REFPRSC_Pos)
¿
CMU_PLLHCR_REFPRSC_DIV8 (0x3U << CMU_PLLHCR_REFPRSC_Pos)
À
CMU_PLLHCR_REFPRSC_DIV12 (0x4U << CMU_PLLHCR_REFPRSC_Pos)
Á
CMU_PLLHCR_REFPRSC_DIV16 (0x5U << CMU_PLLHCR_REFPRSC_Pos)
Â
CMU_PLLHCR_REFPRSC_DIV24 (0x6U << CMU_PLLHCR_REFPRSC_Pos)
Ã
CMU_PLLHCR_REFPRSC_DIV32 (0x7U << CMU_PLLHCR_REFPRSC_Pos)
Å
CMU_PLLHCR_OSEL_Pos 3
È
CMU_PLLHCR_OSEL_Msk (0x1U << CMU_PLLHCR_OSEL_Pos)
É
CMU_PLLHCR_OSEL_X1 (0x0U << CMU_PLLHCR_OSEL_Pos)
Ê
CMU_PLLHCR_OSEL_X2 (0x1U << CMU_PLLHCR_OSEL_Pos)
Ì
CMU_PLLHCR_INSEL_Pos 1
Ï
CMU_PLLHCR_INSEL_Msk (0x1U << CMU_PLLHCR_INSEL_Pos)
Ð
CMU_PLLHCR_INSEL_RCHF (0x0U << CMU_PLLHCR_INSEL_Pos)
Ñ
CMU_PLLHCR_INSEL_XTHF (0x1U << CMU_PLLHCR_INSEL_Pos)
Ó
CMU_PLLHCR_EN_Pos 0
Ö
CMU_PLLHCR_EN_Msk (0x1U << CMU_PLLHCR_EN_Pos)
Ø
CMU_XTHFCR_XTHF_CFG_Pos 8
Û
CMU_XTHFCR_XTHF_CFG_Msk (0x7U << CMU_XTHFCR_XTHF_CFG_Pos)
Ü
CMU_XTHFCR_XTHF_CFG_MIN (0x0U << CMU_XTHFCR_XTHF_CFG_Pos)
Ý
CMU_XTHFCR_XTHF_CFG_MAX (0x7U << CMU_XTHFCR_XTHF_CFG_Pos)
ß
CMU_XTHFCR_XTHFEN_Pos 0
â
CMU_XTHFCR_XTHFEN_Msk (0x1U << CMU_XTHFCR_XTHFEN_Pos)
æ
CMU_IER_SYSCSE_IE_Pos 1
ç
CMU_IER_SYSCSE_IE_Msk (0x1U << CMU_IER_SYSCSE_IE_Pos)
é
CMU_IER_HFDET_IE_Pos 0
ê
CMU_IER_HFDET_IE_Msk (0x1U << CMU_IER_HFDET_IE_Pos)
í
CMU_ISR_HFDETO_Pos 8
ð
CMU_ISR_HFDETO_Msk (0x1U << CMU_ISR_HFDETO_Pos)
ò
CMU_ISR_SYSCSE_IF_Pos 1
ó
CMU_ISR_SYSCSE_IF_Msk (0x1U << CMU_ISR_SYSCSE_IF_Pos)
õ
CMU_ISR_HFDET_IF_Pos 0
ö
CMU_ISR_HFDET_IF_Msk (0x1U << CMU_ISR_HFDET_IF_Pos)
ø
CMU_PCLKCR1_COMP_PCE_Pos 9
ù
CMU_PCLKCR1_COMP_PCE_Msk (0x1U << CMU_PCLKCR1_COMP_PCE_Pos)
û
CMU_PCLKCR1_SVD_PCE_Pos 8
ü
CMU_PCLKCR1_SVD_PCE_Msk (0x1U << CMU_PCLKCR1_SVD_PCE_Pos)
þ
CMU_PCLKCR1_PAD_PCE_Pos 7
ÿ
CMU_PCLKCR1_PAD_PCE_Msk (0x1U << CMU_PCLKCR1_PAD_PCE_Pos)
CMU_PCLKCR1_ANAC_PCE_Pos 6
ƒCMU_PCLKCR1_ANAC_PCE_Msk (0x1U << CMU_PCLKCR1_ANAC_PCE_Pos)
…CMU_PCLKCR1_IWDT_PCE_Pos 5
†CMU_PCLKCR1_IWDT_PCE_Msk (0x1U << CMU_PCLKCR1_IWDT_PCE_Pos)
ˆCMU_PCLKCR1_SCU_PCE_Pos 4
‰CMU_PCLKCR1_SCU_PCE_Msk (0x1U << CMU_PCLKCR1_SCU_PCE_Pos)
‹CMU_PCLKCR1_PMU_PCE_Pos 3
ŒCMU_PCLKCR1_PMU_PCE_Msk (0x1U << CMU_PCLKCR1_PMU_PCE_Pos)
ŽCMU_PCLKCR1_RTC_PCE_Pos 2
CMU_PCLKCR1_RTC_PCE_Msk (0x1U << CMU_PCLKCR1_RTC_PCE_Pos)
‘CMU_PCLKCR1_LPT_PCE_Pos 0
’CMU_PCLKCR1_LPT_PCE_Msk (0x1U << CMU_PCLKCR1_LPT_PCE_Pos)
”CMU_PCLKCR2_PAE_PCE_Pos 17
•CMU_PCLKCR2_PAE_PCE_Msk (0x1U << CMU_PCLKCR2_PAE_PCE_Pos)
—CMU_PCLKCR2_SHA_PCE_Pos 16
˜CMU_PCLKCR2_SHA_PCE_Msk (0x1U << CMU_PCLKCR2_SHA_PCE_Pos)
šCMU_PCLKCR2_CIC_PCE_Pos 8
›CMU_PCLKCR2_CIC_PCE_Msk (0x1U << CMU_PCLKCR2_CIC_PCE_Pos)
CMU_PCLKCR2_WWDT_PCE_Pos 7
žCMU_PCLKCR2_WWDT_PCE_Msk (0x1U << CMU_PCLKCR2_WWDT_PCE_Pos)
 CMU_PCLKCR2_RAMBIST_PCE_Pos 6
¡CMU_PCLKCR2_RAMBIST_PCE_Msk (0x1U << CMU_PCLKCR2_RAMBIST_PCE_Pos)
£CMU_PCLKCR2_NVM_PCE_Pos 5
¤CMU_PCLKCR2_NVM_PCE_Msk (0x1U << CMU_PCLKCR2_NVM_PCE_Pos)
¦CMU_PCLKCR2_DMA_PCE_Pos 4
§CMU_PCLKCR2_DMA_PCE_Msk (0x1U << CMU_PCLKCR2_DMA_PCE_Pos)
©CMU_PCLKCR2_LCD_PCE_Pos 3
ªCMU_PCLKCR2_LCD_PCE_Msk (0x1U << CMU_PCLKCR2_LCD_PCE_Pos)
¬CMU_PCLKCR2_AES_PCE_Pos 2
­CMU_PCLKCR2_AES_PCE_Msk (0x1U << CMU_PCLKCR2_AES_PCE_Pos)
¯CMU_PCLKCR2_TRNG_PCE_Pos 1
°CMU_PCLKCR2_TRNG_PCE_Msk (0x1U << CMU_PCLKCR2_TRNG_PCE_Pos)
²CMU_PCLKCR2_CRC_PCE_Pos 0
³CMU_PCLKCR2_CRC_PCE_Msk (0x1U << CMU_PCLKCR2_CRC_PCE_Pos)
µCMU_PCLKCR3_I2C1_PCE_Pos 25
¶CMU_PCLKCR3_I2C1_PCE_Msk (0x1U << CMU_PCLKCR3_I2C1_PCE_Pos)
¸CMU_PCLKCR3_I2C0_PCE_Pos 24
¹CMU_PCLKCR3_I2C0_PCE_Msk (0x1U << CMU_PCLKCR3_I2C0_PCE_Pos)
»CMU_PCLKCR3_LPUART1_PCE_Pos 18
¼CMU_PCLKCR3_LPUART1_PCE_Msk (0x1U << CMU_PCLKCR3_LPUART1_PCE_Pos)
¾CMU_PCLKCR3_U7816_PCE_Pos 16
¿CMU_PCLKCR3_U7816_PCE_Msk (0x1U << CMU_PCLKCR3_U7816_PCE_Pos)
ÁCMU_PCLKCR3_LPUART0_PCE_Pos 15
ÂCMU_PCLKCR3_LPUART0_PCE_Msk (0x1U << CMU_PCLKCR3_LPUART0_PCE_Pos)
ÄCMU_PCLKCR3_UICR_PCE_Pos 14
ÅCMU_PCLKCR3_UICR_PCE_Msk (0x1U << CMU_PCLKCR3_UICR_PCE_Pos)
ÇCMU_PCLKCR3_UART5_PCE_Pos 13
ÈCMU_PCLKCR3_UART5_PCE_Msk (0x1U << CMU_PCLKCR3_UART5_PCE_Pos)
ÊCMU_PCLKCR3_UART4_PCE_Pos 12
ËCMU_PCLKCR3_UART4_PCE_Msk (0x1U << CMU_PCLKCR3_UART4_PCE_Pos)
ÍCMU_PCLKCR3_UART3_PCE_Pos 11
ÎCMU_PCLKCR3_UART3_PCE_Msk (0x1U << CMU_PCLKCR3_UART3_PCE_Pos)
ÐCMU_PCLKCR3_UART2_PCE_Pos 10
ÑCMU_PCLKCR3_UART2_PCE_Msk (0x1U << CMU_PCLKCR3_UART2_PCE_Pos)
ÓCMU_PCLKCR3_UART1_PCE_Pos 9
ÔCMU_PCLKCR3_UART1_PCE_Msk (0x1U << CMU_PCLKCR3_UART1_PCE_Pos)
ÖCMU_PCLKCR3_UART0_PCE_Pos 8
×CMU_PCLKCR3_UART0_PCE_Msk (0x1U << CMU_PCLKCR3_UART0_PCE_Pos)
ÙCMU_PCLKCR3_QSPI_PCE_Pos 7
ÚCMU_PCLKCR3_QSPI_PCE_Msk (0x1U << CMU_PCLKCR3_QSPI_PCE_Pos)
ÜCMU_PCLKCR3_SPI4_PCE_Pos 4
ÝCMU_PCLKCR3_SPI4_PCE_Msk (0x1U << CMU_PCLKCR3_SPI4_PCE_Pos)
ßCMU_PCLKCR3_SPI3_PCE_Pos 3
àCMU_PCLKCR3_SPI3_PCE_Msk (0x1U << CMU_PCLKCR3_SPI3_PCE_Pos)
âCMU_PCLKCR3_SPI2_PCE_Pos 2
ãCMU_PCLKCR3_SPI2_PCE_Msk (0x1U << CMU_PCLKCR3_SPI2_PCE_Pos)
åCMU_PCLKCR3_SPI1_PCE_Pos 1
æCMU_PCLKCR3_SPI1_PCE_Msk (0x1U << CMU_PCLKCR3_SPI1_PCE_Pos)
èCMU_PCLKCR3_SPI0_PCE_Pos 0
éCMU_PCLKCR3_SPI0_PCE_Msk (0x1U << CMU_PCLKCR3_SPI0_PCE_Pos)
ëCMU_PCLKCR4_ET4_PCE_Pos 6
ìCMU_PCLKCR4_ET4_PCE_Msk (0x1U << CMU_PCLKCR4_ET4_PCE_Pos)
îCMU_PCLKCR4_ET3_PCE_Pos 5
ïCMU_PCLKCR4_ET3_PCE_Msk (0x1U << CMU_PCLKCR4_ET3_PCE_Pos)
ñCMU_PCLKCR4_ET2_PCE_Pos 4
òCMU_PCLKCR4_ET2_PCE_Msk (0x1U << CMU_PCLKCR4_ET2_PCE_Pos)
ôCMU_PCLKCR4_ET1_PCE_Pos 3
õCMU_PCLKCR4_ET1_PCE_Msk (0x1U << CMU_PCLKCR4_ET1_PCE_Pos)
÷CMU_PCLKCR4_BT2_PCE_Pos 2
øCMU_PCLKCR4_BT2_PCE_Msk (0x1U << CMU_PCLKCR4_BT2_PCE_Pos)
úCMU_PCLKCR4_BT1_PCE_Pos 1
ûCMU_PCLKCR4_BT1_PCE_Msk (0x1U << CMU_PCLKCR4_BT1_PCE_Pos)
ýCMU_PCLKCR4_BSTIM_PCE_Pos 0
þCMU_PCLKCR4_BSTIM_PCE_Msk (0x1U << CMU_PCLKCR4_BSTIM_PCE_Pos)
€CMU_OPCCR1_EXTICKE_Pos 31
CMU_OPCCR1_EXTICKE_Msk (0x1U << CMU_OPCCR1_EXTICKE_Pos)
ƒCMU_OPCCR1_EXTICKSEL_Pos 30
„CMU_OPCCR1_EXTICKSEL_Msk (0x1U << CMU_OPCCR1_EXTICKSEL_Pos)
…CMU_OPCCR1_EXTICKSEL_LSCLK (0x1U << CMU_OPCCR1_EXTICKSEL_Pos)
†CMU_OPCCR1_EXTICKSEL_HCLK (0x0U << CMU_OPCCR1_EXTICKSEL_Pos)
ˆCMU_OPCCR1_LPUART1CKE_Pos 29
‰CMU_OPCCR1_LPUART1CKE_Msk (0x1U << CMU_OPCCR1_LPUART1CKE_Pos)
‹CMU_OPCCR1_LPUART0CKE_Pos 28
ŒCMU_OPCCR1_LPUART0CKE_Msk (0x1U << CMU_OPCCR1_LPUART0CKE_Pos)
ŽCMU_OPCCR1_LPUART1CKS_Pos 26
“CMU_OPCCR1_LPUART1CKS_Msk (0x3U << CMU_OPCCR1_LPUART1CKS_Pos)
”CMU_OPCCR1_LPUART1CKS_LSCLK (0x0U << CMU_OPCCR1_LPUART1CKS_Pos)
•CMU_OPCCR1_LPUART1CKS_RCHF (0x1U << CMU_OPCCR1_LPUART1CKS_Pos)
—CMU_OPCCR1_LPUART0CKS_Pos 24
œCMU_OPCCR1_LPUART0CKS_Msk (0x3U << CMU_OPCCR1_LPUART0CKS_Pos)
CMU_OPCCR1_LPUART0CKS_LSCLK (0x0U << CMU_OPCCR1_LPUART0CKS_Pos)
žCMU_OPCCR1_LPUART0CKS_RCHF (0x1U << CMU_OPCCR1_LPUART0CKS_Pos)
 CMU_OPCCR1_I2C1CKE_Pos 21
¡CMU_OPCCR1_I2C1CKE_Msk (0x1U << CMU_OPCCR1_I2C1CKE_Pos)
£CMU_OPCCR1_I2C0CKE_Pos 20
¤CMU_OPCCR1_I2C0CKE_Msk (0x1U << CMU_OPCCR1_I2C0CKE_Pos)
¦CMU_OPCCR1_I2C1CKS_Pos 18
«CMU_OPCCR1_I2C1CKS_Msk (0x3U << CMU_OPCCR1_I2C1CKS_Pos)
¬CMU_OPCCR1_I2C1CKS_APBCLK (0x0U << CMU_OPCCR1_I2C1CKS_Pos)
­CMU_OPCCR1_I2C1CKS_RCHF (0x1U << CMU_OPCCR1_I2C1CKS_Pos)
®CMU_OPCCR1_I2C1CKS_SYSCLK (0x2U << CMU_OPCCR1_I2C1CKS_Pos)
°CMU_OPCCR1_I2C0CKS_Pos 16
µCMU_OPCCR1_I2C0CKS_Msk (0x3U << CMU_OPCCR1_I2C0CKS_Pos)
¶CMU_OPCCR1_I2C0CKS_APBCLK (0x0U << CMU_OPCCR1_I2C0CKS_Pos)
·CMU_OPCCR1_I2C0CKS_RCHF (0x1U << CMU_OPCCR1_I2C0CKS_Pos)
¸CMU_OPCCR1_I2C0CKS_SYSCLK (0x2U << CMU_OPCCR1_I2C0CKS_Pos)
ºCMU_OPCCR1_UART1CKE_Pos 9
»CMU_OPCCR1_UART1CKE_Msk (0x1U << CMU_OPCCR1_UART1CKE_Pos)
½CMU_OPCCR1_UART0CKE_Pos 8
¾CMU_OPCCR1_UART0CKE_Msk (0x1U << CMU_OPCCR1_UART0CKE_Pos)
ÀCMU_OPCCR1_UART1CKS_Pos 2
ÅCMU_OPCCR1_UART1CKS_Msk (0x3U << CMU_OPCCR1_UART1CKS_Pos)
ÆCMU_OPCCR1_UART1CKS_APBCLK (0x0U << CMU_OPCCR1_UART1CKS_Pos)
ÇCMU_OPCCR1_UART1CKS_RCHF (0x1U << CMU_OPCCR1_UART1CKS_Pos)
ÈCMU_OPCCR1_UART1CKS_SYSCLK (0x2U << CMU_OPCCR1_UART1CKS_Pos)
ÊCMU_OPCCR1_UART0CKS_Pos 0
ÏCMU_OPCCR1_UART0CKS_Msk (0x3U << CMU_OPCCR1_UART0CKS_Pos)
ÐCMU_OPCCR1_UART0CKS_APBCLK (0x0U << CMU_OPCCR1_UART0CKS_Pos)
ÑCMU_OPCCR1_UART0CKS_RCHF (0x1U << CMU_OPCCR1_UART0CKS_Pos)
ÒCMU_OPCCR1_UART0CKS_SYSCLK (0x2U << CMU_OPCCR1_UART0CKS_Pos)
ÔCMU_OPCCR2_RNGPRSC_Pos 28
ÜCMU_OPCCR2_RNGPRSC_Msk (0x7U << CMU_OPCCR2_RNGPRSC_Pos)
ÝCMU_OPCCR2_RNGPRSC_DIV1 (0x0U << CMU_OPCCR2_RNGPRSC_Pos)
ÞCMU_OPCCR2_RNGPRSC_DIV2 (0x1U << CMU_OPCCR2_RNGPRSC_Pos)
ßCMU_OPCCR2_RNGPRSC_DIV4 (0x2U << CMU_OPCCR2_RNGPRSC_Pos)
àCMU_OPCCR2_RNGPRSC_DIV8 (0x3U << CMU_OPCCR2_RNGPRSC_Pos)
áCMU_OPCCR2_RNGPRSC_DIV16 (0x4U << CMU_OPCCR2_RNGPRSC_Pos)
âCMU_OPCCR2_RNGPRSC_DIV32 (0x5U << CMU_OPCCR2_RNGPRSC_Pos)
äCMU_OPCCR2_NVMCKE_Pos 22
åCMU_OPCCR2_NVMCKE_Msk (0x1U << CMU_OPCCR2_NVMCKE_Pos)
çCMU_OPCCR2_RNGCKE_Pos 21
èCMU_OPCCR2_RNGCKE_Msk (0x1U << CMU_OPCCR2_RNGCKE_Pos)
êCMU_OPCCR2_LPTCKE_Pos 12
ëCMU_OPCCR2_LPTCKE_Msk (0x1U << CMU_OPCCR2_LPTCKE_Pos)
íCMU_OPCCR2_LPTCKS_Pos 8
òCMU_OPCCR2_LPTCKS_Msk (0x3U << CMU_OPCCR2_LPTCKS_Pos)
óCMU_OPCCR2_LPTCKS_APBCLK (0x0U << CMU_OPCCR2_LPTCKS_Pos)
ôCMU_OPCCR2_LPTCKS_LSCLK (0x1U << CMU_OPCCR2_LPTCKS_Pos)
õCMU_OPCCR2_LPTCKS_RCLP (0x2U << CMU_OPCCR2_LPTCKS_Pos)
öCMU_OPCCR2_LPTCKS_PLL_L (0x3U << CMU_OPCCR2_LPTCKS_Pos)
øCMU_OPCCR2_BSTCKE_Pos 4
ùCMU_OPCCR2_BSTCKE_Msk (0x1U << CMU_OPCCR2_BSTCKE_Pos)
ûCMU_OPCCR2_BSTCKS_Pos 0
€CMU_OPCCR2_BSTCKS_Msk (0x3U << CMU_OPCCR2_BSTCKS_Pos)
CMU_OPCCR2_BSTCKS_APBCLK (0x0U << CMU_OPCCR2_BSTCKS_Pos)
‚CMU_OPCCR2_BSTCKS_LSCLK (0x1U << CMU_OPCCR2_BSTCKS_Pos)
ƒCMU_OPCCR2_BSTCKS_RCLP (0x2U << CMU_OPCCR2_BSTCKS_Pos)
„CMU_OPCCR2_BSTCKS_SYSCLK (0x3U << CMU_OPCCR2_BSTCKS_Pos)
£COMPCLK (0x01000000 + CMU_PCLKCR1_COMP_PCE_Pos)
¤SVDCLK (0x01000000 + CMU_PCLKCR1_SVD_PCE_Pos)
¥PADCLK (0x01000000 + CMU_PCLKCR1_PAD_PCE_Pos)
¦ANACCLK (0x01000000 + CMU_PCLKCR1_ANAC_PCE_Pos)
§IWDTCLK (0x01000000 + CMU_PCLKCR1_IWDT_PCE_Pos)
¨SCUCLK (0x01000000 + CMU_PCLKCR1_SCU_PCE_Pos)
©PMUCLK (0x01000000 + CMU_PCLKCR1_PMU_PCE_Pos)
ªRTCCLK (0x01000000 + CMU_PCLKCR1_RTC_PCE_Pos)
«LPTCLK (0x01000000 + CMU_PCLKCR1_LPT_PCE_Pos)
®PAECLK (0x02000000 + CMU_PCLKCR2_PAE_PCE_Pos)
¯SHACLK (0x02000000 + CMU_PCLKCR2_SHA_PCE_Pos)
°CICCLK (0x02000000 + CMU_PCLKCR2_CIC_PCE_Pos)
±WWDTCLK (0x02000000 + CMU_PCLKCR2_WWDT_PCE_Pos)
²RAMBISTCLK (0x02000000 + CMU_PCLKCR2_RAMBIST_PCE_Pos)
³FLASHCLK (0x02000000 + CMU_PCLKCR2_NVM_PCE_Pos)
´DMACLK (0x02000000 + CMU_PCLKCR2_DMA_PCE_Pos)
µLCDCLK (0x02000000 + CMU_PCLKCR2_LCD_PCE_Pos)
¶AESCLK (0x02000000 + CMU_PCLKCR2_AES_PCE_Pos)
·TRNGCLK (0x02000000 + CMU_PCLKCR2_TRNG_PCE_Pos)
¸CRCCLK (0x02000000 + CMU_PCLKCR2_CRC_PCE_Pos)
ºI2C1CLK (0x03000000 + CMU_PCLKCR3_I2C1_PCE_Pos)
»I2C0CLK (0x03000000 + CMU_PCLKCR3_I2C0_PCE_Pos)
¼LPUART1CLK (0x03000000 + CMU_PCLKCR3_LPUART1_PCE_Pos)
½U7816CLK (0x03000000 + CMU_PCLKCR3_U7816_PCE_Pos)
¾LPUART0CLK (0x03000000 + CMU_PCLKCR3_LPUART0_PCE_Pos)
¿UARTIRCLK (0x03000000 + CMU_PCLKCR3_UICR_PCE_Pos)
ÀUART5CLK (0x03000000 + CMU_PCLKCR3_UART5_PCE_Pos)
ÁUART4CLK (0x03000000 + CMU_PCLKCR3_UART4_PCE_Pos)
ÂUART3CLK (0x03000000 + CMU_PCLKCR3_UART3_PCE_Pos)
ÃUART2CLK (0x03000000 + CMU_PCLKCR3_UART2_PCE_Pos)
ÄUART1CLK (0x03000000 + CMU_PCLKCR3_UART1_PCE_Pos)
ÅUART0CLK (0x03000000 + CMU_PCLKCR3_UART0_PCE_Pos)
ÆQSPICLK (0x03000000 + CMU_PCLKCR3_QSPI_PCE_Pos)
ÇSPI4CLK (0x03000000 + CMU_PCLKCR3_SPI4_PCE_Pos)
ÈSPI3CLK (0x03000000 + CMU_PCLKCR3_SPI3_PCE_Pos)
ÉSPI2CLK (0x03000000 + CMU_PCLKCR3_SPI2_PCE_Pos)
ÊSPI1CLK (0x03000000 + CMU_PCLKCR3_SPI1_PCE_Pos)
ËSPI0CLK (0x03000000 + CMU_PCLKCR3_SPI0_PCE_Pos)
ÎET4CLK (0x04000000 + CMU_PCLKCR4_ET4_PCE_Pos)
ÏET3CLK (0x04000000 + CMU_PCLKCR4_ET3_PCE_Pos)
ÐET2CLK (0x04000000 + CMU_PCLKCR4_ET2_PCE_Pos)
ÑET1CLK (0x04000000 + CMU_PCLKCR4_ET1_PCE_Pos)
ÒBT2CLK (0x04000000 + CMU_PCLKCR4_BT2_PCE_Pos)
ÓBT1CLK (0x04000000 + CMU_PCLKCR4_BT1_PCE_Pos)
ÔBSTIMCLK (0x04000000 + CMU_PCLKCR4_BSTIM_PCE_Pos)`T
 




..\Drivers\..\Core\Include\fm33a0xxev_cmu.h
FM33A0XXEV.h

ð
..\Drivers\fm33a0xxev_cmu.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM*à
FSELf
#RCHFEN
#PCMU_RCHF_InitTypeDef½
)*¢PLLLDBf
#PLLL_EN
#PCMU_PLL_L_InitTypeDefü
/*PLLHDBf
#REFPRSCf
#PLLH_OSELf
#PLLH_INSELf
#PLLH_EN
#PCMU_PLL_H_InitTypeDef?

9*ˆSYSCLKSELf
#AHBPRESf
#APBPRESf
#SLP_ENEXTI
#PCMU_SYSCLK_InitTypeDefº

C*ÛSYSCLK_Frequencyf
#AHBCLK_Frequencyf
#APBCLK_Frequencyf
#RCHF_Frequencyf
#PLL_H_Frequencyf
#XTHF_Frequencyf
#LSCLK_Frequencyf
#PCMU_ClocksType&
N
Ñ
Ò
Ó


__FM33A0XXEV_RTC_H 
/RTC_WRITE_ENABLE ((uint32_t)0xACACACAC)
0RTC_WRITE_DISABLE ((uint32_t)0x55AA55AA)
2RTC_WER_RTCWE_Pos 0
4RTC_WER_RTCWE_Msk (0x1U << RTC_WER_RTCWE_Pos)
6RTC_IER_ADJ_IE_Pos 12
9RTC_IER_ADJ_IE_Msk (0x1U << RTC_IER_ADJ_IE_Pos)
=RTC_IER_ALARM_IE_Pos 11
@RTC_IER_ALARM_IE_Msk (0x1U << RTC_IER_ALARM_IE_Pos)
DRTC_IER_1KHZ_IE_Pos 10
GRTC_IER_1KHZ_IE_Msk (0x1U << RTC_IER_1KHZ_IE_Pos)
KRTC_IER_256HZ_IE_Pos 9
NRTC_IER_256HZ_IE_Msk (0x1U << RTC_IER_256HZ_IE_Pos)
RRTC_IER_64HZ_IE_Pos 8
URTC_IER_64HZ_IE_Msk (0x1U << RTC_IER_64HZ_IE_Pos)
YRTC_IER_16HZ_IE_Pos 7
\RTC_IER_16HZ_IE_Msk (0x1U << RTC_IER_16HZ_IE_Pos)
`RTC_IER_8HZ_IE_Pos 6
cRTC_IER_8HZ_IE_Msk (0x1U << RTC_IER_8HZ_IE_Pos)
gRTC_IER_4HZ_IE_Pos 5
jRTC_IER_4HZ_IE_Msk (0x1U << RTC_IER_4HZ_IE_Pos)
nRTC_IER_2HZ_IE_Pos 4
qRTC_IER_2HZ_IE_Msk (0x1U << RTC_IER_2HZ_IE_Pos)
uRTC_IER_SEC_IE_Pos 3
xRTC_IER_SEC_IE_Msk (0x1U << RTC_IER_SEC_IE_Pos)
|RTC_IER_MIN_IE_Pos 2
RTC_IER_MIN_IE_Msk (0x1U << RTC_IER_MIN_IE_Pos)
ƒ
RTC_IER_HOUR_IE_Pos 1
†
RTC_IER_HOUR_IE_Msk (0x1U << RTC_IER_HOUR_IE_Pos)
Š
RTC_IER_DATE_IE_Pos 0

RTC_IER_DATE_IE_Msk (0x1U << RTC_IER_DATE_IE_Pos)
‘
RTC_ISR_ADJ_IF_Pos 12
”
RTC_ISR_ADJ_IF_Msk (0x1U << RTC_ISR_ADJ_IF_Pos)
–
RTC_ISR_ALARM_IF_Pos 11
™
RTC_ISR_ALARM_IF_Msk (0x1U << RTC_ISR_ALARM_IF_Pos)
›
RTC_ISR_1KHZ_IF_Pos 10
ž
RTC_ISR_1KHZ_IF_Msk (0x1U << RTC_ISR_1KHZ_IF_Pos)
 
RTC_ISR_256HZ_IF_Pos 9
£
RTC_ISR_256HZ_IF_Msk (0x1U << RTC_ISR_256HZ_IF_Pos)
¦
RTC_ISR_64HZ_IF_Pos 8
©
RTC_ISR_64HZ_IF_Msk (0x1U << RTC_ISR_64HZ_IF_Pos)
¬
RTC_ISR_16HZ_IF_Pos 7
¯
RTC_ISR_16HZ_IF_Msk (0x1U << RTC_ISR_16HZ_IF_Pos)
±
RTC_ISR_8HZ_IF_Pos 6
´
RTC_ISR_8HZ_IF_Msk (0x1U << RTC_ISR_8HZ_IF_Pos)
¶
RTC_ISR_4HZ_IF_Pos 5
¹
RTC_ISR_4HZ_IF_Msk (0x1U << RTC_ISR_4HZ_IF_Pos)
»
RTC_ISR_2HZ_IF_Pos 4
¾
RTC_ISR_2HZ_IF_Msk (0x1U << RTC_ISR_2HZ_IF_Pos)
À
RTC_ISR_SEC_IF_Pos 3
Ã
RTC_ISR_SEC_IF_Msk (0x1U << RTC_ISR_SEC_IF_Pos)
Å
RTC_ISR_MIN_IF_Pos 2
È
RTC_ISR_MIN_IF_Msk (0x1U << RTC_ISR_MIN_IF_Pos)
Ê
RTC_ISR_HOUR_IF_Pos 1
Í
RTC_ISR_HOUR_IF_Msk (0x1U << RTC_ISR_HOUR_IF_Pos)
Ï
RTC_ISR_DATE_IF_Pos 0
Ò
RTC_ISR_DATE_IF_Msk (0x1U << RTC_ISR_DATE_IF_Pos)
Ô
RTC_BCDSEC_BCDSEC_Pos 0
Õ
RTC_BCDSEC_BCDSEC_Msk (0x7fU << RTC_BCDSEC_BCDSEC_Pos)
×
RTC_BCDMIN_BCDMIN_Pos 0
Ø
RTC_BCDMIN_BCDMIN_Msk (0x7fU << RTC_BCDMIN_BCDMIN_Pos)
Ú
RTC_BCDHOUR_BCDHOUR_Pos 0
Û
RTC_BCDHOUR_BCDHOUR_Msk (0x3fU << RTC_BCDHOUR_BCDHOUR_Pos)
Ý
RTC_BCDDATE_BCDDATE_Pos 0
Þ
RTC_BCDDATE_BCDDATE_Msk (0x3fU << RTC_BCDDATE_BCDDATE_Pos)
à
RTC_BCDWEEK_BCDWEEK_Pos 0
á
RTC_BCDWEEK_BCDWEEK_Msk (0x7U << RTC_BCDWEEK_BCDWEEK_Pos)
ã
RTC_BCDMONTH_BCDMONTH_Pos 0
ä
RTC_BCDMONTH_BCDMONTH_Msk (0x1fU << RTC_BCDMONTH_BCDMONTH_Pos)
æ
RTC_BCDYEAR_BCDYEAR_Pos 0
ç
RTC_BCDYEAR_BCDYEAR_Msk (0xffU << RTC_BCDYEAR_BCDYEAR_Pos)
é
RTC_ALARM_ALMEN_Pos 31
ì
RTC_ALARM_ALMEN_Msk (0x1U << RTC_ALARM_ALMEN_Pos)
ð
RTC_ALARM_ALARMHOUR_Pos 16
ñ
RTC_ALARM_ALARMHOUR_Msk (0x3fU << RTC_ALARM_ALARMHOUR_Pos)
ó
RTC_ALARM_ALARMMIN_Pos 8
ô
RTC_ALARM_ALARMMIN_Msk (0x7fU << RTC_ALARM_ALARMMIN_Pos)
ö
RTC_ALARM_ALARMSEC_Pos 0
÷
RTC_ALARM_ALARMSEC_Msk (0x7fU << RTC_ALARM_ALARMSEC_Pos)
ù
RTC_TMSEL_FSEL_Pos 0
ŠRTC_TMSEL_FSEL_Msk (0xfU << RTC_TMSEL_FSEL_Pos)
‹RTC_TMSEL_FSEL_PLL1HZ (0x0U << RTC_TMSEL_FSEL_Pos)
ŒRTC_TMSEL_FSEL_PLLD1HZ (0x1U << RTC_TMSEL_FSEL_Pos)
RTC_TMSEL_FSEL_SECOND (0x2U << RTC_TMSEL_FSEL_Pos)
ŽRTC_TMSEL_FSEL_MINUTE (0x3U << RTC_TMSEL_FSEL_Pos)
RTC_TMSEL_FSEL_HOUR (0x4U << RTC_TMSEL_FSEL_Pos)
RTC_TMSEL_FSEL_DAY (0x5U << RTC_TMSEL_FSEL_Pos)
‘RTC_TMSEL_FSEL_ALARM (0x6U << RTC_TMSEL_FSEL_Pos)
’RTC_TMSEL_FSEL_256S (0x7U << RTC_TMSEL_FSEL_Pos)
“RTC_TMSEL_FSEL_PLLD1HZREV (0x8U << RTC_TMSEL_FSEL_Pos)
”RTC_TMSEL_FSEL_SECONDREV (0x9U << RTC_TMSEL_FSEL_Pos)
•RTC_TMSEL_FSEL_MINUTEREV (0xaU << RTC_TMSEL_FSEL_Pos)
–RTC_TMSEL_FSEL_HOURREV (0xbU << RTC_TMSEL_FSEL_Pos)
—RTC_TMSEL_FSEL_DAYREV (0xcU << RTC_TMSEL_FSEL_Pos)
˜RTC_TMSEL_FSEL_ALARMREV (0xdU << RTC_TMSEL_FSEL_Pos)
™RTC_TMSEL_FSEL_PLL1HZREV (0xeU << RTC_TMSEL_FSEL_Pos)
šRTC_TMSEL_FSEL_SECONDRUN (0xfU << RTC_TMSEL_FSEL_Pos)
 RTC_ADJUST_ADJUST_Pos 0
¡RTC_ADJUST_ADJUST_Msk (0x1fffU << RTC_ADJUST_ADJUST_Pos)
£RTC_ADSIGN_ADSIGN_Pos 0
¦RTC_ADSIGN_ADSIGN_Msk (0x1U << RTC_ADSIGN_ADSIGN_Pos)
§RTC_ADSIGN_ADSIGN_INCREASE (0x0U << RTC_ADSIGN_ADSIGN_Pos)
¨RTC_ADSIGN_ADSIGN_DECREASE (0x1U << RTC_ADSIGN_ADSIGN_Pos)
ªRTC_VCAL_PR1SEN_Pos 0
­RTC_VCAL_PR1SEN_Msk (0x1U << RTC_VCAL_PR1SEN_Pos)
±RTC_MSCNT_MSCNT_Pos 0
µRTC_MSCNT_MSCNT_Msk (0xffU << RTC_MSCNT_MSCNT_Pos)
·RTC_CALSTEP_CALSTEP_Pos 0
»RTC_CALSTEP_CALSTEP_Msk (0x1U << RTC_CALSTEP_CALSTEP_Pos)
¼RTC_CALSTEP_CALSTEP_006PPM (0x2U << RTC_CALSTEP_CALSTEP_Pos)
½RTC_CALSTEP_CALSTEP_0119PPM (0x1U << RTC_CALSTEP_CALSTEP_Pos)
¾RTC_CALSTEP_CALSTEP_0238PPM (0x0U << RTC_CALSTEP_CALSTEP_Pos)
ÀRTC_ADCNT_ADJCNT_Pos 0
ÁRTC_ADCNT_ADJCNT_Msk (0x1ffU << RTC_ADCNT_ADJCNT_Pos)
ÃRTC_SSR_SSR_Pos 0
ÅRTC_SSR_SSR_Msk (0x3fU << RTC_SSR_SSR_Pos)
ÇRTC_SSA_SSAEN_Pos 7
ÊRTC_SSA_SSAEN_Msk (0x1U << RTC_SSA_SSAEN_Pos)
ÎRTC_SSA_SS_ALARM_Pos 0
ÐRTC_SSA_SS_ALARM_Msk (0x3fU << RTC_SSA_SS_ALARM_Pos)
ÒRTC_DTR_DUTY_Pos 0
ÓRTC_DTR_DUTY_Msk (0x1ffffffU << RTC_DTR_DUTY_Pos)
ÕRTC_CR_RTC_EN_Pos 0
ÚRTC_CR_RTC_EN_Msk (0x1U << RTC_CR_RTC_EN_Pos)`T
 




..\Drivers\..\Core\Include\fm33a0xxev_rtc.h
FM33A0XXEV.h

°

..\Drivers\fm33a0xxev_rtc.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM*©Year8
#Month8
#
Date8
#Hour8
#Minute8
#Second8
#Week8
#PRTC_TimeDateTypeDef½
#PRTC_StampTmieTypeDef½
#*“Hour8
#Minute8
#
Second8
#PRTC_AlarmTmieTypeDef`

+
Õ
Ö
×


__FM33A0XXEV_DBG_H 
DBG_CR_DBG_LPT_STOP_Pos 15
DBG_CR_DBG_LPT_STOP_Msk (0x1U << DBG_CR_DBG_LPT_STOP_Pos)
 DBG_CR_DBG_BST_STOP_Pos 14
#DBG_CR_DBG_BST_STOP_Msk (0x1U << DBG_CR_DBG_BST_STOP_Pos)
'DBG_CR_DBG_ET4_STOP_Pos 13
*DBG_CR_DBG_ET4_STOP_Msk (0x1U << DBG_CR_DBG_ET4_STOP_Pos)
.DBG_CR_DBG_ET3_STOP_Pos 12
1DBG_CR_DBG_ET3_STOP_Msk (0x1U << DBG_CR_DBG_ET3_STOP_Pos)
5DBG_CR_DBG_ET2_STOP_Pos 11
8DBG_CR_DBG_ET2_STOP_Msk (0x1U << DBG_CR_DBG_ET2_STOP_Pos)
<DBG_CR_DBG_ET1_STOP_Pos 10
?DBG_CR_DBG_ET1_STOP_Msk (0x1U << DBG_CR_DBG_ET1_STOP_Pos)
CDBG_CR_DBG_BT2_STOP_Pos 9
FDBG_CR_DBG_BT2_STOP_Msk (0x1U << DBG_CR_DBG_BT2_STOP_Pos)
JDBG_CR_DBG_BT1_STOP_Pos 8
MDBG_CR_DBG_BT1_STOP_Msk (0x1U << DBG_CR_DBG_BT1_STOP_Pos)
QDBG_CR_DBG_WWDT_STOP_Pos 1
TDBG_CR_DBG_WWDT_STOP_Msk (0x1U << DBG_CR_DBG_WWDT_STOP_Pos)
XDBG_CR_DBG_IWDT_STOP_Pos 0
[DBG_CR_DBG_IWDT_STOP_Msk (0x1U << DBG_CR_DBG_IWDT_STOP_Pos)
_DBG_HDFR_DABORT_ADDR_FLAG_Pos 6
bDBG_HDFR_DABORT_ADDR_FLAG_Msk (0x1U << DBG_HDFR_DABORT_ADDR_FLAG_Pos)
dDBG_HDFR_DABORT_RESP_FLAG_Pos 5
gDBG_HDFR_DABORT_RESP_FLAG_Msk (0x1U << DBG_HDFR_DABORT_RESP_FLAG_Pos)
iDBG_HDFR_SVCUNDEF_FLAG_Pos 4
nDBG_HDFR_SVCUNDEF_FLAG_Msk (0x1U << DBG_HDFR_SVCUNDEF_FLAG_Pos)
pDBG_HDFR_BKPT_FLAG_Pos 3
sDBG_HDFR_BKPT_FLAG_Msk (0x1U << DBG_HDFR_BKPT_FLAG_Pos)
uDBG_HDFR_TBIT_FLAG_Pos 2
xDBG_HDFR_TBIT_FLAG_Msk (0x1U << DBG_HDFR_TBIT_FLAG_Pos)
zDBG_HDFR_SPECIAL_OP_FLAG_Pos 1
}DBG_HDFR_SPECIAL_OP_FLAG_Msk (0x1U << DBG_HDFR_SPECIAL_OP_FLAG_Pos)
DBG_HDFR_HDF_REQUEST_FLAG_Pos 0
‚
DBG_HDFR_HDF_REQUEST_FLAG_Msk (0x1U << DBG_HDFR_HDF_REQUEST_FLAG_Pos)`T
 




..\Drivers\..\Core\Include\fm33a0xxev_dbg.h
FM33A0XXEV.h

¼
..\Drivers\fm33a0xxev_dbg.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM
Ù
Ú
Û


__FM33A0XXEV_SPI_H 
SPIx_CR1_IOSWAP_Pos 11
SPIx_CR1_IOSWAP_Msk (0x1U << SPIx_CR1_IOSWAP_Pos)
SPIx_CR1_IOSWAP_DEFAULT (0x0U << SPIx_CR1_IOSWAP_Pos)
 SPIx_CR1_IOSWAP_EXCHANGE (0x1U << SPIx_CR1_IOSWAP_Pos)
"SPIx_CR1_MSPA_Pos 10
%SPIx_CR1_MSPA_Msk (0x1U << SPIx_CR1_MSPA_Pos)
&SPIx_CR1_MSPA_DELAY (0x1U << SPIx_CR1_MSPA_Pos)
'SPIx_CR1_MSPA_NORMAL (0x0U << SPIx_CR1_MSPA_Pos)
)SPIx_CR1_SSPA_Pos 9
,SPIx_CR1_SSPA_Msk (0x1U << SPIx_CR1_SSPA_Pos)
-SPIx_CR1_SSPA_EARLY (0x1U << SPIx_CR1_SSPA_Pos)
.SPIx_CR1_SSPA_NORMAL (0x0U << SPIx_CR1_SSPA_Pos)
0SPIx_CR1_MM_Pos 8
1SPIx_CR1_MM_Msk (0x1U << SPIx_CR1_MM_Pos)
2SPIx_CR1_MM_MASTER (0x1U << SPIx_CR1_MM_Pos)
3SPIx_CR1_MM_SLAVE (0x0U << SPIx_CR1_MM_Pos)
5SPIx_CR1_WAIT_Pos 6
6SPIx_CR1_WAIT_Msk (0x3U << SPIx_CR1_WAIT_Pos)
7SPIx_CR1_WAIT_1WAIT (0x0U << SPIx_CR1_WAIT_Pos)
8SPIx_CR1_WAIT_2WAIT (0x1U << SPIx_CR1_WAIT_Pos)
9SPIx_CR1_WAIT_3WAIT (0x2U << SPIx_CR1_WAIT_Pos)
:SPIx_CR1_WAIT_4WAIT (0x3U << SPIx_CR1_WAIT_Pos)
<SPIx_CR1_BAUD_Pos 3
=SPIx_CR1_BAUD_Msk (0x7U << SPIx_CR1_BAUD_Pos)
>SPIx_CR1_BAUD_DIV2 (0x0U << SPIx_CR1_BAUD_Pos)
?SPIx_CR1_BAUD_DIV4 (0x1U << SPIx_CR1_BAUD_Pos)
@SPIx_CR1_BAUD_DIV8 (0x2U << SPIx_CR1_BAUD_Pos)
ASPIx_CR1_BAUD_DIV16 (0x3U << SPIx_CR1_BAUD_Pos)
BSPIx_CR1_BAUD_DIV32 (0x4U << SPIx_CR1_BAUD_Pos)
CSPIx_CR1_BAUD_DIV64 (0x5U << SPIx_CR1_BAUD_Pos)
DSPIx_CR1_BAUD_DIV128 (0x6U << SPIx_CR1_BAUD_Pos)
ESPIx_CR1_BAUD_DIV256 (0x7U << SPIx_CR1_BAUD_Pos)
GSPIx_CR1_LSBF_Pos 2
HSPIx_CR1_LSBF_Msk (0x1U << SPIx_CR1_LSBF_Pos)
ISPIx_CR1_LSBF_MSB (0x0U << SPIx_CR1_LSBF_Pos)
JSPIx_CR1_LSBF_LSB (0x1U << SPIx_CR1_LSBF_Pos)
LSPIx_CR1_CPHOL_Pos 1
MSPIx_CR1_CPHOL_Msk (0x1U << SPIx_CR1_CPHOL_Pos)
NSPIx_CR1_CPHOL_LOW (0x0U << SPIx_CR1_CPHOL_Pos)
OSPIx_CR1_CPHOL_HIGH (0x1U << SPIx_CR1_CPHOL_Pos)
QSPIx_CR1_CPHA_Pos 0
RSPIx_CR1_CPHA_Msk (0x1U << SPIx_CR1_CPHA_Pos)
SSPIx_CR1_CPHA_1CLOCK (0x0U << SPIx_CR1_CPHA_Pos)
TSPIx_CR1_CPHA_2CLOCK (0x1U << SPIx_CR1_CPHA_Pos)
VSPIx_CR2_DUMMY_EN_Pos 15
ZSPIx_CR2_DUMMY_EN_Msk (0x1U << SPIx_CR2_DUMMY_EN_Pos)
^SPIx_CR2_RXO_Pos 11
aSPIx_CR2_RXO_Msk (0x1U << SPIx_CR2_RXO_Pos)
eSPIx_CR2_DLEN_Pos 9
jSPIx_CR2_DLEN_Msk (0x3U << SPIx_CR2_DLEN_Pos)
kSPIx_CR2_DLEN_8BIT (0x0U << SPIx_CR2_DLEN_Pos)
lSPIx_CR2_DLEN_16BIT (0x1U << SPIx_CR2_DLEN_Pos)
mSPIx_CR2_DLEN_24BIT (0x2U << SPIx_CR2_DLEN_Pos)
nSPIx_CR2_DLEN_32BIT (0x3U << SPIx_CR2_DLEN_Pos)
pSPIx_CR2_HALFDUPLEX_Pos 8
sSPIx_CR2_HALFDUPLEX_Msk (0x1U << SPIx_CR2_HALFDUPLEX_Pos)
tSPIx_CR2_HALFDUPLEX_SPI (0x0U << SPIx_CR2_HALFDUPLEX_Pos)
uSPIx_CR2_HALFDUPLEX_DCN (0x1U << SPIx_CR2_HALFDUPLEX_Pos)
wSPIx_CR2_HD_RW_Pos 7
zSPIx_CR2_HD_RW_Msk (0x1U << SPIx_CR2_HD_RW_Pos)
{SPIx_CR2_HD_RW_WRITE (0x0U << SPIx_CR2_HD_RW_Pos)
|SPIx_CR2_HD_RW_READ (0x1U << SPIx_CR2_HD_RW_Pos)
~SPIx_CR2_CMD8b_Pos 6

SPIx_CR2_CMD8b_Msk (0x1U << SPIx_CR2_CMD8b_Pos)
‚
SPIx_CR2_CMD8b_8BIT (0x1U << SPIx_CR2_CMD8b_Pos)
ƒ
SPIx_CR2_CMD8b_DLEN (0x0U << SPIx_CR2_CMD8b_Pos)
…
SPIx_CR2_SSNM_Pos 5
ˆ
SPIx_CR2_SSNM_Msk (0x1U << SPIx_CR2_SSNM_Pos)
‰
SPIx_CR2_SSNM_HIGH (0x1U << SPIx_CR2_SSNM_Pos)
Š
SPIx_CR2_SSNM_LOW (0x0U << SPIx_CR2_SSNM_Pos)
Œ
SPIx_CR2_TXO_AC_Pos 4

SPIx_CR2_TXO_AC_Msk (0x1U << SPIx_CR2_TXO_AC_Pos)

SPIx_CR2_TXO_Pos 3
’
SPIx_CR2_TXO_Msk (0x1U << SPIx_CR2_TXO_Pos)
–
SPIx_CR2_SSN_Pos 2
˜
SPIx_CR2_SSN_Msk (0x1U << SPIx_CR2_SSN_Pos)
™
SPIx_CR2_SSN_LOW (0x0U << SPIx_CR2_SSN_Pos)
š
SPIx_CR2_SSN_HIGH (0x1U << SPIx_CR2_SSN_Pos)
œ
SPIx_CR2_SSNSEN_Pos 1
Ÿ
SPIx_CR2_SSNSEN_Msk (0x1U << SPIx_CR2_SSNSEN_Pos)
£
SPIx_CR2_SPIEN_Pos 0
¤
SPIx_CR2_SPIEN_Msk (0x1U << SPIx_CR2_SPIEN_Pos)
¦
SPIx_CR3_TXBFC_Pos 3
§
SPIx_CR3_TXBFC_Msk (0x1U << SPIx_CR3_TXBFC_Pos)
©
SPIx_CR3_RXBFC_Pos 2
ª
SPIx_CR3_RXBFC_Msk (0x1U << SPIx_CR3_RXBFC_Pos)
¬
SPIx_CR3_MERRC_Pos 1
­
SPIx_CR3_MERRC_Msk (0x1U << SPIx_CR3_MERRC_Pos)
¯
SPIx_CR3_SERRC_Pos 0
°
SPIx_CR3_SERRC_Msk (0x1U << SPIx_CR3_SERRC_Pos)
²
SPIx_IER_ERRIE_Pos 2
³
SPIx_IER_ERRIE_Msk (0x1U << SPIx_IER_ERRIE_Pos)
µ
SPIx_IER_TXIE_Pos 1
¶
SPIx_IER_TXIE_Msk (0x1U << SPIx_IER_TXIE_Pos)
¸
SPIx_IER_RXIE_Pos 0
¹
SPIx_IER_RXIE_Msk (0x1U << SPIx_IER_RXIE_Pos)
»
SPIx_ISR_DCN_TX_Pos 12
¿
SPIx_ISR_DCN_TX_Msk (0x1U << SPIx_ISR_DCN_TX_Pos)
À
SPIx_ISR_DCN_TX_COMMAND (0x0U << SPIx_ISR_DCN_TX_Pos)
Á
SPIx_ISR_DCN_TX_DATA (0x1U << SPIx_ISR_DCN_TX_Pos)
Ã
SPIx_ISR_RXCOL_Pos 10
Ä
SPIx_ISR_RXCOL_Msk (0x1U << SPIx_ISR_RXCOL_Pos)
Æ
SPIx_ISR_TXCOL_Pos 9
Ç
SPIx_ISR_TXCOL_Msk (0x1U << SPIx_ISR_TXCOL_Pos)
É
SPIx_ISR_BUSY_Pos 8
Ì
SPIx_ISR_BUSY_Msk (0x1U << SPIx_ISR_BUSY_Pos)
Î
SPIx_ISR_MERR_Pos 6
Ð
SPIx_ISR_MERR_Msk (0x1U << SPIx_ISR_MERR_Pos)
Ò
SPIx_ISR_SERR_Pos 5
Ô
SPIx_ISR_SERR_Msk (0x1U << SPIx_ISR_SERR_Pos)
Ö
SPIx_ISR_TXBE_Pos 1
Ù
SPIx_ISR_TXBE_Msk (0x1U << SPIx_ISR_TXBE_Pos)
Û
SPIx_ISR_RXBF_Pos 0
Þ
SPIx_ISR_RXBF_Msk (0x1U << SPIx_ISR_RXBF_Pos)
à
SPIx_TXBUF_TXBUF_Pos 0
á
SPIx_TXBUF_TXBUF_Msk (0xffffffffU << SPIx_TXBUF_TXBUF_Pos)
ã
SPIx_RXBUF_RXBUF_Pos 0
ä
SPIx_RXBUF_RXBUF_Msk (0xffffffffU << SPIx_RXBUF_RXBUF_Pos)`T
 




..\Drivers\..\Core\Include\fm33a0xxev_spi.h
FM33A0XXEV.h

¼
..\Drivers\fm33a0xxev_spi.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM
Ý
Þ
ß


__FM33A0XXEV_RNG_H 
RNG_CR_EN_Pos 0
RNG_CR_EN_Msk (0x1U << RNG_CR_EN_Pos)
 RNG_DOR_OUT_Pos 0
"RNG_DOR_OUT_Msk (0xffffffffU << RNG_DOR_OUT_Pos)
$RNG_SR_LFSREN_Pos 1
(RNG_SR_LFSREN_Msk (0x1U << RNG_SR_LFSREN_Pos)
-RNG_SR_RNF_Pos 0
0RNG_SR_RNF_Msk (0x1U << RNG_SR_RNF_Pos)
2RNG_CRC_CR_CRCEN_Pos 0
5RNG_CRC_CR_CRCEN_Msk (0x1U << RNG_CRC_CR_CRCEN_Pos)
9RNG_CRC_DIR_CRCIN_Pos 0
:RNG_CRC_DIR_CRCIN_Msk (0xffffffffU << RNG_CRC_DIR_CRCIN_Pos)
<RNG_CRC_SR_CRCDONE_Pos 0
?RNG_CRC_SR_CRCDONE_Msk (0x1U << RNG_CRC_SR_CRCDONE_Pos)`T
 




..\Drivers\..\Core\Include\fm33a0xxev_rng.h
FM33A0XXEV.h

¼
..\Drivers\fm33a0xxev_rng.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM
á
â
ã


__FM33A0XXEV_U7816_H 
7U7816_CR_TXEN_Pos 5
8U7816_CR_TXEN_Msk (0x1U << U7816_CR_TXEN_Pos)
:U7816_CR_RXEN_Pos 4
;U7816_CR_RXEN_Msk (0x1U << U7816_CR_RXEN_Pos)
=U7816_CR_CKOEN_Pos 3
>U7816_CR_CKOEN_Msk (0x1U << U7816_CR_CKOEN_Pos)
@U7816_CR_HPUAT_Pos 2
AU7816_CR_HPUAT_Msk (0x1U << U7816_CR_HPUAT_Pos)
CU7816_CR_HPUEN_Pos 1
DU7816_CR_HPUEN_Msk (0x1U << U7816_CR_HPUEN_Pos)
FU7816_FFR_SFREN_Pos 11
GU7816_FFR_SFREN_Msk (0x1U << U7816_FFR_SFREN_Pos)
HU7816_FFR_SFREN_3ETU (0x1U << U7816_FFR_SFREN_Pos)
IU7816_FFR_SFREN_2ETU (0x0U << U7816_FFR_SFREN_Pos)
KU7816_FFR_ERSW_Pos 9
LU7816_FFR_ERSW_Msk (0x3U << U7816_FFR_ERSW_Pos)
MU7816_FFR_ERSW_1ETU (0x0U << U7816_FFR_ERSW_Pos)
NU7816_FFR_ERSW_1P5ETU (0x1U << U7816_FFR_ERSW_Pos)
OU7816_FFR_ERSW_2ETU (0x2U << U7816_FFR_ERSW_Pos)
QU7816_FFR_ERSGD_Pos 8
SU7816_FFR_ERSGD_Msk (0x1U << U7816_FFR_ERSGD_Pos)
TU7816_FFR_ERSGD_1ETU (0x1U << U7816_FFR_ERSGD_Pos)
UU7816_FFR_ERSGD_2ETU (0x0U << U7816_FFR_ERSGD_Pos)
WU7816_FFR_BGTEN_Pos 7
XU7816_FFR_BGTEN_Msk (0x1U << U7816_FFR_BGTEN_Pos)
ZU7816_FFR_REP_T_Pos 6
[U7816_FFR_REP_T_Msk (0x1U << U7816_FFR_REP_T_Pos)
\U7816_FFR_REP_T_1TIMES (0x0U << U7816_FFR_REP_T_Pos)
]U7816_FFR_REP_T_3TIMES (0x1U << U7816_FFR_REP_T_Pos)
_U7816_FFR_PAR_Pos 4
`U7816_FFR_PAR_Msk (0x3U << U7816_FFR_PAR_Pos)
aU7816_FFR_PAR_EVEN (0x0U << U7816_FFR_PAR_Pos)
bU7816_FFR_PAR_ODD (0x1U << U7816_FFR_PAR_Pos)
cU7816_FFR_PAR_1ALAWAYS (0x2U << U7816_FFR_PAR_Pos)
dU7816_FFR_PAR_NON (0x3U << U7816_FFR_PAR_Pos)
fU7816_FFR_RFREN_Pos 3
gU7816_FFR_RFREN_Msk (0x1U << U7816_FFR_RFREN_Pos)
hU7816_FFR_RFREN_1ETU (0x1U << U7816_FFR_RFREN_Pos)
iU7816_FFR_RFREN_2ETU (0x0U << U7816_FFR_RFREN_Pos)
kU7816_FFR_TREPEN_Pos 2
lU7816_FFR_TREPEN_Msk (0x1U << U7816_FFR_TREPEN_Pos)
nU7816_FFR_RREPEN_Pos 1
oU7816_FFR_RREPEN_Msk (0x1U << U7816_FFR_RREPEN_Pos)
qU7816_FFR_DICONV_Pos 0
rU7816_FFR_DICONV_Msk (0x1U << U7816_FFR_DICONV_Pos)
sU7816_FFR_DICONV_FORWARD (0x0U << U7816_FFR_DICONV_Pos)
tU7816_FFR_DICONV_REVERSE (0x1U << U7816_FFR_DICONV_Pos)
vU7816_EGTR_TXEGT_Pos 0
xU7816_EGTR_TXEGT_Msk (0xffU << U7816_EGTR_TXEGT_Pos)
zU7816_PSC_CLKDIV_Pos 0
{U7816_PSC_CLKDIV_Msk (0x1fU << U7816_PSC_CLKDIV_Pos)
}U7816_BGR_PDIV_Pos 0
€
U7816_BGR_PDIV_Msk (0xfffU << U7816_BGR_PDIV_Pos)
‚
U7816_RXBUF_RXBUF_Pos 0
ƒ
U7816_RXBUF_RXBUF_Msk (0xffU << U7816_RXBUF_RXBUF_Pos)
…
U7816_TXBUF_TXBUF_Pos 0
†
U7816_TXBUF_TXBUF_Msk (0xffU << U7816_TXBUF_TXBUF_Pos)
ˆ
U7816_IER_RXIE_Pos 2
‰
U7816_IER_RXIE_Msk (0x1U << U7816_IER_RXIE_Pos)
‹
U7816_IER_TXIE_Pos 1
Œ
U7816_IER_TXIE_Msk (0x1U << U7816_IER_TXIE_Pos)
Ž
U7816_IER_LSIE_Pos 0

U7816_IER_LSIE_Msk (0x1U << U7816_IER_LSIE_Pos)
‘
U7816_ISR_WAIT_RPT_Pos 18
’
U7816_ISR_WAIT_RPT_Msk (0x1U << U7816_ISR_WAIT_RPT_Pos)
”
U7816_ISR_TXBUSY_Pos 17
•
U7816_ISR_TXBUSY_Msk (0x1U << U7816_ISR_TXBUSY_Pos)
—
U7816_ISR_RXBUSY_Pos 16
˜
U7816_ISR_RXBUSY_Msk (0x1U << U7816_ISR_RXBUSY_Pos)
š
U7816_ISR_TPARERR_Pos 11
›
U7816_ISR_TPARERR_Msk (0x1U << U7816_ISR_TPARERR_Pos)

U7816_ISR_RPARERR_Pos 10
ž
U7816_ISR_RPARERR_Msk (0x1U << U7816_ISR_RPARERR_Pos)
 
U7816_ISR_FRERR_Pos 9
¡
U7816_ISR_FRERR_Msk (0x1U << U7816_ISR_FRERR_Pos)
£
U7816_ISR_OVERR_Pos 8
¤
U7816_ISR_OVERR_Msk (0x1U << U7816_ISR_OVERR_Pos)
¦
U7816_ISR_RXIF_Pos 2
§
U7816_ISR_RXIF_Msk (0x1U << U7816_ISR_RXIF_Pos)
©
U7816_ISR_TXIF_Pos 1
ª
U7816_ISR_TXIF_Msk (0x1U << U7816_ISR_TXIF_Pos)
¬
U7816_ISR_ERRIF_Pos 0
­
U7816_ISR_ERRIF_Msk (0x1U << U7816_ISR_ERRIF_Pos)`V
 




..\Drivers\..\Core\Include\fm33a0xxev_u7816.h
FM33A0XXEV.h


..\Drivers\fm33a0xxev_u7816.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM*ú8TXEN
#RXEN
#
CKOEN
#HPUAT
#HPUEN
#ERSWf
#ERSGDf
#BGTEN
#REP_Tf
#PARf
#SFRENf
#RFRENf
# TREPEN
#$RREPEN
#%DICONV
#&TXEGTf
#(CLKDIVf
#,PDIVf
#0RXIE
#4TXIE
#5LSIE
#6PU7816_InitTypeDef¿
4
å
æ
ç


__FM33A0XXEV_UART_H 
OUARTIR_CR_IRFLAG_Pos 15
RUARTIR_CR_IRFLAG_Msk (0x1U << UARTIR_CR_IRFLAG_Pos)
SUARTIR_CR_IRFLAG_POSITIVE (0x0U << UARTIR_CR_IRFLAG_Pos)
TUARTIR_CR_IRFLAG_NEGTIVE (0x1U << UARTIR_CR_IRFLAG_Pos)
VUARTIR_CR_TH_Pos 11
WUARTIR_CR_TH_Msk (0xfU << UARTIR_CR_TH_Pos)
YUARTIR_CR_TZBRG_Pos 0
ZUARTIR_CR_TZBRG_Msk (0x7ffU << UARTIR_CR_TZBRG_Pos)
\UARTx_CSR_BUSY_Pos 24
_UARTx_CSR_BUSY_Msk (0x1U << UARTx_CSR_BUSY_Pos)
aUARTx_CSR_TXIREN_Pos 17
dUARTx_CSR_TXIREN_Msk (0x1U << UARTx_CSR_TXIREN_Pos)
hUARTx_CSR_RXTOEN_Pos 16
kUARTx_CSR_RXTOEN_Msk (0x1U << UARTx_CSR_RXTOEN_Pos)
oUARTx_CSR_IOSWAP_Pos 12
rUARTx_CSR_IOSWAP_Msk (0x1U << UARTx_CSR_IOSWAP_Pos)
sUARTx_CSR_IOSWAP_DEFAULT (0x0U << UARTx_CSR_IOSWAP_Pos)
tUARTx_CSR_IOSWAP_EXCHANGE (0x1U << UARTx_CSR_IOSWAP_Pos)
vUARTx_CSR_DMATXIFCFG_Pos 10
yUARTx_CSR_DMATXIFCFG_Msk (0x1U << UARTx_CSR_DMATXIFCFG_Pos)
}UARTx_CSR_BITORD_Pos 9
€
UARTx_CSR_BITORD_Msk (0x1U << UARTx_CSR_BITORD_Pos)

UARTx_CSR_BITORD_LSB (0x0U << UARTx_CSR_BITORD_Pos)
‚
UARTx_CSR_BITORD_MSB (0x1U << UARTx_CSR_BITORD_Pos)
„
UARTx_CSR_STOPCFG_Pos 8
‡
UARTx_CSR_STOPCFG_Msk (0x1U << UARTx_CSR_STOPCFG_Pos)
ˆ
UARTx_CSR_STOPCFG_1STOPBIT (0x0U << UARTx_CSR_STOPCFG_Pos)
‰
UARTx_CSR_STOPCFG_2STOPBIT (0x1U << UARTx_CSR_STOPCFG_Pos)
‹
UARTx_CSR_PDSEL_Pos 6

UARTx_CSR_PDSEL_Msk (0x3U << UARTx_CSR_PDSEL_Pos)
‘
UARTx_CSR_PDSEL_7BIT (0x0U << UARTx_CSR_PDSEL_Pos)
’
UARTx_CSR_PDSEL_8BIT (0x1U << UARTx_CSR_PDSEL_Pos)
“
UARTx_CSR_PDSEL_9BIT (0x2U << UARTx_CSR_PDSEL_Pos)
”
UARTx_CSR_PDSEL_6BIT (0x3U << UARTx_CSR_PDSEL_Pos)
–
UARTx_CSR_PARITY_Pos 4
›
UARTx_CSR_PARITY_Msk (0x3U << UARTx_CSR_PARITY_Pos)
œ
UARTx_CSR_PARITY_NONE (0x0U << UARTx_CSR_PARITY_Pos)

UARTx_CSR_PARITY_EVEN (0x1U << UARTx_CSR_PARITY_Pos)
ž
UARTx_CSR_PARITY_ODD (0x2U << UARTx_CSR_PARITY_Pos)
 
UARTx_CSR_RXPOL_Pos 3
£
UARTx_CSR_RXPOL_Msk (0x1U << UARTx_CSR_RXPOL_Pos)
¤
UARTx_CSR_RXPOL_POSITIVE (0x0U << UARTx_CSR_RXPOL_Pos)
¥
UARTx_CSR_RXPOL_NEGTIVE (0x1U << UARTx_CSR_RXPOL_Pos)
§
UARTx_CSR_TXPOL_Pos 2
ª
UARTx_CSR_TXPOL_Msk (0x1U << UARTx_CSR_TXPOL_Pos)
«
UARTx_CSR_TXPOL_POSITIVE (0x0U << UARTx_CSR_TXPOL_Pos)
¬
UARTx_CSR_TXPOL_NEGTIVE (0x1U << UARTx_CSR_TXPOL_Pos)
®
UARTx_CSR_RXEN_Pos 1
¯
UARTx_CSR_RXEN_Msk (0x1U << UARTx_CSR_RXEN_Pos)
°
UARTx_CSR_RXEN_DISBALE (0x0U << UARTx_CSR_RXEN_Pos)
±
UARTx_CSR_RXEN_ENABLE (0x1U << UARTx_CSR_RXEN_Pos)
³
UARTx_CSR_TXEN_Pos 0
´
UARTx_CSR_TXEN_Msk (0x1U << UARTx_CSR_TXEN_Pos)
µ
UARTx_CSR_TXEN_DISBALE (0x0U << UARTx_CSR_TXEN_Pos)
¶
UARTx_CSR_TXEN_ENABLE (0x1U << UARTx_CSR_TXEN_Pos)
¸
UARTx_IER_RXTO_IE_Pos 11
º
UARTx_IER_RXTO_IE_Msk (0x1U << UARTx_IER_RXTO_IE_Pos)
¼
UARTx_IER_RXERR_IE_Pos 10
½
UARTx_IER_RXERR_IE_Msk (0x1U << UARTx_IER_RXERR_IE_Pos)
¿
UARTx_IER_RXBF_IE_Pos 8
À
UARTx_IER_RXBF_IE_Msk (0x1U << UARTx_IER_RXBF_IE_Pos)
Â
UARTx_IER_NEWUP_IE_Pos 7
Ã
UARTx_IER_NEWUP_IE_Msk (0x1U << UARTx_IER_NEWUP_IE_Pos)
Å
UARTx_IER_TXBE_IE_Pos 1
Æ
UARTx_IER_TXBE_IE_Msk (0x1U << UARTx_IER_TXBE_IE_Pos)
È
UARTx_IER_TXSE_IE_Pos 0
É
UARTx_IER_TXSE_IE_Msk (0x1U << UARTx_IER_TXSE_IE_Pos)
Ë
UARTx_ISR_PERR_Pos 18
Ì
UARTx_ISR_PERR_Msk (0x1U << UARTx_ISR_PERR_Pos)
Î
UARTx_ISR_FERR_Pos 17
Ï
UARTx_ISR_FERR_Msk (0x1U << UARTx_ISR_FERR_Pos)
Ñ
UARTx_ISR_OERR_Pos 16
Ó
UARTx_ISR_OERR_Msk (0x1U << UARTx_ISR_OERR_Pos)
Õ
UARTx_ISR_RXTO_Pos 11
×
UARTx_ISR_RXTO_Msk (0x1U << UARTx_ISR_RXTO_Pos)
Ù
UARTx_ISR_RXBF_Pos 8
Ú
UARTx_ISR_RXBF_Msk (0x1U << UARTx_ISR_RXBF_Pos)
Ü
UARTx_ISR_TXBE_Pos 1
Ý
UARTx_ISR_TXBE_Msk (0x1U << UARTx_ISR_TXBE_Pos)
ß
UARTx_ISR_TXSE_Pos 0
à
UARTx_ISR_TXSE_Msk (0x1U << UARTx_ISR_TXSE_Pos)
â
UARTx_TODR_TXDLY_LEN_Pos 8
ã
UARTx_TODR_TXDLY_LEN_Msk (0xffU << UARTx_TODR_TXDLY_LEN_Pos)
å
UARTx_TODR_RXTO_LEN_Pos 0
æ
UARTx_TODR_RXTO_LEN_Msk (0xffU << UARTx_TODR_RXTO_LEN_Pos)
è
UARTx_RXBUF_RXBUF_Pos 0
é
UARTx_RXBUF_RXBUF_Msk (0x1ffU << UARTx_RXBUF_RXBUF_Pos)
ë
UARTx_TXBUF_TXBUF_Pos 0
ì
UARTx_TXBUF_TXBUF_Msk (0x1ffU << UARTx_TXBUF_TXBUF_Pos)
î
UARTx_BRG_SPBRG_Pos 0
ï
UARTx_BRG_SPBRG_Msk (0xffffU << UARTx_BRG_SPBRG_Pos)ti
 




..\Drivers\..\Core\Include\fm33a0xxev_uart.h
FM33A0XXEV.hfm33a0xxev_CMU.h



..\Drivers\fm33a0xxev_uart.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMÕ

RxIntTxInt
PUART_IntTypeDef¾
¢
Seven7BitEight8Bit
Nine9BitSix6BitPUART_DataBitTypeDefì
%Ù
NONEEVEN
ODDPUART_ParityBitTypeDef=

,
OneBitTwoBit
PUART_StopBitTypeDefv

2*‚BaudRatef
#DataBit"
#ParityBitY
#StopBit
#ClockSrcf
#PUART_SInitTypeDefª

;*þRXBF_IE
#TXBE_IE
#
TXSE_IE
#SPBRGf
#PDSELf
#PARITYf
#RXTO_IE
#ERRIE
#RXEN
#STOPSELf
#TXEN
#IREN
#RXDFLAG
#TXDFLAG
#PUART_InitTypeDef
M
é
ê
ë


__FM33A0XXEV_LPTIM_H 
LPTIM_CFGR_ETR_AFEN_Pos 24
LPTIM_CFGR_ETR_AFEN_Msk (0x1U << LPTIM_CFGR_ETR_AFEN_Pos)
 LPTIM_CFGR_PSCSEL_Pos 14
#LPTIM_CFGR_PSCSEL_Msk (0x1U << LPTIM_CFGR_PSCSEL_Pos)
$LPTIM_CFGR_PSCSEL_CLKSEL (0x0U << LPTIM_CFGR_PSCSEL_Pos)
%LPTIM_CFGR_PSCSEL_LPTETRF (0x1U << LPTIM_CFGR_PSCSEL_Pos)
'LPTIM_CFGR_DIVSEL_Pos 10
0LPTIM_CFGR_DIVSEL_Msk (0x7U << LPTIM_CFGR_DIVSEL_Pos)
1LPTIM_CFGR_DIVSEL_DIV1 (0x0U << LPTIM_CFGR_DIVSEL_Pos)
2LPTIM_CFGR_DIVSEL_DIV2 (0x1U << LPTIM_CFGR_DIVSEL_Pos)
3LPTIM_CFGR_DIVSEL_DIV4 (0x2U << LPTIM_CFGR_DIVSEL_Pos)
4LPTIM_CFGR_DIVSEL_DIV8 (0x3U << LPTIM_CFGR_DIVSEL_Pos)
5LPTIM_CFGR_DIVSEL_DIV16 (0x4U << LPTIM_CFGR_DIVSEL_Pos)
6LPTIM_CFGR_DIVSEL_DIV32 (0x5U << LPTIM_CFGR_DIVSEL_Pos)
7LPTIM_CFGR_DIVSEL_DIV64 (0x6U << LPTIM_CFGR_DIVSEL_Pos)
8LPTIM_CFGR_DIVSEL_DIV128 (0x7U << LPTIM_CFGR_DIVSEL_Pos)
:LPTIM_CFGR_EDGESEL_Pos 7
=LPTIM_CFGR_EDGESEL_Msk (0x1U << LPTIM_CFGR_EDGESEL_Pos)
>LPTIM_CFGR_EDGESEL_RISING (0x0U << LPTIM_CFGR_EDGESEL_Pos)
?LPTIM_CFGR_EDGESEL_FALLING (0x1U << LPTIM_CFGR_EDGESEL_Pos)
ALPTIM_CFGR_TRIGCFG_Pos 5
ELPTIM_CFGR_TRIGCFG_Msk (0x3U << LPTIM_CFGR_TRIGCFG_Pos)
FLPTIM_CFGR_TRIGCFG_RISING (0x0U << LPTIM_CFGR_TRIGCFG_Pos)
GLPTIM_CFGR_TRIGCFG_FALLING (0x1U << LPTIM_CFGR_TRIGCFG_Pos)
HLPTIM_CFGR_TRIGCFG_EXTERNAL (0x2U << LPTIM_CFGR_TRIGCFG_Pos)
JLPTIM_CFGR_ONST_Pos 2
MLPTIM_CFGR_ONST_Msk (0x1U << LPTIM_CFGR_ONST_Pos)
NLPTIM_CFGR_ONST_CONTINUE (0x0U << LPTIM_CFGR_ONST_Pos)
OLPTIM_CFGR_ONST_SINGLE (0x1U << LPTIM_CFGR_ONST_Pos)
QLPTIM_CFGR_TMODE_Pos 0
VLPTIM_CFGR_TMODE_Msk (0x3U << LPTIM_CFGR_TMODE_Pos)
WLPTIM_CFGR_TMODE_COUNTER (0x0U << LPTIM_CFGR_TMODE_Pos)
XLPTIM_CFGR_TMODE_PULSE (0x1U << LPTIM_CFGR_TMODE_Pos)
YLPTIM_CFGR_TMODE_ASY (0x2U << LPTIM_CFGR_TMODE_Pos)
ZLPTIM_CFGR_TMODE_TIMEOUT (0x3U << LPTIM_CFGR_TMODE_Pos)
\LPTIM_CNTR_CNT32_Pos 0
]LPTIM_CNTR_CNT32_Msk (0xffffffffU << LPTIM_CNTR_CNT32_Pos)
_LPTIM_CCSR_CAP1SSEL_Pos 24
dLPTIM_CCSR_CAP1SSEL_Msk (0x3U << LPTIM_CCSR_CAP1SSEL_Pos)
eLPTIM_CCSR_CAP1SSEL_LPT_CH1 (0x0U << LPTIM_CCSR_CAP1SSEL_Pos)
fLPTIM_CCSR_CAP1SSEL_XTLF (0x1U << LPTIM_CCSR_CAP1SSEL_Pos)
gLPTIM_CCSR_CAP1SSEL_RCLP (0x2U << LPTIM_CCSR_CAP1SSEL_Pos)
hLPTIM_CCSR_CAP1SSEL_RCMF (0x3U << LPTIM_CCSR_CAP1SSEL_Pos)
jLPTIM_CCSR_CAP4EDGE_Pos 23
mLPTIM_CCSR_CAP4EDGE_Msk (0x1U << LPTIM_CCSR_CAP4EDGE_Pos)
nLPTIM_CCSR_CAP4EDGE_RISING (0x0U << LPTIM_CCSR_CAP4EDGE_Pos)
oLPTIM_CCSR_CAP4EDGE_FALLING (0x1U << LPTIM_CCSR_CAP4EDGE_Pos)
qLPTIM_CCSR_CAP3EDGE_Pos 22
rLPTIM_CCSR_CAP3EDGE_Msk (0x1U << LPTIM_CCSR_CAP3EDGE_Pos)
sLPTIM_CCSR_CAP3EDGE_RISING (0x0U << LPTIM_CCSR_CAP3EDGE_Pos)
tLPTIM_CCSR_CAP3EDGE_FALLING (0x1U << LPTIM_CCSR_CAP3EDGE_Pos)
vLPTIM_CCSR_CAP2EDGE_Pos 21
wLPTIM_CCSR_CAP2EDGE_Msk (0x1U << LPTIM_CCSR_CAP2EDGE_Pos)
xLPTIM_CCSR_CAP2EDGE_RISING (0x0U << LPTIM_CCSR_CAP2EDGE_Pos)
yLPTIM_CCSR_CAP2EDGE_FALLING (0x1U << LPTIM_CCSR_CAP2EDGE_Pos)
{LPTIM_CCSR_CAP1EDGE_Pos 20
|LPTIM_CCSR_CAP1EDGE_Msk (0x1U << LPTIM_CCSR_CAP1EDGE_Pos)
}LPTIM_CCSR_CAP1EDGE_RISING (0x0U << LPTIM_CCSR_CAP1EDGE_Pos)
~LPTIM_CCSR_CAP1EDGE_FALLING (0x1U << LPTIM_CCSR_CAP1EDGE_Pos)
€
LPTIM_CCSR_POLAR4_Pos 19
ƒ
LPTIM_CCSR_POLAR4_Msk (0x1U << LPTIM_CCSR_POLAR4_Pos)
„
LPTIM_CCSR_POLAR4_POS (0x0U << LPTIM_CCSR_POLAR4_Pos)
…
LPTIM_CCSR_POLAR4_NEG (0x1U << LPTIM_CCSR_POLAR4_Pos)
‡
LPTIM_CCSR_POLAR3_Pos 18
ˆ
LPTIM_CCSR_POLAR3_Msk (0x1U << LPTIM_CCSR_POLAR3_Pos)
‰
LPTIM_CCSR_POLAR3_POS (0x0U << LPTIM_CCSR_POLAR3_Pos)
Š
LPTIM_CCSR_POLAR3_NEG (0x1U << LPTIM_CCSR_POLAR3_Pos)
Œ
LPTIM_CCSR_POLAR2_Pos 17

LPTIM_CCSR_POLAR2_Msk (0x1U << LPTIM_CCSR_POLAR2_Pos)
Ž
LPTIM_CCSR_POLAR2_POS (0x0U << LPTIM_CCSR_POLAR2_Pos)

LPTIM_CCSR_POLAR2_NEG (0x1U << LPTIM_CCSR_POLAR2_Pos)
‘
LPTIM_CCSR_POLAR1_Pos 16
’
LPTIM_CCSR_POLAR1_Msk (0x1U << LPTIM_CCSR_POLAR1_Pos)
“
LPTIM_CCSR_POLAR1_POS (0x0U << LPTIM_CCSR_POLAR1_Pos)
”
LPTIM_CCSR_POLAR1_NEG (0x1U << LPTIM_CCSR_POLAR1_Pos)
–
LPTIM_CCSR_CAPCFG4_Pos 14
›
LPTIM_CCSR_CAPCFG4_Msk (0x3U << LPTIM_CCSR_CAPCFG4_Pos)
œ
LPTIM_CCSR_CAPCFG4_RISING (0x0U << LPTIM_CCSR_CAPCFG4_Pos)

LPTIM_CCSR_CAPCFG4_FALLING (0x1U << LPTIM_CCSR_CAPCFG4_Pos)
ž
LPTIM_CCSR_CAPCFG4_BOTH (0x2U << LPTIM_CCSR_CAPCFG4_Pos)
 
LPTIM_CCSR_CAPCFG3_Pos 12
¡
LPTIM_CCSR_CAPCFG3_Msk (0x3U << LPTIM_CCSR_CAPCFG3_Pos)
¢
LPTIM_CCSR_CAPCFG3_RISING (0x0U << LPTIM_CCSR_CAPCFG3_Pos)
£
LPTIM_CCSR_CAPCFG3_FALLING (0x1U << LPTIM_CCSR_CAPCFG3_Pos)
¤
LPTIM_CCSR_CAPCFG3_BOTH (0x2U << LPTIM_CCSR_CAPCFG3_Pos)
¦
LPTIM_CCSR_CAPCFG2_Pos 10
§
LPTIM_CCSR_CAPCFG2_Msk (0x3U << LPTIM_CCSR_CAPCFG2_Pos)
¨
LPTIM_CCSR_CAPCFG2_RISING (0x0U << LPTIM_CCSR_CAPCFG2_Pos)
©
LPTIM_CCSR_CAPCFG2_FALLING (0x1U << LPTIM_CCSR_CAPCFG2_Pos)
ª
LPTIM_CCSR_CAPCFG2_BOTH (0x2U << LPTIM_CCSR_CAPCFG2_Pos)
¬
LPTIM_CCSR_CAPCFG1_Pos 8
­
LPTIM_CCSR_CAPCFG1_Msk (0x3U << LPTIM_CCSR_CAPCFG1_Pos)
®
LPTIM_CCSR_CAPCFG1_RISING (0x0U << LPTIM_CCSR_CAPCFG1_Pos)
¯
LPTIM_CCSR_CAPCFG1_FALLING (0x1U << LPTIM_CCSR_CAPCFG1_Pos)
°
LPTIM_CCSR_CAPCFG1_BOTH (0x2U << LPTIM_CCSR_CAPCFG1_Pos)
²
LPTIM_CCSR_CC4S_Pos 6
¶
LPTIM_CCSR_CC4S_Msk (0x3U << LPTIM_CCSR_CC4S_Pos)
·
LPTIM_CCSR_CC4S_NON (0x0U << LPTIM_CCSR_CC4S_Pos)
¸
LPTIM_CCSR_CC4S_LPT_CH4_IN (0x1U << LPTIM_CCSR_CC4S_Pos)
¹
LPTIM_CCSR_CC4S_LPT_CH4_OUT (0x2U << LPTIM_CCSR_CC4S_Pos)
»
LPTIM_CCSR_CC3S_Pos 4
¼
LPTIM_CCSR_CC3S_Msk (0x3U << LPTIM_CCSR_CC3S_Pos)
½
LPTIM_CCSR_CC3S_NON (0x0U << LPTIM_CCSR_CC3S_Pos)
¾
LPTIM_CCSR_CC3S_LPT_CH3_IN (0x1U << LPTIM_CCSR_CC3S_Pos)
¿
LPTIM_CCSR_CC3S_LPT_CH3_OUT (0x2U << LPTIM_CCSR_CC3S_Pos)
Á
LPTIM_CCSR_CC2S_Pos 2
Â
LPTIM_CCSR_CC2S_Msk (0x3U << LPTIM_CCSR_CC2S_Pos)
Ã
LPTIM_CCSR_CC2S_NON (0x0U << LPTIM_CCSR_CC2S_Pos)
Ä
LPTIM_CCSR_CC2S_LPT_CH2_IN (0x1U << LPTIM_CCSR_CC2S_Pos)
Å
LPTIM_CCSR_CC2S_LPT_CH2_OUT (0x2U << LPTIM_CCSR_CC2S_Pos)
Ç
LPTIM_CCSR_CC1S_Pos 0
È
LPTIM_CCSR_CC1S_Msk (0x3U << LPTIM_CCSR_CC1S_Pos)
É
LPTIM_CCSR_CC1S_NON (0x0U << LPTIM_CCSR_CC1S_Pos)
Ê
LPTIM_CCSR_CC1S_LPT_CH1_IN (0x1U << LPTIM_CCSR_CC1S_Pos)
Ë
LPTIM_CCSR_CC1S_LPT_CH1_OUT (0x2U << LPTIM_CCSR_CC1S_Pos)
Í
LPTIM_ARR_ARR_Pos 0
Ï
LPTIM_ARR_ARR_Msk (0xffffffffU << LPTIM_ARR_ARR_Pos)
Ñ
LPTIM_IER_OVR4IE_Pos 11
Ô
LPTIM_IER_OVR4IE_Msk (0x1U << LPTIM_IER_OVR4IE_Pos)
Ø
LPTIM_IER_OVR3IE_Pos 10
Û
LPTIM_IER_OVR3IE_Msk (0x1U << LPTIM_IER_OVR3IE_Pos)
ß
LPTIM_IER_OVR2IE_Pos 9
â
LPTIM_IER_OVR2IE_Msk (0x1U << LPTIM_IER_OVR2IE_Pos)
æ
LPTIM_IER_OVR1IE_Pos 8
é
LPTIM_IER_OVR1IE_Msk (0x1U << LPTIM_IER_OVR1IE_Pos)
í
LPTIM_IER_TRIGIE_Pos 7
ð
LPTIM_IER_TRIGIE_Msk (0x1U << LPTIM_IER_TRIGIE_Pos)
ô
LPTIM_IER_OVIE_Pos 6
÷
LPTIM_IER_OVIE_Msk (0x1U << LPTIM_IER_OVIE_Pos)
û
LPTIM_IER_CC4IE_Pos 3
þ
LPTIM_IER_CC4IE_Msk (0x1U << LPTIM_IER_CC4IE_Pos)
‚LPTIM_IER_CC3IE_Pos 2
…LPTIM_IER_CC3IE_Msk (0x1U << LPTIM_IER_CC3IE_Pos)
‰LPTIM_IER_CC2IE_Pos 1
ŒLPTIM_IER_CC2IE_Msk (0x1U << LPTIM_IER_CC2IE_Pos)
LPTIM_IER_CC1IE_Pos 0
“LPTIM_IER_CC1IE_Msk (0x1U << LPTIM_IER_CC1IE_Pos)
—LPTIM_ISR_CAP4OVR_Pos 11
˜LPTIM_ISR_CAP4OVR_Msk (0x1U << LPTIM_ISR_CAP4OVR_Pos)
šLPTIM_ISR_CAP3OVR_Pos 10
›LPTIM_ISR_CAP3OVR_Msk (0x1U << LPTIM_ISR_CAP3OVR_Pos)
LPTIM_ISR_CAP2OVR_Pos 9
žLPTIM_ISR_CAP2OVR_Msk (0x1U << LPTIM_ISR_CAP2OVR_Pos)
 LPTIM_ISR_CAP1OVR_Pos 8
¡LPTIM_ISR_CAP1OVR_Msk (0x1U << LPTIM_ISR_CAP1OVR_Pos)
£LPTIM_ISR_TRIGIF_Pos 7
¤LPTIM_ISR_TRIGIF_Msk (0x1U << LPTIM_ISR_TRIGIF_Pos)
¦LPTIM_ISR_OVIF_Pos 6
§LPTIM_ISR_OVIF_Msk (0x1U << LPTIM_ISR_OVIF_Pos)
©LPTIM_ISR_CC4IF_Pos 3
ªLPTIM_ISR_CC4IF_Msk (0x1U << LPTIM_ISR_CC4IF_Pos)
¬LPTIM_ISR_CC3IF_Pos 2
­LPTIM_ISR_CC3IF_Msk (0x1U << LPTIM_ISR_CC3IF_Pos)
¯LPTIM_ISR_CC2IF_Pos 1
°LPTIM_ISR_CC2IF_Msk (0x1U << LPTIM_ISR_CC2IF_Pos)
²LPTIM_ISR_CC1IF_Pos 0
³LPTIM_ISR_CC1IF_Msk (0x1U << LPTIM_ISR_CC1IF_Pos)
µLPTIM_CR_EN_Pos 0
¸LPTIM_CR_EN_Msk (0x1U << LPTIM_CR_EN_Pos)
¼LPTIM_CCR1_CCR1_Pos 0
½LPTIM_CCR1_CCR1_Msk (0xffffffffU << LPTIM_CCR1_CCR1_Pos)
¿LPTIM_CCR2_CCR2_Pos 0
ÀLPTIM_CCR2_CCR2_Msk (0xffffffffU << LPTIM_CCR2_CCR2_Pos)
ÂLPTIM_CCR3_CCR3_Pos 0
ÃLPTIM_CCR3_CCR3_Msk (0xffffffffU << LPTIM_CCR3_CCR3_Pos)
ÅLPTIM_CCR4_CCR4_Pos 0
ÆLPTIM_CCR4_CCR4_Msk (0xffffffffU << LPTIM_CCR4_CCR4_Pos)`V
 




..\Drivers\..\Core\Include\fm33a0xxev_lptim.h
FM33A0XXEV.h

À
..\Drivers\fm33a0xxev_lptim.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM
í
î
ï


__FM33A0XXEV_WWDT_H 
WWDT_CR_CON_Pos 0
WWDT_CR_CON_Msk (0xffU << WWDT_CR_CON_Pos)
WWDT_CFGR_CFG_Pos 0
&WWDT_CFGR_CFG_Msk (0x7U << WWDT_CFGR_CFG_Pos)
(WWDT_CNTR_CNT_Pos 0
)WWDT_CNTR_CNT_Msk (0x3ffU << WWDT_CNTR_CNT_Pos)
+WWDT_IER_IE_Pos 0
.WWDT_IER_IE_Msk (0x1U << WWDT_IER_IE_Pos)
2WWDT_ISR_NOVF_Pos 0
6WWDT_ISR_NOVF_Msk (0x1U << WWDT_ISR_NOVF_Pos)
8WWDT_PSCR_DIV_CNT_Pos 0
9WWDT_PSCR_DIV_CNT_Msk (0xfffU << WWDT_PSCR_DIV_CNT_Pos)`U
 




..\Drivers\..\Core\Include\fm33a0xxev_wwdt.h
FM33A0XXEV.h

¼
..\Drivers\fm33a0xxev_wwdt.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM
ñ
ò
ó


__FM33A0XXEV_SVD_H 
%SVD_CFGR_LVL_Pos 4
'SVD_CFGR_LVL_Msk (0xfU << SVD_CFGR_LVL_Pos)
(SVD_CFGR_LVL_1P800V (0x0U << SVD_CFGR_LVL_Pos)
)SVD_CFGR_LVL_2P014V (0x1U << SVD_CFGR_LVL_Pos)
*SVD_CFGR_LVL_2P229V (0x2U << SVD_CFGR_LVL_Pos)
+SVD_CFGR_LVL_2P443V (0x3U << SVD_CFGR_LVL_Pos)
,SVD_CFGR_LVL_2P657V (0x4U << SVD_CFGR_LVL_Pos)
-SVD_CFGR_LVL_2P871V (0x5U << SVD_CFGR_LVL_Pos)
.SVD_CFGR_LVL_3P086V (0x6U << SVD_CFGR_LVL_Pos)
/SVD_CFGR_LVL_3P300V (0x7U << SVD_CFGR_LVL_Pos)
0SVD_CFGR_LVL_3P514V (0x8U << SVD_CFGR_LVL_Pos)
1SVD_CFGR_LVL_3P729V (0x9U << SVD_CFGR_LVL_Pos)
2SVD_CFGR_LVL_3P943V (0xaU << SVD_CFGR_LVL_Pos)
3SVD_CFGR_LVL_4P157V (0xbU << SVD_CFGR_LVL_Pos)
4SVD_CFGR_LVL_4P371V (0xcU << SVD_CFGR_LVL_Pos)
5SVD_CFGR_LVL_4P586V (0xdU << SVD_CFGR_LVL_Pos)
6SVD_CFGR_LVL_4P800V (0xeU << SVD_CFGR_LVL_Pos)
7SVD_CFGR_LVL_SVS (0xfU << SVD_CFGR_LVL_Pos)
9SVD_CFGR_DFEN_Pos 3
=SVD_CFGR_DFEN_Msk (0x1U << SVD_CFGR_DFEN_Pos)
ASVD_CFGR_MOD_Pos 2
FSVD_CFGR_MOD_Msk (0x1U << SVD_CFGR_MOD_Pos)
GSVD_CFGR_MOD_INTERVAL (0x1U << SVD_CFGR_MOD_Pos)
HSVD_CFGR_MOD_ALWAYSON (0x0U << SVD_CFGR_MOD_Pos)
JSVD_CFGR_ITVL_Pos 0
OSVD_CFGR_ITVL_Msk (0x3U << SVD_CFGR_ITVL_Pos)
PSVD_CFGR_ITVL_62P5MS (0x0U << SVD_CFGR_ITVL_Pos)
QSVD_CFGR_ITVL_256MS (0x1U << SVD_CFGR_ITVL_Pos)
RSVD_CFGR_ITVL_1S (0x2U << SVD_CFGR_ITVL_Pos)
SSVD_CFGR_ITVL_4S (0x3U << SVD_CFGR_ITVL_Pos)
XSVD_CR_TE_Pos 8
YSVD_CR_TE_Msk (0x1U << SVD_CR_TE_Pos)
[SVD_CR_SVSEN_Pos 1
`SVD_CR_SVSEN_Msk (0x1U << SVD_CR_SVSEN_Pos)
dSVD_CR_SVDEN_Pos 0
eSVD_CR_SVDEN_Msk (0x1U << SVD_CR_SVDEN_Pos)
gSVD_IER_PFIE_Pos 1
hSVD_IER_PFIE_Msk (0x1U << SVD_IER_PFIE_Pos)
jSVD_IER_PRIE_Pos 0
kSVD_IER_PRIE_Msk (0x1U << SVD_IER_PRIE_Pos)
mSVD_ISR_SVDO_Pos 8
pSVD_ISR_SVDO_Msk (0x1U << SVD_ISR_SVDO_Pos)
rSVD_ISR_SVDR_Pos 7
tSVD_ISR_SVDR_Msk (0x1U << SVD_ISR_SVDR_Pos)
vSVD_ISR_PFF_Pos 1
wSVD_ISR_PFF_Msk (0x1U << SVD_ISR_PFF_Pos)
ySVD_ISR_PRF_Pos 0
zSVD_ISR_PRF_Msk (0x1U << SVD_ISR_PRF_Pos)
|SVD_VSR_V1P0EN_Pos 2
SVD_VSR_V1P0EN_Msk (0x1U << SVD_VSR_V1P0EN_Pos)

SVD_VSR_V0P95EN_Pos 1
„
SVD_VSR_V0P95EN_Msk (0x1U << SVD_VSR_V0P95EN_Pos)
†
SVD_VSR_V0P9EN_Pos 0
‰
SVD_VSR_V0P9EN_Msk (0x1U << SVD_VSR_V0P9EN_Pos)`T
 




..\Drivers\..\Core\Include\fm33a0xxev_svd.h
FM33A0XXEV.h

D

..\Drivers\fm33a0xxev_svd.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM*¬SVDMODf
#SVDITVLf
#SVDLVLf
#DFEN
#PFIE
# PRIE
#SVDEN
#PSVD_InitTypeDef½
#
õ
ö
÷


__FM33A0XXEV_PAE_H 
ECC_STD_DBL 0x00
ECC_STD_ADD 0x01
ECC_ALG1_DBLADD 0x02
ECC_ALG2_ECDBL 0x03
ECC_ALG2_ECADDDBL 0x04
 ECC_ALG2_YRECOVER 0x05
'PAE_CSR_DATA_TYPE_Pos 8
-PAE_CSR_DATA_TYPE_Msk (0x3U << PAE_CSR_DATA_TYPE_Pos)
.PAE_CSR_DATA_TYPE_NONE (0x0U << PAE_CSR_DATA_TYPE_Pos)
/PAE_CSR_DATA_TYPE_HALFWORD (0x1U << PAE_CSR_DATA_TYPE_Pos)
0PAE_CSR_DATA_TYPE_BYTE (0x2U << PAE_CSR_DATA_TYPE_Pos)
1PAE_CSR_DATA_TYPE_BIT (0x3U << PAE_CSR_DATA_TYPE_Pos)
3PAE_CSR_START_Pos 7
4PAE_CSR_START_Msk (0x1U << PAE_CSR_START_Pos)
6PAE_CSR_RUN_MODE_Pos 4
;PAE_CSR_RUN_MODE_Msk (0x3U << PAE_CSR_RUN_MODE_Pos)
<PAE_CSR_RUN_MODE_MOD (0x0U << PAE_CSR_RUN_MODE_Pos)
=PAE_CSR_RUN_MODE_DOT (0x1U << PAE_CSR_RUN_MODE_Pos)
>PAE_CSR_RUN_MODE_RSA (0x2U << PAE_CSR_RUN_MODE_Pos)
?PAE_CSR_RUN_MODE_ECC (0x3U << PAE_CSR_RUN_MODE_Pos)
APAE_CSR_SOFT_RST_Pos 3
CPAE_CSR_SOFT_RST_Msk (0x1U << PAE_CSR_SOFT_RST_Pos)
FPAE_CSR_PAEIE_Pos 2
IPAE_CSR_PAEIE_Msk (0x1U << PAE_CSR_PAEIE_Pos)
JPAE_CSR_PAEIE_ENABLE (0x1U << PAE_CSR_PAEIE_Pos)
KPAE_CSR_PAEIE_DISABLE (0x0U << PAE_CSR_PAEIE_Pos)
MPAE_CSR_PAEIF_Pos 1
NPAE_CSR_PAEIF_Msk (0x1U << PAE_CSR_PAEIF_Pos)
PPAE_CSR_BUSY_Pos 0
SPAE_CSR_BUSY_Msk (0x1U << PAE_CSR_BUSY_Pos)
UPAE_MLR_PAE_MLR_Pos 0
YPAE_MLR_PAE_MLR_Msk (0x3fU << PAE_MLR_PAE_MLR_Pos)
[PAE_MPR_PAE_MPR_Pos 0
\PAE_MPR_PAE_MPR_Msk (0xffffffffU << PAE_MPR_PAE_MPR_Pos)
^PAE_M0CFG_BLKCFG_Pos 15
aPAE_M0CFG_BLKCFG_Msk (0x1U << PAE_M0CFG_BLKCFG_Pos)
bPAE_M0CFG_BLKCFG_16BLOCK (0x1U << PAE_M0CFG_BLKCFG_Pos)
cPAE_M0CFG_BLKCFG_4BLOCK (0x0U << PAE_M0CFG_BLKCFG_Pos)
ePAE_M0CFG_INS_M0_Pos 12
jPAE_M0CFG_INS_M0_Msk (0x3U << PAE_M0CFG_INS_M0_Pos)
kPAE_M0CFG_INS_M0_MUL (0x0U << PAE_M0CFG_INS_M0_Pos)
lPAE_M0CFG_INS_M0_ADD (0x1U << PAE_M0CFG_INS_M0_Pos)
mPAE_M0CFG_INS_M0_SUB (0x3U << PAE_M0CFG_INS_M0_Pos)
oPAE_M0CFG_RES_BLK_Pos 8
rPAE_M0CFG_RES_BLK_Msk (0xfU << PAE_M0CFG_RES_BLK_Pos)
sPAE_M0CFG_RES_BLK_BLOCK0 (0x0U << PAE_M0CFG_RES_BLK_Pos)
tPAE_M0CFG_RES_BLK_BLOCK1 (0x1U << PAE_M0CFG_RES_BLK_Pos)
uPAE_M0CFG_RES_BLK_BLOCK2 (0x2U << PAE_M0CFG_RES_BLK_Pos)
vPAE_M0CFG_RES_BLK_BLOCK3 (0x3U << PAE_M0CFG_RES_BLK_Pos)
wPAE_M0CFG_RES_BLK_BLOCK4 (0x4U << PAE_M0CFG_RES_BLK_Pos)
xPAE_M0CFG_RES_BLK_BLOCK5 (0x5U << PAE_M0CFG_RES_BLK_Pos)
yPAE_M0CFG_RES_BLK_BLOCK6 (0x6U << PAE_M0CFG_RES_BLK_Pos)
zPAE_M0CFG_RES_BLK_BLOCK7 (0x7U << PAE_M0CFG_RES_BLK_Pos)
{PAE_M0CFG_RES_BLK_BLOCK8 (0x8U << PAE_M0CFG_RES_BLK_Pos)
|PAE_M0CFG_RES_BLK_BLOCK9 (0x9U << PAE_M0CFG_RES_BLK_Pos)
}PAE_M0CFG_RES_BLK_BLOCK10 (0xAU << PAE_M0CFG_RES_BLK_Pos)
~PAE_M0CFG_RES_BLK_BLOCK11 (0xBU << PAE_M0CFG_RES_BLK_Pos)
PAE_M0CFG_RES_BLK_BLOCK12 (0xCU << PAE_M0CFG_RES_BLK_Pos)
€
PAE_M0CFG_RES_BLK_BLOCK13 (0xDU << PAE_M0CFG_RES_BLK_Pos)

PAE_M0CFG_RES_BLK_BLOCK14 (0xEU << PAE_M0CFG_RES_BLK_Pos)
‚
PAE_M0CFG_RES_BLK_BLOCK15 (0xFU << PAE_M0CFG_RES_BLK_Pos)
‰
PAE_M0CFG_OP1_BLK_Pos 4
Œ
PAE_M0CFG_OP1_BLK_Msk (0xfU << PAE_M0CFG_OP1_BLK_Pos)

PAE_M0CFG_OP1_BLK_BLOCK0 (0x0U << PAE_M0CFG_OP1_BLK_Pos)
Ž
PAE_M0CFG_OP1_BLK_BLOCK1 (0x1U << PAE_M0CFG_OP1_BLK_Pos)

PAE_M0CFG_OP1_BLK_BLOCK2 (0x2U << PAE_M0CFG_OP1_BLK_Pos)

PAE_M0CFG_OP1_BLK_BLOCK3 (0x3U << PAE_M0CFG_OP1_BLK_Pos)
‘
PAE_M0CFG_OP1_BLK_BLOCK4 (0x4U << PAE_M0CFG_OP1_BLK_Pos)
’
PAE_M0CFG_OP1_BLK_BLOCK5 (0x5U << PAE_M0CFG_OP1_BLK_Pos)
“
PAE_M0CFG_OP1_BLK_BLOCK6 (0x6U << PAE_M0CFG_OP1_BLK_Pos)
”
PAE_M0CFG_OP1_BLK_BLOCK7 (0x7U << PAE_M0CFG_OP1_BLK_Pos)
•
PAE_M0CFG_OP1_BLK_BLOCK8 (0x8U << PAE_M0CFG_OP1_BLK_Pos)
–
PAE_M0CFG_OP1_BLK_BLOCK9 (0x9U << PAE_M0CFG_OP1_BLK_Pos)
—
PAE_M0CFG_OP1_BLK_BLOCK10 (0xAU << PAE_M0CFG_OP1_BLK_Pos)
˜
PAE_M0CFG_OP1_BLK_BLOCK11 (0xBU << PAE_M0CFG_OP1_BLK_Pos)
™
PAE_M0CFG_OP1_BLK_BLOCK12 (0xCU << PAE_M0CFG_OP1_BLK_Pos)
š
PAE_M0CFG_OP1_BLK_BLOCK13 (0xDU << PAE_M0CFG_OP1_BLK_Pos)
›
PAE_M0CFG_OP1_BLK_BLOCK14 (0xEU << PAE_M0CFG_OP1_BLK_Pos)
œ
PAE_M0CFG_OP1_BLK_BLOCK15 (0xFU << PAE_M0CFG_OP1_BLK_Pos)
¡
PAE_M0CFG_OP2_BLK_Pos 0
¤
PAE_M0CFG_OP2_BLK_Msk (0xfU << PAE_M0CFG_OP2_BLK_Pos)
¥
PAE_M0CFG_OP2_BLK_BLOCK0 (0x0U << PAE_M0CFG_OP2_BLK_Pos)
¦
PAE_M0CFG_OP2_BLK_BLOCK1 (0x1U << PAE_M0CFG_OP2_BLK_Pos)
§
PAE_M0CFG_OP2_BLK_BLOCK2 (0x2U << PAE_M0CFG_OP2_BLK_Pos)
¨
PAE_M0CFG_OP2_BLK_BLOCK3 (0x3U << PAE_M0CFG_OP2_BLK_Pos)
©
PAE_M0CFG_OP2_BLK_BLOCK4 (0x4U << PAE_M0CFG_OP2_BLK_Pos)
ª
PAE_M0CFG_OP2_BLK_BLOCK5 (0x5U << PAE_M0CFG_OP2_BLK_Pos)
«
PAE_M0CFG_OP2_BLK_BLOCK6 (0x6U << PAE_M0CFG_OP2_BLK_Pos)
¬
PAE_M0CFG_OP2_BLK_BLOCK7 (0x7U << PAE_M0CFG_OP2_BLK_Pos)
­
PAE_M0CFG_OP2_BLK_BLOCK8 (0x8U << PAE_M0CFG_OP2_BLK_Pos)
®
PAE_M0CFG_OP2_BLK_BLOCK9 (0x9U << PAE_M0CFG_OP2_BLK_Pos)
¯
PAE_M0CFG_OP2_BLK_BLOCK10 (0xAU << PAE_M0CFG_OP2_BLK_Pos)
°
PAE_M0CFG_OP2_BLK_BLOCK11 (0xBU << PAE_M0CFG_OP2_BLK_Pos)
±
PAE_M0CFG_OP2_BLK_BLOCK12 (0xCU << PAE_M0CFG_OP2_BLK_Pos)
²
PAE_M0CFG_OP2_BLK_BLOCK13 (0xDU << PAE_M0CFG_OP2_BLK_Pos)
³
PAE_M0CFG_OP2_BLK_BLOCK14 (0xEU << PAE_M0CFG_OP2_BLK_Pos)
´
PAE_M0CFG_OP2_BLK_BLOCK15 (0xFU << PAE_M0CFG_OP2_BLK_Pos)
·
PAE_M1CFG_INS_M1_Pos 4
À
PAE_M1CFG_INS_M1_Msk (0x7U << PAE_M1CFG_INS_M1_Pos)
Á
PAE_M1CFG_INS_M1_JACOBIN (0x0U << PAE_M1CFG_INS_M1_Pos)
Â
PAE_M1CFG_INS_M1_MIXADD (0x1U << PAE_M1CFG_INS_M1_Pos)
Ã
PAE_M1CFG_INS_M1_ECDBL (0x3U << PAE_M1CFG_INS_M1_Pos)
Ä
PAE_M1CFG_INS_M1_ECADDDBL (0x4U << PAE_M1CFG_INS_M1_Pos)
Å
PAE_M1CFG_INS_M1_ECYRECOVER (0x5U << PAE_M1CFG_INS_M1_Pos)
Ç
PAE_M1CFG_AEN3_M1_Pos 1
Ê
PAE_M1CFG_AEN3_M1_Msk (0x1U << PAE_M1CFG_AEN3_M1_Pos)
Ë
PAE_M1CFG_AEN3_M1_NE3 (0x1U << PAE_M1CFG_AEN3_M1_Pos)
Ì
PAE_M1CFG_AEN3_M1_EQ3 (0x0U << PAE_M1CFG_AEN3_M1_Pos)
Î
PAE_M1CFG_BIT_VALUE_M1_Pos 0
Ñ
PAE_M1CFG_BIT_VALUE_M1_Msk (0x1U << PAE_M1CFG_BIT_VALUE_M1_Pos)
Ò
PAE_M1CFG_BIT_VALUE_M1_VALUE1 (0x1U << PAE_M1CFG_BIT_VALUE_M1_Pos)
Ó
PAE_M1CFG_BIT_VALUE_M1_VALUE0 (0x0U << PAE_M1CFG_BIT_VALUE_M1_Pos)
Õ
PAE_M2CFG_ALWAYS_MULT_Pos 4
Ø
PAE_M2CFG_ALWAYS_MULT_Msk (0x1U << PAE_M2CFG_ALWAYS_MULT_Pos)
Ù
PAE_M2CFG_ALWAYS_MULT_ALWAYS (0x1U << PAE_M2CFG_ALWAYS_MULT_Pos)
Ú
PAE_M2CFG_ALWAYS_MULT_NONE (0x0U << PAE_M2CFG_ALWAYS_MULT_Pos)
Ü
PAE_M2CFG_FBO_M2_Pos 0
ß
PAE_M2CFG_FBO_M2_Msk (0x1U << PAE_M2CFG_FBO_M2_Pos)
à
PAE_M2CFG_FBO_M2_FB1 (0x1U << PAE_M2CFG_FBO_M2_Pos)
á
PAE_M2CFG_FBO_M2_NFB1 (0x0U << PAE_M2CFG_FBO_M2_Pos)
ã
PAE_M3CFG_AEN3_M3_Pos 4
æ
PAE_M3CFG_AEN3_M3_Msk (0x1U << PAE_M3CFG_AEN3_M3_Pos)
ç
PAE_M3CFG_AEN3_M3_EQ3 (0x1U << PAE_M3CFG_AEN3_M3_Pos)
è
PAE_M3CFG_AEN3_M3_NE3 (0x0U << PAE_M3CFG_AEN3_M3_Pos)
ê
PAE_M3CFG_FBO_M3_Pos 0
í
PAE_M3CFG_FBO_M3_Msk (0x1U << PAE_M3CFG_FBO_M3_Pos)
î
PAE_M3CFG_FBO_M3_FB1 (0x1U << PAE_M3CFG_FBO_M3_Pos)
ï
PAE_M3CFG_FBO_M3_NFB1 (0x0U << PAE_M3CFG_FBO_M3_Pos)
ñ
PAE_WORD_PAE_WORD_Pos 0
ò
PAE_WORD_PAE_WORD_Msk (0xffffffffU << PAE_WORD_PAE_WORD_Pos)`T
 




..\Drivers\..\Core\Include\fm33a0xxev_pae.h
FM33A0XXEV.h

¼
..\Drivers\fm33a0xxev_pae.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM
ù
ú
û


__FM33A0XXEV_HASH_H 
HASH_CSR_START_Pos 7
HASH_CSR_START_Msk (0x1U << HASH_CSR_START_Pos)
HASH_CSR_BUSY_Pos 6
HASH_CSR_BUSY_Msk (0x1U << HASH_CSR_BUSY_Pos)
HASH_CSR_HASHSEL_Pos 1
 HASH_CSR_HASHSEL_Msk (0x1U << HASH_CSR_HASHSEL_Pos)
!HASH_CSR_HASHSEL_SHA256 (0x0U << HASH_CSR_HASHSEL_Pos)
"HASH_CSR_HASHSEL_SHA1 (0x1U << HASH_CSR_HASHSEL_Pos)
$HASH_DTR_DATA_TYPE_Pos 0
+HASH_DTR_DATA_TYPE_Msk (0x3U << HASH_DTR_DATA_TYPE_Pos)
,HASH_DTR_DATA_TYPE_NONE (0x0U << HASH_DTR_DATA_TYPE_Pos)
-HASH_DTR_DATA_TYPE_HALFWORD (0x1U << HASH_DTR_DATA_TYPE_Pos)
.HASH_DTR_DATA_TYPE_BYTE (0x2U << HASH_DTR_DATA_TYPE_Pos)
/HASH_DTR_DATA_TYPE_BIT (0x3U << HASH_DTR_DATA_TYPE_Pos)`U
 




..\Drivers\..\Core\Include\fm33a0xxev_hash.h
FM33A0XXEV.h

¼
..\Drivers\fm33a0xxev_hash.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM
ý
þ
ÿ


__FM33A0XXEV_QSPI_H 
)QSPI_CR_PRESCALER_Pos 24
*QSPI_CR_PRESCALER_Msk (0xffU << QSPI_CR_PRESCALER_Pos)
,QSPI_CR_PMM_Pos 23
/QSPI_CR_PMM_Msk (0x1U << QSPI_CR_PMM_Pos)
0QSPI_CR_PMM_AND (0x0U << QSPI_CR_PMM_Pos)
1QSPI_CR_PMM_OR (0x1U << QSPI_CR_PMM_Pos)
3QSPI_CR_TOIE_Pos 20
6QSPI_CR_TOIE_Msk (0x1U << QSPI_CR_TOIE_Pos)
:QSPI_CR_SMIE_Pos 19
=QSPI_CR_SMIE_Msk (0x1U << QSPI_CR_SMIE_Pos)
AQSPI_CR_FTIE_Pos 18
DQSPI_CR_FTIE_Msk (0x1U << QSPI_CR_FTIE_Pos)
HQSPI_CR_TCIE_Pos 17
KQSPI_CR_TCIE_Msk (0x1U << QSPI_CR_TCIE_Pos)
OQSPI_CR_TEIE_Pos 16
RQSPI_CR_TEIE_Msk (0x1U << QSPI_CR_TEIE_Pos)
VQSPI_CR_FIFOTHR_Pos 8
aQSPI_CR_FIFOTHR_Msk (0xfU << QSPI_CR_FIFOTHR_Pos)
bQSPI_CR_FIFOTHR_1 (0x0U << QSPI_CR_FIFOTHR_Pos)
cQSPI_CR_FIFOTHR_2 (0x1U << QSPI_CR_FIFOTHR_Pos)
dQSPI_CR_FIFOTHR_3 (0x2U << QSPI_CR_FIFOTHR_Pos)
eQSPI_CR_FIFOTHR_4 (0x3U << QSPI_CR_FIFOTHR_Pos)
fQSPI_CR_FIFOTHR_5 (0x4U << QSPI_CR_FIFOTHR_Pos)
gQSPI_CR_FIFOTHR_6 (0x5U << QSPI_CR_FIFOTHR_Pos)
hQSPI_CR_FIFOTHR_7 (0x6U << QSPI_CR_FIFOTHR_Pos)
iQSPI_CR_FIFOTHR_8 (0x7U << QSPI_CR_FIFOTHR_Pos)
jQSPI_CR_FIFOTHR_9 (0x8U << QSPI_CR_FIFOTHR_Pos)
kQSPI_CR_FIFOTHR_10 (0x9U << QSPI_CR_FIFOTHR_Pos)
lQSPI_CR_FIFOTHR_11 (0x10U << QSPI_CR_FIFOTHR_Pos)
mQSPI_CR_FIFOTHR_12 (0x11U << QSPI_CR_FIFOTHR_Pos)
nQSPI_CR_FIFOTHR_13 (0x12U << QSPI_CR_FIFOTHR_Pos)
oQSPI_CR_FIFOTHR_14 (0x13U << QSPI_CR_FIFOTHR_Pos)
pQSPI_CR_FIFOTHR_15 (0x14U << QSPI_CR_FIFOTHR_Pos)
qQSPI_CR_FIFOTHR_16 (0x15U << QSPI_CR_FIFOTHR_Pos)
sQSPI_CR_SSHFT_Pos 4
vQSPI_CR_SSHFT_Msk (0x1U << QSPI_CR_SSHFT_Pos)
zQSPI_CR_TCEN_Pos 3
~QSPI_CR_TCEN_Msk (0x1U << QSPI_CR_TCEN_Pos)
‚
QSPI_CR_DMAEN_Pos 2
…
QSPI_CR_DMAEN_Msk (0x1U << QSPI_CR_DMAEN_Pos)
‰
QSPI_CR_ABORT_Pos 1
Š
QSPI_CR_ABORT_Msk (0x1U << QSPI_CR_ABORT_Pos)
Œ
QSPI_CR_EN_Pos 0

QSPI_CR_EN_Msk (0x1U << QSPI_CR_EN_Pos)
“
QSPI_CFG_CSHT_Pos 8
˜
QSPI_CFG_CSHT_Msk (0x7U << QSPI_CFG_CSHT_Pos)
™
QSPI_CFG_CSHT_1CYCLE (0x0U << QSPI_CFG_CSHT_Pos)
š
QSPI_CFG_CSHT_2CYCLES (0x1U << QSPI_CFG_CSHT_Pos)
›
QSPI_CFG_CSHT_3CYCLES (0x2U << QSPI_CFG_CSHT_Pos)
œ
QSPI_CFG_CSHT_4CYCLES (0x3U << QSPI_CFG_CSHT_Pos)

QSPI_CFG_CSHT_5CYCLES (0x4U << QSPI_CFG_CSHT_Pos)
ž
QSPI_CFG_CSHT_6CYCLES (0x5U << QSPI_CFG_CSHT_Pos)
Ÿ
QSPI_CFG_CSHT_7CYCLES (0x6U << QSPI_CFG_CSHT_Pos)
 
QSPI_CFG_CSHT_8CYCLES (0x7U << QSPI_CFG_CSHT_Pos)
¢
QSPI_CFG_CKMODE_Pos 0
¥
QSPI_CFG_CKMODE_Msk (0x1U << QSPI_CFG_CKMODE_Pos)
¦
QSPI_CFG_CKMODE_MODE0 (0x0U << QSPI_CFG_CKMODE_Pos)
§
QSPI_CFG_CKMODE_MODE3 (0x1U << QSPI_CFG_CKMODE_Pos)
©
QSPI_SR_FIFOLVL_Pos 8
¬
QSPI_SR_FIFOLVL_Msk (0x1fU << QSPI_SR_FIFOLVL_Pos)
®
QSPI_SR_BUSY_Pos 5
¯
QSPI_SR_BUSY_Msk (0x1U << QSPI_SR_BUSY_Pos)
±
QSPI_SR_TOF_Pos 4
²
QSPI_SR_TOF_Msk (0x1U << QSPI_SR_TOF_Pos)
´
QSPI_SR_SMF_Pos 3
µ
QSPI_SR_SMF_Msk (0x1U << QSPI_SR_SMF_Pos)
·
QSPI_SR_FTF_Pos 2
¹
QSPI_SR_FTF_Msk (0x1U << QSPI_SR_FTF_Pos)
»
QSPI_SR_TCF_Pos 1
¼
QSPI_SR_TCF_Msk (0x1U << QSPI_SR_TCF_Pos)
¾
QSPI_DATALEN_QSPI_DATALEN_Pos 0
¿
QSPI_DATALEN_QSPI_DATALEN_Msk (0xffffffffU << QSPI_DATALEN_QSPI_DATALEN_Pos)
Á
QSPI_CCR_CRM_Pos 28
Ä
QSPI_CCR_CRM_Msk (0x1U << QSPI_CCR_CRM_Pos)
Å
QSPI_CCR_CRM_ALWAYS (0x0U << QSPI_CCR_CRM_Pos)
Æ
QSPI_CCR_CRM_ONLY (0x1U << QSPI_CCR_CRM_Pos)
È
QSPI_CCR_OPMODE_Pos 26
Í
QSPI_CCR_OPMODE_Msk (0x3U << QSPI_CCR_OPMODE_Pos)
Î
QSPI_CCR_OPMODE_WRITE (0x0U << QSPI_CCR_OPMODE_Pos)
Ï
QSPI_CCR_OPMODE_READ (0x1U << QSPI_CCR_OPMODE_Pos)
Ð
QSPI_CCR_OPMODE_QUERY (0x2U << QSPI_CCR_OPMODE_Pos)
Ñ
QSPI_CCR_OPMODE_MAP (0x3U << QSPI_CCR_OPMODE_Pos)
Ó
QSPI_CCR_DMODE_Pos 24
Ø
QSPI_CCR_DMODE_Msk (0x3U << QSPI_CCR_DMODE_Pos)
Ù
QSPI_CCR_DMODE_NONE (0x0U << QSPI_CCR_DMODE_Pos)
Ú
QSPI_CCR_DMODE_SINGLE (0x1U << QSPI_CCR_DMODE_Pos)
Û
QSPI_CCR_DMODE_DOUBLE (0x2U << QSPI_CCR_DMODE_Pos)
Ü
QSPI_CCR_DMODE_FOUR (0x3U << QSPI_CCR_DMODE_Pos)
Þ
QSPI_CCR_DUMCYC_Pos 18
ß
QSPI_CCR_DUMCYC_Msk (0x1fU << QSPI_CCR_DUMCYC_Pos)
á
QSPI_CCR_ABSIZE_Pos 16
æ
QSPI_CCR_ABSIZE_Msk (0x3U << QSPI_CCR_ABSIZE_Pos)
ç
QSPI_CCR_ABSIZE_8BITS (0x0U << QSPI_CCR_ABSIZE_Pos)
è
QSPI_CCR_ABSIZE_16BITS (0x1U << QSPI_CCR_ABSIZE_Pos)
é
QSPI_CCR_ABSIZE_24BITS (0x2U << QSPI_CCR_ABSIZE_Pos)
ê
QSPI_CCR_ABSIZE_32BITS (0x3U << QSPI_CCR_ABSIZE_Pos)
ì
QSPI_CCR_ABMODE_Pos 14
ñ
QSPI_CCR_ABMODE_Msk (0x3U << QSPI_CCR_ABMODE_Pos)
ò
QSPI_CCR_ABMODE_NONE (0x0U << QSPI_CCR_ABMODE_Pos)
ó
QSPI_CCR_ABMODE_SINGLE (0x1U << QSPI_CCR_ABMODE_Pos)
ô
QSPI_CCR_ABMODE_DOUBLE (0x2U << QSPI_CCR_ABMODE_Pos)
õ
QSPI_CCR_ABMODE_FOUR (0x3U << QSPI_CCR_ABMODE_Pos)
÷
QSPI_CCR_ADSIZE_Pos 12
ü
QSPI_CCR_ADSIZE_Msk (0x3U << QSPI_CCR_ADSIZE_Pos)
ý
QSPI_CCR_ADSIZE_8BITS (0x0U << QSPI_CCR_ADSIZE_Pos)
þ
QSPI_CCR_ADSIZE_16BITS (0x1U << QSPI_CCR_ADSIZE_Pos)
ÿ
QSPI_CCR_ADSIZE_24BITS (0x2U << QSPI_CCR_ADSIZE_Pos)
€QSPI_CCR_ADSIZE_32BITS (0x3U << QSPI_CCR_ADSIZE_Pos)
‚QSPI_CCR_ADMODE_Pos 10
‡QSPI_CCR_ADMODE_Msk (0x3U << QSPI_CCR_ADMODE_Pos)
ˆQSPI_CCR_ADMODE_NONE (0x0U << QSPI_CCR_ADMODE_Pos)
‰QSPI_CCR_ADMODE_SINGLE (0x1U << QSPI_CCR_ADMODE_Pos)
ŠQSPI_CCR_ADMODE_DOUBLE (0x2U << QSPI_CCR_ADMODE_Pos)
‹QSPI_CCR_ADMODE_FOUR (0x3U << QSPI_CCR_ADMODE_Pos)
QSPI_CCR_IMODE_Pos 8
’QSPI_CCR_IMODE_Msk (0x3U << QSPI_CCR_IMODE_Pos)
“QSPI_CCR_IMODE_NONE (0x0U << QSPI_CCR_IMODE_Pos)
”QSPI_CCR_IMODE_SINGLE (0x1U << QSPI_CCR_IMODE_Pos)
•QSPI_CCR_IMODE_DOUBLE (0x2U << QSPI_CCR_IMODE_Pos)
–QSPI_CCR_IMODE_FOUR (0x3U << QSPI_CCR_IMODE_Pos)
˜QSPI_CCR_INSTRUCTION_Pos 0
™QSPI_CCR_INSTRUCTION_Msk (0xffU << QSPI_CCR_INSTRUCTION_Pos)
›QSPI_ADDR_QSPI_ADDR_Pos 0
œQSPI_ADDR_QSPI_ADDR_Msk (0xffffffffU << QSPI_ADDR_QSPI_ADDR_Pos)
žQSPI_ABR_QSPI_ABR_Pos 0
ŸQSPI_ABR_QSPI_ABR_Msk (0xffffffffU << QSPI_ABR_QSPI_ABR_Pos)
¡QSPI_DR_QSPI_DATA_Pos 0
¥QSPI_DR_QSPI_DATA_Msk (0xffffffffU << QSPI_DR_QSPI_DATA_Pos)
§QSPI_SMSK_QSPI_SMSK_Pos 0
¨QSPI_SMSK_QSPI_SMSK_Msk (0xffffffffU << QSPI_SMSK_QSPI_SMSK_Pos)
ªQSPI_SMAT_QSPI_SMAT_Pos 0
¬QSPI_SMAT_QSPI_SMAT_Msk (0xffffffffU << QSPI_SMAT_QSPI_SMAT_Pos)
®QSPI_PITV_QSPI_PITV_Pos 0
¯QSPI_PITV_QSPI_PITV_Msk (0xffffU << QSPI_PITV_QSPI_PITV_Pos)
±QSPI_TO_QSPI_TO_Pos 0
³QSPI_TO_QSPI_TO_Msk (0xffffU << QSPI_TO_QSPI_TO_Pos)
µQSPI_CCR_DUMCYC_SET(value) ((value << QSPI_CCR_DUMCYC_Pos) & QSPI_CCR_DUMCYC_Msk)
¶QSPI_CCR_DUMCYC_GET(value) ((value >> QSPI_CCR_DUMCYC_Pos) & QSPI_CCR_DUMCYC_Msk)
·QSPI_CCR_INSTRUCTION_SET(value) ((value << QSPI_CCR_INSTRUCTION_Pos) & QSPI_CCR_INSTRUCTION_Msk)
¸QSPI_CCR_INSTRUCTION_GET(value) ((value >> QSPI_CCR_INSTRUCTION_Pos) & QSPI_CCR_INSTRUCTION_Msk)`U
 




..\Drivers\..\Core\Include\fm33a0xxev_qspi.h
FM33A0XXEV.h

¸

..\Drivers\fm33a0xxev_qspi.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM* (Instructionf
#Addressf
#AlternateBytef
#AddressSizef
#AlternateByteSizef
#DummyCyclesf
#InstructionModef
#AddressModef
#AlternateByteModef
# DataModef
#$PQSPI_CmdTypeDef¾
'



__FM33A0XXEV_BT_H 
BTx_CR1_CHEN_Pos 7
BTx_CR1_CHEN_Msk (0x1U << BTx_CR1_CHEN_Pos)
BTx_CR1_CLEN_Pos 6
 BTx_CR1_CLEN_Msk (0x1U << BTx_CR1_CLEN_Pos)
$BTx_CR1_MODE_Pos 5
'BTx_CR1_MODE_Msk (0x1U << BTx_CR1_MODE_Pos)
(BTx_CR1_MODE_CAPTURE (0x1U << BTx_CR1_MODE_Pos)
)BTx_CR1_MODE_COUNTER (0x0U << BTx_CR1_MODE_Pos)
+BTx_CR1_EDGESEL_Pos 4
/BTx_CR1_EDGESEL_Msk (0x1U << BTx_CR1_EDGESEL_Pos)
0BTx_CR1_EDGESEL_FALLING (0x1U << BTx_CR1_EDGESEL_Pos)
1BTx_CR1_EDGESEL_RISING (0x0U << BTx_CR1_EDGESEL_Pos)
3BTx_CR1_CAPMOD_Pos 3
6BTx_CR1_CAPMOD_Msk (0x1U << BTx_CR1_CAPMOD_Pos)
7BTx_CR1_CAPMOD_PULSE (0x1U << BTx_CR1_CAPMOD_Pos)
8BTx_CR1_CAPMOD_CYCLE (0x0U << BTx_CR1_CAPMOD_Pos)
:BTx_CR1_CAPCLR_Pos 2
=BTx_CR1_CAPCLR_Msk (0x1U << BTx_CR1_CAPCLR_Pos)
ABTx_CR1_CAPONCE_Pos 1
DBTx_CR1_CAPONCE_Msk (0x1U << BTx_CR1_CAPONCE_Pos)
EBTx_CR1_CAPONCE_SINGLE (0x1U << BTx_CR1_CAPONCE_Pos)
FBTx_CR1_CAPONCE_CONTINUE (0x0U << BTx_CR1_CAPONCE_Pos)
HBTx_CR1_PWM_Pos 0
KBTx_CR1_PWM_Msk (0x1U << BTx_CR1_PWM_Pos)
OBTx_CR2_SIG2SEL_Pos 7
RBTx_CR2_SIG2SEL_Msk (0x1U << BTx_CR2_SIG2SEL_Pos)
SBTx_CR2_SIG2SEL_GROUP2 (0x1U << BTx_CR2_SIG2SEL_Pos)
TBTx_CR2_SIG2SEL_GROUP1 (0x0U << BTx_CR2_SIG2SEL_Pos)
VBTx_CR2_SIG1SEL_Pos 6
YBTx_CR2_SIG1SEL_Msk (0x1U << BTx_CR2_SIG1SEL_Pos)
ZBTx_CR2_SIG1SEL_GROUP1 (0x1U << BTx_CR2_SIG1SEL_Pos)
[BTx_CR2_SIG1SEL_GROUP2 (0x0U << BTx_CR2_SIG1SEL_Pos)
]BTx_CR2_CNTHSEL_Pos 4
aBTx_CR2_CNTHSEL_Msk (0x3U << BTx_CR2_CNTHSEL_Pos)
bBTx_CR2_CNTHSEL_COUNTER (0x0U << BTx_CR2_CNTHSEL_Pos)
cBTx_CR2_CNTHSEL_CAPTURE (0x1U << BTx_CR2_CNTHSEL_Pos)
dBTx_CR2_CNTHSEL_INNER (0x2U << BTx_CR2_CNTHSEL_Pos)
fBTx_CR2_DIREN_Pos 3
iBTx_CR2_DIREN_Msk (0x1U << BTx_CR2_DIREN_Pos)
mBTx_CR2_STDIR_Pos 2
oBTx_CR2_STDIR_Msk (0x1U << BTx_CR2_STDIR_Pos)
rBTx_CR2_SRCSEL_Pos 1
uBTx_CR2_SRCSEL_Msk (0x1U << BTx_CR2_SRCSEL_Pos)
xBTx_CR2_DIRPO_Pos 0
{BTx_CR2_DIRPO_Msk (0x1U << BTx_CR2_DIRPO_Pos)
|BTx_CR2_DIRPO_REVERSE (0x1U << BTx_CR2_DIRPO_Pos)
}BTx_CR2_DIRPO_NON (0x0U << BTx_CR2_DIRPO_Pos)
BTx_CFGR1_RTCSEL2_Pos 6
„
BTx_CFGR1_RTCSEL2_Msk (0x3U << BTx_CFGR1_RTCSEL2_Pos)
…
BTx_CFGR1_RTCSEL2_32768HZ (0x0U << BTx_CFGR1_RTCSEL2_Pos)
†
BTx_CFGR1_RTCSEL2_RTC_SEC (0x1U << BTx_CFGR1_RTCSEL2_Pos)
‡
BTx_CFGR1_RTCSEL2_RTC_MIN (0x2U << BTx_CFGR1_RTCSEL2_Pos)
‰
BTx_CFGR1_RTCSEL1_Pos 4
Ž
BTx_CFGR1_RTCSEL1_Msk (0x3U << BTx_CFGR1_RTCSEL1_Pos)

BTx_CFGR1_RTCSEL1_32768HZ (0x0U << BTx_CFGR1_RTCSEL1_Pos)

BTx_CFGR1_RTCSEL1_RTC_SEC (0x1U << BTx_CFGR1_RTCSEL1_Pos)
‘
BTx_CFGR1_RTCSEL1_RTC_MIN (0x2U << BTx_CFGR1_RTCSEL1_Pos)
“
BTx_CFGR1_GRP2SEL_Pos 2
™
BTx_CFGR1_GRP2SEL_Msk (0x3U << BTx_CFGR1_GRP2SEL_Pos)
š
BTx_CFGR1_GRP2SEL_APBCLK (0x0U << BTx_CFGR1_GRP2SEL_Pos)
›
BTx_CFGR1_GRP2SEL_RTCOUT2 (0x1U << BTx_CFGR1_GRP2SEL_Pos)
œ
BTx_CFGR1_GRP2SEL_IN_SIG2 (0x2U << BTx_CFGR1_GRP2SEL_Pos)

BTx_CFGR1_GRP2SEL_EX_SIG2 (0x3U << BTx_CFGR1_GRP2SEL_Pos)
Ÿ
BTx_CFGR1_GRP1SEL_Pos 0
¥
BTx_CFGR1_GRP1SEL_Msk (0x3U << BTx_CFGR1_GRP1SEL_Pos)
¦
BTx_CFGR1_GRP1SEL_APBCLK (0x0U << BTx_CFGR1_GRP1SEL_Pos)
§
BTx_CFGR1_GRP1SEL_RTCOUT1 (0x1U << BTx_CFGR1_GRP1SEL_Pos)
¨
BTx_CFGR1_GRP1SEL_IN_SIG1 (0x2U << BTx_CFGR1_GRP1SEL_Pos)
©
BTx_CFGR1_GRP1SEL_EX_SIG1 (0x3U << BTx_CFGR1_GRP1SEL_Pos)
«
BTx_CFGR2_EXSEL2_Pos 6
°
BTx_CFGR2_EXSEL2_Msk (0x3U << BTx_CFGR2_EXSEL2_Pos)
±
BTx_CFGR2_EXSEL2_IN0 (0x0U << BTx_CFGR2_EXSEL2_Pos)
²
BTx_CFGR2_EXSEL2_IN1 (0x1U << BTx_CFGR2_EXSEL2_Pos)
³
BTx_CFGR2_EXSEL2_IN2 (0x2U << BTx_CFGR2_EXSEL2_Pos)
´
BTx_CFGR2_EXSEL2_IN3 (0x3U << BTx_CFGR2_EXSEL2_Pos)
¶
BTx_CFGR2_EXSEL1_Pos 4
»
BTx_CFGR2_EXSEL1_Msk (0x3U << BTx_CFGR2_EXSEL1_Pos)
¼
BTx_CFGR2_EXSEL1_IN0 (0x0U << BTx_CFGR2_EXSEL1_Pos)
½
BTx_CFGR2_EXSEL1_IN1 (0x1U << BTx_CFGR2_EXSEL1_Pos)
¾
BTx_CFGR2_EXSEL1_IN2 (0x2U << BTx_CFGR2_EXSEL1_Pos)
¿
BTx_CFGR2_EXSEL1_IN3 (0x3U << BTx_CFGR2_EXSEL1_Pos)
Á
BTx_CFGR2_INSEL2_Pos 2
Æ
BTx_CFGR2_INSEL2_Msk (0x3U << BTx_CFGR2_INSEL2_Pos)
Ç
BTx_CFGR2_INSEL2_RX3 (0x0U << BTx_CFGR2_INSEL2_Pos)
È
BTx_CFGR2_INSEL2_RX4 (0x1U << BTx_CFGR2_INSEL2_Pos)
É
BTx_CFGR2_INSEL2_RX5 (0x2U << BTx_CFGR2_INSEL2_Pos)
Ê
BTx_CFGR2_INSEL2_RCLP (0x3U << BTx_CFGR2_INSEL2_Pos)
Ì
BTx_CFGR2_INSEL1_Pos 0
Ñ
BTx_CFGR2_INSEL1_Msk (0x3U << BTx_CFGR2_INSEL1_Pos)
Ò
BTx_CFGR2_INSEL1_RX0 (0x0U << BTx_CFGR2_INSEL1_Pos)
Ó
BTx_CFGR2_INSEL1_RX1 (0x1U << BTx_CFGR2_INSEL1_Pos)
Ô
BTx_CFGR2_INSEL1_RX2 (0x2U << BTx_CFGR2_INSEL1_Pos)
Õ
BTx_CFGR2_INSEL1_RCLP (0x3U << BTx_CFGR2_INSEL1_Pos)
×
BTx_PRES_PRESCALE_Pos 0
Ù
BTx_PRES_PRESCALE_Msk (0xffU << BTx_PRES_PRESCALE_Pos)
Û
BTx_LOADCR_LHEN_Pos 4
Ý
BTx_LOADCR_LHEN_Msk (0x1U << BTx_LOADCR_LHEN_Pos)
ß
BTx_LOADCR_LLEN_Pos 0
á
BTx_LOADCR_LLEN_Msk (0x1U << BTx_LOADCR_LLEN_Pos)
ã
BTx_CNTL_CNTL_Pos 0
å
BTx_CNTL_CNTL_Msk (0xffU << BTx_CNTL_CNTL_Pos)
ç
BTx_CNTH_CNTH_Pos 0
é
BTx_CNTH_CNTH_Msk (0xffU << BTx_CNTH_CNTH_Pos)
ë
BTx_PRESET_PRESETH_Pos 8
í
BTx_PRESET_PRESETH_Msk (0xffU << BTx_PRESET_PRESETH_Pos)
ï
BTx_PRESET_PRESETL_Pos 0
ñ
BTx_PRESET_PRESETL_Msk (0xffU << BTx_PRESET_PRESETL_Pos)
ó
BTx_LOADL_LOADL_Pos 0
õ
BTx_LOADL_LOADL_Msk (0xffU << BTx_LOADL_LOADL_Pos)
÷
BTx_LOADH_LOADH_Pos 0
ù
BTx_LOADH_LOADH_Msk (0xffU << BTx_LOADH_LOADH_Pos)
û
BTx_CMPL_CMPL_Pos 0
ý
BTx_CMPL_CMPL_Msk (0xffU << BTx_CMPL_CMPL_Pos)
ÿ
BTx_CMPH_CMPH_Pos 0
BTx_CMPH_CMPH_Msk (0xffU << BTx_CMPH_CMPH_Pos)
ƒBTx_OUTCNT_OUTCNT_Pos 0
…BTx_OUTCNT_OUTCNT_Msk (0xfffU << BTx_OUTCNT_OUTCNT_Pos)
‡BTx_OCR_OUTCLR_Pos 5
ˆBTx_OCR_OUTCLR_Msk (0x1U << BTx_OCR_OUTCLR_Pos)
‰BTx_OCR_OUTCLR_INVALID (0x0U << BTx_OCR_OUTCLR_Pos)
ŠBTx_OCR_OUTCLR_CLEAR (0x1U << BTx_OCR_OUTCLR_Pos)
ŒBTx_OCR_OUTINV_Pos 4
BTx_OCR_OUTINV_Msk (0x1U << BTx_OCR_OUTINV_Pos)
ŽBTx_OCR_OUTINV_NORMAL (0x0U << BTx_OCR_OUTINV_Pos)
BTx_OCR_OUTINV_REVERSE (0x1U << BTx_OCR_OUTINV_Pos)
‘BTx_OCR_OUTMOD_Pos 3
’BTx_OCR_OUTMOD_Msk (0x1U << BTx_OCR_OUTMOD_Pos)
“BTx_OCR_OUTMOD_PULSE_SHIFT (0x0U << BTx_OCR_OUTMOD_Pos)
”BTx_OCR_OUTMOD_NEG (0x1U << BTx_OCR_OUTMOD_Pos)
–BTx_OCR_OUTSEL_Pos 0
—BTx_OCR_OUTSEL_Msk (0x7U << BTx_OCR_OUTSEL_Pos)
˜BTx_OCR_OUTSEL_HIGH (0x0U << BTx_OCR_OUTSEL_Pos)
™BTx_OCR_OUTSEL_LOW (0x1U << BTx_OCR_OUTSEL_Pos)
šBTx_OCR_OUTSEL_GROUP1 (0x2U << BTx_OCR_OUTSEL_Pos)
›BTx_OCR_OUTSEL_GROUP2 (0x3U << BTx_OCR_OUTSEL_Pos)
œBTx_OCR_OUTSEL_PWM (0x4U << BTx_OCR_OUTSEL_Pos)
žBTx_IER_CMPHIE_Pos 4
¡BTx_IER_CMPHIE_Msk (0x1U << BTx_IER_CMPHIE_Pos)
£BTx_IER_CMPLIE_Pos 3
¦BTx_IER_CMPLIE_Msk (0x1U << BTx_IER_CMPLIE_Pos)
¨BTx_IER_OVHIE_Pos 2
«BTx_IER_OVHIE_Msk (0x1U << BTx_IER_OVHIE_Pos)
­BTx_IER_OVLIE_Pos 1
°BTx_IER_OVLIE_Msk (0x1U << BTx_IER_OVLIE_Pos)
²BTx_IER_CAPIE_Pos 0
µBTx_IER_CAPIE_Msk (0x1U << BTx_IER_CAPIE_Pos)
·BTx_ISR_EDGESTA_Pos 5
ºBTx_ISR_EDGESTA_Msk (0x1U << BTx_ISR_EDGESTA_Pos)
¼BTx_ISR_CMPHIF_Pos 4
¿BTx_ISR_CMPHIF_Msk (0x1U << BTx_ISR_CMPHIF_Pos)
ÁBTx_ISR_CMPLIF_Pos 3
ÄBTx_ISR_CMPLIF_Msk (0x1U << BTx_ISR_CMPLIF_Pos)
ÆBTx_ISR_OVHIF_Pos 2
ÉBTx_ISR_OVHIF_Msk (0x1U << BTx_ISR_OVHIF_Pos)
ËBTx_ISR_OVLIF_Pos 1
ÎBTx_ISR_OVLIF_Msk (0x1U << BTx_ISR_OVLIF_Pos)
ÐBTx_ISR_CAPIF_Pos 0
ÓBTx_ISR_CAPIF_Msk (0x1U << BTx_ISR_CAPIF_Pos)\S
 




..\Drivers\..\Core\Include\fm33a0xxev_bt.h
FM33A0XXEV.h

¼
..\Drivers\fm33a0xxev_bt.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM


__FM33A0XXEV_ET_H 
ETx_CR_OPOL_Pos 10
ETx_CR_OPOL_Msk (0x1U << ETx_CR_OPOL_Pos)
ETx_CR_OPOL_NORMAL (0x0U << ETx_CR_OPOL_Pos)
ETx_CR_OPOL_REVERSE (0x1U << ETx_CR_OPOL_Pos)
 ETx_CR_EXFLT_Pos 9
#ETx_CR_EXFLT_Msk (0x1U << ETx_CR_EXFLT_Pos)
$ETx_CR_EXFLT_OPEN (0x1U << ETx_CR_EXFLT_Pos)
%ETx_CR_EXFLT_CLOSE (0x0U << ETx_CR_EXFLT_Pos)
'ETx_CR_PWM_Pos 8
*ETx_CR_PWM_Msk (0x1U << ETx_CR_PWM_Pos)
,ETx_CR_CEN_Pos 7
/ETx_CR_CEN_Msk (0x1U << ETx_CR_CEN_Pos)
1ETx_CR_MOD_Pos 6
4ETx_CR_MOD_Msk (0x1U << ETx_CR_MOD_Pos)
5ETx_CR_MOD_CAPTURE (0x1U << ETx_CR_MOD_Pos)
6ETx_CR_MOD_COUNTER (0x0U << ETx_CR_MOD_Pos)
8ETx_CR_CASEN_Pos 5
;ETx_CR_CASEN_Msk (0x1U << ETx_CR_CASEN_Pos)
<ETx_CR_CASEN_32BITS (0x1U << ETx_CR_CASEN_Pos)
=ETx_CR_CASEN_16BITS (0x0U << ETx_CR_CASEN_Pos)
?ETx_CR_EDGESEL_Pos 4
CETx_CR_EDGESEL_Msk (0x1U << ETx_CR_EDGESEL_Pos)
DETx_CR_EDGESEL_FALLING (0x1U << ETx_CR_EDGESEL_Pos)
EETx_CR_EDGESEL_RISING (0x0U << ETx_CR_EDGESEL_Pos)
GETx_CR_CAPMOD_Pos 3
JETx_CR_CAPMOD_Msk (0x1U << ETx_CR_CAPMOD_Pos)
KETx_CR_CAPMOD_PULSE (0x1U << ETx_CR_CAPMOD_Pos)
LETx_CR_CAPMOD_CYCLE (0x0U << ETx_CR_CAPMOD_Pos)
NETx_CR_CAPCLR_Pos 2
QETx_CR_CAPCLR_Msk (0x1U << ETx_CR_CAPCLR_Pos)
TETx_CR_CAPONCE_Pos 1
WETx_CR_CAPONCE_Msk (0x1U << ETx_CR_CAPONCE_Pos)
XETx_CR_CAPONCE_SINGLE (0x1U << ETx_CR_CAPONCE_Pos)
YETx_CR_CAPONCE_CONTINUE (0x0U << ETx_CR_CAPONCE_Pos)
[ETx_CR_CAPEDGE_Pos 0
^ETx_CR_CAPEDGE_Msk (0x1U << ETx_CR_CAPEDGE_Pos)
_ETx_CR_CAPEDGE_FALLING (0x1U << ETx_CR_CAPEDGE_Pos)
`ETx_CR_CAPEDGE_RISING (0x0U << ETx_CR_CAPEDGE_Pos)
bETx_INSR_SIG2SEL_Pos 7
eETx_INSR_SIG2SEL_Msk (0x1U << ETx_INSR_SIG2SEL_Pos)
fETx_INSR_SIG2SEL_GROUP1 (0x1U << ETx_INSR_SIG2SEL_Pos)
gETx_INSR_SIG2SEL_GROUP2 (0x0U << ETx_INSR_SIG2SEL_Pos)
iETx_INSR_SIG1SEL_Pos 6
lETx_INSR_SIG1SEL_Msk (0x1U << ETx_INSR_SIG1SEL_Pos)
mETx_INSR_SIG1SEL_GROUP2 (0x1U << ETx_INSR_SIG1SEL_Pos)
nETx_INSR_SIG1SEL_GROUP1 (0x0U << ETx_INSR_SIG1SEL_Pos)
pETx_INSR_GRP2SEL_Pos 2
“
ETx_INSR_GRP2SEL_Msk (0x7U << ETx_INSR_GRP2SEL_Pos)
”
ETx_INSR_GRP2SEL_ET1_UART0_RX (0x0U << ETx_INSR_GRP2SEL_Pos)
•
ETx_INSR_GRP2SEL_ET1_UART1_RX (0x1U << ETx_INSR_GRP2SEL_Pos)
–
ETx_INSR_GRP2SEL_ET1_XTLF (0x2U << ETx_INSR_GRP2SEL_Pos)
—
ETx_INSR_GRP2SEL_ET1_IN1 (0x3U << ETx_INSR_GRP2SEL_Pos)
˜
ETx_INSR_GRP2SEL_ET1_IN2 (0x4U << ETx_INSR_GRP2SEL_Pos)
™
ETx_INSR_GRP2SEL_ET1_CMP1O (0x5U << ETx_INSR_GRP2SEL_Pos)
š
ETx_INSR_GRP2SEL_ET1_CMP2O (0x6U << ETx_INSR_GRP2SEL_Pos)
›
ETx_INSR_GRP2SEL_ET1_RCMF (0x7U << ETx_INSR_GRP2SEL_Pos)
œ
ETx_INSR_GRP2SEL_ET2_UART2_RX (0x0U << ETx_INSR_GRP2SEL_Pos)

ETx_INSR_GRP2SEL_ET2_UART3_RX (0x1U << ETx_INSR_GRP2SEL_Pos)
ž
ETx_INSR_GRP2SEL_ET2_XTLF (0x2U << ETx_INSR_GRP2SEL_Pos)
Ÿ
ETx_INSR_GRP2SEL_ET2_IN1 (0x3U << ETx_INSR_GRP2SEL_Pos)
 
ETx_INSR_GRP2SEL_ET2_IN2 (0x4U << ETx_INSR_GRP2SEL_Pos)
¡
ETx_INSR_GRP2SEL_ET2_CMP1O (0x5U << ETx_INSR_GRP2SEL_Pos)
¢
ETx_INSR_GRP2SEL_ET2_CMP2O (0x6U << ETx_INSR_GRP2SEL_Pos)
£
ETx_INSR_GRP2SEL_ET2_RCMF (0x7U << ETx_INSR_GRP2SEL_Pos)
¤
ETx_INSR_GRP2SEL_ET3_IN1 (0x0U << ETx_INSR_GRP2SEL_Pos)
¥
ETx_INSR_GRP2SEL_ET3_XTLF (0x1U << ETx_INSR_GRP2SEL_Pos)
¦
ETx_INSR_GRP2SEL_ET3_UART4_RX (0x2U << ETx_INSR_GRP2SEL_Pos)
§
ETx_INSR_GRP2SEL_ET3_UART5_RX (0x3U << ETx_INSR_GRP2SEL_Pos)
¨
ETx_INSR_GRP2SEL_ET3_RTCSEC (0x4U << ETx_INSR_GRP2SEL_Pos)
©
ETx_INSR_GRP2SEL_ET4_IN (0x0U << ETx_INSR_GRP2SEL_Pos)
ª
ETx_INSR_GRP2SEL_ET4_XTLF (0x1U << ETx_INSR_GRP2SEL_Pos)
«
ETx_INSR_GRP2SEL_ET4_UART_RX2 (0x2U << ETx_INSR_GRP2SEL_Pos)
¬
ETx_INSR_GRP2SEL_ET4_UART_RX0 (0x3U << ETx_INSR_GRP2SEL_Pos)
­
ETx_INSR_GRP2SEL_ET4_CMP1O (0x4U << ETx_INSR_GRP2SEL_Pos)
®
ETx_INSR_GRP2SEL_ET4_CMP2O (0x5U << ETx_INSR_GRP2SEL_Pos)
¯
ETx_INSR_GRP2SEL_ET4_RTCSEC (0x6U << ETx_INSR_GRP2SEL_Pos)
°
ETx_INSR_GRP2SEL_ET4_RCMF (0x7U << ETx_INSR_GRP2SEL_Pos)
²
ETx_INSR_GRP1SEL_Pos 0
Ç
ETx_INSR_GRP1SEL_Msk (0x3U << ETx_INSR_GRP1SEL_Pos)
È
ETx_INSR_GRP1SEL_ET1_APBCLK (0x0U << ETx_INSR_GRP1SEL_Pos)
É
ETx_INSR_GRP1SEL_ET1_XTLF (0x1U << ETx_INSR_GRP1SEL_Pos)
Ê
ETx_INSR_GRP1SEL_ET1_RCLP (0x2U << ETx_INSR_GRP1SEL_Pos)
Ë
ETx_INSR_GRP1SEL_ET1_IN0 (0x3U << ETx_INSR_GRP1SEL_Pos)
Ì
ETx_INSR_GRP1SEL_ET2_APBCLK (0x0U << ETx_INSR_GRP1SEL_Pos)
Í
ETx_INSR_GRP1SEL_ET2_XTLF (0x1U << ETx_INSR_GRP1SEL_Pos)
Î
ETx_INSR_GRP1SEL_ET2_RCLP (0x2U << ETx_INSR_GRP1SEL_Pos)
Ï
ETx_INSR_GRP1SEL_ET2_IN0 (0x3U << ETx_INSR_GRP1SEL_Pos)
Ð
ETx_INSR_GRP1SEL_ET3_APBCLK (0x0U << ETx_INSR_GRP1SEL_Pos)
Ñ
ETx_INSR_GRP1SEL_ET3_IN0 (0x1U << ETx_INSR_GRP1SEL_Pos)
Ò
ETx_INSR_GRP1SEL_ET3_RTCSEC (0x2U << ETx_INSR_GRP1SEL_Pos)
Ó
ETx_INSR_GRP1SEL_ET3_RCLP (0x3U << ETx_INSR_GRP1SEL_Pos)
Ô
ETx_INSR_GRP1SEL_ET4_APBCLK (0x0U << ETx_INSR_GRP1SEL_Pos)
Õ
ETx_INSR_GRP1SEL_ET4_IN0 (0x1U << ETx_INSR_GRP1SEL_Pos)
Ö
ETx_INSR_GRP1SEL_ET4_RTC64HZ (0x2U << ETx_INSR_GRP1SEL_Pos)
×
ETx_INSR_GRP1SEL_ET4_RCMF (0x3U << ETx_INSR_GRP1SEL_Pos)
Ù
ETx_PSCR1_PRESCALE1_Pos 0
Û
ETx_PSCR1_PRESCALE1_Msk (0xffU << ETx_PSCR1_PRESCALE1_Pos)
Ý
ETx_PSCR2_PRESCALE2_Pos 0
ß
ETx_PSCR2_PRESCALE2_Msk (0xffU << ETx_PSCR2_PRESCALE2_Pos)
á
ETx_IVR_INITVALUE_Pos 0
â
ETx_IVR_INITVALUE_Msk (0xffffU << ETx_IVR_INITVALUE_Pos)
ä
ETx_CMPR_CMP_Pos 0
æ
ETx_CMPR_CMP_Msk (0xffffU << ETx_CMPR_CMP_Pos)
è
ETx_IER_CMPIE_Pos 2
ë
ETx_IER_CMPIE_Msk (0x1U << ETx_IER_CMPIE_Pos)
í
ETx_IER_CAPIE_Pos 1
ð
ETx_IER_CAPIE_Msk (0x1U << ETx_IER_CAPIE_Pos)
ò
ETx_IER_OVIE_Pos 0
õ
ETx_IER_OVIE_Msk (0x1U << ETx_IER_OVIE_Pos)
÷
ETx_ISR_CMPIF_Pos 3
ú
ETx_ISR_CMPIF_Msk (0x1U << ETx_ISR_CMPIF_Pos)
ü
ETx_ISR_EDGESTA_Pos 2
ÿ
ETx_ISR_EDGESTA_Msk (0x1U << ETx_ISR_EDGESTA_Pos)
ETx_ISR_CAPIF_Pos 1
„ETx_ISR_CAPIF_Msk (0x1U << ETx_ISR_CAPIF_Pos)
†ETx_ISR_OVIF_Pos 0
‰ETx_ISR_OVIF_Msk (0x1U << ETx_ISR_OVIF_Pos)
‹ETCNTx_CNT_Pos 0
ŒETCNTx_CNT_Msk (0xffffU << ETCNTx_CNT_Pos)\S
 




..\Drivers\..\Core\Include\fm33a0xxev_et.h
FM33A0XXEV.h

¼
..\Drivers\fm33a0xxev_et.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM
    


__FM33A0XXEV_VRTC_H 
HXVAR(object,addr) (*((object *) (addr)))
const_rcmf_Trim HXVAR( uint32_t, 0x1FFFFB44 )
const_rclp_Trim HXVAR( uint32_t, 0x1FFFFB20 )
VRTC_PDRCR_CFG_Pos 0
VRTC_PDRCR_CFG_Msk (0x1U << VRTC_PDRCR_CFG_Pos)
"VRTC_RCMFCR_EN_Msk (0x1U << VRTC_RCMFCR_EN_Pos)
&VRTC_RCMFCR_EN_Pos 7
*VRTC_RCMFCR_EN_Msk (0x1U << VRTC_RCMFCR_EN_Pos)
.VRTC_RCMFCR_TRIM_Pos 0
/VRTC_RCMFCR_TRIM_Msk (0x3fU << VRTC_RCMFCR_TRIM_Pos)
1VRTC_RCLPCR_CHOPEN_Pos 1
2VRTC_RCLPCR_CHOPEN_Msk (0x1U << VRTC_RCLPCR_CHOPEN_Pos)
4VRTC_RCLPCR_RCLP_OFF_Pos 0
8VRTC_RCLPCR_RCLP_OFF_Msk (0x1U << VRTC_RCLPCR_RCLP_OFF_Pos)
<VRTC_RCLPTR_RCLP_TRIM_Pos 0
?VRTC_RCLPTR_RCLP_TRIM_Msk (0xffU << VRTC_RCLPTR_RCLP_TRIM_Pos)
AVRTC_XTLFCR_XTLFIPW_Pos 0
BVRTC_XTLFCR_XTLFIPW_Msk (0xfU << VRTC_XTLFCR_XTLFIPW_Pos)
CVRTC_XTLFCR_XTLFIPW_850NA (0x0U << VRTC_XTLFCR_XTLFIPW_Pos)
DVRTC_XTLFCR_XTLFIPW_800NA (0x1U << VRTC_XTLFCR_XTLFIPW_Pos)
EVRTC_XTLFCR_XTLFIPW_750NA (0x2U << VRTC_XTLFCR_XTLFIPW_Pos)
FVRTC_XTLFCR_XTLFIPW_700NA (0x3U << VRTC_XTLFCR_XTLFIPW_Pos)
GVRTC_XTLFCR_XTLFIPW_650NA (0x4U << VRTC_XTLFCR_XTLFIPW_Pos)
HVRTC_XTLFCR_XTLFIPW_600NA (0x5U << VRTC_XTLFCR_XTLFIPW_Pos)
IVRTC_XTLFCR_XTLFIPW_550NA (0x6U << VRTC_XTLFCR_XTLFIPW_Pos)
JVRTC_XTLFCR_XTLFIPW_500NA (0x7U << VRTC_XTLFCR_XTLFIPW_Pos)
KVRTC_XTLFCR_XTLFIPW_450NA (0x8U << VRTC_XTLFCR_XTLFIPW_Pos)
LVRTC_XTLFCR_XTLFIPW_400NA (0x9U << VRTC_XTLFCR_XTLFIPW_Pos)
MVRTC_XTLFCR_XTLFIPW_350NA (0xaU << VRTC_XTLFCR_XTLFIPW_Pos)
NVRTC_XTLFCR_XTLFIPW_300NA (0xbU << VRTC_XTLFCR_XTLFIPW_Pos)
OVRTC_XTLFCR_XTLFIPW_250NA (0xcU << VRTC_XTLFCR_XTLFIPW_Pos)
PVRTC_XTLFCR_XTLFIPW_200NA (0xdU << VRTC_XTLFCR_XTLFIPW_Pos)
QVRTC_XTLFCR_XTLFIPW_150NA (0xeU << VRTC_XTLFCR_XTLFIPW_Pos)
RVRTC_XTLFCR_XTLFIPW_100NA (0xfU << VRTC_XTLFCR_XTLFIPW_Pos)
TVRTC_ADCCR_CKS_Pos 1
]VRTC_ADCCR_CKS_Msk (0x7U << VRTC_ADCCR_CKS_Pos)
^VRTC_ADCCR_CKS_RCMF (0x0U << VRTC_ADCCR_CKS_Pos)
_VRTC_ADCCR_CKS_RCMF_2 (0x1U << VRTC_ADCCR_CKS_Pos)
`VRTC_ADCCR_CKS_RCMF_4 (0x2U << VRTC_ADCCR_CKS_Pos)
aVRTC_ADCCR_CKS_RCMF_8 (0x3U << VRTC_ADCCR_CKS_Pos)
bVRTC_ADCCR_CKS_RCMF_16 (0x4U << VRTC_ADCCR_CKS_Pos)
cVRTC_ADCCR_CKS_RCMF_32 (0x5U << VRTC_ADCCR_CKS_Pos)
dVRTC_ADCCR_CKS_RCLP (0x6U << VRTC_ADCCR_CKS_Pos)
eVRTC_ADCCR_CKS_XTLF (0x7U << VRTC_ADCCR_CKS_Pos)
gVRTC_ADCCR_CKE_Pos 0
jVRTC_ADCCR_CKE_Msk (0x1U << VRTC_ADCCR_CKE_Pos)
nVRTC_LFDIER_LFDET_IE_Pos 0
oVRTC_LFDIER_LFDET_IE_Msk (0x1U << VRTC_LFDIER_LFDET_IE_Pos)
qVRTC_LFDISR_LFDETO_Pos 1
tVRTC_LFDISR_LFDETO_Msk (0x1U << VRTC_LFDISR_LFDETO_Pos)
vVRTC_LFDISR_LFDET_IF_Pos 0
wVRTC_LFDISR_LFDET_IF_Msk (0x1U << VRTC_LFDISR_LFDET_IF_Pos)`U
 




..\Drivers\..\Core\Include\fm33a0xxev_vrtc.h
FM33A0XXEV.h

¼
..\Drivers\fm33a0xxev_vrtc.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM
 

__FM33A0XXEV_CDIF_H 
CDIF_CR_INTF_EN_Pos 0
CDIF_CR_INTF_EN_Msk (0xfU << CDIF_CR_INTF_EN_Pos)
CDIF_CR_INTF_EN_ENABLE (0xAU << CDIF_CR_INTF_EN_Pos)
CDIF_CR_INTF_EN_DISABLE (0x5U << CDIF_CR_INTF_EN_Pos)
!CDIF_PSCR_PRSC_Pos 0
"CDIF_PSCR_PRSC_Msk (0x7U << CDIF_PSCR_PRSC_Pos)
#CDIF_PSCR_PRSC_DIV1 (0x0U)
$CDIF_PSCR_PRSC_DIV2 (0x1U)
%CDIF_PSCR_PRSC_DIV4 (0x2U)
&CDIF_PSCR_PRSC_DIV8 (0x3U)
'CDIF_PSCR_PRSC_DIV16 (0x4U)
(CDIF_PSCR_PRSC_DIV32 (0x5U)
)CDIF_PSCR_PRSC_DIV64 (0x6U)
*CDIF_PSCR_PRSC_DIV128 (0x7U)`U
 




..\Drivers\..\Core\Include\fm33a0xxev_cdif.h
FM33A0XXEV.h

¼
..\Drivers\fm33a0xxev_cdif.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM


__INCLUDEALL_H__     
     
  !"#$ ÌÂ
 




..\Core\..\Drivers\fm33a0xxev_include_all.h
fm33a0xxev_aes.hfm33a0xxev_adc.hfm33a0xxev_bstim.hfm33a0xxev_comp.hfm33a0xxev_rmu.hfm33a0xxev_crc.hfm33a0xxev_lcd.hfm33a0xxev_dma.hfm33a0xxev_gpio.hfm33a0xxev_i2c.hfm33a0xxev_iwdt.hfm33a0xxev_lpuart.hfm33a0xxev_flash.hfm33a0xxev_pmu.hfm33a0xxev_cmu.hfm33a0xxev_rtc.hfm33a0xxev_dbg.hfm33a0xxev_spi.hfm33a0xxev_rng.hfm33a0xxev_u7816.hfm33a0xxev_uart.hfm33a0xxev_lptim.hfm33a0xxev_wwdt.hfm33a0xxev_svd.hfm33a0xxev_pae.hfm33a0xxev_hash.hfm33a0xxev_qspi.hfm33a0xxev_bt.hfm33a0xxev_et.hfm33a0xxev_vrtc.hfm33a0xxev_cdif.h

À
..\Core\fm33a0xxev_include_all.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM


__string_h 
__ARMCLIB_VERSION 5060037
_ARMABI __declspec(__nothrow)
__STRING_DECLS __CLIBNS
$__CLIBNS 7NULL
8NULL 0XM
 




D:\Keil5\ARM\ARMCC\Bin\..\include\string.h
stdio.h


¤D:\Keil5\ARM\ARMCC\Bin\..\include\string.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]unsigned intPsize_tˆ5


BIT0 0x00000001
BIT1 0x00000002
BIT2 0x00000004
BIT3 0x00000008
BIT4 0x00000010
BIT5 0x00000020
    BIT6 0x00000040

BIT7 0x00000080
BIT8 0x00000100
BIT9 0x00000200
 BIT10 0x00000400
BIT11 0x00000800
BIT12 0x00001000
BIT13 0x00002000
BIT14 0x00004000
BIT15 0x00008000
BIT16 0x00010000
BIT17 0x00020000
BIT18 0x00040000
BIT19 0x00080000
BIT20 0x00100000
BIT21 0x00200000
BIT22 0x00400000
BIT23 0x00800000
BIT24 0x01000000
BIT25 0x02000000
BIT26 0x04000000
BIT27 0x08000000
BIT28 0x10000000
 BIT29 0x20000000
!BIT30 0x40000000
"BIT31 0x80000000
#BITNO 0x00000000
%B0000_0000 0x00
&B0000_0001 0x01
'B0000_0010 0x02
(B0000_0011 0x03
)B0000_0100 0x04
*B0000_0101 0x05
+B0000_0110 0x06
,B0000_0111 0x07
-B0000_1000 0x08
.B0000_1001 0x09
/B0000_1010 0x0A
0B0000_1011 0x0B
1B0000_1100 0x0C
2B0000_1101 0x0D
3B0000_1110 0x0E
4B0000_1111 0x0F
6B0001_0000 0x10
7B0001_0001 0x11
8B0001_0010 0x12
9B0001_0011 0x13
:B0001_0100 0x14
;B0001_0101 0x15
<B0001_0110 0x16
=B0001_0111 0x17
>B0001_1000 0x18
?B0001_1001 0x19
@B0001_1010 0x1A
AB0001_1011 0x1B
BB0001_1100 0x1C
CB0001_1101 0x1D
DB0001_1110 0x1E
EB0001_1111 0x1F
GB0010_0000 0x20
HB0010_0001 0x21
IB0010_0010 0x22
JB0010_0011 0x23
KB0010_0100 0x24
LB0010_0101 0x25
MB0010_0110 0x26
NB0010_0111 0x27
OB0010_1000 0x28
PB0010_1001 0x29
QB0010_1010 0x2A
RB0010_1011 0x2B
SB0010_1100 0x2C
TB0010_1101 0x2D
UB0010_1110 0x2E
VB0010_1111 0x2F
XB0011_0000 0x30
YB0011_0001 0x31
ZB0011_0010 0x32
[B0011_0011 0x33
\B0011_0100 0x34
]B0011_0101 0x35
^B0011_0110 0x36
_B0011_0111 0x37
`B0011_1000 0x38
aB0011_1001 0x39
bB0011_1010 0x3A
cB0011_1011 0x3B
dB0011_1100 0x3C
eB0011_1101 0x3D
fB0011_1110 0x3E
gB0011_1111 0x3F
iB0100_0000 0x40
jB0100_0001 0x41
kB0100_0010 0x42
lB0100_0011 0x43
mB0100_0100 0x44
nB0100_0101 0x45
oB0100_0110 0x46
pB0100_0111 0x47
qB0100_1000 0x48
rB0100_1001 0x49
sB0100_1010 0x4A
tB0100_1011 0x4B
uB0100_1100 0x4C
vB0100_1101 0x4D
wB0100_1110 0x4E
xB0100_1111 0x4F
zB0101_0000 0x50
{B0101_0001 0x51
|B0101_0010 0x52
}B0101_0011 0x53
~B0101_0100 0x54
B0101_0101 0x55
€
B0101_0110 0x56

B0101_0111 0x57
‚
B0101_1000 0x58
ƒ
B0101_1001 0x59
„
B0101_1010 0x5A
…
B0101_1011 0x5B
†
B0101_1100 0x5C
‡
B0101_1101 0x5D
ˆ
B0101_1110 0x5E
‰
B0101_1111 0x5F
‹
B0110_0000 0x60
Œ
B0110_0001 0x61

B0110_0010 0x62
Ž
B0110_0011 0x63

B0110_0100 0x64

B0110_0101 0x65
‘
B0110_0110 0x66
’
B0110_0111 0x67
“
B0110_1000 0x68
”
B0110_1001 0x69
•
B0110_1010 0x6A
–
B0110_1011 0x6B
—
B0110_1100 0x6C
˜
B0110_1101 0x6D
™
B0110_1110 0x6E
š
B0110_1111 0x6F
œ
B0111_0000 0x70

B0111_0001 0x71
ž
B0111_0010 0x72
Ÿ
B0111_0011 0x73
 
B0111_0100 0x74
¡
B0111_0101 0x75
¢
B0111_0110 0x76
£
B0111_0111 0x77
¤
B0111_1000 0x78
¥
B0111_1001 0x79
¦
B0111_1010 0x7A
§
B0111_1011 0x7B
¨
B0111_1100 0x7C
©
B0111_1101 0x7D
ª
B0111_1110 0x7E
«
B0111_1111 0x7F
­
B1000_0000 0x80
®
B1000_0001 0x81
¯
B1000_0010 0x82
°
B1000_0011 0x83
±
B1000_0100 0x84
²
B1000_0101 0x85
³
B1000_0110 0x86
´
B1000_0111 0x87
µ
B1000_1000 0x88
¶
B1000_1001 0x89
·
B1000_1010 0x8A
¸
B1000_1011 0x8B
¹
B1000_1100 0x8C
º
B1000_1101 0x8D
»
B1000_1110 0x8E
¼
B1000_1111 0x8F
¾
B1001_0000 0x90
¿
B1001_0001 0x91
À
B1001_0010 0x92
Á
B1001_0011 0x93
Â
B1001_0100 0x94
Ã
B1001_0101 0x95
Ä
B1001_0110 0x96
Å
B1001_0111 0x97
Æ
B1001_1000 0x98
Ç
B1001_1001 0x99
È
B1001_1010 0x9A
É
B1001_1011 0x9B
Ê
B1001_1100 0x9C
Ë
B1001_1101 0x9D
Ì
B1001_1110 0x9E
Í
B1001_1111 0x9F
Ï
B1010_0000 0xA0
Ð
B1010_0001 0xA1
Ñ
B1010_0010 0xA2
Ò
B1010_0011 0xA3
Ó
B1010_0100 0xA4
Ô
B1010_0101 0xA5
Õ
B1010_0110 0xA6
Ö
B1010_0111 0xA7
×
B1010_1000 0xA8
Ø
B1010_1001 0xA9
Ù
B1010_1010 0xAA
Ú
B1010_1011 0xAB
Û
B1010_1100 0xAC
Ü
B1010_1101 0xAD
Ý
B1010_1110 0xAE
Þ
B1010_1111 0xAF
à
B1011_0000 0xB0
á
B1011_0001 0xB1
â
B1011_0010 0xB2
ã
B1011_0011 0xB3
ä
B1011_0100 0xB4
å
B1011_0101 0xB5
æ
B1011_0110 0xB6
ç
B1011_0111 0xB7
è
B1011_1000 0xB8
é
B1011_1001 0xB9
ê
B1011_1010 0xBA
ë
B1011_1011 0xBB
ì
B1011_1100 0xBC
í
B1011_1101 0xBD
î
B1011_1110 0xBE
ï
B1011_1111 0xBF
ñ
B1100_0000 0xC0
ò
B1100_0001 0xC1
ó
B1100_0010 0xC2
ô
B1100_0011 0xC3
õ
B1100_0100 0xC4
ö
B1100_0101 0xC5
÷
B1100_0110 0xC6
ø
B1100_0111 0xC7
ù
B1100_1000 0xC8
ú
B1100_1001 0xC9
û
B1100_1010 0xCA
ü
B1100_1011 0xCB
ý
B1100_1100 0xCC
þ
B1100_1101 0xCD
ÿ
B1100_1110 0xCE
€B1100_1111 0xCF
‚B1101_0000 0xD0
ƒB1101_0001 0xD1
„B1101_0010 0xD2
…B1101_0011 0xD3
†B1101_0100 0xD4
‡B1101_0101 0xD5
ˆB1101_0110 0xD6
‰B1101_0111 0xD7
ŠB1101_1000 0xD8
‹B1101_1001 0xD9
ŒB1101_1010 0xDA
B1101_1011 0xDB
ŽB1101_1100 0xDC
B1101_1101 0xDD
B1101_1110 0xDE
‘B1101_1111 0xDF
“B1110_0000 0xE0
”B1110_0001 0xE1
•B1110_0010 0xE2
–B1110_0011 0xE3
—B1110_0100 0xE4
˜B1110_0101 0xE5
™B1110_0110 0xE6
šB1110_0111 0xE7
›B1110_1000 0xE8
œB1110_1001 0xE9
B1110_1010 0xEA
žB1110_1011 0xEB
ŸB1110_1100 0xEC
 B1110_1101 0xED
¡B1110_1110 0xEE
¢B1110_1111 0xEF
¤B1111_0000 0xF0
¥B1111_0001 0xF1
¦B1111_0010 0xF2
§B1111_0011 0xF3
¨B1111_0100 0xF4
©B1111_0101 0xF5
ªB1111_0110 0xF6
«B1111_0111 0xF7
¬B1111_1000 0xF8
­B1111_1001 0xF9
®B1111_1010 0xFA
¯B1111_1011 0xFB
°B1111_1100 0xFC
±B1111_1101 0xFD
²B1111_1110 0xFE
³B1111_1111 0xFF4*
 




..\Core\bintohex.h


´
..\Core\bintohex.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM


__DEFINEALL_H__ 
RCHFCLKCFG 8
clkmode 1
SYSCLKdef CMU_RCHFCR_FSEL_8MHZ
5uint08 uint8_t
6uint8 uint8_t
8uint16 uint16_t
9uint32 uint32_t
:int08 int8_t
;int16 int16_t
<int32 int32_t
CIN_NORMAL 0
DIN_PULLUP 1
IOUT_PUSHPULL 0
JOUT_OPENDRAIN 1
QALTFUN_NORMAL 0
RALTFUN_OPENDRAIN 1
SALTFUN_PULLUP 2
TALTFUN_OPENDRAIN_PULLUP 3XYZ[\]^_    
ý
 




..\Core\..\Core\Include\D:\Keil5\ARM\ARMCC\Bin\..\include\..\Hardware\CLOCK\..\Hardware\DELAY\define_all.h
FM33A0XXEV.hfm33a0xxev_include_all.h
stdio.hstdint.hstring.hbintohex.h
user_init.hdelay.h

œ

..\Core\define_all.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM
unsigned charSÜ

B08¶Bit!
PB08_BitÇ
-ˆ
SUCCESS_0ERROR_1
PErrorStatus_STM32ë
3*ž
!bit0¶#

!bit1¶#

!bit2¶#

!bit3¶#

!bit4¶#

!bit5¶#

!bit6¶#


!bit7¶#


!"#

__USER_INIT_H__ XN
 




..\Hardware\CLOCK\..\Core\user_init.h
define_all.h

À
..\Hardware\CLOCK\user_init.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM
%&'

_DELAY_H_ 
SYSTICK_CLOCK_SOURCE_SCLK 0xFFFFFF3F
SYSTICK_CLOCK_SOURCE_LSCLK 0xFFFFFF7F
SYSTICK_CLOCK_SOURCE_RFU 0xFFFFFFBF
    SYSTICK_CLOCK_SOURCE_SYSCLK 0xFFFFFFFF
SYSTICK_CLOCK_SOURCE_U_SCLK 0x00000000
SYSTICK_CLOCK_SOURCE_U_LSCLK 0x00000040
 SYSTICK_CLOCK_SOURCE_U_RFU 0x00000080
SYSTICK_CLOCK_SOURCE_U_SYSCLK 0x000000C0
SYSCLOCK_U 12000000\Q
 




..\Hardware\DELAY\..\Drivers\delay.h
fm33a0xxev_cmu.h

à
..\Hardware\DELAY\delay.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMintNÉ
»"ÂPConditionHookÉ

)*+

_MAIN_H_ 
OS_YEAR ((((__DATE__[7] - '0') * 10 + (__DATE__[8] - '0')) * 10 + (__DATE__[9] - '0')) * 10 + (__DATE__[10] - '0'))

OS_MONTH (__DATE__[2] == 'n' ? (__DATE__[1] == 'a' ? 1 : 6) : __DATE__[2] == 'b' ? 2 : __DATE__[2] == 'r' ? (__DATE__[0] == 'M' ? 3 : 4) : __DATE__[2] == 'y' ? 5 : __DATE__[2] == 'l' ? 7 : __DATE__[2] == 'g' ? 8 : __DATE__[2] == 'p' ? 9 : __DATE__[2] == 't' ? 10 : __DATE__[2] == 'v' ? 11 : 12)
OS_DAY ((__DATE__[4] == ' ' ? 0 : __DATE__[4] - '0') * 10 + (__DATE__[5] - '0'))
OS_HOUR ((__TIME__[0] - '0') * 10 + (__TIME__[1] - '0'))
OS_MINUTE ((__TIME__[3] - '0') * 10 + (__TIME__[4] - '0'))
OS_SENCOND ((__TIME__[6] - '0') * 10 + (__TIME__[7] - '0'))
"FW_VER_RESERVE 0x00
&FW_VER_MAIN 0x01
*FW_VER_MINOR 0x02
.FW_VER_REVISE 0x03
2HARDWARE_VERSION "02154.0203.3"
:FIRMWARE_VERSION "1.3.0.0"
HRS232_PRINTF 
WLCD_NEW 
\SYS_MODE_DEFAULT 8
`SYS_LCD_DISPLAY_MODE_DEFAULT 0
dSOFT_OR_HARD 0
iGET_FLOW_DATA_PERIOD_TIME 10
nSYS_WAKE_UP_TIME 30
sDISPLAY_PARA_TIME 300
xGPRS_TIMEOUT 120
}GPRS_RECONNECTION_INTERVAL_TIME 10
‚
UC_ACTIVE_TIME 600
‡
SET_PARA_MODE_TIMEOUT 10
Œ
CAL_MODE_TIMEOUT 20
‘
CAL_MODE_FORCE_TIME 480
•
GPRS_PROTOCOL_SELECT 1
™
GPRS_HISTORY_OR_REAL_DATA 1

KEY_VERSION 0x80
¡
NB_OR_4G_FLAG 0
¥
APN_SET_FLAG 0
©
IP_OR_YUMING_FLAG 0
®
AUTO_CALI_TIME_SEC_MAX 300
±
STANDARD_PRESSURE 101.325f
´
STANDARD_TEMPERATURE 293.15f
¸
CAL_TEST 
¾
FIRMWARE_VER_1 0x0000
¿
FIRMWARE_VER_2 0x0102
À
FIRMWARE_VER_3 0x0407@6
 




..\Core\main.h
define_all.h


°
..\Core\main.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM
-./0

_GPRS_SUNDRY_API_H_ 
SEND_DATA_PACK_MAX 4\S
 




..\Function\GPRS\..\Core\gprs_sundry_api.h
define_all.h


..\Function\GPRS\gprs_sundry_api.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM*™padding_length8
#padding_total_lengthV
#
plaintext_lengthV
#PGPRS_PROTOCOL_ENCRYPT_PARAÄ
*­
start_addrf
#send_data_log_save_cntV
#now_send_data_numV
#last_remain_data_numV
#PGPRS_SAVE_SEND_PARA_T;

Õ8

qKVer_AES_128Ê


qgprs_protocol_encrypt_para_g


@Õ
KVer_AES_128è
gprs_protocol_encrypt_para_g
2345

_ADMINISTRATOR_H_ 
__SYS_STATUS_BYTES_GET(__HANDLE__) ((&sys_admin_g)->sys_admin.state_bytes.__HANDLE__)
    __SYS_STATUS_BYTES_STATUS(__HANDLE__,__FLAG__,__ID__) do { if (__SYS_STATUS_BYTES_GET(__HANDLE__) != __FLAG__) { ((&sys_admin_g)->sys_admin.state_bytes.__HANDLE__ = __FLAG__); sys_clear_state_bytes_id_g = __ID__; Alarm_List_Node_Deleted(&pList_head,__ID__); } } while (0)
__SYS_ALARM_BYTES_SET(__HANDLE__,__FLAG__) ((&sys_admin_g)->sys_admin.alarm_bytes.__HANDLE__ = __FLAG__)
__SYS_STATUS_ALARM_BYTES_SET(__HANDLE__) do { if (__SYS_STATUS_BYTES_GET(__HANDLE__) != SET) (&sys_admin_g)->sys_admin.state_bytes.__HANDLE__ = (&sys_admin_g)->sys_admin.alarm_bytes.__HANDLE__ = SET; } while (0)
__SYS_FUNC_CFG_BYTES_GET(__HANDLE__) ((&sys_func_cfg_bytes_g)->sys_func_cfg_bytes_s.__HANDLE__)
 __SYS_ALARM_CTL_BYTES_GET(__HANDLE__) ((&sys_alarm_ctl_bytes_g)->sys_alarm_ctl_send.__HANDLE__)
"__SYS_ALARM_SEND_BYTES_GET(__HANDLE__) ((&sys_alarm_send_bytes_g)->sys_alarm_ctl_send.__HANDLE__)
$__SYS_ALARM_CTL_SEND_BYTES_SET(__HANDLE__,__FLAG__) do { if(__SYS_ALARM_CTL_BYTES_GET(__HANDLE__) != __FLAG__) (&sys_alarm_ctl_bytes_g)->sys_alarm_ctl_send.__HANDLE__ = (&sys_alarm_send_bytes_g)->sys_alarm_ctl_send.__HANDLE__ = __FLAG__; }while(0)
-SYS_STATUS_BYTES_TYPE_LENGTH sizeof(SYS_STATUS_T)
.SYS_ALARM_BYTES_TYPE_LENGTH sizeof(SYS_ALARM_T)
/SYS_ALARM_CTL_BYTES_TYPE_LENGTH SYS_ALARM_BYTES_TYPE_LENGTH
0SYS_ALARM_SEND_BYTES_TYPE_LENGTH SYS_ALARM_BYTES_TYPE_LENGTH
1SYS_FUNC_CTL_BYTES_TYPE_LENGTH sizeof(SYS_FUNC_CFG_UNION_T)
3SYS_ALARM_VALVE_ID_FUNC_TABLE_NUM_1 (sizeof(sys_av_id_tab_func_1) / sizeof(SYS_ALARM_VALVE_ID_FUNC_TABLE_DRV_T))
4SYS_ALARM_VALVE_ID_FUNC_TABLE_NUM_2 (sizeof(sys_av_id_tab_func_2) / sizeof(SYS_ALARM_VALVE_ID_FUNC_TABLE_DRV_T))
5SYS_ALARM_VALVE_ID_FUNC_TABLE_NUM_3 (sizeof(sys_av_id_tab_func_3) / sizeof(SYS_ALARM_VALVE_ID_FUNC_TABLE_DRV_T))
6SYS_ALARM_VALVE_ID_FUNC_TABLE_NUM_4 (sizeof(sys_av_id_tab_func_4) / sizeof(SYS_ALARM_VALVE_ID_FUNC_TABLE_DRV_T))
7SYS_ALARM_VALVE_ID_FUNC_TABLE_NUM_5 (sizeof(sys_av_id_tab_func_5) / sizeof(SYS_ALARM_VALVE_ID_FUNC_TABLE_DRV_T))
8SYS_ALARM_VALVE_ID_FUNC_TABLE_NUM_6 (sizeof(sys_av_id_tab_func_6) / sizeof(SYS_ALARM_VALVE_ID_FUNC_TABLE_DRV_T))
9SYS_ALARM_VALVE_ID_FUNC_TABLE_NUM_7 (sizeof(sys_av_id_tab_func_7) / sizeof(SYS_ALARM_VALVE_ID_FUNC_TABLE_DRV_T))
;ALARM_BYTES_DAILY_NUM 2¬dY
 




..\Soft\..\Core\administrator.h
define_all.hlinked_list.h


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..\Soft\administrator.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM•
VALVE_NONEVALVE_OP
VALVE_CLVALVE_OPENINGVALVE_CLOSINGVALVE_ERRORPVALVE_STATE_T¹
Eé
LDM_KEY_AWAKENLDM_ALWAYS_AWAKEN
LDM_FLOW_AWAKENPLCD_DISPLAY_MODE_T*

L¯
BM_NONEBM_DEVICE
BM_PLATFORMPBILLING_MODE_Tƒ

SÌ
PARA_AMEND_NONEGAS_CUMULATE_PARA_AMEND
BALANCE_PARA_AMENDTEMP_CFG_PARA_AMENDPRESS_CFG_PARA_AMENDBILLING_PARA_AMENDGAS_CAL_PARA_AMENDGAS_CFG_PARA_AMENDPLUSE_CAL_PARA_AMENDUT_ERR_PARA_AMEND    UT_CAL_PARA_AMEND
SYS_FUNC_CFG_BYTES_AMENDALARM_CTL_SEND_BYTES_AMENDVALVE_CTL_BYTES_AMEND BILLING_ALARM_CFG_AMENDSEC_ORDER_CORR_PARA_AMENDPPARA_AMEND_TÅ

g–AV_NORMALA_RESTART
AV_EXTERN_VCC_DOWNAV_UNCAP_1AV_UNCAP_2AV_GPRS_FAILAV_LCD_UPAV_LITH_LOWAV_LITH_UNDERAV_LITH_REMOVEAV_ALKA_LOWAV_ALKA_UNDERAV_ALKA_REMOVEAV_VALVE_VCC_LOWAV_VALVE_VCC_DOWNRTC_VCCAV_TEMP_ERR AV_TEMP_UP!AV_TEMP_UP_UP"AV_TEMP_DOWN#AV_TEMP_DOWN_DOWN$AV_PRESS_ERR%AV_PRESS_UP&AV_PRESS_UP_UP'AV_PRESS_DOWN(AV_PRESS_DOWN_DOWN)AV_CPU_TEMP_UP0AV_CPU_TEMP_DOWN1AV_CPU_TEMP_DRASTIC_CHANGE2AV_LCD_TEMP_LOW3AV_UT_LOSE@AV_FLOW_VEL_ERRAAV_TOF_DIFF_ERRBAV_SOUND_VEL_ERRCAV_SNR_ERRDAV_SIG_UPEAV_SIG_TH_ERRFAV_GAIN_ERRGAV_INPUT_WATER_ERRHAV_MEDIA_ERRIAV_DISMANTLEPAV_MEASURE_ERRQAV_FLOW_UP_1`AV_FLOW_UP_2aAV_FLOW_UP_3bAV_FLOW_DIRECTIONcAV_CONSTANT_FLOWdAV_CONSTANT_TINY_FLOWeAV_LEAKAGEfAV_VALVE_ERRpAV_CL_HAVE_FLOWqAV_BALANCE_1AV_BALANCE_2‘AV_BALANCE_3’AV_BALANCE_4“AV_BALANCE_5”AV_SET_CUMULATE•AV_NO_USE_GAS–AV_NO_GPRS—V_KEY_OP–    V_KEY_CL—    V_GPRS_CMD_OP˜    V_GPRS_CMD_CL™    PSYS_ALARM_VALVE_T`
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*Ë!lcd_modeV
#
!V
#

!account_stateV
#

!flow_directionV
#

!work_stateV
#
!V
#


!power_stateV
#


!V
#


!uncap_state_1V
#


!V
#

!valve_stateV
#
!valve_lockV
#

!set_cumulate_up_toV
#

!no_use_gas_date_up_toV
#

!no_gprs_date_up_toV
#


!virtual_billingV
#

!billing_typeV
#
!V
#

!balance_small_1V
#

!balance_small_2V
#

!balance_small_3V
#

!balance_small_4V
#


!balance_small_5V
#

!lith_lowV
#

!lith_underV
#

!lith_removeV
#

!alka_lowV
#

!alka_underV
#

!alka_removeV
#

!V
#
!gprs_statusV
#

!V
#
!temp_errV
#

!temp_upV
#

!temp_up_upV
#

!temp_downV
#

!temp_down_downV
#

!cpu_temp_upV
#

!cpu_temp_downV
#


!cpu_temp_drastic_changeV
#

!press_errV
#

!press_upV
#

!press_up_upV
#

!press_downV
#

!press_down_downV
#

!V
#
!flow_ver_errV
#

!tof_diff_errV
#

!sound_vel_errV
#

!snr_errV
#

!sig_upV
#

!sig_th_errV
#

!gain_errV
#


!ut_loseV
#

!media_statusV
#    
!input_waterV
#    

!measure_errV
#    

!V
#    
!gas_leakageV
#


!lcd_upV
#


!lcd_temp_lowV
#


!flow_up_1V
#


!flow_up_2V
#


!flow_up_3V
#


!constant_tiny_flowV
#



!constant_flowV
#


!cl_have_flowV
#

!V
#
PSYS_STATUS_T°
€*‚*!V
#
!account_stateV
#

!flow_directionV
#

!V
#
!restartV
#


!power_stateV
#


!V
#


!uncap_state_1V
#


!V
#

!valve_errorV
#

!valve_changeV
#

!V
#
!set_cumulate_up_toV
#

!no_use_gas_date_up_toV
#

!no_gprs_date_up_toV
#


!V
#!balance_small_1V
#

!balance_small_2V
#

!balance_small_3V
#

!balance_small_4V
#


!balance_small_5V
#

!lith_lowV
#

!lith_underV
#

!lith_removeV
#

!alka_lowV
#

!alka_underV
#

!alka_removeV
#

!V
#
!gprs_statusV
#

!V
#
!temp_errV
#

!temp_upV
#

!temp_up_upV
#

!temp_downV
#

!temp_down_downV
#

!cpu_temp_upV
#

!cpu_temp_downV
#


!cpu_temp_drastic_changeV
#

!press_errV
#

!press_upV
#

!press_up_upV
#

!press_downV
#

!press_down_downV
#

!V
#
!flow_vel_errV
#

!tof_diff_errV
#

!sound_vel_errV
#

!snr_errV
#

!sig_upV
#

!sig_th_errV
#

!gain_errV
#


!ut_loseV
#

!input_waterV
#    

!media_otherV
#    

!dismantleV
#    

!measure_errV
#    

!V
#    
!gas_leakageV
#


!lcd_upV
#


!lcd_temp_lowV
#


!flow_up_1V
#


!flow_up_2V
#


!flow_up_3V
#


!constant_tiny_flowV
#



!constant_flowV
#


!cl_have_flowV
#

!V
#
!gas_cumulate_amendV
#

!balance_amendV
#

!temp_para_amendV
#

!press_para_amendV
#

!billing_para_amendV
#

!V
#
!flow_cal_amendV
# 

!flow_para_amendV
# 

!pluse_cal_amendV
# 

!ut_err_amendV
# 

!ut_cal_amendV
# 

!V
# 
PSYS_ALARM_Tà 
ÙSÖ*¥*V

alarm_ctl_send_unionsys_alarm_ctl_sendPSYS_ALARM_CTL_SEND_UNION_T
ß*Ú/!V
#
!small_flow_excisionV
#

!V
#

!both_way_measureV
#

!lcd_modeV
#

!V
#

!set_compressibilityV
#
!V
#

!press_corrected_manageV
#
!press_err_manageV
#
!V
#
!temp_corrected_manageV
#
!temp_err_manageV
#
!super_flow_manage_3V
#

!super_flow_manage_2V
#

!V
#!V
#
!virtual_billingV
#

!V
#
!account_stateV
#

!V
#
!balance_display_setV
#

!price_display_setV
#

!logo_display_setV
#

!V
#
!billing_typeV
#
S–0é/V

func_cfg_unionÞsys_func_cfg_bytes_syPSYS_FUNC_CFG_UNION_TÚ
„*Þ0state_bytes^#alarm_bytesb#tË tS”1õ0V

admin_unionjsys_admin3PSYS_ADMIN_UNION_Tf
Ž*„2    alarm_valve_id#offset_bit#alarm_daily_num#alarm_byte#–8
tV
"V
PSYS_ALARM_VALVE_ID_FUNC_TABLE_DRV_T®
–qsys_para_amend_log_flag_gL

qsys_alarm_id_g–

qsys_valve_ctl_id_g–

qsys_admin_g”

qsys_alarm_ctl_bytes_gV

qsys_alarm_send_bytes_gV

qsys_func_cfg_bytes_g

´üFsys_para_amend_log_flag_gfsys_alarm_id_g{sys_valve_ctl_id_g”sys_admin_g¦sys_alarm_ctl_bytes_gÂsys_alarm_send_bytes_gßsys_func_cfg_bytes_g
789:

_LINKED_LIST_H_ 
ALARM_LIST_NODE_LEN sizeof(ALARM_NODE_T)dY
 




..\Soft\..\Core\linked_list.h
define_all.hadministrator.h


8

..\Soft\linked_list.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM)ó
alarm_node_slist_data–#alarm_list_nextó#"·PALARM_NODE_T·
qalarm_list_cnt8


"÷qpList_head"


0<

alarm_list_cnt&
pList_head
<=>?

_RTC_H_ PF
 




..\Hardware\RTC\..\Core\rtc.h
define_all.h

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..\Hardware\RTC\rtc.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMt)
qcalendar_g·

нcalendar_g
ABCD

_EXTERN_RTC_H_ 
 TIMER_COUNTER_0 0
TIMER_COUNTER_1 0
EXTENSION_TIMER_SELECT 0x02
FOUT_FRE_SELECT 0x0
 TIMER_EN 0x00
$UPDATA_INTER_SELECT 0x0
(ALARM_BIT_FLAG 0
,TEST_BIT_FLAG 0
0FLAG_REG 0
5RESET_BIT_FLAG 0x0
9ALARM_BIT_EN 0x0
=TIMER_BIT_FLAG 0x00
AUPDATA_BIT_FLAG 0x000000
ETEMP_BIT_FLAG 0x0000040
LRX8025_WRITE_ADDR 0x64
MRX8025_READ_ADDR 0x65xn
 




..\Function\EXTERN_RTC\..\Core\..\Hardware\RTC\extern_rtc.h
define_all.hrtc.h

`

..\Function\EXTERN_RTC\extern_rtc.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM*°second8
#minute8
#
hour8
#week8
#day8
#month8
#yearV
#PCALENDAR_TIME_TÅ
]t0
qcalendar_test_gG


"d
K
calendar_test_g
FGHI

_KEY_H_ 
KEYA_S1_PORT GPIOD
KEYA_S1_PIN GPIO_Pin_6
    KEYB_S2_PORT GPIOD

KEYB_S2_PIN GPIO_Pin_8
KEYC_S3_PORT GPIOA
 KEYC_S3_PIN GPIO_Pin_0
KEY_A_READ GPIO_ReadInputDataBit(KEYA_S1_PORT,KEYA_S1_PIN)
KEY_B_READ GPIO_ReadInputDataBit(KEYB_S2_PORT,KEYB_S2_PIN)
KEY_C_READ GPIO_ReadInputDataBit(KEYC_S3_PORT,KEYC_S3_PIN)PF
 




..\Function\KEY\..\Core\key.h
define_all.h

Ð
..\Function\KEY\key.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMqkey_awaken_flag_gÓ

$Ô·key_awaken_flag_g
KLM

_LCD_SEGMENTCODE_23A_H_ 
LCD_NEW 
_LCD_SIZHULOG_23A 276
_LCD_BATTERY_SHELL_23A 277
_LCD_BATTERY_4_23A 278
_LCD_BATTERY_3_23A 279
_LCD_BATTERY_2_23A 271
_LCD_BATTERY_1_23A 270
!_LCD_METER_23A 269
"_LCD_SIGNAL_COMMUNICATION_23A 268
#_LCD_VALVE_M_23A 5
$_LCD_LOCK_23A 6
%_LCD_OPEN_23A 7
&_LCD_CLOSE_23A 4
)_LCD_WIFI_23A 63
*_LCD_4G_Flag_23A 71
+_LCD_4G_1_23A 70
,_LCD_4G_2_23A 69
-_LCD_4G_3_23A 77
._LCD_4G_4_23A 78
/_LCD_4G_5_23A 79
0_LCD_WARNING_23A 87
2_LCD_CONFIGURATION_23A 74
3_LCD_T_23A 73
4_LCD_CHARGE_23A 72
5_LCD_LOOKUP_23A 80
6_LCD_BACKSET_23A 75
7_LCD_K_23A 66
8_LCD_BOOTTOOTH_23A 65
9_LCD_CHECK_23A 64
;_LCD_HORIZONTALLINE_1_23A 60
<_LCD_SINGLEBILL_23A 68
=_LCD_LADDERBILL_23A 76
>_LCD_HORIZONTALLINE_2_23A 67
@_LCD_WORK_CONDITION_23A 2
A_LCD_SURPLUSE_23A 3
B_LCD_STAND_CONDITION_23A 1
C_LCD_TOTAL_23A 0
E_LCD_X_23A 275
F_LCD_ACCOUNT_23A 274
G_LCD_BILLBACK_23A 273
I_LCD_LAST_23A 266
J_LCD_RECHARGE_23A 267
K_LCD_SETTLEMENT_23A 260
L_LCD_NOW_23A 272
M_LCD_LADDER_23A 265
N_LCD_UNIT_PRICE_23A 264
P_LCD_N_1_23A 139
Q_LCD_M3_1_23A 130
R_LCD_YUAN_1_23A 131
T_LCD_kPa_23A 140
U_LCD_oC_23A 129
V_LCD_L_pul_23A 128
W_LCD_N_2_23A 142
X_LCD_M3_2_23A 135
Y_LCD_h_23A 134
Z_LCD_YUAN_2_23A 133
[_LCD_YUAN_M3_23A 132
b_LCD_POINT1_23A 19
c_LCD_POINT2_23A 24
d_LCD_POINT3_23A 258
e_LCD_POINT4_23A 256
f_LCD_POINT5_23A 242
g_LCD_POINT6_23A 240
h_LCD_POINT7_23A 227
i_LCD_POINT8_23A 224
j_LCD_POINT9_23A 211
k_LCD_POINT10_23A 200
l_LCD_POINT11_23A 186
m_LCD_POINT12_23A 184
n_LCD_POINT13_23A 170
o_LCD_POINT14_23A 168
p_LCD_POINT15_23A 155
q_LCD_POINT16_23A 152
r_LCD_POINT17_23A 245
s_LCD_POINT18_23A 247
t_LCD_POINT19_23A 229
u_LCD_POINT20_23A 231
v_LCD_POINT21_23A 212
w_LCD_POINT22_23A 215
x_LCD_POINT23_23A 196
y_LCD_POINT24_23A 191
z_LCD_POINT25_23A 173
{_LCD_POINT26_23A 175
|_LCD_POINT27_23A 157
}_LCD_POINT28_23A 159
‚
_LCD_1A_new 15
ƒ
_LCD_1B_new 23
„
_LCD_1C_new 21
…
_LCD_1D_new 12
†
_LCD_1E_new 13
‡
_LCD_1F_new 14
ˆ
_LCD_1G_new 22
Š
_LCD_2A_new 31
‹
_LCD_2B_new 62
Œ
_LCD_2C_new 61

_LCD_2D_new 28
Ž
_LCD_2E_new 20

_LCD_2F_new 30

_LCD_2G_new 29
’
_LCD_3A_new 95
“
_LCD_3B_new 94
”
_LCD_3C_new 93
•
_LCD_3D_new 92
–
_LCD_3E_new 84
—
_LCD_3F_new 86
˜
_LCD_3G_new 85
š
_LCD_4A_new 88
›
_LCD_4B_new 81
œ
_LCD_4C_new 83

_LCD_4D_new 91
ž
_LCD_4E_new 90
Ÿ
_LCD_4F_new 89
 
_LCD_4G_new 82
¢
_LCD_5A_new 11
£
_LCD_5B_new 18
¤
_LCD_5C_new 16
¥
_LCD_5D_new 8
¦
_LCD_5E_new 9
§
_LCD_5F_new 10
¨
_LCD_5G_new 17
ª
_LCD_6A_new 59
«
_LCD_6B_new 58
¬
_LCD_6C_new 57
­
_LCD_6D_new 56
®
_LCD_6E_new 25
¯
_LCD_6F_new 27
°
_LCD_6G_new 26
²
_LCD_7A_new 251
³
_LCD_7B_new 243
´
_LCD_7C_new 249
µ
_LCD_7D_new 248
¶
_LCD_7E_new 257
·
_LCD_7F_new 259
¸
_LCD_7G_new 250
º
_LCD_8A_new 235
»
_LCD_8B_new 226
¼
_LCD_8C_new 225
½
_LCD_8D_new 232
¾
_LCD_8E_new 241
¿
_LCD_8F_new 234
À
_LCD_8G_new 233
Â
_LCD_9A_new 219
Ã
_LCD_9B_new 210
Ä
_LCD_9C_new 208
Å
_LCD_9D_new 216
Æ
_LCD_9E_new 217
Ç
_LCD_9F_new 218
È
_LCD_9G_new 209
Ê
_LCD_10A_new 195
Ë
_LCD_10B_new 194
Ì
_LCD_10C_new 193
Í
_LCD_10D_new 192
Î
_LCD_10E_new 201
Ï
_LCD_10F_new 203
Ð
_LCD_10G_new 202
Ò
_LCD_11A_new 179
Ó
_LCD_11B_new 171
Ô
_LCD_11C_new 177
Õ
_LCD_11D_new 176
Ö
_LCD_11E_new 185
×
_LCD_11F_new 187
Ø
_LCD_11G_new 178
Ú
_LCD_12A_new 163
Û
_LCD_12B_new 154
Ü
_LCD_12C_new 153
Ý
_LCD_12D_new 160
Þ
_LCD_12E_new 169
ß
_LCD_12F_new 162
à
_LCD_12G_new 161
â
_LCD_13A_new 147
ã
_LCD_13B_new 138
ä
_LCD_13C_new 136
å
_LCD_13D_new 144
æ
_LCD_13E_new 145
ç
_LCD_13F_new 146
è
_LCD_13G_new 137
ê
_LCD_14A_new 252
ë
_LCD_14B_new 253
ì
_LCD_14C_new 254
í
_LCD_14D_new 255
î
_LCD_14E_new 263
ï
_LCD_14F_new 261
ð
_LCD_14G_new 262
ò
_LCD_15A_new 236
ó
_LCD_15B_new 228
ô
_LCD_15C_new 238
õ
_LCD_15D_new 239
ö
_LCD_15E_new 246
÷
_LCD_15F_new 244
ø
_LCD_15G_new 237
ú
_LCD_16A_new 220
û
_LCD_16B_new 213
ü
_LCD_16C_new 214
ý
_LCD_16D_new 223
þ
_LCD_16E_new 230
ÿ
_LCD_16F_new 221
€_LCD_16G_new 222
‚_LCD_17A_new 204
ƒ_LCD_17B_new 197
„_LCD_17C_new 199
…_LCD_17D_new 207
†_LCD_17E_new 206
‡_LCD_17F_new 205
ˆ_LCD_17G_new 198
Š_LCD_18A_new 180
‹_LCD_18B_new 181
Œ_LCD_18C_new 182
_LCD_18D_new 183
Ž_LCD_18E_new 190
_LCD_18F_new 188
_LCD_18G_new 189
’_LCD_19A_new 164
“_LCD_19B_new 156
”_LCD_19C_new 166
•_LCD_19D_new 167
–_LCD_19E_new 174
—_LCD_19F_new 172
˜_LCD_19G_new 165
š_LCD_20A_new 148
›_LCD_20B_new 141
œ_LCD_20C_new 143
_LCD_20D_new 151
ž_LCD_20E_new 158
Ÿ_LCD_20F_new 149
 _LCD_20G_new 150XL
 




..\Function\LCD\..\Core\lcd_segmentcode.h
main.h

ø

..\Function\LCD\lcd_segmentcode.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMæ
LOOKUPT
CONFIGURATIONCHECKKBACKSETWORKCONDITIONSURPLUSESTANDCONDITIONTOTAL    N_1
M3_1YUAN_1LAST RECHARGESETTLEMENTNOWLADDERUNITPRICEXHOMECLOUDkPaoCLpulN_2M3_2HYUAN_2YUAN_M3P_LCD_FLAGÃ
Á
OPQR

_LCD_IO_API_H_ 
Segnum 48
LCD_WRITE 0x7C
LCD_READ 0x7D
LCD_REG_DATA 0x80
!LCD_PWR_GPIO_PORT GPIOB
"LCD_PWR_PIN GPIO_Pin_6
$LCD_BACKLIGHT_PWR_GPIO_PORT GPIOB
%LCD_BACKLIGHT_PWR_PIN GPIO_Pin_5
(LCD_PWR_ON GPIO_SetBits(LCD_PWR_GPIO_PORT,LCD_PWR_PIN)
)LCD_PWR_OFF GPIO_ResetBits(LCD_PWR_GPIO_PORT,LCD_PWR_PIN)
,LCD_BACKLIGHT_ON GPIO_SetBits(LCD_BACKLIGHT_PWR_GPIO_PORT,LCD_BACKLIGHT_PWR_PIN)
-LCD_BACKLIGHT_OFF GPIO_ResetBits(LCD_BACKLIGHT_PWR_GPIO_PORT,LCD_BACKLIGHT_PWR_PIN)
6LCD_DISPLAY_SEG(__SEG_NUM__) LCD_buffer[__SEG_NUM__ >> 3] |= 1 << (__SEG_NUM__ % 8)
?LCD_CLEAR_SEG(__SEG_NUM__) LCD_buffer[__SEG_NUM__ >> 3] &= ~(1 << (uint8_t)(__SEG_NUM__ % 8))lb
 




..\Function\LCD\..\Core\lcd_io_api.h
define_all.hlcd_segmentcode.h


Ü

..\Function\LCD\lcd_io_api.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM­
LCD_ALCD_B
LCD_CLCD_DLCD_ELCD_FLCD_GLCD_HLCD_ILCD_J    LCD_K
LCD_LLCD_MLCD_N LCD_OLCD_PLCD_QLCD_RLCD_SLCD_TLCD_ULCD_VLCD_WLCD_XLCD_YLCD_ZPLCD_LETTERS_T¾
]Í8

/qLCD_bufferÂ


à
Í
LCD_buffer
TUVW

_LCD_H_ 
LCD_BACKLIGHT_SELECT(__ALKA_STATE__) ((__ALKA_STATE__ == RESET) ? LCD_BACKLIGHT_ON : LCD_BACKLIGHT_OFF)
LCD_ALL_CLEAR Lcd_Write_Reg(0,LCD_SYSTEM_MODE_OFF_OFF,Segnum)
LCD_ALL_DISPLAY Lcd_Write_Reg(0,LCD_buffer,Segnum)˜Œ
 




..\Function\LCD\..\Core\..\Function\KEY\..\Soft\lcd.h
define_all.hkey.hadministrator.hlcd_io_api.h


ô
..\Function\LCD\lcd.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMÓ
CNV_NONECNV_PARA_MODE_ENTER
CNV_CAL_MODE_ENTERCNV_PARA_MODE_EXITCNV_CAL_MODE_EXITCNV_DISPLAY_MODE_ENTERCNV_DISPLAY_MODE_EXITPTEMP_SYS_MODE_CNV_CMD·
&³
NORMAL_MODE
DISPLAY_PARACALIB_MODESET_PARA_MODEPSYS_DISPLAY_MODEp

-˜
SC_INSTANT_TOTALPRICE_BALANCE
TEMP_SC_TOTALPRESS_SC_TOTALPNORMAL_PAGEË

5 
METER_NUMOTHER_METER_NUM
DATE_TIMEIP_PORTOTHER_IP_PORTSW_VERHW_VERSOUND_VELSEC_CORR_NOWSEC_CORR_NOW_PARA_1    SEC_CORR_NOW_PARA_2
SEC_CORR_NOW_PARA_3SEC_CORR_NOW_PARA_4SEC_CORR_NOW_PARA_5 SEC_CORR_OLDSEC_CORR_OLD_PARA_1SEC_CORR_OLD_PARA_2SEC_CORR_OLD_PARA_3SEC_CORR_OLD_PARA_4SEC_CORR_OLD_PARA_5PPARA_DISPLAY_PAGE+
L*ðnormal_page_status#para_page_status #
PNORMAL_DISPLAY_PAGE_T¹
S*ãtemp_sys_mode_flagS
#sys_and_display_mode³
#
display_page_statusð#PSYS_DISPLAY_PAPA_T 
Yqsys_display_para_gc

qsys_show_state_bytes_id_g–

qsys_clear_state_bytes_id_g–

qlcd_wake_up_flag_g8


yø}sys_display_para_g–sys_show_state_bytes_id_g¸sys_clear_state_bytes_id_gÛlcd_wake_up_flag_g
YZ[\

_SYSTEM_PARAMETER_H_ 
    __SYS_PARA_FLAG_SET_(__HANDLE__) ((&sys_some_flag_g)->__HANDLE__ = SET)
__SYS_PARA_FLAG_CLEAR_(__HANDLE__) ((&sys_some_flag_g)->__HANDLE__ = RESET)
 LINEAR_FUNC_OF_ONE_VARIABLE(__SLOPE__,__INTERCEPT__,__VALVE__) ((__SLOPE__ * __VALVE__) + __INTERCEPT__)
LCD_SHOW_NUM_MAX 1000000
SYS_FLOW_UP_3_VALUE 1.25f
SYS_TEMP_ERROR_VALUE 0xFFFF
SYS_TEMP_MEASURE_MAX 40
SYS_TEMP_MEASURE_MIN (-15)
SYS_PRESS_ERROR_VALUE 0xFFFF
SYS_PRESS_MEASURE_MAX 130.0f
SYS_PRESS_MEASURE_MIN 70.0f
BARO_PRESS 100.0f
G4_FLOW_MIN 0.04f
G4_FLOW_MAX 6
 G6_FLOW_MIN 0.06f
!G6_FLOW_MAX 10
"G10_FLOW_MIN 0.10f
#G10_FLOW_MAX 16
$G16_FLOW_MIN 0.16f
%G16_FLOW_MAX 25
&G25_FLOW_MIN 0.25f
'G25_FLOW_MAX 40
(G40_FLOW_MIN 0.40f
)G40_FLOW_MAX 65
cSEC_ORDER_CORR_PARA_FORMAT_SIZE sizeof(SECOND_ORDER_CORR_T)
jSYS_CAL_PULSE_PARA_FORMAT_SIZE sizeof(CAL_PULSE_PARA_T)
rSYS_FLOW_ALARM_CFG_FORMAT_SIZE sizeof(SYS_FLOW_ALARM_CFG_T)
|SYS_PRESS_ALARM_CFG_FORMAT_SIZE sizeof(SYS_PRESS_ALARM_CFG_T)
‹
SYS_TEMP_ALARM_CFG_FORMAT_SIZE sizeof(SYS_TEMP_ALARM_CFG_T)
œ
MASTER_SOFT_HARD_FORMAT_SIZE sizeof(MASTER_SOFT_HARD_PARA_T)
¨
MASTER_BASIC_FORMAT_SIZE sizeof(MASTER_BASIC_PARA_T)
²
REALTIME_DATA_FORMAT_SIZE sizeof(SYS_REAL_TIME_DATA_T)˜
 




..\Soft\..\Core\..\Function\EXTERN_RTC\..\Function\LCD\system_parameter.h
define_all.hextern_rtc.hlcd.h

(
..\Soft\system_parameter.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMfloatdoublePMEDIA_STATUS¡
1PCALI_PULSE_FACTOR_TÔ
:PDEVICE_TYPE 
CPDEVICE_MODEL} 
SPSYS_TIME_TT
[PSYS_SOME_FLAG_T
aPSECOND_ORDER_CORR_TÃ
h*»cal_pulse_factorV
#cal_pulse_widthV
#«8

reserve 
#PCAL_PULSE_PARA_Ti

p*ósys_flow_up_1¼#sys_flow_up_2¼#sys_flow_down_1¼#flow_up_2_replace_value¼#small_flow_excision_value¼#ã8

reserveX#PSYS_FLOW_ALARM_CFG_TÓ

{*•,press_correction_factor¼#press_intercept¼#press_up_value¼#press_up_up_value¼#press_down_value¼#press_down_down_value¼#press_up_scope¼#press_down_scope¼#press_down_down_replace¼# …8

reservez#$PSYS_PRESS_ALARM_CFG_T
Š
*
&temp_correction_factor¼#temp_intercept¼#temp_up_value
#temp_up_up_value
#
temp_down_value
#temp_down_down_value
#temp_up_scope
#temp_down_scope
#temp_up_up_replace
#temp_drastic_change¼#cpu_temp_up_scope
#cpu_temp_down_scope
#ý    8

reserveò#PSYS_TEMP_ALARM_CFG_T³
›
*¥"¹
8

master_pcb_num.#Ú
8

master_pcb_typeO#ü
8

master_hardware_verq#
¢8

master_firmware_ver—#È8


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master_firmware_timeã#•8

    reserve
#PMASTER_SOFT_HARD_PARA_T*
¦
*Û 5device_type_bcd
#plant_code_bcdV
#
ƒ 8

    factory_numberx#¤ 8

specifications_model™# Ë 8

reserveÀ#!PMASTER_BASIC_PARA_TE
°
)Œmeasure_para`forward_cumulate_scÅ#forward_cumulate_wcÅ#ÇÅ

cal_cumulate_reserve>#ìÅ

err_forward_cumulate_reservec# instant_wc¼#0instant_wc_avg¼#4instant_sc¼#8temperature¼#<temp_amend¼#@temp_avg¼#Dpressure¼#Hpress_amend¼#Lpress_avg¼#Pcompressibility_factor¼#TC_coefficient_reserve¼#XK_coefficient_reserve¼#\)ótime_parayear8
#month8
#
day8
#hour8
#minute8
#second8
#)Çstate_para&cpu_temperature¼#lith_vcc8
#alka_vcc8
#tof_up¼#tof_down¼#
tof_diff¼#signal_intensity_up8
#signal_intensity_down8
#signal_gain_up8
#signal_gain_down8
#snr_upV
#snr_downV
#real_line_aV
#real_line_bV
#sound_vel¼#flow_vel¼#"*ŠŒ
measure_para_s÷#time_para_sŒ#`state_para_só#fPSYS_REAL_TIME_DATA_TG

ä
qsys_device_flow_min_g¼

qsys_device_flow_qt_g¼

tV
qauto_exit_start_min_time_gÞ


qcal_mode_exit_cnt_gÞ


qcal_mode_force_exit_cnt_gÞ


qsys_device_flow_max_g8


qcal_mode_exit_save_cumulate_flag_g8


qsys_time_g%


qsys_some_flag_g7


qmaster_soft_hard_para_g%

qsys_realtime_data_gŠ


qsys_flow_alarm_cfg_gs

qsys_press_alarm_cfg_g•

qsys_temp_alarm_cfg_g 

qcal_pulse_para_g»


qmaster_basic_papa_gÛ

qsec_order_corr_set_gN


qsec_order_corr_real_gN


Ô
MEDIA_UNKNOWNMEDIA_OTHER
AIRGAS—CPF_ONE_TENTH
CPF_1LdCPF_5Lô
CPF_10LèCPF_20Lˆý
DT_NONEDT_HOLISTIC_METER
DT_HOLISTIC_CTL_METERDT_SPLIT_METERDT_SPLIT_CTL_METERÔ
DM_NONEDM_HM_UFG610
DM_HM_UFG620DM_HCM_UFG210DM_SCM_SZV101DM_SM_DTU100DM_SCM_SZV102DM_SCM_SZV103DM_HM_UFG630DM_HM_UFG220    DM_HCM_UFG220
DM_HCM_UFG620DM_HCM_UFG630*‰sys_run_period‰#sys_cal_run_period‰#
tÓ*Ãpara_display_flagÓ#uncap_flagÓ#
*ªPм
second_flow_data_pointÇ#÷¼
second_corr_factorî#š¼
    reserve#(Ú
,§
sys_device_flow_min_gÃ
sys_device_flow_qt_gä
auto_exit_start_min_time_gcal_mode_exit_cnt_gcal_mode_force_exit_cnt_g?sys_device_flow_max_g]cal_mode_exit_save_cumulate_flag_gˆsys_time_g™sys_some_flag_g¯master_soft_hard_para_gÍsys_realtime_data_gçsys_flow_alarm_cfg_gsys_press_alarm_cfg_gsys_temp_alarm_cfg_g9cal_pulse_para_gPmaster_basic_papa_gjsec_order_corr_set_g…sec_order_corr_real_g
^_`

_GPRS_PROTOCOL_IDEACREATED_GASMETER_API_H_ 

PROTOCOL_HEAD_LENGTH sizeof(GPRS_PROTOCOL_HEAD_T)
PROTOCOL_TAIL_LENGTH sizeof(GPRS_PROTOCOL_TAIL_T)
PROTOCOL_NORMAL_DATA_HEAD_LENGTH sizeof(GPRS_PROTOCOL_NORMAL_DATA_HEAD_T)
PROTOCOL_NORMAL_DATA_PACK_LENGTH sizeof(GPRS_PROTOCOL_NORMAL_DATA_PACK_T)
PROTOCOL_NORMAL_DATA_PACK_1_LENGTH sizeof(GPRS_PROTOCOL_NORMAL_DATA_PACK_1_T)
PROTOCOL_NORMAL_DATA_PACK_2_LENGTH sizeof(GPRS_PROTOCOL_NORMAL_DATA_PACK_2_T)
PROTOCOL_SET_CMD_DATA_BACK_LENGTH 1
PROTOCOL_FUNC_PARA_LENGTH sizeof(struct func_para)
PROTOCOL_SEND_CFG_LENGTH sizeof(struct send_cfg)
PROTOCOL_IP_PARA_LENGTH sizeof(struct ip_para)
PROTOCOL_DEVICE_INFO_LENGTH sizeof(struct device_info)
PROTOCOL_BALANCE_ALARM_LENGTH sizeof(struct balance_alarm_para)
PROTOCOL_FLOW_CLOSE_LENGTH sizeof(struct cumulate_flow_close_para)
PROTOCOL_START_CODE 0x68
PROTOCOL_END_CODE 0x16
PROTOCOL_VERSION 0x40
 DATA_START_CODE 0x55
"PROTOCOL_NORMAL_SEND_CMD_U16 0x0101
#PROTOCOL_END_CMD_U16 0x0102
$PROTOCOL_OPERATION_KEY_U16 0x0103
%PROTOCOL_BACKSETTLE_INFO_U16 0x0104
&PROTOCOL_STARTEND_COUNT_U16 0x0201
'PROTOCOL_SET_FUN_PARA_U16 0x0202
(PROTOCOL_READ_FUN_PARA_U16 0x0203
)PROTOCOL_SET_ALARM_COUNT_U16 0x0204
*PROTOCOL_READ_ALARM_COUNT_U16 0x0205
+PROTOCOL_SET_SEND_CYCLE_U16 0x0206
,PROTOCOL_READ_SEND_CYCLE_U16 0x0207
-PROTOCOL_SET_METER_PARA_U16 0x0208
.PROTOCOL_READ_METER_PARA_U16 0x0209
/PROTOCOL_READ_EQUIP_PARA_U16 0x0220
0PROTOCOL_SET_TIME_CMD_U16 0x0221
1PROTOCOL_SET_IP_U16 0x0222
2PROTOCOL_READ_IP_U16 0x0223
3PROTOCOL_CLEAR_EXCEPTION_U16 0x0224
4PROTOCOL_CLEAR_COUNT_U16 0x0225
5PROTOCOL_SAVE_TIME_POINT_U16 0x0230
6PROTOCOL_READ_TIME_POINT_U16 0x0231
7PROTOCOL_READ_HISTORY_U16 0x0232
8PROTOCOL_READ_VALVE_RECORD_U16 0x0233
9PROTOCOL_READ_MODIFY_ACC_RECORD 0x0234
:PROTOCOL_CONT_VALVE 0x0301
;PROTOCOL_SET_BALANCE_CLOSE_VALVE 0x0302
<PROTOCOL_READ_BALANCE_CLOSE_VALVE 0x0303
=PROTOCOL_SET_CLOSE_VALVE 0x0304
>PROTOCOL_READ_CLOSE_VALVE 0x0305
?PROTOCOL_SET_DONT_REPORT_CLOSE_VALVE 0x0306
@PROTOCOL_READ_DONT_REPORT_CLOSE_VALVE 0x0307
APROTOCOL_SET_DONT_USE_GAS_DAY 0x0308
BPROTOCOL_READ_DONT_USE_GAS_DAY 0x0309
CPROTOCOL_SET_COUNT_CLOSE_VALVE 0x0310
DPROTOCOL_READ_NO_COUNT_CLOSE_VALVE 0x0311
FPROTOCOL_PAY_MONEYS_U16 0x0401
GPROTOCOL_ADJUST_PRICE_U16 0x0402
HPROTOCOL_READ_PRICE_U16 0x0403
JPROTOCOL_APP_RESET_U16 0x9600
KPROTOCOL_APP_CONFIG_U16 0x9601
LPROTOCOL_APP_DIFF_DATA_U16 0x9602
MPROTOCOL_APP_CONFIG_CHECK_U16 0x9603
NPROTOCOL_APP_DIFF_MAP_U16 0x9604
QGPRS_PROTOCOL_SEND_FUNC_TABLE_NUM sizeof(gprs_protocol_send_tab_func) / sizeof(GPRS_PROTOCOL_SEND_FUNC_TABLE_DRV_T)
RGPRS_PROTOCOL_RECV_FUNC_TABLE_NUM sizeof(gprs_protocol_recv_tab_func) / sizeof(GPRS_PROTOCOL_RECV_FUNC_TABLE_DRV_T)¼±
 




..\Function\GPRS\..\Core\..\Soft\gprs_protocol_ideacreated_gasmeter_api.h
define_all.hgprs_sundry_api.h
administrator.hsystem_parameter.h

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..\Function\GPRS\gprs_protocol_ideacreated_gasmeter_api.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMlong longfloat)Ìcumulate_flow_close_paraset_cumulate_flow_valuef
#valve_control_type8
#)»price_cfgprice_verV
#set_price_type_mode8
#normal_price_nowf
#period_state8
#)device_infoMÖ8

device_iccidË
#õ8

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#device_net_info8
##¬8

device_hardware_ver_bcd!#$Ö8

device_software_ver_bcdK#)€8

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‡union_buff•»8

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secret_keys»settle_data_s‰account_state8
func_para_s˜send_cfg_sHip_para_sCbalance_alarm_para_spay_moneys_para_sEcumulate_flow_close_para_sñprice_cfg_sL
device_info_s»
PGPRS_PROTOCOL_STATUSB
rPGPRS_PROTOCOL_SEND_BUFFER_TU
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*ç    frame_start_code8
#8

device_num#
data_start_code8
#    Ó8

device_timeH#
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#cmd_code_u16V
#frame_numV
#frame_sumV
#key_ver8
#data_content_lengthV
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#frame_end_code8
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#ÆV

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#-ÿ8

reservet#/data_package_format8
#7data_pack_num8
#8PGPRS_PROTOCOL_NORMAL_DATA_HEAD_TQ
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‰*“Bü8

sample_timeq#sc_cumulatev
#wc_cumulatev
#sc_instant
#wc_instant
#pressureè#temperatureè#"balance)
#&uint_pricef
#.lith_vcc8
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statusy#6PGPRS_PROTOCOL_NORMAL_DATA_PACK_Tm
œ*ÚXË8

sample_timeÀ#sc_cumulatev
#wc_cumulatev
#sc_instant
#wc_instant
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#.lith_vcc8
#2lith_vcc_perý#3alka_vcc8
#4alka_vcc_perý#5signal_noise_ratio_a18
#6signal_noise_ratio_b18
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#8gain_b18
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#:signal_intensity_b18
#;channel_time_a1è#<channel_time_b1è#@Channel_sound_vè#DChannel_flow_rateè#HËV

statusÀ
#LPGPRS_PROTOCOL_NORMAL_DATA_PACK_1_T¼
¸*æ˜
•8

sample_time
#sc_cumulatev
#wc_cumulatev
#re_sc_cumulatev
#re_wc_cumulatev
#sc_instant
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#:uint_pricef
#Blith_vcc8
#Flith_vcc_perý#Galka_vcc8
#Halka_vcc_perý#Isignal_noise_ratio_a18
#Jsignal_noise_ratio_b18
#Ksignal_noise_ratio_a28
#Lsignal_noise_ratio_b28
#Msignal_noise_ratio_a38
#Nsignal_noise_ratio_b38
#Ogain_a18
#Pgain_b18
#Qgain_a28
#Rgain_b28
#Sgain_a38
#Tgain_b38
#Usignal_intensity_a18
#Vsignal_intensity_b18
#Wsignal_intensity_a28
#Xsignal_intensity_b28
#Ysignal_intensity_a38
#Zsignal_intensity_b38
#[channel_time_a1è#\channel_time_b1è#`channel_time_a2è#dchannel_time_b2è#hchannel_time_a3è#lchannel_time_b3è#pChannel_sound_v1è#tChannel_sound_v2è#xChannel_sound_v3è#|Channel_flow_rate1è#€
Channel_flow_rate2è#„
Channel_flow_rate3è#ˆ
ÖV

statusK#Œ
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÷N•!˜%•"×"ŠPpGprs_Protocol_Recv_FuncHandler™
ù *"gprs_protocol_cmd_table_u16#GprsProtocolRecvFuncHandler#V
PGPRS_PROTOCOL_RECV_FUNC_TABLE_DRV_TÅ
þÕ(
PROTOCOL_UNKOWN_STATUSPROTOCOL_END_STATUS
PROTOCOL_NORMAL_SEND_CMDPROTOCOL_ALARM_SEND_CMDPROTOCOL_READ_FUNC_BACKPROTOCOL_READ_ALARM_CONTROL_BACKPROTOCOL_READ_SEND_CYCLE_BACKPROTOCOL_READ_METER_PARA_BACKPROTOCOL_READ_EQUIP_PARA_BACKPROTOCOL_SET_IP_BACK    PROTOCOL_READ_IP_BACK
PROTOCOL_CLEAR_COUNT_BACKPROTOCOL_READ_TIME_POINT_BACKPROTOCOL_READ_HISTORY_BACK PROTOCOL_READ_VALVE_RECORD_BACKPROTOCOL_READ_MODIFY_ACC_RECORD_BACKPROTOCOL_READ_BALANCE_CLOSE_VALVE_BACKPROTOCOL_READ_CLOSE_VALVE_BACKPROTOCOL_READ_DONT_REPORT_CLOSE_VALVE_BACKPROTOCOL_READ_DONT_USE_GAS_DAY_BACKPROTOCOL_READ_NO_COUNT_CLOSE_VALVE_BACKPROTOCOL_PAY_MONEYS_BACKPROTOCOL_READ_PRICE_NOW_INF_BACKPROTOCOL_SET_RECV_SUCCORFAIL*‰)
send_len8
#õ(8
send_bufferk#
)˜+recv_settle_data=©)8

settle_time_bcdž#settle_cumulate_sc)
#settle_balance)
#settle_pricef
#settle_ladder8
#settle_balance_small_state8
#Ð*8

last_pay_timeE#last_pay_money)
#"ˆ+8

reserve}#*)È,func_paralcd_display_mode8
#virtual_billing_state8
#
display_balance8
#display_price8
#gprs_usually_on_line8
#¸,8

reserve-#)Ã0send_cfg9gprs_interval_type8
#gprs_send_period_min_timeV
#
extern_pwr_send_period_reserveV
#Ç-8


gprs_reference_time_bcd¼#gprs_timed_number8
#Œ.8


•.

gprs_timing_time_bcd#gprs_timeoutV
# gprs_restart_send_interval_min_timeV
#"gprs_restart_number8
#$pack_or_independent_data8
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#&extern_pwr_save_period_reserveV
#(‰08


save_reference_time_bcdþ#*³08

reserve(#,)2ip_parastatus_ip_18
#ï08

gprs_ip_1d#
gprs_port_1V
#gprs_link_type_18
#status_ip_28
#Ï18

gprs_ip_2Ä#    gprs_port_2V
# gprs_link_type_28
#)Å4balance_alarm_parabalance_small_value_1
#valve_cfg_flag_18
#balance_small_value_2
#valve_cfg_flag_28
#    balance_small_value_3
#
valve_cfg_flag_38
#balance_small_value_4
#valve_cfg_flag_48
#balance_small_value_5
#valve_cfg_flag_58
#)œ5pay_moneys_parapay_moneys_flag8
#pay_moneys_cntV
#
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bcd

__time_h 
__ARMCLIB_VERSION 5060037
_ARMABI __declspec(__nothrow)
_ARMABI_PURE __declspec(__nothrow) __attribute__((const))
__TIME_DECLS  __CLIBNS
'__CLIBNS :NULL
;NULL 0
FCLOCKS_PER_SEC 100
KCLK_TCK CLOCKS_PER_SECTK
 




D:\Keil5\ARM\ARMCC\Bin\..\include\time.h
stdio.h


LD:\Keil5\ARM\ARMCC\Bin\..\include\time.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]unsigned intintlong
charuvoidPclock_t†
NPtime_t†
O*÷
__extra_1–#__extra_2–#*¨__extra_1_long#__extra_2_long#*Ù__extra_1_cptrY
#__extra_2_cptrY
#"¥*Ž__extra_1_vptrŽ
#__extra_2_vptrŽ
#"­S«Ð÷(
]
)Àtm,tm_sec–#tm_min–#tm_hour–#tm_mday–#tm_mon–#tm_year–#tm_wday–#tm_yday–#tm_isdst–# ’
#$Psize_t†5
fghi

_SUNDRY_H_ 
    FLOW_RING_BUFFER_SIZE 20

TEMP_RING_BUFFER_SIZE 10
PRESS_RING_BUFFER_SIZE 10
INSTANT_WC_RING_BUFFER_SIZE 20
BSWAP_16(x) ((x & 0x00ff) << 8) | ((x & 0xff00) >> 8)
BSWAP_32(x) ((x & 0xff000000) >> 24) | ((x & 0x00ff0000) >> 8) | ((x & 0x0000ff00) << 8) | ((x & 0x000000ff) << 24)
BSWAP_64(x) ((x & 0xff00000000000000) >> 56) | ((x & 0x00ff000000000000) >> 40) | ((x & 0x0000ff0000000000) >> 24) | ((x & 0x000000ff00000000) >> 8) | ((x & 0x00000000ff000000) << 8) | ((x & 0x0000000000ff0000) << 24) | ((x & 0x000000000000ff00) << 40) | ((x & 0x00000000000000ff) << 56)
#__SYS_DELAY_SEC_TIME_SET_(__HANDLE__,__NUMBER__) ((&sys_delay_sec_para_g)->__HANDLE__.delay_time = __NUMBER__)
&__SYS_DELAY_SEC_TIME_GET_(__HANDLE__) ((&sys_delay_sec_para_g)->__HANDLE__.delay_time)
)__SYS_DELAY_SEC_FLAG_GET(__HANDLE__) ((&sys_delay_sec_para_g)->__HANDLE__.delay_flag)
+__SYS_DELAY_SEC_FLAG_SET_(__HANDLE__) ((&sys_delay_sec_para_g)->__HANDLE__.delay_flag = SET)
-__SYS_DELAY_SEC_FLAG_CLEAR_(__HANDLE__) ((&sys_delay_sec_para_g)->__HANDLE__.delay_flag = RESET)
0__PERIOD_FIRST_CALC_FLAG_SET(__HANDLE__) ((&period_para_g)->__HANDLE__.period_flag = SET)
3OFFSET_OF(type,member) ((size_t) & (((type *)0))->member)
4SIZEOF_OF(type,member) (sizeof(((type *)0))->member)
7BCD_2_HEX_U8(__BCD_DATA__) (((__BCD_DATA__) / 16) * 10 + (__BCD_DATA__) % 16)
8HEX_2_BCD_U8(__HEX_DATA__) (((__HEX_DATA__) / 10) * 16 + (__HEX_DATA__) % 10)
;DAILY_ZERO ((&calendar_g)->Hour == 0 && (&calendar_g)->Minute == 0 && (&calendar_g)->Second == 0 ? SET : RESET)
CTYPE_CHECK_SIZE(type,size) extern char sizeof_ ## type ## _is_ ## size ## _error[!!(sizeof(type) == (size_t)(size)) - 1]
ITYPE_MEMBER(type,member) (((type *)0)->member)
QTYPE_MEMBER_CHECK_SIZE(type,member,size) extern int sizeof_ ## type ## _ ## member ## _is_error [!!(sizeof(TYPE_MEMBER(type, member)) == (size_t)(size)) - 1]
ZTYPE_CHILDTYPE_MEMBER_CHECK_SIZE(type,childtype,member,size) extern int sizeof_ ## type ## _ ## childtype ## _ ## member ## _is_error [!!(sizeof(TYPE_MEMBER(type, childtype.member)) == (size_t)(size)) - 1]
cTYPE_MEMBER_CHECK_OFFSET(type,member,value) extern int offset_of_ ## member ## _in_ ## type ## _is_error [!!(__builtin_offsetof(type, member) == ((size_t)(value))) - 1]
mTYPE_CHILDTYPE_MEMBER_CHECK_OFFSET(type,childtype,member,value) extern int offset_of_ ## member ## _in_ ## type ## _ ## childtype ## _is_error [!!(__builtin_offsetof(type, childtype.member) == ((size_t)(value))) - 1] –
 




..\Soft\..\Core\..\Function\EXTERN_RTC\D:\Keil5\ARM\ARMCC\Bin\..\include\sundry.h
define_all.hextern_rtc.htime.h


..\Soft\sundry.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMfloat"²PANALOGOUS_RING_BUFFER_TO
x*‡delay_flag
#delay_time 
#
t8
tV
PDELAY_SEC_TYPE_TÞ
~*Ïgprs_delay_para
#gprs_timeout_para
#flow_data_period_para
#sys_active_time
#    mode_flag_active_time
#sys_restart_delay_time
#PSYS_DELAY_SEC_PARA_T+

ˆ
*™period_flagV
#last_time_m 
#PPERIOD_TYPE_Tì

Ž
*¨gprs_send_period#alka_get_power_period#lith_get_power_period#mcu_get_temperature_period#PPERIOD_PARA_T/
–
qrestart_alarm_flag8


qsys_delay_sec_para_gÏ


qperiod_para_g¨

qflow_ring¿

qtemp_ring¿

qpress_ring¿

qinstant_wc_ring¿

*‘pRing_buffer»#front_index8
#rear_index8
#”¾restart_alarm_flagÙsys_delay_sec_para_gôperiod_para_gflow_ringtemp_ring(press_ring9instant_wc_ring
klm

__assert_h 
_ARMABI_NORETURN __declspec(__nothrow) __declspec(__noreturn)
__ARMCLIB_VERSION 5060037
!__ARM_PROMISE __promise#__CLIBNS
)__CLIBNS 
Hassert(e) ((e) ? (void)0 : __CLIBNS __aeabi_assert(#e, __FILE__, __LINE__), (__ARM_PROMISE)((e)?1:0))
J__promise(e) assert(e)LB
 




D:\Keil5\ARM\ARMCC\Bin\..\include\assert.h


ˆD:\Keil5\ARM\ARMCC\Bin\..\include\assert.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]
opq

 __inttypes_h 
__ARMCLIB_VERSION 5060037
_ARMABI __declspec(__nothrow)
_ARMABI_PURE __declspec(__nothrow) __attribute__((const))
__PRISCN64 "ll"
__PRISCNPTR 
%PRId8 "d"
&PRId16 "d"
'PRId32 "d"
(PRId64 __PRISCN64 "d"
)PRIdLEAST8 "d"
*PRIdLEAST16 "d"
+PRIdLEAST32 "d"
,PRIdLEAST64 __PRISCN64 "d"
-PRIdFAST8 "d"
.PRIdFAST16 "d"
/PRIdFAST32 "d"
0PRIdFAST64 __PRISCN64 "d"
1PRIdMAX "jd"
2PRIdPTR __PRISCNPTR "d"
4PRIi8 "i"
5PRIi16 "i"
6PRIi32 "i"
7PRIi64 __PRISCN64 "i"
8PRIiLEAST8 "i"
9PRIiLEAST16 "i"
:PRIiLEAST32 "i"
;PRIiLEAST64 __PRISCN64 "i"
<PRIiFAST8 "i"
=PRIiFAST16 "i"
>PRIiFAST32 "i"
?PRIiFAST64 __PRISCN64 "i"
@PRIiMAX "ji"
APRIiPTR __PRISCNPTR "i"
CPRIo8 "o"
DPRIo16 "o"
EPRIo32 "o"
FPRIo64 __PRISCN64 "o"
GPRIoLEAST8 "o"
HPRIoLEAST16 "o"
IPRIoLEAST32 "o"
JPRIoLEAST64 __PRISCN64 "o"
KPRIoFAST8 "o"
LPRIoFAST16 "o"
MPRIoFAST32 "o"
NPRIoFAST64 __PRISCN64 "o"
OPRIoMAX "jo"
PPRIoPTR __PRISCNPTR "o"
RPRIu8 "d"
SPRIu16 "d"
TPRIu32 "u"
UPRIu64 __PRISCN64 "u"
VPRIuLEAST8 "d"
WPRIuLEAST16 "d"
XPRIuLEAST32 "u"
YPRIuLEAST64 __PRISCN64 "u"
ZPRIuFAST8 "u"
[PRIuFAST16 "u"
\PRIuFAST32 "u"
]PRIuFAST64 __PRISCN64 "u"
^PRIuMAX "ju"
_PRIuPTR __PRISCNPTR "u"
aPRIx8 "x"
bPRIx16 "x"
cPRIx32 "x"
dPRIx64 __PRISCN64 "x"
ePRIxLEAST8 "x"
fPRIxLEAST16 "x"
gPRIxLEAST32 "x"
hPRIxLEAST64 __PRISCN64 "x"
iPRIxFAST8 "x"
jPRIxFAST16 "x"
kPRIxFAST32 "x"
lPRIxFAST64 __PRISCN64 "x"
mPRIxMAX "jx"
nPRIxPTR __PRISCNPTR "x"
pPRIX8 "X"
qPRIX16 "X"
rPRIX32 "X"
sPRIX64 __PRISCN64 "X"
tPRIXLEAST8 "X"
uPRIXLEAST16 "X"
vPRIXLEAST32 "X"
wPRIXLEAST64 __PRISCN64 "X"
xPRIXFAST8 "X"
yPRIXFAST16 "X"
zPRIXFAST32 "X"
{PRIXFAST64 __PRISCN64 "X"
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SCNxFAST8 "x"
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SCNxPTR __PRISCNPTR "x"\P
 




D:\Keil5\ARM\ARMCC\Bin\..\include\inttypes.h
stdint.h


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PR_BEGIN_EXTERN_C extern "C" {
PR_END_EXTERN_C }
!ENTER_CRITICAL_SECTION() __set_PRIMASK(1)
"EXIT_CRITICAL_SECTION() __set_PRIMASK(0)
0TRUE 1
4FALSE 0ˆ|
 




..\Soft\D:\Keil5\ARM\ARMCC\Bin\..\include\..\Core\port.h
assert.hinttypes.hdefine_all.h

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..\Soft\port.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM
unsigned char
charPBOOL8

$PUCHAR°
&PCHARÁ
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..\Soft\mbcrc.h
port.h


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..\Soft\mbcrc.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM
{|}~

_BILLING_H_ 
LADDER_PRICE_DEFAULT_VER 0
)REALTIME_BILLING_FORMAT_SIZE sizeof(BILLING_REAL_PARA_T)
4SYS_BILLING_ALARM_CFG_FORMAT_SIZE sizeof(BILLING_ALARM_CFG_T)
FSYS_LADDER_PRICE_CFG_FORMAT_SIZE sizeof(LADDER_PRICE_CFG_PARA_T)ˆ}
 




..\Soft\..\Core\..\Function\EXTERN_RTC\billing.h
define_all.hextern_rtc.hadministrator.h


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..\Soft\billing.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMdoublePBILLING_PRICE_MODE_NOW_T»
PSET_PRICE_MODE_T
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__VCC_PARA_FLAG_SET_(__HANDLE__) ((&pwr_vol_g)->__HANDLE__ = SET)

__VCC_PARA_FLAG_CLEAR_(__HANDLE__) ((&pwr_vol_g)->__HANDLE__ = RESET)
 LITHIUM_PWR_DOWN_PORT GPIOF
LITHIUM_PWR_DOWN_PIN GPIO_Pin_11
LIT_PWR_UNDER_PORT GPIOF
LIT_PWR_UNDER_PIN GPIO_Pin_6
LITHIUM_DETECTION_PORT GPIOD
LITHIUM_DETECTION_PIN GPIO_Pin_2
LIT_DEC_ON GPIO_SetBits(LITHIUM_DETECTION_PORT, LITHIUM_DETECTION_PIN)
LIT_DEC_OFF GPIO_ResetBits(LITHIUM_DETECTION_PORT, LITHIUM_DETECTION_PIN)
ALKALI_PWR_DOWN_PORT GPIOA
ALKALI_PWR_DOWN_PIN GPIO_Pin_4
ALKALI_DETECTION_PORT GPIOB
 LITH_TEST_ENALKALI_DETECTION_PIN GPIO_Pin_2
"ALK_DEC_ON GPIO_SetBits(ALKALI_DETECTION_PORT, ALKALI_DETECTION_PIN)
#ALK_DEC_OFF GPIO_ResetBits(ALKALI_DETECTION_PORT, ALKALI_DETECTION_PIN)
%Ad_LITH_PF6_BAT_CH 5
&Ad_LITH_PF6_BAT_CNT 8
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*Ad_LITH_BAT_CH 5
+Ad_LITH_BAT_CNT 8
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/Ad_ALKA_BAT_CH 10
0Ad_ALKA_BAT_CNT 8
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3AD_VTEM_CH ADC_CFGR_BUFSEL_TS
4AD_VTEM_CNT 8€t
 




..\Function\POWER_MANAGE\..\Core\..\Soft\power_manage.h
define_all.hadministrator.h

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..\Function\POWER_MANAGE\power_manage.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMfloatPLITH_MEASURE_STATUSm

<PALKA_MEASURE_STATUS°

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first_power_get_cnt_g]
pwr_vol_g
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GPRS_RECV_LEN_MAX 1024
AT_CMEE "AT+CMEE=1"
AT_ZIPOPEN "AT+ZIPOPEN=1,0"
AT_ZIPCLOSE "AT+ZIPCLOSE=1"
AT_ZIPSENDRAW "AT+ZIPSENDRAW=1"
AT_ZIPCALL "AT+ZIPCALL=1"
AT_CCID "AT+ZGETICCID"
AT_GSN "AT+CGSN"
AT_CSQ "AT+CSQ"
AT_ZIPCFG_CX "AT+ZIPCFG?"
AT_ZIPCFG "AT+ZIPCFG="
AT_ZRST "AT+ZRST"
AT_ZIPRECV "+ZIPRECV:"
 CRLF "\r\n"
#AT_CMEE_NB AT_CMEE
$AT_NCCID_NB "AT+NCCID"
%AT_CGSN_NB "AT+CGSN=1"
&AT_CSQ_NB "AT+CSQ"
'AT_SOPEN_NB "AT+SOPEN=0"
(AT_DTMODE_NB "AT+DTMODE=2"
)AT_SSEND_NB "AT+SSEND=0"
*AT_ZRST_NB AT_ZRST
,__GPRS_MODULE_SEND_LENGTH__(__LEN__) do { uint8_t temp_buffer[25]; sprintf((char *)temp_buffer, "%s,%d", AT_ZIPSENDRAW, __LEN__); Gprs_Send_ATcmd((char *)temp_buffer); } while (0)
4__GPRS_MODULE_SEND_LENGTH_NB__(__LEN__) do { uint8_t temp_buffer[25]; sprintf((char *)temp_buffer, "%s,%d,", AT_SSEND_NB, __LEN__); HAL_UART_Transmit(&huart3, temp_buffer, strlen((char *)temp_buffer), 1000); } while (0)ĸ
 




..\Function\GPRS\..\Core\D:\Keil5\ARM\ARMCC\Bin\..\include\gprs_module_api.h
define_all.hmain.hstring.hgprs_protocol_ideacreated_gasmeter_api.h


´
..\Function\GPRS\gprs_module_api.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM
charÕ
Ä
qsim_imei_gÌ

qgprs_module_para_g{

Ÿ
SEND_CMD_ZIPSENDRAWLOGIN_CMD_CMEE
LOGIN_CMD_ICCIDLOGIN_CMD_IMEILOGIN_CMD_CSQLOGIN_CMD_ZIPCALLLOGIN_CMD_ZIPOPENLOGIN_CMD_ZRSTPGPRS_AT_CMDÿ
Të
GMS_WORSTGMS_POOR
GMS_GENERALGMS_BESTPGPRS_MODULE_SIG²

\*÷„“8

ÿgprs_recv_buf#gprs_recv_lengthV
#€gprs_recv_flagÓ#‚gprs_module_statew#ƒtŸ
PGPRS_MODULE_PARA_T
fqgprs_resend_data_flag_g8


P¸Õsim_imei_gægprs_module_para_g•gprs_resend_data_flag_g
Š‹Œ

_GPRS_H_ 
GPRS_PWR_PORT GPIOA
    GPRS_PWR_PIN GPIO_Pin_7
GPRS_SWITCH_PORT GPIOA
 GPRS_SWITCH_PIN GPIO_Pin_6
GPRS_RE_PORT GPIOA
GPRS_RE_PIN GPIO_Pin_5
GPRS_PWR_ON GPIO_SetBits(GPRS_PWR_PORT, GPRS_PWR_PIN)
GPRS_PWR_OFF GPIO_ResetBits(GPRS_PWR_PORT, GPRS_PWR_PIN)
GPRS_RESTART_EN GPIO_SetBits(GPRS_RE_PORT, GPRS_RE_PIN)
GPRS_RESTART_DIS GPIO_ResetBits(GPRS_RE_PORT, GPRS_RE_PIN)
GPRS_SWITCH_H GPIO_ResetBits(GPRS_SWITCH_PORT, GPRS_SWITCH_PIN)
GPRS_SWITCH_L GPIO_SetBits(GPRS_SWITCH_PORT, GPRS_SWITCH_PIN)
GPRS_SEND_NORMAL(__DATA__,__SIZE__) UARTx_SendData_Normal(UART1, __DATA__, __SIZE__)
GPRS_FUNC_TABLE_NUM (sizeof(gprs_tab_func) / sizeof(GPRS_FUNC_TABLE_DRV_T))
 GPRS_BOOT_INIT_TIME 10
KSYS_GPRS_NETWORK_CFG_FORMAT_SIZE sizeof(GPRS_NETWORK_CFG_PARA_T)h]
 




..\Function\GPRS\..\Core\gprs.h
define_all.hgprs_module_api.h



..\Function\GPRS\gprs.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMì
GPRS_IDLEGPRS_OPEN_PWR
GPRS_OPEN_MODULEGPRS_CLOSE_PWRGPRS_CLOSE_MODULEGPRS_LOGINGPRS_SEND_DATAGPRS_RECV_DATAGPRS_SEND_ALARMGPRS_RESTART    PGPRS_STATUS¹
-–
GPRS_MEANS_NONEGPRS_MEANS_RTC_TIMED
GPRS_MEANS_KEYGPRS_MEANS_ALARMGPRS_MEANS_POWERGPRS_MEANS_RTC_PERIODGPRS_MEANS_AGAINPGPRS_SEND_MEANS

8Ú
GLT_TCPGLT_TELECOM
GLT_MOBILEPGPRS_LINK_TYPE-
?°
GIM_NONEGIM_PERIOD
GIM_TIMEDGIM_PERIOD_TIMEDPGPRS_INTERVAL_MEANSp
G*à    Õ
Û8

gprs_ip_1Ð#gprs_port_1V
#gprs_link_type_1Z#¤8

gprs_ip_2#gprs_port_2V
#gprs_link_type_2Z# save_data_period_min_timeV
#gprs_interval_type°#gprs_send_period_min_timeV
#Í8


gprs_reference_time_bcdÂ#gprs_timed_number8
#’8


›
gprs_timing_time_bcd#gprs_restart_send_interval_min_timeV
#.gprs_restart_number8
#0gprs_timeoutV
#1¢    8

«    —
aes128_secret_key¢#3Ï    8

reserveÄ#Ã
PGPRS_NETWORK_CFG_PARA_TË
_N†
l
"ÿPpGprs_FuncHandler
a*Ö
gprs_func_tableV#GprsFuncHandler
#
8
PGPRS_FUNC_TABLE_DRV_T#
g*«gprs_state«#gprs_send_type_flag#
tl
PGPRS_SOFT_PARA_Ty
mqgprs_soft_para_g¯

qgprs_network_cfg_para_gà

qgprs_save_send_para_g­


YÇgprs_soft_para_gÞgprs_network_cfg_para_gügprs_save_send_para_g
‘’

_CYCLIC_STORAGE_CFG_API_H_ 
CYCLIC_PARA_STORAGE_BLOCK_CNT (1)
CYCLIC_PARA_STORAGE_SIZE (CYCLIC_PARA_STORAGE_BLOCK_CNT * EEPROM_CFG_BLOCK_SIZE)
CYCLIC_PARA_STORAGE_START_ADDR EEPROM_PHYS_START_ADDR
CYCLIC_PARA_STORAGE_END_ADDR (CYCLIC_PARA_STORAGE_START_ADDR + CYCLIC_PARA_STORAGE_SIZE)
SYS_LOG_CYCLIC_TABLE_NUM (sizeof(sys_log_cyclic_table) / sizeof(SYSLOG_CYCLIC_TABLE_T))
PARA_AMEND_TABLE_NUM (sizeof(para_amend_table) / sizeof(PARA_AMEND_TABLE_T))
CYCLIC_INDEX_OFFSET sizeof(uint16_t)
LOG_CYCLIC_FLAG_OFFSET sizeof(uint8_t)
!SYSLOG_CYCLIC_INFO_LEN sizeof(SYSLOG_CYCLIC_INFO_T)
"SYSLOG_CYCLIC_INFO_NUM sizeof(sys_log_cyclic_data_g) / SYSLOG_CYCLIC_INFO_LEN´¨
 




..\Function\STORAGE\..\Core\..\Soft\cyclic_storage_cfg_api.h
define_all.hsystem_parameter.hsundry.hbilling.hadministrator.h

x
..\Function\STORAGE\cyclic_storage_cfg_api.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMô

REVERSE_READPOSITIVE_READ
PREAD_DIRECTIONÎ
* log_indexV
#log_cyclic_full_cnt8
#log_index_addrf
#log_full_cnt_addrf
#log_start_addrf
#log_end_addrf
#PSYSLOG_CYCLIC_INFO_T


.*ötable_idö
#data_sizeV
#data_numV
#" 
PSYSLOG_CYCLIC_TABLE_T¼

5*„    ¢send_flow_data_log 
#sys_hour_flow_data_log 
#sys_day_flow_data_log 
#&sys_month_flow_data_log 
#9measure_alarm_log 
#Lother_alarm_log 
#_valve_log 
#rpay_log 
#…
restore_default_log 
#˜
timing_log 
#«
gas_cumulate_amend_log 
#¾
balance_amend_log 
#Ñ
temp_cfg_amend_log 
#ä
press_cfg_amend_log 
#÷
billing_price_amend_log 
#Šflow_cfg_amend_log 
#cal_pulse_amend_log 
#°sys_func_cfg_amend_log 
#Ãalarm_ctl_send_bytes_amend_log 
#Övalve_ctl_bytes_amend_log 
#ébilling_alarm_cfg_amend_log 
#üsec_corr_para_amend_log 
#PSYSLOG_CYCLIC_DATA_T
Q¯ 
CYCL_SEND_FLOW_DATACYCL_HOUR_FLOW_DATA
CYCL_DAY_FLOW_DATACYCL_MONTH_FLOW_DATACYCL_MEASURE_ALARMCYCL_OTHER_ALARMCYCL_VALVECYCL_PAYCYCL_RESTORE_DEFAULTCYCL_TIMING    CYCL_GAS_CUMULATE_AMEND
CYCL_BALANCE_AMENDCYCL_TEMP_CFG_AMENDCYCL_PRESS_CFG_AMEND CYCL_BILLING_PRICE_AMENDCYCL_FLOW_CFG_AMENDCYCL_CAL_PULSE_AMENDCYCL_SYS_FUNC_CFG_AMENDCYCL_ALARM_CTL_SEND_BYTES_AMENDCYCL_VALVE_CTL_BYTES_AMENDCYCL_BILLING_ALARM_CFG_AMENDCYCL_SEC_CORR_PARA_AMENDPCYCLIC_DATA_TYPE 
m*ò amend_idL#data_addressö#
ú
"òPPARA_AMEND_TABLE_TÇ
sϘqsys_log_cyclic_table

úÄ7
qpara_amend_table;

qsys_log_cyclic_data_g„

V|sys_log_cyclic_tableDpara_amend_table[sys_log_cyclic_data_g
”•–—

_PARA_STORAGE_CFG_API_H_ 
SYS_LOG_PARA_TABLE_NUM (sizeof(sys_store_para_table) / sizeof(SYSLOG_PARA_TABLE_T))
    LOG_CHECKSUM_OFFSET sizeof(uint8_t)
PARA_INDEX_OFFSET sizeof(uint8_t)
FIRST_POWER_PARA_FORMAT_SIZE sizeof(FIRST_POWER_PARA_T)d[
 




..\Function\STORAGE\..\Core\para_storage_cfg_api.h
define_all.h

,
..\Function\STORAGE\para_storage_cfg_api.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMuvoid"ÌPFIRST_POWER_PARA_T
PSYSLOG_PARA_INFO_TW
PSYSLOG_PARA_TABLE_TÚ
&*ÊÔfirst_power_flag_storeð#save_realtime_data_logð#master_soft_hard_para_storeð#"sys_flow_alarm_cfg_storeð#3sys_press_alarm_cfg_storeð#Dsys_temp_alarm_cfg_storeð#Usys_billing_alarm_cfg_storeð#fcal_pulse_para_cfg_storeð#wladder_price_cfg_true_storeð#ˆ
ladder_price_cfg_new_storeð#™
gprs_network_cfg_storeð#ª
save_data_start_time_storeð#»
sys_func_cfg_bytes_storeð#Ì
sys_alarm_ctl_bytes_storeð#Ý
sys_alarm_send_bytes_storeð#î
valve_ctl_bytes_storeð#ÿ
master_basic_para_storeð#micro_constant_flow_para_storeð#¡sec_order_corr_set_para_storeð#²zero_drift_corr_cfg_storeð#ÃPSYSLOG_PARA_DATA_T%

>à
PARA_FIRST_POWER_FLAGPARA_SAVE_REALTIME_DATA
PARA_MASTER_SOFT_HARDPARA_FLOW_ALARM_CFGPARA_PRESS_ALARM_CFGPARA_TEMP_ALARM_CFGPARA_BILLING_ALARM_CFGPARA_CAL_PULSE_CFGPARA_LADDER_PRICE_CFG_TRUEPARA_LADDER_PRICE_CFG_NEW    PARA_GPRS_NETWORK_CFG
PARA_SAVE_DATA_START_TIMEPARA_FUNC_CFG_BYTESPARA_ALARM_CTL_BYTES PARA_ALARM_SEND_BYTESPARA_VALVE_CTL_BYTESPARA_MASTER_BASICPARA_MICRO_CONSTANT_FLOWPARA_SEC_ORDER_CORR_SETPARA_ZERO_DRIFT_CFGPPARA_DATA_TYPEä
V

ƒö
qsys_store_para_tableú

*×first_power_flagV
#Ç8


reserve<#*Ú store_index8
#store_index_addrf
#
store_checksum_addrf
#store_start_addrf
#    store_end_addrf
# *§table_id'#data_bufferÒ#data_sizeV
#data_numV
#
"ð'0sys_store_para_table
™š›œ

_VALVE_CONTROL_H_ 
__VALVE_WORK_TYPE_SET(__TYPE__) (op_cl_valve_log_flag_g = __TYPE__)
    __VALVE_CLOSE_BYTES_NEED_SET(__NUM__,__HANDLE__,__FLAG_L__) do { (&valve_ctl_bytes_g)->__NUM__.__HANDLE__ = __FLAG_L__; } while (0)
__VALVE_CLOSE_BYTES_MODE_SET(__NUM__,__HANDLE__,__MODE_H__) do { (&valve_ctl_bytes_g)->__NUM__.__HANDLE__ = __MODE_H__; } while (0)
__VALVE_CLOSE_BYTES_GET(__NUM__,__HANDLE__) ((&valve_ctl_bytes_g)->__NUM__.__HANDLE__)
VALVE_FORCED_OPEN_PORT GPIOA
VALVE_FORCED_OPEN_PIN GPIO_Pin_1
VALVE_CMD_A_PORT GPIOE
VALVE_CMD_A_PIN GPIO_Pin_2
!VALVE_CMD_B_PORT GPIOE
"VALVE_CMD_B_PIN GPIO_Pin_3
&VALVE_CMD_C_PORT GPIOE
'VALVE_CMD_C_PIN GPIO_Pin_4
-VALVE_PWR_ON GPIO_SetBits(VALVE_CMD_A_PORT, VALVE_CMD_A_PIN)
.VALVE_PWR_OFF GPIO_ResetBits(VALVE_CMD_A_PORT, VALVE_CMD_A_PIN)
1VALVE_OPEN do { GPIO_SetBits(VALVE_CMD_B_PORT, VALVE_CMD_B_PIN); GPIO_ResetBits(VALVE_CMD_C_PORT, VALVE_CMD_C_PIN); } while (0)
8VALVE_CLOSE do { GPIO_ResetBits(VALVE_CMD_B_PORT, VALVE_CMD_B_PIN); GPIO_SetBits(VALVE_CMD_C_PORT, VALVE_CMD_C_PIN); } while (0)
?VALVE_SLEEP do { GPIO_ResetBits(VALVE_CMD_B_PORT, VALVE_CMD_B_PIN); GPIO_ResetBits(VALVE_CMD_C_PORT, VALVE_CMD_C_PIN); } while (0)
HVALVE_CTL_LENGTH (sizeof(VALVE_STATUS_CHANGE_T) + sizeof(VALVE_BILLING_CHANGE_1_T) + sizeof(VALVE_BILLING_CHANGE_2_T) + sizeof(VALVE_VOLTAGE_CHANGE_1_T) + sizeof(VALVE_VOLTAGE_CHANGE_2_T) + sizeof(VALVE_TP_ERR_1_T) + sizeof(VALVE_TP_ERR_2_T) + sizeof(VALVE_MEASURE_ERR_1_T) + sizeof(VALVE_MEASURE_ERR_2_T) + sizeof(VALVE_OTHER_ERR_1_T) + sizeof(VALVE_OTHER_ERR_2_T))
LVALVE_CTL_LEN sizeof(VALVE_CTL_BYTES_T)
NVALVE_CLOSE_FUNC_TABLE_NUM (sizeof(valve_close_tab_func) / sizeof(VALVE_CLOSE_FUNC_TABLE_DRV_T))xn
 




..\Function\VALVE\..\Core\..\Soft\valve_control.h
define_all.hadministrator.h


..\Function\VALVE\valve_control.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM¢
VWT_NONEVWT_NORMAL_CLOSE
VWT_FORCED_CLOSEVWT_OPENVWT_LOCKVWT_UNLOCKPVALVE_WORK_TYPEÃ
X*÷!gprs_cmd_need_close_valve_flagV
#

!gprs_cmd_close_valve_typeV
#

!flow_direction_need_close_valve_flagV
#

!flow_direction_close_valve_typeV
#

!power_sta_need_close_valve_flagV
#

!power_sta_close_valve_typeV
#

!V
#
!uncap_1_need_close_valve_flagV
#


!uncap_1_close_valve_typeV
#


!uncap_2_need_close_valve_flagV
#


!uncap_2_close_valve_typeV
#


!V
#

PVALVE_STATUS_CHANGE_T9

n*œ
!valve_error_need_close_valve_flagV
#

!valve_error_close_valve_typeV
#

!balance_1_need_close_valve_flagV
#

!balance_1_close_valve_typeV
#

!balance_2_need_close_valve_flagV
#

!balance_2_close_valve_typeV
#

!balance_3_need_close_valve_flagV
#


!balance_3_close_valve_typeV
#

!balance_4_need_close_valve_flagV
#


!balance_4_close_valve_typeV
#


!balance_5_need_close_valve_flagV
#


!balance_5_close_valve_typeV
#


!V
#

PVALVE_BILLING_CHANGE_1_T
„
*Ì!set_cumulate_need_close_valve_flagV
#

!set_cumulate_close_valve_typeV
#

!no_use_gas_need_close_valve_flagV
#

!no_use_gas_close_valve_typeV
#

!no_gprs_need_close_valve_flagV
#

!no_gprs_close_valve_typeV
#

!V
#
PVALVE_BILLING_CHANGE_2_T=
‘
*È!lith_low_need_close_valve_flagV
#

!lith_low_close_valve_typeV
#

!lith_down_need_close_valve_flagV
#

!lith_down_close_valve_typeV
#

!lith_remove_need_close_valve_flagV
#

!lith_remove_close_valve_typeV
#

!alka_low_need_close_valve_flagV
#


!alka_low_close_valve_typeV
#

!alka_down_need_close_valve_flagV
#


!alka_down_close_valve_typeV
#


!alka_remove_need_close_valve_flagV
#


!alka_remove_close_valve_typeV
#


!gprs_fail_need_close_valve_flagV
#


!gprs_fail_close_valve_typeV
#


!V
#

PVALVE_VOLTAGE_CHANGE_1_Tm
ª
*‚!reserveV
#PVALVE_VOLTAGE_CHANGE_2_Té
¯
*Ø!temp_up_need_close_valve_flagV
#

!temp_up_close_valve_typeV
#

!temp_up_up_need_close_valve_flagV
#

!temp_up_up_close_valve_typeV
#

!temp_down_need_close_valve_flagV
#

!temp_down_close_valve_typeV
#

!temp_down_down_need_close_valve_flagV
#


!temp_down_down_close_valve_typeV
#

!press_up_need_close_valve_flagV
#


!press_up_close_valve_typeV
#


!press_up_up_need_close_valve_flagV
#


!press_up_up_close_valve_typeV
#


!press_down_need_close_valve_flagV
#


!press_down_close_valve_typeV
#


!press_down_down_need_close_valve_flagV
#



!press_down_down_close_valve_typeV
#


PVALVE_TP_ERR_1_T#    
Ê
*½!temp_err_need_close_valve_flagV
#

!temp_err_close_valve_typeV
#

!press_err_need_close_valve_flagV
#

!press_err_close_valve_typeV
#

!cpu_temp_up_need_close_valve_flagV
#

!cpu_temp_up_close_valve_typeV
#

!cpu_temp_down_need_close_valve_flagV
#


!cpu_temp_down_close_valve_typeV
#

!cpu_temp_drastic_change_close_valve_flagV
#


!cpu_temp_drastic_change_valve_typeV
#


!V
#

PVALVE_TP_ERR_2_Tñ
Ý
*ù !flow_vel_err_need_close_valve_flagV
#

!flow_vel_err_close_valve_typeV
#

!tof_diff_err_need_close_valve_flagV
#

!tof_diff_err_close_valve_typeV
#

!sound_vel_err_need_close_valve_flagV
#

!sound_vel_err_close_valve_typeV
#

!snr_err_need_close_valve_flagV
#


!snr_err_close_valve_typeV
#

!sig_up_need_close_valve_flagV
#


!sig_up_close_valve_typeV
#


!sig_th_err_need_close_valve_flagV
#


!sig_th_err_close_valve_typeV
#


!gain_err_need_close_valve_flagV
#


!gain_err_close_valve_typeV
#


!ut_lose_need_close_valve_flagV
#



!ut_lose_close_valve_typeV
#


PVALVE_MEASURE_ERR_1_TÖ 
ø
*$!input_water_err_need_close_valve_flagV
#

!input_water_err_close_valve_typeV
#

!media_err_need_close_valve_flagV
#

!media_err_close_valve_typeV
#

!dismantle_need_close_valve_flagV
#

!dismantle_close_valve_typeV
#

!measure_err_err_need_close_valve_flagV
#


!measure_err_err_close_valve_typeV
#

!V
#

PVALVE_MEASURE_ERR_2_T—
ˆ*Ï)!leakage_need_close_valve_flagV
#

!leakage_close_valve_typeV
#

!lcd_up_need_close_valve_flagV
#

!lcd_up_close_valve_typeV
#

!lcd_temp_low_need_close_valve_flagV
#

!lcd_temp_low_close_valve_typeV
#

!flow_up_1_need_close_valve_flagV
#


!flow_up_1_close_valve_typeV
#

!flow_up_2_need_close_valve_flagV
#


!flow_up_2_close_valve_typeV
#


!flow_up_3_need_close_valve_flagV
#


!flow_up_3_close_valve_typeV
#


!cl_constant_flow_need_close_valve_flagV
#


!cl_constant_flow_valve_typeV
#


!op_constant_flow_close_valve_flagV
#



!op_constant_flow_valve_typeV
#


PVALVE_OTHER_ERR_1_T+
£*‚,!cl_have_flow_need_close_valve_flagV
#

!cl_have_flow_valve_typeV
#

!e2p_write_err_need_close_valve_flagV
#

!e2p_write_err_flow_valve_typeV
#

!e2p_read_err_need_close_valve_flagV
#

!e2p_read_err_flow_valve_typeV
#

!V
#
PVALVE_OTHER_ERR_2_Të
°*ö-valve_ctr_1÷#valve_ctr_2#valve_ctr_3L#valve_ctr_4È#valve_ctr_5    #valve_ctr_6Ø#
valve_ctr_7½ #valve_ctr_8y#valve_ctr_9 #valve_ctr_10Ï#valve_ctr_11#PVALVE_CTL_BYTES_T
¿*×.valve_close_flagW#offset_bit]#valve_close_bytec#V
8
"V
PVALVE_CLOSE_FUNC_TABLE_DRV_T
Æqop_cl_valve_cause_id–

qop_cl_valve_log_flag_g"


qvalve_signal_complete_gÓ

qvalve_ctl_bytes_gö

tŽop_cl_valve_cause_id«op_cl_valve_log_flag_gÈvalve_signal_complete_gèvalve_ctl_bytes_g
žŸ ¡

_CYCLIC_STORAGE_DATA_CREATED_API_H_ 
SEND_FLOW_DATA_LOG_FORMAT_SIZE sizeof(SYS_SEND_FLOW_DATA_SYSLOG_FORMAT_T)
HISTORY_FLOW_DATA_LOG_FORMAT_SIZE sizeof(SYS_FLOW_DATA_SYSLOG_FORMAT_T)
VALVE_LOG_FORMAT_SIZE sizeof(VALVE_SYSLOG_FORMAT_T)
PAY_LOG_FORMAT_SIZE sizeof(PAY_SYSLOG_FORMAT_T)
RESTORE_DEFAULT_LOG_FORMAT_SIZE sizeof(RESTORE_DEFAULT_SYSLOG_FORMAT_T)
TIMING_LOG_FORMAT_SIZE sizeof(TIMING_SYSLOG_FORMAT_T)
AMEND_LOG_FORMAT_HEAD (sizeof(PARA_AMEND_SYSLOG_FORMAT_T) - sizeof(PARA_AMEND_UNION_T))
GAS_CUMULATE_AMEND_LOG_FORMAT_SIZE (sizeof(struct gas_cumulate_amend) + AMEND_LOG_FORMAT_HEAD)
BALANCE_AMEND_LOG_FORMAT_SIZE (sizeof(struct balance_amend) + AMEND_LOG_FORMAT_HEAD)
BILLING_PRICE_AMEND_LOG_FORMAT_SIZE (sizeof(struct billing_price_amend) + AMEND_LOG_FORMAT_HEAD)
PRESS_CFG_AMEND_LOG_FORMAT_SIZE (sizeof(struct press_cfg_amend) + AMEND_LOG_FORMAT_HEAD)
TEMP_CFG_AMEND_LOG_FORMAT_SIZE (sizeof(struct temp_cfg_amend) + AMEND_LOG_FORMAT_HEAD)
FLOW_CFG_AMEND_LOG_FORMAT_SIZE (sizeof(struct flow_cfg_amend) + AMEND_LOG_FORMAT_HEAD)
CAL_PULSE_AMEND_LOG_FORMAT_SIZE (sizeof(struct cal_pulse_amend) + AMEND_LOG_FORMAT_HEAD)
SYS_FUNC_CFG_AMEND_LOG_FORMAT_SIZE (sizeof(struct sys_func_cfg_amend) + AMEND_LOG_FORMAT_HEAD)
ALARM_CTL_SEND_BYTES_AMEND_LOG_FORMAT_SIZE (sizeof(struct sys_alarm_ctl_send_amend) + AMEND_LOG_FORMAT_HEAD)
VALVE_CTL_BYTES_AMEND_LOG_FORMAT_SIZE (sizeof(struct sys_valve_ctl_bytes_amend) + AMEND_LOG_FORMAT_HEAD)
BILLING_ALARM_CFG_AMEND_LOG_FORMAT_SIZE (sizeof(struct billing_alarm_cfg_amend) + AMEND_LOG_FORMAT_HEAD)
SEC_CORR_PARA_AMEND_LOG_FORMAT_SIZE (sizeof(struct sec_corr_para_amend) + AMEND_LOG_FORMAT_HEAD)
!ALARM_DATA_LOG_FORMAT_HEAD (sizeof(ALARM_SYSLOG_FORMAT_T) - sizeof(ALARM_SYSLOG_UNION_T))
"MEASURE_ALARM_DATA_LOG_FORMAT_SIZE (sizeof(struct measure_alarm_data) + ALARM_DATA_LOG_FORMAT_HEAD)
#OTHER_ALARM_DATA_LOG_FORMAT_SIZE (sizeof(struct other_alarm_data) + ALARM_DATA_LOG_FORMAT_HEAD)ĸ
 




..\Function\STORAGE\..\Core\..\Function\VALVE\..\Soft\cyclic_storage_data_created_api.h
define_all.hvalve_control.hbilling.hsystem_parameter.h

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..\Function\STORAGE\cyclic_storage_data_created_api.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMfloatdoublelong long)Íother_alarm_data price_nowf
#balance_nowà#½8

reserve2
#S‚0measure_alarm_data_sŒother_alarm_data_s÷PSYS_DATA_MENDER
+PTIMING_CAUSE_TM
4PALARM_SYSLOG_UNION_TM

P*…lrecord_numV
#î8

record_timeã
#alarm_idV
#forward_cumulate_scà#
forward_cumulate_wcà#instant_sc×#instant_wc×#temperature×#"pressure×#&cpu_temperature×#*lith_vcc8
#.alka_vcc8
#/ÖV

status_bytesË#0alarm_syslog_union¯
#<PALARM_SYSLOG_FORMAT_TË

b*Árecord_numV
#Å8

record_time:#work_type"
#switch_cause–#    open_cntV
#close_cntV
# ±8

reserve¦#PVALVE_SYSLOG_FORMAT_T"
m*½record_numV
#8

record_timeö#mender‚
#­8


reserve"#    PRESTORE_DEFAULT_SYSLOG_FORMAT_TÞ
u*©
record_numV
#‡    8

record_time|#mender‚
#plant_numberV
#    pay_type8
#pay_cntV
#pay_value
#pay_value_cumulateê#™
8

reserve#PPAY_SYSLOG_FORMAT_Td
‚
*érecord_numV
#è
8

record_time_before]#timing_cause™
#plant_numberV
#    ·8

record_time_now¬#Ù8

reserveÎ#PTIMING_SYSLOG_FORMAT_TE
Œ
)  gas_cumulate_amend$cumulate_sc_beforeà#cumulate_wc_beforeà#cumulate_sc_afterà#cumulate_wc_afterà# 8

reserve…# )ö balance_amendbalance_beforeà#balance_nowà#æ 8

reserveÛ#)Ábilling_price_amendÞ
price_cfg_before#price_cfg_now#o)‡press_cfg_amendXpress_cfg_before•#press_cgf_now•#,)Êtemp_cfg_amendLtemp_cfg_before #temp_cgf_now #&)flow_cfg_amend8flow_cfg_befores#flow_cfg_nows#)Ûcal_pulse_amendcal_pulse_cfg_before»
#cal_pulse_cfg_now»
#)Àsys_func_cfg_amendýV

func_cfg_bytes_beforer#¥V

func_cfg_bytes_nowš#)þsys_alarm_ctl_send_amend8èV

alarm_ctl_bytes_beforeÝ#‘V

alarm_send_bytes_before    #»V

alarm_ctl_bytes_now0    #áV

alarm_send_bytes_nowV    #*)ìsys_valve_ctl_bytes_amend,§V


valve_ctl_bytes_beforeœ    #ÐV


valve_ctl_bytes_nowÅ    #)Âbilling_alarm_cfg_amendNbilling_alarm_before0#billing_alarm_now0#')•sec_corr_para_amend 
sec_corr_para_beforeN
#sec_corr_para_nowN
#PSÉÞ
gas_cumulate_amend_sbalance_amend_s billing_price_amend_söpress_cfg_amend_sAtemp_cfg_amend_s‡flow_cfg_amend_sÊcal_pulse_amend_s sys_func_cfg_amend_s[sys_alarm_ctl_bytes_amend_sÀsys_valve_ctl_bytes_amend_s~    billing_alarm_cfg_amend_sì    sec_corr_para_amend_sB
PPARA_AMEND_UNION_T•

Ò
*Øé
record_numV
#ˆ8

record_timeý#mender‚
#plant_numberV
#    para_amend_unionÉ#PPARA_AMEND_SYSLOG_FORMAT_Tä
Û
*“ncheck_sum8
#8

record_time’#
forward_cumulate_scà#forward_cumulate_wcà#instant_sc×#instant_wc×#temperature×#pressure×##price_nowf
#'balance_nowà#+cpu_temp×#3lith_vcc8
#7alka_vcc8
#8snr_upV
#9snr_downV
#;signal_gain_up8
#=signal_gain_down8
#>signal_intensity_up8
#?signal_intensity_down8
#@tof_up×#Atof_down×#Esound_vel×#Iflow_vel×#MáV

sys_state_bytesV#Qƒ8

reservex#]PSYS_SEND_FLOW_DATA_SYSLOG_FORMAT_T{
ø
*ž>Í8

record_timeÂ#forward_cumulate_scà#forward_cumulate_wcà#instant_sc×#instant_wc×#temperature×#pressure×#"price_nowf
#&balance_nowà#*Ž8

reserveƒ#2PSYS_FLOW_DATA_SYSLOG_FORMAT_T¾
†qpay_para_g)

qvalve_log_gÁ

qpara_amend_log_gX

qtiming_log_gé

Í 
SDM_NULLSDM_UPPER
SDM_BT_APPSDM_GPRS_CMDŒ!
TC_NULLTC_AUTO
TC_GPRSTC_UPPERTC_BT_APP)#measure_alarm_data0tof_up×#tof_down×#tof_diff×#signal_intensity_up8
#signal_intensity_down8
# signal_gain_up8
#signal_gain_down8
#snr_upV
#snr_downV
#sound_vel×#flow_vel×##8

reserve‚#S Äpay_para_gÕvalve_log_gçpara_amend_log_gþtiming_log_g
£¤¥¦

_WORKING_TIME_CALCULATE_H_ 
LITH_BAT_WORKING_TIME_MAX (3 * 365 * 24)

__LITH_BAT_WORKINGTIME_RECOVER__ do{ save_realtime_data_g.lith_bat_working_time_remain_hour = LITH_BAT_WORKING_TIME_MAX; lith_bat_real_per_g = 100; }while(0)\Q
 




..\Soft\..\Core\working_time_calculate.h
define_all.h

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..\Soft\working_time_calculate.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMqlith_bat_real_per_gý

&àÂlith_bat_real_per_g
¨©ª«

_SYSTEM_LOG_H_ 
SAVE_DAY_MONTH_TIMING_LENGTH sizeof(save_day_month_timing_bcd)
REALTIME_DATA_LOG_FORMAT_SIZE sizeof(SAVE_REALTIME_DATA_T)
6SAVE_DATA_START_PARA_FORMAT_SIZE sizeof(SAVE_DATA_START_PARA_T)ÜÑ
 




..\Function\STORAGE\..\Core\..\Soft\system_log.h
define_all.hcyclic_storage_cfg_api.h
para_storage_cfg_api.h
cyclic_storage_data_created_api.h
working_time_calculate.h

€
..\Function\STORAGE\system_log.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMdoublefloat)úrealtime_billing_data%price_type_mode_now8
#price_nowf
#
use_money_sumÂ#balance_nowÂ# residual_gas_nowÂ#ladder_cumulate_scÂ#*¡w‰8

record_time_bcd~
#realtime_flow_data_sÀ#realtime_billing_data_sÕ#>lith_bat_working_time_remain_hourf
#c‘8

reserve#gPSYS_FLOW_DATA_LOG_T1
PSAVE_REALTIME_DATA_Tz

3*¥set_minute_bcd8
#set_hour_bcd8
#
•8

reserveŠ#PSAVE_DATA_START_PARA_TX
<qsave_realtime_data_g<

qsave_day_month_timing_g¥

qpay_flag_g8


qkey_save_send_data_flag_gÓ

À
SYS_FLOW_DATA_NONESYS_FLOW_DATA_5MINS
SYS_FLOW_DATA_PERIODSYS_FLOW_DATA_1HOURSYS_FLOW_DATA_1DAYSYS_FLOW_DATA_1MONTH)    realtime_flow_data8forward_cumulate_scÂ#forward_cumulate_wcÂ#–Â

cal_cumulate_reserve #»Â

err_forward_cumulate_reserve2# temp_avgÌ#0press_avgÌ#4p„Ãsave_realtime_data_gÞsave_day_month_timing_güpay_flag_gkey_save_send_data_flag_g
­®¯

__stdlib_h 
__ARMCLIB_VERSION 5060037
__LONGLONG long long
_ARMABI __declspec(__nothrow)
_ARMABI_PURE __declspec(__nothrow) __attribute__((const))
_ARMABI_NORETURN __declspec(__nothrow) __declspec(__noreturn)
_ARMABI_THROW 
!__STDLIB_DECLS 
)__USE_C99_STDLIB 1-__CLIBNS
4__CLIBNS GNULL
HNULL 0
mEXIT_FAILURE 1
oEXIT_SUCCESS 0

RAND_MAX 0x7fffffff
ˆ
MB_CUR_MAX ( __aeabi_MB_CUR_MAX() )
¥__fpsr_IXE 0x100000
¦__fpsr_UFE 0x80000
§__fpsr_OFE 0x40000
¨__fpsr_DZE 0x20000
©__fpsr_IOE 0x10000
«__fpsr_IXC 0x10
¬__fpsr_UFC 0x8
­__fpsr_OFC 0x4
®__fpsr_DZC 0x2
¯__fpsr_IOC 0x1ý__LONGLONGd[
 




D:\Keil5\ARM\ARMCC\Bin\..\include\stdlib.h
inttypes.h
stdio.h


ÀD:\Keil5\ARM\ARMCC\Bin\..\include\stdlib.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]intlonglong longuvoid
charunsigned intunsigned shortPdiv_tŸ
\))„ldiv_tquot#rem#Pldiv_tá
^/)¶lldiv_tquot—#rem—#Plldiv_t

a2)ë_rand_stateä
߈
8__xV
#)•_ANSI_rand_state‰ˆ
__x€
#N¥ˆ%¥
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V"¤ª"©
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P__heapprt±

ò)ð__sdiv32by16quotˆ#remˆ#P__sdiv32by16Ç

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€9)ì__sdiv64by32remˆ#quotˆ#P__sdiv64by32C
‚0Pwchar_tÂÒ
Psize_t²5)Ádiv_tquotˆ#remˆ#
±²³

_LOW_PWR_TEST_H_ PG
 




..\Soft\..\Core\low_pwr_test.h
define_all.h

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..\Soft\low_pwr_test.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM
µ¶·¸

_UPPER_COMPUTER_RW_API_H_ 
UC_NORMAL_USER 0x0001
    UC_POWER_USER UC_NORMAL_USER << 1

UC_ADMIN_USER UC_POWER_USER << 1
UC_SUPERUSER UC_ADMIN_USER << 1
 UC_RECV_WRITE_TABLE_NUM (sizeof(uc_recv_write_tab_func) / sizeof(UC_RECV_WRITE_FUNC_TABLE_DRV_T))
UC_RECV_READ_TABLE_NUM (sizeof(uc_recv_read_tab_func) / sizeof(UC_RECV_READ_FUNC_TABLE_DRV_T))
UC_DATA_TABLE_BYTES_LENGTH 2
SLAVE_UNION_PARA_LENGTH sizeof(UC_SLAVE_PARA_UNION_T)
SLAVE_SOFT_HARD_PARA_LENGTH sizeof(struct slave_soft_hard)
SLAVE_PIPE_PARA_LENGTH sizeof(struct pipe_para)
SLAVE_UT_PARA_LENGTH sizeof(struct ut_para)
SLAVE_CORR_SET_REAL_PARA_LENGTH sizeof(struct corr_set_real)
SLAVE_RAW_DATA_LENGTH sizeof(struct raw_data)
SLAVE_REAL_TIME_DATA_LENGTH sizeof(struct real_time_data)
SLAVE_UT_REAL_PARA_1_LENGTH sizeof(struct ut_real_para_1)
SLAVE_UT_REAL_PARA_2_LENGTH sizeof(struct ut_real_para_2)
SLAVE_RES_PARA_LENGTH sizeof(struct res_para)
SLAVE_TEMP_TIMEDIFF_PARA_LENGTH sizeof(struct temp_timediff_para)
SLAVE_CORR_FIXED_PARA_LENGTH sizeof(struct corr_fixed)€w
 




..\Function\UPPER_COMPUTER\..\Core\upper_computer_rw_api.h
define_all.hupper_computer.h


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..\Function\UPPER_COMPUTER\upper_computer_rw_api.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMfloatPUC_CMD;

ZPTEMP_TIMEDIFF_T
c)íslave_soft_hard¡8

slave_pcb_num
#Á8

slave_pcb_type6
#â8

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#
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slave_firmware_ver|
#¬8


slave_firmware_crc¡
#Ñ8

slave_firmware_timeÆ
#)‹pipe_parapipe_areaÔ#ut_physical_distanceÔ#ut_effective_distanceÔ#reimburse_time_aÔ#reimburse_time_bÔ#device_type8
#)Äut_para real_vccÔ#real_dac_valueÔ#real_dac_numÔ#ad_conver_factorÔ#ut_ad_line_aÔ#ut_ad_line_bÔ#ut_da_line_line_aÔ#ut_da_line_line_bÔ#)†corr_set_realPßÔ
    flowV#ôÔ
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real_time_data4forward_time_aÔ#reverse_time_bÔ#tof_diffÔ#flow_velÔ#flowÔ#sound_velÔ#forward_sigV
#reverse_sigV
#line_real_aV
#line_real_bV
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#(reserve_gainV
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temp_presstempÔ#pressÔ#)òut_real_para_1res_aV
#res_bV
#line_real_aV
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#signal_max_aV
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)‡ ut_real_para_2gain_max_aV
#gain_min_aV
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)Æ res_parares_state8
#res_a8
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res_b8
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Žë
cdata_buffer#)…corr_fixed"corr_fixed_state8
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íÔ
flow_data_pointd#SëÐslave_soft_hard_s
pipe_para_sí
ut_para_s‹corr_set_real_sDraw_data_s†real_time_data_sÌtemp_press_sAut_real_para_1_sjut_real_para_2_sòres_para_s‡temp_timediff_para_sÆcorr_fixed_s"PUC_SLAVE_PARA_UNION_T…
Ì
N–
%–"8
"‰PpUc_RecvWrite_FuncHandlerœ
Î
*¨    uc_data_table(    #func_admin_mode.    #func_admin_user(    #UcRecvWriteFuncHandler #V
8
PUC_RECV_WRITE_FUNC_TABLE_DRV_TÂ
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%–%l    "V
"[    PpUc_RecvRead_FuncHandlerr    
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*ü    uc_data_table(    #func_admin_mode.    #func_admin_user(    #UcRecvReadFuncHandlerv    #PUC_RECV_READ_FUNC_TABLE_DRV_T—    
à
qslave_para_union_gk

‹UCC_MASTER_INFO_RWUCC_TIME_RW-UCC_SLAVE_INFO_RW_2UCC_FLOW_CFG_PARA_RW
UCC_PRESS_CFG_PARA_RWUCC_TEMP_CFG_PARA_RWUCC_GPRS_CFG_RWUCC_AES_KEYS_RWUCC_SAVE_TIME_RWUCC_CUMULATE_SET_RWUCC_STATE_BYTES_RO_2    UCC_FUNC_CFG_RW_2
UCC_ALARM_CFG_SEND_RWUCC_VALVE_CTL_RW_2UCC_VALVE_FLAG_WO UCC_REALTIME_PARA_ROUCC_MICRO_CONSTANT_PARA_RWUCC_CYCLIC_LOG_DATA_INFO_ROUCC_SEC_CORR_SET_PARA_RWUCC_SEC_CORR_REAL_PARA_ROUCC_ZERO_DRIFT_CFG_RWUCC_BALANCE_SET_WOUCC_PAY_LOG_RO
UCC_PRICE_CFG_RWUCC_BILLING_CFG_RWUCC_SLAVE_INFO_RW UCC_STATE_BYTES_RO UCC_FUNC_CFG_RW UCC_ALARM_CFG_RW UCC_ALARM_SEND_RW UCC_VALVE_CTL_RW     UCC_SLAVE_PIPE_RW UCC_SLAVE_UT_RW UCC_SLAVE_CORR_SET_RW UCC_SLAVE_CORR_REAL_RO UCC_SLAVE_RAW_DATA_RO UCC_SLAVE_TP_DATA_RO UCC_SLAVE_UT_REAL_1_RO UCC_SLAVE_UT_REAL_2_RW UCC_SLAVE_RST_WO  UCC_SLAVE_STATUS_RO! UCC_SLAVE_ALARM_RO" UCC_SLAVE_REAL_DATA_RO# UCC_SLAVE_ZERO_2_ZERO_WO$ UCC_SLAVE_RES_RW% UCC_SLAVE_PWR_RW& UCC_SLAVE_TEMP_TIMEDIFF_RO' UCC_SLAVE_CAL_DATA_PARA_RW( UCC_SLAVE_CORR_FIXED_RW) UCC_BASIC_INFO_RWP UCC_CAL_PULSE_RWQ *¸temp_valueÔ#timediff_valueÔ#%<"
slave_para_union_g
º»¼½

_UPPER_COMPUTER_READ_LOG_API_H_ 
UC_RECV_LOG_TABLE_NUM (sizeof(uc_recv_log_tab_func) / sizeof(UC_RECV_LOG_FUNC_TABLE_DRV_T))
    UC_LOG_NUM_AND_FLAG_LENGTH (SIZEOF_OF(UC_SEND_LOG_PARA_T, send_log_num_now) + SIZEOF_OF(UC_SEND_LOG_PARA_T, send_log_continue_flag))ˆ}
 




..\Function\UPPER_COMPUTER\..\Core\upper_computer_read_log_api.h
define_all.hupper_computer.h


˜
..\Function\UPPER_COMPUTER\upper_computer_read_log_api.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMãUCLC_HOUR_FLOW_RO
UCLC_DAY_FLOW_RO
UCLC_MONTH_FLOW_RO
UCLC_SEND_FLOW_RO
UCLC_SYS_ALARM_RO`UCLC_MEASURE_ALARM_ROaUCLC_CUMULANT_AMEND_ROPUCLC_BALANCE_AMEND_ROQUCLC_TEMP_AMEND_RORUCLC_PRESS_AMEND_ROSUCLC_FLOW_AMEND_ROTUCLC_PRICE_AMEND_ROUUCLC_PULSE_AMEND_ROVUCLC_FUNC_CFG_AMEND_ROWUCLC_ALARM_CTL_SEND_AMEND_ROXUCLC_VALVE_CTL_AMEND_ROYUCLC_BILLING_ALARM_AMEND_ROZUCLC_VALVE_LOG_RO
UCLC_RESTORE_LOG_ROUCLC_TIMING_LOG_ROUCLC_PAY_LOG_RO
PUC_LOG_CMDÚ
%*…send_log_start_addrf
#send_log_indexV
#send_log_num_nowV
#send_log_num_totalV
#send_log_continue_flag8
#
PUC_SEND_LOG_PARA_Tõ
1N¸
%¸%¸%¾%Ä"8
"V
"…"ŸPpUc_RecvLog_FuncHandlerÈ
5*Ï    uc_data_tableO#func_admin_modeU#func_admin_userO#UcRecvLogFuncHandlerÌ#V
8
PUC_RECV_LOG_FUNC_TABLE_DRV_Të
=quc_send_log_para_g…

%œuc_send_log_para_g
¿ÀÁ

_UPPER_COMPUTER_IAP_API_H_ 
UC_RECV_IAP_TABLE_NUM (sizeof(uc_recv_iap_tab_func) / sizeof(UC_RECV_IAP_FUNC_TABLE_DRV_T))pd
 




..\Function\UPPER_COMPUTER\..\Core\upper_computer_iap_api.h
define_all.h

ä

..\Function\UPPER_COMPUTER\upper_computer_iap_api.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMÃUIC_APP_RESET–UIC_APP_CONFIG
–UIC_APP_DIFF_DATA–UIC_APP_CONFIG_CHECK–UIC_APP_DIFF_MAP–PUC_IAP_CMDÕ
Nâ
%b
"8
"U
PpUc_Iap_FuncHandlerh

*¹uc_data_table¹
#UcIapFuncHandlerl
#V
PUC_RECV_IAP_FUNC_TABLE_DRV_T‡


ÃÄÅÆ

_UART_H_ 
UART0_RECV_BUFF_LEN_MAX 200

IR_TX_PORT GPIOF
IR_TX_PIN GPIO_Pin_4
 IR_RX_PORT GPIOF
IR_RX_PIN GPIO_Pin_3
MAIN_TX_PORT GPIOC
MAIN_TX_PIN GPIO_Pin_10
MAIN_RX_PORT GPIOC
MAIN_RX_PIN GPIO_Pin_11
GPRS_TX_PORT GPIOA
GPRS_TX_PIN GPIO_Pin_8
GPRS_RX_PORT GPIOA
GPRS_RX_PIN GPIO_Pin_9„x
 




..\Hardware\UART\..\Core\..\Function\UPPER_COMPUTER\uart.h
define_all.hupper_computer.h

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_BOOTLOADER_IAP_H_ 
 BOOTLOAD_PAGE_SIZE (512)
BOOTLOAD_DIFF_SECTOR_MAP_ADDRESS (0x18C00)
BOOTLOAD_DIFF_MAP_LEN_MAX BOOTLOAD_PAGE_SIZE
BOOTLOAD_CONFIG_START_ADDRESS (BOOTLOAD_DIFF_SECTOR_MAP_ADDRESS + BOOTLOAD_DIFF_MAP_LEN_MAX)
BOOTLOAD_USER_PROG_START_ADDRESS (0x19000)
BOOTLOAD_USER_PROG_LEN_MAX (412 * 1024)
BOOTLOAD_DIFF_PROG_START_ADDRESS (0x1000)
BOOTLOAD_DIFF_PROG_LEN_MAX BOOTLOAD_USER_PROG_LEN_MAX
BOOTLOAT_PARA_SIZE sizeof(BOOTLOAD_PARA_STRUCT)h\
 




..\Function\BOOTLOADER_IAP\..\Core\bootloader_iap.h
define_all.h

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..\Core\..\Function\GPRS\..\Hardware\RTC\D:\Keil5\ARM\ARMCC\Bin\..\include\..\Soft\..\Function\POWER_MANAGE\..\Function\STORAGE\..\Function\VALVE\..\Hardware\UART\..\Function\BOOTLOADER_IAP\..\Function\GPRS\gprs_protocol_ideacreated_gasmeter_api.cmain.h
gprs_protocol_ideacreated_gasmeter_api.hrtc.hstring.hsundry.hmbcrc.hsystem_parameter.hbilling.hpower_manage.hgprs.hsystem_log.hvalve_control.hstdlib.hlow_pwr_test.huart.h    working_time_calculate.hbootloader_iap.h


 

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Input Comments:p2c94-3Component: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]armasm --debug --diag_suppress=9931,9931,1602,1073 --cpu=Cortex-M0 --fpu=SoftVFP --apcs=/interwork/interwork --no_divide gprs_protocol_ideacreated_gasmeter_api.oComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]ArmCC --c99 --split_sections --debug -c --gnu -o.\objects\gprs_protocol_ideacreated_gasmeter_api.o --depend=.\objects\gprs_protocol_ideacreated_gasmeter_api.d --cpu=Cortex-M0 --apcs=interwork -O0 --diag_suppress=9931 -I..\Core -I..\Drivers -I..\Core\Include -I..\Hardware -I.\RTE\Device -I..\Hardware\CLOCK -I..\Hardware\DELAY -I..\Hardware\GPIO -I..\Hardware\UART -I..\Hardware\TIM -I..\Function\KEY -I..\Hardware\EXTI -I..\Hardware\RTC -I..\Hardware\ADC -I..\Hardware\I2C -I..\Function\LCD -I..\Function\EXTERN_RTC -I..\Hardware\SPI -I..\Function\GPRS -I..\Function\HARDWARE_WATCHDOG -I..\Function\IR_NEC -I..\Function\MEASURE_INTERACTION -I..\Function\POWER_MANAGE -I..\Function\STORAGE -I..\Function\UPPER_COMPUTER -I..\Function\VALVE -I..\Soft -I..\MultiButton -I..\USMART -I..\Hardware\DMA -I..\Hardware\ON_CHIP_FLASH -I..\Hardware\SVD -I..\Function\OFF_CHIP_FLASH -I..\Hardware\CRC -I..\Function\BOOTLOADER_IAP -I..\Hardware\COMP -I..\Function\E2P -I..\CmBackTrace -I..\Pre_Drivers -I..\Pre_Drivers -I..\Function\PROJECT_TETS -I.\RTE\_UFG220_FM33A0_MainSystem -ID:\Keil5\ARM\PACK\ARM\CMSIS\5.3.0\CMSIS\Include -ID:\Keil5\ARM\PACK\Keil\FM33A0XXEV_DFP\0.0.4\Device\Include -D__MICROLIB -D__UVISION_VERSION=525 -D_RTE_ -D__VTOR_PRESENT --omf_browse=.\objects\gprs_protocol_ideacreated_gasmeter_api.crf ..\Function\GPRS\gprs_protocol_ideacreated_gasmeter_api.cӉ
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e.ARM.attributes.strtab.shstrtab.rel.debug_pubnames.rel.debug_frame.rel.debug_line.rel.debug_info.rel.data.reli.Gprs_Protocol_SetRecvSuccOrFail.reli.Gprs_Protocol_SendSetIpaddrHandler.reli.Gprs_Protocol_SendSetCloseValveKeyHandler.reli.Gprs_Protocol_SendReadTimePointHandler.reli.Gprs_Protocol_SendReadSendCycleHandler.reli.Gprs_Protocol_SendReadNoCountCloseValveHandler.reli.Gprs_Protocol_SendReadIpaddrHandler.reli.Gprs_Protocol_SendReadFunHandler.reli.Gprs_Protocol_SendReadEquipParaHandler.reli.Gprs_Protocol_SendReadDontUseGasDayHandler.reli.Gprs_Protocol_SendReadDontReportCloseValveHandler.reli.Gprs_Protocol_SendReadBalanceCloseValveHandler.reli.Gprs_Protocol_SendReadAlarmContHandler.reli.Gprs_Protocol_SendPriceNowInfHandler.reli.Gprs_Protocol_SendPayMoneysBackHandler.reli.Gprs_Protocol_SendNormalDataHandler.reli.Gprs_Protocol_SendDataConfig.reli.Gprs_Protocol_SendClearCountHandler.reli.Gprs_Protocol_Recv_ReadCmdGeneralHandler.reli.Gprs_Protocol_RecvStartEndCountHandler.reli.Gprs_Protocol_RecvSetTimeHandler.reli.Gprs_Protocol_RecvSetSendCycleHandler.reli.Gprs_Protocol_RecvSetMeterParaHandler.reli.Gprs_Protocol_RecvSetIpaddrHandler.reli.Gprs_Protocol_RecvSetFunParaHandler.reli.Gprs_Protocol_RecvSetDontUseGasDayHandler.reli.Gprs_Protocol_RecvSetDontReportCloseValveHandler.reli.Gprs_Protocol_RecvSetCountCloseValveHandler.reli.Gprs_Protocol_RecvSetCloseValveHandler.reli.Gprs_Protocol_RecvSetBalanceCloseValveHandler.reli.Gprs_Protocol_RecvSetAlarmContHandler.reli.Gprs_Protocol_RecvSaveTimePointHandler.reli.Gprs_Protocol_RecvPayMoneysHandler.reli.Gprs_Protocol_RecvOperaKeyHandler.reli.Gprs_Protocol_RecvNormalDataHandler.reli.Gprs_Protocol_RecvEndHandler.reli.Gprs_Protocol_RecvDataConfig.reli.Gprs_Protocol_RecvContValveHandler.reli.Gprs_Protocol_RecvClearExceptionHandler.reli.Gprs_Protocol_RecvClearCountHandler.reli.Gprs_Protocol_RecvBackSettleInfoHandler.reli.Gprs_Protocol_RecvAppResetHandler.reli.Gprs_Protocol_RecvAppDiffMapHandler.reli.Gprs_Protocol_RecvAppDiffDataHandler.reli.Gprs_Protocol_RecvAppConfigHandler.reli.Gprs_Protocol_RecvAppConfigCheckHandler.reli.Gprs_Protocol_RecvAdjustPriceHandler.reli.Gprs_Protocol_DataLength.reli.Create_Send_NormalDataPack2.reli.Create_Send_NormalDataPack1.reli.Create_Send_NormalDataPack.symtab.comment.arm_vfe_header__ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000__ARM_grp.gprs_protocol_ideacreated_gasmeter_api.c.2_sDe000_j$TNnsnXPW6_na0000__ARM_grp.bootloader_iap.h.2_Sq1000_tF0qWnRMbVc_700000__ARM_grp.uart.h.2_lI2000_$jgZMoj5iad_h00000__ARM_grp.upper_computer_iap_api.h.2_gD1000_E2Ts3Vy4n99_c00000__ARM_grp.upper_computer_read_log_api.h.2_JE3000_7ALk_SWRX37_D00000__ARM_grp.upper_computer_rw_api.h.2_Fy5000_InlWbuMkvWb_F10000__ARM_grp.low_pwr_test.h.2_8t0000_46_TEZvkO91_300000__ARM_grp.stdlib.h.2_MU0000_QQkXwSyZE52_300000__ARM_grp.system_log.h.2_op8000_oQ01RGgiTZ2_H00000__ARM_grp.working_time_calculate.h.2_SB2000_pck6FWbTHK3_f00000__ARM_grp.cyclic_storage_data_created_api.h.2_7Mn000_6fm_ABNIOSe_5f0000__ARM_grp.valve_control.h.2_8kg000_1UzC0$50UG7_3a0000__ARM_grp.para_storage_cfg_api.h.2_jp3000_9AATclGDWh6_v00000__ARM_grp.cyclic_storage_cfg_api.h.2_Oi8000_zpgb_jH0I38_b60000__ARM_grp.gprs.h.2_d04000_MMU35D1hQle_310000__ARM_grp.gprs_module_api.h.2_EI8000_XcWMt5RD3F7_v00000__ARM_grp.power_manage.h.2_$K8000_vYw28PnOGB1_B00000__ARM_grp.billing.h.2_zS3000_lAduDdy00ja_Z00000__ARM_grp.mbcrc.h.2_8s0000_udjUqJW6TU5_300000__ARM_grp.port.h.2_Em1000_cWymiH7cCq9_b00000__ARM_grp.inttypes.h.2_YM2000_HBynUsOMdLa_800000__ARM_grp.assert.h.2_oA0000_EVegbDxopI6_300000__ARM_grp.sundry.h.2_rG4000_NLRAyNhB77e_p00000__ARM_grp.time.h.2_4G0000_HvoQmatJ1Ad_300000__ARM_grp.gprs_protocol_ideacreated_gasmeter_api.h.2_E98000_Mp0fe6_UmZf_q30000__ARM_grp.system_parameter.h.2_uxa000_t$QaVqwZ90a_T10000__ARM_grp.lcd.h.2_VE7000_sZu_e6bBIC9_$50000__ARM_grp.lcd_io_api.h.2_h33000_shag9T72CS0_f00000__ARM_grp.lcd_segmentcode.h.2_EN2000_3d2rxbsK$Td_300000__ARM_grp.key.h.2_cV7000_B55fAyLVs59_p00000__ARM_grp.extern_rtc.h.2_CN2000_YksEs$T3w1d_r00000__ARM_grp.rtc.h.2_hg5000_Rkqidujx2P5_F00000__ARM_grp.linked_list.h.2_0$6000_T$gveB7RZS9_Z50000__ARM_grp.administrator.h.2_El7000_yWsVCV8hKR8_P50000__ARM_grp.gprs_sundry_api.h.2_YC2000_QzwXuSLBASf_t00000__ARM_grp.main.h.2_ga1000_6c0asbwEXV7_300000__ARM_grp.delay.h.2_EE0000_7GGSWSTJWL4_300000__ARM_grp.user_init.h.2_ot0000_jZWuqvPHwt6_300000__ARM_grp.define_all.h.2_kN0000_fD9tyG24Hn2_300000__ARM_grp.bintohex.h.2_Y33000_duI5XZW3h40_300000__ARM_grp.string.h.2_kw0000_aP4aobzpRT7_300000__ARM_grp.fm33a0xxev_include_all.h.2_UQ0000_xxdaGLUj6Cf_300000__ARM_grp.fm33a0xxev_cdif.h.2_kJ0000_JQTXKb9R3mc_300000__ARM_grp.fm33a0xxev_vrtc.h.2_YK1000_bGKK6ktMN$f_300000__ARM_grp.fm33a0xxev_et.h.2_4h3000_57B3Rgey0je_300000__ARM_grp.fm33a0xxev_bt.h.2_kV3000_MyPILKKQ6H1_300000__ARM_grp.fm33a0xxev_qspi.h.2_Qr4000_J7HoI7y0B84_g00000__ARM_grp.fm33a0xxev_hash.h.2_kO0000_KuZ300H4_80_300000__ARM_grp.fm33a0xxev_pae.h.2_sJ3000_RoohqLgJd45_300000__ARM_grp.fm33a0xxev_svd.h.2_YX4000_B$e1cGixg00_i00000__ARM_gr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