1.Fixed communication failure between MCU and wireless module 2.Fix the wro...

wujiazhi

2024-06-11 65062d0d5b21f838aa0043a15ce54cfab8d72c43

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..\\Drivers\\fm33a0xxev_flash.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM__asm___18_fm33a0xxev_flash_c_bb844dbd____REVSHP9

 




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..\Drivers\fm33a0xxev_flash.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM>ˆ
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__DATE__ "Jun 11 2024"
__TIME__ "13:38:18"
__STDC__ 1
__STDC_VERSION__ 199901L
__STDC_HOSTED__ 1
__STDC_ISO_10646__ 200607
__EDG__ 1
__EDG_VERSION__ 407
__EDG_SIZE_TYPE__ unsigned int
__EDG_PTRDIFF_TYPE__ int
__GNUC__ 4
__GNUC_STDC_INLINE__ 1
__GNUC_MINOR__ 7
__GNUC_PATCHLEVEL__ 0
__VERSION__ "4.7 (EDG gcc mode)"
__CHAR16_TYPE__ unsigned short
__CHAR32_TYPE__ unsigned int
__USER_LABEL_PREFIX__ 
__CHAR_UNSIGNED__ 1
__WCHAR_UNSIGNED__ 1
__SIZE_TYPE__ unsigned int
__PTRDIFF_TYPE__ int
__WCHAR_TYPE__ unsigned short
__WINT_TYPE__ unsigned short
__INTMAX_TYPE__ long long
__UINTMAX_TYPE__ unsigned long long
__sizeof_int 4
__sizeof_long 4
__sizeof_ptr 4
__ARMCC_VERSION 5060750
__TARGET_CPU_CORTEX_M0 1
__TARGET_FPU_SOFTVFP 1
__TARGET_FPU_SOFTVFP 1
__MICROLIB 1
__UVISION_VERSION 525
_RTE_ 1
__VTOR_PRESENT 1
__CC_ARM 1
__arm 1
__arm__ 1
__TARGET_ARCH_6S_M 1
__TARGET_ARCH_ARM 0
__TARGET_ARCH_THUMB 3
__TARGET_ARCH_A64 0
__TARGET_ARCH_AARCH32 1
__TARGET_PROFILE_M 1
__TARGET_FEATURE_HALFWORD 1
__TARGET_FEATURE_THUMB 1
__TARGET_FEATURE_DMB 1
__TARGET_FEATURE_EXTENSION_REGISTER_COUNT 0
__APCS_INTERWORK 1
__thumb 1
__thumb__ 1
__t32__ 1
__OPTIMISE_SPACE 1
__OPTIMIZE_SIZE__ 1
__OPTIMISE_LEVEL 0
__SOFTFP__ 1
$
ÃFLS_RDCR_WAIT_Set$
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#
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%


__stdint_h 
__ARMCLIB_VERSION 5060037
__INT64 __int64
__INT64_C_SUFFIX__ ll
__PASTE2(x,y) x ## y
__PASTE(x,y) __PASTE2(x, y)
__INT64_C(x) __ESCAPE__(__PASTE(x, __INT64_C_SUFFIX__))
__UINT64_C(x) __ESCAPE__(__PASTE(x ## u, __INT64_C_SUFFIX__))
__LONGLONG long long
#__STDINT_DECLS %__CLIBNS
,__CLIBNS 
yINT8_MIN -128
zINT16_MIN -32768
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INT16_MAX 32767
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INT32_MAX 2147483647
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UINT8_MAX 255
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UINT16_MAX 65535
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UINT32_MAX 4294967295u
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UINT64_MAX __UINT64_C(18446744073709551615)
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INT_LEAST16_MIN -32768
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INT_LEAST8_MAX 127
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INT_LEAST16_MAX 32767
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INT_LEAST32_MAX 2147483647
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INT_LEAST64_MAX __INT64_C(9223372036854775807)
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UINT_LEAST8_MAX 255
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UINT_LEAST16_MAX 65535
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UINT_LEAST32_MAX 4294967295u
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UINT_LEAST64_MAX __UINT64_C(18446744073709551615)
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INT_FAST32_MIN (~0x7fffffff)
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INT_FAST64_MIN __INT64_C(~0x7fffffffffffffff)
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INT_FAST8_MAX 2147483647
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INT_FAST16_MAX 2147483647
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INT_FAST32_MAX 2147483647
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INT_FAST64_MAX __INT64_C(9223372036854775807)
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UINT_FAST8_MAX 4294967295u
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UINT_FAST16_MAX 4294967295u
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UINT_FAST32_MAX 4294967295u
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UINT_FAST64_MAX __UINT64_C(18446744073709551615)
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INTPTR_MIN INT32_MIN
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INTPTR_MAX INT32_MAX
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UINTPTR_MAX UINT32_MAX
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UINTMAX_MAX __ESCAPE__(18446744073709551615ull)
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PTRDIFF_MIN INT32_MIN
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PTRDIFF_MAX INT32_MAX
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SIG_ATOMIC_MAX 2147483647
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SIZE_MAX UINT32_MAXí
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WCHAR_MAX 65535
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WINT_MAX 2147483647
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„INT64_C(x) __INT64_C(x)
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‡UINT16_C(x) (x ## u)
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UINTMAX_C(x) __ESCAPE__(x ## ull)¸__INT64¹__LONGLONGLB
 




D:\Keil5\ARM\ARMCC\Bin\..\include\stdint.h


0D:\Keil5\ARM\ARMCC\Bin\..\include\stdint.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]
signed charshortintlong long
unsigned charunsigned shortunsigned intunsigned long longPint8_tˆ
8 Pint16_t—
9 Pint32_t 
: Pint64_t§
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M Pint_least16_t—
N Pint_least32_t 
O Pint_least64_t§
P Puint_least8_t´
S Puint_least16_tÅ
T Puint_least32_t×
U Puint_least64_tç
V Pint_fast8_t 
[ Pint_fast16_t 
\ Pint_fast32_t 
] Pint_fast64_t§
^ Puint_fast8_t×
a Puint_fast16_t×
b Puint_fast32_t×
c Puint_fast64_tç
d Pintptr_t 
k Puintptr_t×
l Pintmax_t§
p!Puintmax_tç
q!
'
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)


'__CORE_CMINSTR_H 
<__NOP __nop
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g__DSB() do { __schedule_barrier(); __dsb(0xF); __schedule_barrier(); } while (0)
r__DMB() do { __schedule_barrier(); __dmb(0xF); __schedule_barrier(); } while (0)
__REV __rev
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__ROR __ror
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__BKPT(value) __breakpoint(value)
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__CLZ __clz@6
 




..\Core\Include\core_cminstr.h




..\Core\Include\core_cminstr.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM;†
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..\Core\Include\core_cmfunc.h


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..\Core\Include\core_cmfunc.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM;ÿ

@__get_CONTROLW
a__resultW

Y__regControlW

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M__set_CONTROL$W
controlY__regControlW

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Z__get_IPSRW
a__resultW

Y__regIPSRW

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a__resultW

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a__resultW

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a__resultW

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/
0
1


 __CORE_CM0PLUS_H_GENERIC "
@__CM0PLUS_CMSIS_VERSION_MAIN ( 5U)
A__CM0PLUS_CMSIS_VERSION_SUB ( 0U)
B__CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | __CM0PLUS_CMSIS_VERSION_SUB )
E__CORTEX_M (0U)
Q__ASM __asm
R__INLINE __inline
S__STATIC_INLINE static __inline
T__NO_RETURN __declspec(noreturn)
U__USED __attribute__((used))
V__WEAK __attribute__((weak))
W__UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
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__FPU_USED 0UÆ
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__I volatile const
__O volatile
‚__IO volatile
…__IM volatile const
†__OM volatile
‡__IOM volatile
³APSR_N_Pos 31U
´APSR_N_Msk (1UL << APSR_N_Pos)
¶APSR_Z_Pos 30U
·APSR_Z_Msk (1UL << APSR_Z_Pos)
¹APSR_C_Pos 29U
ºAPSR_C_Msk (1UL << APSR_C_Pos)
¼APSR_V_Pos 28U
½APSR_V_Msk (1UL << APSR_V_Pos)
ÎIPSR_ISR_Pos 0U
ÏIPSR_ISR_Msk (0x1FFUL )
æxPSR_N_Pos 31U
çxPSR_N_Msk (1UL << xPSR_N_Pos)
éxPSR_Z_Pos 30U
êxPSR_Z_Msk (1UL << xPSR_Z_Pos)
ìxPSR_C_Pos 29U
íxPSR_C_Msk (1UL << xPSR_C_Pos)
ïxPSR_V_Pos 28U
ðxPSR_V_Msk (1UL << xPSR_V_Pos)
òxPSR_T_Pos 24U
óxPSR_T_Msk (1UL << xPSR_T_Pos)
õxPSR_ISR_Pos 0U
öxPSR_ISR_Msk (0x1FFUL )
ˆCONTROL_SPSEL_Pos 1U
‰CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)
‹CONTROL_nPRIV_Pos 0U
ŒCONTROL_nPRIV_Msk (1UL )
ÈSCB_CPUID_IMPLEMENTER_Pos 24U
ÉSCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
ËSCB_CPUID_VARIANT_Pos 20U
ÌSCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
ÎSCB_CPUID_ARCHITECTURE_Pos 16U
ÏSCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
ÑSCB_CPUID_PARTNO_Pos 4U
ÒSCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
ÔSCB_CPUID_REVISION_Pos 0U
ÕSCB_CPUID_REVISION_Msk (0xFUL )
ØSCB_ICSR_NMIPENDSET_Pos 31U
ÙSCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)
ÛSCB_ICSR_PENDSVSET_Pos 28U
ÜSCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
ÞSCB_ICSR_PENDSVCLR_Pos 27U
ßSCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
áSCB_ICSR_PENDSTSET_Pos 26U
âSCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
äSCB_ICSR_PENDSTCLR_Pos 25U
åSCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
çSCB_ICSR_ISRPREEMPT_Pos 23U
èSCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
êSCB_ICSR_ISRPENDING_Pos 22U
ëSCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
íSCB_ICSR_VECTPENDING_Pos 12U
îSCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
ðSCB_ICSR_VECTACTIVE_Pos 0U
ñSCB_ICSR_VECTACTIVE_Msk (0x1FFUL )
õSCB_VTOR_TBLOFF_Pos 8U
öSCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)
úSCB_AIRCR_VECTKEY_Pos 16U
ûSCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
ýSCB_AIRCR_VECTKEYSTAT_Pos 16U
þSCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
€SCB_AIRCR_ENDIANESS_Pos 15U
SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
ƒSCB_AIRCR_SYSRESETREQ_Pos 2U
„SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
†SCB_AIRCR_VECTCLRACTIVE_Pos 1U
‡SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
ŠSCB_SCR_SEVONPEND_Pos 4U
‹SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
SCB_SCR_SLEEPDEEP_Pos 2U
ŽSCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
SCB_SCR_SLEEPONEXIT_Pos 1U
‘SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
”SCB_CCR_STKALIGN_Pos 9U
•SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)
—SCB_CCR_UNALIGN_TRP_Pos 3U
˜SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
›SCB_SHCSR_SVCALLPENDED_Pos 15U
œSCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
´SysTick_CTRL_COUNTFLAG_Pos 16U
µSysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
·SysTick_CTRL_CLKSOURCE_Pos 2U
¸SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
ºSysTick_CTRL_TICKINT_Pos 1U
»SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
½SysTick_CTRL_ENABLE_Pos 0U
¾SysTick_CTRL_ENABLE_Msk (1UL )
ÁSysTick_LOAD_RELOAD_Pos 0U
ÂSysTick_LOAD_RELOAD_Msk (0xFFFFFFUL )
ÅSysTick_VAL_CURRENT_Pos 0U
ÆSysTick_VAL_CURRENT_Msk (0xFFFFFFUL )
ÉSysTick_CALIB_NOREF_Pos 31U
ÊSysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)
ÌSysTick_CALIB_SKEW_Pos 30U
ÍSysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)
ÏSysTick_CALIB_TENMS_Pos 0U
ÐSysTick_CALIB_TENMS_Msk (0xFFFFFFUL )
éMPU_TYPE_IREGION_Pos 16U
êMPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
ìMPU_TYPE_DREGION_Pos 8U
íMPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
ïMPU_TYPE_SEPARATE_Pos 0U
ðMPU_TYPE_SEPARATE_Msk (1UL )
óMPU_CTRL_PRIVDEFENA_Pos 2U
ôMPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
öMPU_CTRL_HFNMIENA_Pos 1U
÷MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
ùMPU_CTRL_ENABLE_Pos 0U
úMPU_CTRL_ENABLE_Msk (1UL )
ýMPU_RNR_REGION_Pos 0U
þMPU_RNR_REGION_Msk (0xFFUL )
MPU_RBAR_ADDR_Pos 8U
‚MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)
„MPU_RBAR_VALID_Pos 4U
…MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos)
‡MPU_RBAR_REGION_Pos 0U
ˆMPU_RBAR_REGION_Msk (0xFUL )
‹MPU_RASR_ATTRS_Pos 16U
ŒMPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos)
ŽMPU_RASR_XN_Pos 28U
MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos)
‘MPU_RASR_AP_Pos 24U
’MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos)
”MPU_RASR_TEX_Pos 19U
•MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos)
—MPU_RASR_S_Pos 18U
˜MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos)
šMPU_RASR_C_Pos 17U
›MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos)
MPU_RASR_B_Pos 16U
žMPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos)
 MPU_RASR_SRD_Pos 8U
¡MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos)
£MPU_RASR_SIZE_Pos 1U
¤MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos)
¦MPU_RASR_ENABLE_Pos 0U
§MPU_RASR_ENABLE_Msk (1UL )
Ä_VAL2FLD(field,value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
Ì_FLD2VAL(field,value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
ÙSCS_BASE (0xE000E000UL)
ÚSysTick_BASE (SCS_BASE + 0x0010UL)
ÛNVIC_BASE (SCS_BASE + 0x0100UL)
ÜSCB_BASE (SCS_BASE + 0x0D00UL)
ÞSCB ((SCB_Type *) SCB_BASE )
ßSysTick ((SysTick_Type *) SysTick_BASE )
àNVIC ((NVIC_Type *) NVIC_BASE )
ãMPU_BASE (SCS_BASE + 0x0D90UL)
äMPU ((MPU_Type *) MPU_BASE )
‚_BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
ƒ_SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
„_IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )”ˆ
 




..\Core\Include\D:\Keil5\ARM\ARMCC\Bin\..\include\core_cm0plus.h
stdint.hcore_cminstr.h
core_cmfunc.h


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..\Core\Include\core_cm0plus.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM*”!_reserved0W
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Å*‰    CTRL #LOAD #VAL #CALIB?#PSysTick_TypeT
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3
4
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__stdio_h 
__ARMCLIB_VERSION 5060037
"_ARMABI __declspec(__nothrow)
%__STDIO_DECLS '__CLIBNS
-__CLIBNS <NULL
=NULL 0
g_SYS_OPEN 16
¥
stdin (&__CLIBNS __stdin)
§
stdout (&__CLIBNS __stdout)
©
stderr (&__CLIBNS __stderr)
¬
_IOFBF 0x100
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_IOLBF 0x200
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_IONBF 0x400
±
BUFSIZ (512)
³
FOPEN_MAX _SYS_OPEN
¹
FILENAME_MAX 256
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L_tmpnam FILENAME_MAX
Ä
TMP_MAX 256
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SEEK_SET 0
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SEEK_CUR 1
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SEEK_END 2
Ú
_IOBIN 0x04
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__STDIN_BUFSIZ (64)
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__STDOUT_BUFSIZ (64)
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__STDERR_BUFSIZ (16)
¿getchar() getc(stdin)
àputchar(c) putc(c, stdout)LA
 




D:\Keil5\ARM\ARMCC\Bin\..\include\stdio.h


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D:\Keil5\ARM\ARMCC\Bin\..\include\stdio.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]unsigned intunsigned long longPsize_t‡
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8
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$FM33A0XXEV_H 
.__RCHF_INITIAL_CLOCK (8000000)
/__RCMF_CLOCK (2000000)
0__RCLP_CLOCK (32000)
1__XTLF_CLOCK (32768)
n__CM0_REV 0x0100
o__MPU_PRESENT 1
p__VTOR_PRESENT 1
q__NVIC_PRIO_BITS 2
r__Vendor_SysTickConfig 0uv
¿FLASH_BASE (( uint32_t)0x00000000)
ÀSRAM_BASE (( uint32_t)0x20000000)
ÁPERIPH_BASE (( uint32_t)0x40000000)
ÊPMU_BASE (PERIPH_BASE +0x00002000)
ËDBG_BASE (PERIPH_BASE +0x00000000)
ÌFLS_BASE (PERIPH_BASE +0x00001000)
ÍRMU_BASE (PERIPH_BASE +0x00002800)
ÎIWDT_BASE (PERIPH_BASE +0x00011400)
ÏWWDT_BASE (PERIPH_BASE +0x00011800)
ÐCMU_BASE (PERIPH_BASE +0x00002400)
ÑCDIF_BASE (PERIPH_BASE +0x0001E000)
ÒVRTC_BASE (PERIPH_BASE +0x0001F800)
ÓSVD_BASE (PERIPH_BASE +0x00012800)
ÔAES_BASE (PERIPH_BASE +0x00013800)
ÕPAE_BASE (PERIPH_BASE +0x00001400)
ÖHASH_BASE (PERIPH_BASE +0x00001800)
×RNG_BASE (PERIPH_BASE +0x00013C00)
ØCOMP_BASE (PERIPH_BASE +0x00015400)
ÙI2C0_BASE (PERIPH_BASE +0x00012400)
ÚI2C1_BASE (PERIPH_BASE +0x00015000)
ÛUARTIR_BASE (PERIPH_BASE +0x00017C00)
ÜUART0_BASE (PERIPH_BASE +0x00012000)
ÝUART1_BASE (PERIPH_BASE +0x00016800)
ÞUART2_BASE (PERIPH_BASE +0x00016C00)
ßUART3_BASE (PERIPH_BASE +0x00017000)
àUART4_BASE (PERIPH_BASE +0x00017400)
áUART5_BASE (PERIPH_BASE +0x00017800)
âLPUART0_BASE (PERIPH_BASE +0x00014000)
ãLPUART1_BASE (PERIPH_BASE +0x00014400)
äSPI0_BASE (PERIPH_BASE +0x00010400)
åSPI1_BASE (PERIPH_BASE +0x00010800)
æSPI2_BASE (PERIPH_BASE +0x00014800)
çSPI3_BASE (PERIPH_BASE +0x00014C00)
èSPI4_BASE (PERIPH_BASE +0x00016400)
éU7816_BASE (PERIPH_BASE +0x00011C00)
êQSPI_BASE (PERIPH_BASE +0x00000800)
ëDMA_BASE (PERIPH_BASE +0x00000400)
ìCRC_BASE (PERIPH_BASE +0x00010000)
íBT1_BASE (PERIPH_BASE +0x00013000)
îBT2_BASE (PERIPH_BASE +0x00013044)
ïET1_BASE (PERIPH_BASE +0x00013090)
ðET2_BASE (PERIPH_BASE +0x000130B0)
ñET3_BASE (PERIPH_BASE +0x000130D0)
òET4_BASE (PERIPH_BASE +0x000130F0)
óETCNT_BASE (PERIPH_BASE +0x00013110)
ôBSTIM_BASE (PERIPH_BASE +0x00016000)
õLPTIM_BASE (PERIPH_BASE +0x00013400)
öRTC_BASE (PERIPH_BASE +0x00011000)
÷LCD_BASE (PERIPH_BASE +0x00010C00)
øADC_BASE (PERIPH_BASE +0x0001FA00)
ùCIC_BASE (PERIPH_BASE +0x00015C00)
úGPIOA_BASE (PERIPH_BASE +0x00000C00)
ûGPIOB_BASE (PERIPH_BASE +0x00000C40)
üGPIOC_BASE (PERIPH_BASE +0x00000C80)
ýGPIOD_BASE (PERIPH_BASE +0x00000CC0)
þGPIOE_BASE (PERIPH_BASE +0x00000D00)
ÿGPIOF_BASE (PERIPH_BASE +0x00000D40)
€GPIOG_BASE (PERIPH_BASE +0x00000D80)
GPIOH_BASE (PERIPH_BASE +0x0001FC00)
‚GPIO_BASE (PERIPH_BASE +0x00000DC0)
ˆPMU ((PMU_Type *) PMU_BASE )
‰DBG ((DBG_Type *) DBG_BASE )
ŠFLS ((FLS_Type *) FLS_BASE )
‹RMU ((RMU_Type *) RMU_BASE )
ŒIWDT ((IWDT_Type *) IWDT_BASE )
WWDT ((WWDT_Type *) WWDT_BASE )
ŽCMU ((CMU_Type *) CMU_BASE )
CDIF ((CDIF_Type *) CDIF_BASE )
VRTC ((VRTC_Type *) VRTC_BASE )
‘SVD ((SVD_Type *) SVD_BASE )
’AES ((AES_Type *) AES_BASE )
“PAE ((PAE_Type *) PAE_BASE )
”HASH ((HASH_Type *) HASH_BASE )
•RNG ((RNG_Type *) RNG_BASE )
–COMP ((COMP_Type *) COMP_BASE )
—I2C0 ((I2C_Type *) I2C0_BASE )
˜I2C1 ((I2C_Type *) I2C1_BASE )
™UARTIR ((UARTIR_Type *) UARTIR_BASE )
šUART0 ((UART_Type *) UART0_BASE )
›UART1 ((UART_Type *) UART1_BASE )
œUART2 ((UART_Type *) UART2_BASE )
UART3 ((UART_Type *) UART3_BASE )
žUART4 ((UART_Type *) UART4_BASE )
ŸUART5 ((UART_Type *) UART5_BASE )
 LPUART0 ((LPUART_Type *) LPUART0_BASE )
¡LPUART1 ((LPUART_Type *) LPUART1_BASE )
¢SPI0 ((SPI_Type *) SPI0_BASE )
£SPI1 ((SPI_Type *) SPI1_BASE )
¤SPI2 ((SPI_Type *) SPI2_BASE )
¥SPI3 ((SPI_Type *) SPI3_BASE )
¦SPI4 ((SPI_Type *) SPI4_BASE )
§U7816 ((U7816_Type *) U7816_BASE )
¨QSPI ((QSPI_Type *) QSPI_BASE )
©DMA ((DMA_Type *) DMA_BASE )
ªCRC ((CRC_Type *) CRC_BASE )
«BT1 ((BT_Type *) BT1_BASE )
¬BT2 ((BT_Type *) BT2_BASE )
­ET1 ((ET_Type *) ET1_BASE )
®ET2 ((ET_Type *) ET2_BASE )
¯ET3 ((ET_Type *) ET3_BASE )
°ET4 ((ET_Type *) ET4_BASE )
±ETCNT ((ETCNT_Type *) ETCNT_BASE )
²BSTIM ((BSTIM_Type *) BSTIM_BASE )
³LPTIM ((LPTIM_Type *) LPTIM_BASE )
´RTC ((RTC_Type *) RTC_BASE )
µLCD ((LCD_Type *) LCD_BASE )
¶ADC ((ADC_Type *) ADC_BASE )
·CIC ((CIC_Type *) CIC_BASE )
¸GPIOA ((GPIO_Type *) GPIOA_BASE )
¹GPIOB ((GPIO_Type *) GPIOB_BASE )
ºGPIOC ((GPIO_Type *) GPIOC_BASE )
»GPIOD ((GPIO_Type *) GPIOD_BASE )
¼GPIOE ((GPIO_Type *) GPIOE_BASE )
½GPIOF ((GPIO_Type *) GPIOF_BASE )
¾GPIOG ((GPIO_Type *) GPIOG_BASE )
¿GPIOH ((GPIOH_Type *) GPIOH_BASE )
ÀGPIO ((GPIO_COMMON_Type *) GPIO_BASE )h]
 




..\Core\Include\FM33A0XXEV.h
core_cm0plus.h
system_FM33A0XXEV.h


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..\Core\Include\FM33A0XXEV.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMÓ

RESETSET
PFlagStatus¾
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Reset_IRQnqNMI_IRQnrHardFault_IRQnsSVC_IRQn{PendSV_IRQn~SysTick_IRQnWWDT_IRQnSVD_IRQn
RTC_IRQnFLASH_IRQnCMU_IRQnADC_IRQnSPI0_IRQnSPI1_IRQnSPI2_IRQnUART0_IRQn    UART1_IRQn
UART2_IRQnUART3_IRQnUART4_IRQn UART5_IRQnU7816_IRQnLPUART0_IRQnI2Cx_IRQnRSV_IRQnCRYPTO_IRQnLPTIM_IRQnDMA_IRQnWKUPx_IRQnCOMP_IRQnBTx_IRQnQSPI_IRQnETx_IRQnBSTIM_IRQnSPI3_IRQnSPI4_IRQnGPIO_IRQnLPUART1_IRQnPIRQn_TypeG

b*öCRv#WKTRv#WKFRv#IERv#ISRv#tW
PPMU_Type9
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‚*» CRv#PSCRv#PCDIF_Type 
Œ*Õ0PDRCRv#ç v
RSV1Þ#RCMFCRv#RCLPCRv#RCLPTRv#XTLFCRv# ADCCRv#$LFDIERv#(LFDISRv#,PVRTC_TypeÍ
ž*£CFGRv#CRv#IERv#ISRv#VSRv#PSVD_Typeg
¬*§TCRv#IERv#ISRv#DIRv#DORˆ#KEY0v#KEY1v#KEY2v#KEY3v# KEY4v#$KEY5v#(KEY6v#,KEY7v#0IVR0v#4IVR1v#8IVR2v#<IVR3v#@H0v#DH1v#HH2v#LH3v#PPAES_Type´
Ê*ž CSRv#MLRv#MPRv#M0CFGv#M1CFGv#M2CFGv#M3CFGv#WORDv#PPAE_Type¸
Û*ÊCSRv#DTRv#PHASH_Type/    
æ*À CRv#DORˆ#þv

RSV1u    #SRv#CRC_CRv#CRC_DIRv#CRC_SRv#PRNG_Type\    
ö*CR1v#CR2v#ICRv#ISRv#PCRv#PCOMP_TypeÑ    
„*ˆ$CFGRv#CRv#IERv#ISRv#SRv#BRGv#BUFv#TIMINGv#TOv# PI2C_Type

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°*ûCSRv#IERv#ISRv#BMRv#RXBUFv#TXBUFv#DMRv#PLPUART_Type%
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Ð*â$CRv#FFRv#EGTRv#PSCv#BGRv#RXBUFˆ#TXBUFv#IERv#ISRv# PU7816_Typeö
â*‚0CRv#CFGv#SRv#DATALENv#CCRv#ADDRv#ABRv#DRv#SMSKv# SMATv#$PITVv#(TOv#,PQSPI_Typeu
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$RSV1†#lCH0CSRv#€CH0MASRv#„CH1CSRv#ˆCH1MASRv#ŒCH2CSRv#CH2MASRv#”CH3CSRv#˜CH3MASRv#œCH4CSRv# CH4MASRv#¤CH5CSRv#¨CH5MASRv#¬CH6CSRv#°CH6MASRv#´PDMA_Type 
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Ó*°" CRv#INSRv#PSCR1v#PSCR2v#IVRv#CMPRv#IERv#ISRv#PET_TypeÎ
ä*õ"CNT1v#CNT2v#CNT3v#CNT4v#PETCNT_Type@
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(SYSTEM_FM33A0XXEV_H 234
O__SYSTEM_CLOCK (8000000)
PDELAY_US (__SYSTEM_CLOCK/1000000)
QDELAY_MS (__SYSTEM_CLOCK/1000)
TDo_DelayStart() { uint32_t LastTick = SysTick->VAL; do {
WWhile_DelayMsEnd(Count) }while(((LastTick - SysTick->VAL)&0xFFFFFF)<DELAY_MS*Count); }
ZWhile_DelayUsEnd(Count) }while(((LastTick - SysTick->VAL)&0xFFFFFF)<DELAY_US*Count); }…
 




..\Core\Include\D:\Keil5\ARM\ARMCC\Bin\..\include\system_FM33A0XXEV.h
stdint.hstdio.hFM33A0XXEV.h


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..\Core\Include\system_FM33A0XXEV.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMqSystemCoreClockW


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A
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__FM33A0XXEV_FLASH_H 
FLS_RDCR_WAIT_Pos 0
FLS_RDCR_WAIT_Msk (0x3U << FLS_RDCR_WAIT_Pos)
FLS_RDCR_WAIT_0CYCLE (0x0U << FLS_RDCR_WAIT_Pos)
 FLS_RDCR_WAIT_1CYCLE (0x1U << FLS_RDCR_WAIT_Pos)
!FLS_RDCR_WAIT_2CYCLE (0x2U << FLS_RDCR_WAIT_Pos)
#FLS_PFCR_PRFTEN_Pos 0
&FLS_PFCR_PRFTEN_Msk (0x1U << FLS_PFCR_PRFTEN_Pos)
*FLS_OPTBR_DBGCFGEN_Pos 31
+FLS_OPTBR_DBGCFGEN_Msk (0x1U << FLS_OPTBR_DBGCFGEN_Pos)
-FLS_OPTBR_IF2LOCK_Pos 18
0FLS_OPTBR_IF2LOCK_Msk (0x1U << FLS_OPTBR_IF2LOCK_Pos)
2FLS_OPTBR_IF1LOCK_Pos 17
5FLS_OPTBR_IF1LOCK_Msk (0x1U << FLS_OPTBR_IF1LOCK_Pos)
7FLS_OPTBR_DFLSEN_Pos 10
:FLS_OPTBR_DFLSEN_Msk (0x1U << FLS_OPTBR_DFLSEN_Pos)
>FLS_OPTBR_BTSEN_Pos 8
AFLS_OPTBR_BTSEN_Msk (0x3U << FLS_OPTBR_BTSEN_Pos)
GFLS_OPTBR_ACLOCKEN_Pos 4
JFLS_OPTBR_ACLOCKEN_Msk (0x3U << FLS_OPTBR_ACLOCKEN_Pos)
PFLS_OPTBR_DBRDPEN_Pos 0
SFLS_OPTBR_DBRDPEN_Msk (0xfU << FLS_OPTBR_DBRDPEN_Pos)
YFLS_OPTBR_LOCK1_Pos 0
ZFLS_OPTBR_LOCK1_Msk (0xffffffffU << FLS_OPTBR_LOCK1_Pos)
\FLS_OPTBR_LOCK2_Pos 0
]FLS_OPTBR_LOCK2_Msk (0xffffffffU << FLS_OPTBR_LOCK2_Pos)
_FLS_OPTBR_LOCK3_Pos 0
`FLS_OPTBR_LOCK3_Msk (0xffffffffU << FLS_OPTBR_LOCK3_Pos)
bFLS_OPTBR_LOCK4_Pos 0
cFLS_OPTBR_LOCK4_Msk (0xffffffffU << FLS_OPTBR_LOCK4_Pos)
eFLS_EPCR_ERTYPE_Pos 8
iFLS_EPCR_ERTYPE_Msk (0x3U << FLS_EPCR_ERTYPE_Pos)
jFLS_EPCR_ERTYPE_PAGE (0x0U << FLS_EPCR_ERTYPE_Pos)
kFLS_EPCR_ERTYPE_SECTOR (0x1U << FLS_EPCR_ERTYPE_Pos)
lFLS_EPCR_ERTYPE_CHIP_ERASE (0x2U << FLS_EPCR_ERTYPE_Pos)
nFLS_EPCR_PREQ_Pos 1
pFLS_EPCR_PREQ_Msk (0x1U << FLS_EPCR_PREQ_Pos)
rFLS_EPCR_EREQ_Pos 0
tFLS_EPCR_EREQ_Msk (0x1U << FLS_EPCR_EREQ_Pos)
vFLS_KEY_KEY_Pos 0
wFLS_KEY_KEY_Msk (0xffffffffU << FLS_KEY_KEY_Pos)
yFLS_IER_OTPIE_Pos 11
zFLS_IER_OTPIE_Msk (0x1U << FLS_IER_OTPIE_Pos)
|FLS_IER_AUTHIE_Pos 10
}FLS_IER_AUTHIE_Msk (0x1U << FLS_IER_AUTHIE_Pos)
FLS_IER_KEYIE_Pos 9
€
FLS_IER_KEYIE_Msk (0x1U << FLS_IER_KEYIE_Pos)
‚
FLS_IER_CKIE_Pos 8
ƒ
FLS_IER_CKIE_Msk (0x1U << FLS_IER_CKIE_Pos)
…
FLS_IER_PRDIE_Pos 1
†
FLS_IER_PRDIE_Msk (0x1U << FLS_IER_PRDIE_Pos)
ˆ
FLS_IER_ERDIE_Pos 0
‰
FLS_IER_ERDIE_Msk (0x1U << FLS_IER_ERDIE_Pos)
‹
FLS_ISR_KEYSTA_Pos 17
’
FLS_ISR_KEYSTA_Msk (0x7U << FLS_ISR_KEYSTA_Pos)
“
FLS_ISR_KEYSTA_KEY_NONE_PROTECT (0x0U << FLS_ISR_KEYSTA_Pos)
”
FLS_ISR_KEYSTA_CHIP_ERASE (0x1U << FLS_ISR_KEYSTA_Pos)
•
FLS_ISR_KEYSTA_SECTOR_ERASE (0x2U << FLS_ISR_KEYSTA_Pos)
–
FLS_ISR_KEYSTA_PROGRAM (0x3U << FLS_ISR_KEYSTA_Pos)
—
FLS_ISR_KEYSTA_KEY_ERR_PROTECT (0x4U << FLS_ISR_KEYSTA_Pos)
™
FLS_ISR_BTSF_Pos 16
œ
FLS_ISR_BTSF_Msk (0x1U << FLS_ISR_BTSF_Pos)

FLS_ISR_BTSF_START_0000H (0x0U << FLS_ISR_BTSF_Pos)
ž
FLS_ISR_BTSF_START_2000H (0x1U << FLS_ISR_BTSF_Pos)
 
FLS_ISR_OTPERR_Pos 11
£
FLS_ISR_OTPERR_Msk (0x1U << FLS_ISR_OTPERR_Pos)
¥
FLS_ISR_AUTHERR_Pos 10
¨
FLS_ISR_AUTHERR_Msk (0x1U << FLS_ISR_AUTHERR_Pos)
ª
FLS_ISR_KEYERR_Pos 9
«
FLS_ISR_KEYERR_Msk (0x1U << FLS_ISR_KEYERR_Pos)
­
FLS_ISR_CKERR_Pos 8
®
FLS_ISR_CKERR_Msk (0x1U << FLS_ISR_CKERR_Pos)
°
FLS_ISR_PRD_Pos 1
±
FLS_ISR_PRD_Msk (0x1U << FLS_ISR_PRD_Pos)
³
FLS_ISR_ERD_Pos 0
´
FLS_ISR_ERD_Msk (0x1U << FLS_ISR_ERD_Pos)`V
 




..\Drivers\..\Core\Include\fm33a0xxev_flash.h
FM33A0XXEV.h

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..\Drivers\fm33a0xxev_flash.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM
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%Component: ARM Compiler 5.06 update 6 (build 750) Tool: armlink [4d35ed]armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=9931,9931,6642 --cpu=Cortex-M0 --fpu=SoftVFP --output=.\objects\fm33a0xxev_flash.o --vfemode=force
Input Comments:p2cb4-3Component: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]armasm --debug --diag_suppress=9931,9931,1602,1073 --cpu=Cortex-M0 --fpu=SoftVFP --apcs=/interwork/interwork --no_divide fm33a0xxev_flash.oComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]ArmCC --c99 --split_sections --debug -c --gnu -o.\objects\fm33a0xxev_flash.o --depend=.\objects\fm33a0xxev_flash.d --cpu=Cortex-M0 --apcs=interwork -O0 --diag_suppress=9931 -I..\Core -I..\Drivers -I..\Core\Include -I..\Hardware -I.\RTE\Device -I..\Hardware\CLOCK -I..\Hardware\DELAY -I..\Hardware\GPIO -I..\Hardware\UART -I..\Hardware\TIM -I..\Function\KEY -I..\Hardware\EXTI -I..\Hardware\RTC -I..\Hardware\ADC -I..\Hardware\I2C -I..\Function\LCD -I..\Function\EXTERN_RTC -I..\Hardware\SPI -I..\Function\GPRS -I..\Function\HARDWARE_WATCHDOG -I..\Function\IR_NEC -I..\Function\MEASURE_INTERACTION -I..\Function\POWER_MANAGE -I..\Function\STORAGE -I..\Function\UPPER_COMPUTER -I..\Function\VALVE -I..\Soft -I..\MultiButton -I..\USMART -I..\Hardware\DMA -I..\Hardware\ON_CHIP_FLASH -I..\Hardware\SVD -I..\Function\OFF_CHIP_FLASH -I..\Hardware\CRC -I..\Function\BOOTLOADER_IAP -I..\Hardware\COMP -I..\Function\E2P -I..\CmBackTrace -I..\Pre_Drivers -I..\Pre_Drivers -I..\Function\PROJECT_TETS -I.\RTE\_UFG220_FM33A0_MainSystem -ID:\Keil5\ARM\PACK\ARM\CMSIS\5.3.0\CMSIS\Include -ID:\Keil5\ARM\PACK\Keil\FM33A0XXEV_DFP\0.0.4\Device\Include -D__MICROLIB -D__UVISION_VERSION=525 -D_RTE_ -D__VTOR_PRESENT --omf_browse=.\objects\fm33a0xxev_flash.crf ..\Drivers\fm33a0xxev_flash.c‹'
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