forked from SZV10X_Software/SZV103_FM33A0xxEV_SiZhu
blame | history | raw
wujiazhi
2024-06-11 65062d0d5b21f838aa0043a15ce54cfab8d72c43 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215

ELF(øl4(¡ž@ºpGÀºpGµ"ªI ÿ÷þÿ¨Hxð!@(Û¥Hx@P(Ü£Hx(


Û Hx    (ܝHxIˆpࠛIˆp࠙Iˆp—H@xð!@(۔H@x@P(ܑH@x(


ێH@x    (܋H@x‹IHpࠉIHpࠇIHp…H€xð!@


!HC‚I‰x        @(#Ú~H€xð!@(Û{H€x@ (ÜyH€x(


ÛvH€x    (ÜsH€xsIp


à qIpà oIpà mIpkHÀxkIHqiHyð!@


!HCeI    y        @ (1ÚbHyð!@


!HC^I    y        @(#Ý[Hyð!@(ÛXHy@0(ÜUHy(


ÛRHy    (ÜOHyOIq


à MIqà KIqà IIqGH@yð!@


!HCDIIy        @ (1Ú@H@yð!@


!HC=IIy        @(#Ý9H@yð!@(Û6H@y@(Ü4H@y(


Û1H@y    (Ü.H@y.IÈp


à ,IÈpà *IÈpà (IÈp&H€yð!@


!HC"I‰y        @d(&ÚH€yð!@(ÛH€y@(ÜH€y( ÛH€y    (ÜH€y!I@IȀ


àHIȀàHIȀà HIȀd ÿ÷þÿ    H€xIIxJx’‘HyÂxÁˆ ÿ÷þÿ½ EXTERNAL RTC TIME = %X-%02X-%02X-%02X-%02X-%02X  


øµF FFÿ÷þÿd ÿ÷þÿ8Fÿ÷þÿÿ÷þÿe ÿ÷þÿ$àÿ÷þÿ(Uÿ÷þÿ`IJp BõÜÿ÷þÿ(Uÿ÷þÿÿ÷þÿø½øµF FFÿ÷þÿd ÿ÷þÿ8Fÿ÷þÿ$à(]ÿ÷þÿ`IJ´BøÛÿ÷þÿø½ÿµƒ°FFFŸ GIpÿ÷þÿö²ð!˜@


!HC™        @<(ÚiF˜qà iFqð! ˜@


!HC ™        @<(ÚiF ˜Hqà iFHqð 8@


!HC9    @(ÚhF‡qà iFˆqiF˜Èqð (@


!HC)    @ (Úð (@


!HC)    @(ÝhFrà iFrð  @


!HC!    @ (Úð  @


!HC!    @(ÝhFDrà iFHrð 0@


!HC1    @d(ÚiFŽrà iFˆr"© ÿ÷þÿ


 ÿ÷þÿ Ip°ð½µ…° Ipÿ÷þÿ ÿ÷þÿ!hFp!Ap!p!ÁpP!q"iF ÿ÷þÿd ÿ÷þÿHˆ(ÐHx(Ñÿ÷þÿÿ÷þÿàÿ÷þÿÿ÷þÿ Ip°½ì..\\Pre_Drivers\\ex_rtc.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM__asm___8_ex_rtc_c_b7bc8562____REV16P9 ..\\Core\\Include\\core_cminstr.h‹ì..\\Pre_Drivers\\ex_rtc.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM__asm___8_ex_rtc_c_b7bc8562____REVSHP9 ..\\Core\\Include\\core_cminstr.hš0ÿÿÿÿarmcc+|     


0ÿÿÿÿarmcc+|     


(ÿÿÿÿarmcc+| JAz„…†‡Ž(ÿÿÿÿarmcc+| 0Az„…†‡Ž(ÿÿÿÿarmcc+|  ,Aw„…†‡ŽAt“{(ÿÿÿÿarmcc+| ®A|Ž(ÿÿÿÿarmcc+| fAŽAzp¸


..\Pre_Drivers\ex_rtc.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM”..\Pre_Drivers\ex_rtc.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMpcalendarpnet_now_time‘pSending_flag8pLast_Send_D8pLast_Send_H8pLast_Send_M8pLast_Sample_D8pLast_Sample_H8pLast_Sample_M8pNext_real_Sample_D8pNext_real_Sample_H8pNext_real_Sample_M8pNext_Sample_D8pNext_Sample_H8pNext_Sample_M8pRTC_corœpRTC_Setting_FlagœpI2C_RECV_DATA4..\Pre_Drivers\ex_rtc.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMJ?“R8025T_readJisaddœ^ibuf?@ilenœ"XiœT$..\Pre_Drivers\ex_rtc.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM0?”,R8025T_write0isaddœ^ibuf?@ilenœ"XiœTX..\Pre_Drivers\ex_rtc.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM,?Ù=Time_Set,iyear‘Îimonthœ°idateœ’iweekœsihourœ`iminœLisecœ8ÌœYtimeA‘TÜ..\Pre_Drivers\ex_rtc.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM®?ۏGet_Time®..\Pre_Drivers\ex_rtc.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMf?„˜set_RTC8025T_peroid_alarmföœYalarmë‘h8. ..\Pre_Drivers\ex_rtc.c/ ..\Pre_Drivers\ex_rtc.c"}|/ ..\Pre_Drivers\ex_rtc.c,#~Ø/ ..\Pre_Drivers\ex_rtc.c=-Q#Q#EACECCEE'Œ/ ..\Pre_Drivers\ex_rtc.c'0+'/+-)$0+'/+-)$]2+'1+    -)$$!Y[]2+'1+    -)$$Y[]2+'1+    -)$$]2+'1+    -;$$iœ/ ..\Pre_Drivers\ex_rtc.c˜'!!}––J}RJVQJUPJW}––0}R0VQ0UP0W}}$*}0*,},‘,‘,W


S


,‘h


R


,UQ,TP,V}®}}}d}df}__DATE__ "Jun 11 2024"__TIME__ "13:38:26"__STDC__ 1__STDC_VERSION__ 199901L__STDC_HOSTED__ 1__STDC_ISO_10646__ 200607__EDG__ 1__EDG_VERSION__ 407__EDG_SIZE_TYPE__ unsigned int__EDG_PTRDIFF_TYPE__ int__GNUC__ 4__GNUC_STDC_INLINE__ 1__GNUC_MINOR__ 7__GNUC_PATCHLEVEL__ 0__VERSION__ "4.7 (EDG gcc mode)"__CHAR16_TYPE__ unsigned short__CHAR32_TYPE__ unsigned int__USER_LABEL_PREFIX__ __CHAR_UNSIGNED__ 1__WCHAR_UNSIGNED__ 1__SIZE_TYPE__ unsigned int__PTRDIFF_TYPE__ int__WCHAR_TYPE__ unsigned short__WINT_TYPE__ unsigned short__INTMAX_TYPE__ long long__UINTMAX_TYPE__ unsigned long long__sizeof_int 4__sizeof_long 4__sizeof_ptr 4__ARMCC_VERSION 5060750__TARGET_CPU_CORTEX_M0 1__TARGET_FPU_SOFTVFP 1__TARGET_FPU_SOFTVFP 1__MICROLIB 1__UVISION_VERSION 525_RTE_ 1__VTOR_PRESENT 1__CC_ARM 1__arm 1__arm__ 1__TARGET_ARCH_6S_M 1__TARGET_ARCH_ARM 0__TARGET_ARCH_THUMB 3__TARGET_ARCH_A64 0__TARGET_ARCH_AARCH32 1__TARGET_PROFILE_M 1__TARGET_FEATURE_HALFWORD 1__TARGET_FEATURE_THUMB 1__TARGET_FEATURE_DMB 1__TARGET_FEATURE_EXTENSION_REGISTER_COUNT 0__APCS_INTERWORK 1__thumb 1__thumb__ 1__t32__ 1__OPTIMISE_SPACE 1__OPTIMIZE_SIZE__ 1__OPTIMISE_LEVEL 0__SOFTFP__ 1Q˜±calendarÇnet_now_timeáSending_flagûLast_Send_DLast_Send_H-Last_Send_MFLast_Sample_DaLast_Sample_H|Last_Sample_M—Next_real_Sample_D·Next_real_Sample_H×Next_real_Sample_M÷Next_Sample_DNext_Sample_H-Next_Sample_MHRTC_cor]RTC_Setting_Flag{I2C_RECV_DATA½R8025T_read½R8025T_write\½Time_Setà½Get_Time,½set_RTC8025T_peroid_alarm/%.123__stdint_h __ARMCLIB_VERSION 5060037__INT64 __int64__INT64_C_SUFFIX__ ll__PASTE2(x,y) x ## y__PASTE(x,y) __PASTE2(x, y)__INT64_C(x) __ESCAPE__(__PASTE(x, __INT64_C_SUFFIX__))__UINT64_C(x) __ESCAPE__(__PASTE(x ## u, __INT64_C_SUFFIX__))__LONGLONG long long#__STDINT_DECLS %__CLIBNS,__CLIBNS yINT8_MIN -128zINT16_MIN -32768{INT32_MIN (~0x7fffffff)|INT64_MIN __INT64_C(~0x7fffffffffffffff)INT8_MAX 127€INT16_MAX 32767INT32_MAX 2147483647‚INT64_MAX __INT64_C(9223372036854775807)…UINT8_MAX 255†UINT16_MAX 65535‡UINT32_MAX 4294967295uˆUINT64_MAX __UINT64_C(18446744073709551615)INT_LEAST8_MIN -128ŽINT_LEAST16_MIN -32768INT_LEAST32_MIN (~0x7fffffff)INT_LEAST64_MIN __INT64_C(~0x7fffffffffffffff)“INT_LEAST8_MAX 127”INT_LEAST16_MAX 32767•INT_LEAST32_MAX 2147483647–INT_LEAST64_MAX __INT64_C(9223372036854775807)™UINT_LEAST8_MAX 255šUINT_LEAST16_MAX 65535›UINT_LEAST32_MAX 4294967295uœUINT_LEAST64_MAX __UINT64_C(18446744073709551615)¡INT_FAST8_MIN (~0x7fffffff)¢INT_FAST16_MIN (~0x7fffffff)£INT_FAST32_MIN (~0x7fffffff)¤INT_FAST64_MIN __INT64_C(~0x7fffffffffffffff)§INT_FAST8_MAX 2147483647¨INT_FAST16_MAX 2147483647©INT_FAST32_MAX 2147483647ªINT_FAST64_MAX __INT64_C(9223372036854775807)­UINT_FAST8_MAX 4294967295u®UINT_FAST16_MAX 4294967295u¯UINT_FAST32_MAX 4294967295u°UINT_FAST64_MAX __UINT64_C(18446744073709551615)¸INTPTR_MIN INT32_MIN¿INTPTR_MAX INT32_MAXÆUINTPTR_MAX UINT32_MAXÌINTMAX_MIN __ESCAPE__(~0x7fffffffffffffffll)ÏINTMAX_MAX __ESCAPE__(9223372036854775807ll)ÒUINTMAX_MAX __ESCAPE__(18446744073709551615ull)ÛPTRDIFF_MIN INT32_MINÜPTRDIFF_MAX INT32_MAXàSIG_ATOMIC_MIN (~0x7fffffff)áSIG_ATOMIC_MAX 2147483647çSIZE_MAX UINT32_MAXíWCHAR_MINîWCHAR_MAXôWCHAR_MIN 0õWCHAR_MAX 65535ùWINT_MIN (~0x7fffffff)úWINT_MAX 2147483647INT8_C(x) (x)‚INT16_C(x) (x)ƒINT32_C(x) (x)„INT64_C(x) __INT64_C(x)†UINT8_C(x) (x ## u)‡UINT16_C(x) (x ## u)ˆUINT32_C(x) (x ## u)‰UINT64_C(x) __UINT64_C(x)ŒINTMAX_C(x) __ESCAPE__(x ## ll)UINTMAX_C(x) __ESCAPE__(x ## ull)¸__INT64¹__LONGLONGLB D:\Keil5\ARM\ARMCC\Bin\..\include\stdint.h4D:\Keil5\ARM\ARMCC\Bin\..\include\stdint.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]signed charshortintlong longunsigned charunsigned shortunsigned intunsigned long longPint8_tˆ8 Pint16_t—9 Pint32_t : Pint64_t§; Puint8_t´> Puint8_t´> Puint16_tÅ? Puint32_t×@ Puint64_tçA Pu32fCPu16VDPu88EPint_least8_tˆM Pint_least16_t—N Pint_least32_t O Pint_least64_t§P Puint_least8_t´S Puint_least16_tÅT Puint_least32_t×U Puint_least64_tçV Pint_fast8_t [ Pint_fast16_t \ Pint_fast32_t ] Pint_fast64_t§^ Puint_fast8_t×a Puint_fast16_t×b Puint_fast32_t×c Puint_fast64_tçd Pintptr_t k Puintptr_t×l Pintmax_t§p!Puintmax_tçq!567'__CORE_CMINSTR_H <__NOP __nopD__WFI __wfiL__WFE __wfeS__SEV __sev\__ISB() do { __schedule_barrier(); __isb(0xF); __schedule_barrier(); } while (0)g__DSB() do { __schedule_barrier(); __dsb(0xF); __schedule_barrier(); } while (0)r__DMB() do { __schedule_barrier(); __dmb(0xF); __schedule_barrier(); } while (0)__REV __rev©__ROR __ror´__BKPT(value) __breakpoint(value)Ú__CLZ __clz@6 ..\Core\Include\core_cminstr.h


..\Core\Include\core_cminstr.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM;†Á9__RBITf$fvaluea__resultf\resultf\s9:;'__CORE_CMFUNC_H @5 ..\Core\Include\core_cmfunc.h€


..\Core\Include\core_cmfunc.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM;ÿ@__get_CONTROLfa__resultfY__regControlfP<¸M__set_CONTROL$fcontrolY__regControlfP;òZ__get_IPSRfa__resultfY__regIPSRfP;¬g__get_APSRfa__resultfY__regAPSRfP;æt__get_xPSRfa__resultfY__regXPSRfP;¯__get_PSPfa__resultfY__regProcessStackPointerfP<øŽ__set_PSP$ftopOfProcStackY__regProcessStackPointerfP;¾›__get_MSPfa__resultfY__regMainStackPointerfP<„¨__set_MSP$ftopOfMainStackY__regMainStackPointerfP;ŵ__get_PRIMASKfa__resultfY__regPriMaskfP<ÿÂ__set_PRIMASK$fpriMaskY__regPriMaskfP=>? __CORE_CM0PLUS_H_GENERIC "@__CM0PLUS_CMSIS_VERSION_MAIN ( 5U)A__CM0PLUS_CMSIS_VERSION_SUB ( 0U)B__CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | __CM0PLUS_CMSIS_VERSION_SUB )E__CORTEX_M (0U)Q__ASM __asmR__INLINE __inlineS__STATIC_INLINE static __inlineT__NO_RETURN __declspec(noreturn)U__USED __attribute__((used))V__WEAK __attribute__((weak))W__UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))Ÿ__FPU_USED 0UÆÇÒ__CORE_CM0PLUS_H_DEPENDANT ÿ__I volatile const__O volatile‚__IO volatile…__IM volatile const†__OM volatile‡__IOM volatile³APSR_N_Pos 31U´APSR_N_Msk (1UL << APSR_N_Pos)¶APSR_Z_Pos 30U·APSR_Z_Msk (1UL << APSR_Z_Pos)¹APSR_C_Pos 29UºAPSR_C_Msk (1UL << APSR_C_Pos)¼APSR_V_Pos 28U½APSR_V_Msk (1UL << APSR_V_Pos)ÎIPSR_ISR_Pos 0UÏIPSR_ISR_Msk (0x1FFUL )æxPSR_N_Pos 31UçxPSR_N_Msk (1UL << xPSR_N_Pos)éxPSR_Z_Pos 30UêxPSR_Z_Msk (1UL << xPSR_Z_Pos)ìxPSR_C_Pos 29UíxPSR_C_Msk (1UL << xPSR_C_Pos)ïxPSR_V_Pos 28UðxPSR_V_Msk (1UL << xPSR_V_Pos)òxPSR_T_Pos 24UóxPSR_T_Msk (1UL << xPSR_T_Pos)õxPSR_ISR_Pos 0UöxPSR_ISR_Msk (0x1FFUL )ˆCONTROL_SPSEL_Pos 1U‰CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)‹CONTROL_nPRIV_Pos 0UŒCONTROL_nPRIV_Msk (1UL )ÈSCB_CPUID_IMPLEMENTER_Pos 24UÉSCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)ËSCB_CPUID_VARIANT_Pos 20UÌSCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)ÎSCB_CPUID_ARCHITECTURE_Pos 16UÏSCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)ÑSCB_CPUID_PARTNO_Pos 4UÒSCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)ÔSCB_CPUID_REVISION_Pos 0UÕSCB_CPUID_REVISION_Msk (0xFUL )ØSCB_ICSR_NMIPENDSET_Pos 31UÙSCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)ÛSCB_ICSR_PENDSVSET_Pos 28UÜSCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)ÞSCB_ICSR_PENDSVCLR_Pos 27UßSCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)áSCB_ICSR_PENDSTSET_Pos 26UâSCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)äSCB_ICSR_PENDSTCLR_Pos 25UåSCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)çSCB_ICSR_ISRPREEMPT_Pos 23UèSCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)êSCB_ICSR_ISRPENDING_Pos 22UëSCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)íSCB_ICSR_VECTPENDING_Pos 12UîSCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)ðSCB_ICSR_VECTACTIVE_Pos 0UñSCB_ICSR_VECTACTIVE_Msk (0x1FFUL )õSCB_VTOR_TBLOFF_Pos 8UöSCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)úSCB_AIRCR_VECTKEY_Pos 16UûSCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)ýSCB_AIRCR_VECTKEYSTAT_Pos 16UþSCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)€SCB_AIRCR_ENDIANESS_Pos 15USCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)ƒSCB_AIRCR_SYSRESETREQ_Pos 2U„SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)†SCB_AIRCR_VECTCLRACTIVE_Pos 1U‡SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)ŠSCB_SCR_SEVONPEND_Pos 4U‹SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)SCB_SCR_SLEEPDEEP_Pos 2UŽSCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)SCB_SCR_SLEEPONEXIT_Pos 1U‘SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)”SCB_CCR_STKALIGN_Pos 9U•SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)—SCB_CCR_UNALIGN_TRP_Pos 3U˜SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)›SCB_SHCSR_SVCALLPENDED_Pos 15UœSCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)´SysTick_CTRL_COUNTFLAG_Pos 16UµSysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)·SysTick_CTRL_CLKSOURCE_Pos 2U¸SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)ºSysTick_CTRL_TICKINT_Pos 1U»SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)½SysTick_CTRL_ENABLE_Pos 0U¾SysTick_CTRL_ENABLE_Msk (1UL )ÁSysTick_LOAD_RELOAD_Pos 0UÂSysTick_LOAD_RELOAD_Msk (0xFFFFFFUL )ÅSysTick_VAL_CURRENT_Pos 0UÆSysTick_VAL_CURRENT_Msk (0xFFFFFFUL )ÉSysTick_CALIB_NOREF_Pos 31UÊSysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)ÌSysTick_CALIB_SKEW_Pos 30UÍSysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)ÏSysTick_CALIB_TENMS_Pos 0UÐSysTick_CALIB_TENMS_Msk (0xFFFFFFUL )éMPU_TYPE_IREGION_Pos 16UêMPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)ìMPU_TYPE_DREGION_Pos 8UíMPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)ïMPU_TYPE_SEPARATE_Pos 0UðMPU_TYPE_SEPARATE_Msk (1UL )óMPU_CTRL_PRIVDEFENA_Pos 2UôMPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)öMPU_CTRL_HFNMIENA_Pos 1U÷MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)ùMPU_CTRL_ENABLE_Pos 0UúMPU_CTRL_ENABLE_Msk (1UL )ýMPU_RNR_REGION_Pos 0UþMPU_RNR_REGION_Msk (0xFFUL )MPU_RBAR_ADDR_Pos 8U‚MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)„MPU_RBAR_VALID_Pos 4U…MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos)‡MPU_RBAR_REGION_Pos 0UˆMPU_RBAR_REGION_Msk (0xFUL )‹MPU_RASR_ATTRS_Pos 16UŒMPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos)ŽMPU_RASR_XN_Pos 28UMPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos)‘MPU_RASR_AP_Pos 24U’MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos)”MPU_RASR_TEX_Pos 19U•MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos)—MPU_RASR_S_Pos 18U˜MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos)šMPU_RASR_C_Pos 17U›MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos)MPU_RASR_B_Pos 16UžMPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) MPU_RASR_SRD_Pos 8U¡MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos)£MPU_RASR_SIZE_Pos 1U¤MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos)¦MPU_RASR_ENABLE_Pos 0U§MPU_RASR_ENABLE_Msk (1UL )Ä_VAL2FLD(field,value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)Ì_FLD2VAL(field,value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)ÙSCS_BASE (0xE000E000UL)ÚSysTick_BASE (SCS_BASE + 0x0010UL)ÛNVIC_BASE (SCS_BASE + 0x0100UL)ÜSCB_BASE (SCS_BASE + 0x0D00UL)ÞSCB ((SCB_Type *) SCB_BASE )ßSysTick ((SysTick_Type *) SysTick_BASE )àNVIC ((NVIC_Type *) NVIC_BASE )ãMPU_BASE (SCS_BASE + 0x0D90UL)äMPU ((MPU_Type *) MPU_BASE )‚_BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)ƒ_SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )„_IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )”ˆ ..\Core\Include\D:\Keil5\ARM\ARMCC\Bin\..\include\core_cm0plus.hstdint.hcore_cminstr.hcore_cmfunc.h°


..\Core\Include\core_cm0plus.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM*”!_reserved0f#!Vf#!Cf#!Zf#!Nf#S§bÀwfPAPSR_Type°*å!ISRf#    !_reserved0f#Søb9wfPIPSR_TypeeË*“!ISRf#    !_reserved0f#!Tf#!_reserved1f#!Vf#!Cf#!Zf#!Nf#S¦bŠwfPxPSR_Typeã*ø!nPRIVf#!SPSELf#!_reserved1f#S‹b8wfPCONTROL_Typex…*  ® ISER¥#ÅfRESERVED0º#ß ICERÖ#€÷fRSERVED1ì#„‘ ISPR#€©fRESERVED2#„Ä ICPR;#€ÜfRESERVED3Q#„ùf?RESERVED4n#€” IP‹#€tfPNVIC_Type §*¹(CPUID?#ICSR #VTOR #AIRCR #SCR #CCR #RESERVED1f#  SHP#SHCSR #$ft9PSCB_Type¸Å*‰    CTRL #LOAD #VAL #CALIB?#PSysTick_TypeT±*Þ    TYPE?#CTRL #RNR #RBAR #RASR #PMPU_Typežæ<’


NVIC_EnableIRQ$(IRQn<¶


œNVIC_DisableIRQ$(IRQn;ò


­NVIC_GetPendingIRQf$(IRQna__resultf<™ÀNVIC_SetPendingIRQ$(IRQn<ÂÏNVIC_ClearPendingIRQ$(IRQn<öáNVIC_SetPriority$(IRQn$fpriority;°ùNVIC_GetPriorityf$(IRQna__resultf<Ê‹NVIC_SystemReset;÷¬SCB_GetFPUTypefa__resultf;° ËSysTick_Configf$fticksa__resultfABCD__stdio_h __ARMCLIB_VERSION 5060037"_ARMABI __declspec(__nothrow)%__STDIO_DECLS '__CLIBNS-__CLIBNS <NULL=NULL 0g_SYS_OPEN 16¥stdin (&__CLIBNS __stdin)§stdout (&__CLIBNS __stdout)©stderr (&__CLIBNS __stderr)¬_IOFBF 0x100­_IOLBF 0x200®_IONBF 0x400±BUFSIZ (512)³FOPEN_MAX _SYS_OPEN¹FILENAME_MAX 256¾L_tmpnam FILENAME_MAXÄTMP_MAX 256ÌEOF (-1)ÒSEEK_SET 0ÓSEEK_CUR 1ÔSEEK_END 2Ú_IOBIN 0x04Ü__STDIN_BUFSIZ (64)Ý__STDOUT_BUFSIZ (64)Þ__STDERR_BUFSIZ (16)¿getchar() getc(stdin)àputchar(c) putc(c, stdout)LA D:\Keil5\ARM\ARMCC\Bin\..\include\stdio.h´D:\Keil5\ARM\ARMCC\Bin\..\include\stdio.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]unsigned intunsigned long longPsize_t‡5P__va_listüF*ó__state1‡#__state2‡#)¦__fpos_t_struct__pos—#__mbstateÎ#Pfpos_tóa-__FILEPFILE4lq__stdin<q__stdout<q__stderr<"<q__aeabi_stdintq__aeabi_stdouttq__aeabi_stderrtl¸H__stdinV__stdoute__stderrx__aeabi_stdinŒ__aeabi_stdout¡__aeabi_stderrFGH$FM33A0XXEV_H .__RCHF_INITIAL_CLOCK (8000000)/__RCMF_CLOCK (2000000)0__RCLP_CLOCK (32000)1__XTLF_CLOCK (32768)n__CM0_REV 0x0100o__MPU_PRESENT 1p__VTOR_PRESENT 1q__NVIC_PRIO_BITS 2r__Vendor_SysTickConfig 0uv¿FLASH_BASE (( uint32_t)0x00000000)ÀSRAM_BASE (( uint32_t)0x20000000)ÁPERIPH_BASE (( uint32_t)0x40000000)ÊPMU_BASE (PERIPH_BASE +0x00002000)ËDBG_BASE (PERIPH_BASE +0x00000000)ÌFLS_BASE (PERIPH_BASE +0x00001000)ÍRMU_BASE (PERIPH_BASE +0x00002800)ÎIWDT_BASE (PERIPH_BASE +0x00011400)ÏWWDT_BASE (PERIPH_BASE +0x00011800)ÐCMU_BASE (PERIPH_BASE +0x00002400)ÑCDIF_BASE (PERIPH_BASE +0x0001E000)ÒVRTC_BASE (PERIPH_BASE +0x0001F800)ÓSVD_BASE (PERIPH_BASE +0x00012800)ÔAES_BASE (PERIPH_BASE +0x00013800)ÕPAE_BASE (PERIPH_BASE +0x00001400)ÖHASH_BASE (PERIPH_BASE +0x00001800)×RNG_BASE (PERIPH_BASE +0x00013C00)ØCOMP_BASE (PERIPH_BASE +0x00015400)ÙI2C0_BASE (PERIPH_BASE +0x00012400)ÚI2C1_BASE (PERIPH_BASE +0x00015000)ÛUARTIR_BASE (PERIPH_BASE +0x00017C00)ÜUART0_BASE (PERIPH_BASE +0x00012000)ÝUART1_BASE (PERIPH_BASE +0x00016800)ÞUART2_BASE (PERIPH_BASE +0x00016C00)ßUART3_BASE (PERIPH_BASE +0x00017000)àUART4_BASE (PERIPH_BASE +0x00017400)áUART5_BASE (PERIPH_BASE +0x00017800)âLPUART0_BASE (PERIPH_BASE +0x00014000)ãLPUART1_BASE (PERIPH_BASE +0x00014400)äSPI0_BASE (PERIPH_BASE +0x00010400)åSPI1_BASE (PERIPH_BASE +0x00010800)æSPI2_BASE (PERIPH_BASE +0x00014800)çSPI3_BASE (PERIPH_BASE +0x00014C00)èSPI4_BASE (PERIPH_BASE +0x00016400)éU7816_BASE (PERIPH_BASE +0x00011C00)êQSPI_BASE (PERIPH_BASE +0x00000800)ëDMA_BASE (PERIPH_BASE +0x00000400)ìCRC_BASE (PERIPH_BASE +0x00010000)íBT1_BASE (PERIPH_BASE +0x00013000)îBT2_BASE (PERIPH_BASE +0x00013044)ïET1_BASE (PERIPH_BASE +0x00013090)ðET2_BASE (PERIPH_BASE +0x000130B0)ñET3_BASE (PERIPH_BASE +0x000130D0)òET4_BASE (PERIPH_BASE +0x000130F0)óETCNT_BASE (PERIPH_BASE +0x00013110)ôBSTIM_BASE (PERIPH_BASE +0x00016000)õLPTIM_BASE (PERIPH_BASE +0x00013400)öRTC_BASE (PERIPH_BASE +0x00011000)÷LCD_BASE (PERIPH_BASE +0x00010C00)øADC_BASE (PERIPH_BASE +0x0001FA00)ùCIC_BASE (PERIPH_BASE +0x00015C00)úGPIOA_BASE (PERIPH_BASE +0x00000C00)ûGPIOB_BASE (PERIPH_BASE +0x00000C40)üGPIOC_BASE (PERIPH_BASE +0x00000C80)ýGPIOD_BASE (PERIPH_BASE +0x00000CC0)þGPIOE_BASE (PERIPH_BASE +0x00000D00)ÿGPIOF_BASE (PERIPH_BASE +0x00000D40)€GPIOG_BASE (PERIPH_BASE +0x00000D80)GPIOH_BASE (PERIPH_BASE +0x0001FC00)‚GPIO_BASE (PERIPH_BASE +0x00000DC0)ˆPMU ((PMU_Type *) PMU_BASE )‰DBG ((DBG_Type *) DBG_BASE )ŠFLS ((FLS_Type *) FLS_BASE )‹RMU ((RMU_Type *) RMU_BASE )ŒIWDT ((IWDT_Type *) IWDT_BASE )WWDT ((WWDT_Type *) WWDT_BASE )ŽCMU ((CMU_Type *) CMU_BASE )CDIF ((CDIF_Type *) CDIF_BASE )VRTC ((VRTC_Type *) VRTC_BASE )‘SVD ((SVD_Type *) SVD_BASE )’AES ((AES_Type *) AES_BASE )“PAE ((PAE_Type *) PAE_BASE )”HASH ((HASH_Type *) HASH_BASE )•RNG ((RNG_Type *) RNG_BASE )–COMP ((COMP_Type *) COMP_BASE )—I2C0 ((I2C_Type *) I2C0_BASE )˜I2C1 ((I2C_Type *) I2C1_BASE )™UARTIR ((UARTIR_Type *) UARTIR_BASE )šUART0 ((UART_Type *) UART0_BASE )›UART1 ((UART_Type *) UART1_BASE )œUART2 ((UART_Type *) UART2_BASE )UART3 ((UART_Type *) UART3_BASE )žUART4 ((UART_Type *) UART4_BASE )ŸUART5 ((UART_Type *) UART5_BASE ) LPUART0 ((LPUART_Type *) LPUART0_BASE )¡LPUART1 ((LPUART_Type *) LPUART1_BASE )¢SPI0 ((SPI_Type *) SPI0_BASE )£SPI1 ((SPI_Type *) SPI1_BASE )¤SPI2 ((SPI_Type *) SPI2_BASE )¥SPI3 ((SPI_Type *) SPI3_BASE )¦SPI4 ((SPI_Type *) SPI4_BASE )§U7816 ((U7816_Type *) U7816_BASE )¨QSPI ((QSPI_Type *) QSPI_BASE )©DMA ((DMA_Type *) DMA_BASE )ªCRC ((CRC_Type *) CRC_BASE )«BT1 ((BT_Type *) BT1_BASE )¬BT2 ((BT_Type *) BT2_BASE )­ET1 ((ET_Type *) ET1_BASE )®ET2 ((ET_Type *) ET2_BASE )¯ET3 ((ET_Type *) ET3_BASE )°ET4 ((ET_Type *) ET4_BASE )±ETCNT ((ETCNT_Type *) ETCNT_BASE )²BSTIM ((BSTIM_Type *) BSTIM_BASE )³LPTIM ((LPTIM_Type *) LPTIM_BASE )´RTC ((RTC_Type *) RTC_BASE )µLCD ((LCD_Type *) LCD_BASE )¶ADC ((ADC_Type *) ADC_BASE )·CIC ((CIC_Type *) CIC_BASE )¸GPIOA ((GPIO_Type *) GPIOA_BASE )¹GPIOB ((GPIO_Type *) GPIOB_BASE )ºGPIOC ((GPIO_Type *) GPIOC_BASE )»GPIOD ((GPIO_Type *) GPIOD_BASE )¼GPIOE ((GPIO_Type *) GPIOE_BASE )½GPIOF ((GPIO_Type *) GPIOF_BASE )¾GPIOG ((GPIO_Type *) GPIOG_BASE )¿GPIOH ((GPIOH_Type *) GPIOH_BASE )ÀGPIO ((GPIO_COMMON_Type *) GPIO_BASE )h] ..\Core\Include\FM33A0XXEV.hcore_cm0plus.hsystem_FM33A0XXEV.h¬


..\Core\Include\FM33A0XXEV.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMÓRESETSETPFlagStatus¾*(PITStatus¾*4DISABLEENABLEPFunStateõ+/´FAILPASSPErrorStatus,'¨Reset_IRQnqNMI_IRQnrHardFault_IRQnsSVC_IRQn{PendSV_IRQn~SysTick_IRQnWWDT_IRQnSVD_IRQnRTC_IRQnFLASH_IRQnCMU_IRQnADC_IRQnSPI0_IRQnSPI1_IRQnSPI2_IRQnUART0_IRQn    UART1_IRQn


UART2_IRQnUART3_IRQnUART4_IRQn UART5_IRQnU7816_IRQnLPUART0_IRQnI2Cx_IRQnRSV_IRQnCRYPTO_IRQnLPTIM_IRQnDMA_IRQnWKUPx_IRQnCOMP_IRQnBTx_IRQnQSPI_IRQnETx_IRQnBSTIM_IRQnSPI3_IRQnSPI4_IRQnGPIO_IRQnLPUART1_IRQnPIRQn_TypeGb*öCRv#WKTRv#WKFRv#IERv#ISRv#tfPPMU_Type9œ*´RSV1v#CRv#HDFRv#PDBG_Type¨*‚    XRDCRv#PFCRv#OPTBRˆ#÷vRSV1î#EPCRv#KEYv#IERv#ISRv# ¹vRSV20#$ACLOCK1v#HACLOCK2v#LACLOCK3v#PACLOCK4v#Tft‚PFLS_Typež*Ÿ


$PDRCRv#BORCRv#RSTCFGRv#SOFTRSTv#RSRv#PRSTENv#AHBRSTv#APBRST1v#APBRST2v# PRMU_TypeÐ*Ù


SERVv#CFGRv#CNTRˆ#PIWDT_Type0Ü*´CRv#CFGRv#CNTRˆ#IERv#ISRv#PSCRˆ#PWWDT_Typekë* 8SYSCLKCRv#RCHFCRv#RCHFTRv#PLLLCRv#PLLHCRv#XTHFCRv#IERv#ISRv#PCLKCR1v# PCLKCR2v#$PCLKCR3v#(PCLKCR4v#,OPCCR1v#0OPCCR2v#4PCMU_TypeÆ‚*» CRv#PSCRv#PCDIF_Type Œ*Õ0PDRCRv#ç vRSV1Þ#RCMFCRv#RCLPCRv#RCLPTRv#XTLFCRv# ADCCRv#$LFDIERv#(LFDISRv#,PVRTC_TypeÍž*£CFGRv#CRv#IERv#ISRv#VSRv#PSVD_Typeg¬*§TCRv#IERv#ISRv#DIRv#DORˆ#KEY0v#KEY1v#KEY2v#KEY3v# KEY4v#$KEY5v#(KEY6v#,KEY7v#0IVR0v#4IVR1v#8IVR2v#<IVR3v#@H0v#DH1v#HH2v#LH3v#PPAES_Type´Ê*ž CSRv#MLRv#MPRv#M0CFGv#M1CFGv#M2CFGv#M3CFGv#WORDv#PPAE_Type¸Û*ÊCSRv#DTRv#PHASH_Type/    æ*À CRv#DORˆ#þvRSV1u    #SRv#CRC_CRv#CRC_DIRv#CRC_SRv#PRNG_Type\    ö*CR1v#CR2v#ICRv#ISRv#PCRv#PCOMP_TypeÑ    „*ˆ$CFGRv#CRv#IERv#ISRv#SRv#BRGv#BUFv#TIMINGv#TOv# PI2C_Type


–*¨CRv#PUARTIR_Type™


 *“CSRv#IERv#ISRv#TODRv#RXBUFˆ#TXBUFv#BGRv#PUART_Type¼


°*ûCSRv#IERv#ISRv#BMRv#RXBUFv#TXBUFv#DMRv#PLPUART_Type%À*åCR1v#CR2v#CR3v#IERv#ISRv#TXBUFv#RXBUFˆ#PSPI_TypeÐ*â$CRv#FFRv#EGTRv#PSCv#BGRv#RXBUFˆ#TXBUFv#IERv#ISRv# PU7816_Typeöâ*‚0CRv#CFGv#SRv#DATALENv#CCRv#ADDRv#ABRv#DRv#SMSKv# SMATv#$PITVv#(TOv#,PQSPI_Typeu÷*õ¸GCRv#CH0CRv#CH0MARv#CH1CRv#CH1MARv#CH2CRv#CH2MARv#CH3CRv#CH3MARv# CH4CRv#$CH4MARv#(CH5CRv#,CH5MARv#0CH6CRv#4CH6MARv#8CH7CRv#<CH7MARv#@CH8CRv#DCH8MARv#HCH9CRv#LCH9MARv#PCH10CRv#TCH10MARv#XCH11CRv#\CH11FARv#`CH11RARv#dISRv#hv$RSV1†#lCH0CSRv#€CH0MASRv#„CH1CSRv#ˆCH1MASRv#ŒCH2CSRv#CH2MASRv#”CH3CSRv#˜CH3MASRv#œCH4CSRv# CH4MASRv#¤CH5CSRv#¨CH5MASRv#¬CH6CSRv#°CH6MASRv#´PDMA_Type ª*× DRv#CRv#LFSRv#XORv#¾vRSV1µ#POLYv#PCRC_Type†¹*¾!DCR1v#CR2v#CFGR1v#CFGR2v#PRESv#LOADCRv#CNTLˆ#CNTHˆ#PRESETv# LOADLv#$LOADHv#(CMPLv#,CMPHv#0OUTCNTv#4OCRv#8IERv#<ISRv#@PBT_TypeèÓ*°" CRv#INSRv#PSCR1v#PSCR2v#IVRv#CMPRv#IERv#ISRv#PET_TypeÎä*õ"CNT1v#CNT2v#CNT3v#CNT4v#PETCNT_Type@ï*ˆ$0CR1v#CR2v#RSV1v#IERv#ISRv#EGRv#Ø#vRSV2Ï#CNTRv#$PSCRv#(ARRv#,PBSTIM_Typeˆ*«%0CFGRv#CNTRˆ#CCSRv#ARRv#IERv#ISRv#CRv#RSV1v#CCR1v# CCR2v#$CCR3v#(CCR4v#,PLPTIM_Type–*ø'€WERv#IERv#ISRv#BCDSECv#BCDMINv#BCDHOURv#BCDDATEv#BCDWEEKv#BCDMONTHv# BCDYEARv#$ALARMv#(TMSELv#,ADJUSTv#0ADSIGNv#4VCALv#8MSCNTv#<CALSTEPv#@ADCNTˆ#DSSRˆ#HSSAv#LDTRv#Pá'v    RSV1Ø#TCRv#|PRTC_Type¾¶*¿*`CRv#TESTv#FCRv#FLKTv#RSV1v#IERv#ISRv#å(vRSV2\#DATA0v#$DATA1v#(DATA2v#,DATA3v#0DATA4v#4DATA5v#8DATA6v#<DATA7v#@DATA8v#DDATA9v#Hü)vRSV3ó#LCOMENv#PSEGEN0v#TSEGEN1v#XBSTCRv#\PLCD_Type    Õ*Œ+CRv#TRIMv#DRˆ#ISRv#CFGRv#PADC_TypePã*×+DRˆ#OSv#USDRˆ#CRv#ISRv#PCIC_Typeñ*ë,,INENv#PUENv#ODENv#FCRv#DOv#DSETv#DRSTv#DINˆ#DFSv# RSVv#$ANENv#(PGPIO_Typeè…*º-INENv#PUENv#FCRv#DOv#DINv#PGPIOH_Type}’*”/ÄEXTISEL0v#EXTISEL1v#EXTIEDS0v#EXTIEDS1v#EXTIDFv#EXTIISRv#EXTIDIˆ#Æ.vRSV1=#FOUTSELv#@IOMCRv#D÷.v=RSV2n#HPINWKENv#ÀPGPIO_COMMON_TypeͦJKLM(SYSTEM_FM33A0XXEV_H 234O__SYSTEM_CLOCK (8000000)PDELAY_US (__SYSTEM_CLOCK/1000000)QDELAY_MS (__SYSTEM_CLOCK/1000)TDo_DelayStart() { uint32_t LastTick = SysTick->VAL; do {WWhile_DelayMsEnd(Count) }while(((LastTick - SysTick->VAL)&0xFFFFFF)<DELAY_MS*Count); }ZWhile_DelayUsEnd(Count) }while(((LastTick - SysTick->VAL)&0xFFFFFF)<DELAY_US*Count); }… ..\Core\Include\D:\Keil5\ARM\ARMCC\Bin\..\include\system_FM33A0XXEV.hstdint.hstdio.hFM33A0XXEV.hÜ


..\Core\Include\system_FM33A0XXEV.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMqSystemCoreClockf"àÅSystemCoreClockOPQ__FM33A0XXEV_AES_H )AES_CR_KEYLEN_Pos 13/AES_CR_KEYLEN_Msk (0x3U << AES_CR_KEYLEN_Pos)0AES_CR_KEYLEN_128BIT (0x0U << AES_CR_KEYLEN_Pos)1AES_CR_KEYLEN_192BIT (0x1U << AES_CR_KEYLEN_Pos)2AES_CR_KEYLEN_256BIT (0x2U << AES_CR_KEYLEN_Pos)3AES_CR_KEYLEN_ (0x3U << AES_CR_KEYLEN_Pos)5AES_CR_DMAOEN_Pos 12:AES_CR_DMAOEN_Msk (0x1U << AES_CR_DMAOEN_Pos)=AES_CR_DMAIEN_Pos 11BAES_CR_DMAIEN_Msk (0x1U << AES_CR_DMAIEN_Pos)EAES_CR_CHMOD_Pos 5KAES_CR_CHMOD_Msk (0x3U << AES_CR_CHMOD_Pos)LAES_CR_CHMOD_ECB (0x0U << AES_CR_CHMOD_Pos)MAES_CR_CHMOD_CBC (0x1U << AES_CR_CHMOD_Pos)NAES_CR_CHMOD_CTR (0x2U << AES_CR_CHMOD_Pos)OAES_CR_CHMOD_MULTH (0x3U << AES_CR_CHMOD_Pos)QAES_CR_MODE_Pos 3XAES_CR_MODE_Msk (0x3U << AES_CR_MODE_Pos)YAES_CR_MODE_ENCRYPT (0x0U << AES_CR_MODE_Pos)ZAES_CR_MODE_KEYEXP (0x1U << AES_CR_MODE_Pos)[AES_CR_MODE_DECRYPT (0x2U << AES_CR_MODE_Pos)\AES_CR_MODE_KEYEXPDECRYPT (0x3U << AES_CR_MODE_Pos)^AES_CR_DATATYP_Pos 1dAES_CR_DATATYP_Msk (0x3U << AES_CR_DATATYP_Pos)eAES_CR_DATATYP_32BITNOEX (0x0U << AES_CR_DATATYP_Pos)fAES_CR_DATATYP_16BITEX (0x1U << AES_CR_DATATYP_Pos)gAES_CR_DATATYP_8BITEX (0x2U << AES_CR_DATATYP_Pos)hAES_CR_DATATYP_1BITEX (0x3U << AES_CR_DATATYP_Pos)jAES_CR_EN_Pos 0oAES_CR_EN_Msk (0x1U << AES_CR_EN_Pos)sAES_IER_WRERR_IE_Pos 2tAES_IER_WRERR_IE_Msk (0x1U << AES_IER_WRERR_IE_Pos)vAES_IER_RDERR_IE_Pos 1wAES_IER_RDERR_IE_Msk (0x1U << AES_IER_RDERR_IE_Pos)yAES_IER_CCF_IE_Pos 0zAES_IER_CCF_IE_Msk (0x1U << AES_IER_CCF_IE_Pos)|AES_DIR_DIN_Pos 0AES_DIR_DIN_Msk (0xffffffffU << AES_DIR_DIN_Pos)ƒAES_DOR_DOUT_Pos 0ˆAES_DOR_DOUT_Msk (0xffffffffU << AES_DOR_DOUT_Pos)ŠAES_KEY0_KEYx_Pos 0ŒAES_KEY0_KEYx_Msk (0xffffffffU << AES_KEY0_KEYx_Pos)ŽAES_KEY1_KEYx_Pos 0AES_KEY1_KEYx_Msk (0xffffffffU << AES_KEY1_KEYx_Pos)’AES_KEY2_KEYx_Pos 0”AES_KEY2_KEYx_Msk (0xffffffffU << AES_KEY2_KEYx_Pos)–AES_KEY3_KEYx_Pos 0˜AES_KEY3_KEYx_Msk (0xffffffffU << AES_KEY3_KEYx_Pos)šAES_KEY4_KEYx_Pos 0œAES_KEY4_KEYx_Msk (0xffffffffU << AES_KEY4_KEYx_Pos)žAES_KEY5_KEYx_Pos 0 AES_KEY5_KEYx_Msk (0xffffffffU << AES_KEY5_KEYx_Pos)¢AES_KEY6_KEYx_Pos 0¤AES_KEY6_KEYx_Msk (0xffffffffU << AES_KEY6_KEYx_Pos)¦AES_KEY7_KEYx_Pos 0¨AES_KEY7_KEYx_Msk (0xffffffffU << AES_KEY7_KEYx_Pos)ªAES_IVR0_IVRx_Pos 0¬AES_IVR0_IVRx_Msk (0xffffffffU << AES_IVR0_IVRx_Pos)®AES_IVR1_IVRx_Pos 0°AES_IVR1_IVRx_Msk (0xffffffffU << AES_IVR1_IVRx_Pos)²AES_IVR2_IVRx_Pos 0´AES_IVR2_IVRx_Msk (0xffffffffU << AES_IVR2_IVRx_Pos)¶AES_IVR3_IVRx_Pos 0¸AES_IVR3_IVRx_Msk (0xffffffffU << AES_IVR3_IVRx_Pos)ºAES_H0_Hx_Pos 0¼AES_H0_Hx_Msk (0xffffffffU << AES_H0_Hx_Pos)¾AES_H1_Hx_Pos 0ÀAES_H1_Hx_Msk (0xffffffffU << AES_H1_Hx_Pos)ÂAES_H2_Hx_Pos 0ÄAES_H2_Hx_Msk (0xffffffffU << AES_H2_Hx_Pos)ÆAES_H3_Hx_Pos 0ÈAES_H3_Hx_Msk (0xffffffffU << AES_H3_Hx_Pos)ÊAES_ISR_WRERR_Pos 2ËAES_ISR_WRERR_Msk (0x1U << AES_ISR_WRERR_Pos)ÍAES_ISR_RDERR_Pos 1ÎAES_ISR_RDERR_Msk (0x1U << AES_ISR_RDERR_Pos)ÐAES_ISR_CCF_Pos 0ÓAES_ISR_CCF_Msk (0x1U << AES_ISR_CCF_Pos)`T ..\Drivers\..\Core\Include\fm33a0xxev_aes.hFM33A0XXEV.ht


..\Drivers\fm33a0xxev_aes.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM*ÞKEYLENf#CHMODf#MODEf#DATATYPf#DMAOEN#DMAIEN#WERRIE#RERRIE#CCFIE#AESEN#PAES_InitTypeDef½'STU__FM33A0XXEV_ADC_H ADC_CR_ADC_IE_Pos 7ADC_CR_ADC_IE_Msk (0x1U << ADC_CR_ADC_IE_Pos)ADC_CR_ACC_IE_Pos 6ADC_CR_ACC_IE_Msk (0x1U << ADC_CR_ACC_IE_Pos)ADC_CR_HPEN_Pos 3"ADC_CR_HPEN_Msk (0x1U << ADC_CR_HPEN_Pos)#ADC_CR_HPEN_1MHZ (0x0U << ADC_CR_HPEN_Pos)$ADC_CR_HPEN_2MHZ (0x1U << ADC_CR_HPEN_Pos)&ADC_CR_MODE_Pos 2)ADC_CR_MODE_Msk (0x1U << ADC_CR_MODE_Pos)*ADC_CR_MODE_INNER (0x0U << ADC_CR_MODE_Pos)+ADC_CR_MODE_EXTERNAL (0x1U << ADC_CR_MODE_Pos)-ADC_CR_RSTCTRL_EN_Pos 10ADC_CR_RSTCTRL_EN_Msk (0x1U << ADC_CR_RSTCTRL_EN_Pos)4ADC_CR_EN_Pos 09ADC_CR_EN_Msk (0x1U << ADC_CR_EN_Pos)>ADC_TRIM_ADC_TRIM_Pos 0AADC_TRIM_ADC_TRIM_Msk (0x7ffU << ADC_TRIM_ADC_TRIM_Pos)CADC_DR_ADC_DATA_Pos 0FADC_DR_ADC_DATA_Msk (0xffffU << ADC_DR_ADC_DATA_Pos)HADC_ISR_INIT_RDY_Pos 9MADC_ISR_INIT_RDY_Msk (0x1U << ADC_ISR_INIT_RDY_Pos)OADC_ISR_ACC_IF_Pos 8PADC_ISR_ACC_IF_Msk (0x1U << ADC_ISR_ACC_IF_Pos)RADC_ISR_ADC_DONE_Pos 1TADC_ISR_ADC_DONE_Msk (0x1U << ADC_ISR_ADC_DONE_Pos)VADC_ISR_ADC_IF_Pos 0WADC_ISR_ADC_IF_Msk (0x1U << ADC_ISR_ADC_IF_Pos)YADC_CFGR_ACC_PERIOD_Pos 16`ADC_CFGR_ACC_PERIOD_Msk (0x7U << ADC_CFGR_ACC_PERIOD_Pos)aADC_CFGR_ACC_PERIOD_10BITS (0x0U << ADC_CFGR_ACC_PERIOD_Pos)bADC_CFGR_ACC_PERIOD_11BITS (0x1U << ADC_CFGR_ACC_PERIOD_Pos)cADC_CFGR_ACC_PERIOD_12BITS (0x2U << ADC_CFGR_ACC_PERIOD_Pos)dADC_CFGR_ACC_PERIOD_13BITS (0x3U << ADC_CFGR_ACC_PERIOD_Pos)eADC_CFGR_ACC_PERIOD_14BITS (0x4U << ADC_CFGR_ACC_PERIOD_Pos)gADC_CFGR_RST_CTRL_DELAY_Pos 8lADC_CFGR_RST_CTRL_DELAY_Msk (0xffU << ADC_CFGR_RST_CTRL_DELAY_Pos)nADC_CFGR_BUFEN_Pos 5oADC_CFGR_BUFEN_Msk (0x1U << ADC_CFGR_BUFEN_Pos)qADC_CFGR_BUFSEL_Pos 0‚ADC_CFGR_BUFSEL_Msk (0xfU << ADC_CFGR_BUFSEL_Pos)ƒADC_CFGR_BUFSEL_ADC_IN1 (0x1U << ADC_CFGR_BUFSEL_Pos)„ADC_CFGR_BUFSEL_ADC_IN2 (0x2U << ADC_CFGR_BUFSEL_Pos)…ADC_CFGR_BUFSEL_ADC_IN3 (0x3U << ADC_CFGR_BUFSEL_Pos)†ADC_CFGR_BUFSEL_ADC_IN4 (0x4U << ADC_CFGR_BUFSEL_Pos)‡ADC_CFGR_BUFSEL_ADC_IN5 (0x5U << ADC_CFGR_BUFSEL_Pos)ˆADC_CFGR_BUFSEL_ADC_IN6 (0x6U << ADC_CFGR_BUFSEL_Pos)‰ADC_CFGR_BUFSEL_ADC_IN7 (0x7U << ADC_CFGR_BUFSEL_Pos)ŠADC_CFGR_BUFSEL_ADC_IN8 (0x8U << ADC_CFGR_BUFSEL_Pos)‹ADC_CFGR_BUFSEL_ADC_IN9 (0x9U << ADC_CFGR_BUFSEL_Pos)ŒADC_CFGR_BUFSEL_ADC_IN10 (0xaU << ADC_CFGR_BUFSEL_Pos)ADC_CFGR_BUFSEL_ADC_IN11 (0xbU << ADC_CFGR_BUFSEL_Pos)ŽADC_CFGR_BUFSEL_ADC_IN12 (0xcU << ADC_CFGR_BUFSEL_Pos)ADC_CFGR_BUFSEL_VBAT (0xeU << ADC_CFGR_BUFSEL_Pos)ADC_CFGR_BUFSEL_TS (0xfU << ADC_CFGR_BUFSEL_Pos)’CIC_DR_ADC_CIC_DATA_Pos 0“CIC_DR_ADC_CIC_DATA_Msk (0xffffffU << CIC_DR_ADC_CIC_DATA_Pos)•CIC_OS_ADC_CIC_OS_Pos 0–CIC_OS_ADC_CIC_OS_Msk (0xffffffU << CIC_OS_ADC_CIC_OS_Pos)˜CIC_USDR_ADC_CIC_USDR_Pos 0™CIC_USDR_ADC_CIC_USDR_Msk (0xffffffU << CIC_USDR_ADC_CIC_USDR_Pos)›CIC_CR_CIC_EN_Pos 31žCIC_CR_CIC_EN_Msk (0x1U << CIC_CR_CIC_EN_Pos)¢CIC_CR_NS_DISC_Pos 8¥CIC_CR_NS_DISC_Msk (0xffU << CIC_CR_NS_DISC_Pos)§CIC_CR_OVR_IE_Pos 7ªCIC_CR_OVR_IE_Msk (0x1U << CIC_CR_OVR_IE_Pos)®CIC_CR_CIC_IE_Pos 6±CIC_CR_CIC_IE_Msk (0x1U << CIC_CR_CIC_IE_Pos)µCIC_CR_TRUNC_Pos 3·CIC_CR_TRUNC_Msk (0x7U << CIC_CR_TRUNC_Pos)¹CIC_CR_OSR_Pos 0ÂCIC_CR_OSR_Msk (0x7U << CIC_CR_OSR_Pos)ÃCIC_CR_OSR_X8 (0x0U << CIC_CR_OSR_Pos)ÄCIC_CR_OSR_X16 (0x1U << CIC_CR_OSR_Pos)ÅCIC_CR_OSR_X32 (0x2U << CIC_CR_OSR_Pos)ÆCIC_CR_OSR_X64 (0x3U << CIC_CR_OSR_Pos)ÇCIC_CR_OSR_X128 (0x4U << CIC_CR_OSR_Pos)ÈCIC_CR_OSR_X256 (0x5U << CIC_CR_OSR_Pos)ÉCIC_CR_OSR_X512 (0x6U << CIC_CR_OSR_Pos)ÊCIC_CR_OSR_X1024 (0x7U << CIC_CR_OSR_Pos)ÌCIC_ISR_CIC_OVR_Pos 1ÍCIC_ISR_CIC_OVR_Msk (0x1U << CIC_ISR_CIC_OVR_Pos)ÏCIC_ISR_CIC_IF_Pos 0ÐCIC_ISR_CIC_IF_Msk (0x1U << CIC_ISR_CIC_IF_Pos)`T ..\Drivers\..\Core\Include\fm33a0xxev_adc.hFM33A0XXEV.h¼


..\Drivers\fm33a0xxev_adc.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMWXY__FM33A0XXEV_BSTIM_H BSTIM_CR1_ARPE_Pos 7BSTIM_CR1_ARPE_Msk (0x1U << BSTIM_CR1_ARPE_Pos) BSTIM_CR1_OPM_Pos 3#BSTIM_CR1_OPM_Msk (0x1U << BSTIM_CR1_OPM_Pos)$BSTIM_CR1_OPM_CONTINUE (0x0U << BSTIM_CR1_OPM_Pos)%BSTIM_CR1_OPM_STOP (0x1U << BSTIM_CR1_OPM_Pos)'BSTIM_CR1_URS_Pos 2-BSTIM_CR1_URS_Msk (0x1U << BSTIM_CR1_URS_Pos).BSTIM_CR1_URS_ALL (0x0U << BSTIM_CR1_URS_Pos)/BSTIM_CR1_URS_COUNT (0x1U << BSTIM_CR1_URS_Pos)1BSTIM_CR1_UDIS_Pos 17BSTIM_CR1_UDIS_Msk (0x1U << BSTIM_CR1_UDIS_Pos);BSTIM_CR1_CEN_Pos 0?BSTIM_CR1_CEN_Msk (0x1U << BSTIM_CR1_CEN_Pos)DBSTIM_CR2_MMS_Pos 4KBSTIM_CR2_MMS_Msk (0x7U << BSTIM_CR2_MMS_Pos)MBSTIM_IER_UIE_Pos 0PBSTIM_IER_UIE_Msk (0x1U << BSTIM_IER_UIE_Pos)TBSTIM_ISR_UIF_Pos 0YBSTIM_ISR_UIF_Msk (0x1U << BSTIM_ISR_UIF_Pos)[BSTIM_EGR_UG_Pos 0]BSTIM_EGR_UG_Msk (0x1U << BSTIM_EGR_UG_Pos)_BSTIM_CNTR_CNT_Pos 0`BSTIM_CNTR_CNT_Msk (0xffffffffU << BSTIM_CNTR_CNT_Pos)bBSTIM_PSCR_PSC_Pos 0eBSTIM_PSCR_PSC_Msk (0xffffffffU << BSTIM_PSCR_PSC_Pos)gBSTIM_ARR_ARR_Pos 0iBSTIM_ARR_ARR_Msk (0xffffffffU << BSTIM_ARR_ARR_Pos)`V ..\Drivers\..\Core\Include\fm33a0xxev_bstim.hFM33A0XXEV.hÀ


..\Drivers\fm33a0xxev_bstim.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM[\]__FM33A0XXEV_COMP_H COMP_CR1_DFLEN_Pos 19COMP_CR1_DFLEN_Msk (0x1fU << COMP_CR1_DFLEN_Pos)COMP_CR1_DFLEN_X3 (0x2U << COMP_CR1_DFLEN_Pos)COMP_CR1_DFLEN_X32 (0x1fU << COMP_CR1_DFLEN_Pos)!COMP_CR1_WINMODE_Pos 18$COMP_CR1_WINMODE_Msk (0x1U << COMP_CR1_WINMODE_Pos)(COMP_CR1_POLAR_Pos 17+COMP_CR1_POLAR_Msk (0x1U << COMP_CR1_POLAR_Pos),COMP_CR1_POLAR_POS (0x0U << COMP_CR1_POLAR_Pos)-COMP_CR1_POLAR_NEG (0x1U << COMP_CR1_POLAR_Pos)/COMP_CR1_DFEN_Pos 162COMP_CR1_DFEN_Msk (0x1U << COMP_CR1_DFEN_Pos)6COMP_CR1_CMP1OR_Pos 97COMP_CR1_CMP1OR_Msk (0x1U << COMP_CR1_CMP1OR_Pos)9COMP_CR1_CMP1OF_Pos 8:COMP_CR1_CMP1OF_Msk (0x1U << COMP_CR1_CMP1OF_Pos)<COMP_CR1_V1NSEL_Pos 4ECOMP_CR1_V1NSEL_Msk (0x7U << COMP_CR1_V1NSEL_Pos)FCOMP_CR1_V1NSEL_COMP1_INN1 (0x0U << COMP_CR1_V1NSEL_Pos)GCOMP_CR1_V1NSEL_COMP1_INN2 (0x1U << COMP_CR1_V1NSEL_Pos)HCOMP_CR1_V1NSEL_VREF (0x2U << COMP_CR1_V1NSEL_Pos)ICOMP_CR1_V1NSEL_3_4_VREF (0x3U << COMP_CR1_V1NSEL_Pos)JCOMP_CR1_V1NSEL_1_2_VREF (0x4U << COMP_CR1_V1NSEL_Pos)KCOMP_CR1_V1NSEL_1_4_VREF (0x5U << COMP_CR1_V1NSEL_Pos)LCOMP_CR1_V1NSEL_1_8_VREF (0x6U << COMP_CR1_V1NSEL_Pos)NCOMP_CR1_V1PSEL_Pos 1SCOMP_CR1_V1PSEL_Msk (0x3U << COMP_CR1_V1PSEL_Pos)TCOMP_CR1_V1PSEL_COMP1_INP1 (0x0U << COMP_CR1_V1PSEL_Pos)UCOMP_CR1_V1PSEL_COMP1_INP2 (0x1U << COMP_CR1_V1PSEL_Pos)VCOMP_CR1_V1PSEL_COMP1_INP3 (0x2U << COMP_CR1_V1PSEL_Pos)WCOMP_CR1_V1PSEL_COMP1_INP4 (0x3U << COMP_CR1_V1PSEL_Pos)YCOMP_CR1_CMP1EN_Pos 0\COMP_CR1_CMP1EN_Msk (0x1U << COMP_CR1_CMP1EN_Pos)`COMP_CR2_DFLEN_Pos 19dCOMP_CR2_DFLEN_Msk (0x1fU << COMP_CR2_DFLEN_Pos)eCOMP_CR2_DFLEN_X3 (0x2U << COMP_CR2_DFLEN_Pos)fCOMP_CR2_DFLEN_X32 (0x1fU << COMP_CR2_DFLEN_Pos)hCOMP_CR2_WINMODE_Pos 18kCOMP_CR2_WINMODE_Msk (0x1U << COMP_CR2_WINMODE_Pos)oCOMP_CR2_POLAR_Pos 17rCOMP_CR2_POLAR_Msk (0x1U << COMP_CR2_POLAR_Pos)sCOMP_CR2_POLAR_POS (0x0U << COMP_CR2_POLAR_Pos)tCOMP_CR2_POLAR_NEG (0x1U << COMP_CR2_POLAR_Pos)vCOMP_CR2_DFEN_Pos 16yCOMP_CR2_DFEN_Msk (0x1U << COMP_CR2_DFEN_Pos)}COMP_CR2_CMP2OR_Pos 9~COMP_CR2_CMP2OR_Msk (0x1U << COMP_CR2_CMP2OR_Pos)€COMP_CR2_CMP2OF_Pos 8COMP_CR2_CMP2OF_Msk (0x1U << COMP_CR2_CMP2OF_Pos)ƒCOMP_CR2_V2NSEL_Pos 4ŒCOMP_CR2_V2NSEL_Msk (0x7U << COMP_CR2_V2NSEL_Pos)COMP_CR2_V2NSEL_COMP2_INN1 (0x0U << COMP_CR2_V2NSEL_Pos)ŽCOMP_CR2_V2NSEL_COMP2_INN2 (0x1U << COMP_CR2_V2NSEL_Pos)COMP_CR2_V2NSEL_VREF (0x2U << COMP_CR2_V2NSEL_Pos)COMP_CR2_V2NSEL_3_4_VREF (0x3U << COMP_CR2_V2NSEL_Pos)‘COMP_CR2_V2NSEL_1_2_VREF (0x4U << COMP_CR2_V2NSEL_Pos)’COMP_CR2_V2NSEL_1_4_VREF (0x5U << COMP_CR2_V2NSEL_Pos)“COMP_CR2_V2NSEL_1_8_VREF (0x6U << COMP_CR2_V2NSEL_Pos)”COMP_CR2_V2NSEL_REFIN (0x7U << COMP_CR2_V2NSEL_Pos)–COMP_CR2_V2PSEL_Pos 1žCOMP_CR2_V2PSEL_Msk (0x7U << COMP_CR2_V2PSEL_Pos)ŸCOMP_CR2_V2PSEL_COMP2_INP1 (0x0U << COMP_CR2_V2PSEL_Pos) COMP_CR2_V2PSEL_COMP2_INP2 (0x1U << COMP_CR2_V2PSEL_Pos)¡COMP_CR2_V2PSEL_COMP1_INP1 (0x2U << COMP_CR2_V2PSEL_Pos)¢COMP_CR2_V2PSEL_COMP1_INP2 (0x3U << COMP_CR2_V2PSEL_Pos)£COMP_CR2_V2PSEL_AVREF (0x4U << COMP_CR2_V2PSEL_Pos)¤COMP_CR2_V2PSEL_VDD15 (0x5U << COMP_CR2_V2PSEL_Pos)¦COMP_CR2_CMP2EN_Pos 0©COMP_CR2_CMP2EN_Msk (0x1U << COMP_CR2_CMP2EN_Pos)­COMP_ICR_OOW_IE_Pos 9®COMP_ICR_OOW_IE_Msk (0x1U << COMP_ICR_OOW_IE_Pos)°COMP_ICR_WIN_IE_Pos 8±COMP_ICR_WIN_IE_Msk (0x1U << COMP_ICR_WIN_IE_Pos)³COMP_ICR_BUFBYP_Pos 7¶COMP_ICR_BUFBYP_Msk (0x1U << COMP_ICR_BUFBYP_Pos)¸COMP_ICR_BUF_OFF_Pos 6»COMP_ICR_BUF_OFF_Msk (0x1U << COMP_ICR_BUF_OFF_Pos)½COMP_ICR_CMP2SEL_Pos 4ÁCOMP_ICR_CMP2SEL_Msk (0x3U << COMP_ICR_CMP2SEL_Pos)ÂCOMP_ICR_CMP2SEL_BOTH (0x0U << COMP_ICR_CMP2SEL_Pos)ÃCOMP_ICR_CMP2SEL_RISING (0x1U << COMP_ICR_CMP2SEL_Pos)ÄCOMP_ICR_CMP2SEL_FALLING (0x2U << COMP_ICR_CMP2SEL_Pos)ÆCOMP_ICR_CMP1SEL_Pos 2ÊCOMP_ICR_CMP1SEL_Msk (0x3U << COMP_ICR_CMP1SEL_Pos)ËCOMP_ICR_CMP1SEL_BOTH (0x0U << COMP_ICR_CMP1SEL_Pos)ÌCOMP_ICR_CMP1SEL_RISING (0x1U << COMP_ICR_CMP1SEL_Pos)ÍCOMP_ICR_CMP1SEL_FALLING (0x2U << COMP_ICR_CMP1SEL_Pos)ÏCOMP_ICR_CMP2IE_Pos 1ÐCOMP_ICR_CMP2IE_Msk (0x1U << COMP_ICR_CMP2IE_Pos)ÒCOMP_ICR_CMP1IE_Pos 0ÓCOMP_ICR_CMP1IE_Msk (0x1U << COMP_ICR_CMP1IE_Pos)ÕCOMP_ISR_OOW_IF_Pos 3ÖCOMP_ISR_OOW_IF_Msk (0x1U << COMP_ISR_OOW_IF_Pos)ØCOMP_ISR_WIN_IF_Pos 2ÙCOMP_ISR_WIN_IF_Msk (0x1U << COMP_ISR_WIN_IF_Pos)ÛCOMP_ISR_CMP2IF_Pos 1ÜCOMP_ISR_CMP2IF_Msk (0x1U << COMP_ISR_CMP2IF_Pos)ÞCOMP_ISR_CMP1IF_Pos 0ßCOMP_ISR_CMP1IF_Msk (0x1U << COMP_ISR_CMP1IF_Pos)áCOMP_PCR_HSCMPBUF_EN_Pos 2äCOMP_PCR_HSCMPBUF_EN_Msk (0x1U << COMP_PCR_HSCMPBUF_EN_Pos)åCOMP_PCR_HSCMPBUF_EN_SLOW (0x0U << COMP_PCR_HSCMPBUF_EN_Pos)æCOMP_PCR_HSCMPBUF_EN_FAST (0x1U << COMP_PCR_HSCMPBUF_EN_Pos)èCOMP_PCR_HSCMP2_EN_Pos 1ëCOMP_PCR_HSCMP2_EN_Msk (0x1U << COMP_PCR_HSCMP2_EN_Pos)ìCOMP_PCR_HSCMP2_EN_SLOW (0x0U << COMP_PCR_HSCMP2_EN_Pos)íCOMP_PCR_HSCMP2_EN_FAST (0x1U << COMP_PCR_HSCMP2_EN_Pos)ïCOMP_PCR_HSCMP1_EN_Pos 0òCOMP_PCR_HSCMP1_EN_Msk (0x1U << COMP_PCR_HSCMP1_EN_Pos)óCOMP_PCR_HSCMP1_EN_SLOW (0x0U << COMP_PCR_HSCMP1_EN_Pos)ôCOMP_PCR_HSCMP1_EN_FAST (0x1U << COMP_PCR_HSCMP1_EN_Pos)`U ..\Drivers\..\Core\Include\fm33a0xxev_comp.hFM33A0XXEV.h¼


..\Drivers\fm33a0xxev_comp.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM_`a__FM33A0XXEV_RMU_H RMU_PDRCR_PDRCFG_Pos 1RMU_PDRCR_PDRCFG_Msk (0x3U << RMU_PDRCR_PDRCFG_Pos)RMU_PDRCR_PDRCFG_1P5V (0x0U << RMU_PDRCR_PDRCFG_Pos)RMU_PDRCR_PDRCFG_1P25V (0x1U << RMU_PDRCR_PDRCFG_Pos)RMU_PDRCR_PDRCFG_1P35V (0x2U << RMU_PDRCR_PDRCFG_Pos)RMU_PDRCR_PDRCFG_1P4V (0x3U << RMU_PDRCR_PDRCFG_Pos) RMU_PDRCR_PDREN_Pos 0!RMU_PDRCR_PDREN_Msk (0x1U << RMU_PDRCR_PDREN_Pos)%RMU_BORCR_BOR_PDRCFG_Pos 1&RMU_BORCR_BOR_PDRCFG_Msk (0x3U << RMU_BORCR_BOR_PDRCFG_Pos)'RMU_BORCR_BOR_PDRCFG_1P7V (0x0U << RMU_BORCR_BOR_PDRCFG_Pos)(RMU_BORCR_BOR_PDRCFG_1P6V (0x1U << RMU_BORCR_BOR_PDRCFG_Pos))RMU_BORCR_BOR_PDRCFG_1P65V (0x2U << RMU_BORCR_BOR_PDRCFG_Pos)*RMU_BORCR_BOR_PDRCFG_1P75V (0x3U << RMU_BORCR_BOR_PDRCFG_Pos),RMU_BORCR_OFF_BOR_Pos 0-RMU_BORCR_OFF_BOR_Msk (0x1U << RMU_BORCR_OFF_BOR_Pos)1RMU_RSTCFGR_LKUPRST_EN_Pos 12RMU_RSTCFGR_LKUPRST_EN_Msk (0x1U << RMU_RSTCFGR_LKUPRST_EN_Pos)6RMU_SOFTRST_SOFTRST_Pos 07RMU_SOFTRST_SOFTRST_Msk (0xffffffffU << RMU_SOFTRST_SOFTRST_Pos)9RMU_RSR_NRSTN_FLAG_Pos 11:RMU_RSR_NRSTN_FLAG_Msk (0x1U << RMU_RSR_NRSTN_FLAG_Pos)<RMU_RSR_TESTN_FLAG_Pos 10=RMU_RSR_TESTN_FLAG_Msk (0x1U << RMU_RSR_TESTN_FLAG_Pos)?RMU_RSR_PORN_FLAG_Pos 9@RMU_RSR_PORN_FLAG_Msk (0x1U << RMU_RSR_PORN_FLAG_Pos)BRMU_RSR_PDRN_FLAG_Pos 8CRMU_RSR_PDRN_FLAG_Msk (0x1U << RMU_RSR_PDRN_FLAG_Pos)ERMU_RSR_SOFTN_FLAG_Pos 5FRMU_RSR_SOFTN_FLAG_Msk (0x1U << RMU_RSR_SOFTN_FLAG_Pos)HRMU_RSR_IWDTN_FLAG_Pos 4IRMU_RSR_IWDTN_FLAG_Msk (0x1U << RMU_RSR_IWDTN_FLAG_Pos)KRMU_RSR_WWDTN_FLAG_Pos 2LRMU_RSR_WWDTN_FLAG_Msk (0x1U << RMU_RSR_WWDTN_FLAG_Pos)NRMU_RSR_LKUPN_FLAG_Pos 1ORMU_RSR_LKUPN_FLAG_Msk (0x1U << RMU_RSR_LKUPN_FLAG_Pos)QRMU_RSR_NVICN_FLAG_Pos 0RRMU_RSR_NVICN_FLAG_Msk (0x1U << RMU_RSR_NVICN_FLAG_Pos)TRMU_PRSTEN_PERHRSTEN_Pos 0URMU_PRSTEN_PERHRSTEN_Msk (0xffffffffU << RMU_PRSTEN_PERHRSTEN_Pos)WRMU_AHBRST_HASHRST_Pos 2XRMU_AHBRST_HASHRST_Msk (0x1U << RMU_AHBRST_HASHRST_Pos)\RMU_AHBRST_PAERST_Pos 1]RMU_AHBRST_PAERST_Msk (0x1U << RMU_AHBRST_PAERST_Pos)aRMU_AHBRST_DMARST_Pos 0bRMU_AHBRST_DMARST_Msk (0x1U << RMU_AHBRST_DMARST_Pos)fRMU_APBRST1_UART5RST_Pos 31gRMU_APBRST1_UART5RST_Msk (0x1U << RMU_APBRST1_UART5RST_Pos)kRMU_APBRST1_UART4RST_Pos 30lRMU_APBRST1_UART4RST_Msk (0x1U << RMU_APBRST1_UART4RST_Pos)pRMU_APBRST1_UART3RST_Pos 29qRMU_APBRST1_UART3RST_Msk (0x1U << RMU_APBRST1_UART3RST_Pos)uRMU_APBRST1_UART2RST_Pos 28vRMU_APBRST1_UART2RST_Msk (0x1U << RMU_APBRST1_UART2RST_Pos)zRMU_APBRST1_TIMARST_Pos 23{RMU_APBRST1_TIMARST_Msk (0x1U << RMU_APBRST1_TIMARST_Pos)RMU_APBRST1_LCDRST_Pos 16€RMU_APBRST1_LCDRST_Msk (0x1U << RMU_APBRST1_LCDRST_Pos)„RMU_APBRST1_U7816RST_Pos 14…RMU_APBRST1_U7816RST_Msk (0x1U << RMU_APBRST1_U7816RST_Pos)‰RMU_APBRST1_SPI4RST_Pos 12ŠRMU_APBRST1_SPI4RST_Msk (0x1U << RMU_APBRST1_SPI4RST_Pos)ŽRMU_APBRST1_SPI3RST_Pos 11RMU_APBRST1_SPI3RST_Msk (0x1U << RMU_APBRST1_SPI3RST_Pos)“RMU_APBRST1_SPI2RST_Pos 10”RMU_APBRST1_SPI2RST_Msk (0x1U << RMU_APBRST1_SPI2RST_Pos)˜RMU_APBRST1_LPUART0RST_Pos 6™RMU_APBRST1_LPUART0RST_Msk (0x1U << RMU_APBRST1_LPUART0RST_Pos)RMU_APBRST1_I2C1RST_Pos 3žRMU_APBRST1_I2C1RST_Msk (0x1U << RMU_APBRST1_I2C1RST_Pos)¢RMU_APBRST1_LPTRST_Pos 0£RMU_APBRST1_LPTRST_Msk (0x1U << RMU_APBRST1_LPTRST_Pos)§RMU_APBRST2_UART1RST_Pos 31¨RMU_APBRST2_UART1RST_Msk (0x1U << RMU_APBRST2_UART1RST_Pos)¬RMU_APBRST2_UART0RST_Pos 30­RMU_APBRST2_UART0RST_Msk (0x1U << RMU_APBRST2_UART0RST_Pos)±RMU_APBRST2_UARTIRRST_Pos 29²RMU_APBRST2_UARTIRRST_Msk (0x1U << RMU_APBRST2_UARTIRRST_Pos)¶RMU_APBRST2_BSTRST_Pos 28·RMU_APBRST2_BSTRST_Msk (0x1U << RMU_APBRST2_BSTRST_Pos)»RMU_APBRST2_CICRST_Pos 24¼RMU_APBRST2_CICRST_Msk (0x1U << RMU_APBRST2_CICRST_Pos)ÀRMU_APBRST2_ADCRST_Pos 23ÁRMU_APBRST2_ADCRST_Msk (0x1U << RMU_APBRST2_ADCRST_Pos)ÅRMU_APBRST2_AESRST_Pos 18ÆRMU_APBRST2_AESRST_Msk (0x1U << RMU_APBRST2_AESRST_Pos)ÊRMU_APBRST2_CRCRST_Pos 17ËRMU_APBRST2_CRCRST_Msk (0x1U << RMU_APBRST2_CRCRST_Pos)ÏRMU_APBRST2_RNGRST_Pos 16ÐRMU_APBRST2_RNGRST_Msk (0x1U << RMU_APBRST2_RNGRST_Pos)ÔRMU_APBRST2_SPI1RST_Pos 9ÕRMU_APBRST2_SPI1RST_Msk (0x1U << RMU_APBRST2_SPI1RST_Pos)ÙRMU_APBRST2_SPI0RST_Pos 8ÚRMU_APBRST2_SPI0RST_Msk (0x1U << RMU_APBRST2_SPI0RST_Pos)ÞRMU_APBRST2_LPUART1RST_Pos 7ßRMU_APBRST2_LPUART1RST_Msk (0x1U << RMU_APBRST2_LPUART1RST_Pos)ãRMU_APBRST2_I2C0RST_Pos 4äRMU_APBRST2_I2C0RST_Msk (0x1U << RMU_APBRST2_I2C0RST_Pos)èRMU_APBRST2_SVDRST_Pos 1éRMU_APBRST2_SVDRST_Msk (0x1U << RMU_APBRST2_SVDRST_Pos)íRMU_APBRST2_COMPRST_Pos 0îRMU_APBRST2_COMPRST_Msk (0x1U << RMU_APBRST2_COMPRST_Pos)`T ..\Drivers\..\Core\Include\fm33a0xxev_rmu.hFM33A0XXEV.h¼


..\Drivers\fm33a0xxev_rmu.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMcde__FM33A0XXEV_CRC_H &CRC_DR_DR_Pos 0)CRC_DR_DR_Msk (0xffffffffU << CRC_DR_DR_Pos)+CRC_CR_OPWD_Pos 9.CRC_CR_OPWD_Msk (0x1U << CRC_CR_OPWD_Pos)/CRC_CR_OPWD_BYTE (0x0U << CRC_CR_OPWD_Pos)0CRC_CR_OPWD_WORD (0x1U << CRC_CR_OPWD_Pos)2CRC_CR_PARA_Pos 85CRC_CR_PARA_Msk (0x1U << CRC_CR_PARA_Pos)6CRC_CR_PARA_SERIAL (0x0U << CRC_CR_PARA_Pos)7CRC_CR_PARA_PARALLEL (0x1U << CRC_CR_PARA_Pos)9CRC_CR_RFLTIN_Pos 6ACRC_CR_RFLTIN_Msk (0x3U << CRC_CR_RFLTIN_Pos)BCRC_CR_RFLTIN_NONE (0x0U << CRC_CR_RFLTIN_Pos)CCRC_CR_RFLTIN_BYTE (0x1U << CRC_CR_RFLTIN_Pos)DCRC_CR_RFLTIN_HALFWORD (0x2U << CRC_CR_RFLTIN_Pos)ECRC_CR_RFLTIN_WORD (0x3U << CRC_CR_RFLTIN_Pos)GCRC_CR_RFLTO_Pos 5LCRC_CR_RFLTO_Msk (0x1U << CRC_CR_RFLTO_Pos)MCRC_CR_RFLTO_NON (0x0U << CRC_CR_RFLTO_Pos)NCRC_CR_RFLTO_BYTE (0x1U << CRC_CR_RFLTO_Pos)PCRC_CR_RES_Pos 4SCRC_CR_RES_Msk (0x1U << CRC_CR_RES_Pos)UCRC_CR_BUSY_Pos 3XCRC_CR_BUSY_Msk (0x1U << CRC_CR_BUSY_Pos)ZCRC_CR_XOR_Pos 2]CRC_CR_XOR_Msk (0x1U << CRC_CR_XOR_Pos)aCRC_CR_SEL_Pos 0fCRC_CR_SEL_Msk (0x3U << CRC_CR_SEL_Pos)gCRC_CR_SEL_CRC32 (0x0U << CRC_CR_SEL_Pos)hCRC_CR_SEL_CRC16 (0x1U << CRC_CR_SEL_Pos)iCRC_CR_SEL_CRC8 (0x2U << CRC_CR_SEL_Pos)jCRC_CR_SEL_CRC7 (0x3U << CRC_CR_SEL_Pos)lCRC_LFSR_LFSR_Pos 0nCRC_LFSR_LFSR_Msk (0xffffffffU << CRC_LFSR_LFSR_Pos)pCRC_XOR_XOR_Pos 0rCRC_XOR_XOR_Msk (0xffffffffU << CRC_XOR_XOR_Pos)tCRC_POLY_POLY_Pos 0uCRC_POLY_POLY_Msk (0xffffffffU << CRC_POLY_POLY_Pos)`T ..\Drivers\..\Core\Include\fm33a0xxev_crc.hFM33A0XXEV.h`


..\Drivers\fm33a0xxev_crc.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM*Ê$CRCSELf#OPWDf#PARAf#RFLTINf#RFLTOf#XOR#CRC_XORf#CRCPOLYf#LFSRf# PCRC_InitTypeDef½$ghi__FM33A0XXEV_LCD_H LCD_CR_SCSEL_Pos 20"LCD_CR_SCSEL_Msk (0x7U << LCD_CR_SCSEL_Pos)#LCD_CR_SCSEL_LSCLK_COM (0x0U << LCD_CR_SCSEL_Pos)$LCD_CR_SCSEL_LSCLK_8 (0x1U << LCD_CR_SCSEL_Pos)%LCD_CR_SCSEL_LSCLK_16 (0x2U << LCD_CR_SCSEL_Pos)&LCD_CR_SCSEL_LSCLK_32 (0x3U << LCD_CR_SCSEL_Pos)'LCD_CR_SCSEL_LSCLK_64 (0x4U << LCD_CR_SCSEL_Pos)(LCD_CR_SCSEL_LSCLK_128 (0x5U << LCD_CR_SCSEL_Pos))LCD_CR_SCSEL_LSCLK_256 (0x6U << LCD_CR_SCSEL_Pos)*LCD_CR_SCSEL_LSCLK_512 (0x7U << LCD_CR_SCSEL_Pos),LCD_CR_SC_CTRL_Pos 181LCD_CR_SC_CTRL_Msk (0x3U << LCD_CR_SC_CTRL_Pos)2LCD_CR_SC_CTRL_S0 (0x0U << LCD_CR_SC_CTRL_Pos)3LCD_CR_SC_CTRL_S1 (0x1U << LCD_CR_SC_CTRL_Pos)4LCD_CR_SC_CTRL_S2 (0x2U << LCD_CR_SC_CTRL_Pos)5LCD_CR_SC_CTRL_S3 (0x3U << LCD_CR_SC_CTRL_Pos)8LCD_CR_IC_CTRL_Pos 16=LCD_CR_IC_CTRL_Msk (0x3U << LCD_CR_IC_CTRL_Pos)>LCD_CR_IC_CTRL_L3 (0x0U << LCD_CR_IC_CTRL_Pos)?LCD_CR_IC_CTRL_L2 (0x1U << LCD_CR_IC_CTRL_Pos)@LCD_CR_IC_CTRL_L1 (0x2U << LCD_CR_IC_CTRL_Pos)ALCD_CR_IC_CTRL_L0 (0x3U << LCD_CR_IC_CTRL_Pos)CLCD_CR_ENMODE_Pos 15FLCD_CR_ENMODE_Msk (0x1U << LCD_CR_ENMODE_Pos)GLCD_CR_ENMODE_EXTERNALCAP (0x0U << LCD_CR_ENMODE_Pos)HLCD_CR_ENMODE_INNERRESISTER (0x1U << LCD_CR_ENMODE_Pos)JLCD_CR_FLICK_Pos 14MLCD_CR_FLICK_Msk (0x1U << LCD_CR_FLICK_Pos)QLCD_CR_BIAS_Pos 8RLCD_CR_BIAS_Msk (0xfU << LCD_CR_BIAS_Pos)TLCD_CR_BIASMD_Pos 5WLCD_CR_BIASMD_Msk (0x1U << LCD_CR_BIASMD_Pos)XLCD_CR_BIASMD_3BIAS (0x1U << LCD_CR_BIASMD_Pos)YLCD_CR_BIASMD_4BIAS (0x0U << LCD_CR_BIASMD_Pos)[LCD_CR_ANTIPOLAR_Pos 4^LCD_CR_ANTIPOLAR_Msk (0x1U << LCD_CR_ANTIPOLAR_Pos)_LCD_CR_ANTIPOLAR_GND (0x1U << LCD_CR_ANTIPOLAR_Pos)`LCD_CR_ANTIPOLAR_FLOAT (0x0U << LCD_CR_ANTIPOLAR_Pos)bLCD_CR_WFT_Pos 3eLCD_CR_WFT_Msk (0x1U << LCD_CR_WFT_Pos)fLCD_CR_WFT_BTYPE (0x1U << LCD_CR_WFT_Pos)gLCD_CR_WFT_ATYPE (0x0U << LCD_CR_WFT_Pos)iLCD_CR_LMUX_Pos 1mLCD_CR_LMUX_Msk (0x3U << LCD_CR_LMUX_Pos)nLCD_CR_LMUX_4COM (0x0U << LCD_CR_LMUX_Pos)oLCD_CR_LMUX_6COM (0x1U << LCD_CR_LMUX_Pos)pLCD_CR_LMUX_8COM (0x2U << LCD_CR_LMUX_Pos)sLCD_CR_EN_Pos 0vLCD_CR_EN_Msk (0x1U << LCD_CR_EN_Pos)zLCD_TEST_LCCTRL_Pos 7|LCD_TEST_LCCTRL_Msk (0x1U << LCD_TEST_LCCTRL_Pos)}LCD_TEST_LCCTRL_LOW (0x0U << LCD_TEST_LCCTRL_Pos)~LCD_TEST_LCCTRL_HIGH (0x1U << LCD_TEST_LCCTRL_Pos)€LCD_TEST_TESTEN_Pos 0ƒLCD_TEST_TESTEN_Msk (0x1U << LCD_TEST_TESTEN_Pos)‡LCD_FCR_DF_Pos 0ˆLCD_FCR_DF_Msk (0xffU << LCD_FCR_DF_Pos)ŠLCD_FLKT_TOFF_Pos 8ŒLCD_FLKT_TOFF_Msk (0xffU << LCD_FLKT_TOFF_Pos)ŽLCD_FLKT_TON_Pos 0LCD_FLKT_TON_Msk (0xffU << LCD_FLKT_TON_Pos)’LCD_IER_DONIE_Pos 1•LCD_IER_DONIE_Msk (0x1U << LCD_IER_DONIE_Pos)™LCD_IER_DOFFIE_Pos 0œLCD_IER_DOFFIE_Msk (0x1U << LCD_IER_DOFFIE_Pos) LCD_ISR_DONIF_Pos 1¢LCD_ISR_DONIF_Msk (0x1U << LCD_ISR_DONIF_Pos)¤LCD_ISR_DOFFIF_Pos 0¦LCD_ISR_DOFFIF_Msk (0x1U << LCD_ISR_DOFFIF_Pos)¨LCD_BSTCR_OSC_CFG_Pos 12©LCD_BSTCR_OSC_CFG_Msk (0xfU << LCD_BSTCR_OSC_CFG_Pos)«LCD_BSTCR_BUF_OFF_Pos 9¬LCD_BSTCR_BUF_OFF_Msk (0x1U << LCD_BSTCR_BUF_OFF_Pos)®LCD_BSTCR_BUFBYP_Pos 8¯LCD_BSTCR_BUFBYP_Msk (0x1U << LCD_BSTCR_BUFBYP_Pos)±LCD_BSTCR_VLCDPD_Pos 7²LCD_BSTCR_VLCDPD_Msk (0x1U << LCD_BSTCR_VLCDPD_Pos)´LCD_BSTCR_VLCDCFG_Pos 2µLCD_BSTCR_VLCDCFG_Msk (0x1fU << LCD_BSTCR_VLCDCFG_Pos)¶LCD_BSTCR_VLCDCFG_2_4V (0x0U << LCD_BSTCR_VLCDCFG_Pos)·LCD_BSTCR_VLCDCFG_2_6V (0x1U << LCD_BSTCR_VLCDCFG_Pos)¸LCD_BSTCR_VLCDCFG_2_8V (0x2U << LCD_BSTCR_VLCDCFG_Pos)¹LCD_BSTCR_VLCDCFG_3_0V (0x3U << LCD_BSTCR_VLCDCFG_Pos)ºLCD_BSTCR_VLCDCFG_3_2V (0x4U << LCD_BSTCR_VLCDCFG_Pos)»LCD_BSTCR_VLCDCFG_3_4V (0x5U << LCD_BSTCR_VLCDCFG_Pos)¼LCD_BSTCR_VLCDCFG_3_6V (0x6U << LCD_BSTCR_VLCDCFG_Pos)½LCD_BSTCR_VLCDCFG_3_8V (0x7U << LCD_BSTCR_VLCDCFG_Pos)¾LCD_BSTCR_VLCDCFG_4_0V (0x8U << LCD_BSTCR_VLCDCFG_Pos)¿LCD_BSTCR_VLCDCFG_4_2V (0x9U << LCD_BSTCR_VLCDCFG_Pos)ÀLCD_BSTCR_VLCDCFG_4_4V (0xaU << LCD_BSTCR_VLCDCFG_Pos)ÁLCD_BSTCR_VLCDCFG_4_6V (0xbU << LCD_BSTCR_VLCDCFG_Pos)ÂLCD_BSTCR_VLCDCFG_4_8V (0xcU << LCD_BSTCR_VLCDCFG_Pos)ÃLCD_BSTCR_VLCDCFG_5_0V (0xdU << LCD_BSTCR_VLCDCFG_Pos)ÄLCD_BSTCR_VLCDCFG_5_2V (0xeU << LCD_BSTCR_VLCDCFG_Pos)ÅLCD_BSTCR_VLCDCFG_5_4V (0xfU << LCD_BSTCR_VLCDCFG_Pos)ÇLCD_BSTCR_BOOST_TEN_Pos 1ÈLCD_BSTCR_BOOST_TEN_Msk (0x1U << LCD_BSTCR_BOOST_TEN_Pos)ÊLCD_BSTCR_BOOST_EN_Pos 0ËLCD_BSTCR_BOOST_EN_Msk (0x1U << LCD_BSTCR_BOOST_EN_Pos)ÍLCD_COM_EN_COMEN_Pos 0ÎLCD_COM_EN_COMEN_Msk (0xfU << LCD_COM_EN_COMEN_Pos)ÐLCD_SEG_EN0_SEGENx_Pos 0ÑLCD_SEG_EN0_SEGENx_Msk (0xffffffffU << LCD_SEG_EN0_SEGENx_Pos)ÓLCD_SEG_EN1_SEGENx_Pos 0ÔLCD_SEG_EN1_SEGENx_Msk (0xfffU << LCD_SEG_EN1_SEGENx_Pos)ÖLCD_COM_EN_COMEN3_Pos 3×LCD_COM_EN_COMEN3_Msk (0x1U << LCD_COM_EN_COMEN3_Pos)ÙLCD_COM_EN_COMEN2_Pos 2ÚLCD_COM_EN_COMEN2_Msk (0x1U << LCD_COM_EN_COMEN2_Pos)ÜLCD_COM_EN_COMEN1_Pos 1ÝLCD_COM_EN_COMEN1_Msk (0x1U << LCD_COM_EN_COMEN1_Pos)ßLCD_COM_EN_COMEN0_Pos 0àLCD_COM_EN_COMEN0_Msk (0x1U << LCD_COM_EN_COMEN0_Pos)âLCD_SEG_EN0_SEGEN31_Pos 31ãLCD_SEG_EN0_SEGEN31_Msk (0x1U << LCD_SEG_EN0_SEGEN31_Pos)åLCD_SEG_EN0_SEGEN30_Pos 30æLCD_SEG_EN0_SEGEN30_Msk (0x1U << LCD_SEG_EN0_SEGEN30_Pos)èLCD_SEG_EN0_SEGEN29_Pos 29éLCD_SEG_EN0_SEGEN29_Msk (0x1U << LCD_SEG_EN0_SEGEN29_Pos)ëLCD_SEG_EN0_SEGEN28_Pos 28ìLCD_SEG_EN0_SEGEN28_Msk (0x1U << LCD_SEG_EN0_SEGEN28_Pos)îLCD_SEG_EN0_SEGEN27_Pos 27ïLCD_SEG_EN0_SEGEN27_Msk (0x1U << LCD_SEG_EN0_SEGEN27_Pos)ñLCD_SEG_EN0_SEGEN26_Pos 26òLCD_SEG_EN0_SEGEN26_Msk (0x1U << LCD_SEG_EN0_SEGEN26_Pos)ôLCD_SEG_EN0_SEGEN25_Pos 25õLCD_SEG_EN0_SEGEN25_Msk (0x1U << LCD_SEG_EN0_SEGEN25_Pos)÷LCD_SEG_EN0_SEGEN24_Pos 24øLCD_SEG_EN0_SEGEN24_Msk (0x1U << LCD_SEG_EN0_SEGEN24_Pos)úLCD_SEG_EN0_SEGEN23_Pos 23ûLCD_SEG_EN0_SEGEN23_Msk (0x1U << LCD_SEG_EN0_SEGEN23_Pos)ýLCD_SEG_EN0_SEGEN22_Pos 22þLCD_SEG_EN0_SEGEN22_Msk (0x1U << LCD_SEG_EN0_SEGEN22_Pos)€LCD_SEG_EN0_SEGEN21_Pos 21LCD_SEG_EN0_SEGEN21_Msk (0x1U << LCD_SEG_EN0_SEGEN21_Pos)ƒLCD_SEG_EN0_SEGEN20_Pos 20„LCD_SEG_EN0_SEGEN20_Msk (0x1U << LCD_SEG_EN0_SEGEN20_Pos)†LCD_SEG_EN0_SEGEN19_Pos 19‡LCD_SEG_EN0_SEGEN19_Msk (0x1U << LCD_SEG_EN0_SEGEN19_Pos)‰LCD_SEG_EN0_SEGEN18_Pos 18ŠLCD_SEG_EN0_SEGEN18_Msk (0x1U << LCD_SEG_EN0_SEGEN18_Pos)ŒLCD_SEG_EN0_SEGEN17_Pos 17LCD_SEG_EN0_SEGEN17_Msk (0x1U << LCD_SEG_EN0_SEGEN17_Pos)LCD_SEG_EN0_SEGEN16_Pos 16LCD_SEG_EN0_SEGEN16_Msk (0x1U << LCD_SEG_EN0_SEGEN16_Pos)’LCD_SEG_EN0_SEGEN15_Pos 15“LCD_SEG_EN0_SEGEN15_Msk (0x1U << LCD_SEG_EN0_SEGEN15_Pos)•LCD_SEG_EN0_SEGEN14_Pos 14–LCD_SEG_EN0_SEGEN14_Msk (0x1U << LCD_SEG_EN0_SEGEN14_Pos)˜LCD_SEG_EN0_SEGEN13_Pos 13™LCD_SEG_EN0_SEGEN13_Msk (0x1U << LCD_SEG_EN0_SEGEN13_Pos)›LCD_SEG_EN0_SEGEN12_Pos 12œLCD_SEG_EN0_SEGEN12_Msk (0x1U << LCD_SEG_EN0_SEGEN12_Pos)žLCD_SEG_EN0_SEGEN11_Pos 11ŸLCD_SEG_EN0_SEGEN11_Msk (0x1U << LCD_SEG_EN0_SEGEN11_Pos)¡LCD_SEG_EN0_SEGEN10_Pos 10¢LCD_SEG_EN0_SEGEN10_Msk (0x1U << LCD_SEG_EN0_SEGEN10_Pos)¤LCD_SEG_EN0_SEGEN9_Pos 9¥LCD_SEG_EN0_SEGEN9_Msk (0x1U << LCD_SEG_EN0_SEGEN9_Pos)§LCD_SEG_EN0_SEGEN8_Pos 8¨LCD_SEG_EN0_SEGEN8_Msk (0x1U << LCD_SEG_EN0_SEGEN8_Pos)ªLCD_SEG_EN0_SEGEN7_Pos 7«LCD_SEG_EN0_SEGEN7_Msk (0x1U << LCD_SEG_EN0_SEGEN7_Pos)­LCD_SEG_EN0_SEGEN6_Pos 6®LCD_SEG_EN0_SEGEN6_Msk (0x1U << LCD_SEG_EN0_SEGEN6_Pos)°LCD_SEG_EN0_SEGEN5_Pos 5±LCD_SEG_EN0_SEGEN5_Msk (0x1U << LCD_SEG_EN0_SEGEN5_Pos)³LCD_SEG_EN0_SEGEN4_Pos 4´LCD_SEG_EN0_SEGEN4_Msk (0x1U << LCD_SEG_EN0_SEGEN4_Pos)¶LCD_SEG_EN0_SEGEN3_Pos 3·LCD_SEG_EN0_SEGEN3_Msk (0x1U << LCD_SEG_EN0_SEGEN3_Pos)¹LCD_SEG_EN0_SEGEN2_Pos 2ºLCD_SEG_EN0_SEGEN2_Msk (0x1U << LCD_SEG_EN0_SEGEN2_Pos)¼LCD_SEG_EN0_SEGEN1_Pos 1½LCD_SEG_EN0_SEGEN1_Msk (0x1U << LCD_SEG_EN0_SEGEN1_Pos)¿LCD_SEG_EN0_SEGEN0_Pos 0ÀLCD_SEG_EN0_SEGEN0_Msk (0x1U << LCD_SEG_EN0_SEGEN0_Pos)ÂLCD_SEG_EN1_SEGEN43_Pos 11ÃLCD_SEG_EN1_SEGEN43_Msk (0x1U << LCD_SEG_EN1_SEGEN43_Pos)ÅLCD_SEG_EN1_SEGEN42_Pos 10ÆLCD_SEG_EN1_SEGEN42_Msk (0x1U << LCD_SEG_EN1_SEGEN42_Pos)ÈLCD_SEG_EN1_SEGEN41_Pos 9ÉLCD_SEG_EN1_SEGEN41_Msk (0x1U << LCD_SEG_EN1_SEGEN41_Pos)ËLCD_SEG_EN1_SEGEN40_Pos 8ÌLCD_SEG_EN1_SEGEN40_Msk (0x1U << LCD_SEG_EN1_SEGEN40_Pos)ÎLCD_SEG_EN1_SEGEN39_Pos 7ÏLCD_SEG_EN1_SEGEN39_Msk (0x1U << LCD_SEG_EN1_SEGEN39_Pos)ÑLCD_SEG_EN1_SEGEN38_Pos 6ÒLCD_SEG_EN1_SEGEN38_Msk (0x1U << LCD_SEG_EN1_SEGEN38_Pos)ÔLCD_SEG_EN1_SEGEN37_Pos 5ÕLCD_SEG_EN1_SEGEN37_Msk (0x1U << LCD_SEG_EN1_SEGEN37_Pos)×LCD_SEG_EN1_SEGEN36_Pos 4ØLCD_SEG_EN1_SEGEN36_Msk (0x1U << LCD_SEG_EN1_SEGEN36_Pos)ÚLCD_SEG_EN1_SEGEN35_Pos 3ÛLCD_SEG_EN1_SEGEN35_Msk (0x1U << LCD_SEG_EN1_SEGEN35_Pos)ÝLCD_SEG_EN1_SEGEN34_Pos 2ÞLCD_SEG_EN1_SEGEN34_Msk (0x1U << LCD_SEG_EN1_SEGEN34_Pos)àLCD_SEG_EN1_SEGEN33_Pos 1áLCD_SEG_EN1_SEGEN33_Msk (0x1U << LCD_SEG_EN1_SEGEN33_Pos)ãLCD_SEG_EN1_SEGEN32_Pos 0äLCD_SEG_EN1_SEGEN32_Msk (0x1U << LCD_SEG_EN1_SEGEN32_Pos)æLCD_SEG_EN1_COMEN7_Pos 11çLCD_SEG_EN1_COMEN7_Msk (0x1U << LCD_SEG_EN1_COMEN7_Pos)éLCD_SEG_EN1_COMEN6_Pos 10êLCD_SEG_EN1_COMEN6_Msk (0x1U << LCD_SEG_EN1_COMEN6_Pos)ìLCD_SEG_EN1_COMEN5_Pos 9íLCD_SEG_EN1_COMEN5_Msk (0x1U << LCD_SEG_EN1_COMEN5_Pos)ïLCD_SEG_EN1_COMEN4_Pos 8ðLCD_SEG_EN1_COMEN4_Msk (0x1U << LCD_SEG_EN1_COMEN4_Pos)`T ..\Drivers\..\Core\Include\fm33a0xxev_lcd.hFM33A0XXEV.h¼


..\Drivers\fm33a0xxev_lcd.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMklm__FM33A0XXEV_DMA_H 2DMA_GCR_DMA_ADDRERR_EN_Pos 15DMA_GCR_DMA_ADDRERR_EN_Msk (0x1U << DMA_GCR_DMA_ADDRERR_EN_Pos)7DMA_GCR_DMAEN_Pos 0:DMA_GCR_DMAEN_Msk (0x1U << DMA_GCR_DMAEN_Pos)<DMA_CHxCR_CHxTSIZE_Pos 16=DMA_CHxCR_CHxTSIZE_Msk (0x1fffU << DMA_CHxCR_CHxTSIZE_Pos)?DMA_CHxCR_CHxPRI_Pos 12DDMA_CHxCR_CHxPRI_Msk (0x3U << DMA_CHxCR_CHxPRI_Pos)EDMA_CHxCR_CHxPRI_LOW (0x0U << DMA_CHxCR_CHxPRI_Pos)FDMA_CHxCR_CHxPRI_MEDIUM (0x1U << DMA_CHxCR_CHxPRI_Pos)GDMA_CHxCR_CHxPRI_HIGH (0x2U << DMA_CHxCR_CHxPRI_Pos)HDMA_CHxCR_CHxPRI_VERY_HIGH (0x3U << DMA_CHxCR_CHxPRI_Pos)JDMA_CHxCR_CHxINC_Pos 11MDMA_CHxCR_CHxINC_Msk (0x1U << DMA_CHxCR_CHxINC_Pos)NDMA_CHxCR_CHxINC_INCREASE (0x1U << DMA_CHxCR_CHxINC_Pos)ODMA_CHxCR_CHxINC_DECREASE (0x0U << DMA_CHxCR_CHxINC_Pos)QDMA_CHxCR_CHxSSEL_Pos 8SDMA_CHxCR_CHxSSEL_Msk (0x7U << DMA_CHxCR_CHxSSEL_Pos)UDMA_CHxCR_CH0SSEL_ADC (0x0U << DMA_CHxCR_CHxSSEL_Pos)VDMA_CHxCR_CH0SSEL_SPI3_RX (0x1U << DMA_CHxCR_CHxSSEL_Pos)WDMA_CHxCR_CH0SSEL_LPUART0_RX (0x2U << DMA_CHxCR_CHxSSEL_Pos)XDMA_CHxCR_CH0SSEL_LPUART1_RX (0x3U << DMA_CHxCR_CHxSSEL_Pos)YDMA_CHxCR_CH0SSEL_UART2_RX (0x4U << DMA_CHxCR_CHxSSEL_Pos)ZDMA_CHxCR_CH0SSEL_UART4_RX (0x5U << DMA_CHxCR_CHxSSEL_Pos)[DMA_CHxCR_CH0SSEL_AES_IN (0x6U << DMA_CHxCR_CHxSSEL_Pos)\DMA_CHxCR_CH0SSEL_QSPI (0x7U << DMA_CHxCR_CHxSSEL_Pos)^DMA_CHxCR_CH1SSEL_ADC (0x0U << DMA_CHxCR_CHxSSEL_Pos)_DMA_CHxCR_CH1SSEL_SPI0_RX (0x1U << DMA_CHxCR_CHxSSEL_Pos)`DMA_CHxCR_CH1SSEL_SPI2_RX (0x2U << DMA_CHxCR_CHxSSEL_Pos)aDMA_CHxCR_CH1SSEL_SPI3_TX (0x3U << DMA_CHxCR_CHxSSEL_Pos)bDMA_CHxCR_CH1SSEL_UART0_RX (0x4U << DMA_CHxCR_CHxSSEL_Pos)cDMA_CHxCR_CH1SSEL_UART2_TX (0x5U << DMA_CHxCR_CHxSSEL_Pos)dDMA_CHxCR_CH1SSEL_UART3_RX (0x6U << DMA_CHxCR_CHxSSEL_Pos)eDMA_CHxCR_CH1SSEL_U7816_RX (0x7U << DMA_CHxCR_CHxSSEL_Pos)gDMA_CHxCR_CH2SSEL_SPI0_TX (0x0U << DMA_CHxCR_CHxSSEL_Pos)hDMA_CHxCR_CH2SSEL_SPI2_TX (0x1U << DMA_CHxCR_CHxSSEL_Pos)iDMA_CHxCR_CH2SSEL_SPI4_RX (0x2U << DMA_CHxCR_CHxSSEL_Pos)jDMA_CHxCR_CH2SSEL_UART0_TX (0x3U << DMA_CHxCR_CHxSSEL_Pos)kDMA_CHxCR_CH2SSEL_UART3_TX (0x4U << DMA_CHxCR_CHxSSEL_Pos)lDMA_CHxCR_CH2SSEL_UART5_RX (0x5U << DMA_CHxCR_CHxSSEL_Pos)mDMA_CHxCR_CH2SSEL_U7816_TX (0x6U << DMA_CHxCR_CHxSSEL_Pos)nDMA_CHxCR_CH2SSEL_AES_OUT (0x7U << DMA_CHxCR_CHxSSEL_Pos)pDMA_CHxCR_CH3SSEL_SPI1_RX (0x0U << DMA_CHxCR_CHxSSEL_Pos)qDMA_CHxCR_CH3SSEL_SPI4_TX (0x1U << DMA_CHxCR_CHxSSEL_Pos)rDMA_CHxCR_CH3SSEL_LPUART0_RX (0x2U << DMA_CHxCR_CHxSSEL_Pos)sDMA_CHxCR_CH3SSEL_UART1_RX (0x3U << DMA_CHxCR_CHxSSEL_Pos)tDMA_CHxCR_CH3SSEL_UART4_RX (0x4U << DMA_CHxCR_CHxSSEL_Pos)uDMA_CHxCR_CH3SSEL_UART5_TX (0x5U << DMA_CHxCR_CHxSSEL_Pos)vDMA_CHxCR_CH3SSEL_I2C0_TX (0x6U << DMA_CHxCR_CHxSSEL_Pos)wDMA_CHxCR_CH3SSEL_AES_IN (0x7U << DMA_CHxCR_CHxSSEL_Pos)yDMA_CHxCR_CH4SSEL_SPI1_TX (0x0U << DMA_CHxCR_CHxSSEL_Pos)zDMA_CHxCR_CH4SSEL_SPI3_RX (0x1U << DMA_CHxCR_CHxSSEL_Pos){DMA_CHxCR_CH4SSEL_LPUART0_TX (0x2U << DMA_CHxCR_CHxSSEL_Pos)|DMA_CHxCR_CH4SSEL_UART1_TX (0x3U << DMA_CHxCR_CHxSSEL_Pos)}DMA_CHxCR_CH4SSEL_UART2_RX (0x4U << DMA_CHxCR_CHxSSEL_Pos)~DMA_CHxCR_CH4SSEL_UART4_TX (0x5U << DMA_CHxCR_CHxSSEL_Pos)DMA_CHxCR_CH4SSEL_I2C0_RX (0x6U << DMA_CHxCR_CHxSSEL_Pos)€DMA_CHxCR_CH4SSEL_AES_OUT (0x7U << DMA_CHxCR_CHxSSEL_Pos)‚DMA_CHxCR_CH5SSEL_SPI0_RX (0x0U << DMA_CHxCR_CHxSSEL_Pos)ƒDMA_CHxCR_CH5SSEL_SPI2_RX (0x1U << DMA_CHxCR_CHxSSEL_Pos)„DMA_CHxCR_CH5SSEL_LPUART1_RX (0x2U << DMA_CHxCR_CHxSSEL_Pos)…DMA_CHxCR_CH5SSEL_UART1_RX (0x3U << DMA_CHxCR_CHxSSEL_Pos)†DMA_CHxCR_CH5SSEL_UART2_TX (0x4U << DMA_CHxCR_CHxSSEL_Pos)‡DMA_CHxCR_CH5SSEL_UART3_RX (0x5U << DMA_CHxCR_CHxSSEL_Pos)ˆDMA_CHxCR_CH5SSEL_UART5_RX (0x6U << DMA_CHxCR_CHxSSEL_Pos)‰DMA_CHxCR_CH5SSEL_I2C1_TX (0x7U << DMA_CHxCR_CHxSSEL_Pos)‹DMA_CHxCR_CH6SSEL_SPI0_TX (0x0U << DMA_CHxCR_CHxSSEL_Pos)ŒDMA_CHxCR_CH6SSEL_SPI2_TX (0x1U << DMA_CHxCR_CHxSSEL_Pos)DMA_CHxCR_CH6SSEL_LPUART1_TX (0x2U << DMA_CHxCR_CHxSSEL_Pos)ŽDMA_CHxCR_CH6SSEL_UART1_TX (0x3U << DMA_CHxCR_CHxSSEL_Pos)DMA_CHxCR_CH6SSEL_UART3_TX (0x4U << DMA_CHxCR_CHxSSEL_Pos)DMA_CHxCR_CH6SSEL_UART5_TX (0x5U << DMA_CHxCR_CHxSSEL_Pos)‘DMA_CHxCR_CH6SSEL_I2C1_RX (0x6U << DMA_CHxCR_CHxSSEL_Pos)’DMA_CHxCR_CH6SSEL_CRC (0x7U << DMA_CHxCR_CHxSSEL_Pos)”DMA_CHxCR_CH7SSEL_ADC (0x0U << DMA_CHxCR_CHxSSEL_Pos)•DMA_CHxCR_CH7SSEL_SPI1_RX (0x1U << DMA_CHxCR_CHxSSEL_Pos)–DMA_CHxCR_CH7SSEL_SPI3_RX (0x2U << DMA_CHxCR_CHxSSEL_Pos)—DMA_CHxCR_CH7SSEL_LPUART0_RX (0x3U << DMA_CHxCR_CHxSSEL_Pos)˜DMA_CHxCR_CH7SSEL_UART0_RX (0x4U << DMA_CHxCR_CHxSSEL_Pos)™DMA_CHxCR_CH7SSEL_UART2_RX (0x5U << DMA_CHxCR_CHxSSEL_Pos)šDMA_CHxCR_CH7SSEL_UART4_RX (0x6U << DMA_CHxCR_CHxSSEL_Pos)›DMA_CHxCR_CH7SSEL_QSPI (0x7U << DMA_CHxCR_CHxSSEL_Pos)DMA_CHxCR_CH8SSEL_ADC (0x0U << DMA_CHxCR_CHxSSEL_Pos)žDMA_CHxCR_CH8SSEL_SPI1_TX (0x1U << DMA_CHxCR_CHxSSEL_Pos)ŸDMA_CHxCR_CH8SSEL_SPI2_RX (0x2U << DMA_CHxCR_CHxSSEL_Pos) DMA_CHxCR_CH8SSEL_SPI3_TX (0x3U << DMA_CHxCR_CHxSSEL_Pos)¡DMA_CHxCR_CH8SSEL_LPUART0_TX (0x4U << DMA_CHxCR_CHxSSEL_Pos)¢DMA_CHxCR_CH8SSEL_UART0_TX (0x5U << DMA_CHxCR_CHxSSEL_Pos)£DMA_CHxCR_CH8SSEL_UART2_TX (0x6U << DMA_CHxCR_CHxSSEL_Pos)¤DMA_CHxCR_CH8SSEL_UART4_TX (0x7U << DMA_CHxCR_CHxSSEL_Pos)¦DMA_CHxCR_CH9SSEL_SPI0_RX (0x0U << DMA_CHxCR_CHxSSEL_Pos)§DMA_CHxCR_CH9SSEL_SPI2_TX (0x1U << DMA_CHxCR_CHxSSEL_Pos)¨DMA_CHxCR_CH9SSEL_SPI4_RX (0x2U << DMA_CHxCR_CHxSSEL_Pos)©DMA_CHxCR_CH9SSEL_LPUART1_RX (0x3U << DMA_CHxCR_CHxSSEL_Pos)ªDMA_CHxCR_CH9SSEL_UART1_RX (0x4U << DMA_CHxCR_CHxSSEL_Pos)«DMA_CHxCR_CH9SSEL_UART3_RX (0x5U << DMA_CHxCR_CHxSSEL_Pos)¬DMA_CHxCR_CH9SSEL_UART5_RX (0x6U << DMA_CHxCR_CHxSSEL_Pos)­DMA_CHxCR_CH9SSEL_I2C0_TX (0x7U << DMA_CHxCR_CHxSSEL_Pos)¯DMA_CHxCR_CH10SSEL_SPI0_TX (0x0U << DMA_CHxCR_CHxSSEL_Pos)°DMA_CHxCR_CH10SSEL_SPI4_TX (0x1U << DMA_CHxCR_CHxSSEL_Pos)±DMA_CHxCR_CH10SSEL_LPUART1_TX (0x2U << DMA_CHxCR_CHxSSEL_Pos)²DMA_CHxCR_CH10SSEL_UART1_TX (0x3U << DMA_CHxCR_CHxSSEL_Pos)³DMA_CHxCR_CH10SSEL_UART3_TX (0x4U << DMA_CHxCR_CHxSSEL_Pos)´DMA_CHxCR_CH10SSEL_UART5_TX (0x5U << DMA_CHxCR_CHxSSEL_Pos)µDMA_CHxCR_CH10SSEL_I2C0_RX (0x6U << DMA_CHxCR_CHxSSEL_Pos)¶DMA_CHxCR_CH10SSEL_CRC (0x7U << DMA_CHxCR_CHxSSEL_Pos)¸DMA_CHxCR_CIRC_UPD_Pos 7¼DMA_CHxCR_CIRC_UPD_Msk (0x1U << DMA_CHxCR_CIRC_UPD_Pos)ÁDMA_CHxCR_DIR_Pos 6ÄDMA_CHxCR_DIR_Msk (0x1U << DMA_CHxCR_DIR_Pos)ÅDMA_CHxCR_DIR_TO_RAM (0x0U << DMA_CHxCR_DIR_Pos)ÆDMA_CHxCR_DIR_TO_PER (0x1U << DMA_CHxCR_DIR_Pos)ÈDMA_CHxCR_BDW_Pos 4ÍDMA_CHxCR_BDW_Msk (0x3U << DMA_CHxCR_BDW_Pos)ÎDMA_CHxCR_BDW_8BITS (0x0U << DMA_CHxCR_BDW_Pos)ÏDMA_CHxCR_BDW_16BITS (0x1U << DMA_CHxCR_BDW_Pos)ÐDMA_CHxCR_BDW_32BITS (0x2U << DMA_CHxCR_BDW_Pos)ÒDMA_CHxCR_CIRC_Pos 3ÕDMA_CHxCR_CIRC_Msk (0x1U << DMA_CHxCR_CIRC_Pos)ÙDMA_CHxCR_CHxFTIE_Pos 2ÜDMA_CHxCR_CHxFTIE_Msk (0x1U << DMA_CHxCR_CHxFTIE_Pos)àDMA_CHxCR_CHxHTIE_Pos 1ãDMA_CHxCR_CHxHTIE_Msk (0x1U << DMA_CHxCR_CHxHTIE_Pos)çDMA_CHxCR_ChxEN_Pos 0êDMA_CHxCR_ChxEN_Msk (0x1U << DMA_CHxCR_ChxEN_Pos)îDMA_CHxMAR_CHxMEMAD_Pos 0ôDMA_CHxMAR_CHxMEMAD_Msk (0xffffffffU << DMA_CHxMAR_CHxMEMAD_Pos)öDMA_CH11CR_CH11TSIZE_Pos 16÷DMA_CH11CR_CH11TSIZE_Msk (0x1fffU << DMA_CH11CR_CH11TSIZE_Pos)ùDMA_CH11CR_CH11PRI_Pos 12þDMA_CH11CR_CH11PRI_Msk (0x3U << DMA_CH11CR_CH11PRI_Pos)ÿDMA_CH11CR_CH11PRI_LOW (0x0U << DMA_CH11CR_CH11PRI_Pos)€DMA_CH11CR_CH11PRI_MEDIUM (0x1U << DMA_CH11CR_CH11PRI_Pos)DMA_CH11CR_CH11PRI_HIGH (0x2U << DMA_CH11CR_CH11PRI_Pos)‚DMA_CH11CR_CH11PRI_VERY_HIGH (0x3U << DMA_CH11CR_CH11PRI_Pos)„DMA_CH11CR_CH11DIR_Pos 10‡DMA_CH11CR_CH11DIR_Msk (0x1U << DMA_CH11CR_CH11DIR_Pos)ˆDMA_CH11CR_CH11DIR_TO_RAM (0x1U << DMA_CH11CR_CH11DIR_Pos)‰DMA_CH11CR_CH11DIR_TO_FLASH (0x0U << DMA_CH11CR_CH11DIR_Pos)‹DMA_CH11CR_CH11RI_Pos 9ŽDMA_CH11CR_CH11RI_Msk (0x1U << DMA_CH11CR_CH11RI_Pos)DMA_CH11CR_CH11RI_INCREASE (0x1U << DMA_CH11CR_CH11RI_Pos)DMA_CH11CR_CH11RI_DECREASE (0x0U << DMA_CH11CR_CH11RI_Pos)’DMA_CH11CR_CH11FI_Pos 8•DMA_CH11CR_CH11FI_Msk (0x1U << DMA_CH11CR_CH11FI_Pos)–DMA_CH11CR_CH11FI_INCREASE (0x1U << DMA_CH11CR_CH11FI_Pos)—DMA_CH11CR_CH11FI_DECREASE (0x0U << DMA_CH11CR_CH11FI_Pos)™DMA_CH11CR_CH11FTIE_Pos 2œDMA_CH11CR_CH11FTIE_Msk (0x1U << DMA_CH11CR_CH11FTIE_Pos) DMA_CH11CR_CH11HTIE_Pos 1£DMA_CH11CR_CH11HTIE_Msk (0x1U << DMA_CH11CR_CH11HTIE_Pos)§DMA_CH11CR_CH11EN_Pos 0ªDMA_CH11CR_CH11EN_Msk (0x1U << DMA_CH11CR_CH11EN_Pos)®DMA_CH11FAR_CH11FLSAD_Pos 0±DMA_CH11FAR_CH11FLSAD_Msk (0x7fffU << DMA_CH11FAR_CH11FLSAD_Pos)³DMA_CH11RAR_CH7RAMAD_Pos 0µDMA_CH11RAR_CH7RAMAD_Msk (0x7fffU << DMA_CH11RAR_CH7RAMAD_Pos)·DMA_ISR_DMA_ADDRERR_Pos 28¸DMA_ISR_DMA_ADDRERR_Msk (0x1U << DMA_ISR_DMA_ADDRERR_Pos)ºDMA_ISR_DMACHFT_Pos 16½DMA_ISR_DMACHFT_Msk (0xfffU << DMA_ISR_DMACHFT_Pos)¿DMA_ISR_DMACHHT_Pos 0ÀDMA_ISR_DMACHHT_Msk (0xfffU << DMA_ISR_DMACHHT_Pos)ÂDMA_CHxCSR_CHxTSIZE_SDW_Pos 16ÃDMA_CHxCSR_CHxTSIZE_SDW_Msk (0x1fffU << DMA_CHxCSR_CHxTSIZE_SDW_Pos)ÅDMA_CHxCSR_CHxINC_SDW_Pos 11ÆDMA_CHxCSR_CHxINC_SDW_Msk (0x1U << DMA_CHxCSR_CHxINC_SDW_Pos)ÈDMA_CHxMASR_CHxMAD_SDW_Pos 0ÊDMA_CHxMASR_CHxMAD_SDW_Msk (0xffffffffU << DMA_CHxMASR_CHxMAD_SDW_Pos)`T ..\Drivers\..\Core\Include\fm33a0xxev_dma.hFM33A0XXEV.hl


..\Drivers\fm33a0xxev_dma.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMÈDMA_CH0DMA_CH1DMA_CH2DMA_CH3DMA_CH4DMA_CH5DMA_CH6DMA_CH7DMA_CH8DMA_CH9    DMA_CH10


DMA_CH11PDMA_CH_Type½*Õ0CHxH#CHxTSIZEf#CHxPRIf#CHxINCf#CHxSSELf#CHxDIRf#CHxBDWf#CHxCICR#CHxFTIE#CHxHTIE#CHxEN#CHxRAMADf# CH11RIf#$CH11FIf#(CH11FLSADf#,PDMA_InitTypeDef[0opq__FM33A0XXEV_GPIO_H cIS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))lIS_GPIO_INTERRUPT_TRIGER_EDGE(EDGE) (((EDGE) == EXTI_RISING) || ((EDGE) == EXTI_FALLING)|| ((EDGE) == EXTI_BOTH)|| ((EDGE) == EXTIDISABLE))}IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || ((PERIPH) == GPIOB) || ((PERIPH) == GPIOC) || ((PERIPH) == GPIOD) || ((PERIPH) == GPIOE) || ((PERIPH) == GPIOF) || ((PERIPH) == GPIOG))…IS_GPIO_HD_PERIPH(PERIPH) ((PERIPH) == GPIOH)‰GPIO_Pin_0 ((uint32_t)0x00000001)ŠGPIO_Pin_1 ((uint32_t)0x00000002)‹GPIO_Pin_2 ((uint32_t)0x00000004)ŒGPIO_Pin_3 ((uint32_t)0x00000008)GPIO_Pin_4 ((uint32_t)0x00000010)ŽGPIO_Pin_5 ((uint32_t)0x00000020)GPIO_Pin_6 ((uint32_t)0x00000040)GPIO_Pin_7 ((uint32_t)0x00000080)‘GPIO_Pin_8 ((uint32_t)0x00000100)’GPIO_Pin_9 ((uint32_t)0x00000200)“GPIO_Pin_10 ((uint32_t)0x00000400)”GPIO_Pin_11 ((uint32_t)0x00000800)•GPIO_Pin_12 ((uint32_t)0x00001000)–GPIO_Pin_13 ((uint32_t)0x00002000)—GPIO_Pin_14 ((uint32_t)0x00004000)˜GPIO_Pin_15 ((uint32_t)0x00008000)™GPIO_Pin_All ((uint16_t)0xFFFF)›IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00))œIS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || ((PIN) == GPIO_Pin_1) || ((PIN) == GPIO_Pin_2) || ((PIN) == GPIO_Pin_3) || ((PIN) == GPIO_Pin_4) || ((PIN) == GPIO_Pin_5) || ((PIN) == GPIO_Pin_6) || ((PIN) == GPIO_Pin_7) || ((PIN) == GPIO_Pin_8) || ((PIN) == GPIO_Pin_9) || ((PIN) == GPIO_Pin_10) || ((PIN) == GPIO_Pin_11) || ((PIN) == GPIO_Pin_12) || ((PIN) == GPIO_Pin_13) || ((PIN) == GPIO_Pin_14) || ((PIN) == GPIO_Pin_15))¯IS_GET_GPIOH_PIN(PIN) (((PIN) == GPIO_Pin_0) || ((PIN) == GPIO_Pin_1) || ((PIN) == GPIO_Pin_2) || ((PIN) == GPIO_Pin_3))·PINWKEN_PD6 7¸PINWKEN_PE9 6¹PINWKEN_PE2 5ºPINWKEN_PA13 4»PINWKEN_PG7 3¼PINWKEN_PC13 2½PINWKEN_PB0 1¾PINWKEN_PF5 0ÁGPIOx_INEN_INEN_Pos 0ÂGPIOx_INEN_INEN_Msk (0xffffU << GPIOx_INEN_INEN_Pos)ÈGPIOx_PUEN_PUEN_Pos 0ÉGPIOx_PUEN_PUEN_Msk (0xffffU << GPIOx_PUEN_PUEN_Pos)ÏGPIOx_ODEN_ODEN_Pos 0ÐGPIOx_ODEN_ODEN_Msk (0xffffU << GPIOx_ODEN_ODEN_Pos)ÖGPIOx_FCR_Px15FCR_Pos 30×GPIOx_FCR_Px15FCR_Msk (0x03U << GPIOx_FCR_Px15FCR_Pos)ÝGPIOx_FCR_Px14FCR_Pos 28ÞGPIOx_FCR_Px14FCR_Msk (0x03U << GPIOx_FCR_Px14FCR_Pos)äGPIOx_FCR_Px13FCR_Pos 26åGPIOx_FCR_Px13FCR_Msk (0x03U << GPIOx_FCR_Px13FCR_Pos)ëGPIOx_FCR_Px12FCR_Pos 24ìGPIOx_FCR_Px12FCR_Msk (0x03U << GPIOx_FCR_Px12FCR_Pos)òGPIOx_FCR_Px11FCR_Pos 22óGPIOx_FCR_Px11FCR_Msk (0x03U << GPIOx_FCR_Px11FCR_Pos)ùGPIOx_FCR_Px10FCR_Pos 20úGPIOx_FCR_Px10FCR_Msk (0x03U << GPIOx_FCR_Px10FCR_Pos)€GPIOx_FCR_Px9FCR_Pos 18GPIOx_FCR_Px9FCR_Msk (0x03U << GPIOx_FCR_Px9FCR_Pos)‡GPIOx_FCR_Px8FCR_Pos 16ˆGPIOx_FCR_Px8FCR_Msk (0x03U << GPIOx_FCR_Px8FCR_Pos)ŽGPIOx_FCR_Px7FCR_Pos 14GPIOx_FCR_Px7FCR_Msk (0x03U << GPIOx_FCR_Px7FCR_Pos)•GPIOx_FCR_Px6FCR_Pos 12–GPIOx_FCR_Px6FCR_Msk (0x03U << GPIOx_FCR_Px6FCR_Pos)œGPIOx_FCR_Px5FCR_Pos 10GPIOx_FCR_Px5FCR_Msk (0x03U << GPIOx_FCR_Px5FCR_Pos)£GPIOx_FCR_Px4FCR_Pos 8¤GPIOx_FCR_Px4FCR_Msk (0x03U << GPIOx_FCR_Px4FCR_Pos)ªGPIOx_FCR_Px3FCR_Pos 6«GPIOx_FCR_Px3FCR_Msk (0x03U << GPIOx_FCR_Px3FCR_Pos)±GPIOx_FCR_Px2FCR_Pos 4²GPIOx_FCR_Px2FCR_Msk (0x03U << GPIOx_FCR_Px2FCR_Pos)¸GPIOx_FCR_Px1FCR_Pos 2¹GPIOx_FCR_Px1FCR_Msk (0x03U << GPIOx_FCR_Px1FCR_Pos)¿GPIOx_FCR_Px0FCR_Pos 0ÀGPIOx_FCR_Px0FCR_Msk (0x03U << GPIOx_FCR_Px0FCR_Pos)ÈGPIOx_DO_DO_Pos 0ÉGPIOx_DO_DO_Msk (0xffffU << GPIOx_DO_DO_Pos)ÍGPIOx_DSET_DSET_Pos 0ÎGPIOx_DSET_DSET_Msk (0xffffU << GPIOx_DSET_DSET_Pos)ÔGPIOx_DRST_DRESET_Pos 0ÕGPIOx_DRST_DRESET_Msk (0xffffU << GPIOx_DRST_DRESET_Pos)ÛGPIOx_DIN_DIN_Pos 0ÜGPIOx_DIN_DIN_Msk (0xffffU << GPIOx_DIN_DIN_Pos)âGPIOx_DFS_DFS_Pos 0ãGPIOx_DFS_DFS_Msk (0xffffU << GPIOx_DFS_DFS_Pos)éGPIOx_ANEN_ANEN_Pos 0êGPIOx_ANEN_ANEN_Msk (0xffffU << GPIOx_ANEN_ANEN_Pos)öGPIO_FOUTSEL_FOUT1SEL_Pos 8÷GPIO_FOUTSEL_FOUT1SEL_Msk (0x1fU << GPIO_FOUTSEL_FOUT1SEL_Pos)øGPIO_FOUTSEL_FOUT1SEL_XTLF (0x0U << GPIO_FOUTSEL_FOUT1SEL_Pos)ùGPIO_FOUTSEL_FOUT1SEL_RCLP (0x1U << GPIO_FOUTSEL_FOUT1SEL_Pos)úGPIO_FOUTSEL_FOUT1SEL_RCHFD64 (0x2U << GPIO_FOUTSEL_FOUT1SEL_Pos)ûGPIO_FOUTSEL_FOUT1SEL_LSCLK (0x3U << GPIO_FOUTSEL_FOUT1SEL_Pos)üGPIO_FOUTSEL_FOUT1SEL_AHBCLKD64 (0x4U << GPIO_FOUTSEL_FOUT1SEL_Pos)ýGPIO_FOUTSEL_FOUT1SEL_RTC_TM (0x5U << GPIO_FOUTSEL_FOUT1SEL_Pos)þGPIO_FOUTSEL_FOUT1SEL_PLLHD64 (0x6U << GPIO_FOUTSEL_FOUT1SEL_Pos)ÿGPIO_FOUTSEL_FOUT1SEL_RTCCLK64Hz (0x7U << GPIO_FOUTSEL_FOUT1SEL_Pos)€GPIO_FOUTSEL_FOUT1SEL_APBCLKD64 (0x8U << GPIO_FOUTSEL_FOUT1SEL_Pos)GPIO_FOUTSEL_FOUT1SEL_PLL_L (0x9U << GPIO_FOUTSEL_FOUT1SEL_Pos)‚GPIO_FOUTSEL_FOUT1SEL_RCMF (0xAU << GPIO_FOUTSEL_FOUT1SEL_Pos)ƒGPIO_FOUTSEL_FOUT1SEL_RCHF (0xBU << GPIO_FOUTSEL_FOUT1SEL_Pos)„GPIO_FOUTSEL_FOUT1SEL_XTHFD64 (0xCU << GPIO_FOUTSEL_FOUT1SEL_Pos)…GPIO_FOUTSEL_FOUT1SEL_ADCCLK (0xDU << GPIO_FOUTSEL_FOUT1SEL_Pos)†GPIO_FOUTSEL_FOUT1SEL_PLL_H (0xEU << GPIO_FOUTSEL_FOUT1SEL_Pos)‡GPIO_FOUTSEL_FOUT1SEL_BOOST_FLAG (0x10U << GPIO_FOUTSEL_FOUT1SEL_Pos)ˆGPIO_FOUTSEL_FOUT1SEL_AUTOTRIM_OUTPUT (0x11U << GPIO_FOUTSEL_FOUT1SEL_Pos)‹GPIO_FOUTSEL_FOUT0SEL_Pos 0ŒGPIO_FOUTSEL_FOUT0SEL_Msk (0x1fU << GPIO_FOUTSEL_FOUT0SEL_Pos)GPIO_FOUTSEL_FOUT0SEL_XTLF (0x0U << GPIO_FOUTSEL_FOUT0SEL_Pos)ŽGPIO_FOUTSEL_FOUT0SEL_RCLP (0x1U << GPIO_FOUTSEL_FOUT0SEL_Pos)GPIO_FOUTSEL_FOUT0SEL_RCHFD64 (0x2U << GPIO_FOUTSEL_FOUT0SEL_Pos)GPIO_FOUTSEL_FOUT0SEL_LSCLK (0x3U << GPIO_FOUTSEL_FOUT0SEL_Pos)‘GPIO_FOUTSEL_FOUT0SEL_AHBCLKD64 (0x4U << GPIO_FOUTSEL_FOUT0SEL_Pos)’GPIO_FOUTSEL_FOUT0SEL_RTC_TM (0x5U << GPIO_FOUTSEL_FOUT0SEL_Pos)“GPIO_FOUTSEL_FOUT0SEL_PLLHD64 (0x6U << GPIO_FOUTSEL_FOUT0SEL_Pos)”GPIO_FOUTSEL_FOUT0SEL_RTCCLK64Hz (0x7U << GPIO_FOUTSEL_FOUT0SEL_Pos)•GPIO_FOUTSEL_FOUT0SEL_APBCLKD64 (0x8U << GPIO_FOUTSEL_FOUT0SEL_Pos)–GPIO_FOUTSEL_FOUT0SEL_PLL_L (0x9U << GPIO_FOUTSEL_FOUT0SEL_Pos)—GPIO_FOUTSEL_FOUT0SEL_RCMF (0xAU << GPIO_FOUTSEL_FOUT0SEL_Pos)˜GPIO_FOUTSEL_FOUT0SEL_RCHF (0xBU << GPIO_FOUTSEL_FOUT0SEL_Pos)™GPIO_FOUTSEL_FOUT0SEL_XTHFD64 (0xCU << GPIO_FOUTSEL_FOUT0SEL_Pos)šGPIO_FOUTSEL_FOUT0SEL_ADCCLK (0xDU << GPIO_FOUTSEL_FOUT0SEL_Pos)›GPIO_FOUTSEL_FOUT0SEL_PLL_H (0xEU << GPIO_FOUTSEL_FOUT0SEL_Pos)œGPIO_FOUTSEL_FOUT0SEL_BOOST_FLAG (0x10U << GPIO_FOUTSEL_FOUT0SEL_Pos)žGPIO_IOMCR_IOMUXSEL_Pos 1ŸGPIO_IOMCR_IOMUXSEL_Msk (0x3U << GPIO_IOMCR_IOMUXSEL_Pos) GPIO_IOMCR_IOMUXSEL_PD6 (0x0U << GPIO_IOMCR_IOMUXSEL_Pos)¡GPIO_IOMCR_IOMUXSEL_PD7 (0x1U << GPIO_IOMCR_IOMUXSEL_Pos)¢GPIO_IOMCR_IOMUXSEL_PG2 (0x2U << GPIO_IOMCR_IOMUXSEL_Pos)£GPIO_IOMCR_IOMUXSEL_PG3 (0x3U << GPIO_IOMCR_IOMUXSEL_Pos)¥GPIO_IOMCR_IOMUXEN_Pos 0¦GPIO_IOMCR_IOMCUEN_Msk (0x1U << GPIO_IOMCR_IOMUXEN_Pos)¨GPIO_PINWKEN_WKISEL_Pos 31©GPIO_PINWKEN_WKISEL_Msk (0x1U << GPIO_PINWKEN_WKISEL_Pos)ªGPIO_PINWKEN_WKISEL_NMI (0x0U << GPIO_PINWKEN_WKISEL_Pos)«GPIO_PINWKEN_WKISEL_46 (0x1U << GPIO_PINWKEN_WKISEL_Pos)­GPIO_PINWKEN_PINWKSEL_Pos 8®GPIO_PINWKEN_PINWKSEL_Msk (0xffffU << GPIO_PINWKEN_PINWKSEL_Pos)¯GPIO_PINWKEN_PINWKSEL_FALLING 0°GPIO_PINWKEN_PINWKSEL_RISING 1±GPIO_PINWKEN_PINWKSEL_BOTH 2³GPIO_PINWKEN_PINWKEN_Pos 0´GPIO_PINWKEN_PINWKEN_Msk (0xffU << GPIO_PINWKEN_PINWKEN_Pos)¸GPIOH_DO_PHDO_Pos 0¹GPIOH_DO_PHDO_Msk (0xfU << GPIOH_DO_PHDO_Pos)¼GPIOH_DIN_PHDIN_Pos 0½GPIOH_DIN_PHDIN_Msk (0xfU << GPIOH_DIN_PHDIN_Pos)`U ..\Drivers\..\Core\Include\fm33a0xxev_gpio.hFM33A0XXEV.h$


..\Drivers\fm33a0xxev_gpio.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM‚GPIO_FCR_INGPIO_FCR_OUTGPIO_FCR_DIGGPIO_FCR_ANAPGPIO_FCR_TypeDef¾ ¼GPIO_OD_DisGPIO_OD_EnPGPIO_ODEN_TypeDef)÷GPIO_PU_DisGPIO_PU_EnPGPIO_PUEN_TypeDefU2²GPIO_IN_DisGPIO_IN_EnPGPIO_INEN_TypeDef;íGPIO_HD_DisGPIO_HD_EnPGPIO_HD_TypeDefËDªGPIO_ANEN_DisGPIO_ANEN_EnPGPIO_ANEN_TypeDefM*ŒPinf#PxFCR#PxODEN<#PxPUENw#PxINEN²#PGPIO_InitTypeDefCYÁBit_RESETBit_SETPBitAction¤b’EXTI_RISINGEXTI_FALLINGEXTI_BOTHEXTIDISABLEPGPIOExtiEdgeÒkstu__FM33A0XXEV_I2C_H I2C_SEND_STARTBIT(I2Cx) I2Cx_CR_SEN_Setable(I2Cx,ENABLE)I2C_SEND_RESTARTBIT(I2Cx) I2Cx_CR_RSEN_Setable(I2Cx,ENABLE)I2C_SEND_STOPBIT(I2Cx) I2Cx_CR_PEN_Setable(I2Cx,ENABLE)I2C_SEND_ACK_0(I2Cx) I2Cx_SR_ACKMO_Set(I2Cx,I2Cx_SR_ACKMO_RESET)I2C_SEND_ACK_1(I2Cx) I2Cx_SR_ACKMO_Set(I2Cx,I2Cx_SR_ACKMO_SET)!I2Cx_CFGR_AUTOEND_Pos 17$I2Cx_CFGR_AUTOEND_Msk (0x1U << I2Cx_CFGR_AUTOEND_Pos)%I2Cx_CFGR_AUTOEND_AUTO (0x1U << I2Cx_CFGR_AUTOEND_Pos)&I2Cx_CFGR_AUTOEND_MANUAL (0x0U << I2Cx_CFGR_AUTOEND_Pos)(I2Cx_CFGR_MSP_DMAEN_Pos 16+I2Cx_CFGR_MSP_DMAEN_Msk (0x1U << I2Cx_CFGR_MSP_DMAEN_Pos)/I2Cx_CFGR_TOEN_Pos 12I2Cx_CFGR_TOEN_Msk (0x1U << I2Cx_CFGR_TOEN_Pos)3I2Cx_CFGR_TOEN_ENABLE (0x1U << I2Cx_CFGR_TOEN_Pos)4I2Cx_CFGR_TOEN_DISABLE (0x0U << I2Cx_CFGR_TOEN_Pos)6I2Cx_CFGR_MSPEN_Pos 07I2Cx_CFGR_MSPEN_Msk (0x1U << I2Cx_CFGR_MSPEN_Pos)9I2Cx_CR_RCEN_Pos 3<I2Cx_CR_RCEN_Msk (0x1U << I2Cx_CR_RCEN_Pos)>I2Cx_CR_PEN_Pos 2?I2Cx_CR_PEN_Msk (0x1U << I2Cx_CR_PEN_Pos)AI2Cx_CR_RSEN_Pos 1BI2Cx_CR_RSEN_Msk (0x1U << I2Cx_CR_RSEN_Pos)DI2Cx_CR_SEN_Pos 0EI2Cx_CR_SEN_Msk (0x1U << I2Cx_CR_SEN_Pos)GI2Cx_IER_WCOLE_Pos 6JI2Cx_IER_WCOLE_Msk (0x1U << I2Cx_IER_WCOLE_Pos)NI2Cx_IER_TOE_Pos 5QI2Cx_IER_TOE_Msk (0x1U << I2Cx_IER_TOE_Pos)SI2Cx_IER_SE_Pos 4VI2Cx_IER_SE_Msk (0x1U << I2Cx_IER_SE_Pos)ZI2Cx_IER_PE_Pos 3]I2Cx_IER_PE_Msk (0x1U << I2Cx_IER_PE_Pos)aI2Cx_IER_NACKE_Pos 2dI2Cx_IER_NACKE_Msk (0x1U << I2Cx_IER_NACKE_Pos)hI2Cx_IER_TXIE_Pos 1kI2Cx_IER_TXIE_Msk (0x1U << I2Cx_IER_TXIE_Pos)oI2Cx_IER_RXIE_Pos 0rI2Cx_IER_RXIE_Msk (0x1U << I2Cx_IER_RXIE_Pos)vI2Cx_ISR_WCOL_Pos 6zI2Cx_ISR_WCOL_Msk (0x1U << I2Cx_ISR_WCOL_Pos)|I2Cx_ISR_TO_Pos 5}I2Cx_ISR_TO_Msk (0x1U << I2Cx_ISR_TO_Pos)€I2Cx_ISR_S_Pos 4‚I2Cx_ISR_S_Msk (0x1U << I2Cx_ISR_S_Pos)„I2Cx_ISR_P_Pos 3†I2Cx_ISR_P_Msk (0x1U << I2Cx_ISR_P_Pos)ˆI2Cx_ISR_ACKSTA_Pos 2‹I2Cx_ISR_ACKSTA_Msk (0x1U << I2Cx_ISR_ACKSTA_Pos)I2Cx_ISR_TXIF_Pos 1ŽI2Cx_ISR_TXIF_Msk (0x1U << I2Cx_ISR_TXIF_Pos)I2Cx_ISR_RXIF_Pos 0‘I2Cx_ISR_RXIF_Msk (0x1U << I2Cx_ISR_RXIF_Pos)“I2Cx_SR_BUSY_Pos 5–I2Cx_SR_BUSY_Msk (0x1U << I2Cx_SR_BUSY_Pos)˜I2Cx_SR_RW_Pos 4›I2Cx_SR_RW_Msk (0x1U << I2Cx_SR_RW_Pos)I2Cx_SR_BF_Pos 2¤I2Cx_SR_BF_Msk (0x1U << I2Cx_SR_BF_Pos)¦I2Cx_SR_ACKMO_Pos 0¬I2Cx_SR_ACKMO_Msk (0x1U << I2Cx_SR_ACKMO_Pos)­I2Cx_SR_ACKMO_RESET (0x0U << I2Cx_SR_ACKMO_Pos)®I2Cx_SR_ACKMO_SET (0x1U << I2Cx_SR_ACKMO_Pos)°I2Cx_BRG_MSPBRGH_Pos 16±I2Cx_BRG_MSPBRGH_Msk (0x1ffU << I2Cx_BRG_MSPBRGH_Pos)³I2Cx_BRG_MSPBRGL_Pos 0´I2Cx_BRG_MSPBRGL_Msk (0x1ffU << I2Cx_BRG_MSPBRGL_Pos)¶I2Cx_BUF_WR_Pos 0·I2Cx_BUF_WR_Msk (0xffU << I2Cx_BUF_WR_Pos)¹I2Cx_TIMING_SDAHD_Pos 0»I2Cx_TIMING_SDAHD_Msk (0x1ffU << I2Cx_TIMING_SDAHD_Pos)½I2Cx_TO_TIMEOUT_Pos 0¿I2Cx_TO_TIMEOUT_Msk (0xfffU << I2Cx_TO_TIMEOUT_Pos)`T ..\Drivers\..\Core\Include\fm33a0xxev_i2c.hFM33A0XXEV.h¼


..\Drivers\fm33a0xxev_i2c.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMwxy__FM33A0XXEV_IWDT_H IWDT_SERV_IWDTSERV_KEY 0x12345A5AUIWDT_SERV_IWDTSERV_Pos 0IWDT_SERV_IWDTSERV_Msk (0xffffffffU << IWDT_SERV_IWDTSERV_Pos)IWDT_CFGR_IWDTOVP_Pos 0"IWDT_CFGR_IWDTOVP_Msk (0x7U << IWDT_CFGR_IWDTOVP_Pos)#IWDT_IWDTOVP_125MS (0x0U << IWDT_CFGR_IWDTOVP_Pos)$IWDT_IWDTOVP_500MS (0x1U << IWDT_CFGR_IWDTOVP_Pos)%IWDT_IWDTOVP_2S (0x2U << IWDT_CFGR_IWDTOVP_Pos)&IWDT_IWDTOVP_8S (0x3U << IWDT_CFGR_IWDTOVP_Pos)(IWDT_IWDTOVP_4096S (0x4U << IWDT_CFGR_IWDTOVP_Pos)*IWDT_CNTR_IWDTCNT_Pos 0+IWDT_CNTR_IWDTCNT_Msk (0xfffffU << IWDT_CNTR_IWDTCNT_Pos)`U ..\Drivers\..\Core\Include\fm33a0xxev_iwdt.hFM33A0XXEV.h¼


..\Drivers\fm33a0xxev_iwdt.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM{|}__FM33A0XXEV_LPUART_H LPUARTx_MCTL_FOR9600 (0x00000552<<16)LPUARTx_MCTL_FOR4800 (0x00001EFB<<16)LPUARTx_MCTL_FOR2400 (0x000016DB<<16)LPUARTx_MCTL_FOR1200 (0x00000492<<16)LPUARTx_MCTL_FOR600 (0x000016D6<<16)LPUARTx_MCTL_FOR300 (0x00000842<<16) LPUARTx_CSR_BUSY_Pos 24#LPUARTx_CSR_BUSY_Msk (0x1U << LPUARTx_CSR_BUSY_Pos)%LPUARTx_CSR_WKBYTECFG_Pos 19(LPUARTx_CSR_WKBYTECFG_Msk (0x1U << LPUARTx_CSR_WKBYTECFG_Pos)*LPUARTx_CSR_RXEV_Pos 160LPUARTx_CSR_RXEV_Msk (0x3U << LPUARTx_CSR_RXEV_Pos)1LPUARTx_CSR_RXEV_START (0x0U << LPUARTx_CSR_RXEV_Pos)2LPUARTx_CSR_RXEV_1BYTE (0x1U << LPUARTx_CSR_RXEV_Pos)3LPUARTx_CSR_RXEV_MATCH (0x2U << LPUARTx_CSR_RXEV_Pos)4LPUARTx_CSR_RXEV_FALLING (0x3U << LPUARTx_CSR_RXEV_Pos)6LPUARTx_CSR_IOSWAP_Pos 119LPUARTx_CSR_IOSWAP_Msk (0x1U << LPUARTx_CSR_IOSWAP_Pos):LPUARTx_CSR_IOSWAP_DEFUALT (0x0U << LPUARTx_CSR_IOSWAP_Pos);LPUARTx_CSR_IOSWAP_SWAP (0x1U << LPUARTx_CSR_IOSWAP_Pos)>LPUARTx_CSR_DMATXIFCFG_Pos 10ALPUARTx_CSR_DMATXIFCFG_Msk (0x1U << LPUARTx_CSR_DMATXIFCFG_Pos)ELPUARTx_CSR_BITORD_Pos 9HLPUARTx_CSR_BITORD_Msk (0x1U << LPUARTx_CSR_BITORD_Pos)ILPUARTx_CSR_BITORD_LSB (0x0U << LPUARTx_CSR_BITORD_Pos)JLPUARTx_CSR_BITORD_MSB (0x1U << LPUARTx_CSR_BITORD_Pos)LLPUARTx_CSR_STOPCFG_Pos 8OLPUARTx_CSR_STOPCFG_Msk (0x1U << LPUARTx_CSR_STOPCFG_Pos)PLPUARTx_CSR_STOPCFG_1STOP (0x0U << LPUARTx_CSR_STOPCFG_Pos)QLPUARTx_CSR_STOPCFG_2STOP (0x1U << LPUARTx_CSR_STOPCFG_Pos)SLPUARTx_CSR_PDSEL_Pos 6YLPUARTx_CSR_PDSEL_Msk (0x3U << LPUARTx_CSR_PDSEL_Pos)ZLPUARTx_CSR_PDSEL_7BITS (0x0U << LPUARTx_CSR_PDSEL_Pos)[LPUARTx_CSR_PDSEL_8BITS (0x1U << LPUARTx_CSR_PDSEL_Pos)\LPUARTx_CSR_PDSEL_9BITS (0x2U << LPUARTx_CSR_PDSEL_Pos)]LPUARTx_CSR_PDSEL_6BITS (0x3U << LPUARTx_CSR_PDSEL_Pos)_LPUARTx_CSR_PARITY_Pos 4dLPUARTx_CSR_PARITY_Msk (0x3U << LPUARTx_CSR_PARITY_Pos)eLPUARTx_CSR_PARITY_NON (0x0U << LPUARTx_CSR_PARITY_Pos)fLPUARTx_CSR_PARITY_EVEN (0x1U << LPUARTx_CSR_PARITY_Pos)gLPUARTx_CSR_PARITY_ODD (0x2U << LPUARTx_CSR_PARITY_Pos)iLPUARTx_CSR_RXPOL_Pos 3lLPUARTx_CSR_RXPOL_Msk (0x1U << LPUARTx_CSR_RXPOL_Pos)mLPUARTx_CSR_RXPOL_POS (0x0U << LPUARTx_CSR_RXPOL_Pos)nLPUARTx_CSR_RXPOL_NEG (0x1U << LPUARTx_CSR_RXPOL_Pos)pLPUARTx_CSR_TXPOL_Pos 2sLPUARTx_CSR_TXPOL_Msk (0x1U << LPUARTx_CSR_TXPOL_Pos)tLPUARTx_CSR_TXPOL_POS (0x0U << LPUARTx_CSR_TXPOL_Pos)uLPUARTx_CSR_TXPOL_NEG (0x1U << LPUARTx_CSR_TXPOL_Pos)wLPUARTx_CSR_RXEN_Pos 1xLPUARTx_CSR_RXEN_Msk (0x1U << LPUARTx_CSR_RXEN_Pos)zLPUARTx_CSR_TXEN_Pos 0{LPUARTx_CSR_TXEN_Msk (0x1U << LPUARTx_CSR_TXEN_Pos)}LPUARTx_IER_RXEV_IE_Pos 12~LPUARTx_IER_RXEV_IE_Msk (0x1U << LPUARTx_IER_RXEV_IE_Pos)€LPUARTx_IER_RXERR_IE_Pos 10LPUARTx_IER_RXERR_IE_Msk (0x1U << LPUARTx_IER_RXERR_IE_Pos)ƒLPUARTx_IER_RXBF_IE_Pos 8„LPUARTx_IER_RXBF_IE_Msk (0x1U << LPUARTx_IER_RXBF_IE_Pos)†LPUARTx_IER_TXBE_IE_Pos 1‡LPUARTx_IER_TXBE_IE_Msk (0x1U << LPUARTx_IER_TXBE_IE_Pos)‰LPUARTx_IER_TXSE_IE_Pos 0ŠLPUARTx_IER_TXSE_IE_Msk (0x1U << LPUARTx_IER_TXSE_IE_Pos)ŒLPUARTx_ISR_RXEVF_Pos 24ŽLPUARTx_ISR_RXEVF_Msk (0x1U << LPUARTx_ISR_RXEVF_Pos)LPUARTx_ISR_TXOV_Pos 19’LPUARTx_ISR_TXOV_Msk (0x1U << LPUARTx_ISR_TXOV_Pos)”LPUARTx_ISR_PERR_Pos 18•LPUARTx_ISR_PERR_Msk (0x1U << LPUARTx_ISR_PERR_Pos)—LPUARTx_ISR_FERR_Pos 17˜LPUARTx_ISR_FERR_Msk (0x1U << LPUARTx_ISR_FERR_Pos)šLPUARTx_ISR_OERR_Pos 16›LPUARTx_ISR_OERR_Msk (0x1U << LPUARTx_ISR_OERR_Pos)LPUARTx_ISR_RXBF_Pos 8žLPUARTx_ISR_RXBF_Msk (0x1U << LPUARTx_ISR_RXBF_Pos) LPUARTx_ISR_TXBE_Pos 1¡LPUARTx_ISR_TXBE_Msk (0x1U << LPUARTx_ISR_TXBE_Pos)£LPUARTx_ISR_TXSE_Pos 0¤LPUARTx_ISR_TXSE_Msk (0x1U << LPUARTx_ISR_TXSE_Pos)¦LPUARTx_BMR_MCTL_Pos 16§LPUARTx_BMR_MCTL_Msk (0x1fffU << LPUARTx_BMR_MCTL_Pos)©LPUARTx_BMR_BAUD_Pos 0°LPUARTx_BMR_BAUD_Msk (0x7U << LPUARTx_BMR_BAUD_Pos)±LPUARTx_BMR_BAUD_9600 (0x0U << LPUARTx_BMR_BAUD_Pos)²LPUARTx_BMR_BAUD_4800 (0x1U << LPUARTx_BMR_BAUD_Pos)³LPUARTx_BMR_BAUD_2400 (0x2U << LPUARTx_BMR_BAUD_Pos)´LPUARTx_BMR_BAUD_1200 (0x3U << LPUARTx_BMR_BAUD_Pos)µLPUARTx_BMR_BAUD_600 (0x4U << LPUARTx_BMR_BAUD_Pos)¶LPUARTx_BMR_BAUD_300 (0x5U << LPUARTx_BMR_BAUD_Pos)¸LPUARTx_RXBUF_RXBUF_Pos 0¹LPUARTx_RXBUF_RXBUF_Msk (0x1ffU << LPUARTx_RXBUF_RXBUF_Pos)»LPUARTx_TXBUF_TXBUF_Pos 0¼LPUARTx_TXBUF_TXBUF_Msk (0x1ffU << LPUARTx_TXBUF_TXBUF_Pos)¾LPUARTx_DMR_MATD_Pos 0ÀLPUARTx_DMR_MATD_Msk (0x1ffU << LPUARTx_DMR_MATD_Pos)`W ..\Drivers\..\Core\Include\fm33a0xxev_lpuart.hFM33A0XXEV.hÀ


..\Drivers\fm33a0xxev_lpuart.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM€__FM33A0XXEV_FLASH_H FLS_RDCR_WAIT_Pos 0FLS_RDCR_WAIT_Msk (0x3U << FLS_RDCR_WAIT_Pos)FLS_RDCR_WAIT_0CYCLE (0x0U << FLS_RDCR_WAIT_Pos) FLS_RDCR_WAIT_1CYCLE (0x1U << FLS_RDCR_WAIT_Pos)!FLS_RDCR_WAIT_2CYCLE (0x2U << FLS_RDCR_WAIT_Pos)#FLS_PFCR_PRFTEN_Pos 0&FLS_PFCR_PRFTEN_Msk (0x1U << FLS_PFCR_PRFTEN_Pos)*FLS_OPTBR_DBGCFGEN_Pos 31+FLS_OPTBR_DBGCFGEN_Msk (0x1U << FLS_OPTBR_DBGCFGEN_Pos)-FLS_OPTBR_IF2LOCK_Pos 180FLS_OPTBR_IF2LOCK_Msk (0x1U << FLS_OPTBR_IF2LOCK_Pos)2FLS_OPTBR_IF1LOCK_Pos 175FLS_OPTBR_IF1LOCK_Msk (0x1U << FLS_OPTBR_IF1LOCK_Pos)7FLS_OPTBR_DFLSEN_Pos 10:FLS_OPTBR_DFLSEN_Msk (0x1U << FLS_OPTBR_DFLSEN_Pos)>FLS_OPTBR_BTSEN_Pos 8AFLS_OPTBR_BTSEN_Msk (0x3U << FLS_OPTBR_BTSEN_Pos)GFLS_OPTBR_ACLOCKEN_Pos 4JFLS_OPTBR_ACLOCKEN_Msk (0x3U << FLS_OPTBR_ACLOCKEN_Pos)PFLS_OPTBR_DBRDPEN_Pos 0SFLS_OPTBR_DBRDPEN_Msk (0xfU << FLS_OPTBR_DBRDPEN_Pos)YFLS_OPTBR_LOCK1_Pos 0ZFLS_OPTBR_LOCK1_Msk (0xffffffffU << FLS_OPTBR_LOCK1_Pos)\FLS_OPTBR_LOCK2_Pos 0]FLS_OPTBR_LOCK2_Msk (0xffffffffU << FLS_OPTBR_LOCK2_Pos)_FLS_OPTBR_LOCK3_Pos 0`FLS_OPTBR_LOCK3_Msk (0xffffffffU << FLS_OPTBR_LOCK3_Pos)bFLS_OPTBR_LOCK4_Pos 0cFLS_OPTBR_LOCK4_Msk (0xffffffffU << FLS_OPTBR_LOCK4_Pos)eFLS_EPCR_ERTYPE_Pos 8iFLS_EPCR_ERTYPE_Msk (0x3U << FLS_EPCR_ERTYPE_Pos)jFLS_EPCR_ERTYPE_PAGE (0x0U << FLS_EPCR_ERTYPE_Pos)kFLS_EPCR_ERTYPE_SECTOR (0x1U << FLS_EPCR_ERTYPE_Pos)lFLS_EPCR_ERTYPE_CHIP_ERASE (0x2U << FLS_EPCR_ERTYPE_Pos)nFLS_EPCR_PREQ_Pos 1pFLS_EPCR_PREQ_Msk (0x1U << FLS_EPCR_PREQ_Pos)rFLS_EPCR_EREQ_Pos 0tFLS_EPCR_EREQ_Msk (0x1U << FLS_EPCR_EREQ_Pos)vFLS_KEY_KEY_Pos 0wFLS_KEY_KEY_Msk (0xffffffffU << FLS_KEY_KEY_Pos)yFLS_IER_OTPIE_Pos 11zFLS_IER_OTPIE_Msk (0x1U << FLS_IER_OTPIE_Pos)|FLS_IER_AUTHIE_Pos 10}FLS_IER_AUTHIE_Msk (0x1U << FLS_IER_AUTHIE_Pos)FLS_IER_KEYIE_Pos 9€FLS_IER_KEYIE_Msk (0x1U << FLS_IER_KEYIE_Pos)‚FLS_IER_CKIE_Pos 8ƒFLS_IER_CKIE_Msk (0x1U << FLS_IER_CKIE_Pos)…FLS_IER_PRDIE_Pos 1†FLS_IER_PRDIE_Msk (0x1U << FLS_IER_PRDIE_Pos)ˆFLS_IER_ERDIE_Pos 0‰FLS_IER_ERDIE_Msk (0x1U << FLS_IER_ERDIE_Pos)‹FLS_ISR_KEYSTA_Pos 17’FLS_ISR_KEYSTA_Msk (0x7U << FLS_ISR_KEYSTA_Pos)“FLS_ISR_KEYSTA_KEY_NONE_PROTECT (0x0U << FLS_ISR_KEYSTA_Pos)”FLS_ISR_KEYSTA_CHIP_ERASE (0x1U << FLS_ISR_KEYSTA_Pos)•FLS_ISR_KEYSTA_SECTOR_ERASE (0x2U << FLS_ISR_KEYSTA_Pos)–FLS_ISR_KEYSTA_PROGRAM (0x3U << FLS_ISR_KEYSTA_Pos)—FLS_ISR_KEYSTA_KEY_ERR_PROTECT (0x4U << FLS_ISR_KEYSTA_Pos)™FLS_ISR_BTSF_Pos 16œFLS_ISR_BTSF_Msk (0x1U << FLS_ISR_BTSF_Pos)FLS_ISR_BTSF_START_0000H (0x0U << FLS_ISR_BTSF_Pos)žFLS_ISR_BTSF_START_2000H (0x1U << FLS_ISR_BTSF_Pos) FLS_ISR_OTPERR_Pos 11£FLS_ISR_OTPERR_Msk (0x1U << FLS_ISR_OTPERR_Pos)¥FLS_ISR_AUTHERR_Pos 10¨FLS_ISR_AUTHERR_Msk (0x1U << FLS_ISR_AUTHERR_Pos)ªFLS_ISR_KEYERR_Pos 9«FLS_ISR_KEYERR_Msk (0x1U << FLS_ISR_KEYERR_Pos)­FLS_ISR_CKERR_Pos 8®FLS_ISR_CKERR_Msk (0x1U << FLS_ISR_CKERR_Pos)°FLS_ISR_PRD_Pos 1±FLS_ISR_PRD_Msk (0x1U << FLS_ISR_PRD_Pos)³FLS_ISR_ERD_Pos 0´FLS_ISR_ERD_Msk (0x1U << FLS_ISR_ERD_Pos)`V ..\Drivers\..\Core\Include\fm33a0xxev_flash.hFM33A0XXEV.hÀ


..\Drivers\fm33a0xxev_flash.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMƒ„…__FM33A0XXEV_PMU_H  PMU_CR_LDO15EN_Pos 17#PMU_CR_LDO15EN_Msk (0x1U << PMU_CR_LDO15EN_Pos)%PMU_CR_LDO15EN_B_Pos 16&PMU_CR_LDO15EN_B_Msk (0x1U << PMU_CR_LDO15EN_B_Pos)(PMU_CR_WKFSEL_Pos 10-PMU_CR_WKFSEL_Msk (0x3U << PMU_CR_WKFSEL_Pos).PMU_CR_WKFSEL_RCHF_8M (0x0U << PMU_CR_WKFSEL_Pos)/PMU_CR_WKFSEL_RCHF_16M (0x1U << PMU_CR_WKFSEL_Pos)0PMU_CR_WKFSEL_RCHF_24M (0x2U << PMU_CR_WKFSEL_Pos)1PMU_CR_WKFSEL_RCHF_32M (0x3U << PMU_CR_WKFSEL_Pos)3PMU_CR_SLPDP_Pos 98PMU_CR_SLPDP_Msk (0x1U << PMU_CR_SLPDP_Pos)9PMU_CR_SLPDP_DEEPSLEEP (0x1U << PMU_CR_SLPDP_Pos):PMU_CR_SLPDP_SLEEP (0x0U << PMU_CR_SLPDP_Pos)<PMU_CR_CVS_Pos 8@PMU_CR_CVS_Msk (0x1U << PMU_CR_CVS_Pos)APMU_CR_CVS_DISABLE (0x0U << PMU_CR_CVS_Pos)BPMU_CR_CVS_ENABLE (0x1U << PMU_CR_CVS_Pos)DPMU_CR_PMOD_Pos 0IPMU_CR_PMOD_Msk (0x3U << PMU_CR_PMOD_Pos)JPMU_CR_PMOD_ACTIVE (0x0U << PMU_CR_PMOD_Pos)KPMU_CR_PMOD_LPRUN (0x1U << PMU_CR_PMOD_Pos)LPMU_CR_PMOD_SLEEP (0x2U << PMU_CR_PMOD_Pos)NPMU_WKTR_STPCLR_Pos 2QPMU_WKTR_STPCLR_Msk (0x1U << PMU_WKTR_STPCLR_Pos)RPMU_WKTR_STPCLR_SYN (0x0U << PMU_WKTR_STPCLR_Pos)SPMU_WKTR_STPCLR_ASY (0x1U << PMU_WKTR_STPCLR_Pos)UPMU_WKTR_T1A_Pos 0[PMU_WKTR_T1A_Msk (0x3U << PMU_WKTR_T1A_Pos)\PMU_WKTR_T1A_0US (0x0U << PMU_WKTR_T1A_Pos)]PMU_WKTR_T1A_2US (0x1U << PMU_WKTR_T1A_Pos)^PMU_WKTR_T1A_4US (0x2U << PMU_WKTR_T1A_Pos)_PMU_WKTR_T1A_8US (0x3U << PMU_WKTR_T1A_Pos)aPMU_WKFR_ADCWKF_Pos 31bPMU_WKFR_ADCWKF_Msk (0x1U << PMU_WKFR_ADCWKF_Pos)dPMU_WKFR_RTCWKF_Pos 28ePMU_WKFR_RTCWKF_Msk (0x1U << PMU_WKFR_RTCWKF_Pos)gPMU_WKFR_SVDWKF_Pos 27hPMU_WKFR_SVDWKF_Msk (0x1U << PMU_WKFR_SVDWKF_Pos)jPMU_WKFR_LFDETWKF_Pos 26kPMU_WKFR_LFDETWKF_Msk (0x1U << PMU_WKFR_LFDETWKF_Pos)mPMU_WKFR_IOWKF_Pos 24nPMU_WKFR_IOWKF_Msk (0x1U << PMU_WKFR_IOWKF_Pos)pPMU_WKFR_LPU1WKF_Pos 21qPMU_WKFR_LPU1WKF_Msk (0x1U << PMU_WKFR_LPU1WKF_Pos)sPMU_WKFR_LPU0WKF_Pos 20tPMU_WKFR_LPU0WKF_Msk (0x1U << PMU_WKFR_LPU0WKF_Pos)vPMU_WKFR_COMP_OOWF_Pos 19wPMU_WKFR_COMP_OOWF_Msk (0x1U << PMU_WKFR_COMP_OOWF_Pos)yPMU_WKFR_COMP_WINF_Pos 18zPMU_WKFR_COMP_WINF_Msk (0x1U << PMU_WKFR_COMP_WINF_Pos)|PMU_WKFR_COMP2WKF_Pos 17}PMU_WKFR_COMP2WKF_Msk (0x1U << PMU_WKFR_COMP2WKF_Pos)PMU_WKFR_COMP1WKF_Pos 16€PMU_WKFR_COMP1WKF_Msk (0x1U << PMU_WKFR_COMP1WKF_Pos)‚PMU_WKFR_LPTWKF_Pos 10ƒPMU_WKFR_LPTWKF_Msk (0x1U << PMU_WKFR_LPTWKF_Pos)…PMU_WKFR_BSTWKF_Pos 9†PMU_WKFR_BSTWKF_Msk (0x1U << PMU_WKFR_BSTWKF_Pos)ˆPMU_WKFR_DBGWKF_Pos 8‰PMU_WKFR_DBGWKF_Msk (0x1U << PMU_WKFR_DBGWKF_Pos)ŒPMU_IER_SLPEIE_Pos 1PMU_IER_SLPEIE_Msk (0x1U << PMU_IER_SLPEIE_Pos)“PMU_IER_RTCEIE_Pos 0–PMU_IER_RTCEIE_Msk (0x1U << PMU_IER_RTCEIE_Pos)šPMU_ISR_SLPEIF_Pos 1PMU_ISR_SLPEIF_Msk (0x1U << PMU_ISR_SLPEIF_Pos)ŸPMU_ISR_RTCEIF_Pos 0¢PMU_ISR_RTCEIF_Msk (0x1U << PMU_ISR_RTCEIF_Pos)`T ..\Drivers\..\Core\Include\fm33a0xxev_pmu.hFM33A0XXEV.h$


..\Drivers\fm33a0xxev_pmu.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM*†PMODf#SLPDPf#CVS#SCRf#TIAf#PPMU_SleepCfg_InitTypeDef½‡ˆ‰__FM33A0XXEV_CMU_H HXVAR(object,addr) (*((object *) (addr)))const_rchf_Trim8 HXVAR( uint32_t, 0x1FFFFB40 )const_rchf_Trim16 HXVAR( uint32_t, 0x1FFFFB3C )const_rchf_Trim24 HXVAR( uint32_t, 0x1FFFFB38 )const_rchf_Trim32 HXVAR( uint32_t, 0x1FFFFB34)!__XTHF_CLOCK (12000000)RCMU_SYSCLKCR_SLP_ENEXTI_Pos 25SCMU_SYSCLKCR_SLP_ENEXTI_Msk (0x1U << CMU_SYSCLKCR_SLP_ENEXTI_Pos)UCMU_SYSCLKCR_APBPRES_Pos 16[CMU_SYSCLKCR_APBPRES_Msk (0x7U << CMU_SYSCLKCR_APBPRES_Pos)\CMU_SYSCLKCR_APBPRES_DIV1 (0x0U << CMU_SYSCLKCR_APBPRES_Pos)]CMU_SYSCLKCR_APBPRES_DIV2 (0x4U << CMU_SYSCLKCR_APBPRES_Pos)^CMU_SYSCLKCR_APBPRES_DIV4 (0x5U << CMU_SYSCLKCR_APBPRES_Pos)_CMU_SYSCLKCR_APBPRES_DIV8 (0x6U << CMU_SYSCLKCR_APBPRES_Pos)`CMU_SYSCLKCR_APBPRES_DIV16 (0x7U << CMU_SYSCLKCR_APBPRES_Pos)bCMU_SYSCLKCR_AHBPRES_Pos 8hCMU_SYSCLKCR_AHBPRES_Msk (0x7U << CMU_SYSCLKCR_AHBPRES_Pos)iCMU_SYSCLKCR_AHBPRES_DIV1 (0x0U << CMU_SYSCLKCR_AHBPRES_Pos)jCMU_SYSCLKCR_AHBPRES_DIV2 (0x4U << CMU_SYSCLKCR_AHBPRES_Pos)kCMU_SYSCLKCR_AHBPRES_DIV4 (0x5U << CMU_SYSCLKCR_AHBPRES_Pos)lCMU_SYSCLKCR_AHBPRES_DIV8 (0x6U << CMU_SYSCLKCR_AHBPRES_Pos)mCMU_SYSCLKCR_AHBPRES_DIV16 (0x7U << CMU_SYSCLKCR_AHBPRES_Pos)oCMU_SYSCLKCR_STCLKSEL_Pos 6tCMU_SYSCLKCR_STCLKSEL_Msk (0x3U << CMU_SYSCLKCR_STCLKSEL_Pos)uCMU_SYSCLKCR_STCLKSEL_SCLK (0x0U << CMU_SYSCLKCR_STCLKSEL_Pos)vCMU_SYSCLKCR_STCLKSEL_LSCLK (0x1U << CMU_SYSCLKCR_STCLKSEL_Pos)wCMU_SYSCLKCR_STCLKSEL_RC4M (0x2U << CMU_SYSCLKCR_STCLKSEL_Pos)xCMU_SYSCLKCR_STCLKSEL_SYSCLK (0x3U << CMU_SYSCLKCR_STCLKSEL_Pos)zCMU_SYSCLKCR_SYSCLKSEL_Pos 0{CMU_SYSCLKCR_SYSCLKSEL_Msk (0x7U << CMU_SYSCLKCR_SYSCLKSEL_Pos)|CMU_SYSCLKCR_SYSCLKSEL_RCHF (0x0U << CMU_SYSCLKCR_SYSCLKSEL_Pos)}CMU_SYSCLKCR_SYSCLKSEL_XTHF (0x1U << CMU_SYSCLKCR_SYSCLKSEL_Pos)~CMU_SYSCLKCR_SYSCLKSEL_PLL_H (0x2U << CMU_SYSCLKCR_SYSCLKSEL_Pos)CMU_SYSCLKCR_SYSCLKSEL_LSCLK (0x3U << CMU_SYSCLKCR_SYSCLKSEL_Pos)CMU_RCHFCR_FSEL_Pos 16ˆCMU_RCHFCR_FSEL_Msk (0xfU << CMU_RCHFCR_FSEL_Pos)‰CMU_RCHFCR_FSEL_8MHZ (0x0U << CMU_RCHFCR_FSEL_Pos)ŠCMU_RCHFCR_FSEL_16MHZ (0x1U << CMU_RCHFCR_FSEL_Pos)‹CMU_RCHFCR_FSEL_24MHZ (0x2U << CMU_RCHFCR_FSEL_Pos)ŒCMU_RCHFCR_FSEL_32MHZ (0x3U << CMU_RCHFCR_FSEL_Pos)ŽCMU_RCHFCR_RCHFEN_Pos 0‘CMU_RCHFCR_RCHFEN_Msk (0x1U << CMU_RCHFCR_RCHFEN_Pos)•CMU_RCHFTR_RCHFTRIM_Pos 0˜CMU_RCHFTR_RCHFTRIM_Msk (0xffU << CMU_RCHFTR_RCHFTRIM_Pos)šCMU_PLLLCR_PLLDB_Pos 16›CMU_PLLLCR_PLLDB_Msk (0x3ffU << CMU_PLLLCR_PLLDB_Pos)CMU_PLLLCR_LOCKED_Pos 7žCMU_PLLLCR_LOCKED_Msk (0x1U << CMU_PLLLCR_LOCKED_Pos) CMU_PLLLCR_PLLEN_Pos 0£CMU_PLLLCR_PLLEN_Msk (0x1U << CMU_PLLLCR_PLLEN_Pos)¥CMU_PLLHCR_PLLHDB_Pos 16¨CMU_PLLHCR_PLLHDB_Msk (0x3ffU << CMU_PLLHCR_PLLHDB_Pos)©CMU_PLLHCR_PLLHDB_X32 (0x1fU << CMU_PLLHCR_PLLHDB_Pos)ªCMU_PLLHCR_PLLHDB_X48 (0x2fU << CMU_PLLHCR_PLLHDB_Pos)«CMU_PLLHCR_PLLHDB_X64 (0x3fU << CMU_PLLHCR_PLLHDB_Pos)­CMU_PLLHCR_LOCKED_Pos 7°CMU_PLLHCR_LOCKED_Msk (0x1U << CMU_PLLHCR_LOCKED_Pos)²CMU_PLLHCR_REFPRSC_Pos 4»CMU_PLLHCR_REFPRSC_Msk (0x7U << CMU_PLLHCR_REFPRSC_Pos)¼CMU_PLLHCR_REFPRSC_DIV1 (0x0U << CMU_PLLHCR_REFPRSC_Pos)½CMU_PLLHCR_REFPRSC_DIV2 (0x1U << CMU_PLLHCR_REFPRSC_Pos)¾CMU_PLLHCR_REFPRSC_DIV4 (0x2U << CMU_PLLHCR_REFPRSC_Pos)¿CMU_PLLHCR_REFPRSC_DIV8 (0x3U << CMU_PLLHCR_REFPRSC_Pos)ÀCMU_PLLHCR_REFPRSC_DIV12 (0x4U << CMU_PLLHCR_REFPRSC_Pos)ÁCMU_PLLHCR_REFPRSC_DIV16 (0x5U << CMU_PLLHCR_REFPRSC_Pos)ÂCMU_PLLHCR_REFPRSC_DIV24 (0x6U << CMU_PLLHCR_REFPRSC_Pos)ÃCMU_PLLHCR_REFPRSC_DIV32 (0x7U << CMU_PLLHCR_REFPRSC_Pos)ÅCMU_PLLHCR_OSEL_Pos 3ÈCMU_PLLHCR_OSEL_Msk (0x1U << CMU_PLLHCR_OSEL_Pos)ÉCMU_PLLHCR_OSEL_X1 (0x0U << CMU_PLLHCR_OSEL_Pos)ÊCMU_PLLHCR_OSEL_X2 (0x1U << CMU_PLLHCR_OSEL_Pos)ÌCMU_PLLHCR_INSEL_Pos 1ÏCMU_PLLHCR_INSEL_Msk (0x1U << CMU_PLLHCR_INSEL_Pos)ÐCMU_PLLHCR_INSEL_RCHF (0x0U << CMU_PLLHCR_INSEL_Pos)ÑCMU_PLLHCR_INSEL_XTHF (0x1U << CMU_PLLHCR_INSEL_Pos)ÓCMU_PLLHCR_EN_Pos 0ÖCMU_PLLHCR_EN_Msk (0x1U << CMU_PLLHCR_EN_Pos)ØCMU_XTHFCR_XTHF_CFG_Pos 8ÛCMU_XTHFCR_XTHF_CFG_Msk (0x7U << CMU_XTHFCR_XTHF_CFG_Pos)ÜCMU_XTHFCR_XTHF_CFG_MIN (0x0U << CMU_XTHFCR_XTHF_CFG_Pos)ÝCMU_XTHFCR_XTHF_CFG_MAX (0x7U << CMU_XTHFCR_XTHF_CFG_Pos)ßCMU_XTHFCR_XTHFEN_Pos 0âCMU_XTHFCR_XTHFEN_Msk (0x1U << CMU_XTHFCR_XTHFEN_Pos)æCMU_IER_SYSCSE_IE_Pos 1çCMU_IER_SYSCSE_IE_Msk (0x1U << CMU_IER_SYSCSE_IE_Pos)éCMU_IER_HFDET_IE_Pos 0êCMU_IER_HFDET_IE_Msk (0x1U << CMU_IER_HFDET_IE_Pos)íCMU_ISR_HFDETO_Pos 8ðCMU_ISR_HFDETO_Msk (0x1U << CMU_ISR_HFDETO_Pos)òCMU_ISR_SYSCSE_IF_Pos 1óCMU_ISR_SYSCSE_IF_Msk (0x1U << CMU_ISR_SYSCSE_IF_Pos)õCMU_ISR_HFDET_IF_Pos 0öCMU_ISR_HFDET_IF_Msk (0x1U << CMU_ISR_HFDET_IF_Pos)øCMU_PCLKCR1_COMP_PCE_Pos 9ùCMU_PCLKCR1_COMP_PCE_Msk (0x1U << CMU_PCLKCR1_COMP_PCE_Pos)ûCMU_PCLKCR1_SVD_PCE_Pos 8üCMU_PCLKCR1_SVD_PCE_Msk (0x1U << CMU_PCLKCR1_SVD_PCE_Pos)þCMU_PCLKCR1_PAD_PCE_Pos 7ÿCMU_PCLKCR1_PAD_PCE_Msk (0x1U << CMU_PCLKCR1_PAD_PCE_Pos)CMU_PCLKCR1_ANAC_PCE_Pos 6ƒCMU_PCLKCR1_ANAC_PCE_Msk (0x1U << CMU_PCLKCR1_ANAC_PCE_Pos)…CMU_PCLKCR1_IWDT_PCE_Pos 5†CMU_PCLKCR1_IWDT_PCE_Msk (0x1U << CMU_PCLKCR1_IWDT_PCE_Pos)ˆCMU_PCLKCR1_SCU_PCE_Pos 4‰CMU_PCLKCR1_SCU_PCE_Msk (0x1U << CMU_PCLKCR1_SCU_PCE_Pos)‹CMU_PCLKCR1_PMU_PCE_Pos 3ŒCMU_PCLKCR1_PMU_PCE_Msk (0x1U << CMU_PCLKCR1_PMU_PCE_Pos)ŽCMU_PCLKCR1_RTC_PCE_Pos 2CMU_PCLKCR1_RTC_PCE_Msk (0x1U << CMU_PCLKCR1_RTC_PCE_Pos)‘CMU_PCLKCR1_LPT_PCE_Pos 0’CMU_PCLKCR1_LPT_PCE_Msk (0x1U << CMU_PCLKCR1_LPT_PCE_Pos)”CMU_PCLKCR2_PAE_PCE_Pos 17•CMU_PCLKCR2_PAE_PCE_Msk (0x1U << CMU_PCLKCR2_PAE_PCE_Pos)—CMU_PCLKCR2_SHA_PCE_Pos 16˜CMU_PCLKCR2_SHA_PCE_Msk (0x1U << CMU_PCLKCR2_SHA_PCE_Pos)šCMU_PCLKCR2_CIC_PCE_Pos 8›CMU_PCLKCR2_CIC_PCE_Msk (0x1U << CMU_PCLKCR2_CIC_PCE_Pos)CMU_PCLKCR2_WWDT_PCE_Pos 7žCMU_PCLKCR2_WWDT_PCE_Msk (0x1U << CMU_PCLKCR2_WWDT_PCE_Pos) CMU_PCLKCR2_RAMBIST_PCE_Pos 6¡CMU_PCLKCR2_RAMBIST_PCE_Msk (0x1U << CMU_PCLKCR2_RAMBIST_PCE_Pos)£CMU_PCLKCR2_NVM_PCE_Pos 5¤CMU_PCLKCR2_NVM_PCE_Msk (0x1U << CMU_PCLKCR2_NVM_PCE_Pos)¦CMU_PCLKCR2_DMA_PCE_Pos 4§CMU_PCLKCR2_DMA_PCE_Msk (0x1U << CMU_PCLKCR2_DMA_PCE_Pos)©CMU_PCLKCR2_LCD_PCE_Pos 3ªCMU_PCLKCR2_LCD_PCE_Msk (0x1U << CMU_PCLKCR2_LCD_PCE_Pos)¬CMU_PCLKCR2_AES_PCE_Pos 2­CMU_PCLKCR2_AES_PCE_Msk (0x1U << CMU_PCLKCR2_AES_PCE_Pos)¯CMU_PCLKCR2_TRNG_PCE_Pos 1°CMU_PCLKCR2_TRNG_PCE_Msk (0x1U << CMU_PCLKCR2_TRNG_PCE_Pos)²CMU_PCLKCR2_CRC_PCE_Pos 0³CMU_PCLKCR2_CRC_PCE_Msk (0x1U << CMU_PCLKCR2_CRC_PCE_Pos)µCMU_PCLKCR3_I2C1_PCE_Pos 25¶CMU_PCLKCR3_I2C1_PCE_Msk (0x1U << CMU_PCLKCR3_I2C1_PCE_Pos)¸CMU_PCLKCR3_I2C0_PCE_Pos 24¹CMU_PCLKCR3_I2C0_PCE_Msk (0x1U << CMU_PCLKCR3_I2C0_PCE_Pos)»CMU_PCLKCR3_LPUART1_PCE_Pos 18¼CMU_PCLKCR3_LPUART1_PCE_Msk (0x1U << CMU_PCLKCR3_LPUART1_PCE_Pos)¾CMU_PCLKCR3_U7816_PCE_Pos 16¿CMU_PCLKCR3_U7816_PCE_Msk (0x1U << CMU_PCLKCR3_U7816_PCE_Pos)ÁCMU_PCLKCR3_LPUART0_PCE_Pos 15ÂCMU_PCLKCR3_LPUART0_PCE_Msk (0x1U << CMU_PCLKCR3_LPUART0_PCE_Pos)ÄCMU_PCLKCR3_UICR_PCE_Pos 14ÅCMU_PCLKCR3_UICR_PCE_Msk (0x1U << CMU_PCLKCR3_UICR_PCE_Pos)ÇCMU_PCLKCR3_UART5_PCE_Pos 13ÈCMU_PCLKCR3_UART5_PCE_Msk (0x1U << CMU_PCLKCR3_UART5_PCE_Pos)ÊCMU_PCLKCR3_UART4_PCE_Pos 12ËCMU_PCLKCR3_UART4_PCE_Msk (0x1U << CMU_PCLKCR3_UART4_PCE_Pos)ÍCMU_PCLKCR3_UART3_PCE_Pos 11ÎCMU_PCLKCR3_UART3_PCE_Msk (0x1U << CMU_PCLKCR3_UART3_PCE_Pos)ÐCMU_PCLKCR3_UART2_PCE_Pos 10ÑCMU_PCLKCR3_UART2_PCE_Msk (0x1U << CMU_PCLKCR3_UART2_PCE_Pos)ÓCMU_PCLKCR3_UART1_PCE_Pos 9ÔCMU_PCLKCR3_UART1_PCE_Msk (0x1U << CMU_PCLKCR3_UART1_PCE_Pos)ÖCMU_PCLKCR3_UART0_PCE_Pos 8×CMU_PCLKCR3_UART0_PCE_Msk (0x1U << CMU_PCLKCR3_UART0_PCE_Pos)ÙCMU_PCLKCR3_QSPI_PCE_Pos 7ÚCMU_PCLKCR3_QSPI_PCE_Msk (0x1U << CMU_PCLKCR3_QSPI_PCE_Pos)ÜCMU_PCLKCR3_SPI4_PCE_Pos 4ÝCMU_PCLKCR3_SPI4_PCE_Msk (0x1U << CMU_PCLKCR3_SPI4_PCE_Pos)ßCMU_PCLKCR3_SPI3_PCE_Pos 3àCMU_PCLKCR3_SPI3_PCE_Msk (0x1U << CMU_PCLKCR3_SPI3_PCE_Pos)âCMU_PCLKCR3_SPI2_PCE_Pos 2ãCMU_PCLKCR3_SPI2_PCE_Msk (0x1U << CMU_PCLKCR3_SPI2_PCE_Pos)åCMU_PCLKCR3_SPI1_PCE_Pos 1æCMU_PCLKCR3_SPI1_PCE_Msk (0x1U << CMU_PCLKCR3_SPI1_PCE_Pos)èCMU_PCLKCR3_SPI0_PCE_Pos 0éCMU_PCLKCR3_SPI0_PCE_Msk (0x1U << CMU_PCLKCR3_SPI0_PCE_Pos)ëCMU_PCLKCR4_ET4_PCE_Pos 6ìCMU_PCLKCR4_ET4_PCE_Msk (0x1U << CMU_PCLKCR4_ET4_PCE_Pos)îCMU_PCLKCR4_ET3_PCE_Pos 5ïCMU_PCLKCR4_ET3_PCE_Msk (0x1U << CMU_PCLKCR4_ET3_PCE_Pos)ñCMU_PCLKCR4_ET2_PCE_Pos 4òCMU_PCLKCR4_ET2_PCE_Msk (0x1U << CMU_PCLKCR4_ET2_PCE_Pos)ôCMU_PCLKCR4_ET1_PCE_Pos 3õCMU_PCLKCR4_ET1_PCE_Msk (0x1U << CMU_PCLKCR4_ET1_PCE_Pos)÷CMU_PCLKCR4_BT2_PCE_Pos 2øCMU_PCLKCR4_BT2_PCE_Msk (0x1U << CMU_PCLKCR4_BT2_PCE_Pos)úCMU_PCLKCR4_BT1_PCE_Pos 1ûCMU_PCLKCR4_BT1_PCE_Msk (0x1U << CMU_PCLKCR4_BT1_PCE_Pos)ýCMU_PCLKCR4_BSTIM_PCE_Pos 0þCMU_PCLKCR4_BSTIM_PCE_Msk (0x1U << CMU_PCLKCR4_BSTIM_PCE_Pos)€CMU_OPCCR1_EXTICKE_Pos 31CMU_OPCCR1_EXTICKE_Msk (0x1U << CMU_OPCCR1_EXTICKE_Pos)ƒCMU_OPCCR1_EXTICKSEL_Pos 30„CMU_OPCCR1_EXTICKSEL_Msk (0x1U << CMU_OPCCR1_EXTICKSEL_Pos)…CMU_OPCCR1_EXTICKSEL_LSCLK (0x1U << CMU_OPCCR1_EXTICKSEL_Pos)†CMU_OPCCR1_EXTICKSEL_HCLK (0x0U << CMU_OPCCR1_EXTICKSEL_Pos)ˆCMU_OPCCR1_LPUART1CKE_Pos 29‰CMU_OPCCR1_LPUART1CKE_Msk (0x1U << CMU_OPCCR1_LPUART1CKE_Pos)‹CMU_OPCCR1_LPUART0CKE_Pos 28ŒCMU_OPCCR1_LPUART0CKE_Msk (0x1U << CMU_OPCCR1_LPUART0CKE_Pos)ŽCMU_OPCCR1_LPUART1CKS_Pos 26“CMU_OPCCR1_LPUART1CKS_Msk (0x3U << CMU_OPCCR1_LPUART1CKS_Pos)”CMU_OPCCR1_LPUART1CKS_LSCLK (0x0U << CMU_OPCCR1_LPUART1CKS_Pos)•CMU_OPCCR1_LPUART1CKS_RCHF (0x1U << CMU_OPCCR1_LPUART1CKS_Pos)—CMU_OPCCR1_LPUART0CKS_Pos 24œCMU_OPCCR1_LPUART0CKS_Msk (0x3U << CMU_OPCCR1_LPUART0CKS_Pos)CMU_OPCCR1_LPUART0CKS_LSCLK (0x0U << CMU_OPCCR1_LPUART0CKS_Pos)žCMU_OPCCR1_LPUART0CKS_RCHF (0x1U << CMU_OPCCR1_LPUART0CKS_Pos) CMU_OPCCR1_I2C1CKE_Pos 21¡CMU_OPCCR1_I2C1CKE_Msk (0x1U << CMU_OPCCR1_I2C1CKE_Pos)£CMU_OPCCR1_I2C0CKE_Pos 20¤CMU_OPCCR1_I2C0CKE_Msk (0x1U << CMU_OPCCR1_I2C0CKE_Pos)¦CMU_OPCCR1_I2C1CKS_Pos 18«CMU_OPCCR1_I2C1CKS_Msk (0x3U << CMU_OPCCR1_I2C1CKS_Pos)¬CMU_OPCCR1_I2C1CKS_APBCLK (0x0U << CMU_OPCCR1_I2C1CKS_Pos)­CMU_OPCCR1_I2C1CKS_RCHF (0x1U << CMU_OPCCR1_I2C1CKS_Pos)®CMU_OPCCR1_I2C1CKS_SYSCLK (0x2U << CMU_OPCCR1_I2C1CKS_Pos)°CMU_OPCCR1_I2C0CKS_Pos 16µCMU_OPCCR1_I2C0CKS_Msk (0x3U << CMU_OPCCR1_I2C0CKS_Pos)¶CMU_OPCCR1_I2C0CKS_APBCLK (0x0U << CMU_OPCCR1_I2C0CKS_Pos)·CMU_OPCCR1_I2C0CKS_RCHF (0x1U << CMU_OPCCR1_I2C0CKS_Pos)¸CMU_OPCCR1_I2C0CKS_SYSCLK (0x2U << CMU_OPCCR1_I2C0CKS_Pos)ºCMU_OPCCR1_UART1CKE_Pos 9»CMU_OPCCR1_UART1CKE_Msk (0x1U << CMU_OPCCR1_UART1CKE_Pos)½CMU_OPCCR1_UART0CKE_Pos 8¾CMU_OPCCR1_UART0CKE_Msk (0x1U << CMU_OPCCR1_UART0CKE_Pos)ÀCMU_OPCCR1_UART1CKS_Pos 2ÅCMU_OPCCR1_UART1CKS_Msk (0x3U << CMU_OPCCR1_UART1CKS_Pos)ÆCMU_OPCCR1_UART1CKS_APBCLK (0x0U << CMU_OPCCR1_UART1CKS_Pos)ÇCMU_OPCCR1_UART1CKS_RCHF (0x1U << CMU_OPCCR1_UART1CKS_Pos)ÈCMU_OPCCR1_UART1CKS_SYSCLK (0x2U << CMU_OPCCR1_UART1CKS_Pos)ÊCMU_OPCCR1_UART0CKS_Pos 0ÏCMU_OPCCR1_UART0CKS_Msk (0x3U << CMU_OPCCR1_UART0CKS_Pos)ÐCMU_OPCCR1_UART0CKS_APBCLK (0x0U << CMU_OPCCR1_UART0CKS_Pos)ÑCMU_OPCCR1_UART0CKS_RCHF (0x1U << CMU_OPCCR1_UART0CKS_Pos)ÒCMU_OPCCR1_UART0CKS_SYSCLK (0x2U << CMU_OPCCR1_UART0CKS_Pos)ÔCMU_OPCCR2_RNGPRSC_Pos 28ÜCMU_OPCCR2_RNGPRSC_Msk (0x7U << CMU_OPCCR2_RNGPRSC_Pos)ÝCMU_OPCCR2_RNGPRSC_DIV1 (0x0U << CMU_OPCCR2_RNGPRSC_Pos)ÞCMU_OPCCR2_RNGPRSC_DIV2 (0x1U << CMU_OPCCR2_RNGPRSC_Pos)ßCMU_OPCCR2_RNGPRSC_DIV4 (0x2U << CMU_OPCCR2_RNGPRSC_Pos)àCMU_OPCCR2_RNGPRSC_DIV8 (0x3U << CMU_OPCCR2_RNGPRSC_Pos)áCMU_OPCCR2_RNGPRSC_DIV16 (0x4U << CMU_OPCCR2_RNGPRSC_Pos)âCMU_OPCCR2_RNGPRSC_DIV32 (0x5U << CMU_OPCCR2_RNGPRSC_Pos)äCMU_OPCCR2_NVMCKE_Pos 22åCMU_OPCCR2_NVMCKE_Msk (0x1U << CMU_OPCCR2_NVMCKE_Pos)çCMU_OPCCR2_RNGCKE_Pos 21èCMU_OPCCR2_RNGCKE_Msk (0x1U << CMU_OPCCR2_RNGCKE_Pos)êCMU_OPCCR2_LPTCKE_Pos 12ëCMU_OPCCR2_LPTCKE_Msk (0x1U << CMU_OPCCR2_LPTCKE_Pos)íCMU_OPCCR2_LPTCKS_Pos 8òCMU_OPCCR2_LPTCKS_Msk (0x3U << CMU_OPCCR2_LPTCKS_Pos)óCMU_OPCCR2_LPTCKS_APBCLK (0x0U << CMU_OPCCR2_LPTCKS_Pos)ôCMU_OPCCR2_LPTCKS_LSCLK (0x1U << CMU_OPCCR2_LPTCKS_Pos)õCMU_OPCCR2_LPTCKS_RCLP (0x2U << CMU_OPCCR2_LPTCKS_Pos)öCMU_OPCCR2_LPTCKS_PLL_L (0x3U << CMU_OPCCR2_LPTCKS_Pos)øCMU_OPCCR2_BSTCKE_Pos 4ùCMU_OPCCR2_BSTCKE_Msk (0x1U << CMU_OPCCR2_BSTCKE_Pos)ûCMU_OPCCR2_BSTCKS_Pos 0€CMU_OPCCR2_BSTCKS_Msk (0x3U << CMU_OPCCR2_BSTCKS_Pos)CMU_OPCCR2_BSTCKS_APBCLK (0x0U << CMU_OPCCR2_BSTCKS_Pos)‚CMU_OPCCR2_BSTCKS_LSCLK (0x1U << CMU_OPCCR2_BSTCKS_Pos)ƒCMU_OPCCR2_BSTCKS_RCLP (0x2U << CMU_OPCCR2_BSTCKS_Pos)„CMU_OPCCR2_BSTCKS_SYSCLK (0x3U << CMU_OPCCR2_BSTCKS_Pos)£COMPCLK (0x01000000 + CMU_PCLKCR1_COMP_PCE_Pos)¤SVDCLK (0x01000000 + CMU_PCLKCR1_SVD_PCE_Pos)¥PADCLK (0x01000000 + CMU_PCLKCR1_PAD_PCE_Pos)¦ANACCLK (0x01000000 + CMU_PCLKCR1_ANAC_PCE_Pos)§IWDTCLK (0x01000000 + CMU_PCLKCR1_IWDT_PCE_Pos)¨SCUCLK (0x01000000 + CMU_PCLKCR1_SCU_PCE_Pos)©PMUCLK (0x01000000 + CMU_PCLKCR1_PMU_PCE_Pos)ªRTCCLK (0x01000000 + CMU_PCLKCR1_RTC_PCE_Pos)«LPTCLK (0x01000000 + CMU_PCLKCR1_LPT_PCE_Pos)®PAECLK (0x02000000 + CMU_PCLKCR2_PAE_PCE_Pos)¯SHACLK (0x02000000 + CMU_PCLKCR2_SHA_PCE_Pos)°CICCLK (0x02000000 + CMU_PCLKCR2_CIC_PCE_Pos)±WWDTCLK (0x02000000 + CMU_PCLKCR2_WWDT_PCE_Pos)²RAMBISTCLK (0x02000000 + CMU_PCLKCR2_RAMBIST_PCE_Pos)³FLASHCLK (0x02000000 + CMU_PCLKCR2_NVM_PCE_Pos)´DMACLK (0x02000000 + CMU_PCLKCR2_DMA_PCE_Pos)µLCDCLK (0x02000000 + CMU_PCLKCR2_LCD_PCE_Pos)¶AESCLK (0x02000000 + CMU_PCLKCR2_AES_PCE_Pos)·TRNGCLK (0x02000000 + CMU_PCLKCR2_TRNG_PCE_Pos)¸CRCCLK (0x02000000 + CMU_PCLKCR2_CRC_PCE_Pos)ºI2C1CLK (0x03000000 + CMU_PCLKCR3_I2C1_PCE_Pos)»I2C0CLK (0x03000000 + CMU_PCLKCR3_I2C0_PCE_Pos)¼LPUART1CLK (0x03000000 + CMU_PCLKCR3_LPUART1_PCE_Pos)½U7816CLK (0x03000000 + CMU_PCLKCR3_U7816_PCE_Pos)¾LPUART0CLK (0x03000000 + CMU_PCLKCR3_LPUART0_PCE_Pos)¿UARTIRCLK (0x03000000 + CMU_PCLKCR3_UICR_PCE_Pos)ÀUART5CLK (0x03000000 + CMU_PCLKCR3_UART5_PCE_Pos)ÁUART4CLK (0x03000000 + CMU_PCLKCR3_UART4_PCE_Pos)ÂUART3CLK (0x03000000 + CMU_PCLKCR3_UART3_PCE_Pos)ÃUART2CLK (0x03000000 + CMU_PCLKCR3_UART2_PCE_Pos)ÄUART1CLK (0x03000000 + CMU_PCLKCR3_UART1_PCE_Pos)ÅUART0CLK (0x03000000 + CMU_PCLKCR3_UART0_PCE_Pos)ÆQSPICLK (0x03000000 + CMU_PCLKCR3_QSPI_PCE_Pos)ÇSPI4CLK (0x03000000 + CMU_PCLKCR3_SPI4_PCE_Pos)ÈSPI3CLK (0x03000000 + CMU_PCLKCR3_SPI3_PCE_Pos)ÉSPI2CLK (0x03000000 + CMU_PCLKCR3_SPI2_PCE_Pos)ÊSPI1CLK (0x03000000 + CMU_PCLKCR3_SPI1_PCE_Pos)ËSPI0CLK (0x03000000 + CMU_PCLKCR3_SPI0_PCE_Pos)ÎET4CLK (0x04000000 + CMU_PCLKCR4_ET4_PCE_Pos)ÏET3CLK (0x04000000 + CMU_PCLKCR4_ET3_PCE_Pos)ÐET2CLK (0x04000000 + CMU_PCLKCR4_ET2_PCE_Pos)ÑET1CLK (0x04000000 + CMU_PCLKCR4_ET1_PCE_Pos)ÒBT2CLK (0x04000000 + CMU_PCLKCR4_BT2_PCE_Pos)ÓBT1CLK (0x04000000 + CMU_PCLKCR4_BT1_PCE_Pos)ÔBSTIMCLK (0x04000000 + CMU_PCLKCR4_BSTIM_PCE_Pos)`T ..\Drivers\..\Core\Include\fm33a0xxev_cmu.hFM33A0XXEV.hð


..\Drivers\fm33a0xxev_cmu.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM*àFSELf#RCHFEN#PCMU_RCHF_InitTypeDef½)*¢PLLLDBf#PLLL_EN#PCMU_PLL_L_InitTypeDefü/*PLLHDBf#REFPRSCf#PLLH_OSELf#PLLH_INSELf#PLLH_EN#PCMU_PLL_H_InitTypeDef?9*ˆSYSCLKSELf#AHBPRESf#APBPRESf#SLP_ENEXTI#PCMU_SYSCLK_InitTypeDefºC*ÛSYSCLK_Frequencyf#AHBCLK_Frequencyf#APBCLK_Frequencyf#RCHF_Frequencyf#PLL_H_Frequencyf#XTHF_Frequencyf#LSCLK_Frequencyf#PCMU_ClocksType&N‹Œ__FM33A0XXEV_RTC_H /RTC_WRITE_ENABLE ((uint32_t)0xACACACAC)0RTC_WRITE_DISABLE ((uint32_t)0x55AA55AA)2RTC_WER_RTCWE_Pos 04RTC_WER_RTCWE_Msk (0x1U << RTC_WER_RTCWE_Pos)6RTC_IER_ADJ_IE_Pos 129RTC_IER_ADJ_IE_Msk (0x1U << RTC_IER_ADJ_IE_Pos)=RTC_IER_ALARM_IE_Pos 11@RTC_IER_ALARM_IE_Msk (0x1U << RTC_IER_ALARM_IE_Pos)DRTC_IER_1KHZ_IE_Pos 10GRTC_IER_1KHZ_IE_Msk (0x1U << RTC_IER_1KHZ_IE_Pos)KRTC_IER_256HZ_IE_Pos 9NRTC_IER_256HZ_IE_Msk (0x1U << RTC_IER_256HZ_IE_Pos)RRTC_IER_64HZ_IE_Pos 8URTC_IER_64HZ_IE_Msk (0x1U << RTC_IER_64HZ_IE_Pos)YRTC_IER_16HZ_IE_Pos 7\RTC_IER_16HZ_IE_Msk (0x1U << RTC_IER_16HZ_IE_Pos)`RTC_IER_8HZ_IE_Pos 6cRTC_IER_8HZ_IE_Msk (0x1U << RTC_IER_8HZ_IE_Pos)gRTC_IER_4HZ_IE_Pos 5jRTC_IER_4HZ_IE_Msk (0x1U << RTC_IER_4HZ_IE_Pos)nRTC_IER_2HZ_IE_Pos 4qRTC_IER_2HZ_IE_Msk (0x1U << RTC_IER_2HZ_IE_Pos)uRTC_IER_SEC_IE_Pos 3xRTC_IER_SEC_IE_Msk (0x1U << RTC_IER_SEC_IE_Pos)|RTC_IER_MIN_IE_Pos 2RTC_IER_MIN_IE_Msk (0x1U << RTC_IER_MIN_IE_Pos)ƒRTC_IER_HOUR_IE_Pos 1†RTC_IER_HOUR_IE_Msk (0x1U << RTC_IER_HOUR_IE_Pos)ŠRTC_IER_DATE_IE_Pos 0RTC_IER_DATE_IE_Msk (0x1U << RTC_IER_DATE_IE_Pos)‘RTC_ISR_ADJ_IF_Pos 12”RTC_ISR_ADJ_IF_Msk (0x1U << RTC_ISR_ADJ_IF_Pos)–RTC_ISR_ALARM_IF_Pos 11™RTC_ISR_ALARM_IF_Msk (0x1U << RTC_ISR_ALARM_IF_Pos)›RTC_ISR_1KHZ_IF_Pos 10žRTC_ISR_1KHZ_IF_Msk (0x1U << RTC_ISR_1KHZ_IF_Pos) RTC_ISR_256HZ_IF_Pos 9£RTC_ISR_256HZ_IF_Msk (0x1U << RTC_ISR_256HZ_IF_Pos)¦RTC_ISR_64HZ_IF_Pos 8©RTC_ISR_64HZ_IF_Msk (0x1U << RTC_ISR_64HZ_IF_Pos)¬RTC_ISR_16HZ_IF_Pos 7¯RTC_ISR_16HZ_IF_Msk (0x1U << RTC_ISR_16HZ_IF_Pos)±RTC_ISR_8HZ_IF_Pos 6´RTC_ISR_8HZ_IF_Msk (0x1U << RTC_ISR_8HZ_IF_Pos)¶RTC_ISR_4HZ_IF_Pos 5¹RTC_ISR_4HZ_IF_Msk (0x1U << RTC_ISR_4HZ_IF_Pos)»RTC_ISR_2HZ_IF_Pos 4¾RTC_ISR_2HZ_IF_Msk (0x1U << RTC_ISR_2HZ_IF_Pos)ÀRTC_ISR_SEC_IF_Pos 3ÃRTC_ISR_SEC_IF_Msk (0x1U << RTC_ISR_SEC_IF_Pos)ÅRTC_ISR_MIN_IF_Pos 2ÈRTC_ISR_MIN_IF_Msk (0x1U << RTC_ISR_MIN_IF_Pos)ÊRTC_ISR_HOUR_IF_Pos 1ÍRTC_ISR_HOUR_IF_Msk (0x1U << RTC_ISR_HOUR_IF_Pos)ÏRTC_ISR_DATE_IF_Pos 0ÒRTC_ISR_DATE_IF_Msk (0x1U << RTC_ISR_DATE_IF_Pos)ÔRTC_BCDSEC_BCDSEC_Pos 0ÕRTC_BCDSEC_BCDSEC_Msk (0x7fU << RTC_BCDSEC_BCDSEC_Pos)×RTC_BCDMIN_BCDMIN_Pos 0ØRTC_BCDMIN_BCDMIN_Msk (0x7fU << RTC_BCDMIN_BCDMIN_Pos)ÚRTC_BCDHOUR_BCDHOUR_Pos 0ÛRTC_BCDHOUR_BCDHOUR_Msk (0x3fU << RTC_BCDHOUR_BCDHOUR_Pos)ÝRTC_BCDDATE_BCDDATE_Pos 0ÞRTC_BCDDATE_BCDDATE_Msk (0x3fU << RTC_BCDDATE_BCDDATE_Pos)àRTC_BCDWEEK_BCDWEEK_Pos 0áRTC_BCDWEEK_BCDWEEK_Msk (0x7U << RTC_BCDWEEK_BCDWEEK_Pos)ãRTC_BCDMONTH_BCDMONTH_Pos 0äRTC_BCDMONTH_BCDMONTH_Msk (0x1fU << RTC_BCDMONTH_BCDMONTH_Pos)æRTC_BCDYEAR_BCDYEAR_Pos 0çRTC_BCDYEAR_BCDYEAR_Msk (0xffU << RTC_BCDYEAR_BCDYEAR_Pos)éRTC_ALARM_ALMEN_Pos 31ìRTC_ALARM_ALMEN_Msk (0x1U << RTC_ALARM_ALMEN_Pos)ðRTC_ALARM_ALARMHOUR_Pos 16ñRTC_ALARM_ALARMHOUR_Msk (0x3fU << RTC_ALARM_ALARMHOUR_Pos)óRTC_ALARM_ALARMMIN_Pos 8ôRTC_ALARM_ALARMMIN_Msk (0x7fU << RTC_ALARM_ALARMMIN_Pos)öRTC_ALARM_ALARMSEC_Pos 0÷RTC_ALARM_ALARMSEC_Msk (0x7fU << RTC_ALARM_ALARMSEC_Pos)ùRTC_TMSEL_FSEL_Pos 0ŠRTC_TMSEL_FSEL_Msk (0xfU << RTC_TMSEL_FSEL_Pos)‹RTC_TMSEL_FSEL_PLL1HZ (0x0U << RTC_TMSEL_FSEL_Pos)ŒRTC_TMSEL_FSEL_PLLD1HZ (0x1U << RTC_TMSEL_FSEL_Pos)RTC_TMSEL_FSEL_SECOND (0x2U << RTC_TMSEL_FSEL_Pos)ŽRTC_TMSEL_FSEL_MINUTE (0x3U << RTC_TMSEL_FSEL_Pos)RTC_TMSEL_FSEL_HOUR (0x4U << RTC_TMSEL_FSEL_Pos)RTC_TMSEL_FSEL_DAY (0x5U << RTC_TMSEL_FSEL_Pos)‘RTC_TMSEL_FSEL_ALARM (0x6U << RTC_TMSEL_FSEL_Pos)’RTC_TMSEL_FSEL_256S (0x7U << RTC_TMSEL_FSEL_Pos)“RTC_TMSEL_FSEL_PLLD1HZREV (0x8U << RTC_TMSEL_FSEL_Pos)”RTC_TMSEL_FSEL_SECONDREV (0x9U << RTC_TMSEL_FSEL_Pos)•RTC_TMSEL_FSEL_MINUTEREV (0xaU << RTC_TMSEL_FSEL_Pos)–RTC_TMSEL_FSEL_HOURREV (0xbU << RTC_TMSEL_FSEL_Pos)—RTC_TMSEL_FSEL_DAYREV (0xcU << RTC_TMSEL_FSEL_Pos)˜RTC_TMSEL_FSEL_ALARMREV (0xdU << RTC_TMSEL_FSEL_Pos)™RTC_TMSEL_FSEL_PLL1HZREV (0xeU << RTC_TMSEL_FSEL_Pos)šRTC_TMSEL_FSEL_SECONDRUN (0xfU << RTC_TMSEL_FSEL_Pos) RTC_ADJUST_ADJUST_Pos 0¡RTC_ADJUST_ADJUST_Msk (0x1fffU << RTC_ADJUST_ADJUST_Pos)£RTC_ADSIGN_ADSIGN_Pos 0¦RTC_ADSIGN_ADSIGN_Msk (0x1U << RTC_ADSIGN_ADSIGN_Pos)§RTC_ADSIGN_ADSIGN_INCREASE (0x0U << RTC_ADSIGN_ADSIGN_Pos)¨RTC_ADSIGN_ADSIGN_DECREASE (0x1U << RTC_ADSIGN_ADSIGN_Pos)ªRTC_VCAL_PR1SEN_Pos 0­RTC_VCAL_PR1SEN_Msk (0x1U << RTC_VCAL_PR1SEN_Pos)±RTC_MSCNT_MSCNT_Pos 0µRTC_MSCNT_MSCNT_Msk (0xffU << RTC_MSCNT_MSCNT_Pos)·RTC_CALSTEP_CALSTEP_Pos 0»RTC_CALSTEP_CALSTEP_Msk (0x1U << RTC_CALSTEP_CALSTEP_Pos)¼RTC_CALSTEP_CALSTEP_006PPM (0x2U << RTC_CALSTEP_CALSTEP_Pos)½RTC_CALSTEP_CALSTEP_0119PPM (0x1U << RTC_CALSTEP_CALSTEP_Pos)¾RTC_CALSTEP_CALSTEP_0238PPM (0x0U << RTC_CALSTEP_CALSTEP_Pos)ÀRTC_ADCNT_ADJCNT_Pos 0ÁRTC_ADCNT_ADJCNT_Msk (0x1ffU << RTC_ADCNT_ADJCNT_Pos)ÃRTC_SSR_SSR_Pos 0ÅRTC_SSR_SSR_Msk (0x3fU << RTC_SSR_SSR_Pos)ÇRTC_SSA_SSAEN_Pos 7ÊRTC_SSA_SSAEN_Msk (0x1U << RTC_SSA_SSAEN_Pos)ÎRTC_SSA_SS_ALARM_Pos 0ÐRTC_SSA_SS_ALARM_Msk (0x3fU << RTC_SSA_SS_ALARM_Pos)ÒRTC_DTR_DUTY_Pos 0ÓRTC_DTR_DUTY_Msk (0x1ffffffU << RTC_DTR_DUTY_Pos)ÕRTC_CR_RTC_EN_Pos 0ÚRTC_CR_RTC_EN_Msk (0x1U << RTC_CR_RTC_EN_Pos)`T ..\Drivers\..\Core\Include\fm33a0xxev_rtc.hFM33A0XXEV.h°


..\Drivers\fm33a0xxev_rtc.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM*©Year8#Month8#Date8#Hour8#Minute8#Second8#Week8#PRTC_TimeDateTypeDef½#PRTC_StampTmieTypeDef½#*“Hour8#Minute8#Second8#PRTC_AlarmTmieTypeDef`+‘__FM33A0XXEV_DBG_H DBG_CR_DBG_LPT_STOP_Pos 15DBG_CR_DBG_LPT_STOP_Msk (0x1U << DBG_CR_DBG_LPT_STOP_Pos) DBG_CR_DBG_BST_STOP_Pos 14#DBG_CR_DBG_BST_STOP_Msk (0x1U << DBG_CR_DBG_BST_STOP_Pos)'DBG_CR_DBG_ET4_STOP_Pos 13*DBG_CR_DBG_ET4_STOP_Msk (0x1U << DBG_CR_DBG_ET4_STOP_Pos).DBG_CR_DBG_ET3_STOP_Pos 121DBG_CR_DBG_ET3_STOP_Msk (0x1U << DBG_CR_DBG_ET3_STOP_Pos)5DBG_CR_DBG_ET2_STOP_Pos 118DBG_CR_DBG_ET2_STOP_Msk (0x1U << DBG_CR_DBG_ET2_STOP_Pos)<DBG_CR_DBG_ET1_STOP_Pos 10?DBG_CR_DBG_ET1_STOP_Msk (0x1U << DBG_CR_DBG_ET1_STOP_Pos)CDBG_CR_DBG_BT2_STOP_Pos 9FDBG_CR_DBG_BT2_STOP_Msk (0x1U << DBG_CR_DBG_BT2_STOP_Pos)JDBG_CR_DBG_BT1_STOP_Pos 8MDBG_CR_DBG_BT1_STOP_Msk (0x1U << DBG_CR_DBG_BT1_STOP_Pos)QDBG_CR_DBG_WWDT_STOP_Pos 1TDBG_CR_DBG_WWDT_STOP_Msk (0x1U << DBG_CR_DBG_WWDT_STOP_Pos)XDBG_CR_DBG_IWDT_STOP_Pos 0[DBG_CR_DBG_IWDT_STOP_Msk (0x1U << DBG_CR_DBG_IWDT_STOP_Pos)_DBG_HDFR_DABORT_ADDR_FLAG_Pos 6bDBG_HDFR_DABORT_ADDR_FLAG_Msk (0x1U << DBG_HDFR_DABORT_ADDR_FLAG_Pos)dDBG_HDFR_DABORT_RESP_FLAG_Pos 5gDBG_HDFR_DABORT_RESP_FLAG_Msk (0x1U << DBG_HDFR_DABORT_RESP_FLAG_Pos)iDBG_HDFR_SVCUNDEF_FLAG_Pos 4nDBG_HDFR_SVCUNDEF_FLAG_Msk (0x1U << DBG_HDFR_SVCUNDEF_FLAG_Pos)pDBG_HDFR_BKPT_FLAG_Pos 3sDBG_HDFR_BKPT_FLAG_Msk (0x1U << DBG_HDFR_BKPT_FLAG_Pos)uDBG_HDFR_TBIT_FLAG_Pos 2xDBG_HDFR_TBIT_FLAG_Msk (0x1U << DBG_HDFR_TBIT_FLAG_Pos)zDBG_HDFR_SPECIAL_OP_FLAG_Pos 1}DBG_HDFR_SPECIAL_OP_FLAG_Msk (0x1U << DBG_HDFR_SPECIAL_OP_FLAG_Pos)DBG_HDFR_HDF_REQUEST_FLAG_Pos 0‚DBG_HDFR_HDF_REQUEST_FLAG_Msk (0x1U << DBG_HDFR_HDF_REQUEST_FLAG_Pos)`T ..\Drivers\..\Core\Include\fm33a0xxev_dbg.hFM33A0XXEV.h¼


..\Drivers\fm33a0xxev_dbg.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM“”•__FM33A0XXEV_SPI_H SPIx_CR1_IOSWAP_Pos 11SPIx_CR1_IOSWAP_Msk (0x1U << SPIx_CR1_IOSWAP_Pos)SPIx_CR1_IOSWAP_DEFAULT (0x0U << SPIx_CR1_IOSWAP_Pos) SPIx_CR1_IOSWAP_EXCHANGE (0x1U << SPIx_CR1_IOSWAP_Pos)"SPIx_CR1_MSPA_Pos 10%SPIx_CR1_MSPA_Msk (0x1U << SPIx_CR1_MSPA_Pos)&SPIx_CR1_MSPA_DELAY (0x1U << SPIx_CR1_MSPA_Pos)'SPIx_CR1_MSPA_NORMAL (0x0U << SPIx_CR1_MSPA_Pos))SPIx_CR1_SSPA_Pos 9,SPIx_CR1_SSPA_Msk (0x1U << SPIx_CR1_SSPA_Pos)-SPIx_CR1_SSPA_EARLY (0x1U << SPIx_CR1_SSPA_Pos).SPIx_CR1_SSPA_NORMAL (0x0U << SPIx_CR1_SSPA_Pos)0SPIx_CR1_MM_Pos 81SPIx_CR1_MM_Msk (0x1U << SPIx_CR1_MM_Pos)2SPIx_CR1_MM_MASTER (0x1U << SPIx_CR1_MM_Pos)3SPIx_CR1_MM_SLAVE (0x0U << SPIx_CR1_MM_Pos)5SPIx_CR1_WAIT_Pos 66SPIx_CR1_WAIT_Msk (0x3U << SPIx_CR1_WAIT_Pos)7SPIx_CR1_WAIT_1WAIT (0x0U << SPIx_CR1_WAIT_Pos)8SPIx_CR1_WAIT_2WAIT (0x1U << SPIx_CR1_WAIT_Pos)9SPIx_CR1_WAIT_3WAIT (0x2U << SPIx_CR1_WAIT_Pos):SPIx_CR1_WAIT_4WAIT (0x3U << SPIx_CR1_WAIT_Pos)<SPIx_CR1_BAUD_Pos 3=SPIx_CR1_BAUD_Msk (0x7U << SPIx_CR1_BAUD_Pos)>SPIx_CR1_BAUD_DIV2 (0x0U << SPIx_CR1_BAUD_Pos)?SPIx_CR1_BAUD_DIV4 (0x1U << SPIx_CR1_BAUD_Pos)@SPIx_CR1_BAUD_DIV8 (0x2U << SPIx_CR1_BAUD_Pos)ASPIx_CR1_BAUD_DIV16 (0x3U << SPIx_CR1_BAUD_Pos)BSPIx_CR1_BAUD_DIV32 (0x4U << SPIx_CR1_BAUD_Pos)CSPIx_CR1_BAUD_DIV64 (0x5U << SPIx_CR1_BAUD_Pos)DSPIx_CR1_BAUD_DIV128 (0x6U << SPIx_CR1_BAUD_Pos)ESPIx_CR1_BAUD_DIV256 (0x7U << SPIx_CR1_BAUD_Pos)GSPIx_CR1_LSBF_Pos 2HSPIx_CR1_LSBF_Msk (0x1U << SPIx_CR1_LSBF_Pos)ISPIx_CR1_LSBF_MSB (0x0U << SPIx_CR1_LSBF_Pos)JSPIx_CR1_LSBF_LSB (0x1U << SPIx_CR1_LSBF_Pos)LSPIx_CR1_CPHOL_Pos 1MSPIx_CR1_CPHOL_Msk (0x1U << SPIx_CR1_CPHOL_Pos)NSPIx_CR1_CPHOL_LOW (0x0U << SPIx_CR1_CPHOL_Pos)OSPIx_CR1_CPHOL_HIGH (0x1U << SPIx_CR1_CPHOL_Pos)QSPIx_CR1_CPHA_Pos 0RSPIx_CR1_CPHA_Msk (0x1U << SPIx_CR1_CPHA_Pos)SSPIx_CR1_CPHA_1CLOCK (0x0U << SPIx_CR1_CPHA_Pos)TSPIx_CR1_CPHA_2CLOCK (0x1U << SPIx_CR1_CPHA_Pos)VSPIx_CR2_DUMMY_EN_Pos 15ZSPIx_CR2_DUMMY_EN_Msk (0x1U << SPIx_CR2_DUMMY_EN_Pos)^SPIx_CR2_RXO_Pos 11aSPIx_CR2_RXO_Msk (0x1U << SPIx_CR2_RXO_Pos)eSPIx_CR2_DLEN_Pos 9jSPIx_CR2_DLEN_Msk (0x3U << SPIx_CR2_DLEN_Pos)kSPIx_CR2_DLEN_8BIT (0x0U << SPIx_CR2_DLEN_Pos)lSPIx_CR2_DLEN_16BIT (0x1U << SPIx_CR2_DLEN_Pos)mSPIx_CR2_DLEN_24BIT (0x2U << SPIx_CR2_DLEN_Pos)nSPIx_CR2_DLEN_32BIT (0x3U << SPIx_CR2_DLEN_Pos)pSPIx_CR2_HALFDUPLEX_Pos 8sSPIx_CR2_HALFDUPLEX_Msk (0x1U << SPIx_CR2_HALFDUPLEX_Pos)tSPIx_CR2_HALFDUPLEX_SPI (0x0U << SPIx_CR2_HALFDUPLEX_Pos)uSPIx_CR2_HALFDUPLEX_DCN (0x1U << SPIx_CR2_HALFDUPLEX_Pos)wSPIx_CR2_HD_RW_Pos 7zSPIx_CR2_HD_RW_Msk (0x1U << SPIx_CR2_HD_RW_Pos){SPIx_CR2_HD_RW_WRITE (0x0U << SPIx_CR2_HD_RW_Pos)|SPIx_CR2_HD_RW_READ (0x1U << SPIx_CR2_HD_RW_Pos)~SPIx_CR2_CMD8b_Pos 6SPIx_CR2_CMD8b_Msk (0x1U << SPIx_CR2_CMD8b_Pos)‚SPIx_CR2_CMD8b_8BIT (0x1U << SPIx_CR2_CMD8b_Pos)ƒSPIx_CR2_CMD8b_DLEN (0x0U << SPIx_CR2_CMD8b_Pos)…SPIx_CR2_SSNM_Pos 5ˆSPIx_CR2_SSNM_Msk (0x1U << SPIx_CR2_SSNM_Pos)‰SPIx_CR2_SSNM_HIGH (0x1U << SPIx_CR2_SSNM_Pos)ŠSPIx_CR2_SSNM_LOW (0x0U << SPIx_CR2_SSNM_Pos)ŒSPIx_CR2_TXO_AC_Pos 4SPIx_CR2_TXO_AC_Msk (0x1U << SPIx_CR2_TXO_AC_Pos)SPIx_CR2_TXO_Pos 3’SPIx_CR2_TXO_Msk (0x1U << SPIx_CR2_TXO_Pos)–SPIx_CR2_SSN_Pos 2˜SPIx_CR2_SSN_Msk (0x1U << SPIx_CR2_SSN_Pos)™SPIx_CR2_SSN_LOW (0x0U << SPIx_CR2_SSN_Pos)šSPIx_CR2_SSN_HIGH (0x1U << SPIx_CR2_SSN_Pos)œSPIx_CR2_SSNSEN_Pos 1ŸSPIx_CR2_SSNSEN_Msk (0x1U << SPIx_CR2_SSNSEN_Pos)£SPIx_CR2_SPIEN_Pos 0¤SPIx_CR2_SPIEN_Msk (0x1U << SPIx_CR2_SPIEN_Pos)¦SPIx_CR3_TXBFC_Pos 3§SPIx_CR3_TXBFC_Msk (0x1U << SPIx_CR3_TXBFC_Pos)©SPIx_CR3_RXBFC_Pos 2ªSPIx_CR3_RXBFC_Msk (0x1U << SPIx_CR3_RXBFC_Pos)¬SPIx_CR3_MERRC_Pos 1­SPIx_CR3_MERRC_Msk (0x1U << SPIx_CR3_MERRC_Pos)¯SPIx_CR3_SERRC_Pos 0°SPIx_CR3_SERRC_Msk (0x1U << SPIx_CR3_SERRC_Pos)²SPIx_IER_ERRIE_Pos 2³SPIx_IER_ERRIE_Msk (0x1U << SPIx_IER_ERRIE_Pos)µSPIx_IER_TXIE_Pos 1¶SPIx_IER_TXIE_Msk (0x1U << SPIx_IER_TXIE_Pos)¸SPIx_IER_RXIE_Pos 0¹SPIx_IER_RXIE_Msk (0x1U << SPIx_IER_RXIE_Pos)»SPIx_ISR_DCN_TX_Pos 12¿SPIx_ISR_DCN_TX_Msk (0x1U << SPIx_ISR_DCN_TX_Pos)ÀSPIx_ISR_DCN_TX_COMMAND (0x0U << SPIx_ISR_DCN_TX_Pos)ÁSPIx_ISR_DCN_TX_DATA (0x1U << SPIx_ISR_DCN_TX_Pos)ÃSPIx_ISR_RXCOL_Pos 10ÄSPIx_ISR_RXCOL_Msk (0x1U << SPIx_ISR_RXCOL_Pos)ÆSPIx_ISR_TXCOL_Pos 9ÇSPIx_ISR_TXCOL_Msk (0x1U << SPIx_ISR_TXCOL_Pos)ÉSPIx_ISR_BUSY_Pos 8ÌSPIx_ISR_BUSY_Msk (0x1U << SPIx_ISR_BUSY_Pos)ÎSPIx_ISR_MERR_Pos 6ÐSPIx_ISR_MERR_Msk (0x1U << SPIx_ISR_MERR_Pos)ÒSPIx_ISR_SERR_Pos 5ÔSPIx_ISR_SERR_Msk (0x1U << SPIx_ISR_SERR_Pos)ÖSPIx_ISR_TXBE_Pos 1ÙSPIx_ISR_TXBE_Msk (0x1U << SPIx_ISR_TXBE_Pos)ÛSPIx_ISR_RXBF_Pos 0ÞSPIx_ISR_RXBF_Msk (0x1U << SPIx_ISR_RXBF_Pos)àSPIx_TXBUF_TXBUF_Pos 0áSPIx_TXBUF_TXBUF_Msk (0xffffffffU << SPIx_TXBUF_TXBUF_Pos)ãSPIx_RXBUF_RXBUF_Pos 0äSPIx_RXBUF_RXBUF_Msk (0xffffffffU << SPIx_RXBUF_RXBUF_Pos)`T ..\Drivers\..\Core\Include\fm33a0xxev_spi.hFM33A0XXEV.h¼


..\Drivers\fm33a0xxev_spi.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM—˜™__FM33A0XXEV_RNG_H RNG_CR_EN_Pos 0RNG_CR_EN_Msk (0x1U << RNG_CR_EN_Pos) RNG_DOR_OUT_Pos 0"RNG_DOR_OUT_Msk (0xffffffffU << RNG_DOR_OUT_Pos)$RNG_SR_LFSREN_Pos 1(RNG_SR_LFSREN_Msk (0x1U << RNG_SR_LFSREN_Pos)-RNG_SR_RNF_Pos 00RNG_SR_RNF_Msk (0x1U << RNG_SR_RNF_Pos)2RNG_CRC_CR_CRCEN_Pos 05RNG_CRC_CR_CRCEN_Msk (0x1U << RNG_CRC_CR_CRCEN_Pos)9RNG_CRC_DIR_CRCIN_Pos 0:RNG_CRC_DIR_CRCIN_Msk (0xffffffffU << RNG_CRC_DIR_CRCIN_Pos)<RNG_CRC_SR_CRCDONE_Pos 0?RNG_CRC_SR_CRCDONE_Msk (0x1U << RNG_CRC_SR_CRCDONE_Pos)`T ..\Drivers\..\Core\Include\fm33a0xxev_rng.hFM33A0XXEV.h¼


..\Drivers\fm33a0xxev_rng.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM›œ__FM33A0XXEV_U7816_H 7U7816_CR_TXEN_Pos 58U7816_CR_TXEN_Msk (0x1U << U7816_CR_TXEN_Pos):U7816_CR_RXEN_Pos 4;U7816_CR_RXEN_Msk (0x1U << U7816_CR_RXEN_Pos)=U7816_CR_CKOEN_Pos 3>U7816_CR_CKOEN_Msk (0x1U << U7816_CR_CKOEN_Pos)@U7816_CR_HPUAT_Pos 2AU7816_CR_HPUAT_Msk (0x1U << U7816_CR_HPUAT_Pos)CU7816_CR_HPUEN_Pos 1DU7816_CR_HPUEN_Msk (0x1U << U7816_CR_HPUEN_Pos)FU7816_FFR_SFREN_Pos 11GU7816_FFR_SFREN_Msk (0x1U << U7816_FFR_SFREN_Pos)HU7816_FFR_SFREN_3ETU (0x1U << U7816_FFR_SFREN_Pos)IU7816_FFR_SFREN_2ETU (0x0U << U7816_FFR_SFREN_Pos)KU7816_FFR_ERSW_Pos 9LU7816_FFR_ERSW_Msk (0x3U << U7816_FFR_ERSW_Pos)MU7816_FFR_ERSW_1ETU (0x0U << U7816_FFR_ERSW_Pos)NU7816_FFR_ERSW_1P5ETU (0x1U << U7816_FFR_ERSW_Pos)OU7816_FFR_ERSW_2ETU (0x2U << U7816_FFR_ERSW_Pos)QU7816_FFR_ERSGD_Pos 8SU7816_FFR_ERSGD_Msk (0x1U << U7816_FFR_ERSGD_Pos)TU7816_FFR_ERSGD_1ETU (0x1U << U7816_FFR_ERSGD_Pos)UU7816_FFR_ERSGD_2ETU (0x0U << U7816_FFR_ERSGD_Pos)WU7816_FFR_BGTEN_Pos 7XU7816_FFR_BGTEN_Msk (0x1U << U7816_FFR_BGTEN_Pos)ZU7816_FFR_REP_T_Pos 6[U7816_FFR_REP_T_Msk (0x1U << U7816_FFR_REP_T_Pos)\U7816_FFR_REP_T_1TIMES (0x0U << U7816_FFR_REP_T_Pos)]U7816_FFR_REP_T_3TIMES (0x1U << U7816_FFR_REP_T_Pos)_U7816_FFR_PAR_Pos 4`U7816_FFR_PAR_Msk (0x3U << U7816_FFR_PAR_Pos)aU7816_FFR_PAR_EVEN (0x0U << U7816_FFR_PAR_Pos)bU7816_FFR_PAR_ODD (0x1U << U7816_FFR_PAR_Pos)cU7816_FFR_PAR_1ALAWAYS (0x2U << U7816_FFR_PAR_Pos)dU7816_FFR_PAR_NON (0x3U << U7816_FFR_PAR_Pos)fU7816_FFR_RFREN_Pos 3gU7816_FFR_RFREN_Msk (0x1U << U7816_FFR_RFREN_Pos)hU7816_FFR_RFREN_1ETU (0x1U << U7816_FFR_RFREN_Pos)iU7816_FFR_RFREN_2ETU (0x0U << U7816_FFR_RFREN_Pos)kU7816_FFR_TREPEN_Pos 2lU7816_FFR_TREPEN_Msk (0x1U << U7816_FFR_TREPEN_Pos)nU7816_FFR_RREPEN_Pos 1oU7816_FFR_RREPEN_Msk (0x1U << U7816_FFR_RREPEN_Pos)qU7816_FFR_DICONV_Pos 0rU7816_FFR_DICONV_Msk (0x1U << U7816_FFR_DICONV_Pos)sU7816_FFR_DICONV_FORWARD (0x0U << U7816_FFR_DICONV_Pos)tU7816_FFR_DICONV_REVERSE (0x1U << U7816_FFR_DICONV_Pos)vU7816_EGTR_TXEGT_Pos 0xU7816_EGTR_TXEGT_Msk (0xffU << U7816_EGTR_TXEGT_Pos)zU7816_PSC_CLKDIV_Pos 0{U7816_PSC_CLKDIV_Msk (0x1fU << U7816_PSC_CLKDIV_Pos)}U7816_BGR_PDIV_Pos 0€U7816_BGR_PDIV_Msk (0xfffU << U7816_BGR_PDIV_Pos)‚U7816_RXBUF_RXBUF_Pos 0ƒU7816_RXBUF_RXBUF_Msk (0xffU << U7816_RXBUF_RXBUF_Pos)…U7816_TXBUF_TXBUF_Pos 0†U7816_TXBUF_TXBUF_Msk (0xffU << U7816_TXBUF_TXBUF_Pos)ˆU7816_IER_RXIE_Pos 2‰U7816_IER_RXIE_Msk (0x1U << U7816_IER_RXIE_Pos)‹U7816_IER_TXIE_Pos 1ŒU7816_IER_TXIE_Msk (0x1U << U7816_IER_TXIE_Pos)ŽU7816_IER_LSIE_Pos 0U7816_IER_LSIE_Msk (0x1U << U7816_IER_LSIE_Pos)‘U7816_ISR_WAIT_RPT_Pos 18’U7816_ISR_WAIT_RPT_Msk (0x1U << U7816_ISR_WAIT_RPT_Pos)”U7816_ISR_TXBUSY_Pos 17•U7816_ISR_TXBUSY_Msk (0x1U << U7816_ISR_TXBUSY_Pos)—U7816_ISR_RXBUSY_Pos 16˜U7816_ISR_RXBUSY_Msk (0x1U << U7816_ISR_RXBUSY_Pos)šU7816_ISR_TPARERR_Pos 11›U7816_ISR_TPARERR_Msk (0x1U << U7816_ISR_TPARERR_Pos)U7816_ISR_RPARERR_Pos 10žU7816_ISR_RPARERR_Msk (0x1U << U7816_ISR_RPARERR_Pos) U7816_ISR_FRERR_Pos 9¡U7816_ISR_FRERR_Msk (0x1U << U7816_ISR_FRERR_Pos)£U7816_ISR_OVERR_Pos 8¤U7816_ISR_OVERR_Msk (0x1U << U7816_ISR_OVERR_Pos)¦U7816_ISR_RXIF_Pos 2§U7816_ISR_RXIF_Msk (0x1U << U7816_ISR_RXIF_Pos)©U7816_ISR_TXIF_Pos 1ªU7816_ISR_TXIF_Msk (0x1U << U7816_ISR_TXIF_Pos)¬U7816_ISR_ERRIF_Pos 0­U7816_ISR_ERRIF_Msk (0x1U << U7816_ISR_ERRIF_Pos)`V ..\Drivers\..\Core\Include\fm33a0xxev_u7816.hFM33A0XXEV.h


..\Drivers\fm33a0xxev_u7816.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM*ú8TXEN#RXEN#CKOEN#HPUAT#HPUEN#ERSWf#ERSGDf#BGTEN#REP_Tf#PARf#SFRENf#RFRENf# TREPEN#$RREPEN#%DICONV#&TXEGTf#(CLKDIVf#,PDIVf#0RXIE#4TXIE#5LSIE#6PU7816_InitTypeDef¿4Ÿ ¡__FM33A0XXEV_UART_H OUARTIR_CR_IRFLAG_Pos 15RUARTIR_CR_IRFLAG_Msk (0x1U << UARTIR_CR_IRFLAG_Pos)SUARTIR_CR_IRFLAG_POSITIVE (0x0U << UARTIR_CR_IRFLAG_Pos)TUARTIR_CR_IRFLAG_NEGTIVE (0x1U << UARTIR_CR_IRFLAG_Pos)VUARTIR_CR_TH_Pos 11WUARTIR_CR_TH_Msk (0xfU << UARTIR_CR_TH_Pos)YUARTIR_CR_TZBRG_Pos 0ZUARTIR_CR_TZBRG_Msk (0x7ffU << UARTIR_CR_TZBRG_Pos)\UARTx_CSR_BUSY_Pos 24_UARTx_CSR_BUSY_Msk (0x1U << UARTx_CSR_BUSY_Pos)aUARTx_CSR_TXIREN_Pos 17dUARTx_CSR_TXIREN_Msk (0x1U << UARTx_CSR_TXIREN_Pos)hUARTx_CSR_RXTOEN_Pos 16kUARTx_CSR_RXTOEN_Msk (0x1U << UARTx_CSR_RXTOEN_Pos)oUARTx_CSR_IOSWAP_Pos 12rUARTx_CSR_IOSWAP_Msk (0x1U << UARTx_CSR_IOSWAP_Pos)sUARTx_CSR_IOSWAP_DEFAULT (0x0U << UARTx_CSR_IOSWAP_Pos)tUARTx_CSR_IOSWAP_EXCHANGE (0x1U << UARTx_CSR_IOSWAP_Pos)vUARTx_CSR_DMATXIFCFG_Pos 10yUARTx_CSR_DMATXIFCFG_Msk (0x1U << UARTx_CSR_DMATXIFCFG_Pos)}UARTx_CSR_BITORD_Pos 9€UARTx_CSR_BITORD_Msk (0x1U << UARTx_CSR_BITORD_Pos)UARTx_CSR_BITORD_LSB (0x0U << UARTx_CSR_BITORD_Pos)‚UARTx_CSR_BITORD_MSB (0x1U << UARTx_CSR_BITORD_Pos)„UARTx_CSR_STOPCFG_Pos 8‡UARTx_CSR_STOPCFG_Msk (0x1U << UARTx_CSR_STOPCFG_Pos)ˆUARTx_CSR_STOPCFG_1STOPBIT (0x0U << UARTx_CSR_STOPCFG_Pos)‰UARTx_CSR_STOPCFG_2STOPBIT (0x1U << UARTx_CSR_STOPCFG_Pos)‹UARTx_CSR_PDSEL_Pos 6UARTx_CSR_PDSEL_Msk (0x3U << UARTx_CSR_PDSEL_Pos)‘UARTx_CSR_PDSEL_7BIT (0x0U << UARTx_CSR_PDSEL_Pos)’UARTx_CSR_PDSEL_8BIT (0x1U << UARTx_CSR_PDSEL_Pos)“UARTx_CSR_PDSEL_9BIT (0x2U << UARTx_CSR_PDSEL_Pos)”UARTx_CSR_PDSEL_6BIT (0x3U << UARTx_CSR_PDSEL_Pos)–UARTx_CSR_PARITY_Pos 4›UARTx_CSR_PARITY_Msk (0x3U << UARTx_CSR_PARITY_Pos)œUARTx_CSR_PARITY_NONE (0x0U << UARTx_CSR_PARITY_Pos)UARTx_CSR_PARITY_EVEN (0x1U << UARTx_CSR_PARITY_Pos)žUARTx_CSR_PARITY_ODD (0x2U << UARTx_CSR_PARITY_Pos) UARTx_CSR_RXPOL_Pos 3£UARTx_CSR_RXPOL_Msk (0x1U << UARTx_CSR_RXPOL_Pos)¤UARTx_CSR_RXPOL_POSITIVE (0x0U << UARTx_CSR_RXPOL_Pos)¥UARTx_CSR_RXPOL_NEGTIVE (0x1U << UARTx_CSR_RXPOL_Pos)§UARTx_CSR_TXPOL_Pos 2ªUARTx_CSR_TXPOL_Msk (0x1U << UARTx_CSR_TXPOL_Pos)«UARTx_CSR_TXPOL_POSITIVE (0x0U << UARTx_CSR_TXPOL_Pos)¬UARTx_CSR_TXPOL_NEGTIVE (0x1U << UARTx_CSR_TXPOL_Pos)®UARTx_CSR_RXEN_Pos 1¯UARTx_CSR_RXEN_Msk (0x1U << UARTx_CSR_RXEN_Pos)°UARTx_CSR_RXEN_DISBALE (0x0U << UARTx_CSR_RXEN_Pos)±UARTx_CSR_RXEN_ENABLE (0x1U << UARTx_CSR_RXEN_Pos)³UARTx_CSR_TXEN_Pos 0´UARTx_CSR_TXEN_Msk (0x1U << UARTx_CSR_TXEN_Pos)µUARTx_CSR_TXEN_DISBALE (0x0U << UARTx_CSR_TXEN_Pos)¶UARTx_CSR_TXEN_ENABLE (0x1U << UARTx_CSR_TXEN_Pos)¸UARTx_IER_RXTO_IE_Pos 11ºUARTx_IER_RXTO_IE_Msk (0x1U << UARTx_IER_RXTO_IE_Pos)¼UARTx_IER_RXERR_IE_Pos 10½UARTx_IER_RXERR_IE_Msk (0x1U << UARTx_IER_RXERR_IE_Pos)¿UARTx_IER_RXBF_IE_Pos 8ÀUARTx_IER_RXBF_IE_Msk (0x1U << UARTx_IER_RXBF_IE_Pos)ÂUARTx_IER_NEWUP_IE_Pos 7ÃUARTx_IER_NEWUP_IE_Msk (0x1U << UARTx_IER_NEWUP_IE_Pos)ÅUARTx_IER_TXBE_IE_Pos 1ÆUARTx_IER_TXBE_IE_Msk (0x1U << UARTx_IER_TXBE_IE_Pos)ÈUARTx_IER_TXSE_IE_Pos 0ÉUARTx_IER_TXSE_IE_Msk (0x1U << UARTx_IER_TXSE_IE_Pos)ËUARTx_ISR_PERR_Pos 18ÌUARTx_ISR_PERR_Msk (0x1U << UARTx_ISR_PERR_Pos)ÎUARTx_ISR_FERR_Pos 17ÏUARTx_ISR_FERR_Msk (0x1U << UARTx_ISR_FERR_Pos)ÑUARTx_ISR_OERR_Pos 16ÓUARTx_ISR_OERR_Msk (0x1U << UARTx_ISR_OERR_Pos)ÕUARTx_ISR_RXTO_Pos 11×UARTx_ISR_RXTO_Msk (0x1U << UARTx_ISR_RXTO_Pos)ÙUARTx_ISR_RXBF_Pos 8ÚUARTx_ISR_RXBF_Msk (0x1U << UARTx_ISR_RXBF_Pos)ÜUARTx_ISR_TXBE_Pos 1ÝUARTx_ISR_TXBE_Msk (0x1U << UARTx_ISR_TXBE_Pos)ßUARTx_ISR_TXSE_Pos 0àUARTx_ISR_TXSE_Msk (0x1U << UARTx_ISR_TXSE_Pos)âUARTx_TODR_TXDLY_LEN_Pos 8ãUARTx_TODR_TXDLY_LEN_Msk (0xffU << UARTx_TODR_TXDLY_LEN_Pos)åUARTx_TODR_RXTO_LEN_Pos 0æUARTx_TODR_RXTO_LEN_Msk (0xffU << UARTx_TODR_RXTO_LEN_Pos)èUARTx_RXBUF_RXBUF_Pos 0éUARTx_RXBUF_RXBUF_Msk (0x1ffU << UARTx_RXBUF_RXBUF_Pos)ëUARTx_TXBUF_TXBUF_Pos 0ìUARTx_TXBUF_TXBUF_Msk (0x1ffU << UARTx_TXBUF_TXBUF_Pos)îUARTx_BRG_SPBRG_Pos 0ïUARTx_BRG_SPBRG_Msk (0xffffU << UARTx_BRG_SPBRG_Pos)ti ..\Drivers\..\Core\Include\fm33a0xxev_uart.hFM33A0XXEV.hfm33a0xxev_CMU.h


..\Drivers\fm33a0xxev_uart.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMÕRxIntTxIntPUART_IntTypeDef¾¢Seven7BitEight8BitNine9BitSix6BitPUART_DataBitTypeDefì%ÙNONEEVENODDPUART_ParityBitTypeDef=,OneBitTwoBitPUART_StopBitTypeDefv2*‚BaudRatef#DataBit"#ParityBitY#StopBit#ClockSrcf#PUART_SInitTypeDefª;*þRXBF_IE#TXBE_IE#TXSE_IE#SPBRGf#PDSELf#PARITYf#RXTO_IE#ERRIE#RXEN#STOPSELf#TXEN#IREN#RXDFLAG#TXDFLAG#PUART_InitTypeDefM£¤¥__FM33A0XXEV_LPTIM_H LPTIM_CFGR_ETR_AFEN_Pos 24LPTIM_CFGR_ETR_AFEN_Msk (0x1U << LPTIM_CFGR_ETR_AFEN_Pos) LPTIM_CFGR_PSCSEL_Pos 14#LPTIM_CFGR_PSCSEL_Msk (0x1U << LPTIM_CFGR_PSCSEL_Pos)$LPTIM_CFGR_PSCSEL_CLKSEL (0x0U << LPTIM_CFGR_PSCSEL_Pos)%LPTIM_CFGR_PSCSEL_LPTETRF (0x1U << LPTIM_CFGR_PSCSEL_Pos)'LPTIM_CFGR_DIVSEL_Pos 100LPTIM_CFGR_DIVSEL_Msk (0x7U << LPTIM_CFGR_DIVSEL_Pos)1LPTIM_CFGR_DIVSEL_DIV1 (0x0U << LPTIM_CFGR_DIVSEL_Pos)2LPTIM_CFGR_DIVSEL_DIV2 (0x1U << LPTIM_CFGR_DIVSEL_Pos)3LPTIM_CFGR_DIVSEL_DIV4 (0x2U << LPTIM_CFGR_DIVSEL_Pos)4LPTIM_CFGR_DIVSEL_DIV8 (0x3U << LPTIM_CFGR_DIVSEL_Pos)5LPTIM_CFGR_DIVSEL_DIV16 (0x4U << LPTIM_CFGR_DIVSEL_Pos)6LPTIM_CFGR_DIVSEL_DIV32 (0x5U << LPTIM_CFGR_DIVSEL_Pos)7LPTIM_CFGR_DIVSEL_DIV64 (0x6U << LPTIM_CFGR_DIVSEL_Pos)8LPTIM_CFGR_DIVSEL_DIV128 (0x7U << LPTIM_CFGR_DIVSEL_Pos):LPTIM_CFGR_EDGESEL_Pos 7=LPTIM_CFGR_EDGESEL_Msk (0x1U << LPTIM_CFGR_EDGESEL_Pos)>LPTIM_CFGR_EDGESEL_RISING (0x0U << LPTIM_CFGR_EDGESEL_Pos)?LPTIM_CFGR_EDGESEL_FALLING (0x1U << LPTIM_CFGR_EDGESEL_Pos)ALPTIM_CFGR_TRIGCFG_Pos 5ELPTIM_CFGR_TRIGCFG_Msk (0x3U << LPTIM_CFGR_TRIGCFG_Pos)FLPTIM_CFGR_TRIGCFG_RISING (0x0U << LPTIM_CFGR_TRIGCFG_Pos)GLPTIM_CFGR_TRIGCFG_FALLING (0x1U << LPTIM_CFGR_TRIGCFG_Pos)HLPTIM_CFGR_TRIGCFG_EXTERNAL (0x2U << LPTIM_CFGR_TRIGCFG_Pos)JLPTIM_CFGR_ONST_Pos 2MLPTIM_CFGR_ONST_Msk (0x1U << LPTIM_CFGR_ONST_Pos)NLPTIM_CFGR_ONST_CONTINUE (0x0U << LPTIM_CFGR_ONST_Pos)OLPTIM_CFGR_ONST_SINGLE (0x1U << LPTIM_CFGR_ONST_Pos)QLPTIM_CFGR_TMODE_Pos 0VLPTIM_CFGR_TMODE_Msk (0x3U << LPTIM_CFGR_TMODE_Pos)WLPTIM_CFGR_TMODE_COUNTER (0x0U << LPTIM_CFGR_TMODE_Pos)XLPTIM_CFGR_TMODE_PULSE (0x1U << LPTIM_CFGR_TMODE_Pos)YLPTIM_CFGR_TMODE_ASY (0x2U << LPTIM_CFGR_TMODE_Pos)ZLPTIM_CFGR_TMODE_TIMEOUT (0x3U << LPTIM_CFGR_TMODE_Pos)\LPTIM_CNTR_CNT32_Pos 0]LPTIM_CNTR_CNT32_Msk (0xffffffffU << LPTIM_CNTR_CNT32_Pos)_LPTIM_CCSR_CAP1SSEL_Pos 24dLPTIM_CCSR_CAP1SSEL_Msk (0x3U << LPTIM_CCSR_CAP1SSEL_Pos)eLPTIM_CCSR_CAP1SSEL_LPT_CH1 (0x0U << LPTIM_CCSR_CAP1SSEL_Pos)fLPTIM_CCSR_CAP1SSEL_XTLF (0x1U << LPTIM_CCSR_CAP1SSEL_Pos)gLPTIM_CCSR_CAP1SSEL_RCLP (0x2U << LPTIM_CCSR_CAP1SSEL_Pos)hLPTIM_CCSR_CAP1SSEL_RCMF (0x3U << LPTIM_CCSR_CAP1SSEL_Pos)jLPTIM_CCSR_CAP4EDGE_Pos 23mLPTIM_CCSR_CAP4EDGE_Msk (0x1U << LPTIM_CCSR_CAP4EDGE_Pos)nLPTIM_CCSR_CAP4EDGE_RISING (0x0U << LPTIM_CCSR_CAP4EDGE_Pos)oLPTIM_CCSR_CAP4EDGE_FALLING (0x1U << LPTIM_CCSR_CAP4EDGE_Pos)qLPTIM_CCSR_CAP3EDGE_Pos 22rLPTIM_CCSR_CAP3EDGE_Msk (0x1U << LPTIM_CCSR_CAP3EDGE_Pos)sLPTIM_CCSR_CAP3EDGE_RISING (0x0U << LPTIM_CCSR_CAP3EDGE_Pos)tLPTIM_CCSR_CAP3EDGE_FALLING (0x1U << LPTIM_CCSR_CAP3EDGE_Pos)vLPTIM_CCSR_CAP2EDGE_Pos 21wLPTIM_CCSR_CAP2EDGE_Msk (0x1U << LPTIM_CCSR_CAP2EDGE_Pos)xLPTIM_CCSR_CAP2EDGE_RISING (0x0U << LPTIM_CCSR_CAP2EDGE_Pos)yLPTIM_CCSR_CAP2EDGE_FALLING (0x1U << LPTIM_CCSR_CAP2EDGE_Pos){LPTIM_CCSR_CAP1EDGE_Pos 20|LPTIM_CCSR_CAP1EDGE_Msk (0x1U << LPTIM_CCSR_CAP1EDGE_Pos)}LPTIM_CCSR_CAP1EDGE_RISING (0x0U << LPTIM_CCSR_CAP1EDGE_Pos)~LPTIM_CCSR_CAP1EDGE_FALLING (0x1U << LPTIM_CCSR_CAP1EDGE_Pos)€LPTIM_CCSR_POLAR4_Pos 19ƒLPTIM_CCSR_POLAR4_Msk (0x1U << LPTIM_CCSR_POLAR4_Pos)„LPTIM_CCSR_POLAR4_POS (0x0U << LPTIM_CCSR_POLAR4_Pos)…LPTIM_CCSR_POLAR4_NEG (0x1U << LPTIM_CCSR_POLAR4_Pos)‡LPTIM_CCSR_POLAR3_Pos 18ˆLPTIM_CCSR_POLAR3_Msk (0x1U << LPTIM_CCSR_POLAR3_Pos)‰LPTIM_CCSR_POLAR3_POS (0x0U << LPTIM_CCSR_POLAR3_Pos)ŠLPTIM_CCSR_POLAR3_NEG (0x1U << LPTIM_CCSR_POLAR3_Pos)ŒLPTIM_CCSR_POLAR2_Pos 17LPTIM_CCSR_POLAR2_Msk (0x1U << LPTIM_CCSR_POLAR2_Pos)ŽLPTIM_CCSR_POLAR2_POS (0x0U << LPTIM_CCSR_POLAR2_Pos)LPTIM_CCSR_POLAR2_NEG (0x1U << LPTIM_CCSR_POLAR2_Pos)‘LPTIM_CCSR_POLAR1_Pos 16’LPTIM_CCSR_POLAR1_Msk (0x1U << LPTIM_CCSR_POLAR1_Pos)“LPTIM_CCSR_POLAR1_POS (0x0U << LPTIM_CCSR_POLAR1_Pos)”LPTIM_CCSR_POLAR1_NEG (0x1U << LPTIM_CCSR_POLAR1_Pos)–LPTIM_CCSR_CAPCFG4_Pos 14›LPTIM_CCSR_CAPCFG4_Msk (0x3U << LPTIM_CCSR_CAPCFG4_Pos)œLPTIM_CCSR_CAPCFG4_RISING (0x0U << LPTIM_CCSR_CAPCFG4_Pos)LPTIM_CCSR_CAPCFG4_FALLING (0x1U << LPTIM_CCSR_CAPCFG4_Pos)žLPTIM_CCSR_CAPCFG4_BOTH (0x2U << LPTIM_CCSR_CAPCFG4_Pos) LPTIM_CCSR_CAPCFG3_Pos 12¡LPTIM_CCSR_CAPCFG3_Msk (0x3U << LPTIM_CCSR_CAPCFG3_Pos)¢LPTIM_CCSR_CAPCFG3_RISING (0x0U << LPTIM_CCSR_CAPCFG3_Pos)£LPTIM_CCSR_CAPCFG3_FALLING (0x1U << LPTIM_CCSR_CAPCFG3_Pos)¤LPTIM_CCSR_CAPCFG3_BOTH (0x2U << LPTIM_CCSR_CAPCFG3_Pos)¦LPTIM_CCSR_CAPCFG2_Pos 10§LPTIM_CCSR_CAPCFG2_Msk (0x3U << LPTIM_CCSR_CAPCFG2_Pos)¨LPTIM_CCSR_CAPCFG2_RISING (0x0U << LPTIM_CCSR_CAPCFG2_Pos)©LPTIM_CCSR_CAPCFG2_FALLING (0x1U << LPTIM_CCSR_CAPCFG2_Pos)ªLPTIM_CCSR_CAPCFG2_BOTH (0x2U << LPTIM_CCSR_CAPCFG2_Pos)¬LPTIM_CCSR_CAPCFG1_Pos 8­LPTIM_CCSR_CAPCFG1_Msk (0x3U << LPTIM_CCSR_CAPCFG1_Pos)®LPTIM_CCSR_CAPCFG1_RISING (0x0U << LPTIM_CCSR_CAPCFG1_Pos)¯LPTIM_CCSR_CAPCFG1_FALLING (0x1U << LPTIM_CCSR_CAPCFG1_Pos)°LPTIM_CCSR_CAPCFG1_BOTH (0x2U << LPTIM_CCSR_CAPCFG1_Pos)²LPTIM_CCSR_CC4S_Pos 6¶LPTIM_CCSR_CC4S_Msk (0x3U << LPTIM_CCSR_CC4S_Pos)·LPTIM_CCSR_CC4S_NON (0x0U << LPTIM_CCSR_CC4S_Pos)¸LPTIM_CCSR_CC4S_LPT_CH4_IN (0x1U << LPTIM_CCSR_CC4S_Pos)¹LPTIM_CCSR_CC4S_LPT_CH4_OUT (0x2U << LPTIM_CCSR_CC4S_Pos)»LPTIM_CCSR_CC3S_Pos 4¼LPTIM_CCSR_CC3S_Msk (0x3U << LPTIM_CCSR_CC3S_Pos)½LPTIM_CCSR_CC3S_NON (0x0U << LPTIM_CCSR_CC3S_Pos)¾LPTIM_CCSR_CC3S_LPT_CH3_IN (0x1U << LPTIM_CCSR_CC3S_Pos)¿LPTIM_CCSR_CC3S_LPT_CH3_OUT (0x2U << LPTIM_CCSR_CC3S_Pos)ÁLPTIM_CCSR_CC2S_Pos 2ÂLPTIM_CCSR_CC2S_Msk (0x3U << LPTIM_CCSR_CC2S_Pos)ÃLPTIM_CCSR_CC2S_NON (0x0U << LPTIM_CCSR_CC2S_Pos)ÄLPTIM_CCSR_CC2S_LPT_CH2_IN (0x1U << LPTIM_CCSR_CC2S_Pos)ÅLPTIM_CCSR_CC2S_LPT_CH2_OUT (0x2U << LPTIM_CCSR_CC2S_Pos)ÇLPTIM_CCSR_CC1S_Pos 0ÈLPTIM_CCSR_CC1S_Msk (0x3U << LPTIM_CCSR_CC1S_Pos)ÉLPTIM_CCSR_CC1S_NON (0x0U << LPTIM_CCSR_CC1S_Pos)ÊLPTIM_CCSR_CC1S_LPT_CH1_IN (0x1U << LPTIM_CCSR_CC1S_Pos)ËLPTIM_CCSR_CC1S_LPT_CH1_OUT (0x2U << LPTIM_CCSR_CC1S_Pos)ÍLPTIM_ARR_ARR_Pos 0ÏLPTIM_ARR_ARR_Msk (0xffffffffU << LPTIM_ARR_ARR_Pos)ÑLPTIM_IER_OVR4IE_Pos 11ÔLPTIM_IER_OVR4IE_Msk (0x1U << LPTIM_IER_OVR4IE_Pos)ØLPTIM_IER_OVR3IE_Pos 10ÛLPTIM_IER_OVR3IE_Msk (0x1U << LPTIM_IER_OVR3IE_Pos)ßLPTIM_IER_OVR2IE_Pos 9âLPTIM_IER_OVR2IE_Msk (0x1U << LPTIM_IER_OVR2IE_Pos)æLPTIM_IER_OVR1IE_Pos 8éLPTIM_IER_OVR1IE_Msk (0x1U << LPTIM_IER_OVR1IE_Pos)íLPTIM_IER_TRIGIE_Pos 7ðLPTIM_IER_TRIGIE_Msk (0x1U << LPTIM_IER_TRIGIE_Pos)ôLPTIM_IER_OVIE_Pos 6÷LPTIM_IER_OVIE_Msk (0x1U << LPTIM_IER_OVIE_Pos)ûLPTIM_IER_CC4IE_Pos 3þLPTIM_IER_CC4IE_Msk (0x1U << LPTIM_IER_CC4IE_Pos)‚LPTIM_IER_CC3IE_Pos 2…LPTIM_IER_CC3IE_Msk (0x1U << LPTIM_IER_CC3IE_Pos)‰LPTIM_IER_CC2IE_Pos 1ŒLPTIM_IER_CC2IE_Msk (0x1U << LPTIM_IER_CC2IE_Pos)LPTIM_IER_CC1IE_Pos 0“LPTIM_IER_CC1IE_Msk (0x1U << LPTIM_IER_CC1IE_Pos)—LPTIM_ISR_CAP4OVR_Pos 11˜LPTIM_ISR_CAP4OVR_Msk (0x1U << LPTIM_ISR_CAP4OVR_Pos)šLPTIM_ISR_CAP3OVR_Pos 10›LPTIM_ISR_CAP3OVR_Msk (0x1U << LPTIM_ISR_CAP3OVR_Pos)LPTIM_ISR_CAP2OVR_Pos 9žLPTIM_ISR_CAP2OVR_Msk (0x1U << LPTIM_ISR_CAP2OVR_Pos) LPTIM_ISR_CAP1OVR_Pos 8¡LPTIM_ISR_CAP1OVR_Msk (0x1U << LPTIM_ISR_CAP1OVR_Pos)£LPTIM_ISR_TRIGIF_Pos 7¤LPTIM_ISR_TRIGIF_Msk (0x1U << LPTIM_ISR_TRIGIF_Pos)¦LPTIM_ISR_OVIF_Pos 6§LPTIM_ISR_OVIF_Msk (0x1U << LPTIM_ISR_OVIF_Pos)©LPTIM_ISR_CC4IF_Pos 3ªLPTIM_ISR_CC4IF_Msk (0x1U << LPTIM_ISR_CC4IF_Pos)¬LPTIM_ISR_CC3IF_Pos 2­LPTIM_ISR_CC3IF_Msk (0x1U << LPTIM_ISR_CC3IF_Pos)¯LPTIM_ISR_CC2IF_Pos 1°LPTIM_ISR_CC2IF_Msk (0x1U << LPTIM_ISR_CC2IF_Pos)²LPTIM_ISR_CC1IF_Pos 0³LPTIM_ISR_CC1IF_Msk (0x1U << LPTIM_ISR_CC1IF_Pos)µLPTIM_CR_EN_Pos 0¸LPTIM_CR_EN_Msk (0x1U << LPTIM_CR_EN_Pos)¼LPTIM_CCR1_CCR1_Pos 0½LPTIM_CCR1_CCR1_Msk (0xffffffffU << LPTIM_CCR1_CCR1_Pos)¿LPTIM_CCR2_CCR2_Pos 0ÀLPTIM_CCR2_CCR2_Msk (0xffffffffU << LPTIM_CCR2_CCR2_Pos)ÂLPTIM_CCR3_CCR3_Pos 0ÃLPTIM_CCR3_CCR3_Msk (0xffffffffU << LPTIM_CCR3_CCR3_Pos)ÅLPTIM_CCR4_CCR4_Pos 0ÆLPTIM_CCR4_CCR4_Msk (0xffffffffU << LPTIM_CCR4_CCR4_Pos)`V ..\Drivers\..\Core\Include\fm33a0xxev_lptim.hFM33A0XXEV.hÀ


..\Drivers\fm33a0xxev_lptim.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM§¨©__FM33A0XXEV_WWDT_H WWDT_CR_CON_Pos 0WWDT_CR_CON_Msk (0xffU << WWDT_CR_CON_Pos)WWDT_CFGR_CFG_Pos 0&WWDT_CFGR_CFG_Msk (0x7U << WWDT_CFGR_CFG_Pos)(WWDT_CNTR_CNT_Pos 0)WWDT_CNTR_CNT_Msk (0x3ffU << WWDT_CNTR_CNT_Pos)+WWDT_IER_IE_Pos 0.WWDT_IER_IE_Msk (0x1U << WWDT_IER_IE_Pos)2WWDT_ISR_NOVF_Pos 06WWDT_ISR_NOVF_Msk (0x1U << WWDT_ISR_NOVF_Pos)8WWDT_PSCR_DIV_CNT_Pos 09WWDT_PSCR_DIV_CNT_Msk (0xfffU << WWDT_PSCR_DIV_CNT_Pos)`U ..\Drivers\..\Core\Include\fm33a0xxev_wwdt.hFM33A0XXEV.h¼


..\Drivers\fm33a0xxev_wwdt.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM«¬­__FM33A0XXEV_SVD_H %SVD_CFGR_LVL_Pos 4'SVD_CFGR_LVL_Msk (0xfU << SVD_CFGR_LVL_Pos)(SVD_CFGR_LVL_1P800V (0x0U << SVD_CFGR_LVL_Pos))SVD_CFGR_LVL_2P014V (0x1U << SVD_CFGR_LVL_Pos)*SVD_CFGR_LVL_2P229V (0x2U << SVD_CFGR_LVL_Pos)+SVD_CFGR_LVL_2P443V (0x3U << SVD_CFGR_LVL_Pos),SVD_CFGR_LVL_2P657V (0x4U << SVD_CFGR_LVL_Pos)-SVD_CFGR_LVL_2P871V (0x5U << SVD_CFGR_LVL_Pos).SVD_CFGR_LVL_3P086V (0x6U << SVD_CFGR_LVL_Pos)/SVD_CFGR_LVL_3P300V (0x7U << SVD_CFGR_LVL_Pos)0SVD_CFGR_LVL_3P514V (0x8U << SVD_CFGR_LVL_Pos)1SVD_CFGR_LVL_3P729V (0x9U << SVD_CFGR_LVL_Pos)2SVD_CFGR_LVL_3P943V (0xaU << SVD_CFGR_LVL_Pos)3SVD_CFGR_LVL_4P157V (0xbU << SVD_CFGR_LVL_Pos)4SVD_CFGR_LVL_4P371V (0xcU << SVD_CFGR_LVL_Pos)5SVD_CFGR_LVL_4P586V (0xdU << SVD_CFGR_LVL_Pos)6SVD_CFGR_LVL_4P800V (0xeU << SVD_CFGR_LVL_Pos)7SVD_CFGR_LVL_SVS (0xfU << SVD_CFGR_LVL_Pos)9SVD_CFGR_DFEN_Pos 3=SVD_CFGR_DFEN_Msk (0x1U << SVD_CFGR_DFEN_Pos)ASVD_CFGR_MOD_Pos 2FSVD_CFGR_MOD_Msk (0x1U << SVD_CFGR_MOD_Pos)GSVD_CFGR_MOD_INTERVAL (0x1U << SVD_CFGR_MOD_Pos)HSVD_CFGR_MOD_ALWAYSON (0x0U << SVD_CFGR_MOD_Pos)JSVD_CFGR_ITVL_Pos 0OSVD_CFGR_ITVL_Msk (0x3U << SVD_CFGR_ITVL_Pos)PSVD_CFGR_ITVL_62P5MS (0x0U << SVD_CFGR_ITVL_Pos)QSVD_CFGR_ITVL_256MS (0x1U << SVD_CFGR_ITVL_Pos)RSVD_CFGR_ITVL_1S (0x2U << SVD_CFGR_ITVL_Pos)SSVD_CFGR_ITVL_4S (0x3U << SVD_CFGR_ITVL_Pos)XSVD_CR_TE_Pos 8YSVD_CR_TE_Msk (0x1U << SVD_CR_TE_Pos)[SVD_CR_SVSEN_Pos 1`SVD_CR_SVSEN_Msk (0x1U << SVD_CR_SVSEN_Pos)dSVD_CR_SVDEN_Pos 0eSVD_CR_SVDEN_Msk (0x1U << SVD_CR_SVDEN_Pos)gSVD_IER_PFIE_Pos 1hSVD_IER_PFIE_Msk (0x1U << SVD_IER_PFIE_Pos)jSVD_IER_PRIE_Pos 0kSVD_IER_PRIE_Msk (0x1U << SVD_IER_PRIE_Pos)mSVD_ISR_SVDO_Pos 8pSVD_ISR_SVDO_Msk (0x1U << SVD_ISR_SVDO_Pos)rSVD_ISR_SVDR_Pos 7tSVD_ISR_SVDR_Msk (0x1U << SVD_ISR_SVDR_Pos)vSVD_ISR_PFF_Pos 1wSVD_ISR_PFF_Msk (0x1U << SVD_ISR_PFF_Pos)ySVD_ISR_PRF_Pos 0zSVD_ISR_PRF_Msk (0x1U << SVD_ISR_PRF_Pos)|SVD_VSR_V1P0EN_Pos 2SVD_VSR_V1P0EN_Msk (0x1U << SVD_VSR_V1P0EN_Pos)SVD_VSR_V0P95EN_Pos 1„SVD_VSR_V0P95EN_Msk (0x1U << SVD_VSR_V0P95EN_Pos)†SVD_VSR_V0P9EN_Pos 0‰SVD_VSR_V0P9EN_Msk (0x1U << SVD_VSR_V0P9EN_Pos)`T ..\Drivers\..\Core\Include\fm33a0xxev_svd.hFM33A0XXEV.hD


..\Drivers\fm33a0xxev_svd.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM*¬SVDMODf#SVDITVLf#SVDLVLf#DFEN#PFIE# PRIE#SVDEN#PSVD_InitTypeDef½#¯°±__FM33A0XXEV_PAE_H ECC_STD_DBL 0x00ECC_STD_ADD 0x01ECC_ALG1_DBLADD 0x02ECC_ALG2_ECDBL 0x03ECC_ALG2_ECADDDBL 0x04 ECC_ALG2_YRECOVER 0x05'PAE_CSR_DATA_TYPE_Pos 8-PAE_CSR_DATA_TYPE_Msk (0x3U << PAE_CSR_DATA_TYPE_Pos).PAE_CSR_DATA_TYPE_NONE (0x0U << PAE_CSR_DATA_TYPE_Pos)/PAE_CSR_DATA_TYPE_HALFWORD (0x1U << PAE_CSR_DATA_TYPE_Pos)0PAE_CSR_DATA_TYPE_BYTE (0x2U << PAE_CSR_DATA_TYPE_Pos)1PAE_CSR_DATA_TYPE_BIT (0x3U << PAE_CSR_DATA_TYPE_Pos)3PAE_CSR_START_Pos 74PAE_CSR_START_Msk (0x1U << PAE_CSR_START_Pos)6PAE_CSR_RUN_MODE_Pos 4;PAE_CSR_RUN_MODE_Msk (0x3U << PAE_CSR_RUN_MODE_Pos)<PAE_CSR_RUN_MODE_MOD (0x0U << PAE_CSR_RUN_MODE_Pos)=PAE_CSR_RUN_MODE_DOT (0x1U << PAE_CSR_RUN_MODE_Pos)>PAE_CSR_RUN_MODE_RSA (0x2U << PAE_CSR_RUN_MODE_Pos)?PAE_CSR_RUN_MODE_ECC (0x3U << PAE_CSR_RUN_MODE_Pos)APAE_CSR_SOFT_RST_Pos 3CPAE_CSR_SOFT_RST_Msk (0x1U << PAE_CSR_SOFT_RST_Pos)FPAE_CSR_PAEIE_Pos 2IPAE_CSR_PAEIE_Msk (0x1U << PAE_CSR_PAEIE_Pos)JPAE_CSR_PAEIE_ENABLE (0x1U << PAE_CSR_PAEIE_Pos)KPAE_CSR_PAEIE_DISABLE (0x0U << PAE_CSR_PAEIE_Pos)MPAE_CSR_PAEIF_Pos 1NPAE_CSR_PAEIF_Msk (0x1U << PAE_CSR_PAEIF_Pos)PPAE_CSR_BUSY_Pos 0SPAE_CSR_BUSY_Msk (0x1U << PAE_CSR_BUSY_Pos)UPAE_MLR_PAE_MLR_Pos 0YPAE_MLR_PAE_MLR_Msk (0x3fU << PAE_MLR_PAE_MLR_Pos)[PAE_MPR_PAE_MPR_Pos 0\PAE_MPR_PAE_MPR_Msk (0xffffffffU << PAE_MPR_PAE_MPR_Pos)^PAE_M0CFG_BLKCFG_Pos 15aPAE_M0CFG_BLKCFG_Msk (0x1U << PAE_M0CFG_BLKCFG_Pos)bPAE_M0CFG_BLKCFG_16BLOCK (0x1U << PAE_M0CFG_BLKCFG_Pos)cPAE_M0CFG_BLKCFG_4BLOCK (0x0U << PAE_M0CFG_BLKCFG_Pos)ePAE_M0CFG_INS_M0_Pos 12jPAE_M0CFG_INS_M0_Msk (0x3U << PAE_M0CFG_INS_M0_Pos)kPAE_M0CFG_INS_M0_MUL (0x0U << PAE_M0CFG_INS_M0_Pos)lPAE_M0CFG_INS_M0_ADD (0x1U << PAE_M0CFG_INS_M0_Pos)mPAE_M0CFG_INS_M0_SUB (0x3U << PAE_M0CFG_INS_M0_Pos)oPAE_M0CFG_RES_BLK_Pos 8rPAE_M0CFG_RES_BLK_Msk (0xfU << PAE_M0CFG_RES_BLK_Pos)sPAE_M0CFG_RES_BLK_BLOCK0 (0x0U << PAE_M0CFG_RES_BLK_Pos)tPAE_M0CFG_RES_BLK_BLOCK1 (0x1U << PAE_M0CFG_RES_BLK_Pos)uPAE_M0CFG_RES_BLK_BLOCK2 (0x2U << PAE_M0CFG_RES_BLK_Pos)vPAE_M0CFG_RES_BLK_BLOCK3 (0x3U << PAE_M0CFG_RES_BLK_Pos)wPAE_M0CFG_RES_BLK_BLOCK4 (0x4U << PAE_M0CFG_RES_BLK_Pos)xPAE_M0CFG_RES_BLK_BLOCK5 (0x5U << PAE_M0CFG_RES_BLK_Pos)yPAE_M0CFG_RES_BLK_BLOCK6 (0x6U << PAE_M0CFG_RES_BLK_Pos)zPAE_M0CFG_RES_BLK_BLOCK7 (0x7U << PAE_M0CFG_RES_BLK_Pos){PAE_M0CFG_RES_BLK_BLOCK8 (0x8U << PAE_M0CFG_RES_BLK_Pos)|PAE_M0CFG_RES_BLK_BLOCK9 (0x9U << PAE_M0CFG_RES_BLK_Pos)}PAE_M0CFG_RES_BLK_BLOCK10 (0xAU << PAE_M0CFG_RES_BLK_Pos)~PAE_M0CFG_RES_BLK_BLOCK11 (0xBU << PAE_M0CFG_RES_BLK_Pos)PAE_M0CFG_RES_BLK_BLOCK12 (0xCU << PAE_M0CFG_RES_BLK_Pos)€PAE_M0CFG_RES_BLK_BLOCK13 (0xDU << PAE_M0CFG_RES_BLK_Pos)PAE_M0CFG_RES_BLK_BLOCK14 (0xEU << PAE_M0CFG_RES_BLK_Pos)‚PAE_M0CFG_RES_BLK_BLOCK15 (0xFU << PAE_M0CFG_RES_BLK_Pos)‰PAE_M0CFG_OP1_BLK_Pos 4ŒPAE_M0CFG_OP1_BLK_Msk (0xfU << PAE_M0CFG_OP1_BLK_Pos)PAE_M0CFG_OP1_BLK_BLOCK0 (0x0U << PAE_M0CFG_OP1_BLK_Pos)ŽPAE_M0CFG_OP1_BLK_BLOCK1 (0x1U << PAE_M0CFG_OP1_BLK_Pos)PAE_M0CFG_OP1_BLK_BLOCK2 (0x2U << PAE_M0CFG_OP1_BLK_Pos)PAE_M0CFG_OP1_BLK_BLOCK3 (0x3U << PAE_M0CFG_OP1_BLK_Pos)‘PAE_M0CFG_OP1_BLK_BLOCK4 (0x4U << PAE_M0CFG_OP1_BLK_Pos)’PAE_M0CFG_OP1_BLK_BLOCK5 (0x5U << PAE_M0CFG_OP1_BLK_Pos)“PAE_M0CFG_OP1_BLK_BLOCK6 (0x6U << PAE_M0CFG_OP1_BLK_Pos)”PAE_M0CFG_OP1_BLK_BLOCK7 (0x7U << PAE_M0CFG_OP1_BLK_Pos)•PAE_M0CFG_OP1_BLK_BLOCK8 (0x8U << PAE_M0CFG_OP1_BLK_Pos)–PAE_M0CFG_OP1_BLK_BLOCK9 (0x9U << PAE_M0CFG_OP1_BLK_Pos)—PAE_M0CFG_OP1_BLK_BLOCK10 (0xAU << PAE_M0CFG_OP1_BLK_Pos)˜PAE_M0CFG_OP1_BLK_BLOCK11 (0xBU << PAE_M0CFG_OP1_BLK_Pos)™PAE_M0CFG_OP1_BLK_BLOCK12 (0xCU << PAE_M0CFG_OP1_BLK_Pos)šPAE_M0CFG_OP1_BLK_BLOCK13 (0xDU << PAE_M0CFG_OP1_BLK_Pos)›PAE_M0CFG_OP1_BLK_BLOCK14 (0xEU << PAE_M0CFG_OP1_BLK_Pos)œPAE_M0CFG_OP1_BLK_BLOCK15 (0xFU << PAE_M0CFG_OP1_BLK_Pos)¡PAE_M0CFG_OP2_BLK_Pos 0¤PAE_M0CFG_OP2_BLK_Msk (0xfU << PAE_M0CFG_OP2_BLK_Pos)¥PAE_M0CFG_OP2_BLK_BLOCK0 (0x0U << PAE_M0CFG_OP2_BLK_Pos)¦PAE_M0CFG_OP2_BLK_BLOCK1 (0x1U << PAE_M0CFG_OP2_BLK_Pos)§PAE_M0CFG_OP2_BLK_BLOCK2 (0x2U << PAE_M0CFG_OP2_BLK_Pos)¨PAE_M0CFG_OP2_BLK_BLOCK3 (0x3U << PAE_M0CFG_OP2_BLK_Pos)©PAE_M0CFG_OP2_BLK_BLOCK4 (0x4U << PAE_M0CFG_OP2_BLK_Pos)ªPAE_M0CFG_OP2_BLK_BLOCK5 (0x5U << PAE_M0CFG_OP2_BLK_Pos)«PAE_M0CFG_OP2_BLK_BLOCK6 (0x6U << PAE_M0CFG_OP2_BLK_Pos)¬PAE_M0CFG_OP2_BLK_BLOCK7 (0x7U << PAE_M0CFG_OP2_BLK_Pos)­PAE_M0CFG_OP2_BLK_BLOCK8 (0x8U << PAE_M0CFG_OP2_BLK_Pos)®PAE_M0CFG_OP2_BLK_BLOCK9 (0x9U << PAE_M0CFG_OP2_BLK_Pos)¯PAE_M0CFG_OP2_BLK_BLOCK10 (0xAU << PAE_M0CFG_OP2_BLK_Pos)°PAE_M0CFG_OP2_BLK_BLOCK11 (0xBU << PAE_M0CFG_OP2_BLK_Pos)±PAE_M0CFG_OP2_BLK_BLOCK12 (0xCU << PAE_M0CFG_OP2_BLK_Pos)²PAE_M0CFG_OP2_BLK_BLOCK13 (0xDU << PAE_M0CFG_OP2_BLK_Pos)³PAE_M0CFG_OP2_BLK_BLOCK14 (0xEU << PAE_M0CFG_OP2_BLK_Pos)´PAE_M0CFG_OP2_BLK_BLOCK15 (0xFU << PAE_M0CFG_OP2_BLK_Pos)·PAE_M1CFG_INS_M1_Pos 4ÀPAE_M1CFG_INS_M1_Msk (0x7U << PAE_M1CFG_INS_M1_Pos)ÁPAE_M1CFG_INS_M1_JACOBIN (0x0U << PAE_M1CFG_INS_M1_Pos)ÂPAE_M1CFG_INS_M1_MIXADD (0x1U << PAE_M1CFG_INS_M1_Pos)ÃPAE_M1CFG_INS_M1_ECDBL (0x3U << PAE_M1CFG_INS_M1_Pos)ÄPAE_M1CFG_INS_M1_ECADDDBL (0x4U << PAE_M1CFG_INS_M1_Pos)ÅPAE_M1CFG_INS_M1_ECYRECOVER (0x5U << PAE_M1CFG_INS_M1_Pos)ÇPAE_M1CFG_AEN3_M1_Pos 1ÊPAE_M1CFG_AEN3_M1_Msk (0x1U << PAE_M1CFG_AEN3_M1_Pos)ËPAE_M1CFG_AEN3_M1_NE3 (0x1U << PAE_M1CFG_AEN3_M1_Pos)ÌPAE_M1CFG_AEN3_M1_EQ3 (0x0U << PAE_M1CFG_AEN3_M1_Pos)ÎPAE_M1CFG_BIT_VALUE_M1_Pos 0ÑPAE_M1CFG_BIT_VALUE_M1_Msk (0x1U << PAE_M1CFG_BIT_VALUE_M1_Pos)ÒPAE_M1CFG_BIT_VALUE_M1_VALUE1 (0x1U << PAE_M1CFG_BIT_VALUE_M1_Pos)ÓPAE_M1CFG_BIT_VALUE_M1_VALUE0 (0x0U << PAE_M1CFG_BIT_VALUE_M1_Pos)ÕPAE_M2CFG_ALWAYS_MULT_Pos 4ØPAE_M2CFG_ALWAYS_MULT_Msk (0x1U << PAE_M2CFG_ALWAYS_MULT_Pos)ÙPAE_M2CFG_ALWAYS_MULT_ALWAYS (0x1U << PAE_M2CFG_ALWAYS_MULT_Pos)ÚPAE_M2CFG_ALWAYS_MULT_NONE (0x0U << PAE_M2CFG_ALWAYS_MULT_Pos)ÜPAE_M2CFG_FBO_M2_Pos 0ßPAE_M2CFG_FBO_M2_Msk (0x1U << PAE_M2CFG_FBO_M2_Pos)àPAE_M2CFG_FBO_M2_FB1 (0x1U << PAE_M2CFG_FBO_M2_Pos)áPAE_M2CFG_FBO_M2_NFB1 (0x0U << PAE_M2CFG_FBO_M2_Pos)ãPAE_M3CFG_AEN3_M3_Pos 4æPAE_M3CFG_AEN3_M3_Msk (0x1U << PAE_M3CFG_AEN3_M3_Pos)çPAE_M3CFG_AEN3_M3_EQ3 (0x1U << PAE_M3CFG_AEN3_M3_Pos)èPAE_M3CFG_AEN3_M3_NE3 (0x0U << PAE_M3CFG_AEN3_M3_Pos)êPAE_M3CFG_FBO_M3_Pos 0íPAE_M3CFG_FBO_M3_Msk (0x1U << PAE_M3CFG_FBO_M3_Pos)îPAE_M3CFG_FBO_M3_FB1 (0x1U << PAE_M3CFG_FBO_M3_Pos)ïPAE_M3CFG_FBO_M3_NFB1 (0x0U << PAE_M3CFG_FBO_M3_Pos)ñPAE_WORD_PAE_WORD_Pos 0òPAE_WORD_PAE_WORD_Msk (0xffffffffU << PAE_WORD_PAE_WORD_Pos)`T ..\Drivers\..\Core\Include\fm33a0xxev_pae.hFM33A0XXEV.h¼


..\Drivers\fm33a0xxev_pae.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM³´µ__FM33A0XXEV_HASH_H HASH_CSR_START_Pos 7HASH_CSR_START_Msk (0x1U << HASH_CSR_START_Pos)HASH_CSR_BUSY_Pos 6HASH_CSR_BUSY_Msk (0x1U << HASH_CSR_BUSY_Pos)HASH_CSR_HASHSEL_Pos 1 HASH_CSR_HASHSEL_Msk (0x1U << HASH_CSR_HASHSEL_Pos)!HASH_CSR_HASHSEL_SHA256 (0x0U << HASH_CSR_HASHSEL_Pos)"HASH_CSR_HASHSEL_SHA1 (0x1U << HASH_CSR_HASHSEL_Pos)$HASH_DTR_DATA_TYPE_Pos 0+HASH_DTR_DATA_TYPE_Msk (0x3U << HASH_DTR_DATA_TYPE_Pos),HASH_DTR_DATA_TYPE_NONE (0x0U << HASH_DTR_DATA_TYPE_Pos)-HASH_DTR_DATA_TYPE_HALFWORD (0x1U << HASH_DTR_DATA_TYPE_Pos).HASH_DTR_DATA_TYPE_BYTE (0x2U << HASH_DTR_DATA_TYPE_Pos)/HASH_DTR_DATA_TYPE_BIT (0x3U << HASH_DTR_DATA_TYPE_Pos)`U ..\Drivers\..\Core\Include\fm33a0xxev_hash.hFM33A0XXEV.h¼


..\Drivers\fm33a0xxev_hash.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM·¸¹__FM33A0XXEV_QSPI_H )QSPI_CR_PRESCALER_Pos 24*QSPI_CR_PRESCALER_Msk (0xffU << QSPI_CR_PRESCALER_Pos),QSPI_CR_PMM_Pos 23/QSPI_CR_PMM_Msk (0x1U << QSPI_CR_PMM_Pos)0QSPI_CR_PMM_AND (0x0U << QSPI_CR_PMM_Pos)1QSPI_CR_PMM_OR (0x1U << QSPI_CR_PMM_Pos)3QSPI_CR_TOIE_Pos 206QSPI_CR_TOIE_Msk (0x1U << QSPI_CR_TOIE_Pos):QSPI_CR_SMIE_Pos 19=QSPI_CR_SMIE_Msk (0x1U << QSPI_CR_SMIE_Pos)AQSPI_CR_FTIE_Pos 18DQSPI_CR_FTIE_Msk (0x1U << QSPI_CR_FTIE_Pos)HQSPI_CR_TCIE_Pos 17KQSPI_CR_TCIE_Msk (0x1U << QSPI_CR_TCIE_Pos)OQSPI_CR_TEIE_Pos 16RQSPI_CR_TEIE_Msk (0x1U << QSPI_CR_TEIE_Pos)VQSPI_CR_FIFOTHR_Pos 8aQSPI_CR_FIFOTHR_Msk (0xfU << QSPI_CR_FIFOTHR_Pos)bQSPI_CR_FIFOTHR_1 (0x0U << QSPI_CR_FIFOTHR_Pos)cQSPI_CR_FIFOTHR_2 (0x1U << QSPI_CR_FIFOTHR_Pos)dQSPI_CR_FIFOTHR_3 (0x2U << QSPI_CR_FIFOTHR_Pos)eQSPI_CR_FIFOTHR_4 (0x3U << QSPI_CR_FIFOTHR_Pos)fQSPI_CR_FIFOTHR_5 (0x4U << QSPI_CR_FIFOTHR_Pos)gQSPI_CR_FIFOTHR_6 (0x5U << QSPI_CR_FIFOTHR_Pos)hQSPI_CR_FIFOTHR_7 (0x6U << QSPI_CR_FIFOTHR_Pos)iQSPI_CR_FIFOTHR_8 (0x7U << QSPI_CR_FIFOTHR_Pos)jQSPI_CR_FIFOTHR_9 (0x8U << QSPI_CR_FIFOTHR_Pos)kQSPI_CR_FIFOTHR_10 (0x9U << QSPI_CR_FIFOTHR_Pos)lQSPI_CR_FIFOTHR_11 (0x10U << QSPI_CR_FIFOTHR_Pos)mQSPI_CR_FIFOTHR_12 (0x11U << QSPI_CR_FIFOTHR_Pos)nQSPI_CR_FIFOTHR_13 (0x12U << QSPI_CR_FIFOTHR_Pos)oQSPI_CR_FIFOTHR_14 (0x13U << QSPI_CR_FIFOTHR_Pos)pQSPI_CR_FIFOTHR_15 (0x14U << QSPI_CR_FIFOTHR_Pos)qQSPI_CR_FIFOTHR_16 (0x15U << QSPI_CR_FIFOTHR_Pos)sQSPI_CR_SSHFT_Pos 4vQSPI_CR_SSHFT_Msk (0x1U << QSPI_CR_SSHFT_Pos)zQSPI_CR_TCEN_Pos 3~QSPI_CR_TCEN_Msk (0x1U << QSPI_CR_TCEN_Pos)‚QSPI_CR_DMAEN_Pos 2…QSPI_CR_DMAEN_Msk (0x1U << QSPI_CR_DMAEN_Pos)‰QSPI_CR_ABORT_Pos 1ŠQSPI_CR_ABORT_Msk (0x1U << QSPI_CR_ABORT_Pos)ŒQSPI_CR_EN_Pos 0QSPI_CR_EN_Msk (0x1U << QSPI_CR_EN_Pos)“QSPI_CFG_CSHT_Pos 8˜QSPI_CFG_CSHT_Msk (0x7U << QSPI_CFG_CSHT_Pos)™QSPI_CFG_CSHT_1CYCLE (0x0U << QSPI_CFG_CSHT_Pos)šQSPI_CFG_CSHT_2CYCLES (0x1U << QSPI_CFG_CSHT_Pos)›QSPI_CFG_CSHT_3CYCLES (0x2U << QSPI_CFG_CSHT_Pos)œQSPI_CFG_CSHT_4CYCLES (0x3U << QSPI_CFG_CSHT_Pos)QSPI_CFG_CSHT_5CYCLES (0x4U << QSPI_CFG_CSHT_Pos)žQSPI_CFG_CSHT_6CYCLES (0x5U << QSPI_CFG_CSHT_Pos)ŸQSPI_CFG_CSHT_7CYCLES (0x6U << QSPI_CFG_CSHT_Pos) QSPI_CFG_CSHT_8CYCLES (0x7U << QSPI_CFG_CSHT_Pos)¢QSPI_CFG_CKMODE_Pos 0¥QSPI_CFG_CKMODE_Msk (0x1U << QSPI_CFG_CKMODE_Pos)¦QSPI_CFG_CKMODE_MODE0 (0x0U << QSPI_CFG_CKMODE_Pos)§QSPI_CFG_CKMODE_MODE3 (0x1U << QSPI_CFG_CKMODE_Pos)©QSPI_SR_FIFOLVL_Pos 8¬QSPI_SR_FIFOLVL_Msk (0x1fU << QSPI_SR_FIFOLVL_Pos)®QSPI_SR_BUSY_Pos 5¯QSPI_SR_BUSY_Msk (0x1U << QSPI_SR_BUSY_Pos)±QSPI_SR_TOF_Pos 4²QSPI_SR_TOF_Msk (0x1U << QSPI_SR_TOF_Pos)´QSPI_SR_SMF_Pos 3µQSPI_SR_SMF_Msk (0x1U << QSPI_SR_SMF_Pos)·QSPI_SR_FTF_Pos 2¹QSPI_SR_FTF_Msk (0x1U << QSPI_SR_FTF_Pos)»QSPI_SR_TCF_Pos 1¼QSPI_SR_TCF_Msk (0x1U << QSPI_SR_TCF_Pos)¾QSPI_DATALEN_QSPI_DATALEN_Pos 0¿QSPI_DATALEN_QSPI_DATALEN_Msk (0xffffffffU << QSPI_DATALEN_QSPI_DATALEN_Pos)ÁQSPI_CCR_CRM_Pos 28ÄQSPI_CCR_CRM_Msk (0x1U << QSPI_CCR_CRM_Pos)ÅQSPI_CCR_CRM_ALWAYS (0x0U << QSPI_CCR_CRM_Pos)ÆQSPI_CCR_CRM_ONLY (0x1U << QSPI_CCR_CRM_Pos)ÈQSPI_CCR_OPMODE_Pos 26ÍQSPI_CCR_OPMODE_Msk (0x3U << QSPI_CCR_OPMODE_Pos)ÎQSPI_CCR_OPMODE_WRITE (0x0U << QSPI_CCR_OPMODE_Pos)ÏQSPI_CCR_OPMODE_READ (0x1U << QSPI_CCR_OPMODE_Pos)ÐQSPI_CCR_OPMODE_QUERY (0x2U << QSPI_CCR_OPMODE_Pos)ÑQSPI_CCR_OPMODE_MAP (0x3U << QSPI_CCR_OPMODE_Pos)ÓQSPI_CCR_DMODE_Pos 24ØQSPI_CCR_DMODE_Msk (0x3U << QSPI_CCR_DMODE_Pos)ÙQSPI_CCR_DMODE_NONE (0x0U << QSPI_CCR_DMODE_Pos)ÚQSPI_CCR_DMODE_SINGLE (0x1U << QSPI_CCR_DMODE_Pos)ÛQSPI_CCR_DMODE_DOUBLE (0x2U << QSPI_CCR_DMODE_Pos)ÜQSPI_CCR_DMODE_FOUR (0x3U << QSPI_CCR_DMODE_Pos)ÞQSPI_CCR_DUMCYC_Pos 18ßQSPI_CCR_DUMCYC_Msk (0x1fU << QSPI_CCR_DUMCYC_Pos)áQSPI_CCR_ABSIZE_Pos 16æQSPI_CCR_ABSIZE_Msk (0x3U << QSPI_CCR_ABSIZE_Pos)çQSPI_CCR_ABSIZE_8BITS (0x0U << QSPI_CCR_ABSIZE_Pos)èQSPI_CCR_ABSIZE_16BITS (0x1U << QSPI_CCR_ABSIZE_Pos)éQSPI_CCR_ABSIZE_24BITS (0x2U << QSPI_CCR_ABSIZE_Pos)êQSPI_CCR_ABSIZE_32BITS (0x3U << QSPI_CCR_ABSIZE_Pos)ìQSPI_CCR_ABMODE_Pos 14ñQSPI_CCR_ABMODE_Msk (0x3U << QSPI_CCR_ABMODE_Pos)òQSPI_CCR_ABMODE_NONE (0x0U << QSPI_CCR_ABMODE_Pos)óQSPI_CCR_ABMODE_SINGLE (0x1U << QSPI_CCR_ABMODE_Pos)ôQSPI_CCR_ABMODE_DOUBLE (0x2U << QSPI_CCR_ABMODE_Pos)õQSPI_CCR_ABMODE_FOUR (0x3U << QSPI_CCR_ABMODE_Pos)÷QSPI_CCR_ADSIZE_Pos 12üQSPI_CCR_ADSIZE_Msk (0x3U << QSPI_CCR_ADSIZE_Pos)ýQSPI_CCR_ADSIZE_8BITS (0x0U << QSPI_CCR_ADSIZE_Pos)þQSPI_CCR_ADSIZE_16BITS (0x1U << QSPI_CCR_ADSIZE_Pos)ÿQSPI_CCR_ADSIZE_24BITS (0x2U << QSPI_CCR_ADSIZE_Pos)€QSPI_CCR_ADSIZE_32BITS (0x3U << QSPI_CCR_ADSIZE_Pos)‚QSPI_CCR_ADMODE_Pos 10‡QSPI_CCR_ADMODE_Msk (0x3U << QSPI_CCR_ADMODE_Pos)ˆQSPI_CCR_ADMODE_NONE (0x0U << QSPI_CCR_ADMODE_Pos)‰QSPI_CCR_ADMODE_SINGLE (0x1U << QSPI_CCR_ADMODE_Pos)ŠQSPI_CCR_ADMODE_DOUBLE (0x2U << QSPI_CCR_ADMODE_Pos)‹QSPI_CCR_ADMODE_FOUR (0x3U << QSPI_CCR_ADMODE_Pos)QSPI_CCR_IMODE_Pos 8’QSPI_CCR_IMODE_Msk (0x3U << QSPI_CCR_IMODE_Pos)“QSPI_CCR_IMODE_NONE (0x0U << QSPI_CCR_IMODE_Pos)”QSPI_CCR_IMODE_SINGLE (0x1U << QSPI_CCR_IMODE_Pos)•QSPI_CCR_IMODE_DOUBLE (0x2U << QSPI_CCR_IMODE_Pos)–QSPI_CCR_IMODE_FOUR (0x3U << QSPI_CCR_IMODE_Pos)˜QSPI_CCR_INSTRUCTION_Pos 0™QSPI_CCR_INSTRUCTION_Msk (0xffU << QSPI_CCR_INSTRUCTION_Pos)›QSPI_ADDR_QSPI_ADDR_Pos 0œQSPI_ADDR_QSPI_ADDR_Msk (0xffffffffU << QSPI_ADDR_QSPI_ADDR_Pos)žQSPI_ABR_QSPI_ABR_Pos 0ŸQSPI_ABR_QSPI_ABR_Msk (0xffffffffU << QSPI_ABR_QSPI_ABR_Pos)¡QSPI_DR_QSPI_DATA_Pos 0¥QSPI_DR_QSPI_DATA_Msk (0xffffffffU << QSPI_DR_QSPI_DATA_Pos)§QSPI_SMSK_QSPI_SMSK_Pos 0¨QSPI_SMSK_QSPI_SMSK_Msk (0xffffffffU << QSPI_SMSK_QSPI_SMSK_Pos)ªQSPI_SMAT_QSPI_SMAT_Pos 0¬QSPI_SMAT_QSPI_SMAT_Msk (0xffffffffU << QSPI_SMAT_QSPI_SMAT_Pos)®QSPI_PITV_QSPI_PITV_Pos 0¯QSPI_PITV_QSPI_PITV_Msk (0xffffU << QSPI_PITV_QSPI_PITV_Pos)±QSPI_TO_QSPI_TO_Pos 0³QSPI_TO_QSPI_TO_Msk (0xffffU << QSPI_TO_QSPI_TO_Pos)µQSPI_CCR_DUMCYC_SET(value) ((value << QSPI_CCR_DUMCYC_Pos) & QSPI_CCR_DUMCYC_Msk)¶QSPI_CCR_DUMCYC_GET(value) ((value >> QSPI_CCR_DUMCYC_Pos) & QSPI_CCR_DUMCYC_Msk)·QSPI_CCR_INSTRUCTION_SET(value) ((value << QSPI_CCR_INSTRUCTION_Pos) & QSPI_CCR_INSTRUCTION_Msk)¸QSPI_CCR_INSTRUCTION_GET(value) ((value >> QSPI_CCR_INSTRUCTION_Pos) & QSPI_CCR_INSTRUCTION_Msk)`U ..\Drivers\..\Core\Include\fm33a0xxev_qspi.hFM33A0XXEV.h¸


..\Drivers\fm33a0xxev_qspi.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM* (Instructionf#Addressf#AlternateBytef#AddressSizef#AlternateByteSizef#DummyCyclesf#InstructionModef#AddressModef#AlternateByteModef# DataModef#$PQSPI_CmdTypeDef¾'»¼½__FM33A0XXEV_BT_H BTx_CR1_CHEN_Pos 7BTx_CR1_CHEN_Msk (0x1U << BTx_CR1_CHEN_Pos)BTx_CR1_CLEN_Pos 6 BTx_CR1_CLEN_Msk (0x1U << BTx_CR1_CLEN_Pos)$BTx_CR1_MODE_Pos 5'BTx_CR1_MODE_Msk (0x1U << BTx_CR1_MODE_Pos)(BTx_CR1_MODE_CAPTURE (0x1U << BTx_CR1_MODE_Pos))BTx_CR1_MODE_COUNTER (0x0U << BTx_CR1_MODE_Pos)+BTx_CR1_EDGESEL_Pos 4/BTx_CR1_EDGESEL_Msk (0x1U << BTx_CR1_EDGESEL_Pos)0BTx_CR1_EDGESEL_FALLING (0x1U << BTx_CR1_EDGESEL_Pos)1BTx_CR1_EDGESEL_RISING (0x0U << BTx_CR1_EDGESEL_Pos)3BTx_CR1_CAPMOD_Pos 36BTx_CR1_CAPMOD_Msk (0x1U << BTx_CR1_CAPMOD_Pos)7BTx_CR1_CAPMOD_PULSE (0x1U << BTx_CR1_CAPMOD_Pos)8BTx_CR1_CAPMOD_CYCLE (0x0U << BTx_CR1_CAPMOD_Pos):BTx_CR1_CAPCLR_Pos 2=BTx_CR1_CAPCLR_Msk (0x1U << BTx_CR1_CAPCLR_Pos)ABTx_CR1_CAPONCE_Pos 1DBTx_CR1_CAPONCE_Msk (0x1U << BTx_CR1_CAPONCE_Pos)EBTx_CR1_CAPONCE_SINGLE (0x1U << BTx_CR1_CAPONCE_Pos)FBTx_CR1_CAPONCE_CONTINUE (0x0U << BTx_CR1_CAPONCE_Pos)HBTx_CR1_PWM_Pos 0KBTx_CR1_PWM_Msk (0x1U << BTx_CR1_PWM_Pos)OBTx_CR2_SIG2SEL_Pos 7RBTx_CR2_SIG2SEL_Msk (0x1U << BTx_CR2_SIG2SEL_Pos)SBTx_CR2_SIG2SEL_GROUP2 (0x1U << BTx_CR2_SIG2SEL_Pos)TBTx_CR2_SIG2SEL_GROUP1 (0x0U << BTx_CR2_SIG2SEL_Pos)VBTx_CR2_SIG1SEL_Pos 6YBTx_CR2_SIG1SEL_Msk (0x1U << BTx_CR2_SIG1SEL_Pos)ZBTx_CR2_SIG1SEL_GROUP1 (0x1U << BTx_CR2_SIG1SEL_Pos)[BTx_CR2_SIG1SEL_GROUP2 (0x0U << BTx_CR2_SIG1SEL_Pos)]BTx_CR2_CNTHSEL_Pos 4aBTx_CR2_CNTHSEL_Msk (0x3U << BTx_CR2_CNTHSEL_Pos)bBTx_CR2_CNTHSEL_COUNTER (0x0U << BTx_CR2_CNTHSEL_Pos)cBTx_CR2_CNTHSEL_CAPTURE (0x1U << BTx_CR2_CNTHSEL_Pos)dBTx_CR2_CNTHSEL_INNER (0x2U << BTx_CR2_CNTHSEL_Pos)fBTx_CR2_DIREN_Pos 3iBTx_CR2_DIREN_Msk (0x1U << BTx_CR2_DIREN_Pos)mBTx_CR2_STDIR_Pos 2oBTx_CR2_STDIR_Msk (0x1U << BTx_CR2_STDIR_Pos)rBTx_CR2_SRCSEL_Pos 1uBTx_CR2_SRCSEL_Msk (0x1U << BTx_CR2_SRCSEL_Pos)xBTx_CR2_DIRPO_Pos 0{BTx_CR2_DIRPO_Msk (0x1U << BTx_CR2_DIRPO_Pos)|BTx_CR2_DIRPO_REVERSE (0x1U << BTx_CR2_DIRPO_Pos)}BTx_CR2_DIRPO_NON (0x0U << BTx_CR2_DIRPO_Pos)BTx_CFGR1_RTCSEL2_Pos 6„BTx_CFGR1_RTCSEL2_Msk (0x3U << BTx_CFGR1_RTCSEL2_Pos)…BTx_CFGR1_RTCSEL2_32768HZ (0x0U << BTx_CFGR1_RTCSEL2_Pos)†BTx_CFGR1_RTCSEL2_RTC_SEC (0x1U << BTx_CFGR1_RTCSEL2_Pos)‡BTx_CFGR1_RTCSEL2_RTC_MIN (0x2U << BTx_CFGR1_RTCSEL2_Pos)‰BTx_CFGR1_RTCSEL1_Pos 4ŽBTx_CFGR1_RTCSEL1_Msk (0x3U << BTx_CFGR1_RTCSEL1_Pos)BTx_CFGR1_RTCSEL1_32768HZ (0x0U << BTx_CFGR1_RTCSEL1_Pos)BTx_CFGR1_RTCSEL1_RTC_SEC (0x1U << BTx_CFGR1_RTCSEL1_Pos)‘BTx_CFGR1_RTCSEL1_RTC_MIN (0x2U << BTx_CFGR1_RTCSEL1_Pos)“BTx_CFGR1_GRP2SEL_Pos 2™BTx_CFGR1_GRP2SEL_Msk (0x3U << BTx_CFGR1_GRP2SEL_Pos)šBTx_CFGR1_GRP2SEL_APBCLK (0x0U << BTx_CFGR1_GRP2SEL_Pos)›BTx_CFGR1_GRP2SEL_RTCOUT2 (0x1U << BTx_CFGR1_GRP2SEL_Pos)œBTx_CFGR1_GRP2SEL_IN_SIG2 (0x2U << BTx_CFGR1_GRP2SEL_Pos)BTx_CFGR1_GRP2SEL_EX_SIG2 (0x3U << BTx_CFGR1_GRP2SEL_Pos)ŸBTx_CFGR1_GRP1SEL_Pos 0¥BTx_CFGR1_GRP1SEL_Msk (0x3U << BTx_CFGR1_GRP1SEL_Pos)¦BTx_CFGR1_GRP1SEL_APBCLK (0x0U << BTx_CFGR1_GRP1SEL_Pos)§BTx_CFGR1_GRP1SEL_RTCOUT1 (0x1U << BTx_CFGR1_GRP1SEL_Pos)¨BTx_CFGR1_GRP1SEL_IN_SIG1 (0x2U << BTx_CFGR1_GRP1SEL_Pos)©BTx_CFGR1_GRP1SEL_EX_SIG1 (0x3U << BTx_CFGR1_GRP1SEL_Pos)«BTx_CFGR2_EXSEL2_Pos 6°BTx_CFGR2_EXSEL2_Msk (0x3U << BTx_CFGR2_EXSEL2_Pos)±BTx_CFGR2_EXSEL2_IN0 (0x0U << BTx_CFGR2_EXSEL2_Pos)²BTx_CFGR2_EXSEL2_IN1 (0x1U << BTx_CFGR2_EXSEL2_Pos)³BTx_CFGR2_EXSEL2_IN2 (0x2U << BTx_CFGR2_EXSEL2_Pos)´BTx_CFGR2_EXSEL2_IN3 (0x3U << BTx_CFGR2_EXSEL2_Pos)¶BTx_CFGR2_EXSEL1_Pos 4»BTx_CFGR2_EXSEL1_Msk (0x3U << BTx_CFGR2_EXSEL1_Pos)¼BTx_CFGR2_EXSEL1_IN0 (0x0U << BTx_CFGR2_EXSEL1_Pos)½BTx_CFGR2_EXSEL1_IN1 (0x1U << BTx_CFGR2_EXSEL1_Pos)¾BTx_CFGR2_EXSEL1_IN2 (0x2U << BTx_CFGR2_EXSEL1_Pos)¿BTx_CFGR2_EXSEL1_IN3 (0x3U << BTx_CFGR2_EXSEL1_Pos)ÁBTx_CFGR2_INSEL2_Pos 2ÆBTx_CFGR2_INSEL2_Msk (0x3U << BTx_CFGR2_INSEL2_Pos)ÇBTx_CFGR2_INSEL2_RX3 (0x0U << BTx_CFGR2_INSEL2_Pos)ÈBTx_CFGR2_INSEL2_RX4 (0x1U << BTx_CFGR2_INSEL2_Pos)ÉBTx_CFGR2_INSEL2_RX5 (0x2U << BTx_CFGR2_INSEL2_Pos)ÊBTx_CFGR2_INSEL2_RCLP (0x3U << BTx_CFGR2_INSEL2_Pos)ÌBTx_CFGR2_INSEL1_Pos 0ÑBTx_CFGR2_INSEL1_Msk (0x3U << BTx_CFGR2_INSEL1_Pos)ÒBTx_CFGR2_INSEL1_RX0 (0x0U << BTx_CFGR2_INSEL1_Pos)ÓBTx_CFGR2_INSEL1_RX1 (0x1U << BTx_CFGR2_INSEL1_Pos)ÔBTx_CFGR2_INSEL1_RX2 (0x2U << BTx_CFGR2_INSEL1_Pos)ÕBTx_CFGR2_INSEL1_RCLP (0x3U << BTx_CFGR2_INSEL1_Pos)×BTx_PRES_PRESCALE_Pos 0ÙBTx_PRES_PRESCALE_Msk (0xffU << BTx_PRES_PRESCALE_Pos)ÛBTx_LOADCR_LHEN_Pos 4ÝBTx_LOADCR_LHEN_Msk (0x1U << BTx_LOADCR_LHEN_Pos)ßBTx_LOADCR_LLEN_Pos 0áBTx_LOADCR_LLEN_Msk (0x1U << BTx_LOADCR_LLEN_Pos)ãBTx_CNTL_CNTL_Pos 0åBTx_CNTL_CNTL_Msk (0xffU << BTx_CNTL_CNTL_Pos)çBTx_CNTH_CNTH_Pos 0éBTx_CNTH_CNTH_Msk (0xffU << BTx_CNTH_CNTH_Pos)ëBTx_PRESET_PRESETH_Pos 8íBTx_PRESET_PRESETH_Msk (0xffU << BTx_PRESET_PRESETH_Pos)ïBTx_PRESET_PRESETL_Pos 0ñBTx_PRESET_PRESETL_Msk (0xffU << BTx_PRESET_PRESETL_Pos)óBTx_LOADL_LOADL_Pos 0õBTx_LOADL_LOADL_Msk (0xffU << BTx_LOADL_LOADL_Pos)÷BTx_LOADH_LOADH_Pos 0ùBTx_LOADH_LOADH_Msk (0xffU << BTx_LOADH_LOADH_Pos)ûBTx_CMPL_CMPL_Pos 0ýBTx_CMPL_CMPL_Msk (0xffU << BTx_CMPL_CMPL_Pos)ÿBTx_CMPH_CMPH_Pos 0BTx_CMPH_CMPH_Msk (0xffU << BTx_CMPH_CMPH_Pos)ƒBTx_OUTCNT_OUTCNT_Pos 0…BTx_OUTCNT_OUTCNT_Msk (0xfffU << BTx_OUTCNT_OUTCNT_Pos)‡BTx_OCR_OUTCLR_Pos 5ˆBTx_OCR_OUTCLR_Msk (0x1U << BTx_OCR_OUTCLR_Pos)‰BTx_OCR_OUTCLR_INVALID (0x0U << BTx_OCR_OUTCLR_Pos)ŠBTx_OCR_OUTCLR_CLEAR (0x1U << BTx_OCR_OUTCLR_Pos)ŒBTx_OCR_OUTINV_Pos 4BTx_OCR_OUTINV_Msk (0x1U << BTx_OCR_OUTINV_Pos)ŽBTx_OCR_OUTINV_NORMAL (0x0U << BTx_OCR_OUTINV_Pos)BTx_OCR_OUTINV_REVERSE (0x1U << BTx_OCR_OUTINV_Pos)‘BTx_OCR_OUTMOD_Pos 3’BTx_OCR_OUTMOD_Msk (0x1U << BTx_OCR_OUTMOD_Pos)“BTx_OCR_OUTMOD_PULSE_SHIFT (0x0U << BTx_OCR_OUTMOD_Pos)”BTx_OCR_OUTMOD_NEG (0x1U << BTx_OCR_OUTMOD_Pos)–BTx_OCR_OUTSEL_Pos 0—BTx_OCR_OUTSEL_Msk (0x7U << BTx_OCR_OUTSEL_Pos)˜BTx_OCR_OUTSEL_HIGH (0x0U << BTx_OCR_OUTSEL_Pos)™BTx_OCR_OUTSEL_LOW (0x1U << BTx_OCR_OUTSEL_Pos)šBTx_OCR_OUTSEL_GROUP1 (0x2U << BTx_OCR_OUTSEL_Pos)›BTx_OCR_OUTSEL_GROUP2 (0x3U << BTx_OCR_OUTSEL_Pos)œBTx_OCR_OUTSEL_PWM (0x4U << BTx_OCR_OUTSEL_Pos)žBTx_IER_CMPHIE_Pos 4¡BTx_IER_CMPHIE_Msk (0x1U << BTx_IER_CMPHIE_Pos)£BTx_IER_CMPLIE_Pos 3¦BTx_IER_CMPLIE_Msk (0x1U << BTx_IER_CMPLIE_Pos)¨BTx_IER_OVHIE_Pos 2«BTx_IER_OVHIE_Msk (0x1U << BTx_IER_OVHIE_Pos)­BTx_IER_OVLIE_Pos 1°BTx_IER_OVLIE_Msk (0x1U << BTx_IER_OVLIE_Pos)²BTx_IER_CAPIE_Pos 0µBTx_IER_CAPIE_Msk (0x1U << BTx_IER_CAPIE_Pos)·BTx_ISR_EDGESTA_Pos 5ºBTx_ISR_EDGESTA_Msk (0x1U << BTx_ISR_EDGESTA_Pos)¼BTx_ISR_CMPHIF_Pos 4¿BTx_ISR_CMPHIF_Msk (0x1U << BTx_ISR_CMPHIF_Pos)ÁBTx_ISR_CMPLIF_Pos 3ÄBTx_ISR_CMPLIF_Msk (0x1U << BTx_ISR_CMPLIF_Pos)ÆBTx_ISR_OVHIF_Pos 2ÉBTx_ISR_OVHIF_Msk (0x1U << BTx_ISR_OVHIF_Pos)ËBTx_ISR_OVLIF_Pos 1ÎBTx_ISR_OVLIF_Msk (0x1U << BTx_ISR_OVLIF_Pos)ÐBTx_ISR_CAPIF_Pos 0ÓBTx_ISR_CAPIF_Msk (0x1U << BTx_ISR_CAPIF_Pos)\S ..\Drivers\..\Core\Include\fm33a0xxev_bt.hFM33A0XXEV.h¼


..\Drivers\fm33a0xxev_bt.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM¿ÀÁ__FM33A0XXEV_ET_H ETx_CR_OPOL_Pos 10ETx_CR_OPOL_Msk (0x1U << ETx_CR_OPOL_Pos)ETx_CR_OPOL_NORMAL (0x0U << ETx_CR_OPOL_Pos)ETx_CR_OPOL_REVERSE (0x1U << ETx_CR_OPOL_Pos) ETx_CR_EXFLT_Pos 9#ETx_CR_EXFLT_Msk (0x1U << ETx_CR_EXFLT_Pos)$ETx_CR_EXFLT_OPEN (0x1U << ETx_CR_EXFLT_Pos)%ETx_CR_EXFLT_CLOSE (0x0U << ETx_CR_EXFLT_Pos)'ETx_CR_PWM_Pos 8*ETx_CR_PWM_Msk (0x1U << ETx_CR_PWM_Pos),ETx_CR_CEN_Pos 7/ETx_CR_CEN_Msk (0x1U << ETx_CR_CEN_Pos)1ETx_CR_MOD_Pos 64ETx_CR_MOD_Msk (0x1U << ETx_CR_MOD_Pos)5ETx_CR_MOD_CAPTURE (0x1U << ETx_CR_MOD_Pos)6ETx_CR_MOD_COUNTER (0x0U << ETx_CR_MOD_Pos)8ETx_CR_CASEN_Pos 5;ETx_CR_CASEN_Msk (0x1U << ETx_CR_CASEN_Pos)<ETx_CR_CASEN_32BITS (0x1U << ETx_CR_CASEN_Pos)=ETx_CR_CASEN_16BITS (0x0U << ETx_CR_CASEN_Pos)?ETx_CR_EDGESEL_Pos 4CETx_CR_EDGESEL_Msk (0x1U << ETx_CR_EDGESEL_Pos)DETx_CR_EDGESEL_FALLING (0x1U << ETx_CR_EDGESEL_Pos)EETx_CR_EDGESEL_RISING (0x0U << ETx_CR_EDGESEL_Pos)GETx_CR_CAPMOD_Pos 3JETx_CR_CAPMOD_Msk (0x1U << ETx_CR_CAPMOD_Pos)KETx_CR_CAPMOD_PULSE (0x1U << ETx_CR_CAPMOD_Pos)LETx_CR_CAPMOD_CYCLE (0x0U << ETx_CR_CAPMOD_Pos)NETx_CR_CAPCLR_Pos 2QETx_CR_CAPCLR_Msk (0x1U << ETx_CR_CAPCLR_Pos)TETx_CR_CAPONCE_Pos 1WETx_CR_CAPONCE_Msk (0x1U << ETx_CR_CAPONCE_Pos)XETx_CR_CAPONCE_SINGLE (0x1U << ETx_CR_CAPONCE_Pos)YETx_CR_CAPONCE_CONTINUE (0x0U << ETx_CR_CAPONCE_Pos)[ETx_CR_CAPEDGE_Pos 0^ETx_CR_CAPEDGE_Msk (0x1U << ETx_CR_CAPEDGE_Pos)_ETx_CR_CAPEDGE_FALLING (0x1U << ETx_CR_CAPEDGE_Pos)`ETx_CR_CAPEDGE_RISING (0x0U << ETx_CR_CAPEDGE_Pos)bETx_INSR_SIG2SEL_Pos 7eETx_INSR_SIG2SEL_Msk (0x1U << ETx_INSR_SIG2SEL_Pos)fETx_INSR_SIG2SEL_GROUP1 (0x1U << ETx_INSR_SIG2SEL_Pos)gETx_INSR_SIG2SEL_GROUP2 (0x0U << ETx_INSR_SIG2SEL_Pos)iETx_INSR_SIG1SEL_Pos 6lETx_INSR_SIG1SEL_Msk (0x1U << ETx_INSR_SIG1SEL_Pos)mETx_INSR_SIG1SEL_GROUP2 (0x1U << ETx_INSR_SIG1SEL_Pos)nETx_INSR_SIG1SEL_GROUP1 (0x0U << ETx_INSR_SIG1SEL_Pos)pETx_INSR_GRP2SEL_Pos 2“ETx_INSR_GRP2SEL_Msk (0x7U << ETx_INSR_GRP2SEL_Pos)”ETx_INSR_GRP2SEL_ET1_UART0_RX (0x0U << ETx_INSR_GRP2SEL_Pos)•ETx_INSR_GRP2SEL_ET1_UART1_RX (0x1U << ETx_INSR_GRP2SEL_Pos)–ETx_INSR_GRP2SEL_ET1_XTLF (0x2U << ETx_INSR_GRP2SEL_Pos)—ETx_INSR_GRP2SEL_ET1_IN1 (0x3U << ETx_INSR_GRP2SEL_Pos)˜ETx_INSR_GRP2SEL_ET1_IN2 (0x4U << ETx_INSR_GRP2SEL_Pos)™ETx_INSR_GRP2SEL_ET1_CMP1O (0x5U << ETx_INSR_GRP2SEL_Pos)šETx_INSR_GRP2SEL_ET1_CMP2O (0x6U << ETx_INSR_GRP2SEL_Pos)›ETx_INSR_GRP2SEL_ET1_RCMF (0x7U << ETx_INSR_GRP2SEL_Pos)œETx_INSR_GRP2SEL_ET2_UART2_RX (0x0U << ETx_INSR_GRP2SEL_Pos)ETx_INSR_GRP2SEL_ET2_UART3_RX (0x1U << ETx_INSR_GRP2SEL_Pos)žETx_INSR_GRP2SEL_ET2_XTLF (0x2U << ETx_INSR_GRP2SEL_Pos)ŸETx_INSR_GRP2SEL_ET2_IN1 (0x3U << ETx_INSR_GRP2SEL_Pos) ETx_INSR_GRP2SEL_ET2_IN2 (0x4U << ETx_INSR_GRP2SEL_Pos)¡ETx_INSR_GRP2SEL_ET2_CMP1O (0x5U << ETx_INSR_GRP2SEL_Pos)¢ETx_INSR_GRP2SEL_ET2_CMP2O (0x6U << ETx_INSR_GRP2SEL_Pos)£ETx_INSR_GRP2SEL_ET2_RCMF (0x7U << ETx_INSR_GRP2SEL_Pos)¤ETx_INSR_GRP2SEL_ET3_IN1 (0x0U << ETx_INSR_GRP2SEL_Pos)¥ETx_INSR_GRP2SEL_ET3_XTLF (0x1U << ETx_INSR_GRP2SEL_Pos)¦ETx_INSR_GRP2SEL_ET3_UART4_RX (0x2U << ETx_INSR_GRP2SEL_Pos)§ETx_INSR_GRP2SEL_ET3_UART5_RX (0x3U << ETx_INSR_GRP2SEL_Pos)¨ETx_INSR_GRP2SEL_ET3_RTCSEC (0x4U << ETx_INSR_GRP2SEL_Pos)©ETx_INSR_GRP2SEL_ET4_IN (0x0U << ETx_INSR_GRP2SEL_Pos)ªETx_INSR_GRP2SEL_ET4_XTLF (0x1U << ETx_INSR_GRP2SEL_Pos)«ETx_INSR_GRP2SEL_ET4_UART_RX2 (0x2U << ETx_INSR_GRP2SEL_Pos)¬ETx_INSR_GRP2SEL_ET4_UART_RX0 (0x3U << ETx_INSR_GRP2SEL_Pos)­ETx_INSR_GRP2SEL_ET4_CMP1O (0x4U << ETx_INSR_GRP2SEL_Pos)®ETx_INSR_GRP2SEL_ET4_CMP2O (0x5U << ETx_INSR_GRP2SEL_Pos)¯ETx_INSR_GRP2SEL_ET4_RTCSEC (0x6U << ETx_INSR_GRP2SEL_Pos)°ETx_INSR_GRP2SEL_ET4_RCMF (0x7U << ETx_INSR_GRP2SEL_Pos)²ETx_INSR_GRP1SEL_Pos 0ÇETx_INSR_GRP1SEL_Msk (0x3U << ETx_INSR_GRP1SEL_Pos)ÈETx_INSR_GRP1SEL_ET1_APBCLK (0x0U << ETx_INSR_GRP1SEL_Pos)ÉETx_INSR_GRP1SEL_ET1_XTLF (0x1U << ETx_INSR_GRP1SEL_Pos)ÊETx_INSR_GRP1SEL_ET1_RCLP (0x2U << ETx_INSR_GRP1SEL_Pos)ËETx_INSR_GRP1SEL_ET1_IN0 (0x3U << ETx_INSR_GRP1SEL_Pos)ÌETx_INSR_GRP1SEL_ET2_APBCLK (0x0U << ETx_INSR_GRP1SEL_Pos)ÍETx_INSR_GRP1SEL_ET2_XTLF (0x1U << ETx_INSR_GRP1SEL_Pos)ÎETx_INSR_GRP1SEL_ET2_RCLP (0x2U << ETx_INSR_GRP1SEL_Pos)ÏETx_INSR_GRP1SEL_ET2_IN0 (0x3U << ETx_INSR_GRP1SEL_Pos)ÐETx_INSR_GRP1SEL_ET3_APBCLK (0x0U << ETx_INSR_GRP1SEL_Pos)ÑETx_INSR_GRP1SEL_ET3_IN0 (0x1U << ETx_INSR_GRP1SEL_Pos)ÒETx_INSR_GRP1SEL_ET3_RTCSEC (0x2U << ETx_INSR_GRP1SEL_Pos)ÓETx_INSR_GRP1SEL_ET3_RCLP (0x3U << ETx_INSR_GRP1SEL_Pos)ÔETx_INSR_GRP1SEL_ET4_APBCLK (0x0U << ETx_INSR_GRP1SEL_Pos)ÕETx_INSR_GRP1SEL_ET4_IN0 (0x1U << ETx_INSR_GRP1SEL_Pos)ÖETx_INSR_GRP1SEL_ET4_RTC64HZ (0x2U << ETx_INSR_GRP1SEL_Pos)×ETx_INSR_GRP1SEL_ET4_RCMF (0x3U << ETx_INSR_GRP1SEL_Pos)ÙETx_PSCR1_PRESCALE1_Pos 0ÛETx_PSCR1_PRESCALE1_Msk (0xffU << ETx_PSCR1_PRESCALE1_Pos)ÝETx_PSCR2_PRESCALE2_Pos 0ßETx_PSCR2_PRESCALE2_Msk (0xffU << ETx_PSCR2_PRESCALE2_Pos)áETx_IVR_INITVALUE_Pos 0âETx_IVR_INITVALUE_Msk (0xffffU << ETx_IVR_INITVALUE_Pos)äETx_CMPR_CMP_Pos 0æETx_CMPR_CMP_Msk (0xffffU << ETx_CMPR_CMP_Pos)èETx_IER_CMPIE_Pos 2ëETx_IER_CMPIE_Msk (0x1U << ETx_IER_CMPIE_Pos)íETx_IER_CAPIE_Pos 1ðETx_IER_CAPIE_Msk (0x1U << ETx_IER_CAPIE_Pos)òETx_IER_OVIE_Pos 0õETx_IER_OVIE_Msk (0x1U << ETx_IER_OVIE_Pos)÷ETx_ISR_CMPIF_Pos 3úETx_ISR_CMPIF_Msk (0x1U << ETx_ISR_CMPIF_Pos)üETx_ISR_EDGESTA_Pos 2ÿETx_ISR_EDGESTA_Msk (0x1U << ETx_ISR_EDGESTA_Pos)ETx_ISR_CAPIF_Pos 1„ETx_ISR_CAPIF_Msk (0x1U << ETx_ISR_CAPIF_Pos)†ETx_ISR_OVIF_Pos 0‰ETx_ISR_OVIF_Msk (0x1U << ETx_ISR_OVIF_Pos)‹ETCNTx_CNT_Pos 0ŒETCNTx_CNT_Msk (0xffffU << ETCNTx_CNT_Pos)\S ..\Drivers\..\Core\Include\fm33a0xxev_et.hFM33A0XXEV.h¼


..\Drivers\fm33a0xxev_et.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMÃÄÅ__FM33A0XXEV_VRTC_H HXVAR(object,addr) (*((object *) (addr)))const_rcmf_Trim HXVAR( uint32_t, 0x1FFFFB44 )const_rclp_Trim HXVAR( uint32_t, 0x1FFFFB20 )VRTC_PDRCR_CFG_Pos 0VRTC_PDRCR_CFG_Msk (0x1U << VRTC_PDRCR_CFG_Pos)"VRTC_RCMFCR_EN_Msk (0x1U << VRTC_RCMFCR_EN_Pos)&VRTC_RCMFCR_EN_Pos 7*VRTC_RCMFCR_EN_Msk (0x1U << VRTC_RCMFCR_EN_Pos).VRTC_RCMFCR_TRIM_Pos 0/VRTC_RCMFCR_TRIM_Msk (0x3fU << VRTC_RCMFCR_TRIM_Pos)1VRTC_RCLPCR_CHOPEN_Pos 12VRTC_RCLPCR_CHOPEN_Msk (0x1U << VRTC_RCLPCR_CHOPEN_Pos)4VRTC_RCLPCR_RCLP_OFF_Pos 08VRTC_RCLPCR_RCLP_OFF_Msk (0x1U << VRTC_RCLPCR_RCLP_OFF_Pos)<VRTC_RCLPTR_RCLP_TRIM_Pos 0?VRTC_RCLPTR_RCLP_TRIM_Msk (0xffU << VRTC_RCLPTR_RCLP_TRIM_Pos)AVRTC_XTLFCR_XTLFIPW_Pos 0BVRTC_XTLFCR_XTLFIPW_Msk (0xfU << VRTC_XTLFCR_XTLFIPW_Pos)CVRTC_XTLFCR_XTLFIPW_850NA (0x0U << VRTC_XTLFCR_XTLFIPW_Pos)DVRTC_XTLFCR_XTLFIPW_800NA (0x1U << VRTC_XTLFCR_XTLFIPW_Pos)EVRTC_XTLFCR_XTLFIPW_750NA (0x2U << VRTC_XTLFCR_XTLFIPW_Pos)FVRTC_XTLFCR_XTLFIPW_700NA (0x3U << VRTC_XTLFCR_XTLFIPW_Pos)GVRTC_XTLFCR_XTLFIPW_650NA (0x4U << VRTC_XTLFCR_XTLFIPW_Pos)HVRTC_XTLFCR_XTLFIPW_600NA (0x5U << VRTC_XTLFCR_XTLFIPW_Pos)IVRTC_XTLFCR_XTLFIPW_550NA (0x6U << VRTC_XTLFCR_XTLFIPW_Pos)JVRTC_XTLFCR_XTLFIPW_500NA (0x7U << VRTC_XTLFCR_XTLFIPW_Pos)KVRTC_XTLFCR_XTLFIPW_450NA (0x8U << VRTC_XTLFCR_XTLFIPW_Pos)LVRTC_XTLFCR_XTLFIPW_400NA (0x9U << VRTC_XTLFCR_XTLFIPW_Pos)MVRTC_XTLFCR_XTLFIPW_350NA (0xaU << VRTC_XTLFCR_XTLFIPW_Pos)NVRTC_XTLFCR_XTLFIPW_300NA (0xbU << VRTC_XTLFCR_XTLFIPW_Pos)OVRTC_XTLFCR_XTLFIPW_250NA (0xcU << VRTC_XTLFCR_XTLFIPW_Pos)PVRTC_XTLFCR_XTLFIPW_200NA (0xdU << VRTC_XTLFCR_XTLFIPW_Pos)QVRTC_XTLFCR_XTLFIPW_150NA (0xeU << VRTC_XTLFCR_XTLFIPW_Pos)RVRTC_XTLFCR_XTLFIPW_100NA (0xfU << VRTC_XTLFCR_XTLFIPW_Pos)TVRTC_ADCCR_CKS_Pos 1]VRTC_ADCCR_CKS_Msk (0x7U << VRTC_ADCCR_CKS_Pos)^VRTC_ADCCR_CKS_RCMF (0x0U << VRTC_ADCCR_CKS_Pos)_VRTC_ADCCR_CKS_RCMF_2 (0x1U << VRTC_ADCCR_CKS_Pos)`VRTC_ADCCR_CKS_RCMF_4 (0x2U << VRTC_ADCCR_CKS_Pos)aVRTC_ADCCR_CKS_RCMF_8 (0x3U << VRTC_ADCCR_CKS_Pos)bVRTC_ADCCR_CKS_RCMF_16 (0x4U << VRTC_ADCCR_CKS_Pos)cVRTC_ADCCR_CKS_RCMF_32 (0x5U << VRTC_ADCCR_CKS_Pos)dVRTC_ADCCR_CKS_RCLP (0x6U << VRTC_ADCCR_CKS_Pos)eVRTC_ADCCR_CKS_XTLF (0x7U << VRTC_ADCCR_CKS_Pos)gVRTC_ADCCR_CKE_Pos 0jVRTC_ADCCR_CKE_Msk (0x1U << VRTC_ADCCR_CKE_Pos)nVRTC_LFDIER_LFDET_IE_Pos 0oVRTC_LFDIER_LFDET_IE_Msk (0x1U << VRTC_LFDIER_LFDET_IE_Pos)qVRTC_LFDISR_LFDETO_Pos 1tVRTC_LFDISR_LFDETO_Msk (0x1U << VRTC_LFDISR_LFDETO_Pos)vVRTC_LFDISR_LFDET_IF_Pos 0wVRTC_LFDISR_LFDET_IF_Msk (0x1U << VRTC_LFDISR_LFDET_IF_Pos)`U ..\Drivers\..\Core\Include\fm33a0xxev_vrtc.hFM33A0XXEV.h¼


..\Drivers\fm33a0xxev_vrtc.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMÇÈÉ__FM33A0XXEV_CDIF_H CDIF_CR_INTF_EN_Pos 0CDIF_CR_INTF_EN_Msk (0xfU << CDIF_CR_INTF_EN_Pos)CDIF_CR_INTF_EN_ENABLE (0xAU << CDIF_CR_INTF_EN_Pos)CDIF_CR_INTF_EN_DISABLE (0x5U << CDIF_CR_INTF_EN_Pos)!CDIF_PSCR_PRSC_Pos 0"CDIF_PSCR_PRSC_Msk (0x7U << CDIF_PSCR_PRSC_Pos)#CDIF_PSCR_PRSC_DIV1 (0x0U)$CDIF_PSCR_PRSC_DIV2 (0x1U)%CDIF_PSCR_PRSC_DIV4 (0x2U)&CDIF_PSCR_PRSC_DIV8 (0x3U)'CDIF_PSCR_PRSC_DIV16 (0x4U)(CDIF_PSCR_PRSC_DIV32 (0x5U))CDIF_PSCR_PRSC_DIV64 (0x6U)*CDIF_PSCR_PRSC_DIV128 (0x7U)`U ..\Drivers\..\Core\Include\fm33a0xxev_cdif.hFM33A0XXEV.h¼


..\Drivers\fm33a0xxev_cdif.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMËÌÍ__INCLUDEALL_H__     


     


  !"#$ ÌÂ ..\Core\..\Drivers\fm33a0xxev_include_all.hfm33a0xxev_aes.hfm33a0xxev_adc.hfm33a0xxev_bstim.hfm33a0xxev_comp.hfm33a0xxev_rmu.hfm33a0xxev_crc.hfm33a0xxev_lcd.hfm33a0xxev_dma.hfm33a0xxev_gpio.hfm33a0xxev_i2c.hfm33a0xxev_iwdt.hfm33a0xxev_lpuart.hfm33a0xxev_flash.hfm33a0xxev_pmu.hfm33a0xxev_cmu.hfm33a0xxev_rtc.hfm33a0xxev_dbg.hfm33a0xxev_spi.hfm33a0xxev_rng.hfm33a0xxev_u7816.hfm33a0xxev_uart.hfm33a0xxev_lptim.hfm33a0xxev_wwdt.hfm33a0xxev_svd.hfm33a0xxev_pae.hfm33a0xxev_hash.hfm33a0xxev_qspi.hfm33a0xxev_bt.hfm33a0xxev_et.hfm33a0xxev_vrtc.hfm33a0xxev_cdif.hÀ


..\Core\fm33a0xxev_include_all.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMÏÐÑ__string_h __ARMCLIB_VERSION 5060037_ARMABI __declspec(__nothrow)__STRING_DECLS __CLIBNS$__CLIBNS 7NULL8NULL 0XM D:\Keil5\ARM\ARMCC\Bin\..\include\string.hstdio.h¤D:\Keil5\ARM\ARMCC\Bin\..\include\string.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]unsigned intPsize_tˆ5ÓÔÕBIT0 0x00000001BIT1 0x00000002BIT2 0x00000004BIT3 0x00000008BIT4 0x00000010BIT5 0x00000020    BIT6 0x00000040


BIT7 0x00000080BIT8 0x00000100BIT9 0x00000200 BIT10 0x00000400BIT11 0x00000800BIT12 0x00001000BIT13 0x00002000BIT14 0x00004000BIT15 0x00008000BIT16 0x00010000BIT17 0x00020000BIT18 0x00040000BIT19 0x00080000BIT20 0x00100000BIT21 0x00200000BIT22 0x00400000BIT23 0x00800000BIT24 0x01000000BIT25 0x02000000BIT26 0x04000000BIT27 0x08000000BIT28 0x10000000 BIT29 0x20000000!BIT30 0x40000000"BIT31 0x80000000#BITNO 0x00000000%B0000_0000 0x00&B0000_0001 0x01'B0000_0010 0x02(B0000_0011 0x03)B0000_0100 0x04*B0000_0101 0x05+B0000_0110 0x06,B0000_0111 0x07-B0000_1000 0x08.B0000_1001 0x09/B0000_1010 0x0A0B0000_1011 0x0B1B0000_1100 0x0C2B0000_1101 0x0D3B0000_1110 0x0E4B0000_1111 0x0F6B0001_0000 0x107B0001_0001 0x118B0001_0010 0x129B0001_0011 0x13:B0001_0100 0x14;B0001_0101 0x15<B0001_0110 0x16=B0001_0111 0x17>B0001_1000 0x18?B0001_1001 0x19@B0001_1010 0x1AAB0001_1011 0x1BBB0001_1100 0x1CCB0001_1101 0x1DDB0001_1110 0x1EEB0001_1111 0x1FGB0010_0000 0x20HB0010_0001 0x21IB0010_0010 0x22JB0010_0011 0x23KB0010_0100 0x24LB0010_0101 0x25MB0010_0110 0x26NB0010_0111 0x27OB0010_1000 0x28PB0010_1001 0x29QB0010_1010 0x2ARB0010_1011 0x2BSB0010_1100 0x2CTB0010_1101 0x2DUB0010_1110 0x2EVB0010_1111 0x2FXB0011_0000 0x30YB0011_0001 0x31ZB0011_0010 0x32[B0011_0011 0x33\B0011_0100 0x34]B0011_0101 0x35^B0011_0110 0x36_B0011_0111 0x37`B0011_1000 0x38aB0011_1001 0x39bB0011_1010 0x3AcB0011_1011 0x3BdB0011_1100 0x3CeB0011_1101 0x3DfB0011_1110 0x3EgB0011_1111 0x3FiB0100_0000 0x40jB0100_0001 0x41kB0100_0010 0x42lB0100_0011 0x43mB0100_0100 0x44nB0100_0101 0x45oB0100_0110 0x46pB0100_0111 0x47qB0100_1000 0x48rB0100_1001 0x49sB0100_1010 0x4AtB0100_1011 0x4BuB0100_1100 0x4CvB0100_1101 0x4DwB0100_1110 0x4ExB0100_1111 0x4FzB0101_0000 0x50{B0101_0001 0x51|B0101_0010 0x52}B0101_0011 0x53~B0101_0100 0x54B0101_0101 0x55€B0101_0110 0x56B0101_0111 0x57‚B0101_1000 0x58ƒB0101_1001 0x59„B0101_1010 0x5A…B0101_1011 0x5B†B0101_1100 0x5C‡B0101_1101 0x5DˆB0101_1110 0x5E‰B0101_1111 0x5F‹B0110_0000 0x60ŒB0110_0001 0x61B0110_0010 0x62ŽB0110_0011 0x63B0110_0100 0x64B0110_0101 0x65‘B0110_0110 0x66’B0110_0111 0x67“B0110_1000 0x68”B0110_1001 0x69•B0110_1010 0x6A–B0110_1011 0x6B—B0110_1100 0x6C˜B0110_1101 0x6D™B0110_1110 0x6EšB0110_1111 0x6FœB0111_0000 0x70B0111_0001 0x71žB0111_0010 0x72ŸB0111_0011 0x73 B0111_0100 0x74¡B0111_0101 0x75¢B0111_0110 0x76£B0111_0111 0x77¤B0111_1000 0x78¥B0111_1001 0x79¦B0111_1010 0x7A§B0111_1011 0x7B¨B0111_1100 0x7C©B0111_1101 0x7DªB0111_1110 0x7E«B0111_1111 0x7F­B1000_0000 0x80®B1000_0001 0x81¯B1000_0010 0x82°B1000_0011 0x83±B1000_0100 0x84²B1000_0101 0x85³B1000_0110 0x86´B1000_0111 0x87µB1000_1000 0x88¶B1000_1001 0x89·B1000_1010 0x8A¸B1000_1011 0x8B¹B1000_1100 0x8CºB1000_1101 0x8D»B1000_1110 0x8E¼B1000_1111 0x8F¾B1001_0000 0x90¿B1001_0001 0x91ÀB1001_0010 0x92ÁB1001_0011 0x93ÂB1001_0100 0x94ÃB1001_0101 0x95ÄB1001_0110 0x96ÅB1001_0111 0x97ÆB1001_1000 0x98ÇB1001_1001 0x99ÈB1001_1010 0x9AÉB1001_1011 0x9BÊB1001_1100 0x9CËB1001_1101 0x9DÌB1001_1110 0x9EÍB1001_1111 0x9FÏB1010_0000 0xA0ÐB1010_0001 0xA1ÑB1010_0010 0xA2ÒB1010_0011 0xA3ÓB1010_0100 0xA4ÔB1010_0101 0xA5ÕB1010_0110 0xA6ÖB1010_0111 0xA7×B1010_1000 0xA8ØB1010_1001 0xA9ÙB1010_1010 0xAAÚB1010_1011 0xABÛB1010_1100 0xACÜB1010_1101 0xADÝB1010_1110 0xAEÞB1010_1111 0xAFàB1011_0000 0xB0áB1011_0001 0xB1âB1011_0010 0xB2ãB1011_0011 0xB3äB1011_0100 0xB4åB1011_0101 0xB5æB1011_0110 0xB6çB1011_0111 0xB7èB1011_1000 0xB8éB1011_1001 0xB9êB1011_1010 0xBAëB1011_1011 0xBBìB1011_1100 0xBCíB1011_1101 0xBDîB1011_1110 0xBEïB1011_1111 0xBFñB1100_0000 0xC0òB1100_0001 0xC1óB1100_0010 0xC2ôB1100_0011 0xC3õB1100_0100 0xC4öB1100_0101 0xC5÷B1100_0110 0xC6øB1100_0111 0xC7ùB1100_1000 0xC8úB1100_1001 0xC9ûB1100_1010 0xCAüB1100_1011 0xCBýB1100_1100 0xCCþB1100_1101 0xCDÿB1100_1110 0xCE€B1100_1111 0xCF‚B1101_0000 0xD0ƒB1101_0001 0xD1„B1101_0010 0xD2…B1101_0011 0xD3†B1101_0100 0xD4‡B1101_0101 0xD5ˆB1101_0110 0xD6‰B1101_0111 0xD7ŠB1101_1000 0xD8‹B1101_1001 0xD9ŒB1101_1010 0xDAB1101_1011 0xDBŽB1101_1100 0xDCB1101_1101 0xDDB1101_1110 0xDE‘B1101_1111 0xDF“B1110_0000 0xE0”B1110_0001 0xE1•B1110_0010 0xE2–B1110_0011 0xE3—B1110_0100 0xE4˜B1110_0101 0xE5™B1110_0110 0xE6šB1110_0111 0xE7›B1110_1000 0xE8œB1110_1001 0xE9B1110_1010 0xEAžB1110_1011 0xEBŸB1110_1100 0xEC B1110_1101 0xED¡B1110_1110 0xEE¢B1110_1111 0xEF¤B1111_0000 0xF0¥B1111_0001 0xF1¦B1111_0010 0xF2§B1111_0011 0xF3¨B1111_0100 0xF4©B1111_0101 0xF5ªB1111_0110 0xF6«B1111_0111 0xF7¬B1111_1000 0xF8­B1111_1001 0xF9®B1111_1010 0xFA¯B1111_1011 0xFB°B1111_1100 0xFC±B1111_1101 0xFD²B1111_1110 0xFE³B1111_1111 0xFF4* ..\Core\bintohex.h´


..\Core\bintohex.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM×ØÙ__DEFINEALL_H__ RCHFCLKCFG 8clkmode 1SYSCLKdef CMU_RCHFCR_FSEL_8MHZ5uint08 uint8_t6uint8 uint8_t8uint16 uint16_t9uint32 uint32_t:int08 int8_t;int16 int16_t<int32 int32_tCIN_NORMAL 0DIN_PULLUP 1IOUT_PUSHPULL 0JOUT_OPENDRAIN 1QALTFUN_NORMAL 0RALTFUN_OPENDRAIN 1SALTFUN_PULLUP 2TALTFUN_OPENDRAIN_PULLUP 3XYZ[\]^_    ý ..\Core\..\Core\Include\D:\Keil5\ARM\ARMCC\Bin\..\include\..\Hardware\CLOCK\..\Hardware\DELAY\define_all.hFM33A0XXEV.hfm33a0xxev_include_all.hstdio.hstdint.hstring.hbintohex.huser_init.hdelay.hœ


..\Core\define_all.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMunsigned charSÜB08¶Bit!PB08_BitÇ-ˆSUCCESS_0ERROR_1PErrorStatus_STM32ë3*ž!bit0¶#!bit1¶#!bit2¶#!bit3¶#!bit4¶#!bit5¶#!bit6¶#!bit7¶#ÛÜÝ__USER_INIT_H__ XN ..\Hardware\CLOCK\..\Core\user_init.hdefine_all.hÀ


..\Hardware\CLOCK\user_init.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMßàá_DELAY_H_ SYSTICK_CLOCK_SOURCE_SCLK 0xFFFFFF3FSYSTICK_CLOCK_SOURCE_LSCLK 0xFFFFFF7FSYSTICK_CLOCK_SOURCE_RFU 0xFFFFFFBF    SYSTICK_CLOCK_SOURCE_SYSCLK 0xFFFFFFFFSYSTICK_CLOCK_SOURCE_U_SCLK 0x00000000SYSTICK_CLOCK_SOURCE_U_LSCLK 0x00000040 SYSTICK_CLOCK_SOURCE_U_RFU 0x00000080SYSTICK_CLOCK_SOURCE_U_SYSCLK 0x000000C0SYSCLOCK_U 12000000\Q ..\Hardware\DELAY\..\Drivers\delay.hfm33a0xxev_cmu.hà


..\Hardware\DELAY\delay.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMintNÉ»"ÂPConditionHookÉãäå__EX_RTC_H_ RX8025_ADDR_READ 0x65RX8025_ADDR_WRITE 0x64TH ..\Pre_Drivers\..\Core\ex_rtc.hdefine_all.h 


..\Pre_Drivers\ex_rtc.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM*Ÿhourœ#minœ#secœ#monthœ#dateœ#weekœ#year‘#Pcalendar_obj¹*‘yearN8#monthN8#dateN8#hourN8#minN8#secN8#PNETTIME3çèé__DEVICEGPIOINIT_H FM25V02_CS_LOW(__CS_TYPE__) do { if (__CS_TYPE__ == CS_1) { FM25V02_CS1_L; FM25V02_CS2_H; } else { FM25V02_CS2_L; FM25V02_CS1_H; } } while (0)FM25V02_CS_HIGH do { FM25V02_CS1_H; FM25V02_CS2_H; } while (0)!Fram_Flash_SPI_SCL_PIN_NUM GPIO_Pin_7"Fram_Flash_SPI_SCL_GROUP GPIOC$Fram_Flash_SPI_MISO_PIN_NUM GPIO_Pin_8%Fram_Flash_SPI_MISO_PIN_GROUP GPIOC'Fram_Flash_SPI_MOSI_PIN_NUM GPIO_Pin_9(Fram_Flash_SPI_MOSI_PIN_GROUP GPIOC*FRAM_CS1_NUM GPIO_Pin_6+FRAM_CS1_GROUP GPIOC,FM25V02_CS1_H GPIO_SetBits(FRAM_CS1_GROUP, FRAM_CS1_NUM)-FM25V02_CS1_L GPIO_ResetBits(FRAM_CS1_GROUP, FRAM_CS1_NUM)/FRAM_CS2_NUM GPIO_Pin_140FRAM_CS2_GROUP GPIOC1FM25V02_CS2_H GPIO_SetBits(FRAM_CS2_GROUP, FRAM_CS2_NUM)2FM25V02_CS2_L GPIO_ResetBits(FRAM_CS2_GROUP, FRAM_CS2_NUM)4E2P_VCC_EN_NUM GPIO_Pin_115E2P_VCC_EN_GROUP GPIOC6E2P_VCC_ON GPIO_ResetBits(E2P_VCC_EN_GROUP, E2P_VCC_EN_NUM)7E2P_VCC_OFF GPIO_SetBits(E2P_VCC_EN_GROUP, E2P_VCC_EN_NUM):LCD_POWER_CON_NUM GPIO_Pin_0;LCD_POWER_CON_GROUP GPIOF<LCD_Power_ON GPIO_SetBits(LCD_POWER_CON_GROUP, LCD_POWER_CON_NUM)=LCD_Power_OFF GPIO_ResetBits(LCD_POWER_CON_GROUP, LCD_POWER_CON_NUM)@LCD_SDA_PIN_NUM GPIO_Pin_3ALCD_SDA_PIN_GROUP GPIODBLCD_SDA_H GPIO_SetBits(LCD_SDA_PIN_GROUP, LCD_SDA_PIN_NUM)CLCD_SDA_L GPIO_ResetBits(LCD_SDA_PIN_GROUP, LCD_SDA_PIN_NUM)ELCD_SCL_PIN_NUM GPIO_Pin_2FLCD_SCL_PIN_GROUP GPIODGLCD_SCL_H GPIO_SetBits(LCD_SCL_PIN_GROUP, LCD_SCL_PIN_NUM)HLCD_SCL_L GPIO_ResetBits(LCD_SCL_PIN_GROUP, LCD_SCL_PIN_NUM)JLCD_SCL_READ GPIO_ReadInputDataBit(LCD_SCL_PIN_GROUP, LCD_SCL_PIN_NUM)KLCD_SDA_READ GPIO_ReadInputDataBit(LCD_SDA_PIN_GROUP, LCD_SDA_PIN_NUM)MLCD_RD_CLK_PIN_NUM GPIO_Pin_5NLCD_RD_CLK_PIN_GROUP GPIODOLCD_CS_PIN_NUM GPIO_Pin_4PLCD_CS_PIN_GROUP GPIODSPOWER_EX_EN_PIN_NUM GPIO_Pin_13TPOWER_EX_EN_PIN_GROUP GPIOBUpowerEX_ON GPIO_SetBits(POWER_EX_EN_PIN_GROUP, POWER_EX_EN_PIN_NUM)VpowerEX_OFF GPIO_ResetBits(POWER_EX_EN_PIN_GROUP, POWER_EX_EN_PIN_NUM)XPOWER_9V_EN_PIN_NUM GPIO_Pin_14YPOWER_9V_EN_PIN_GROUP GPIOBZpower9V_ON GPIO_SetBits(POWER_9V_EN_PIN_GROUP, POWER_9V_EN_PIN_NUM)[power9V_OFF GPIO_ResetBits(POWER_9V_EN_PIN_GROUP, POWER_9V_EN_PIN_NUM)]POWER_12V_EN_PIN_NUM GPIO_Pin_15^POWER_12V_EN_PIN_GROUP GPIOB_power12V_ON GPIO_SetBits(POWER_12V_EN_PIN_GROUP, POWER_12V_EN_PIN_NUM)`power12V_OFF GPIO_ResetBits(POWER_12V_EN_PIN_GROUP, POWER_12V_EN_PIN_NUM)bOUTPUT1_EN_PIN_NUM GPIO_Pin_11cOUTPUT1_EN_PIN_GROUP GPIOBdOUTPUT1_EN_ON GPIO_SetBits(OUTPUT1_EN_PIN_GROUP, OUTPUT1_EN_PIN_NUM)eOUTPUT1_EN_OFF GPIO_ResetBits(OUTPUT1_EN_PIN_GROUP, OUTPUT1_EN_PIN_NUM)gOUTPUT2_EN_PIN_NUM GPIO_Pin_12hOUTPUT2_EN_PIN_GROUP GPIOBiOUTPUT2_EN_ON GPIO_SetBits(OUTPUT2_EN_PIN_GROUP, OUTPUT2_EN_PIN_NUM)jOUTPUT2_EN_OFF GPIO_ResetBits(OUTPUT2_EN_PIN_GROUP, OUTPUT2_EN_PIN_NUM)mRS485_SYNC_PIN_NUM GPIO_Pin_2nRS485_SYNC_PIN_GROUP GPIOEoRS485_SYNC_READ GPIO_ReadInputDataBit(RS485_SYNC_PIN_GROUP, RS485_SYNC_PIN_NUM)qLOW_PWR_INT_PIN_NUM GPIO_Pin_2rLOW_PWR_INT_PIN_GROUP GPIOBsLOW_PWR_READ GPIO_ReadInputDataBit(LOW_PWR_INT_PIN_GROUP, LOW_PWR_INT_PIN_NUM)uUNDER_PWR_INT_PIN_NUM GPIO_Pin_3vUNDER_PWR_INT_PIN_GROUP GPIOBwUNDER_PWR_READ GPIO_ReadInputDataBit(UNDER_PWR_INT_PIN_GROUP, UNDER_PWR_INT_PIN_NUM)yALARM_LINE_PIN_NUM GPIO_Pin_13zALARM_LINE_PIN_GROUP GPIOA{ALARM_LINE_READ GPIO_ReadInputDataBit(ALARM_LINE_PIN_GROUP, ALARM_LINE_PIN_NUM)}LITH_BAT_LOW_PWR_PIN_NUM GPIO_Pin_0~LITH_BAT_LOW_PWR_PIN_GROUP GPIODLITH_BAT_LOW_PWR_PIN_READ GPIO_ReadInputDataBit(LITH_BAT_LOW_PWR_PIN_GROUP, LITH_BAT_LOW_PWR_PIN_NUM)ALKA_BAT_M_PIN_NUM GPIO_Pin_0‚ALKA_BAT_M_PIN_GROUP GPIOH„LITH_BAT_M_PIN_NUM GPIO_Pin_6…LITH_BAT_M_PIN_GROUP GPIOF‡ALKA_TEST_EN_PIN_NUM GPIO_Pin_4ˆALKA_TEST_EN_PIN_GROUP GPIOF‰ALKA_TEST_ON GPIO_SetBits(ALKA_TEST_EN_PIN_GROUP, ALKA_TEST_EN_PIN_NUM)ŠALKA_TEST_OFF GPIO_ResetBits(ALKA_TEST_EN_PIN_GROUP, ALKA_TEST_EN_PIN_NUM)ŒLITH_TEST_EN_PIN_NUM GPIO_Pin_3LITH_TEST_EN_PIN_GROUP GPIOFŽLITH_TEST_ON GPIO_SetBits(LITH_TEST_EN_PIN_GROUP, LITH_TEST_EN_PIN_NUM)LITH_TEST_OFF GPIO_ResetBits(LITH_TEST_EN_PIN_GROUP, LITH_TEST_EN_PIN_NUM)‘HWID0_PIN_NUM GPIO_Pin_5’HWID0_PIN_GROUP GPIOF“HWID0_READ GPIO_ReadInputDataBit(HWID0_PIN_GROUP, HWID0_PIN_NUM)”HWID0_H GPIO_SetBits(HWID0_PIN_GROUP, HWID0_PIN_NUM)•HWID0_L GPIO_ResetBits(HWID0_PIN_GROUP, HWID0_PIN_NUM)—EX_PWR_EN_PIN_NUM GPIO_Pin_3˜EX_PWR_EN_PIN_GROUP GPIOG™EX_PWR_EN_H GPIO_SetBits(EX_PWR_EN_PIN_GROUP, EX_PWR_EN_PIN_NUM)šEX_PWR_EN_L GPIO_ResetBits(EX_PWR_EN_PIN_GROUP, EX_PWR_EN_PIN_NUM)›EX_PWR_EN_READ GPIO_ReadInputDataBit(EX_PWR_EN_PIN_GROUP, EX_PWR_EN_PIN_NUM)LIMIT_TRIG_PIN_NUM GPIO_Pin_13žLIMIT_TRIG_PIN_GROUP GPIOCŸLIMIT_TRIG_READ GPIO_ReadInputDataBit(LIMIT_TRIG_PIN_GROUP, LIMIT_TRIG_PIN_NUM)¢KEY1_PIN_NUM GPIO_Pin_9£KEY1_PIN_GROUP GPIOE¥KEY2_PIN_NUM GPIO_Pin_15¦KEY2_PIN_GROUP GPIOF¨KEY3_PIN_NUM GPIO_Pin_14©KEY3_PIN_GROUP GPIOF«KEY1_PRESS GPIO_ReadInputDataBit(KEY1_PIN_GROUP, KEY1_PIN_NUM)¬KEY2_PRESS GPIO_ReadInputDataBit(KEY2_PIN_GROUP, KEY2_PIN_NUM)­KEY3_PRESS GPIO_ReadInputDataBit(KEY3_PIN_GROUP, KEY3_PIN_NUM)°RS485_RE_EN_PIN_NUM GPIO_Pin_14±RS485_RE_EN_PIN_GROUP GPIOA²RS485_RE_H GPIO_SetBits(RS485_RE_EN_PIN_GROUP, RS485_RE_EN_PIN_NUM)³RS485_RE_L GPIO_ResetBits(RS485_RE_EN_PIN_GROUP, RS485_RE_EN_PIN_NUM)µRS485_TXD_EN_PIN_NUM GPIO_Pin_1¶RS485_TXD_EN_PIN_GROUP GPIOB·RS485_RXD_EN_PIN_NUM GPIO_Pin_0¸RS485_RXD_EN_PIN_GROUP GPIOBºRS485_POWER_EN_PIN_NUM GPIO_Pin_15»RS485_POWER_EN_PIN_GROUP GPIOA¼RS485_POWER_ON GPIO_SetBits(RS485_POWER_EN_PIN_GROUP, RS485_POWER_EN_PIN_NUM)½RS485_POWER_OFF GPIO_ResetBits(RS485_POWER_EN_PIN_GROUP, RS485_POWER_EN_PIN_NUM)ÀGPRSRS232_TXD_EN_PIN_NUM GPIO_Pin_4ÁGPRSRS232_TXD_EN_PIN_GROUP GPIOEÂGPRSRS232_RXD_EN_PIN_NUM GPIO_Pin_3ÃGPRSRS232_RXD_EN_PIN_GROUP GPIOEÆUTRXD_RE_EN_PIN_NUM GPIO_Pin_10ÇUTXRD_RE_EN_PIN_GROUP GPIOAÈUTRXD_RE_H GPIO_SetBits(UTXRD_RE_EN_PIN_GROUP, UTRXD_RE_EN_PIN_NUM)ÉUTRXD_RE_L GPIO_ResetBits(UTXRD_RE_EN_PIN_GROUP, UTRXD_RE_EN_PIN_NUM)ËUTXD_EN_PIN_NUM GPIO_Pin_9ÌUTXD_EN_PIN_GROUP GPIOAÍURXD_EN_PIN_NUM GPIO_Pin_8ÎURXD_EN_PIN_GROUP GPIOAÑMotor_A_PIN_NUM GPIO_Pin_8ÒMotor_A_PIN_GROUP GPIOBÓMotor_A_EN_H GPIO_SetBits(Motor_A_PIN_GROUP, Motor_A_PIN_NUM)ÔMotor_A_EN_L GPIO_ResetBits(Motor_A_PIN_GROUP, Motor_A_PIN_NUM)ÖMotor_B_PIN_NUM GPIO_Pin_9×Motor_B_PIN_GROUP GPIOBØMotor_B_EN_H GPIO_SetBits(Motor_B_PIN_GROUP, Motor_B_PIN_NUM)ÙMotor_B_EN_L GPIO_ResetBits(Motor_B_PIN_GROUP, Motor_B_PIN_NUM)ÛMotor_OP_PIN_NUM GPIO_Pin_6ÜMotor_OP_PIN_GROUP GPIOBÝMotor_OP_PIN_READ GPIO_ReadInputDataBit(Motor_OP_PIN_GROUP, Motor_OP_PIN_NUM)ßMotor_CL_PIN_NUM GPIO_Pin_7àMotor_CL_PIN_GROUP GPIOBáMotor_CL_PIN_READ GPIO_ReadInputDataBit(Motor_CL_PIN_GROUP, Motor_CL_PIN_NUM)äRTC_SDA_PIN_NUM GPIO_Pin_3åRTC_SDA_PIN_GROUP GPIODæRTC_CLK_PIN_NUM GPIO_Pin_2çRTC_CLK_PIN_GROUP GPIODéRTC_INT_PIN_NUM GPIO_Pin_6êRTC_INT_PIN_GROUP GPIODíLOWPLUSE_PIN_NUM GPIO_Pin_3îLOWPLUSE_PIN_GROUP GPIOHïPULSE_LINE_READ GPIOH_ReadInputDataBit(LOWPLUSE_PIN_NUM)òGPIO_GPRS_POWER_PIN_NUM GPIO_Pin_7óGPIO_GPRS_POWER_PIN_GROUP GPIOEôGPRS_POWER_ON GPIO_SetBits(GPIO_GPRS_POWER_PIN_GROUP, GPIO_GPRS_POWER_PIN_NUM)õGPRS_POWER_OFF GPIO_ResetBits(GPIO_GPRS_POWER_PIN_GROUP, GPIO_GPRS_POWER_PIN_NUM)÷GPRS_PWR_EN_PIN_NUM GPIO_Pin_6øGPRS_PWR_EN_PIN_GROUP GPIOEùGPRS_POWER_EN_H GPIO_SetBits(GPRS_PWR_EN_PIN_GROUP, GPRS_PWR_EN_PIN_NUM)úGPRS_POWER_EN_L GPIO_ResetBits(GPRS_PWR_EN_PIN_GROUP, GPRS_PWR_EN_PIN_NUM)ýUNCAP_INT_PIN_NUM GPIO_Pin_1þUNCAP_INT_PIN_GROUP GPIODÿUNCAP_INT_READ GPIO_ReadInputDataBit(UNCAP_INT_PIN_GROUP, UNCAP_INT_PIN_NUM)€UNCAP_INT_L GPIO_ResetBits(UNCAP_INT_PIN_GROUP, UNCAP_INT_PIN_NUM)ƒFORCE_OPEN_INT_PIN_NUM GPIO_Pin_12„FORCE_OPEN_INT_PIN_GROUP GPIOC…FORCE_OPEN_INT_READ GPIO_ReadInputDataBit(FORCE_OPEN_INT_PIN_GROUP, FORCE_OPEN_INT_PIN_NUM)ˆBORROW_PWR_EN_PIN_NUM GPIO_Pin_2‰BORROW_PWR_EN_PIN_NUM_GROUP GPIOGŠBORROW_PWR_EN_PIN_H GPIO_SetBits(BORROW_PWR_EN_PIN_NUM_GROUP, BORROW_PWR_EN_PIN_NUM)‹BORROW_PWR_EN_NUM_L GPIO_ResetBits(BORROW_PWR_EN_PIN_NUM_GROUP, BORROW_PWR_EN_PIN_NUM)\P ..\Pre_Drivers\..\Core\devicegpioinit.hdefine_all.hè


..\Pre_Drivers\devicegpioinit.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMÖCS_1CS_2PCS_TYPED_TÁ


ëìí__ADC_H const_adc_Slope (*((uint16_t *)(0x1FFFFA88)))const_adc_Offset (*((int16_t *)(0x1FFFFA8A)))const_T_30 *(uint16_t *)0x1FFFFA92const_T_30_14BIT *(uint16_t *)0x1FFFFB54AD_ALKA_BAT_REF_VOL 3.3AD_ALKA_BAT_CH 12AD_ALKA_BAT_CNT 26ALKA_VOL_COE 3.5AD_LITH_BAT_REF_VOL 3.3AD_LITH_BAT_CH 5AD_LITH_BAT_CNT 26LITH_VOL_COE 4.3PF ..\Pre_Drivers\..\Core\1ADC.hdefine_all.h 


..\Pre_Drivers\1ADC.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM)‘ad_data_getlÒ‘1ad_get_address_pÇ#ad_buffer_cnt†#dad_chœ#hPad_data_s·$ïðñò__PARA_H FIRMWARE_VER_1 0x0000    FIRMWARE_VER_2 0x0102


FIRMWARE_VER_3 0x0407__UPPER_DATA_ALTER(__LAST__,__NOW__) ((__LAST__ != __NOW__) ? SET : RESET)READSUCCESSFULLYTIMES 3READFAILEDTIMES 200PULSE_MODE 0x01RS485_MODE 0x02RS485_AND_PULSE_MODE 0x03ACTIVE 1NOACTIVE 0HOST_COMPUTER_DATA_INDEX 3FLOW_LOW_PWR_ALARM_CODE 0x0101 FLOW_UNDER_VOLTAGE_ALARM_CODE 0x0102!FLOW_PWR_DOWN_ALARM_CODE 0x0103"ALKA_PWR_DOWN_ALARM_CODE 0x0104#LITH_PWR_DOWN_ALARM_CODE 0x0105$EXTERNAL_PWR_ACCESS_ALARM_CODE 0x0106%EXTERNAL_PWR_DOWN_ALARM_CODE 0x0107&ALKA_PWR_LOW_ALARM_CODE 0x0108'LITH_PWR_LOW_ALARM_CODE 0x0109)PULSE_LINE_DISCONNECTED_ALARM_CODE 0x0201*FORCED_TO_CLOSE_VALVE_ALARM_CODE 0x0202+VALVE_OPEN_ALARM_CODE 0x0203,VALVE_ABNORMAL_ALARM_CODE 0x0204-VALVE_FORCE_OPEN_ALARM_CODE 0x0205.PULSE_LINE_MISMATCH_ALARM_CODE 0xfff1/GAS_LEAK_ALARM_CODE 0x02081RS485_READ_FLOW_FAILED_ALARM_CODE 0x03012RS485_READ_ABNORMAL_SMALL_READING_CODE 0x03024TEMPERATURE_ABNORMAL_ALARM_CODE 0x04015PRESSURE_ABNORMAL_ALARM_CODE 0x04027AMOUNT_SMALL_ALARM_CODE 0x05018AMOUNT_ARREARS_ALARM_CODE 0x05029AMOUNT_OVERDRAFT_ALARM_CODE 0x0503;E2RW_READ_ABNORMAL_ALARM_CODE 0x0701<E2RW_WRITE_ABNORMAL_ALARM_CODE 0x0702>CAP_OPEN_ALARM_CODE 0x0802DDeviceAddress_Addr 0x0004ETyf_Addr 0x0012FTy_Addr 0x0014GTyp_Addr 0x0016HTp_Addr 0x0018JTime1_Flag_Addr 0x001CKSendTiming_Hour_Addr 0x001DLSendTiming_Min_Addr 0x001EMTime2_Flag_Addr 0x001FNSendTiming_Hour2_Addr 0x0020OSendTiming_Min2_Addr 0x0021PGPRS_RestartTime_Addr 0x0022QIP_Addr 0x0028SNumDataStored_Addr 0x0037TDataStoredFlag_Addr 0x003CVKVER_ADDR 62WKEY_ADDR 64YREALTIME_CUMULATIVE_GAS_USAGE_ADDR 80ZREALTIME_CUMULATIVE_FEE_USAGE_ADDR 88[REALTIME_BALANCE_ADDR 96^DATA_OBTAIN_TYPE_ADDR 104_PULSE_COE_ADDR 108`BILLING_TYPE_ADDR 112aSINGLE_BILLING_FEE_ADDR 113bSTEP_BILLING_FIRST_ADDR 117cSTEP_BILLING_FEE_FIRST_ADDR 121dSTEP_BILLING_SECOND_ADDR 125eSTEP_BILLING_FEE_SECOND_ADDR 129fSTEP_BILLING_THIRD_ADDR 133gSTEP_BILLING_FEE_THIRD_ADDR 137hBALANCE_INSUF_ALARM_AMOUNT_ADDR 141iCREDITS_ADDR 145kMETER_TYPE_CODE_ADDR 149mPULSE_WITDH_ADDR 151oACCOUNT_STATUS_ADDR 155qBAUD_RATE_CODE_ADDR 156rRS485_PARITY_ADDR 157sEXP_VOLTAGE_CODE_ADDR 158tLOW_POWER_ALARM_LINE_ADDR 159uSLAVE_ADDRESS_ADDR 160wSHOW_BALANCE_FLAG_ADDR 161xSHOW_PRICE_FLAG_ADDR 162zLCD_LOGO_ADDR 169{LCD_FLAG_ADDR 170|LOGO_DISPLAY_FLAG_ADDR 171}OPEN_VALVE_AUTHORIZE_FLAG_ADDR 172~OPEN_VALVE_AUTHORIZE_TIME_CNT_ADDRA 173VALVE_STATE_ADDR 177€VALVE_TYPE_ADDR 178‚DeviceserialNum1_ADDR 200ƒDeviceserialNum2_ADDR 202„DeviceserialNum3_ADDR 204…DeviceserialNum4_ADDR 206‡HardwareVerSn1_ADDR 208ˆHardwareVerSn2_ADDR 210‰HardwareVerSn3_ADDR 212‹FirmwareVerSn1_ADDR 214ŒFirmwareVerSn2_ADDR 216FirmwareVerSn3_ADDR 218FirmwareCRC_ADDR 220‘FirmwareDateyear_ADDR 222’FirmwareDatemonth_ADDR 224“FirmwareDateday_ADDR 226”EquipmentCaliberAndModel_ADDR 228˜RS485_SETTLEMENT_FLAG_ADDR 299™DATA_READABLE_FLAG_ADDR 300šSCACC_BIL_ADDR 301›BALANCE_BIL_ADDR 305œGAS_USAGE_BIL_ADDR 313FEE_USAGE_BIL_ADDR 321ŸTIME_BIL_ADDR 329¢REALTIME_CUMULATIVE_GAS_USAGE_B_ADDR 350£REALTIME_CUMULATIVE_FEE_USAGE_B_ADDR 358¤REALTIME_BALANCE_B_ADDR 366¦E2RW_READ_ABNORMAL_FLAG_ADDR 375§E2RW_WRITE_ABNORMAL_FLAG_ADDR 376©VALVE_OPEN_TIMES_ADDR 925ªVALVE_CLOSE_TIMES_ADDR 927¬REALTIME_CUMULATIVE_GAS_USAGE_C_ADDR 970­REALTIME_CUMULATIVE_FEE_USAGE_C_ADDR 978®REALTIME_BALANCE_C_ADDR 986°NumStoredLength 750±WCACC_addr 0x03E8²SCACC_addr 0x1068³PRE_addr 0x1CE8´TEM_addr 0x2968µWCINS_addr 0x35E8¶SCINS_addr 0x4268·SCCor_addr 0x4EE8¹YEAR_addr 0x5B68ºMONTH_addr 0x5E88»DAY_addr 0x61A8¼HOUR_addr 0x64C8½MIN_addr 0x67E8¾SEC_addr 0x6B08ÀBAT_LITH_addr 0x6E28ÂBAT_ALKA_addr 0x6E2CÃBAT_EX_addr 0x6E30ÅCUMULATIVE_GAS_USAGE_ADDR 31400ÆCUMULATIVE_FEE_USAGE_ADDR 37400ÇBALANCE_ADDR 43400ÊCURRENT_BIL_RECORD_NUM_ADDR 49990ËBIL_RECORD_FULL_FLAG_ADDR 49992ÌFIRST_BIL_RECORD_ADDR 50000ÎBIL_RECORD_LENGTH 100ÏBIL_RECORD_NUM 100ÒCURRENT_ALARM_RECORD_NUM_ADDR 60000ÓALARM_RECORD_FULL_FLAG_ADDR 60002ÔFIRST_ALARM_RECORD_ADDR 60004ÖALARM_RECORD_LENGTH 9×ALARM_RECORD_NUM 1000ÚCUMULANTS_MODIFY_RECORD_NUM_ADDR 70000ÛCUMULANTS_MODIFY_RECORD_FULL_FLAG_ADDR 70002ÜFIRST_CUMULANTS_MODIFY_RECORD_ADDR 70004ÞCUMULANTS_MODIFY_RECORD_LENGTH 50ßCUMULANTS_MODIFY_RECORD_NUM 50áMODBUS_SLAVE_ADDR 75000äBALANCE_SAVE_TYPE_ADDR 75002 VALVE_ABNORMAL_THRESHOLD 3\P ..\Pre_Drivers\..\Core\para.hdefine_all.h1ADC.h


..\Pre_Drivers\para.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMfloatdoubleintcharPLLJ_DATAù†*ÿ Tyf8#Tf8#Typ8#Tp8#sampling_TimeV#time1_flag8#sendTiming_hour8#sendTiming_min8#time2_flag8#    sendTiming_hour28#


sendTiming_min28#GPRS_RESTARTTIME8#real_sendTiming_hour8# real_sendTiming_min8#real_sendTiming_day8#RTC_sendTiming_hour8#RTC_sendTiming_min8#RTC_sendTiming_day8#AccountStatus8#TestStatus8#Hour_Updata_flag8#Key_Power_Det8#Logo_Display_Flag8#Sample_Min_Time‘#Sample_Interval‘#Send_Interval‘#show_balance_flagœ#show_price_flagœ#PDEVICE_PARMê¬*›Ialarm_l8#u16AlarmStoreNumV#u8AlarmStoreFullFlag8#alarm_Sample8#alarm_PRE8#alarm_TEM8#alarm_FlowPowerLOW8#alarm_FlowUnderPower8#alarm_FlowPowerDOWN8#    alarm_AlkaPowerDOWN8#


alarm_AlkaPowerLOW8#alarm_LithPowerDOWN8#alarm_LithPowerLOW8# alarm_EXPowerIN8#alarm_EXPowerRemove8#alarm_Pulse_Broken8#alarm_Pulse_Dismatch8#alarm_Valve_close8#alarm_Valve_open8#alarm_Valve_Abnormal8#alarm_Gas_Leak8#alarm_Gas_Leak_time8#alarm_Balance_Small8#alarm_Balance_08#alarm_Credits_08#alarm_Credits_0TimesV#alarm_E2RW_read_abnormal8#alarm_E2RW_write_abnormal8#alarm_Cap_OPEN8#alarm_Valve_Force_Open8#fTempratureLowLimit·# fTempratureHighLimit·#$fPressureLowLimit·#(fPressureHighLimit·#,u8ReadfailedTimes8#0u8ReadSuccessfullyTimes8#1alarm_Send_failed_time8#2Data_Send_failed_time8#3alarm_Valve_Abnormal_time8#4alarm_RS485_Abnormal_Small_Reading8#5u8PulseBrokenTimes8#6alarm_FlowPowerLOW_time8#7alarm_AlkaPowerLow_LCDFLAG8#8alarm_LithPowerLow_LCDFLAG8#9alarm_AlkaPowerDOWN_LCDFLAG8#:alarm_LithPowerDOWN_LCDFLAG8#;alarm_Pulse_Broken_LCDFLAG8#<alarm_Pulse_Dismatch_LCDFLAG8#=alarm_Gas_Leak_LCDFLAG8#>alarm_Sample_LCDFLAG8#?alarm_PRE_LCDFLAG8#@alarm_TEM_LCDFLAG8#Aalarm_Balance_Small_LCDFLAG8#Balarm_RS485Cardinalityfree_LCDFLAG8#Calarm_E2RW_read_abnormal_FLAG8#Dalarm_E2RW_write_abnormal_FLAG8#Ealarm_RS485_Abnormal_Small_Reading_FLAG8#Falarm_Cap_OPEN_LCDFALG8#Galarm_FlowPowerLOW_FLAG8#HPSYSTEM_ALARM“ø*«u16BilRecordNUMV#u8BilStoreFullFlag8#u16CumulantsRecordNUMV#u8CumulantsStoreFullFlag8#PSYSTEM_RECORD°


…)Ôparameter_bil5cDataObtainTypeœ#u8PulseWidthœ#fPulseCoefficient·#cBillingTypeœ#fSingleBillingFee·#fStepBilling_First·#fStepBillingFee_First·#fStepBilling_Second·#fStepBillingFee_Second·#fStepBilling_Third·#fStepBillingFee_Third·#s32RechargeAmountÊ##dRechargeAmountÀ#'iBalanceInsufAlarmAmountV#/fCredits·#1PPARAMETER_BILA)ïvalve_abnormal_paravalveCloseFirstCumÀ#valveCloseFirstFlagœ#valveCloseNextCumÀ#    valveCloseNextFlagœ#PVALVE_ABNORMAL_PARAê©*ßšVhardwareVerSn #ºVfirmwareVer¯ #firmwareCRCV#firmwareVerDate_yearV#firmwareVerDate_monthV#firmwareVerDate_dayV#EquipmentCaliberAndModel8#PdeviceSerialNum_t‹ º*«slave_time_flagœ#slave_addrœ#PMODBUS_DEV_PARAyÀt_qregDevSerialNumÃqTime_For_valve_openVqTime_For_wakeupVqLCD_sleepTimeVqLCD_flag8qLOGO_Flag8qk_indexfqflag8qbegin8qLPM3_FLAG8qnumÊqsleepTimeÊqtotal_dataGroupNum8qyushu8qFirstTimeRunFlag8íÑ•qDebugãqdevice_Parmqparameter_bilÔqsystem_alarm›


qsystem_record+qRS485_statusœqBT_statusœtqad_data_gmtÙqLLJ_data_gƒqPower_ON_cnt†qPower_ON_flagœt«qmodbus_dev_paraÃqvalve_abnormal_para_go )†&LLJ_dataPyearV#month8#date8#hour8#min8#sec8#Lith_Battery_V·#Alka_Battery_V·#EX_Battery_V·#Meter_Battery_V·#MeterBatVoltagePercentœ#SC_Accumulation·#WC_Accumulation·#SC_Accumulation_longf# WC_Accumulation_longf#$SC_Accumulation_doubleÀ#(WC_Accumulation_doubleÀ#0SC_Weight_Factor#8WC_Weight_Factor#:Temperature·#<Pressure·#@SC_instant·#DWC_instant·#HKB_battery_Q·#LÐÇregDevSerialNumÝTime_For_valve_openùTime_For_wakeupLCD_sleepTime'LCD_flag8LOGO_FlagJk_indexZflaggbeginuLPM3_FLAG‡num‘sleepTime¡total_dataGroupNum¼yushuÊFirstTimeRunFlagíDebugùdevice_Parmparameter_bilsystem_alarm2system_recordFRS485_status[BT_statussad_data_g‡LLJ_data_g˜Power_ON_cnt­Power_ON_flagÇmodbus_dev_paraÝvalve_abnormal_para_gôõö÷_KEY_H_ KEYA_S1_PORT GPIODKEYA_S1_PIN GPIO_Pin_6    KEYB_S2_PORT GPIOD


KEYB_S2_PIN GPIO_Pin_8KEYC_S3_PORT GPIOA KEYC_S3_PIN GPIO_Pin_0KEY_A_READ GPIO_ReadInputDataBit(KEYA_S1_PORT,KEYA_S1_PIN)KEY_B_READ GPIO_ReadInputDataBit(KEYB_S2_PORT,KEYB_S2_PIN)KEY_C_READ GPIO_ReadInputDataBit(KEYC_S3_PORT,KEYC_S3_PIN)PF ..\Function\KEY\..\Core\key.hdefine_all.hÐ


..\Function\KEY\key.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMqkey_awaken_flag_gÓ$Ô·key_awaken_flag_gùúûü_ADMINISTRATOR_H_ __SYS_STATUS_BYTES_GET(__HANDLE__) ((&sys_admin_g)->sys_admin.state_bytes.__HANDLE__)    __SYS_STATUS_BYTES_STATUS(__HANDLE__,__FLAG__,__ID__) do { if (__SYS_STATUS_BYTES_GET(__HANDLE__) != __FLAG__) { ((&sys_admin_g)->sys_admin.state_bytes.__HANDLE__ = __FLAG__); sys_clear_state_bytes_id_g = __ID__; Alarm_List_Node_Deleted(&pList_head,__ID__); } } while (0)__SYS_ALARM_BYTES_SET(__HANDLE__,__FLAG__) ((&sys_admin_g)->sys_admin.alarm_bytes.__HANDLE__ = __FLAG__)__SYS_STATUS_ALARM_BYTES_SET(__HANDLE__) do { if (__SYS_STATUS_BYTES_GET(__HANDLE__) != SET) (&sys_admin_g)->sys_admin.state_bytes.__HANDLE__ = (&sys_admin_g)->sys_admin.alarm_bytes.__HANDLE__ = SET; } while (0)__SYS_FUNC_CFG_BYTES_GET(__HANDLE__) ((&sys_func_cfg_bytes_g)->sys_func_cfg_bytes_s.__HANDLE__) __SYS_ALARM_CTL_BYTES_GET(__HANDLE__) ((&sys_alarm_ctl_bytes_g)->sys_alarm_ctl_send.__HANDLE__)"__SYS_ALARM_SEND_BYTES_GET(__HANDLE__) ((&sys_alarm_send_bytes_g)->sys_alarm_ctl_send.__HANDLE__)$__SYS_ALARM_CTL_SEND_BYTES_SET(__HANDLE__,__FLAG__) do { if(__SYS_ALARM_CTL_BYTES_GET(__HANDLE__) != __FLAG__) (&sys_alarm_ctl_bytes_g)->sys_alarm_ctl_send.__HANDLE__ = (&sys_alarm_send_bytes_g)->sys_alarm_ctl_send.__HANDLE__ = __FLAG__; }while(0)-SYS_STATUS_BYTES_TYPE_LENGTH sizeof(SYS_STATUS_T).SYS_ALARM_BYTES_TYPE_LENGTH sizeof(SYS_ALARM_T)/SYS_ALARM_CTL_BYTES_TYPE_LENGTH SYS_ALARM_BYTES_TYPE_LENGTH0SYS_ALARM_SEND_BYTES_TYPE_LENGTH SYS_ALARM_BYTES_TYPE_LENGTH1SYS_FUNC_CTL_BYTES_TYPE_LENGTH sizeof(SYS_FUNC_CFG_UNION_T)3SYS_ALARM_VALVE_ID_FUNC_TABLE_NUM_1 (sizeof(sys_av_id_tab_func_1) / sizeof(SYS_ALARM_VALVE_ID_FUNC_TABLE_DRV_T))4SYS_ALARM_VALVE_ID_FUNC_TABLE_NUM_2 (sizeof(sys_av_id_tab_func_2) / sizeof(SYS_ALARM_VALVE_ID_FUNC_TABLE_DRV_T))5SYS_ALARM_VALVE_ID_FUNC_TABLE_NUM_3 (sizeof(sys_av_id_tab_func_3) / sizeof(SYS_ALARM_VALVE_ID_FUNC_TABLE_DRV_T))6SYS_ALARM_VALVE_ID_FUNC_TABLE_NUM_4 (sizeof(sys_av_id_tab_func_4) / sizeof(SYS_ALARM_VALVE_ID_FUNC_TABLE_DRV_T))7SYS_ALARM_VALVE_ID_FUNC_TABLE_NUM_5 (sizeof(sys_av_id_tab_func_5) / sizeof(SYS_ALARM_VALVE_ID_FUNC_TABLE_DRV_T))8SYS_ALARM_VALVE_ID_FUNC_TABLE_NUM_6 (sizeof(sys_av_id_tab_func_6) / sizeof(SYS_ALARM_VALVE_ID_FUNC_TABLE_DRV_T))9SYS_ALARM_VALVE_ID_FUNC_TABLE_NUM_7 (sizeof(sys_av_id_tab_func_7) / sizeof(SYS_ALARM_VALVE_ID_FUNC_TABLE_DRV_T));ALARM_BYTES_DAILY_NUM 2¬dY ..\Soft\..\Core\administrator.hdefine_all.hlinked_list.hø


..\Soft\administrator.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM•VALVE_NONEVALVE_OPVALVE_CLVALVE_OPENINGVALVE_CLOSINGVALVE_ERRORPVALVE_STATE_T¹EéLDM_KEY_AWAKENLDM_ALWAYS_AWAKENLDM_FLOW_AWAKENPLCD_DISPLAY_MODE_T*L¯BM_NONEBM_DEVICEBM_PLATFORMPBILLING_MODE_TƒSÌPARA_AMEND_NONEGAS_CUMULATE_PARA_AMENDBALANCE_PARA_AMENDTEMP_CFG_PARA_AMENDPRESS_CFG_PARA_AMENDBILLING_PARA_AMENDGAS_CAL_PARA_AMENDGAS_CFG_PARA_AMENDPLUSE_CAL_PARA_AMENDUT_ERR_PARA_AMEND    UT_CAL_PARA_AMEND


SYS_FUNC_CFG_BYTES_AMENDALARM_CTL_SEND_BYTES_AMENDVALVE_CTL_BYTES_AMEND BILLING_ALARM_CFG_AMENDSEC_ORDER_CORR_PARA_AMENDPPARA_AMEND_TÅg–AV_NORMALA_RESTARTAV_EXTERN_VCC_DOWNAV_UNCAP_1AV_UNCAP_2AV_GPRS_FAILAV_LCD_UPAV_LITH_LOWAV_LITH_UNDERAV_LITH_REMOVEAV_ALKA_LOWAV_ALKA_UNDERAV_ALKA_REMOVEAV_VALVE_VCC_LOWAV_VALVE_VCC_DOWNRTC_VCCAV_TEMP_ERR AV_TEMP_UP!AV_TEMP_UP_UP"AV_TEMP_DOWN#AV_TEMP_DOWN_DOWN$AV_PRESS_ERR%AV_PRESS_UP&AV_PRESS_UP_UP'AV_PRESS_DOWN(AV_PRESS_DOWN_DOWN)AV_CPU_TEMP_UP0AV_CPU_TEMP_DOWN1AV_CPU_TEMP_DRASTIC_CHANGE2AV_LCD_TEMP_LOW3AV_UT_LOSE@AV_FLOW_VEL_ERRAAV_TOF_DIFF_ERRBAV_SOUND_VEL_ERRCAV_SNR_ERRDAV_SIG_UPEAV_SIG_TH_ERRFAV_GAIN_ERRGAV_INPUT_WATER_ERRHAV_MEDIA_ERRIAV_DISMANTLEPAV_MEASURE_ERRQAV_FLOW_UP_1`AV_FLOW_UP_2aAV_FLOW_UP_3bAV_FLOW_DIRECTIONcAV_CONSTANT_FLOWdAV_CONSTANT_TINY_FLOWeAV_LEAKAGEfAV_VALVE_ERRpAV_CL_HAVE_FLOWqAV_BALANCE_1AV_BALANCE_2‘AV_BALANCE_3’AV_BALANCE_4“AV_BALANCE_5”AV_SET_CUMULATE•AV_NO_USE_GAS–AV_NO_GPRS—V_KEY_OP–    V_KEY_CL—    V_GPRS_CMD_OP˜    V_GPRS_CMD_CL™    PSYS_ALARM_VALVE_T`±*Ë!lcd_modeV#!V#!account_stateV#!flow_directionV#!work_stateV#!V#!power_stateV#!V#!uncap_state_1V#!V#!valve_stateV#!valve_lockV#!set_cumulate_up_toV#!no_use_gas_date_up_toV#!no_gprs_date_up_toV#!virtual_billingV#!billing_typeV#!V#!balance_small_1V#!balance_small_2V#!balance_small_3V#!balance_small_4V#!balance_small_5V#!lith_lowV#!lith_underV#!lith_removeV#!alka_lowV#!alka_underV#!alka_removeV#!V#!gprs_statusV#!V#!temp_errV#!temp_upV#!temp_up_upV#!temp_downV#!temp_down_downV#!cpu_temp_upV#!cpu_temp_downV#!cpu_temp_drastic_changeV#!press_errV#!press_upV#!press_up_upV#!press_downV#!press_down_downV#!V#!flow_ver_errV#!tof_diff_errV#!sound_vel_errV#!snr_errV#!sig_upV#!sig_th_errV#!gain_errV#!ut_loseV#!media_statusV#    !input_waterV#    !measure_errV#    !V#    !gas_leakageV#


!lcd_upV#


!lcd_temp_lowV#


!flow_up_1V#


!flow_up_2V#


!flow_up_3V#


!constant_tiny_flowV#


!constant_flowV#


!cl_have_flowV#!V#PSYS_STATUS_T°€*‚*!V#!account_stateV#!flow_directionV#!V#!restartV#!power_stateV#!V#!uncap_state_1V#!V#!valve_errorV#!valve_changeV#!V#!set_cumulate_up_toV#!no_use_gas_date_up_toV#!no_gprs_date_up_toV#!V#!balance_small_1V#!balance_small_2V#!balance_small_3V#!balance_small_4V#!balance_small_5V#!lith_lowV#!lith_underV#!lith_removeV#!alka_lowV#!alka_underV#!alka_removeV#!V#!gprs_statusV#!V#!temp_errV#!temp_upV#!temp_up_upV#!temp_downV#!temp_down_downV#!cpu_temp_upV#!cpu_temp_downV#!cpu_temp_drastic_changeV#!press_errV#!press_upV#!press_up_upV#!press_downV#!press_down_downV#!V#!flow_vel_errV#!tof_diff_errV#!sound_vel_errV#!snr_errV#!sig_upV#!sig_th_errV#!gain_errV#!ut_loseV#!input_waterV#    !media_otherV#    !dismantleV#    !measure_errV#    !V#    !gas_leakageV#


!lcd_upV#


!lcd_temp_lowV#


!flow_up_1V#


!flow_up_2V#


!flow_up_3V#


!constant_tiny_flowV#


!constant_flowV#


!cl_have_flowV#!V#!gas_cumulate_amendV#!balance_amendV#!temp_para_amendV#!press_para_amendV#!billing_para_amendV#!V#!flow_cal_amendV# !flow_para_amendV# !pluse_cal_amendV# !ut_err_amendV# !ut_cal_amendV# !V# PSYS_ALARM_Tà ÙSÖ*¥*Valarm_ctl_send_unionsys_alarm_ctl_sendPSYS_ALARM_CTL_SEND_UNION_Tß*Ú/!V#!small_flow_excisionV#!V#!both_way_measureV#!lcd_modeV#!V#!set_compressibilityV#!V#!press_corrected_manageV#!press_err_manageV#!V#!temp_corrected_manageV#!temp_err_manageV#!super_flow_manage_3V#!super_flow_manage_2V#!V#!V#!virtual_billingV#!V#!account_stateV#!V#!balance_display_setV#!price_display_setV#!logo_display_setV#!V#!billing_typeV#S–0é/Vfunc_cfg_unionÞsys_func_cfg_bytes_syPSYS_FUNC_CFG_UNION_TÚ„*Þ0state_bytes^#alarm_bytesb#tË tS”1õ0Vadmin_unionjsys_admin3PSYS_ADMIN_UNION_TfŽ*„2    alarm_valve_id#offset_bit#alarm_daily_num#alarm_byte#–8tV"VPSYS_ALARM_VALVE_ID_FUNC_TABLE_DRV_T®–qsys_para_amend_log_flag_gLqsys_alarm_id_g–qsys_valve_ctl_id_g–qsys_admin_g”qsys_alarm_ctl_bytes_gVqsys_alarm_send_bytes_gVqsys_func_cfg_bytes_g´üFsys_para_amend_log_flag_gfsys_alarm_id_g{sys_valve_ctl_id_g”sys_admin_g¦sys_alarm_ctl_bytes_gÂsys_alarm_send_bytes_gßsys_func_cfg_bytes_gþÿ_LINKED_LIST_H_ ALARM_LIST_NODE_LEN sizeof(ALARM_NODE_T)dY ..\Soft\..\Core\linked_list.hdefine_all.hadministrator.h8


..\Soft\linked_list.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM)óalarm_node_slist_data–#alarm_list_nextó#"·PALARM_NODE_T·qalarm_list_cnt8"÷qpList_head"0<alarm_list_cnt&pList_head_MAIN_H_ OS_YEAR ((((__DATE__[7] - '0') * 10 + (__DATE__[8] - '0')) * 10 + (__DATE__[9] - '0')) * 10 + (__DATE__[10] - '0'))


OS_MONTH (__DATE__[2] == 'n' ? (__DATE__[1] == 'a' ? 1 : 6) : __DATE__[2] == 'b' ? 2 : __DATE__[2] == 'r' ? (__DATE__[0] == 'M' ? 3 : 4) : __DATE__[2] == 'y' ? 5 : __DATE__[2] == 'l' ? 7 : __DATE__[2] == 'g' ? 8 : __DATE__[2] == 'p' ? 9 : __DATE__[2] == 't' ? 10 : __DATE__[2] == 'v' ? 11 : 12)OS_DAY ((__DATE__[4] == ' ' ? 0 : __DATE__[4] - '0') * 10 + (__DATE__[5] - '0'))OS_HOUR ((__TIME__[0] - '0') * 10 + (__TIME__[1] - '0'))OS_MINUTE ((__TIME__[3] - '0') * 10 + (__TIME__[4] - '0'))OS_SENCOND ((__TIME__[6] - '0') * 10 + (__TIME__[7] - '0'))"FW_VER_RESERVE 0x00&FW_VER_MAIN 0x01*FW_VER_MINOR 0x02.FW_VER_REVISE 0x032HARDWARE_VERSION "02154.0203.3":FIRMWARE_VERSION "1.3.0.0"HRS232_PRINTF WLCD_NEW \SYS_MODE_DEFAULT 8`SYS_LCD_DISPLAY_MODE_DEFAULT 0dSOFT_OR_HARD 0iGET_FLOW_DATA_PERIOD_TIME 10nSYS_WAKE_UP_TIME 30sDISPLAY_PARA_TIME 300xGPRS_TIMEOUT 120}GPRS_RECONNECTION_INTERVAL_TIME 10‚UC_ACTIVE_TIME 600‡SET_PARA_MODE_TIMEOUT 10ŒCAL_MODE_TIMEOUT 20‘CAL_MODE_FORCE_TIME 480•GPRS_PROTOCOL_SELECT 1™GPRS_HISTORY_OR_REAL_DATA 1KEY_VERSION 0x80¡NB_OR_4G_FLAG 0¥APN_SET_FLAG 0©IP_OR_YUMING_FLAG 0®AUTO_CALI_TIME_SEC_MAX 300±STANDARD_PRESSURE 101.325f´STANDARD_TEMPERATURE 293.15f¸CAL_TEST ¾FIRMWARE_VER_1 0x0000¿FIRMWARE_VER_2 0x0102ÀFIRMWARE_VER_3 0x0407@6 ..\Core\main.hdefine_all.h°


..\Core\main.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM    _LCD_SEGMENTCODE_23A_H_ LCD_NEW _LCD_SIZHULOG_23A 276_LCD_BATTERY_SHELL_23A 277_LCD_BATTERY_4_23A 278_LCD_BATTERY_3_23A 279_LCD_BATTERY_2_23A 271_LCD_BATTERY_1_23A 270!_LCD_METER_23A 269"_LCD_SIGNAL_COMMUNICATION_23A 268#_LCD_VALVE_M_23A 5$_LCD_LOCK_23A 6%_LCD_OPEN_23A 7&_LCD_CLOSE_23A 4)_LCD_WIFI_23A 63*_LCD_4G_Flag_23A 71+_LCD_4G_1_23A 70,_LCD_4G_2_23A 69-_LCD_4G_3_23A 77._LCD_4G_4_23A 78/_LCD_4G_5_23A 790_LCD_WARNING_23A 872_LCD_CONFIGURATION_23A 743_LCD_T_23A 734_LCD_CHARGE_23A 725_LCD_LOOKUP_23A 806_LCD_BACKSET_23A 757_LCD_K_23A 668_LCD_BOOTTOOTH_23A 659_LCD_CHECK_23A 64;_LCD_HORIZONTALLINE_1_23A 60<_LCD_SINGLEBILL_23A 68=_LCD_LADDERBILL_23A 76>_LCD_HORIZONTALLINE_2_23A 67@_LCD_WORK_CONDITION_23A 2A_LCD_SURPLUSE_23A 3B_LCD_STAND_CONDITION_23A 1C_LCD_TOTAL_23A 0E_LCD_X_23A 275F_LCD_ACCOUNT_23A 274G_LCD_BILLBACK_23A 273I_LCD_LAST_23A 266J_LCD_RECHARGE_23A 267K_LCD_SETTLEMENT_23A 260L_LCD_NOW_23A 272M_LCD_LADDER_23A 265N_LCD_UNIT_PRICE_23A 264P_LCD_N_1_23A 139Q_LCD_M3_1_23A 130R_LCD_YUAN_1_23A 131T_LCD_kPa_23A 140U_LCD_oC_23A 129V_LCD_L_pul_23A 128W_LCD_N_2_23A 142X_LCD_M3_2_23A 135Y_LCD_h_23A 134Z_LCD_YUAN_2_23A 133[_LCD_YUAN_M3_23A 132b_LCD_POINT1_23A 19c_LCD_POINT2_23A 24d_LCD_POINT3_23A 258e_LCD_POINT4_23A 256f_LCD_POINT5_23A 242g_LCD_POINT6_23A 240h_LCD_POINT7_23A 227i_LCD_POINT8_23A 224j_LCD_POINT9_23A 211k_LCD_POINT10_23A 200l_LCD_POINT11_23A 186m_LCD_POINT12_23A 184n_LCD_POINT13_23A 170o_LCD_POINT14_23A 168p_LCD_POINT15_23A 155q_LCD_POINT16_23A 152r_LCD_POINT17_23A 245s_LCD_POINT18_23A 247t_LCD_POINT19_23A 229u_LCD_POINT20_23A 231v_LCD_POINT21_23A 212w_LCD_POINT22_23A 215x_LCD_POINT23_23A 196y_LCD_POINT24_23A 191z_LCD_POINT25_23A 173{_LCD_POINT26_23A 175|_LCD_POINT27_23A 157}_LCD_POINT28_23A 159‚_LCD_1A_new 15ƒ_LCD_1B_new 23„_LCD_1C_new 21…_LCD_1D_new 12†_LCD_1E_new 13‡_LCD_1F_new 14ˆ_LCD_1G_new 22Š_LCD_2A_new 31‹_LCD_2B_new 62Œ_LCD_2C_new 61_LCD_2D_new 28Ž_LCD_2E_new 20_LCD_2F_new 30_LCD_2G_new 29’_LCD_3A_new 95“_LCD_3B_new 94”_LCD_3C_new 93•_LCD_3D_new 92–_LCD_3E_new 84—_LCD_3F_new 86˜_LCD_3G_new 85š_LCD_4A_new 88›_LCD_4B_new 81œ_LCD_4C_new 83_LCD_4D_new 91ž_LCD_4E_new 90Ÿ_LCD_4F_new 89 _LCD_4G_new 82¢_LCD_5A_new 11£_LCD_5B_new 18¤_LCD_5C_new 16¥_LCD_5D_new 8¦_LCD_5E_new 9§_LCD_5F_new 10¨_LCD_5G_new 17ª_LCD_6A_new 59«_LCD_6B_new 58¬_LCD_6C_new 57­_LCD_6D_new 56®_LCD_6E_new 25¯_LCD_6F_new 27°_LCD_6G_new 26²_LCD_7A_new 251³_LCD_7B_new 243´_LCD_7C_new 249µ_LCD_7D_new 248¶_LCD_7E_new 257·_LCD_7F_new 259¸_LCD_7G_new 250º_LCD_8A_new 235»_LCD_8B_new 226¼_LCD_8C_new 225½_LCD_8D_new 232¾_LCD_8E_new 241¿_LCD_8F_new 234À_LCD_8G_new 233Â_LCD_9A_new 219Ã_LCD_9B_new 210Ä_LCD_9C_new 208Å_LCD_9D_new 216Æ_LCD_9E_new 217Ç_LCD_9F_new 218È_LCD_9G_new 209Ê_LCD_10A_new 195Ë_LCD_10B_new 194Ì_LCD_10C_new 193Í_LCD_10D_new 192Î_LCD_10E_new 201Ï_LCD_10F_new 203Ð_LCD_10G_new 202Ò_LCD_11A_new 179Ó_LCD_11B_new 171Ô_LCD_11C_new 177Õ_LCD_11D_new 176Ö_LCD_11E_new 185×_LCD_11F_new 187Ø_LCD_11G_new 178Ú_LCD_12A_new 163Û_LCD_12B_new 154Ü_LCD_12C_new 153Ý_LCD_12D_new 160Þ_LCD_12E_new 169ß_LCD_12F_new 162à_LCD_12G_new 161â_LCD_13A_new 147ã_LCD_13B_new 138ä_LCD_13C_new 136å_LCD_13D_new 144æ_LCD_13E_new 145ç_LCD_13F_new 146è_LCD_13G_new 137ê_LCD_14A_new 252ë_LCD_14B_new 253ì_LCD_14C_new 254í_LCD_14D_new 255î_LCD_14E_new 263ï_LCD_14F_new 261ð_LCD_14G_new 262ò_LCD_15A_new 236ó_LCD_15B_new 228ô_LCD_15C_new 238õ_LCD_15D_new 239ö_LCD_15E_new 246÷_LCD_15F_new 244ø_LCD_15G_new 237ú_LCD_16A_new 220û_LCD_16B_new 213ü_LCD_16C_new 214ý_LCD_16D_new 223þ_LCD_16E_new 230ÿ_LCD_16F_new 221€_LCD_16G_new 222‚_LCD_17A_new 204ƒ_LCD_17B_new 197„_LCD_17C_new 199…_LCD_17D_new 207†_LCD_17E_new 206‡_LCD_17F_new 205ˆ_LCD_17G_new 198Š_LCD_18A_new 180‹_LCD_18B_new 181Œ_LCD_18C_new 182_LCD_18D_new 183Ž_LCD_18E_new 190_LCD_18F_new 188_LCD_18G_new 189’_LCD_19A_new 164“_LCD_19B_new 156”_LCD_19C_new 166•_LCD_19D_new 167–_LCD_19E_new 174—_LCD_19F_new 172˜_LCD_19G_new 165š_LCD_20A_new 148›_LCD_20B_new 141œ_LCD_20C_new 143_LCD_20D_new 151ž_LCD_20E_new 158Ÿ_LCD_20F_new 149 _LCD_20G_new 150XL ..\Function\LCD\..\Core\lcd_segmentcode.hmain.hø


..\Function\LCD\lcd_segmentcode.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMæLOOKUPTCONFIGURATIONCHECKKBACKSETWORKCONDITIONSURPLUSESTANDCONDITIONTOTAL    N_1


M3_1YUAN_1LAST RECHARGESETTLEMENTNOWLADDERUNITPRICEXHOMECLOUDkPaoCLpulN_2M3_2HYUAN_2YUAN_M3P_LCD_FLAGÃÁ _LCD_IO_API_H_ Segnum 48LCD_WRITE 0x7CLCD_READ 0x7DLCD_REG_DATA 0x80!LCD_PWR_GPIO_PORT GPIOB"LCD_PWR_PIN GPIO_Pin_6$LCD_BACKLIGHT_PWR_GPIO_PORT GPIOB%LCD_BACKLIGHT_PWR_PIN GPIO_Pin_5(LCD_PWR_ON GPIO_SetBits(LCD_PWR_GPIO_PORT,LCD_PWR_PIN))LCD_PWR_OFF GPIO_ResetBits(LCD_PWR_GPIO_PORT,LCD_PWR_PIN),LCD_BACKLIGHT_ON GPIO_SetBits(LCD_BACKLIGHT_PWR_GPIO_PORT,LCD_BACKLIGHT_PWR_PIN)-LCD_BACKLIGHT_OFF GPIO_ResetBits(LCD_BACKLIGHT_PWR_GPIO_PORT,LCD_BACKLIGHT_PWR_PIN)6LCD_DISPLAY_SEG(__SEG_NUM__) LCD_buffer[__SEG_NUM__ >> 3] |= 1 << (__SEG_NUM__ % 8)?LCD_CLEAR_SEG(__SEG_NUM__) LCD_buffer[__SEG_NUM__ >> 3] &= ~(1 << (uint8_t)(__SEG_NUM__ % 8))lb ..\Function\LCD\..\Core\lcd_io_api.hdefine_all.hlcd_segmentcode.hÜ


..\Function\LCD\lcd_io_api.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM­LCD_ALCD_BLCD_CLCD_DLCD_ELCD_FLCD_GLCD_HLCD_ILCD_J    LCD_K


LCD_LLCD_MLCD_N LCD_OLCD_PLCD_QLCD_RLCD_SLCD_TLCD_ULCD_VLCD_WLCD_XLCD_YLCD_ZPLCD_LETTERS_T¾]Í8/qLCD_bufferÂàÍLCD_buffer_LCD_H_ LCD_BACKLIGHT_SELECT(__ALKA_STATE__) ((__ALKA_STATE__ == RESET) ? LCD_BACKLIGHT_ON : LCD_BACKLIGHT_OFF)LCD_ALL_CLEAR Lcd_Write_Reg(0,LCD_SYSTEM_MODE_OFF_OFF,Segnum)LCD_ALL_DISPLAY Lcd_Write_Reg(0,LCD_buffer,Segnum)˜Œ ..\Function\LCD\..\Core\..\Function\KEY\..\Soft\lcd.hdefine_all.hkey.hadministrator.hlcd_io_api.hô


..\Function\LCD\lcd.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMÓCNV_NONECNV_PARA_MODE_ENTERCNV_CAL_MODE_ENTERCNV_PARA_MODE_EXITCNV_CAL_MODE_EXITCNV_DISPLAY_MODE_ENTERCNV_DISPLAY_MODE_EXITPTEMP_SYS_MODE_CNV_CMD·&³NORMAL_MODEDISPLAY_PARACALIB_MODESET_PARA_MODEPSYS_DISPLAY_MODEp-˜SC_INSTANT_TOTALPRICE_BALANCETEMP_SC_TOTALPRESS_SC_TOTALPNORMAL_PAGEË5 METER_NUMOTHER_METER_NUMDATE_TIMEIP_PORTOTHER_IP_PORTSW_VERHW_VERSOUND_VELSEC_CORR_NOWSEC_CORR_NOW_PARA_1    SEC_CORR_NOW_PARA_2


SEC_CORR_NOW_PARA_3SEC_CORR_NOW_PARA_4SEC_CORR_NOW_PARA_5 SEC_CORR_OLDSEC_CORR_OLD_PARA_1SEC_CORR_OLD_PARA_2SEC_CORR_OLD_PARA_3SEC_CORR_OLD_PARA_4SEC_CORR_OLD_PARA_5PPARA_DISPLAY_PAGE+L*ðnormal_page_status#para_page_status #PNORMAL_DISPLAY_PAGE_T¹S*ãtemp_sys_mode_flagS#sys_and_display_mode³#display_page_statusð#PSYS_DISPLAY_PAPA_T Yqsys_display_para_gcqsys_show_state_bytes_id_g–qsys_clear_state_bytes_id_g–qlcd_wake_up_flag_g8yø}sys_display_para_g–sys_show_state_bytes_id_g¸sys_clear_state_bytes_id_gÛlcd_wake_up_flag_g_LCD_NEW_H LCD_DRIVE_MODE_COMMAND_ADDR 0x82LCD_DRIVE_MODE_14_13 0x00 LCD_DRIVE_MODE_14_14 0x01LCD_DRIVE_MODE_18_13 0x02LCD_DRIVE_MODE_18_14 0x03LCD_SYSTEM_MODE_COMMAND_ADDR 0x84LCD_SYSTEM_MODE_OFF_OFF 0x00LCD_SYSTEM_MODE_ON_OFF 0x02LCD_SYSTEM_MODE_ON_ON 0x03LCD_FRAME_RATE_COMMAND_ADDR 0x86LCD_FRAME_RATE_80 0x00LCD_FRAME_RATE_160 0x01LCD_FLICKER_COMMAND_ADDR 0x88LCD_FLICKER_OFF 0x00LCD_FLICKER_2HZ 0x01LCD_FLICKER_1HZ 0x02LCD_FLICKER_05HZ 0x03'_LCD_WORK_TOTAL_FLOW_NEW 8(_LCD_STAND_TOTAL_FLOW_NEW 0)_LCD_WORK_FLOW_NEW 24*_LCD_STAND_FLOW_NEW 16+_LCD_DISCONNECT_NEW 56/_LCD_SIZHULOG_NEW 200_LCD_WIFI_NEW 361_LCD_VALVE_M_NEW 522_LCD_OPEN_NEW 683_LCD_CLOSE_NEW 845_LCD_BATTERY_1_NEW 1426_LCD_BATTERY_2_NEW 1437_LCD_BATTERY_3_NEW 1518_LCD_BATTERY_4_NEW 1509_LCD_BATTERY_SHELL_NEW 102;_LCD_LITH_NEW 110<_LCD_ALKA_NEW 101=_LCD_EXPOWER_NEW 109>_LCD_WARRING_NEW 108?_LCD_TOTAL_NEW 4@_LCD_UP_N_NEW 149A_LCD_M3_NEW 141B_LCD_P_NEW 100D_LCD_DOWN_NM3_NEW 148E_LCD_YUAN_NEW 140F_LCD_MARGIN_NEW 16G_LCD_UNIT_PRICE_NEW 272H_LCD_YUAN_M3_NEW 224J_LCD_FUSHU_NEW 0L_LCD_POINT1_NEW 180M_LCD_POINT2_NEW 192N_LCD_POINT3_NEW 240R_LCD_1A_NEW 15S_LCD_1B_NEW 14T_LCD_1C_NEW 13U_LCD_1D_NEW 12V_LCD_1E_NEW 5W_LCD_1F_NEW 7X_LCD_1G_NEW 6^_LCD_2A_NEW 31__LCD_2B_NEW 30`_LCD_2C_NEW 29a_LCD_2D_NEW 28b_LCD_2E_NEW 21c_LCD_2F_NEW 23d_LCD_2G_NEW 22i_LCD_3A_NEW 47j_LCD_3B_NEW 46k_LCD_3C_NEW 45l_LCD_3D_NEW 44m_LCD_3E_NEW 37n_LCD_3F_NEW 39o_LCD_3G_NEW 38q_LCD_4A_NEW 63r_LCD_4B_NEW 62s_LCD_4C_NEW 61t_LCD_4D_NEW 60u_LCD_4E_NEW 53v_LCD_4F_NEW 55w_LCD_4G_NEW 54y_LCD_5A_NEW 79z_LCD_5B_NEW 78{_LCD_5C_NEW 77|_LCD_5D_NEW 76}_LCD_5E_NEW 69~_LCD_5F_NEW 71_LCD_5G_NEW 70_LCD_6A_NEW 95‚_LCD_6B_NEW 94ƒ_LCD_6C_NEW 93„_LCD_6D_NEW 92…_LCD_6E_NEW 85†_LCD_6F_NEW 87‡_LCD_6G_NEW 86‰_LCD_7A_NEW 207Š_LCD_7B_NEW 206‹_LCD_7C_NEW 205Œ_LCD_7D_NEW 204_LCD_7E_NEW 213Ž_LCD_7F_NEW 215_LCD_7G_NEW 214‘_LCD_8A_NEW 191’_LCD_8B_NEW 190“_LCD_8C_NEW 189”_LCD_8D_NEW 188•_LCD_8E_NEW 197–_LCD_8F_NEW 199—_LCD_8G_NEW 198™_LCD_9A_NEW 175š_LCD_9B_NEW 174›_LCD_9C_NEW 173œ_LCD_9D_NEW 172_LCD_9E_NEW 181ž_LCD_9F_NEW 183Ÿ_LCD_9G_NEW 182¡_LCD_10A_NEW 159¢_LCD_10B_NEW 158£_LCD_10C_NEW 157¤_LCD_10D_NEW 156¥_LCD_10E_NEW 165¦_LCD_10F_NEW 167§_LCD_10G_NEW 166ª_LCD_11A_NEW 11«_LCD_11B_NEW 10¬_LCD_11C_NEW 9­_LCD_11D_NEW 8®_LCD_11E_NEW 1¯_LCD_11F_NEW 3°_LCD_11G_NEW 2³_LCD_12A_NEW 27´_LCD_12B_NEW 26µ_LCD_12C_NEW 25¶_LCD_12D_NEW 24·_LCD_12E_NEW 17¸_LCD_12F_NEW 19¹_LCD_12G_NEW 18¼_LCD_13A_NEW 43½_LCD_13B_NEW 42¾_LCD_13C_NEW 41¿_LCD_13D_NEW 40À_LCD_13E_NEW 33Á_LCD_13F_NEW 35Â_LCD_13G_NEW 34Å_LCD_14A_NEW 59Æ_LCD_14B_NEW 58Ç_LCD_14C_NEW 57È_LCD_14D_NEW 56É_LCD_14E_NEW 49Ê_LCD_14F_NEW 51Ë_LCD_14G_NEW 50Î_LCD_15A_NEW 75Ï_LCD_15B_NEW 74Ð_LCD_15C_NEW 73Ñ_LCD_15D_NEW 72Ò_LCD_15E_NEW 65Ó_LCD_15F_NEW 67Ô_LCD_15G_NEW 66Ø_LCD_16A_NEW 91Ù_LCD_16B_NEW 90Ú_LCD_16C_NEW 89Û_LCD_16D_NEW 88Ü_LCD_16E_NEW 81Ý_LCD_16F_NEW 83Þ_LCD_16G_NEW 82á_LCD_17A_NEW 203â_LCD_17B_NEW 202ã_LCD_17C_NEW 201ä_LCD_17D_NEW 200å_LCD_17E_NEW 209æ_LCD_17F_NEW 211ç_LCD_17G_NEW 210ê_LCD_18A_NEW 187ë_LCD_18B_NEW 186ì_LCD_18C_NEW 185í_LCD_18D_NEW 184î_LCD_18E_NEW 193ï_LCD_18F_NEW 195ð_LCD_18G_NEW 194õ_LCD_19A_NEW 171ö_LCD_19B_NEW 170÷_LCD_19C_NEW 169ø_LCD_19D_NEW 168ù_LCD_19E_NEW 177ú_LCD_19F_NEW 179û_LCD_19G_NEW 178þ_LCD_20A_NEW 267ÿ_LCD_20B_NEW 266€_LCD_20C_NEW 265_LCD_20D_NEW 264‚_LCD_20E_NEW 273ƒ_LCD_20F_NEW 275„_LCD_20G_NEW 274‡_LCD_21A_NEW 251ˆ_LCD_21B_NEW 250‰_LCD_21C_NEW 249Š_LCD_21D_NEW 248‹_LCD_21E_NEW 257Œ_LCD_21F_NEW 259_LCD_21G_NEW 258_LCD_22A_NEW 235‘_LCD_22B_NEW 234’_LCD_22C_NEW 233“_LCD_22D_NEW 232”_LCD_22E_NEW 241•_LCD_22F_NEW 243–_LCD_22G_NEW 242™_LCD_23A_NEW 219š_LCD_23B_NEW 218›_LCD_23C_NEW 217œ_LCD_23D_NEW 216_LCD_23E_NEW 225ž_LCD_23F_NEW 227Ÿ_LCD_23G_NEW 226¢_LCD_24A_NEW 155£_LCD_24B_NEW 154¤_LCD_24C_NEW 153¥_LCD_24D_NEW 152¦_LCD_24E_NEW 161§_LCD_24F_NEW 163¨_LCD_24G_NEW 162«_LCD_25A_NEW 139¬_LCD_25B_NEW 138­_LCD_25C_NEW 137®_LCD_25D_NEW 136¯_LCD_25E_NEW 145°_LCD_25F_NEW 147±_LCD_25G_NEW 146´_LCD_26A_NEW 107µ_LCD_26B_NEW 106¶_LCD_26C_NEW 105·_LCD_26D_NEW 104¸_LCD_26E_NEW 97¹_LCD_26F_NEW 99º_LCD_26G_NEW 98¿_LCD_27A_NEW 123À_LCD_27B_NEW 122Á_LCD_27C_NEW 121Â_LCD_27D_NEW 120Ã_LCD_27E_NEW 113Ä_LCD_27F_NEW 115Å_LCD_27G_NEW 114È_LCD_28A_NEW 127É_LCD_28B_NEW 126Ê_LCD_28C_NEW 125Ë_LCD_28D_NEW 124Ì_LCD_28E_NEW 117Í_LCD_28F_NEW 119Î_LCD_28G_NEW 118Ñ_LCD_29A_NEW 284Ò_LCD_29B_NEW 285Ó_LCD_29C_NEW 286Ô_LCD_29D_NEW 287Õ_LCD_29E_NEW 294Ö_LCD_29F_NEW 292×_LCD_29G_NEW 293Ú_LCD_30A_NEW 291Û_LCD_30B_NEW 290Ü_LCD_30C_NEW 289Ý_LCD_30D_NEW 288Þ_LCD_30E_NEW 281ß_LCD_30F_NEW 283à_LCD_30G_NEW 282ã_LCD_31A_NEW 307ä_LCD_31B_NEW 306å_LCD_31C_NEW 305æ_LCD_31D_NEW 304ç_LCD_31E_NEW 297è_LCD_31F_NEW 299é_LCD_31G_NEW 298ì_LCD_32A_NEW 264í_LCD_32B_NEW 265î_LCD_32C_NEW 266ï_LCD_32D_NEW 267ð_LCD_32E_NEW 259ñ_LCD_32F_NEW 257ò_LCD_32G_NEW 258õ_LCD_33A_NEW 312ö_LCD_33B_NEW 313÷_LCD_33C_NEW 314ø_LCD_33D_NEW 315ù_LCD_33E_NEW 275ú_LCD_33F_NEW 273û_LCD_33G_NEW 274ƒ_LCD_SIZHULOG_new 276…_LCD_BATTERY_SHELL_new 277†_LCD_BATTERY_4_new 278‡_LCD_BATTERY_3_new 279ˆ_LCD_BATTERY_2_new 271‰_LCD_BATTERY_1_new 270Œ_LCD_METER_new 269_LCD_SIGNAL_COMMUNICATION_new 268Ž_LCD_VALVE_M_new 5_LCD_LOCK_new 6_LCD_OPEN_new 7‘_LCD_CLOSE_new 4”_LCD_WIFI_new 63•_LCD_4G_Flag_new 71–_LCD_4G_1_new 70—_LCD_4G_2_new 69˜_LCD_4G_3_new 77™_LCD_4G_4_new 78š_LCD_4G_5_new 79›_LCD_WARNING_new 87_LCD_CONFIGURATION_new 74ž_LCD_T_new 73Ÿ_LCD_CHARGE_new 72 _LCD_LOOKUP_new 80¡_LCD_BACKSET_new 75¢_LCD_K_new 66£_LCD_BOOTTOOTH_new 65¤_LCD_CHECK_new 64¦_LCD_HORIZONTALLINE_1_new 60§_LCD_SINGLEBILL_new 68¨_LCD_LADDERBILL_new 76©_LCD_HORIZONTALLINE_2_new 67«_LCD_WORK_CONDITION_new 2¬_LCD_SURPLUSE_new 3­_LCD_STAND_CONDITION_new 1®_LCD_TOTAL_new 0°_LCD_X_new 275±_LCD_ACCOUNT_new 274²_LCD_BILLBACK_new 273´_LCD_LAST_new 266µ_LCD_RECHARGE_new 267¶_LCD_SETTLEMENT_new 260·_LCD_NOW_new 272¸_LCD_LADDER_new 265¹_LCD_UNIT_PRICE_new 264»_LCD_N_1_new 139¼_LCD_M3_1_new 130½_LCD_YUAN_1_new 131¿_LCD_kPa_new 140À_LCD_oC_new 129Á_LCD_L_pul_new 128Â_LCD_N_2_new 142Ã_LCD_M3_2_new 135Ä_LCD_h_new 134Å_LCD_YUAN_2_new 133Æ_LCD_YUAN_M3_new 132Í_LCD_POINT1_new 19Î_LCD_POINT2_new 24Ï_LCD_POINT3_new 258Ð_LCD_POINT4_new 256Ñ_LCD_POINT5_new 242Ò_LCD_POINT6_new 240Ó_LCD_POINT7_new 227Ô_LCD_POINT8_new 224Õ_LCD_POINT9_new 211Ö_LCD_POINT10_new 200×_LCD_POINT11_new 186Ø_LCD_POINT12_new 184Ù_LCD_POINT13_new 170Ú_LCD_POINT14_new 168Û_LCD_POINT15_new 155Ü_LCD_POINT16_new 152Ý_LCD_POINT17_new 245Þ_LCD_POINT18_new 247ß_LCD_POINT19_new 229à_LCD_POINT20_new 231á_LCD_POINT21_new 212â_LCD_POINT22_new 215ã_LCD_POINT23_new 196ä_LCD_POINT24_new 191å_LCD_POINT25_new 173æ_LCD_POINT26_new 175ç_LCD_POINT27_new 157è_LCD_POINT28_new 159í_LCD_1A_new 15î_LCD_1B_new 23ï_LCD_1C_new 21ð_LCD_1D_new 12ñ_LCD_1E_new 13ò_LCD_1F_new 14ó_LCD_1G_new 22õ_LCD_2A_new 31ö_LCD_2B_new 62÷_LCD_2C_new 61ø_LCD_2D_new 28ù_LCD_2E_new 20ú_LCD_2F_new 30û_LCD_2G_new 29ý_LCD_3A_new 95þ_LCD_3B_new 94ÿ_LCD_3C_new 93€_LCD_3D_new 92_LCD_3E_new 84‚_LCD_3F_new 86ƒ_LCD_3G_new 85…_LCD_4A_new 88†_LCD_4B_new 81‡_LCD_4C_new 83ˆ_LCD_4D_new 91‰_LCD_4E_new 90Š_LCD_4F_new 89‹_LCD_4G_new 82_LCD_5A_new 11Ž_LCD_5B_new 18_LCD_5C_new 16_LCD_5D_new 8‘_LCD_5E_new 9’_LCD_5F_new 10“_LCD_5G_new 17•_LCD_6A_new 59–_LCD_6B_new 58—_LCD_6C_new 57˜_LCD_6D_new 56™_LCD_6E_new 25š_LCD_6F_new 27›_LCD_6G_new 26_LCD_7A_new 251ž_LCD_7B_new 243Ÿ_LCD_7C_new 249 _LCD_7D_new 248¡_LCD_7E_new 257¢_LCD_7F_new 259£_LCD_7G_new 250¥_LCD_8A_new 235¦_LCD_8B_new 226§_LCD_8C_new 225¨_LCD_8D_new 232©_LCD_8E_new 241ª_LCD_8F_new 234«_LCD_8G_new 233­_LCD_9A_new 219®_LCD_9B_new 210¯_LCD_9C_new 208°_LCD_9D_new 216±_LCD_9E_new 217²_LCD_9F_new 218³_LCD_9G_new 209µ_LCD_10A_new 195¶_LCD_10B_new 194·_LCD_10C_new 193¸_LCD_10D_new 192¹_LCD_10E_new 201º_LCD_10F_new 203»_LCD_10G_new 202½_LCD_11A_new 179¾_LCD_11B_new 171¿_LCD_11C_new 177À_LCD_11D_new 176Á_LCD_11E_new 185Â_LCD_11F_new 187Ã_LCD_11G_new 178Å_LCD_12A_new 163Æ_LCD_12B_new 154Ç_LCD_12C_new 153È_LCD_12D_new 160É_LCD_12E_new 169Ê_LCD_12F_new 162Ë_LCD_12G_new 161Í_LCD_13A_new 147Î_LCD_13B_new 138Ï_LCD_13C_new 136Ð_LCD_13D_new 144Ñ_LCD_13E_new 145Ò_LCD_13F_new 146Ó_LCD_13G_new 137Õ_LCD_14A_new 252Ö_LCD_14B_new 253×_LCD_14C_new 254Ø_LCD_14D_new 255Ù_LCD_14E_new 263Ú_LCD_14F_new 261Û_LCD_14G_new 262Ý_LCD_15A_new 236Þ_LCD_15B_new 228ß_LCD_15C_new 238à_LCD_15D_new 239á_LCD_15E_new 246â_LCD_15F_new 244ã_LCD_15G_new 237å_LCD_16A_new 220æ_LCD_16B_new 213ç_LCD_16C_new 214è_LCD_16D_new 223é_LCD_16E_new 230ê_LCD_16F_new 221ë_LCD_16G_new 222í_LCD_17A_new 204î_LCD_17B_new 197ï_LCD_17C_new 199ð_LCD_17D_new 207ñ_LCD_17E_new 206ò_LCD_17F_new 205ó_LCD_17G_new 198õ_LCD_18A_new 180ö_LCD_18B_new 181÷_LCD_18C_new 182ø_LCD_18D_new 183ù_LCD_18E_new 190ú_LCD_18F_new 188û_LCD_18G_new 189ý_LCD_19A_new 164þ_LCD_19B_new 156ÿ_LCD_19C_new 166€_LCD_19D_new 167_LCD_19E_new 174‚_LCD_19F_new 172ƒ_LCD_19G_new 165…_LCD_20A_new 148†_LCD_20B_new 141‡_LCD_20C_new 143ˆ_LCD_20D_new 151‰_LCD_20E_new 158Š_LCD_20F_new 149‹_LCD_20G_new 150pd ..\Pre_Drivers\..\Core\..\Function\LCD\1lcd_new.hdefine_all.hlcd.hô


..\Pre_Drivers\1lcd_new.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMqLCD_Menu_Levelœqk1œqk2œqkkk‘7ø»LCD_Menu_LevelÒk1Ýk2èkkk__LCD_H SEGNUM 48LCD_WAKEUP_TIME 60#LCD_CS_LOW GPIO_ResetBits(GPIOC, GPIO_Pin_8)$LCD_CS_HIGH GPIO_SetBits(GPIOC, GPIO_Pin_8)&LCD_RD_LOW GPIO_ResetBits(GPIOC, GPIO_Pin_7)'LCD_RD_HIGH GPIO_SetBits(GPIOC, GPIO_Pin_7))LCD_WR_LOW GPIO_ResetBits(GPIOB, GPIO_Pin_8)*LCD_WR_HIGH GPIO_SetBits(GPIOB, GPIO_Pin_8),LCD_DATA_LOW GPIO_ResetBits(GPIOB, GPIO_Pin_9)-LCD_DATA_HIGH GPIO_SetBits(GPIOB, GPIO_Pin_9).Read_data GPIO_ReadInputDataBit(GPIOB, GPIO_Pin_9)1LCD_COMMAND 0x042LCD_WriteModeID 0x053LCD_ReadModeID 0x064LCD_INIT 0xff5LCD_ON 0x036LCD_OSC 0x01:_LCD_WORK_TOTAL_FLOW 8;_LCD_STAND_TOTAL_FLOW 0<_LCD_WORK_FLOW 24=_LCD_STAND_FLOW 16>_LCD_DISCONNECT 56B_LCD_SIZHULOG 20C_LCD_WIFI 36D_LCD_VALVE_M 52E_LCD_OPEN 68F_LCD_CLOSE 84H_LCD_BATTERY_1 246I_LCD_BATTERY_2 247J_LCD_BATTERY_3 255K_LCD_BATTERY_4 254L_LCD_BATTERY_SHELL 102N_LCD_LITH 110O_LCD_ALKA 101P_LCD_EXPOWER 109Q_LCD_WARRING 108R_LCD_TOTAL 4S_LCD_UP_N 253T_LCD_M3 245U_LCD_P 100W_LCD_DOWN_NM3 252X_LCD_YUAN 244Y_LCD_MARGIN 16Z_LCD_UNIT_PRICE 376[_LCD_YUAN_M3 328]_LCD_FUSHU 0__LCD_POINT1 284`_LCD_POINT2 296a_LCD_POINT3 344f_LCD_1A 15g_LCD_1B 14h_LCD_1C 13i_LCD_1D 12j_LCD_1E 5k_LCD_1F 7l_LCD_1G 6n_LCD_2A 31o_LCD_2B 30p_LCD_2C 29q_LCD_2D 28r_LCD_2E 21s_LCD_2F 23t_LCD_2G 22v_LCD_3A 47w_LCD_3B 46x_LCD_3C 45y_LCD_3D 44z_LCD_3E 37{_LCD_3F 39|_LCD_3G 38~_LCD_4A 63_LCD_4B 62€_LCD_4C 61_LCD_4D 60‚_LCD_4E 53ƒ_LCD_4F 55„_LCD_4G 54†_LCD_5A 79‡_LCD_5B 78ˆ_LCD_5C 77‰_LCD_5D 76Š_LCD_5E 69‹_LCD_5F 71Œ_LCD_5G 70Ž_LCD_6A 95_LCD_6B 94_LCD_6C 93‘_LCD_6D 92’_LCD_6E 85“_LCD_6F 87”_LCD_6G 86–_LCD_7A 311—_LCD_7B 310˜_LCD_7C 309™_LCD_7D 308š_LCD_7E 317›_LCD_7F 319œ_LCD_7G 318ž_LCD_8A 295Ÿ_LCD_8B 294 _LCD_8C 293¡_LCD_8D 292¢_LCD_8E 301£_LCD_8F 303¤_LCD_8G 302¦_LCD_9A 279§_LCD_9B 278¨_LCD_9C 277©_LCD_9D 276ª_LCD_9E 285«_LCD_9F 287¬_LCD_9G 286®_LCD_10A 263¯_LCD_10B 262°_LCD_10C 261±_LCD_10D 260²_LCD_10E 269³_LCD_10F 271´_LCD_10G 270·_LCD_11A 11¸_LCD_11B 10¹_LCD_11C 9º_LCD_11D 8»_LCD_11E 1¼_LCD_11F 3½_LCD_11G 2À_LCD_12A 27Á_LCD_12B 26Â_LCD_12C 25Ã_LCD_12D 24Ä_LCD_12E 17Å_LCD_12F 19Æ_LCD_12G 18É_LCD_13A 43Ê_LCD_13B 42Ë_LCD_13C 41Ì_LCD_13D 40Í_LCD_13E 33Î_LCD_13F 35Ï_LCD_13G 34Ò_LCD_14A 59Ó_LCD_14B 58Ô_LCD_14C 57Õ_LCD_14D 56Ö_LCD_14E 49×_LCD_14F 51Ø_LCD_14G 50Û_LCD_15A 75Ü_LCD_15B 74Ý_LCD_15C 73Þ_LCD_15D 72ß_LCD_15E 65à_LCD_15F 67á_LCD_15G 66ä_LCD_16A 91å_LCD_16B 90æ_LCD_16C 89ç_LCD_16D 88è_LCD_16E 81é_LCD_16F 83ê_LCD_16G 82í_LCD_17A 307î_LCD_17B 306ï_LCD_17C 305ð_LCD_17D 304ñ_LCD_17E 313ò_LCD_17F 315ó_LCD_17G 314ö_LCD_18A 291÷_LCD_18B 290ø_LCD_18C 289ù_LCD_18D 288ú_LCD_18E 297û_LCD_18F 299ü_LCD_18G 298_LCD_19A 275‚_LCD_19B 274ƒ_LCD_19C 273„_LCD_19D 272…_LCD_19E 281†_LCD_19F 283‡_LCD_19G 282Š_LCD_20A 371‹_LCD_20B 370Œ_LCD_20C 369_LCD_20D 368Ž_LCD_20E 377_LCD_20F 379_LCD_20G 378“_LCD_21A 355”_LCD_21B 354•_LCD_21C 353–_LCD_21D 352—_LCD_21E 361˜_LCD_21F 363™_LCD_21G 362œ_LCD_22A 339_LCD_22B 338ž_LCD_22C 337Ÿ_LCD_22D 336 _LCD_22E 345¡_LCD_22F 347¢_LCD_22G 346¥_LCD_23A 323¦_LCD_23B 322§_LCD_23C 321¨_LCD_23D 320©_LCD_23E 329ª_LCD_23F 331«_LCD_23G 330®_LCD_24A 259¯_LCD_24B 258°_LCD_24C 257±_LCD_24D 256²_LCD_24E 265³_LCD_24F 267´_LCD_24G 266·_LCD_25A 243¸_LCD_25B 242¹_LCD_25C 241º_LCD_25D 240»_LCD_25E 249¼_LCD_25F 251½_LCD_25G 250À_LCD_26A 107Á_LCD_26B 106Â_LCD_26C 105Ã_LCD_26D 104Ä_LCD_26E 97Å_LCD_26F 99Æ_LCD_26G 98Ë_LCD_27A 123Ì_LCD_27B 122Í_LCD_27C 121Î_LCD_27D 120Ï_LCD_27E 113Ð_LCD_27F 115Ñ_LCD_27G 114Ô_LCD_28A 127Õ_LCD_28B 126Ö_LCD_28C 125×_LCD_28D 124Ø_LCD_28E 117Ù_LCD_28F 119Ú_LCD_28G 118Ý_LCD_29A 284Þ_LCD_29B 285ß_LCD_29C 286à_LCD_29D 287á_LCD_29E 294â_LCD_29F 292ã_LCD_29G 293æ_LCD_30A 291ç_LCD_30B 290è_LCD_30C 289é_LCD_30D 288ê_LCD_30E 281ë_LCD_30F 283ì_LCD_30G 282ï_LCD_31A 307ð_LCD_31B 306ñ_LCD_31C 305ò_LCD_31D 304ó_LCD_31E 297ô_LCD_31F 299õ_LCD_31G 298ø_LCD_32A 264ù_LCD_32B 265ú_LCD_32C 266û_LCD_32D 267ü_LCD_32E 259ý_LCD_32F 257þ_LCD_32G 258_LCD_33A 312‚_LCD_33B 313ƒ_LCD_33C 314„_LCD_33D 315…_LCD_33E 275†_LCD_33F 273‡_LCD_33G 274Š_LCD_DOT1 320‹_LCD_DOT2 80Œ_LCD_DOT3 232_LCD_DOT4 268Ž_LCD_DOT5 280_LCD_DOT6 0_LCD_DOT7 31‘_LCD_DOT8 39’_LCD_DOT9 1“_LCD_DOT10 47”_LCD_DOT11 168•_LCD_DOT12 176–_LCD_DOT13 184—_LCD_DOT14 192˜_LCD_DOT15 200™_LCD_DOT16 63š_LCD_DOT17 208›_LCD_DOT18 216œ_LCD_DOT19 62_LCD_DOT20 72 _LCD_COLON1_U 0¡_LCD_COLON1_D 23£_LCD_COLON2_U 1¤_LCD_COLON2_D 39¦_LCD_COLON3_U 63§_LCD_COLON3_D 200©_LCD_COLON4_U 62ª_LCD_COLON4_D 216­SIZHULOG 0®NET_SIG 1¯POWER_CONNECT 2°WARNING_SYM 3²BAT_CAP_0 0³BAT_CAP_1 1´BAT_CAP_2 2µBAT_CAP_3 3¶BAT_CAP_4 4L@ ..\Pre_Drivers\..\Core\1lcd.hmain.hÔ


..\Pre_Drivers\1lcd.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARMÂœ/qLCD_Buffer·ØÂLCD_Buffer !"__MENU_H 


LEVEL1 0X01LEVEL2 0X02LEVEL_POWER_OFF 0X05MENU_ORG 0X00External_Power 0Battery_Below20 1Battery_Upon20 2Battery_Upon40 3Battery_Upon60 4Battery_Upon80 5PF ..\Pre_Drivers\..\Core\menu.hdefine_all.h„


..\Pre_Drivers\menu.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM)émenu_modulesystem_tickœ#ble_cntœ#gprs_one_key_upœ#system_menulevelœ#key_numœ#lcd_stateœ#lcd_actœ#flow_tickœ#PMENU_MODULE_T·))°lcdSignal_flagLCD_show_on_flagœ#PowerSignal_Selectœ#Device_Alarmœ#Device_Warningœ#Config_Modeœ#LCD_first_upœ#Sleepœ#PLCDSIGNAL_FLAG~6qLCD_TYPE_FLAGœqmenu_dataiqLCDSignal_flag_g0CˆFLCD_TYPE_FLAG\menu_datalLCDSignal_flag_g$%&__bool_true_false_are_defined 1__ARMCLIB_VERSION 5060037bool _Booltrue 1false 0LC D:\Keil5\ARM\ARMCC\Bin\..\include\stdbool.hˆD:\Keil5\ARM\ARMCC\Bin\..\include\stdbool.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]()*_LCD_IIC_H LCD_ADDR_WRITE 0x7CLCD_ADDR_READ 0x7D


LCD_REG_DATA_ADDR 0x80„y ..\Pre_Drivers\..\Core\D:\Keil5\ARM\ARMCC\Bin\..\include\lcd_iic.hdefine_all.hstdbool.h¸


..\Pre_Drivers\lcd_iic.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM,-. — ..\Pre_Drivers\..\Pre_Drivers\ex_rtc.cex_rtc.hdevicegpioinit.hpara.h1lcd_new.h1lcd.hmenu.hlcd_iic.hD


..\Pre_Drivers\ex_rtc.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]F:\work\Project\SZV10X_Test\SZV103_FM33A0xxEV_Hard_Test\KEIL_MDKARM_Complex long_double_Complex double_Complex floatuvoid)—__va_list__ap#"öP__builtin_va_listü¿œ"œ0!/!I$>%%%%    %C


%C%% %%%C%C&I(( 1111 I8     I  I8    4! I8     "I#7I$I%I&I    'I(I)*+,-./404142434445.:;9?I6.:;9?7.:;9G8.:;9?I 9.:;9? :.:;9G ;.:;9?I<.:;9?=.:;9G>.:;9?I@?.:;9?@@.:;9G@A.:;9?I@


B.:;9?@


C.:;9G@


D1E1F1XYWG1XYWH.1I.1@J.1@


K.1L.<4I?M.<4?NIOPI:;9QI4RSTUVW1X4I    ,Y4I    Z4I[4I,\4I]4I    4^4I    ,4_4I4`4I,4a4I4b41    ,c41d41,e41f1g1hI    iIjIkI    4lI    ,4mI4n1    o1p4I    ?q4I?<r4I,s4It5Iu;v=w%x<%Component: ARM Compiler 5.06 update 6 (build 750) Tool: armlink [4d35ed]armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=9931,9931,6642 --cpu=Cortex-M0 --fpu=SoftVFP --output=.\objects\ex_rtc.o --vfemode=force


Input Comments:p3030-3Component: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]armasm --debug --diag_suppress=9931,9931,1602,1073 --cpu=Cortex-M0 --fpu=SoftVFP --apcs=/interwork/interwork --no_divide ex_rtc.oComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]ArmCC --c99 --split_sections --debug -c --gnu -o.\objects\ex_rtc.o --depend=.\objects\ex_rtc.d --cpu=Cortex-M0 --apcs=interwork -O0 --diag_suppress=9931 -I..\Core -I..\Drivers -I..\Core\Include -I..\Hardware -I.\RTE\Device -I..\Hardware\CLOCK -I..\Hardware\DELAY -I..\Hardware\GPIO -I..\Hardware\UART -I..\Hardware\TIM -I..\Function\KEY -I..\Hardware\EXTI -I..\Hardware\RTC -I..\Hardware\ADC -I..\Hardware\I2C -I..\Function\LCD -I..\Function\EXTERN_RTC -I..\Hardware\SPI -I..\Function\GPRS -I..\Function\HARDWARE_WATCHDOG -I..\Function\IR_NEC -I..\Function\MEASURE_INTERACTION -I..\Function\POWER_MANAGE -I..\Function\STORAGE -I..\Function\UPPER_COMPUTER -I..\Function\VALVE -I..\Soft -I..\MultiButton -I..\USMART -I..\Hardware\DMA -I..\Hardware\ON_CHIP_FLASH -I..\Hardware\SVD -I..\Function\OFF_CHIP_FLASH -I..\Hardware\CRC -I..\Function\BOOTLOADER_IAP -I..\Hardware\COMP -I..\Function\E2P -I..\CmBackTrace -I..\Pre_Drivers -I..\Pre_Drivers -I..\Function\PROJECT_TETS -I.\RTE\_UFG220_FM33A0_MainSystem -ID:\Keil5\ARM\PACK\ARM\CMSIS\5.3.0\CMSIS\Include -ID:\Keil5\ARM\PACK\Keil\FM33A0XXEV_DFP\0.0.4\Device\Include -D__MICROLIB -D__UVISION_VERSION=525 -D_RTE_ -D__VTOR_PRESENT --omf_browse=.\objects\ex_rtc.crf ..\Pre_Drivers\ex_rtc.cnFnFnFkF®nFnFnFkF,nFkFf_F_F    _F1EFñÿ9F-Fð


TðT DD /Fñÿ§E§EœE)EE)EE)EE)EåD)EàD)EÚD    )E    ÀD¦DŒDrDXD@D(DDöCÝCÄC«C“CzCaCHC/C C!þB"æB#ÎB$¶B%žB&ƒB'fB(IB),B*B+òA,ÕA-¼A/—ArAdA[A    NA    AA    5A    )A    A    A    A    ó@    à@    Í@    º@    ¬@    ž@    @    ˆ@    w@    =@0@íÉ?‹?K?H?ûÊ>Ո>?G>;>7Å=ي=áF=é


=.Î<åŠ<UF<Q<Y½;½x;É4;‰ï:]«:eg:‘#:mà9Áš9U9q9µÌ8u€8Í;8y÷7i±7¥j7}&7±â6…6¹Y6a6™Ñ55•I5­5¾4¡y4Å44©û3öÂ3…3*E3 3    ¿2…2K2!2ñÔ1&˜13]1C!1ÑÚ0L›0Ýn0íA00Ý/H§/ûv/ÕA/? /;Ø.7¥.Ùw.á@.é..â-å«-Ut-Q;-Y-½Í,ɖ,‰^,]',eð+‘¹+mƒ+ÁJ++qÚ*µ£*ud*Í,*yõ)i¼)¥‚)}K)±)…Ü(¹¥(an(™7((•É'­'X'¡ 'Åè&©¼&ö&`&*-& õ%    Á%”%g%!:%ñ


%&Û$3­$C~$ÑD$L$ÝØ#ìž#`# #GÝ"úŸ"Ô]">":Ú!6š!Ø_!à!èß -£ ä_ T PÕX’¼MÈ    ˆÄ\€d<ølµÀo€*på´¡tUÌxÌh†¤?|û°·„r¸.`꘦Œb”¬Øœ“ NÄ    ¨Ðõ—Z)Õ”ÿZ  æð©%m22BöЯKpÜ3ëöµrF,ùëÓ¦=b95ÚלßUç,×ãSIOWº»rÇ+‡ã[œcUkÈ ¿ 7 oï³¨sYËwÊg£7{ð


¯©


ƒa


·


_Ó    —Œ    ‹E    “þ«µ›mŸ%Ãݧ¡ôe%(âšVþÜŸï_$ 1âA£ÏYJÛÙ—Pü÷Ö’M"Ñò’DGMžE®EJE0E,çDf8$ùçÙ̾°¢˜ŠueQ?5,#")Eñÿpomqrn


]ˆ


s¨


l°J´K


g


f


f


g


f&


e,


c:


e@


dD


h


g


f


f


f*


h


k


^


s,[


 


k


s0


^6


sJ


tN


aT


uX


bh[ljpiG²¶ºäèFG²¶ºäèF8<8<0)40*40+4!0,40-4#\±@µ5\¼jÂKÖjÜLð•öM    •N"•(O;•APV•\Qq•wRŒ•’S¬•²TÌ•ÒUì•òV• W"•(X=•CYR•XZp•v[‹i‘J\±µ¹6ÐÔØ;ã•ç;ñiõ;ÿ•;•\±µ¹7ÑÕÙ<ä•è<òiö<•<•\±!µ!¹8Í!Ñ!Õ=à•ä=ð•ô=ÿ•=•=•!=+•/=9•==E•\±µ¹9ÎÒÖ>\±#µ#¹:ß#ã#ç?ï•<<<!<<#/01234\€L„\¸¼ßЕ֕ë•ù••\·»ÞÕ•ä•ø••1•K•Z•k•…•”•¥•¿•Î•ß•ù••(•C•q•‹•š•·•Ò•ý••*•>•]•x•\¸¼ÝÑ•ß•í•û•    •"•C•Z•s•”•«•¹•Ð•Þ•ì•ú••!•D•V•m•†•¾•ð•"•U•r•¢••;•`,`R•X`l•`¸`Ý`è••`*•b•q••••ª•\MƒÇi–\¶ºÚx•„•\½OÁו˜\µ#¹æÊ•Ù•ç•ø•``(`8`G`V`\µ"¹å\·$»ç\¶(ºë\µ9¹ü\µ)¹ìÊ•Ø•æ•ö••`#•4•B•\µ3¹ö\µ+¹îu•…•••¦•¶•Æ•×`è`ù``•*•:•M•\¶.ºñM•\µ0¹ó\¶2ºõ\¸5¼ø\·-»ð\µ7¹úȕוä`ñ•þ•\µ'¹êÈ•Ø`    •`L•]•p•„••`Ê•Û•ì•`=•W•q•‰•¢•º•Ó•\µ;¹þȕוå•ó•••!•k•{•‹•\µ*¹í\µ<¹ÿ\µ:¹ý\·>»Ê`Ø`ç`ö``•"•1`@•M•\•k•{`‹`›`ª•º•È•Ö`ä`ò`\¶?º¹•ú•)`:`K`Z•i•y•Š`™`§`¸•Æ`Ô`å`ö`\·4»÷\¶Aº\µ=¹Ê•Û•ë•ù```$`\µ6¹ù\¶/ºò\¶8ºûЕá•ø• •(•=•V•k•†•˜•\´%¸è\´,¸ï\¶@º\¶&ºé\º1¾ô\€N„\¬°Ü\®²à\·P»\³·á\±!µäÄ•Ñ•Þ•í•û•    ••?•O•^•m•{•‰•\¹½â\¯³×Ë•ú•    •\¯J³ ô•• ••0•D•]•u•‰•£•¼•Ö•ô••.•K•g•ƒ•š•®•È•ß•ú••,•C•^•w•¡•»•Ù•ï•••1•O•l•‰•¥•Â•Þ•÷••0•N•i•ƒ•¡•¹•Ö•ó••%•C•e•ˆ• •À•E•f•†•¥•È•ô••1•U•y•ž•Ã•ç•     •-    •K    •f    •    •¦    •Ò    •ù    •!


•R


•r


•“


•Æ


•â


••#•e•{•ª•¼•2 •g •“ •³ •Û •ù ••5•W••£•ó••!•2•D•T•a•o••¶•Ä•Ý•U•g•o]§•½• ••*•8•E•R•É••3•‰•£•“\¯B³Ë`‹\±µÛ¿•Ì•æ•••%•=•J•d•q•‰• •¿•á•    •    •5    •B    •^    •z    •–    •²    •Î    •ã    •ú    •


•'


•>


•V


•c


•{


•ˆ


•


•±


•È


•Þ


•ù


••+•O•e•z•’•©•Å•Ò•ë•••2•E•\•q•…•ž•¶•Î•Û•ó• • •5 •K •a •€ •š •³ •À •ç •••)•=•U•b•|•‰•¡•º•Ç•æ••'•4•P•l•ˆ•¤•À•Õ•ì•••0•H•U•m•z••£•º•Ð•ë•••A•W•l•„•›•·•Ä•Ý•ö••$•7•N•c•w••§•½•Õ•â•ú• •&•<•R•h•‡•¡•º•Ç•æ•••9•X•e•€•œ•¸•Ñ•ê•÷••€• •­•Ê•ß•ì•••<•Y•f•ˆ•¤•Ä•ä•ñ•þ••'•A•N•n•Œ•©•¶•Ï•â•n•


•••a\¯G³


Ôa•\¨H¬\»F¿    \¶EºÆ•Ž\¯C³²aÕað•Œ\³·Ù̕וâ•î•_\¯³Ø»•^\¯I³Õ•æ•ÿ••*•=•N•a•¤•À•Ö•î•••(•V•’\K…\²D¶\± µã8•A•.ARM.attributes.strtab.shstrtab.rel.debug_pubnames.rel.debug_frame.rel.debug_line.rel.debug_info.reli.set_RTC8025T_peroid_alarm.reli.Time_Set.reli.R8025T_write.reli.R8025T_read.reli.Get_Time.symtab.comment.arm_vfe_header__ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000__ARM_grp.ex_rtc.c.2_wi1000_Cop_GpkcCsb_800000__ARM_grp.lcd_iic.h.2_Mw0000_q4tdBSyVENe_300000__ARM_grp.stdbool.h.2_ou0000_sX0KWuH_8w2_300000__ARM_grp.menu.h.2_7N2000_pwE5LTwnxO3_J00000__ARM_grp.1lcd.h.2_Bj6000_0DpFEv$qZsf_f00000__ARM_grp.1lcd_new.h.2_X$9000_NQCZJ0R2jX0_l00000__ARM_grp.lcd.h.2_VE7000_sZu_e6bBIC9_$50000__ARM_grp.lcd_io_api.h.2_h33000_shag9T72CS0_f00000__ARM_grp.lcd_segmentcode.h.2_EN2000_3d2rxbsK$Td_300000__ARM_grp.main.h.2_ga1000_6c0asbwEXV7_300000__ARM_grp.linked_list.h.2_0$6000_T$gveB7RZS9_Z50000__ARM_grp.administrator.h.2_El7000_yWsVCV8hKR8_P50000__ARM_grp.key.h.2_cV7000_B55fAyLVs59_p00000__ARM_grp.para.h.2_Ez8000_khDVHof8zWa_t40000__ARM_grp.1ADC.h.2_Qp1000_8FudzCBNeP8_900000__ARM_grp.devicegpioinit.h.2_0w4000_64Z46PStLCa_300000__ARM_grp.ex_rtc.h.2_Qi1000_JeDdoy8l9Z9_j00000__ARM_grp.delay.h.2_EE0000_7GGSWSTJWL4_300000__ARM_grp.user_init.h.2_ot0000_jZWuqvPHwt6_300000__ARM_grp.define_all.h.2_kN0000_fD9tyG24Hn2_300000__ARM_grp.bintohex.h.2_Y33000_duI5XZW3h40_300000__ARM_grp.string.h.2_kw0000_aP4aobzpRT7_300000__ARM_grp.fm33a0xxev_include_all.h.2_UQ0000_xxdaGLUj6Cf_300000__ARM_grp.fm33a0xxev_cdif.h.2_kJ0000_JQTXKb9R3mc_300000__ARM_grp.fm33a0xxev_vrtc.h.2_YK1000_bGKK6ktMN$f_300000__ARM_grp.fm33a0xxev_et.h.2_4h3000_57B3Rgey0je_300000__ARM_grp.fm33a0xxev_bt.h.2_kV3000_MyPILKKQ6H1_300000__ARM_grp.fm33a0xxev_qspi.h.2_Qr4000_J7HoI7y0B84_g00000__ARM_grp.fm33a0xxev_hash.h.2_kO0000_KuZ300H4_80_300000__ARM_grp.fm33a0xxev_pae.h.2_sJ3000_RoohqLgJd45_300000__ARM_grp.fm33a0xxev_svd.h.2_YX4000_B$e1cGixg00_i00000__ARM_grp.fm33a0xxev_wwdt.h.2_4H0000_TVah5VHd$Wd_300000__ARM_grp.fm33a0xxev_lptim.h.2_8q4000_BFHTRuxu1ie_300000__ARM_grp.fm33a0xxev_uart.h.2_s_5000_gGxJA_bT3g3_r00000__ARM_grp.fm33a0xxev_u7816.h.2_sD5000_T7w3HnfvCn7_w00000__ARM_grp.fm33a0xxev_rng.h.2_IJ0000_vzTWbGvNuZe_300000__ARM_grp.fm33a0xxev_spi.h.2_AU2000_7eFMvsSXzw0_300000__ARM_grp.fm33a0xxev_dbg.h.2_4f1000_pVDK34opiR1_300000__ARM_grp.fm33a0xxev_rtc.h.2_sS3000_IylpavQ6INd_g00000__ARM_grp.fm33a0xxev_cmu.h.2_Ekb000_qHj10Bv8MJ6_v00000__ARM_grp.fm33a0xxev_pmu.h.2_Af5000_lOjh94cQJQf_g00000__ARM_grp.fm33a0xxev_flash.h.2_0_1000_TO3GMzQCtL1_300000__ARM_grp.fm33a0xxev_lpuart.h.2_oE2000_Ig0fu_ljcn3_300000__ARM_grp.fm33a0xxev_iwdt.h.2_4L0000_LcDBel0usy8_300000__ARM_grp.fm33a0xxev_i2c.h.2_IS1000_g4ErNZQBGwd_300000__ARM_grp.fm33a0xxev_gpio.h.2_815000_upDQZZvAzia_700000__ARM_grp.fm33a0xxev_dma.h.2_ks8000_OrTMHX6QIe0_p00000__ARM_grp.fm33a0xxev_lcd.h.2_Y$4000_kUmWRnNV3_4_300000__ARM_grp.fm33a0xxev_crc.h.2_8C4000_La7VPM3Tip8_k00000__ARM_grp.fm33a0xxev_rmu.h.2_4L2000_C$q$9vNhOp0_300000__ARM_grp.fm33a0xxev_comp.h.2_k_2000_e5VaGx8gTre_300000__ARM_grp.fm33a0xxev_bstim.h.2_g$0000_A3CHw2qJcga_300000__ARM_grp.fm33a0xxev_adc.h.2_Yh2000_DMQIo6NAW82_300000__ARM_grp.fm33a0xxev_aes.h.2_4p5000_ig0fpeqfTIb_l00000__ARM_grp.system_FM33A0XXEV.h.2_qK2000_3p2q1l7JLmc_f00000__ARM_grp.FM33A0XXEV.h.2_0U4000_APjZ6EN_n61_800000__ARM_grp.stdio.h.2_od3000_xcoIxO01eC7_p00000__ARM_grp.core_cm0plus.h.2_oo7000_NmZU1Rz5UO8_W00000__ARM_grp.core_cmfunc.h.2_4o1000_5BOwGSyN3D1_z00000__ARM_grp.core_cminstr.h.2_gq1000_Kwrp1OO1xx3_b00000__ARM_grp.stdint.h.2_QG1000_h7K9OtBs0h1_300000.debug_abbrev__ARM_asm.debug_abbrev.1.debug_macinfo.debug_loc.data.bss.revsh_text.rev16_textLib$$Request$$armliblcd_init_newlcd_initdelay_ms_printf_x_printf_widthprec_printf_pre_padding_printf_percent_printf_longlong_hex_printf_flags__2printfRTC_GPIO_InitLCD_sleepTimeLCD_TYPE_FLAGLCD_IIC_StopLCD_IIC_StartLCD_IIC_Send_ByteLCD_IIC_Read_ByteLCD_IIC_NAckLCD_IIC_AckLCD_DisplayAll_New1LCD_DisplayAll__ARM_grp..debug_pubnames$system_FM33A0XXEV.h$.2_qK2000_3p2q1l7JLmc_f00000__ARM_grp..debug_pubnames$stdio.h$.2_od3000_xcoIxO01eC7_p00000__ARM_grp..debug_pubnames$para.h$.2_Ez8000_khDVHof8zWa_t40000__ARM_grp..debug_pubnames$menu.h$.2_7N2000_pwE5LTwnxO3_J00000__ARM_grp..debug_pubnames$linked_list.h$.2_0$6000_T$gveB7RZS9_Z50000__ARM_grp..debug_pubnames$lcd_io_api.h$.2_h33000_shag9T72CS0_f00000__ARM_grp..debug_pubnames$lcd.h$.2_VE7000_sZu_e6bBIC9_$50000__ARM_grp..debug_pubnames$key.h$.2_cV7000_B55fAyLVs59_p00000__ARM_grp..debug_pubnames$administrator.h$.2_El7000_yWsVCV8hKR8_P50000__ARM_grp..debug_pubnames$1lcd_new.h$.2_X$9000_NQCZJ0R2jX0_l00000__ARM_grp..debug_pubnames$1lcd.h$.2_Bj6000_0DpFEv$qZsf_f00000__ARM_grp..debug_macinfo$user_init.h$.2_ot0000_jZWuqvPHwt6_300000__ARM_grp..debug_macinfo$system_FM33A0XXEV.h$.2_qK2000_3p2q1l7JLmc_f00000__ARM_grp..debug_macinfo$string.h$.2_kw0000_aP4aobzpRT7_300000__ARM_grp..debug_macinfo$stdio.h$.2_od3000_xcoIxO01eC7_p00000__ARM_grp..debug_macinfo$stdint.h$.2_QG1000_h7K9OtBs0h1_300000__ARM_grp..debug_macinfo$stdbool.h$.2_ou0000_sX0KWuH_8w2_300000__ARM_grp..debug_macinfo$para.h$.2_Ez8000_khDVHof8zWa_t40000__ARM_grp..debug_macinfo$menu.h$.2_7N2000_pwE5LTwnxO3_J00000__ARM_grp..debug_macinfo$main.h$.2_ga1000_6c0asbwEXV7_300000__ARM_grp..debug_macinfo$linked_list.h$.2_0$6000_T$gveB7RZS9_Z50000__ARM_grp..debug_macinfo$lcd_segmentcode.h$.2_EN2000_3d2rxbsK$Td_300000__ARM_grp..debug_macinfo$lcd_io_api.h$.2_h33000_shag9T72CS0_f00000__ARM_grp..debug_macinfo$lcd_iic.h$.2_Mw0000_q4tdBSyVENe_300000__ARM_grp..debug_macinfo$lcd.h$.2_VE7000_sZu_e6bBIC9_$50000__ARM_grp..debug_macinfo$key.h$.2_cV7000_B55fAyLVs59_p00000__ARM_grp..debug_macinfo$fm33a0xxev_wwdt.h$.2_4H0000_TVah5VHd$Wd_300000__ARM_grp..debug_macinfo$fm33a0xxev_vrtc.h$.2_YK1000_bGKK6ktMN$f_300000__ARM_grp..debug_macinfo$fm33a0xxev_uart.h$.2_s_5000_gGxJA_bT3g3_r00000__ARM_grp..debug_macinfo$fm33a0xxev_u7816.h$.2_sD5000_T7w3HnfvCn7_w00000__ARM_grp..debug_macinfo$fm33a0xxev_svd.h$.2_YX4000_B$e1cGixg00_i00000__ARM_grp..debug_macinfo$fm33a0xxev_spi.h$.2_AU2000_7eFMvsSXzw0_300000__ARM_grp..debug_macinfo$fm33a0xxev_rtc.h$.2_sS3000_IylpavQ6INd_g00000__ARM_grp..debug_macinfo$fm33a0xxev_rng.h$.2_IJ0000_vzTWbGvNuZe_300000__ARM_grp..debug_macinfo$fm33a0xxev_rmu.h$.2_4L2000_C$q$9vNhOp0_300000__ARM_grp..debug_macinfo$fm33a0xxev_qspi.h$.2_Qr4000_J7HoI7y0B84_g00000__ARM_grp..debug_macinfo$fm33a0xxev_pmu.h$.2_Af5000_lOjh94cQJQf_g00000__ARM_grp..debug_macinfo$fm33a0xxev_pae.h$.2_sJ3000_RoohqLgJd45_300000__ARM_grp..debug_macinfo$fm33a0xxev_lpuart.h$.2_oE2000_Ig0fu_ljcn3_300000__ARM_grp..debug_macinfo$fm33a0xxev_lptim.h$.2_8q4000_BFHTRuxu1ie_300000__ARM_grp..debug_macinfo$fm33a0xxev_lcd.h$.2_Y$4000_kUmWRnNV3_4_300000__ARM_grp..debug_macinfo$fm33a0xxev_iwdt.h$.2_4L0000_LcDBel0usy8_300000__ARM_grp..debug_macinfo$fm33a0xxev_include_all.h$.2_UQ0000_xxdaGLUj6Cf_300000__ARM_grp..debug_macinfo$fm33a0xxev_i2c.h$.2_IS1000_g4ErNZQBGwd_300000__ARM_grp..debug_macinfo$fm33a0xxev_hash.h$.2_kO0000_KuZ300H4_80_300000__ARM_grp..debug_macinfo$fm33a0xxev_gpio.h$.2_815000_upDQZZvAzia_700000__ARM_grp..debug_macinfo$fm33a0xxev_flash.h$.2_0_1000_TO3GMzQCtL1_300000__ARM_grp..debug_macinfo$fm33a0xxev_et.h$.2_4h3000_57B3Rgey0je_300000__ARM_grp..debug_macinfo$fm33a0xxev_dma.h$.2_ks8000_OrTMHX6QIe0_p00000__ARM_grp..debug_macinfo$fm33a0xxev_dbg.h$.2_4f1000_pVDK34opiR1_300000__ARM_grp..debug_macinfo$fm33a0xxev_crc.h$.2_8C4000_La7VPM3Tip8_k00000__ARM_grp..debug_macinfo$fm33a0xxev_comp.h$.2_k_2000_e5VaGx8gTre_300000__ARM_grp..debug_macinfo$fm33a0xxev_cmu.h$.2_Ekb000_qHj10Bv8MJ6_v00000__ARM_grp..debug_macinfo$fm33a0xxev_cdif.h$.2_kJ0000_JQTXKb9R3mc_300000__ARM_grp..debug_macinfo$fm33a0xxev_bt.h$.2_kV3000_MyPILKKQ6H1_300000__ARM_grp..debug_macinfo$fm33a0xxev_bstim.h$.2_g$0000_A3CHw2qJcga_300000__ARM_grp..debug_macinfo$fm33a0xxev_aes.h$.2_4p5000_ig0fpeqfTIb_l00000__ARM_grp..debug_macinfo$fm33a0xxev_adc.h$.2_Yh2000_DMQIo6NAW82_300000__ARM_grp..debug_macinfo$ex_rtc.h$.2_Qi1000_JeDdoy8l9Z9_j00000__ARM_grp..debug_macinfo$ex_rtc.c$.2_wi1000_Cop_GpkcCsb_800000__ARM_grp..debug_macinfo$devicegpioinit.h$.2_0w4000_64Z46PStLCa_300000__ARM_grp..debug_macinfo$delay.h$.2_EE0000_7GGSWSTJWL4_300000__ARM_grp..debug_macinfo$define_all.h$.2_kN0000_fD9tyG24Hn2_300000__ARM_grp..debug_macinfo$core_cminstr.h$.2_gq1000_Kwrp1OO1xx3_b00000__ARM_grp..debug_macinfo$core_cmfunc.h$.2_4o1000_5BOwGSyN3D1_z00000__ARM_grp..debug_macinfo$core_cm0plus.h$.2_oo7000_NmZU1Rz5UO8_W00000__ARM_grp..debug_macinfo$bintohex.h$.2_Y33000_duI5XZW3h40_300000__ARM_grp..debug_macinfo$administrator.h$.2_El7000_yWsVCV8hKR8_P50000__ARM_grp..debug_macinfo$FM33A0XXEV.h$.2_0U4000_APjZ6EN_n61_800000__ARM_grp..debug_macinfo$1lcd_new.h$.2_X$9000_NQCZJ0R2jX0_l00000__ARM_grp..debug_macinfo$1lcd.h$.2_Bj6000_0DpFEv$qZsf_f00000__ARM_grp..debug_macinfo$1ADC.h$.2_Qp1000_8FudzCBNeP8_900000__ARM_grp..debug_line$user_init.h$.2_ot0000_jZWuqvPHwt6_300000__ARM_grp..debug_line$system_FM33A0XXEV.h$.2_qK2000_3p2q1l7JLmc_f00000__ARM_grp..debug_line$string.h$.2_kw0000_aP4aobzpRT7_300000__ARM_grp..debug_line$stdio.h$.2_od3000_xcoIxO01eC7_p00000__ARM_grp..debug_line$stdint.h$.2_QG1000_h7K9OtBs0h1_300000__ARM_grp..debug_line$stdbool.h$.2_ou0000_sX0KWuH_8w2_300000__ARM_grp..debug_line$para.h$.2_Ez8000_khDVHof8zWa_t40000__ARM_grp..debug_line$menu.h$.2_7N2000_pwE5LTwnxO3_J00000__ARM_grp..debug_line$main.h$.2_ga1000_6c0asbwEXV7_300000__ARM_grp..debug_line$linked_list.h$.2_0$6000_T$gveB7RZS9_Z50000__ARM_grp..debug_line$lcd_segmentcode.h$.2_EN2000_3d2rxbsK$Td_300000__ARM_grp..debug_line$lcd_io_api.h$.2_h33000_shag9T72CS0_f00000__ARM_grp..debug_line$lcd_iic.h$.2_Mw0000_q4tdBSyVENe_300000__ARM_grp..debug_line$lcd.h$.2_VE7000_sZu_e6bBIC9_$50000__ARM_grp..debug_line$key.h$.2_cV7000_B55fAyLVs59_p00000__ARM_grp..debug_line$fm33a0xxev_wwdt.h$.2_4H0000_TVah5VHd$Wd_300000__ARM_grp..debug_line$fm33a0xxev_vrtc.h$.2_YK1000_bGKK6ktMN$f_300000__ARM_grp..debug_line$fm33a0xxev_uart.h$.2_s_5000_gGxJA_bT3g3_r00000__ARM_grp..debug_line$fm33a0xxev_u7816.h$.2_sD5000_T7w3HnfvCn7_w00000__ARM_grp..debug_line$fm33a0xxev_svd.h$.2_YX4000_B$e1cGixg00_i00000__ARM_grp..debug_line$fm33a0xxev_spi.h$.2_AU2000_7eFMvsSXzw0_300000__ARM_grp..debug_line$fm33a0xxev_rtc.h$.2_sS3000_IylpavQ6INd_g00000__ARM_grp..debug_line$fm33a0xxev_rng.h$.2_IJ0000_vzTWbGvNuZe_300000__ARM_grp..debug_line$fm33a0xxev_rmu.h$.2_4L2000_C$q$9vNhOp0_300000__ARM_grp..debug_line$fm33a0xxev_qspi.h$.2_Qr4000_J7HoI7y0B84_g00000__ARM_grp..debug_line$fm33a0xxev_pmu.h$.2_Af5000_lOjh94cQJQf_g00000__ARM_grp..debug_line$fm33a0xxev_pae.h$.2_sJ3000_RoohqLgJd45_300000__ARM_grp..debug_line$fm33a0xxev_lpuart.h$.2_oE2000_Ig0fu_ljcn3_300000__ARM_grp..debug_line$fm33a0xxev_lptim.h$.2_8q4000_BFHTRuxu1ie_300000__ARM_grp..debug_line$fm33a0xxev_lcd.h$.2_Y$4000_kUmWRnNV3_4_300000__ARM_grp..debug_line$fm33a0xxev_iwdt.h$.2_4L0000_LcDBel0usy8_300000__ARM_grp..debug_line$fm33a0xxev_include_all.h$.2_UQ0000_xxdaGLUj6Cf_300000__ARM_grp..debug_line$fm33a0xxev_i2c.h$.2_IS1000_g4ErNZQBGwd_300000__ARM_grp..debug_line$fm33a0xxev_hash.h$.2_kO0000_KuZ300H4_80_300000__ARM_grp..debug_line$fm33a0xxev_gpio.h$.2_815000_upDQZZvAzia_700000__ARM_grp..debug_line$fm33a0xxev_flash.h$.2_0_1000_TO3GMzQCtL1_300000__ARM_grp..debug_line$fm33a0xxev_et.h$.2_4h3000_57B3Rgey0je_300000__ARM_grp..debug_line$fm33a0xxev_dma.h$.2_ks8000_OrTMHX6QIe0_p00000__ARM_grp..debug_line$fm33a0xxev_dbg.h$.2_4f1000_pVDK34opiR1_300000__ARM_grp..debug_line$fm33a0xxev_crc.h$.2_8C4000_La7VPM3Tip8_k00000__ARM_grp..debug_line$fm33a0xxev_comp.h$.2_k_2000_e5VaGx8gTre_300000__ARM_grp..debug_line$fm33a0xxev_cmu.h$.2_Ekb000_qHj10Bv8MJ6_v00000__ARM_grp..debug_line$fm33a0xxev_cdif.h$.2_kJ0000_JQTXKb9R3mc_300000__ARM_grp..debug_line$fm33a0xxev_bt.h$.2_kV3000_MyPILKKQ6H1_300000__ARM_grp..debug_line$fm33a0xxev_bstim.h$.2_g$0000_A3CHw2qJcga_300000__ARM_grp..debug_line$fm33a0xxev_aes.h$.2_4p5000_ig0fpeqfTIb_l00000__ARM_grp..debug_line$fm33a0xxev_adc.h$.2_Yh2000_DMQIo6NAW82_300000__ARM_grp..debug_line$ex_rtc.h$.2_Qi1000_JeDdoy8l9Z9_j00000__ARM_grp..debug_line$ex_rtc.c$.2_wi1000_Cop_GpkcCsb_800000__ARM_grp..debug_line$devicegpioinit.h$.2_0w4000_64Z46PStLCa_300000__ARM_grp..debug_line$delay.h$.2_EE0000_7GGSWSTJWL4_300000__ARM_grp..debug_line$define_all.h$.2_kN0000_fD9tyG24Hn2_300000__ARM_grp..debug_line$core_cminstr.h$.2_gq1000_Kwrp1OO1xx3_b00000__ARM_grp..debug_line$core_cmfunc.h$.2_4o1000_5BOwGSyN3D1_z00000__ARM_grp..debug_line$core_cm0plus.h$.2_oo7000_NmZU1Rz5UO8_W00000__ARM_grp..debug_line$bintohex.h$.2_Y33000_duI5XZW3h40_300000__ARM_grp..debug_line$administrator.h$.2_El7000_yWsVCV8hKR8_P50000__ARM_grp..debug_line$FM33A0XXEV.h$.2_0U4000_APjZ6EN_n61_800000__ARM_grp..debug_line$1lcd_new.h$.2_X$9000_NQCZJ0R2jX0_l00000__ARM_grp..debug_line$1lcd.h$.2_Bj6000_0DpFEv$qZsf_f00000__ARM_grp..debug_line$1ADC.h$.2_Qp1000_8FudzCBNeP8_900000__ARM_grp.user_init.h.2_ot0000_jZWuqvPHwt6_300000__ARM_grp.system_FM33A0XXEV.h.2_qK2000_3p2q1l7JLmc_f00000__ARM_grp.string.h.2_kw0000_aP4aobzpRT7_300000__ARM_grp.stdio.h.2_od3000_xcoIxO01eC7_p00000__ARM_grp.stdint.h.2_QG1000_h7K9OtBs0h1_300000__ARM_grp.stdbool.h.2_ou0000_sX0KWuH_8w2_300000__ARM_grp.para.h.2_Ez8000_khDVHof8zWa_t40000__ARM_grp.menu.h.2_7N2000_pwE5LTwnxO3_J00000__ARM_grp.main.h.2_ga1000_6c0asbwEXV7_300000__ARM_grp.linked_list.h.2_0$6000_T$gveB7RZS9_Z50000__ARM_grp.lcd_segmentcode.h.2_EN2000_3d2rxbsK$Td_300000__ARM_grp.lcd_io_api.h.2_h33000_shag9T72CS0_f00000__ARM_grp.lcd_iic.h.2_Mw0000_q4tdBSyVENe_300000__ARM_grp.lcd.h.2_VE7000_sZu_e6bBIC9_$50000__ARM_grp.key.h.2_cV7000_B55fAyLVs59_p00000__ARM_grp.fm33a0xxev_wwdt.h.2_4H0000_TVah5VHd$Wd_300000__ARM_grp.fm33a0xxev_vrtc.h.2_YK1000_bGKK6ktMN$f_300000__ARM_grp.fm33a0xxev_uart.h.2_s_5000_gGxJA_bT3g3_r00000__ARM_grp.fm33a0xxev_u7816.h.2_sD5000_T7w3HnfvCn7_w00000__ARM_grp.fm33a0xxev_svd.h.2_YX4000_B$e1cGixg00_i00000__ARM_grp.fm33a0xxev_spi.h.2_AU2000_7eFMvsSXzw0_300000__ARM_grp.fm33a0xxev_rtc.h.2_sS3000_IylpavQ6INd_g00000__ARM_grp.fm33a0xxev_rng.h.2_IJ0000_vzTWbGvNuZe_300000__ARM_grp.fm33a0xxev_rmu.h.2_4L2000_C$q$9vNhOp0_300000__ARM_grp.fm33a0xxev_qspi.h.2_Qr4000_J7HoI7y0B84_g00000__ARM_grp.fm33a0xxev_pmu.h.2_Af5000_lOjh94cQJQf_g00000__ARM_grp.fm33a0xxev_pae.h.2_sJ3000_RoohqLgJd45_300000__ARM_grp.fm33a0xxev_lpuart.h.2_oE2000_Ig0fu_ljcn3_300000__ARM_grp.fm33a0xxev_lptim.h.2_8q4000_BFHTRuxu1ie_300000__ARM_grp.fm33a0xxev_lcd.h.2_Y$4000_kUmWRnNV3_4_300000__ARM_grp.fm33a0xxev_iwdt.h.2_4L0000_LcDBel0usy8_300000__ARM_grp.fm33a0xxev_include_all.h.2_UQ0000_xxdaGLUj6Cf_300000__ARM_grp.fm33a0xxev_i2c.h.2_IS1000_g4ErNZQBGwd_300000__ARM_grp.fm33a0xxev_hash.h.2_kO0000_KuZ300H4_80_300000__ARM_grp.fm33a0xxev_gpio.h.2_815000_upDQZZvAzia_700000__ARM_grp.fm33a0xxev_flash.h.2_0_1000_TO3GMzQCtL1_300000__ARM_grp.fm33a0xxev_et.h.2_4h3000_57B3Rgey0je_300000__ARM_grp.fm33a0xxev_dma.h.2_ks8000_OrTMHX6QIe0_p00000__ARM_grp.fm33a0xxev_dbg.h.2_4f1000_pVDK34opiR1_300000__ARM_grp.fm33a0xxev_crc.h.2_8C4000_La7VPM3Tip8_k00000__ARM_grp.fm33a0xxev_comp.h.2_k_2000_e5VaGx8gTre_300000__ARM_grp.fm33a0xxev_cmu.h.2_Ekb000_qHj10Bv8MJ6_v00000__ARM_grp.fm33a0xxev_cdif.h.2_kJ0000_JQTXKb9R3mc_300000__ARM_grp.fm33a0xxev_bt.h.2_kV3000_MyPILKKQ6H1_300000__ARM_grp.fm33a0xxev_bstim.h.2_g$0000_A3CHw2qJcga_300000__ARM_grp.fm33a0xxev_aes.h.2_4p5000_ig0fpeqfTIb_l00000__ARM_grp.fm33a0xxev_adc.h.2_Yh2000_DMQIo6NAW82_300000__ARM_grp.ex_rtc.h.2_Qi1000_JeDdoy8l9Z9_j00000__ARM_grp.ex_rtc.c.2_wi1000_Cop_GpkcCsb_800000__ARM_grp.devicegpioinit.h.2_0w4000_64Z46PStLCa_300000__ARM_grp.delay.h.2_EE0000_7GGSWSTJWL4_300000__ARM_grp.define_all.h.2_kN0000_fD9tyG24Hn2_300000__ARM_grp.core_cminstr.h.2_gq1000_Kwrp1OO1xx3_b00000__ARM_grp.core_cmfunc.h.2_4o1000_5BOwGSyN3D1_z00000__ARM_grp.core_cm0plus.h.2_oo7000_NmZU1Rz5UO8_W00000__ARM_grp.bintohex.h.2_Y33000_duI5XZW3h40_300000__ARM_grp.administrator.h.2_El7000_yWsVCV8hKR8_P50000__ARM_grp.FM33A0XXEV.h.2_0U4000_APjZ6EN_n61_800000__ARM_grp.1lcd_new.h.2_X$9000_NQCZJ0R2jX0_l00000__ARM_grp.1lcd.h.2_Bj6000_0DpFEv$qZsf_f00000__ARM_grp.1ADC.h.2_Qp1000_8FudzCBNeP8_900000__ARM_grp..debug_info$user_init.h$.2_ot0000_jZWuqvPHwt6_300000__ARM_grp..debug_info$system_FM33A0XXEV.h$.2_qK2000_3p2q1l7JLmc_f00000__ARM_grp..debug_info$string.h$.2_kw0000_aP4aobzpRT7_300000__ARM_grp..debug_info$stdio.h$.2_od3000_xcoIxO01eC7_p00000__ARM_grp..debug_info$stdint.h$.2_QG1000_h7K9OtBs0h1_300000__ARM_grp..debug_info$stdbool.h$.2_ou0000_sX0KWuH_8w2_300000__ARM_grp..debug_info$para.h$.2_Ez8000_khDVHof8zWa_t40000__ARM_grp..debug_info$menu.h$.2_7N2000_pwE5LTwnxO3_J00000__ARM_grp..debug_info$main.h$.2_ga1000_6c0asbwEXV7_300000__ARM_grp..debug_info$linked_list.h$.2_0$6000_T$gveB7RZS9_Z50000__ARM_grp..debug_info$lcd_segmentcode.h$.2_EN2000_3d2rxbsK$Td_300000__ARM_grp..debug_info$lcd_io_api.h$.2_h33000_shag9T72CS0_f00000__ARM_grp..debug_info$lcd_iic.h$.2_Mw0000_q4tdBSyVENe_300000__ARM_grp..debug_info$lcd.h$.2_VE7000_sZu_e6bBIC9_$50000__ARM_grp..debug_info$key.h$.2_cV7000_B55fAyLVs59_p00000__ARM_grp..debug_info$fm33a0xxev_wwdt.h$.2_4H0000_TVah5VHd$Wd_300000__ARM_grp..debug_info$fm33a0xxev_vrtc.h$.2_YK1000_bGKK6ktMN$f_300000__ARM_grp..debug_info$fm33a0xxev_uart.h$.2_s_5000_gGxJA_bT3g3_r00000__ARM_grp..debug_info$fm33a0xxev_u7816.h$.2_sD5000_T7w3HnfvCn7_w00000__ARM_grp..debug_info$fm33a0xxev_svd.h$.2_YX4000_B$e1cGixg00_i00000__ARM_grp..debug_info$fm33a0xxev_spi.h$.2_AU2000_7eFMvsSXzw0_300000__ARM_grp..debug_info$fm33a0xxev_rtc.h$.2_sS3000_IylpavQ6INd_g00000__ARM_grp..debug_info$fm33a0xxev_rng.h$.2_IJ0000_vzTWbGvNuZe_300000__ARM_grp..debug_info$fm33a0xxev_rmu.h$.2_4L2000_C$q$9vNhOp0_300000__ARM_grp..debug_info$fm33a0xxev_qspi.h$.2_Qr4000_J7HoI7y0B84_g00000__ARM_grp..debug_info$fm33a0xxev_pmu.h$.2_Af5000_lOjh94cQJQf_g00000__ARM_grp..debug_info$fm33a0xxev_pae.h$.2_sJ3000_RoohqLgJd45_300000__ARM_grp..debug_info$fm33a0xxev_lpuart.h$.2_oE2000_Ig0fu_ljcn3_300000__ARM_grp..debug_info$fm33a0xxev_lptim.h$.2_8q4000_BFHTRuxu1ie_300000__ARM_grp..debug_info$fm33a0xxev_lcd.h$.2_Y$4000_kUmWRnNV3_4_300000__ARM_grp..debug_info$fm33a0xxev_iwdt.h$.2_4L0000_LcDBel0usy8_300000__ARM_grp..debug_info$fm33a0xxev_include_all.h$.2_UQ0000_xxdaGLUj6Cf_300000__ARM_grp..debug_info$fm33a0xxev_i2c.h$.2_IS1000_g4ErNZQBGwd_300000__ARM_grp..debug_info$fm33a0xxev_hash.h$.2_kO0000_KuZ300H4_80_300000__ARM_grp..debug_info$fm33a0xxev_gpio.h$.2_815000_upDQZZvAzia_700000__ARM_grp..debug_info$fm33a0xxev_flash.h$.2_0_1000_TO3GMzQCtL1_300000__ARM_grp..debug_info$fm33a0xxev_et.h$.2_4h3000_57B3Rgey0je_300000__ARM_grp..debug_info$fm33a0xxev_dma.h$.2_ks8000_OrTMHX6QIe0_p00000__ARM_grp..debug_info$fm33a0xxev_dbg.h$.2_4f1000_pVDK34opiR1_300000__ARM_grp..debug_info$fm33a0xxev_crc.h$.2_8C4000_La7VPM3Tip8_k00000__ARM_grp..debug_info$fm33a0xxev_comp.h$.2_k_2000_e5VaGx8gTre_300000__ARM_grp..debug_info$fm33a0xxev_cmu.h$.2_Ekb000_qHj10Bv8MJ6_v00000__ARM_grp..debug_info$fm33a0xxev_cdif.h$.2_kJ0000_JQTXKb9R3mc_300000__ARM_grp..debug_info$fm33a0xxev_bt.h$.2_kV3000_MyPILKKQ6H1_300000__ARM_grp..debug_info$fm33a0xxev_bstim.h$.2_g$0000_A3CHw2qJcga_300000__ARM_grp..debug_info$fm33a0xxev_aes.h$.2_4p5000_ig0fpeqfTIb_l00000__ARM_grp..debug_info$fm33a0xxev_adc.h$.2_Yh2000_DMQIo6NAW82_300000__ARM_grp..debug_info$ex_rtc.h$.2_Qi1000_JeDdoy8l9Z9_j00000__ARM_grp..debug_info$ex_rtc.c$.2_wi1000_Cop_GpkcCsb_800000__ARM_grp..debug_info$devicegpioinit.h$.2_0w4000_64Z46PStLCa_300000__ARM_grp..debug_info$delay.h$.2_EE0000_7GGSWSTJWL4_300000__ARM_grp..debug_info$define_all.h$.2_kN0000_fD9tyG24Hn2_300000__ARM_grp..debug_info$core_cminstr.h$.2_gq1000_Kwrp1OO1xx3_b00000__ARM_grp..debug_info$core_cmfunc.h$.2_4o1000_5BOwGSyN3D1_z00000__ARM_grp..debug_info$core_cm0plus.h$.2_oo7000_NmZU1Rz5UO8_W00000__ARM_grp..debug_info$bintohex.h$.2_Y33000_duI5XZW3h40_300000__ARM_grp..debug_info$administrator.h$.2_El7000_yWsVCV8hKR8_P50000__ARM_grp..debug_info$FM33A0XXEV.h$.2_0U4000_APjZ6EN_n61_800000__ARM_grp..debug_info$1lcd_new.h$.2_X$9000_NQCZJ0R2jX0_l00000__ARM_grp..debug_info$1lcd.h$.2_Bj6000_0DpFEv$qZsf_f00000__ARM_grp..debug_info$1ADC.h$.2_Qp1000_8FudzCBNeP8_900000__ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000RTC_Setting_FlagRTC_corNext_Sample_MNext_Sample_HNext_Sample_DNext_real_Sample_MNext_real_Sample_HNext_real_Sample_DLast_Sample_MLast_Sample_HLast_Sample_DLast_Send_MLast_Send_HLast_Send_DSending_flagnet_now_timecalendarI2C_RECV_DATA__asm___8_ex_rtc_c_b7bc8562____REVSH__asm___8_ex_rtc_c_b7bc8562____REV16__ARM_asm.debug_abbrev.1__ARM_grp_.debug_pubnames$45__ARM_grp_.debug_pubnames$38__ARM_grp_.debug_pubnames$31__ARM_grp_.debug_pubnames$24__ARM_grp_.debug_pubnames$17__ARM_grp_.debug_pubnames$10__ARM_grp_.debug_macinfo$4__ARM_grp_.debug_loc$47__ARM_grp_.debug_loc$40__ARM_grp_.debug_loc$33__ARM_grp_.debug_loc$26__ARM_grp_.debug_loc$19__ARM_grp_.debug_line$43__ARM_grp_.debug_line$36__ARM_grp_.debug_line$29__ARM_grp_.debug_line$22__ARM_grp_.debug_line$15__ARM_grp_.debug_line$1__ARM_grp_.debug_info$44__ARM_grp_.debug_info$37__ARM_grp_.debug_info$30__ARM_grp_.debug_info$23__ARM_grp_.debug_info$16__ARM_grp_.debug_info$9__ARM_grp_.debug_info$2__ARM_grp_.debug_frame$48__ARM_grp_.debug_frame$41__ARM_grp_.debug_frame$34__ARM_grp_.debug_frame$27__ARM_grp_.debug_frame$20.data.bssi.set_RTC8025T_peroid_alarmi.Time_Seti.R8025T_writei.R8025T_readBuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$~SHL$OSPACE$EBA8$REQ8$PRES8$EABIv2i.Get_TimeBuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$~SHL$OSPACE$EBA8$PRES8$EABIv2..\Pre_Drivers\ex_rtc.c.revsh_text.rev16_text..\\Pre_Drivers\\ex_rtc.c$d.realdata$d$tAMaeabiCortex-M0        C2.09ARM


4û 8À<ð®,J›v0Œ¨0lØtö Lð L\iðLYT\­ðLT;ñD;5D;yL;ÅL;    P;a    D;¥    H\í    ¼\©


˜\A \Y\q\\Íà\­Lµ<Lñ”L…€LÜLáLq å |å |å     ìå õ å 8Ö M4'U'Ö"'ø#' ': 'Y 0½ Œ 3G¯ ”  € ´ 3ÒÖ Ä œL`)P\°)8K è,3¢Ö ø,œL”.D\Ø. à/3¡Ö ð/L0D\L0„âÐ33 Ö à3<LM˜\´M´´hT3ÓÖ |THLÄVP\W¸'ÌXp<Y3Ö LYØL$kl\k°G@ƒ3ÕÖ TƒxL̄”\`…à'@†&h†3©Ö x†$Lœ’d\“xÙx”3¨Ö ˆ”¨L0£d\”£À T¤3ªÖ d¤PL´¨d\©ÄhÜ©3®Ö ì©4L ¾d\„¾À1D¿3¿Ö T¿LL Ñd\ÒÀú


ÄÒ3¯Ö ÔÒÐL¤Ød\ÙdÃ


lÚ3¹Ö |Úh$Läþd\HÿÀŒ


3±Ö $L($d\Œ$pT


ü&3´Ö 'HLTDd\¸D(


àG3¶Ö ðG@L0Sd\”SÀå    TT3¸Ö dTLL°Vd\WÀ«    ÔW3»Ö äWtLXid\¼iÄr    €j3³Ö j(L¸vd\wÄ;    àw3½Ö ðwLƒd\pƒ(    ˜„3­Ö ¨„Ø:L€¿d\ä¿ôÍØÂ3ÁÖ è¬L”×d\ø×´–¬Ù3°Ö ¼ÙLLàd\làÀ_,á3ÂÖ <á|L¸ôd\õÀ(Üõ3ÀÖ ìõ Lød\pøÀï0ù3ÄÖ @ù  Làd\D·\    3ÅÖ l    ìLXx\Ð~è3ºÖ ø¬L¤<d\=ÄFÌ=3ÇÖ Ü=ÌL¨?d\@ÀÌ@3ÃÖ Ü@˜LtId\ØIHØ K3¼Ö 0KLHed\¬eÀ lf3µÖ |f´L0id\”iÀhTj3¾Ö djTL¸ƒd\„¼2؅3«Ö è…˜L€¡`\à¡Àü ¢3²Ö °¢L@¹`\ ¹ÀÄ`º3ÆÖ pºH


L¸Äd\ÅÀŒÜÅ3¬Ö ìÅLÈd\dÈÀM$É3·Ö 4ɘLÌÉÐ\œÌÄ`Í3ÔÖ p͈LøÍ\\TΨíüÎ3ŸÖ ÏL$ä8\\为å3£Ö $å|L æ\¬ç ˆLé3ÖÖ \éLxé\\ÔéÄZ˜ê3¤Ö ¨êpLì`\xìä+\í3§Ö líLL¸íX\î¤ô´ï3¥Ö ÄïX L`\|ìÇh3šÖ xpLèT\<$š`3ÐÖ t,L &`\'':ÔnÜ;3ÈÖ ð;XLH=T\œ=Ô'p>(8˜>3žÖ ¬>P    LüGh\dHü'`b¸c3ÍÖ ,cLLxch\àc<'e4×Pe3ÎÖ `eØL8kD\|k´Ÿ0l3ÌÖ @lLH~\\¤~ül €3ËÖ ´€°Ldƒp\ԃà'´…!@؅3ÉÖ ì…L솜\ˆ‡ø'€Œ}3œÖ L(L`µt\Ôµø'̶;â·3›Ö ·ÜLøËP\HÌØ' Í!µDÍ3ÏÖ XÍÌL$ÎT\xΈ'ÑG…HÑ3ÑÖ XÑdL¼ÑP\ÒŒU˜Ò3ÊÖ ¨Ò`LÓˆ\Ó¼&LÔ3¦Ö \Ô$L€Ô¤\$ÕHìlÖ3\¯ tÖ¤ÜÜÓÜË〟G¼    œúX3ª    ôúP3—    Dû(3ˆ    lû 3h    ŒûX3X    äû03


H    ü3X    ü03H    Lü3 7    Tü37    dü37    tü37    „ü37    ”ü37    ¤ü37    ´ü3X    Äü3X    Üü(3X    þp3X    tþp3X    äþ°3X    ”ÿ83X    Ìÿ@3H    3H    3H    3H    $3 H    ,3!#    43(#    <3)#    D3*#    L3+#    T3,#    \3-X    d33X    |@37X    ¼3;X    ¼3?X    L 3C#    l3DX    t(3HX    œ 3L#    ¼3MX    Äh3QX    ,3UX    D3YX    \3]X    t3aX    Œ`3eX    ì3iX    ˆ3mX    Œ 3qX    ¬3uX    Ä3yX    Ü3}X    ô3X    @3…X    L¸3‰X    h3X    l3‘X    „3•X    œ3™X    ´À3X    t˜3¡X        3¥X    $    3©X    <    P3­X    Œ    3±X    ¤    3µX    ¼    h3¹X    $


3½X    <


3ÁX    T


3ÅX    l


3ÉX    „


3ÍX    œ


3ÑX    ´


3ÕX    Ì


3ÙX    ä


3ÝX    ü


3áX    €3åX    ”3éX    ¬03íX    Ü(3ñ#    3òX     3ö#    ,3÷X    4°3û#    ä3üX    ì(3#    3X    3X    43    X    L 3 #    l3X    t03#    ¤3X    ¬83#    ä3X    ì 3#    3X    ˜3!#    ¬3"X    ´3&X    Ì3*X    ä(3.&qFplg