/**
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******************************************************************************
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* @file fm33a0xxev_spi.c
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* @author FM33A0XXEV Application Team
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* @version V1.0.0
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* @date 16-April-2020
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* @brief This file provides firmware functions to manage the following
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* functionalities of....:
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*
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "fm33a0xxev_spi.h"
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#include "fm33a0xxev_rmu.h"
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/** @addtogroup fm33a0xxev_StdPeriph_Driver
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* @{
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*/
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/** @defgroup SPI
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* @brief SPI driver modules
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* @{
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*/
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/* MOSIºÍMISOÒý½Å½»»» (IO swapping)
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0£ºÄ¬ÈÏÒý½Å˳Ðò
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1£º½»»»Òý½Å˳Ðò Ïà¹Øº¯Êý */
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void SPIx_CR1_IOSWAP_Set(SPI_Type* SPIx, uint32_t SetValue)
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{
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uint32_t tmpreg;
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tmpreg = SPIx->CR1 ;
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tmpreg &= ~(SPIx_CR1_IOSWAP_Msk);
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tmpreg |= (SetValue & SPIx_CR1_IOSWAP_Msk);
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SPIx->CR1 = tmpreg;
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}
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uint32_t SPIx_CR1_IOSWAP_Get(SPI_Type* SPIx)
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{
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return (SPIx->CR1 & SPIx_CR1_IOSWAP_Msk);
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}
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/* Master Sampling Position Adjustment£¬Master¶ÔMISOÐźŵIJÉÑùλÖõ÷Õû£¬ÓÃÓÚ¸ßËÙͨÐÅʱ²¹³¥PCB×ßÏßÑÓ³Ù
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1£º²ÉÑùµãÑÓ³Ù°ë¸öSCKÖÜÆÚ
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0£º²»µ÷Õû Ïà¹Øº¯Êý */
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void SPIx_CR1_MSPA_Set(SPI_Type* SPIx, uint32_t SetValue)
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{
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uint32_t tmpreg;
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tmpreg = SPIx->CR1 ;
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tmpreg &= ~(SPIx_CR1_MSPA_Msk);
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tmpreg |= (SetValue & SPIx_CR1_MSPA_Msk);
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SPIx->CR1 = tmpreg;
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}
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uint32_t SPIx_CR1_MSPA_Get(SPI_Type* SPIx)
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{
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return (SPIx->CR1 & SPIx_CR1_MSPA_Msk);
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}
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/* Slave Sending Position Adjustment£¬Slave MISO·¢ËÍλÖõ÷Õû
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1£ºÌáÇ°°ë¸öSCKÖÜÆÚ·¢ËÍ
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0£º²»µ÷Õû Ïà¹Øº¯Êý */
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void SPIx_CR1_SSPA_Set(SPI_Type* SPIx, uint32_t SetValue)
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{
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uint32_t tmpreg;
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tmpreg = SPIx->CR1 ;
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tmpreg &= ~(SPIx_CR1_SSPA_Msk);
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tmpreg |= (SetValue & SPIx_CR1_SSPA_Msk);
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SPIx->CR1 = tmpreg;
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}
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uint32_t SPIx_CR1_SSPA_Get(SPI_Type* SPIx)
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{
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return (SPIx->CR1 & SPIx_CR1_SSPA_Msk);
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}
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/* Master/SlaveģʽѡÔñ¡£(Master Mode) 1£ºMasterģʽ 0£ºSlaveģʽ Ïà¹Øº¯Êý */
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void SPIx_CR1_MM_Set(SPI_Type* SPIx, uint32_t SetValue)
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{
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uint32_t tmpreg;
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tmpreg = SPIx->CR1 ;
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tmpreg &= ~(SPIx_CR1_MM_Msk);
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tmpreg |= (SetValue & SPIx_CR1_MM_Msk);
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SPIx->CR1 = tmpreg;
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}
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uint32_t SPIx_CR1_MM_Get(SPI_Type* SPIx)
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{
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return (SPIx->CR1 & SPIx_CR1_MM_Msk);
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}
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/* MasterģʽÏ£¬Ã¿·¢ËÍÍêÒ»Ö¡ºó¼ÓÈëÖÁÉÙ(1+WAIT)¸öSCK cycleµÈ´ýʱ¼ä£¬ÔÙ´«ÊäÏÂÒ»Ö¡µÄÊý¾Ý¡£Èç¹ûSSNÓÉÓ²¼þ¿ØÖÆ£¬²¢ÇÒSSNM=1£¬ÔòÓ²¼þ»á×Ô¶¯À¸ßSSN¡£ Ïà¹Øº¯Êý */
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void SPIx_CR1_WAIT_Set(SPI_Type* SPIx, uint32_t SetValue)
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{
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uint32_t tmpreg;
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tmpreg = SPIx->CR1 ;
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tmpreg &= ~(SPIx_CR1_WAIT_Msk);
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tmpreg |= (SetValue & SPIx_CR1_WAIT_Msk);
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SPIx->CR1 = tmpreg;
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}
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uint32_t SPIx_CR1_WAIT_Get(SPI_Type* SPIx)
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{
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return (SPIx->CR1 & SPIx_CR1_WAIT_Msk);
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}
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/* Masterģʽ²¨ÌØÂÊÅäÖÃλ: (Baud rate) 000£º fAPBCLK/2 001£º fAPBCLK/4 010£º fAPBCLK/8 011£º fAPBCLK/16 100£º fAPBCLK/32 101£º fAPBCLK/64 110£º fAPBCLK/128 111£º fAPBCLK/256 µ±Í¨ÐÅÕýÔÚ½øÐеÄʱºò£¬²»ÄÜÐÞ¸ÄÕâЩλ¡£ Ïà¹Øº¯Êý */
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void SPIx_CR1_BAUD_Set(SPI_Type* SPIx, uint32_t SetValue)
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{
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uint32_t tmpreg;
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tmpreg = SPIx->CR1 ;
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tmpreg &= ~(SPIx_CR1_BAUD_Msk);
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tmpreg |= (SetValue & SPIx_CR1_BAUD_Msk);
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SPIx->CR1 = tmpreg;
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}
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uint32_t SPIx_CR1_BAUD_Get(SPI_Type* SPIx)
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{
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return (SPIx->CR1 & SPIx_CR1_BAUD_Msk);
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}
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/* Ö¡¸ñʽ (LSB First) 0£ºÏÈ·¢ËÍMSB 1£ºÏÈ·¢ËÍLSB ×¢£ºµ±Í¨ÐÅÔÚ½øÐÐʱ²»Äܸıä¸ÃλµÄÖµ¡£ Ïà¹Øº¯Êý */
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void SPIx_CR1_LSBF_Set(SPI_Type* SPIx, uint32_t SetValue)
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{
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uint32_t tmpreg;
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tmpreg = SPIx->CR1 ;
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tmpreg &= ~(SPIx_CR1_LSBF_Msk);
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tmpreg |= (SetValue & SPIx_CR1_LSBF_Msk);
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SPIx->CR1 = tmpreg;
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}
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uint32_t SPIx_CR1_LSBF_Get(SPI_Type* SPIx)
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{
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return (SPIx->CR1 & SPIx_CR1_LSBF_Msk);
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}
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void SPIx_CR1_CPHOL_Set(SPI_Type* SPIx, uint32_t SetValue)
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{
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uint32_t tmpreg;
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tmpreg = SPIx->CR1 ;
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tmpreg &= ~(SPIx_CR1_CPHOL_Msk);
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tmpreg |= (SetValue & SPIx_CR1_CPHOL_Msk);
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SPIx->CR1 = tmpreg;
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}
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uint32_t SPIx_CR1_CPHOL_Get(SPI_Type* SPIx)
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{
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return (SPIx->CR1 & SPIx_CR1_CPHOL_Msk);
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}
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/* ʱÖÓÏàλѡÔñ (Clock Phase) 1£ºµÚ¶þ¸öʱÖÓ±ßÑØÊǵÚÒ»¸ö²¶×½±ßÑØ 0£ºµÚÒ»¸öʱÖÓ±ßÑØÊǵÚÒ»¸ö²¶×½±ßÑØ ×¢£ºµ±Í¨ÐÅÔÚ½øÐÐʱ²»Äܸıä¸ÃλµÄÖµ¡£ Ïà¹Øº¯Êý */
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void SPIx_CR1_CPHA_Set(SPI_Type* SPIx, uint32_t SetValue)
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{
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uint32_t tmpreg;
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tmpreg = SPIx->CR1 ;
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tmpreg &= ~(SPIx_CR1_CPHA_Msk);
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tmpreg |= (SetValue & SPIx_CR1_CPHA_Msk);
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SPIx->CR1 = tmpreg;
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}
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uint32_t SPIx_CR1_CPHA_Get(SPI_Type* SPIx)
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{
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return (SPIx->CR1 & SPIx_CR1_CPHA_Msk);
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}
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/* 4Ïß°ëË«¹¤ÐÒéÏÂÊÇ·ñÔÚ¶Á²Ù×÷ÖвåÈëdummy cycle
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(Dummy cycle Enable)
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0£º²»²åÈëdummy cycle
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1£ºÔÚ¶ÁÃüÁîÖ®ºó²åÈëÒ»¸ödummy cycle Ïà¹Øº¯Êý */
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void SPIx_CR2_DUMMY_EN_Setable(SPI_Type* SPIx, FunState NewState)
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{
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if (NewState == ENABLE)
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{
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SPIx->CR2 |= (SPIx_CR2_DUMMY_EN_Msk);
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}
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else
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{
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SPIx->CR2 &= ~(SPIx_CR2_DUMMY_EN_Msk);
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}
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}
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FunState SPIx_CR2_DUMMY_EN_Getable(SPI_Type* SPIx)
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{
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if (SPIx->CR2 & (SPIx_CR2_DUMMY_EN_Msk))
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{
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return ENABLE;
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}
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else
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{
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return DISABLE;
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}
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}
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/* RXONLY¿ØÖÆ룬´Ë¼Ä´æÆ÷ÖÃλʱ£¬SPI¿ÉÒÔÁ¬Ðø½ÓÊÕ£¬ÎÞÐèÈí¼þдTXBUF (Receive Only mode)
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1£ºÆô¶¯MasterµÄµ¥½ÓÊÕģʽ
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0£º¹Ø±Õµ¥½ÓÊÕģʽ£¨ÊÕ·¢È«Ë«¹¤£© Ïà¹Øº¯Êý */
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void SPIx_CR2_RXO_Setable(SPI_Type* SPIx, FunState NewState)
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{
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if (NewState == ENABLE)
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{
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SPIx->CR2 |= (SPIx_CR2_RXO_Msk);
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}
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else
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{
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SPIx->CR2 &= ~(SPIx_CR2_RXO_Msk);
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}
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}
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FunState SPIx_CR2_RXO_Getable(SPI_Type* SPIx)
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{
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if (SPIx->CR2 & (SPIx_CR2_RXO_Msk))
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{
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return ENABLE;
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}
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else
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{
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return DISABLE;
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}
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}
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/* ͨÐÅÊý¾Ý×Ö³¤ÅäÖà (Data Length)
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00£º8bit
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01£º16bit
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10£º24bit
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11£º32bit Ïà¹Øº¯Êý */
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void SPIx_CR2_DLEN_Set(SPI_Type* SPIx, uint32_t SetValue)
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{
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uint32_t tmpreg;
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tmpreg = SPIx->CR2 ;
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tmpreg &= ~(SPIx_CR2_DLEN_Msk);
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tmpreg |= (SetValue & SPIx_CR2_DLEN_Msk);
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SPIx->CR2 = tmpreg;
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}
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uint32_t SPIx_CR2_DLEN_Get(SPI_Type* SPIx)
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{
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return (SPIx->CR2 & SPIx_CR2_DLEN_Msk);
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}
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/* ͨÐÅģʽѡÔñ (Half-Duplex mode)
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0£º±ê×¼SPIģʽ£¬4ÏßÈ«Ë«¹¤
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1£ºDCNģʽ£¬4Ïß°ëË«¹¤ Ïà¹Øº¯Êý */
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void SPIx_CR2_HALFDUPLEX_Set(SPI_Type* SPIx, uint32_t SetValue)
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{
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uint32_t tmpreg;
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tmpreg = SPIx->CR2 ;
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tmpreg &= ~(SPIx_CR2_HALFDUPLEX_Msk);
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tmpreg |= (SetValue & SPIx_CR2_HALFDUPLEX_Msk);
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SPIx->CR2 = tmpreg;
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}
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uint32_t SPIx_CR2_HALFDUPLEX_Get(SPI_Type* SPIx)
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{
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return (SPIx->CR2 & SPIx_CR2_HALFDUPLEX_Msk);
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}
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/* °ëË«¹¤Ä£Ê½ÏÂÖ÷»ú¶Áд²Ù×÷ÅäÖà (Read/Write config for Half-Duplex mode)
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0£º4Ïß°ëË«¹¤ÐÒéÏÂÖ÷»úдÈë´Ó»ú
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1£º4Ïß°ëË«¹¤ÐÒéÏÂÖ÷»ú¶ÁÈ¡´Ó»ú Ïà¹Øº¯Êý */
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void SPIx_CR2_HD_RW_Set(SPI_Type* SPIx, uint32_t SetValue)
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{
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uint32_t tmpreg;
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tmpreg = SPIx->CR2 ;
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tmpreg &= ~(SPIx_CR2_HD_RW_Msk);
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tmpreg |= (SetValue & SPIx_CR2_HD_RW_Msk);
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SPIx->CR2 = tmpreg;
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}
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uint32_t SPIx_CR2_HD_RW_Get(SPI_Type* SPIx)
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{
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return (SPIx->CR2 & SPIx_CR2_HD_RW_Msk);
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}
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/* °ëË«¹¤Ä£Ê½Ï¶¨ÒåcommandÖ¡³¤¶È (Command 8 bits)
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1£ºcommandÖ¡¹Ì¶¨Îª8bit
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0£ºcommandÖ¡³¤¶ÈÓÉDLEN¶¨Òå Ïà¹Øº¯Êý */
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void SPIx_CR2_CMD8b_Set(SPI_Type* SPIx, uint32_t SetValue)
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{
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uint32_t tmpreg;
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tmpreg = SPIx->CR2 ;
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tmpreg &= ~(SPIx_CR2_CMD8b_Msk);
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tmpreg |= (SetValue & SPIx_CR2_CMD8b_Msk);
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SPIx->CR2 = tmpreg;
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}
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uint32_t SPIx_CR2_CMD8b_Get(SPI_Type* SPIx)
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{
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return (SPIx->CR2 & SPIx_CR2_CMD8b_Msk);
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}
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/* MasterģʽÏÂSSN¿ØÖÆģʽѡÔñ (SSN mode)
|
1£ºÃ¿·¢ËÍÍêÒ»Ö¡ºóMasterÀ¸ßSSN£¬Î¬³Ö¸ßµçƽʱ¼äÓÉWAIT¼Ä´æÆ÷¿ØÖÆ
|
0£ºÃ¿·¢ËÍÍêÒ»Ö¡ºóMaster±£³ÖSSNΪµÍ Ïà¹Øº¯Êý */
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void SPIx_CR2_SSNM_Set(SPI_Type* SPIx, uint32_t SetValue)
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{
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uint32_t tmpreg;
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tmpreg = SPIx->CR2 ;
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tmpreg &= ~(SPIx_CR2_SSNM_Msk);
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tmpreg |= (SetValue & SPIx_CR2_SSNM_Msk);
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SPIx->CR2 = tmpreg;
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}
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uint32_t SPIx_CR2_SSNM_Get(SPI_Type* SPIx)
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{
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return (SPIx->CR2 & SPIx_CR2_SSNM_Msk);
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}
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/* TXONLYÓ²¼þ×Ô¶¯Çå¿ÕµÄʹÄÜ (TXONLY auto-clear enable) 1£ºTXONLYÓ²¼þ×Ô¶¯ÇåÁãÓÐЧ£¬Èí¼þʹÄÜTXOºó£¬µÈ´ý·¢ËÍÍê±Ïºó£¬Ó²¼þÇåÁã 0£º¹Ø±ÕTXONLYÓ²¼þ×Ô¶¯ÇåÁã Ïà¹Øº¯Êý */
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void SPIx_CR2_TXO_AC_Setable(SPI_Type* SPIx, FunState NewState)
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{
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if (NewState == ENABLE)
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{
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SPIx->CR2 |= (SPIx_CR2_TXO_AC_Msk);
|
}
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else
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{
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SPIx->CR2 &= ~(SPIx_CR2_TXO_AC_Msk);
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}
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}
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FunState SPIx_CR2_TXO_AC_Getable(SPI_Type* SPIx)
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{
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if (SPIx->CR2 & (SPIx_CR2_TXO_AC_Msk))
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{
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return ENABLE;
|
}
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else
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{
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return DISABLE;
|
}
|
}
|
|
/* TXONLY¿ØÖÆλ (Transmit Only mode enable)
|
1£ºÆô¶¯MasterµÄµ¥·¢ËÍģʽ
|
0£º¹Ø±Õµ¥·¢ËÍģʽ£¨ÊÕ·¢È«Ë«¹¤£© Ïà¹Øº¯Êý */
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void SPIx_CR2_TXO_Setable(SPI_Type* SPIx, FunState NewState)
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{
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if (NewState == ENABLE)
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{
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SPIx->CR2 |= (SPIx_CR2_TXO_Msk);
|
}
|
else
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{
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SPIx->CR2 &= ~(SPIx_CR2_TXO_Msk);
|
}
|
}
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|
FunState SPIx_CR2_TXO_Getable(SPI_Type* SPIx)
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{
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if (SPIx->CR2 & (SPIx_CR2_TXO_Msk))
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{
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return ENABLE;
|
}
|
else
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{
|
return DISABLE;
|
}
|
}
|
|
/* MasterģʽÏ£¬Èç¹ûSSNSENΪ1£¬Èí¼þ¿ÉÒÔͨ¹ý´Ëλ¿ØÖÆSSNÊä³öµçƽ 1£ºSSNÊä³ö¸ßµçƽ
|
0£ºSSNÊä³öµÍµçƽ Ïà¹Øº¯Êý */
|
void SPIx_CR2_SSN_Set(SPI_Type* SPIx, uint32_t SetValue)
|
{
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uint32_t tmpreg;
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tmpreg = SPIx->CR2 ;
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tmpreg &= ~(SPIx_CR2_SSN_Msk);
|
tmpreg |= (SetValue & SPIx_CR2_SSN_Msk);
|
SPIx->CR2 = tmpreg;
|
}
|
|
uint32_t SPIx_CR2_SSN_Get(SPI_Type* SPIx)
|
{
|
return (SPIx->CR2 & SPIx_CR2_SSN_Msk);
|
}
|
|
/* MasterģʽÏ£¬Èí¼þ¿ØÖÆSSNʹÄÜ (SSN Software Enable)
|
1£ºMasterģʽÏÂSSNÊä³öÓÉÈí¼þ¿ØÖÆ
|
0£ºMasterģʽÏÂSSNÊä³öÓÉÓ²¼þ×Ô¶¯¿ØÖÆ Ïà¹Øº¯Êý */
|
void SPIx_CR2_SSNSEN_Setable(SPI_Type* SPIx, FunState NewState)
|
{
|
if (NewState == ENABLE)
|
{
|
SPIx->CR2 |= (SPIx_CR2_SSNSEN_Msk);
|
}
|
else
|
{
|
SPIx->CR2 &= ~(SPIx_CR2_SSNSEN_Msk);
|
}
|
}
|
|
FunState SPIx_CR2_SSNSEN_Getable(SPI_Type* SPIx)
|
{
|
if (SPIx->CR2 & (SPIx_CR2_SSNSEN_Msk))
|
{
|
return ENABLE;
|
}
|
else
|
{
|
return DISABLE;
|
}
|
}
|
|
/* SPIʹÄÜ (SPI enable) 1£ºÊ¹ÄÜSPI 0£º¹Ø±ÕSPI£¬Çå¿Õ·¢ËͽÓÊÕ»º´æ Ïà¹Øº¯Êý */
|
void SPIx_CR2_SPIEN_Setable(SPI_Type* SPIx, FunState NewState)
|
{
|
if (NewState == ENABLE)
|
{
|
SPIx->CR2 |= (SPIx_CR2_SPIEN_Msk);
|
}
|
else
|
{
|
SPIx->CR2 &= ~(SPIx_CR2_SPIEN_Msk);
|
}
|
}
|
|
FunState SPIx_CR2_SPIEN_Getable(SPI_Type* SPIx)
|
{
|
if (SPIx->CR2 & (SPIx_CR2_SPIEN_Msk))
|
{
|
return ENABLE;
|
}
|
else
|
{
|
return DISABLE;
|
}
|
}
|
|
/* Transmit Buffer Clear£¬Èí¼þд1Çå³ý·¢ËÍ»º´æ£¬Ð´0ÎÞЧ Ïà¹Øº¯Êý */
|
void SPIx_CR3_TXBFC_Clr(SPI_Type* SPIx)
|
{
|
SPIx->CR3 = SPIx_CR3_TXBFC_Msk;
|
}
|
|
/* Receive Buffer Clear£¬Èí¼þд1Çå³ý·¢ËÍ»º´æ£¬Ð´0ÎÞЧ Ïà¹Øº¯Êý */
|
void SPIx_CR3_RXBFC_Clr(SPI_Type* SPIx)
|
{
|
SPIx->CR3 = SPIx_CR3_RXBFC_Msk;
|
}
|
|
/* Master Error Clear£¬Èí¼þд1Çå³ýHSPISTA.MERR¼Ä´æÆ÷ Ïà¹Øº¯Êý */
|
void SPIx_CR3_MERRC_Clr(SPI_Type* SPIx)
|
{
|
SPIx->CR3 = SPIx_CR3_MERRC_Msk;
|
}
|
|
/* Slave Error Clear£¬Èí¼þд1Çå³ýHSPISTA.SERR¼Ä´æÆ÷ Ïà¹Øº¯Êý */
|
void SPIx_CR3_SERRC_Clr(SPI_Type* SPIx)
|
{
|
SPIx->CR3 = SPIx_CR3_SERRC_Msk;
|
}
|
|
/* SPI´íÎóÖжÏʹÄÜ (Error Interrupt Enable) Ïà¹Øº¯Êý */
|
void SPIx_IER_ERRIE_Setable(SPI_Type* SPIx, FunState NewState)
|
{
|
if (NewState == ENABLE)
|
{
|
SPIx->IER |= (SPIx_IER_ERRIE_Msk);
|
}
|
else
|
{
|
SPIx->IER &= ~(SPIx_IER_ERRIE_Msk);
|
}
|
}
|
|
FunState SPIx_IER_ERRIE_Getable(SPI_Type* SPIx)
|
{
|
if (SPIx->IER & (SPIx_IER_ERRIE_Msk))
|
{
|
return ENABLE;
|
}
|
else
|
{
|
return DISABLE;
|
}
|
}
|
|
/* ·¢ËÍÍê³ÉÖжÏʹÄÜ (Transmit Interrupt Enable) Ïà¹Øº¯Êý */
|
void SPIx_IER_TXIE_Setable(SPI_Type* SPIx, FunState NewState)
|
{
|
if (NewState == ENABLE)
|
{
|
SPIx->IER |= (SPIx_IER_TXIE_Msk);
|
}
|
else
|
{
|
SPIx->IER &= ~(SPIx_IER_TXIE_Msk);
|
}
|
}
|
|
FunState SPIx_IER_TXIE_Getable(SPI_Type* SPIx)
|
{
|
if (SPIx->IER & (SPIx_IER_TXIE_Msk))
|
{
|
return ENABLE;
|
}
|
else
|
{
|
return DISABLE;
|
}
|
}
|
|
/* ½ÓÊÕÍê³ÉÖжÏʹÄÜ (Receive Interrupt Enable) Ïà¹Øº¯Êý */
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void SPIx_IER_RXIE_Setable(SPI_Type* SPIx, FunState NewState)
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{
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if (NewState == ENABLE)
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{
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SPIx->IER |= (SPIx_IER_RXIE_Msk);
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}
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else
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{
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SPIx->IER &= ~(SPIx_IER_RXIE_Msk);
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}
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}
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FunState SPIx_IER_RXIE_Getable(SPI_Type* SPIx)
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{
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if (SPIx->IER & (SPIx_IER_RXIE_Msk))
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{
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return ENABLE;
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}
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else
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{
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return DISABLE;
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}
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}
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/* °ëË«¹¤Ä£Ê½Ï£¨HALFDUPLEX=1£©£¬ÅäÖÃÔÚÿ¸öÊý¾ÝÖ¡µÄ×îºóbit·¢Ë͵ÄDCNÐźŵçƽ (Data/Command transmit config)
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0£ºDCN=0£¬±íʾÃüÁîÖ¡
|
1£ºDCN=1£¬±íʾÊý¾ÝÖ¡
|
Èí¼þÓ¦ÔÚ·¢ËÍÇ°ÉèÖÃDCN_TX¼Ä´æÆ÷£¬Èç¹ûDCN_TX=0£¬Ó²¼þÔÚÍê³ÉÒ»Ö¡·¢Ëͺó£¬×Ô¶¯½«DCN_TXÖÃ1£¬¼´Ä¬ÈÏÖ»»á·¢ËÍÒ»¸öÃüÁîÖ¡£¬ºóÐø¶¼ÊÇÊý¾ÝÖ¡¡£ Ïà¹Øº¯Êý */
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void SPIx_ISR_DCN_TX_Set(SPI_Type* SPIx, uint32_t SetValue)
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{
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uint32_t tmpreg;
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tmpreg = SPIx->ISR ;
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tmpreg &= ~(SPIx_ISR_DCN_TX_Msk);
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tmpreg |= (SetValue & SPIx_ISR_DCN_TX_Msk);
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SPIx->ISR = tmpreg;
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}
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uint32_t SPIx_ISR_DCN_TX_Get(SPI_Type* SPIx)
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{
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return (SPIx->ISR & SPIx_ISR_DCN_TX_Msk);
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}
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/* ½ÓÊÕ»º´æÒç³ö£¬Èí¼þд1ÇåÁã (Receive Collision flag,write 1 to flag) Ïà¹Øº¯Êý */
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void SPIx_ISR_RXCOL_Clr(SPI_Type* SPIx)
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{
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SPIx->ISR = SPIx_ISR_RXCOL_Msk;
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}
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FlagStatus SPIx_ISR_RXCOL_Chk(SPI_Type* SPIx)
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{
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if (SPIx->ISR & SPIx_ISR_RXCOL_Msk)
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{
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return SET;
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}
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else
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{
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return RESET;
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}
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}
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/* ·¢ËÍ»º´æÒç³ö£¬Èí¼þд1ÇåÁã (Transmit Collision flag,write 1 to clear) Ïà¹Øº¯Êý */
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void SPIx_ISR_TXCOL_Clr(SPI_Type* SPIx)
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{
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SPIx->ISR = SPIx_ISR_TXCOL_Msk;
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}
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FlagStatus SPIx_ISR_TXCOL_Chk(SPI_Type* SPIx)
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{
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if (SPIx->ISR & SPIx_ISR_TXCOL_Msk)
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{
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return SET;
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}
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else
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{
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return RESET;
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}
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}
|
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/* SPI¿ÕÏбêÖ¾£¬Ö»¶Á (busy flag)
|
1£ºSPI´«Êä½øÐÐÖÐ
|
0£ºSPI´«Êä¿ÕÏÐ Ïà¹Øº¯Êý */
|
FlagStatus SPIx_ISR_BUSY_Chk(SPI_Type* SPIx)
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{
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if (SPIx->ISR & SPIx_ISR_BUSY_Msk)
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{
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return SET;
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}
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else
|
{
|
return RESET;
|
}
|
}
|
|
/* Master Error±êÖ¾(Master Error flag)
|
µ±MasterÏ´«ÊäδÂú8λSSN¾Í±»À¸ßʱ£¬MERRÖÃλ Ïà¹Øº¯Êý */
|
FlagStatus SPIx_ISR_MERR_Chk(SPI_Type* SPIx)
|
{
|
if (SPIx->ISR & SPIx_ISR_MERR_Msk)
|
{
|
return SET;
|
}
|
else
|
{
|
return RESET;
|
}
|
}
|
|
/* Slave Error±êÖ¾(Slave Error flag)
|
µ±SlaveÏ´«ÊäδÂú8λSSN¾Í±»À¸ßʱ£¬SERRÖÃλ Ïà¹Øº¯Êý */
|
FlagStatus SPIx_ISR_SERR_Chk(SPI_Type* SPIx)
|
{
|
if (SPIx->ISR & SPIx_ISR_SERR_Msk)
|
{
|
return SET;
|
}
|
else
|
{
|
return RESET;
|
}
|
}
|
|
/* TX Buffer Empty±ê־λ(TX Buffer Empty flag)
|
1£º·¢ËÍ»º´æ¿Õ£¬Èí¼þдTXBUFÇåÁã
|
0£º·¢ËÍ»º´æÂú Ïà¹Øº¯Êý */
|
FlagStatus SPIx_ISR_TXBE_Chk(SPI_Type* SPIx)
|
{
|
if (SPIx->ISR & SPIx_ISR_TXBE_Msk)
|
{
|
return SET;
|
}
|
else
|
{
|
return RESET;
|
}
|
}
|
|
/* RX Buffer Full±ê־λ(RX Buffer Full flag)
|
1£º½ÓÊÕ»º´æÂú£¬Èí¼þ¶ÁRXBUFÇåÁã
|
0£º½ÓÊÕ»º´æ¿Õ Ïà¹Øº¯Êý */
|
FlagStatus SPIx_ISR_RXBF_Chk(SPI_Type* SPIx)
|
{
|
if (SPIx->ISR & SPIx_ISR_RXBF_Msk)
|
{
|
return SET;
|
}
|
else
|
{
|
return RESET;
|
}
|
}
|
|
/* SPI·¢ËÍ»º´æ (Transmit Buffer) Ïà¹Øº¯Êý */
|
void SPIx_TXBUF_Write(SPI_Type* SPIx, uint32_t SetValue)
|
{
|
SPIx->TXBUF = (SetValue);
|
}
|
|
/* SPI½ÓÊÕ»º´æ (Receive Buffer) Ïà¹Øº¯Êý */
|
uint32_t SPIx_RXBUF_Read(SPI_Type* SPIx)
|
{
|
return (SPIx->RXBUF );
|
}
|
|
void SPIx_Deinit(SPI_Type* SPIx)
|
{
|
RMU_PRSTEN_Write(0x13579BDF);
|
if (SPIx == SPI0)
|
{
|
RMU_APBRST2_SPI0RST_Setable(ENABLE);
|
RMU_APBRST2_SPI0RST_Setable(DISABLE);
|
}
|
else if (SPIx == SPI1)
|
{
|
RMU_APBRST2_SPI1RST_Setable(ENABLE);
|
RMU_APBRST2_SPI1RST_Setable(DISABLE);
|
}
|
else if (SPIx == SPI2)
|
{
|
RMU_APBRST1_SPI2RST_Setable(ENABLE);
|
RMU_APBRST1_SPI2RST_Setable(DISABLE);
|
}
|
else if (SPIx == SPI3)
|
{
|
RMU_APBRST1_SPI3RST_Setable(ENABLE);
|
RMU_APBRST1_SPI3RST_Setable(DISABLE);
|
}
|
else if (SPIx == SPI4)
|
{
|
RMU_APBRST1_SPI4RST_Setable(ENABLE);
|
RMU_APBRST1_SPI4RST_Setable(DISABLE);
|
}
|
RMU_PRSTEN_Write(0x00000000);
|
}
|
|
/********************************
|
SPIµÄSSNÉèÖõçƽµÍµÄº¯Êý
|
********************************/
|
void SPI_SSN_Set_Low(SPI_Type* SPIx)//Çý¶¯¼¶
|
{
|
SPIx_CR2_SSN_Set(SPIx, SPIx_CR2_SSN_LOW);//ÀµÍSSNÐźÅ
|
}
|
|
/********************************
|
SPIµÄSSNÉèÖõçƽ¸ßµÄº¯Êý
|
********************************/
|
void SPI_SSN_Set_High(SPI_Type* SPIx)//Çý¶¯¼¶
|
{
|
SPIx_CR2_SSN_Set(SPIx, SPIx_CR2_SSN_HIGH);//À¸ßSSNÐźÅ
|
}
|
|
/********************************
|
SPI·¢ËͲ¢½ÓÊÕÒ»¸ö×ֽڵĺ¯Êý
|
¹¦ÄÜ£ºSPI·¢ËͺͽÓÊÕÒ»¸ö×Ö½Ú
|
ÊäÈ룺SPIÒª·¢Ë͵Ä×Ö½Ú£¬Êä³ö£ºSPI½ÓÊÕ×Ö½Ú
|
********************************/
|
uint8_t SPI_RW_Byte(SPI_Type* SPIx, uint8_t data)//SPI·¢ËͲ¢½ÓÊÕÒ»×Ö½Ú
|
{
|
unsigned char rx_data;
|
uint32_t Temp32;
|
uint32_t i;
|
|
Temp32 = SPIx_CR1_BAUD_Get(SPIx);
|
Temp32 = Temp32>>SPIx_CR1_BAUD_Pos;
|
Temp32 = 0x1U<<(Temp32+1);
|
Temp32 = Temp32*8;
|
|
for(i=0; i<Temp32; i++)
|
{
|
if (SPIx_ISR_TXBE_Chk(SPIx) == SET)
|
{
|
break;
|
}
|
}
|
SPIx_TXBUF_Write(SPIx, data);
|
|
for(i=0; i<Temp32; i++)
|
{
|
if (SPIx_ISR_RXBF_Chk(SPIx) == SET)
|
{
|
break;
|
}
|
}
|
rx_data = SPIx_RXBUF_Read(SPIx);
|
return rx_data;
|
}
|
|
/******END OF FILE****/
|
